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Require Export Iron.Language.SimpleRef.SubstExpExp.
Require Import Iron.Language.SimpleRef.Preservation.
Require Import Iron.Language.SimpleRef.Ty.
Require Export Iron.Language.SimpleRef.Step.
Require Export Iron.Language.SimpleRef.Exp.
(********************************************************************)
(** Big Step Evaluation *)
(* This is also called 'Natural Semantics'.
It provides a relation between the expression to be reduced
and its final value. *)
Inductive EVAL : heap -> exp -> heap -> exp -> Prop :=
| EvDone
: forall h v2
, value v2
-> wfH h
-> EVAL h v2 h v2
| EvLamApp
: forall h0 h1 h2 h3 x1 t11 x12 x2 v2 v3
, EVAL h0 x1 h1 (XLam t11 x12)
-> EVAL h1 x2 h2 v2
-> EVAL h2 (substX 0 v2 x12) h3 v3
-> EVAL h0 (XApp x1 x2) h3 v3
(* Heap operations *)
| EvNewRef
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1 (* evaluate new heap value *)
-> EVAL h0 (XNewRef x1) (* push that value onto the heap *)
(v1 <: h1) (XLoc (length h1))
| EvReadRef
: forall h0 x1 h1 v2 l
, EVAL h0 x1 h1 (XLoc l) (* evaluate heap location *)
-> get l h1 = Some v2 (* lookup up that location from the heap *)
-> EVAL h0 (XReadRef x1)
h1 v2
| EvWriteRef
: forall h0 x1 h1 x2 v2 h2 l
, EVAL h0 x1 h1 (XLoc l) (* evaluate heap location *)
-> EVAL h1 x2 h2 v2 (* evaluate argument to a value *)
-> EVAL h0 (XWriteRef x1 x2)
(update l v2 h2) xUnit. (* update heap with that value*)
Hint Constructors EVAL.
(* Invert all hypothesis that are compound eval statements *)
Ltac inverts_eval :=
repeat
(match goal with
| [ H: EVAL _ (XLoc _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XCon _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XLam _ _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XApp _ _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XNewRef _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XReadRef _) _ _ |- _ ] => inverts H
| [ H: EVAL _ (XWriteRef _ _) _ _ |- _ ] => inverts H
end).
Lemma eval_value_eq
: forall h0 v0 h1 v1
, value v0
-> EVAL h0 v0 h1 v1
-> h1 = h0 /\ v1 = v0.
Proof.
intros.
destruct v0; inverts_eval; nope; eauto.
Qed.
(* A terminating big-step evaluation always produces a wnf,
and preserves the wellformedness of the heap.
The fact that the evaluation terminated is implied by the fact
that we have a finite proof of EVAL to pass to this lemma. *)
Lemma eval_produces_wfH_value
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1
-> wfH h1 /\ value v1.
Proof.
intros. induction H; rip; try burn.
inverts H1; eauto.
eapply Forall_update; eauto.
eapply Forall_update; eauto.
unfold xUnit. auto.
Qed.
(* A terminating big-step evaluation produces a well formed heap. *)
Lemma eval_produces_wfH
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1
-> wfH h1.
Proof.
intros. lets D: eval_produces_wfH_value H. burn.
Qed.
Hint Resolve eval_produces_wfH.
(* A terminating big-step evaluation produces a value. *)
Lemma eval_produces_value
: forall h0 x1 h1 v1
, EVAL h0 x1 h1 v1
-> value v1.
Proof.
intros. lets D: eval_produces_wfH_value H. burn.
Qed.
Hint Resolve eval_produces_value.
(********************************************************************)
(** * Big to Small steps *)
(* Flatten out a big-step evaluation into a list of individual
machine steps.
Proof:
This is tedious but straightforward. We assert each of the
intermediate STEPS to get the intermediate values, then use
preservation to show the results have the same type as before.
Once we've got a STEPS for each of the hyps of the EVAL we're
we're flattening, join them all together with an EsAppend,
stating the contexts we're performing the reductions in.
*)
Lemma steps_of_eval
: forall se h0 h1 x1 t1 x2
, wfH h0 -> TYPEH se h0
-> TYPE nil se x1 t1
-> EVAL h0 x1 h1 x2
-> STEPS h0 x1 h1 x2.
Proof.
intros se h0 h1 x1 t1 v2 HTW HTH HT HE. gen se t1.
(* Induction over the form of (EVAL x1 x2) *)
induction HE; intros.
Case "EvDone".
apply EsNone.
(* Function Application **********)
Case "EvLamApp".
inverts_type.
rename H3 into Tx1.
rename H5 into Tx2.
(* evaluate function *)
have Sx1: (STEPS h0 x1 h1 (XLam t11 x12)).
clear IHHE1.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
inverts keep H2.
(* evaluate arg *)
have (TYPE nil se1 x2 t0).
have Sx2: (STEPS h1 x2 h2 v2).
clear IHHE2.
lets Rx1: preservation_steps se1 h1 x2 t0 h2.
lets Rx1': Rx1 v2.
clear Rx1. rip.
destruct Rx1' as [se2]. rip.
(* perform substitution *)
have (TYPE nil se2 (substX 0 v2 x12) t1)
by burn using subst_exp_exp.
have (STEPS h2 (substX 0 v2 x12) h3 v3).
lets Rx2: preservation_steps se2 h2 (substX 0 v2 x12) t1 h3.
lets Rx2': Rx2 v3.
clear Rx2. rip.
destruct Rx2' as [se3]. rip.
eapply EsAppend.
lets D: steps_context XcApp1.
eapply D. eauto.
eapply EsAppend.
lets D: steps_context XcApp2.
have WL: (wnfX (XLam t0 x12)).
eauto. eapply D. eauto.
eapply EsAppend; eauto.
(* Create a new Reference *******)
Case "EvNewRef".
inverts_type.
rename H2 into Tx1.
(* evaluate argument *)
have Sx1: (STEPS h0 x1 h1 v1).
clear IHHE.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
eapply EsAppend.
lets D: steps_context XcNewRef.
eapply D. eauto.
eapply EsStep. eauto.
(* Read a reference ************)
Case "EvReadRef".
inverts_type.
rename H3 into Tx1.
(* evaluate argument to a location *)
have Sx1: (STEPS h0 x1 h1 (XLoc l)).
clear IHHE.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
eapply EsAppend.
lets D: steps_context XcReadRef.
eapply D. eauto.
eapply EsStep. eauto.
(* Write a reference **********)
Case "EvWriteRef".
inverts_type.
rename H3 into Tx1.
rename H5 into Tx2.
(* evaluate first argument to a location *)
have Sx1: (STEPS h0 x1 h1 (XLoc l)).
clear IHHE1.
lets Rx1: preservation_steps HTH Tx1 Sx1.
destruct Rx1 as [se1]. rip.
(* evaluate second argument to a value *)
have Sx2: (STEPS h1 x2 h2 v2).
clear IHHE2.
have Tx2': (TYPE nil se1 x2 tData).
lets Rx2: preservation_steps H Tx2' Sx2.
destruct Rx2 as [se2]. rip.
eapply EsAppend.
lets D: steps_context XcWriteRef1.
eapply D. eapply Sx1.
eapply EsAppend.
lets D: steps_context XcWriteRef2.
have (value (XLoc l)). eauto.
eapply D. eapply Sx2.
eauto.
Qed.
(********************************************************************)
(** * Small to Big steps *)
(** Convert a list of individual machine steps to a big-step
evaluation. The main part of this is the expansion lemma, which
we use to build up the overall big-step evaluation one small-step
at a time. The other lemmas are used to feed it small-steps.
*)
(* Given an existing big-step evalution, we can produce a new one
that does an extra step before returning the original value.
*)
Lemma eval_expansion
: forall se h1 x1 t1 h2 x2 h3 v3
, wfH h1 -> TYPEH se h1
-> TYPE nil se x1 t1
-> STEP h1 x1 h2 x2 -> EVAL h2 x2 h3 v3
-> EVAL h1 x1 h3 v3.
Proof.
intros se h1 x1 t1 h2 x2 h3 v3 HW HTH HT HS HE.
gen se t1 h3 v3.
(* Induction over the form of (STEP x1 x2) *)
induction HS; intros.
Case "context".
destruct H; eauto; inverts_type.
SCase "XcApp".
inverts_eval. nope. eauto.
inverts_eval. nope.
assert (h1 = h' /\ XLam t11 x12 = v1).
eapply eval_value_eq; eauto. rip.
eapply EvLamApp. eauto. eauto.
eauto.
SCase "XcNewRef".
inverts_eval; burn.
SCase "XcReadRef".
inverts_eval; burn.
SCase "XcWriteRef".
inverts_eval; burn.
inverts_eval. nope.
assert (h1 = h' /\ XLoc l0 = v1).
eapply eval_value_eq; eauto. rip.
eauto.
Case "XApp".
inverts_type.
eapply EvLamApp; eauto.
have (value (XLam t0 x12)). burn.
Case "XNewRef".
assert (h3 = v1 <: h /\ v3 = XLoc (length h)).
eapply eval_value_eq; eauto. burn. rip.
Case "XReadRef".
have (value v).
assert (h3 = h /\ v3 = v).
eapply eval_value_eq; eauto. rip.
eapply EvReadRef; eauto.
eapply EvDone; burn.
Case "XWriteRef".
assert (h3 = update l v2 h /\ v3 = xUnit).
eapply eval_value_eq; eauto.
unfold xUnit; burn.
rip.
eapply EvWriteRef.
eapply EvDone; burn.
inverts HE.
inverts_type.
have (value v2).
assert (exists xData, get l h = Some xData).
eauto using (@Forall2_get_get_right exp).
eauto.
Qed.
(* Convert a list of small steps to a big-step evaluation. *)
Lemma eval_of_stepsl
: forall se h1 x1 t1 h2 v2
, wfH h1 -> TYPEH se h1
-> TYPE nil se x1 t1
-> STEPSL h1 x1 h2 v2 -> value v2
-> EVAL h1 x1 h2 v2.
Proof.
intros. gen se.
induction H2; intros.
Case "EslNone".
apply EvDone; auto.
Case "EslCons".
eapply eval_expansion; eauto.
lets D: preservation H1 H4 H0.
dest D. rip.
have (wfH h2) by burn using step_preserves_wfH.
burn.
Qed.
(* Convert a multi-step evaluation to a big-step evaluation.
We use stepsl_of_steps to flatten out the append constructors
in the multi-step evaluation, leaving a list of individual
small-steps. *)
Lemma eval_of_steps
: forall se h1 x1 t1 h2 v2
, wfH h1 -> TYPEH se h1
-> TYPE nil se x1 t1
-> STEPS h1 x1 h2 v2 -> value v2
-> EVAL h1 x1 h2 v2.
Proof.
intros.
eapply eval_of_stepsl; eauto.
apply stepsl_of_steps; auto.
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_1_V
`define SKY130_FD_SC_HDLL__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_1_V
|
#include <bits/stdc++.h> using namespace std; int cnt[2]; int main() { ios::sync_with_stdio(false); string s; cin >> s; for (int i = s.size() - 1; i >= -1; i--) { if (i > -1) cnt[s[i] - 0 ]++; if (s[i] == 1 && (i == 0 || s[i - 1] == 0 )) { int req = cnt[1] - cnt[0]; for (int j = i; j < s.size() && s[j] == 1 && req > 0; j++) { cnt[0]++; req--; s[j] = 0 ; } } } cout << s << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int N = 122231; int n, k; vector<int> g[N]; int used[N]; int done[150][150][150]; int memo[150][150][150]; vector<int> sons[N]; int max_dep[N]; void dfs(int v) { used[v] = 1; max_dep[v] = 0; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (used[to]) continue; sons[v].push_back(to); dfs(to); max_dep[v] = max(max_dep[v], max_dep[to] + 1); } } int solve(int v, int top1, int covered_pref) { if (done[v][top1][covered_pref]) return memo[v][top1][covered_pref]; done[v][top1][covered_pref] = 1; if (top1 == 100) { memo[v][top1][covered_pref] = (covered_pref > max_dep[v]); return memo[v][top1][covered_pref]; } if (top1 > k && covered_pref == 0) { memo[v][top1][covered_pref] = 0; return 0; } long long ways[2], nways[2]; ways[0] = ways[1] = nways[0] = nways[1] = 0; if (top1 == 0) { ways[1] = 1; } else { ways[0] = 1; } for (int i = 0; i < sons[v].size(); i++) { int to = sons[v][i]; for (int j = 0; j < 2; j++) nways[j] = 0; int new_pref = max(covered_pref - 1, k - top1); if (new_pref < 0) new_pref = 0; for (int dep_there = 0; dep_there <= 100; dep_there++) { int is_ok_dep = 1; if (dep_there + 1 < top1) is_ok_dep = 0; if (dep_there == 100) { if (new_pref <= max_dep[to]) is_ok_dep = 0; } else { int covered2 = dep_there - k; if (covered2 > new_pref) is_ok_dep = 0; } if (is_ok_dep == 0) continue; if (solve(to, dep_there, new_pref) == 0) continue; for (int j = 0; j < 2; j++) { nways[j | ((dep_there + 1) == top1)] = 1ll * nways[j | ((dep_there + 1) == top1)] + 1ll * ways[j] * solve(to, dep_there, new_pref) % 1000000007; nways[j | ((dep_there + 1) == top1)] %= 1000000007; } } for (int j = 0; j < 2; j++) { ways[j] = nways[j]; } } memo[v][top1][covered_pref] = ways[1]; return memo[v][top1][covered_pref]; } int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } int root = 1; dfs(root); int res = 0; for (int i = 0; i <= k; i++) { res += solve(root, i, 0); res %= 1000000007; } cout << res << endl; cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long a, b, x, y, i, k, j, t, n, s; cin >> t; while (t--) { cin >> n >> k; if (n % 2 == 0) { s = n + (k * 2); cout << s << endl; } else { s = (k - 1) * 2; a = 0; for (i = 3; i * i <= n; i += 2) { if (n % i == 0) { a = i; break; } } if (a == 0) a = n; s = a + n + s; cout << s << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int min1, min2, min3, max1, max2, max3; cin >> min1 >> max1 >> min2 >> max2 >> min3 >> max3; int c = n; int ans1 = min1, ans2 = min2, ans3 = min3; for (int i = min1; i < max1; i++) { if (ans1 + ans2 + ans3 == n) break; ans1++; } for (int i = min2; i < max2; i++) { if (ans1 + ans2 + ans3 == n) break; ans2++; } for (int i = min3; i < max3; i++) { if (ans1 + ans2 + ans3 == n) break; ans3++; } cout << ans1 << << ans2 << << ans3; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Register Block Level 2
// File : der_reg_2.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Second level register block
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_reg_2
(
input de_clk, // drawing engine clock input
input de_rstn, // de reset input
input load_actvn, // load active command parameters
input cmdcpyclr, // command copy clear.
input [12:0] buf_ctrl_1, // buffer control register input
input [31:0] sorg_1, // source origin register input
input [31:0] dorg_1, // destination origin register input
input [11:0] sptch_1, // source pitch register input
input [11:0] dptch_1, // destination pitch register input
input [3:0] opc_1, // opcode register input
input [3:0] rop_1, // raster opcode register input
input [4:0] style_1, // drawing style register input
input nlst_1, // drawing pattern style register input
input [1:0] apat_1, // drawing area pattern mode
input [2:0] clp_1, // drawing clip control register input
input [31:0] fore_1, // foreground color register input
input [31:0] back_1, // background color register input
input [3:0] mask_1, // plane mask register input
input [23:0] de_key_1, // Key data
input [15:0] alpha_1, // Alpha Register
input [17:0] acntrl_1, // Alpha Control Register
input [1:0] bc_lvl_1,
output [12:0] buf_ctrl_2, // buffer control register input
output reg [31:0] sorg_2, // source origin register input
output reg [31:0] dorg_2, // destination origin register input
output reg [11:0] sptch_2, // source pitch register input
output reg [11:0] dptch_2, // destination pitch register input
output reg [3:0] rop_2, // raster opcode register input
output reg [4:0] style_2, // drawing style register input
output reg nlst_2, // drawing pattern style register input
output reg [1:0] apat_2, // drawing area pattern mode.
output reg [2:0] clp_2, // drawing clip control register input
output reg [31:0] fore_2, // foreground color register input
output reg [31:0] back_2, // background color register input
output reg [3:0] mask_2, // plane mask register input
output reg [23:0] de_key_2, // Key data
output reg [15:0] alpha_2, // Alpha Register
output reg [17:0] acntrl_2, // Alpha Control Register
output reg [1:0] bc_lvl_2,
output reg [3:0] opc_2
);
reg [12:0] buf_ctrl_r; // buffer control register input
/***************************************************************************/
/* */
/* ASSIGN OUTPUTS TO REGISTERS */
/* */
/***************************************************************************/
assign buf_ctrl_2 = {
buf_ctrl_r[12:4],
(buf_ctrl_r[3] | (buf_ctrl_r[2] & buf_ctrl_r[0])),
buf_ctrl_r[2:0]
};
/***************************************************************************/
/* REGISTER WRITE FUNCTION */
/* BYTE SELECTION ORDER */
/* */
/* | 63-56 | 55-48 | 47-40 | 39-32 | 31-24 | 23-16 | 15-8 | 7-0 | */
/* | wb7n | wb6n | wb5n | wb4n | wb3n | wb2n | wb1n | wb0n| */
/* */
/***************************************************************************/
/* Replicate the foreground and background depending on the bits per pixel.*/
wire [1:0] psize;
reg [31:0] fore_rep;
reg [31:0] back_rep;
assign psize = buf_ctrl_1[8:7];
always @*
casex (psize)
2'b00: begin
// 8 Bpp
fore_rep = {4{fore_1[7:0]}};
back_rep = {4{back_1[7:0]}};
end
2'bx1: begin
// 16 Bpp
fore_rep = {2{fore_1[15:0]}};
back_rep = {2{back_1[15:0]}};
end
default: begin
// 32Bpp
fore_rep = fore_1;
back_rep = back_1;
end
endcase // casex(psize)
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) opc_2 <= 4'b0;
else if(cmdcpyclr) opc_2 <= 4'b0;
else if(!load_actvn) opc_2 <= opc_1;
end
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn) begin
buf_ctrl_r <= 13'b0;
sorg_2 <= 32'b0;
dorg_2 <= 32'b0;
rop_2 <= 4'b0;
style_2 <= 5'b0;
nlst_2 <= 1'b0;
apat_2 <= 2'b0;
clp_2 <= 3'b0;
bc_lvl_2 <= 2'b0;
sptch_2 <= 12'b0;
dptch_2 <= 12'b0;
fore_2 <= 32'b0;
back_2 <= 32'b0;
mask_2 <= 4'b0;
de_key_2 <= 24'b0;
alpha_2 <= 16'b0;
acntrl_2 <= 18'b0;
end else if(!load_actvn) begin
buf_ctrl_r <= buf_ctrl_1;
sorg_2 <= sorg_1;
dorg_2 <= dorg_1;
rop_2 <= rop_1;
style_2 <= style_1;
nlst_2 <= nlst_1;
apat_2 <= apat_1;
clp_2 <= clp_1;
bc_lvl_2 <= bc_lvl_1;
sptch_2 <= sptch_1;
dptch_2 <= dptch_1;
fore_2 <= fore_rep;
back_2 <= back_rep;
mask_2 <= mask_1;
de_key_2 <= de_key_1;
alpha_2 <= alpha_1;
acntrl_2 <= acntrl_1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<vector<int>> moves(2, vector<int>()); for (int i = 0; i < 2; ++i) { int k; cin >> k; for (int j = 0; j < k; ++j) { int m; cin >> m; moves[i].push_back(m); } } queue<std::pair<int, int>> q; q.push({0, 0}); q.push({0, 1}); vector<vector<int>> res(n, vector<int>(2, -1)); res[0][0] = 0; res[0][1] = 0; vector<vector<int>> counter(n, vector<int>(2, 0)); while (!q.empty()) { std::pair<int, int> v = q.front(); q.pop(); int pos = v.first; int player = v.second; if (res[pos][player] == 0) { for (const auto& m : moves[1 ^ player]) { int k = pos - m; if (k < 0) { k += n; } if (res[k][1 ^ player] == -1) { res[k][1 ^ player] = 1; q.push({k, 1 ^ player}); } } } else { for (const auto& m : moves[1 ^ player]) { int k = pos - m; if (k < 0) { k += n; } if (res[k][1 ^ player] == -1) { ++counter[k][1 ^ player]; if (counter[k][1 ^ player] == (int)moves[1 ^ player].size()) { res[k][1 ^ player] = 0; q.push({k, 1 ^ player}); } } } } } for (int i = 0; i < 2; ++i) { for (int j = 1; j < n; ++j) { if (res[j][i] == 0) { cout << Lose ; } else if (res[j][i] == 1) { cout << Win ; } else { cout << Loop ; } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> const long long int INF = (1e9 + 12312), MOD = 1e9 + 7; const long double EPS = 0.0000000001; using namespace std; vector<pair<long long int, long long int> > a; pair<long long int, pair<long long int, long long int> > l(long long int x, long long int y) { long long int x1, x2, y1, y2; x1 = a[x].first; x2 = a[y].first; y1 = a[x].second; y2 = a[y].second; long long int a = y2 - y1; long long int b = x1 - x2; long long int c = x2 * y1 - x1 * y2; return make_pair(a, make_pair(b, c)); } bool can(long long int x, long long int y) { auto ff = l(x, y); long long int a1, b1, c1; a1 = ff.first; b1 = ff.second.first; c1 = ff.second.second; vector<long long int> rer; for (long long int i = 0; i < (long long int)a.size(); i++) { if (a1 * a[i].first + b1 * a[i].second + c1 != 0) { rer.push_back(i); } } if ((long long int)rer.size() < 3) { return 1; } auto f2 = l(rer[0], rer[1]); long long int a2, b2, c2; a2 = f2.first; b2 = f2.second.first; c2 = f2.second.second; for (long long int i = 0; i < (long long int)a.size(); i++) { if (a1 * a[i].first + b1 * a[i].second + c1 != 0) { if (a2 * a[i].first + b2 * a[i].second + c2 != 0) { return 0; } } } return 1; } int main() { long long int n; cin >> n; if (n < 3) { cout << YES n ; return 0; } for (long long int i = 0; i < n; i++) { long long int x, y; cin >> x >> y; a.push_back(make_pair(x, y)); } if (can(0, 1)) { cout << YES n ; return 0; } if (can(1, 2)) { cout << YES n ; return 0; } if (can(0, 2)) { cout << YES n ; return 0; } cout << NO n ; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define ll long long #define ull unsigned long long #define inf INT_MAX #define minf INT_MIN #define infl LLONG_MAX #define minfl LLONG_MIN #define mod 1000000007 /*----------------------Debugger-----------------------------------*/ #ifndef ONLINE_JUDGE #define show(x) cerr<< #x << : ; _print(x); cerr <<endl; #else #define show(x) #endif template<class T> void _print(T x){ cerr<<x<<endl; } template<class T> void _print(vector<T> x){cerr<< [ ; for(auto i: x) cerr<<i<< , ; cerr<< ] n ;} template<class T> void _print(set<T> x){ cerr<< { ; for(auto i: x) cerr<<i<< , ; cerr<< } n ;} /*-------------------------------------------------------------------------------------------------*/ ll exp(int a,int b,int p){ll res=1; a=a%p; while(b){ if(b & 1) res=(res*a)%p; a=((ll)a*a)%p; b=b>>1; } return res; } ll mmiPrime(int a, int p){ return exp(a,p-2,p); } pair<int,int> extendedGCD(int a, int b){ if(b==0){ pair<int,int> ans; ans.first=1; ans.second=0; return ans; } pair<int,int> temp=extendedGCD(b,a%b); pair<int,int> ans; ans.first=temp.second; ans.second=temp.first - (a/b)*temp.second; return ans; } int mmi(int a, int m){ pair<int,int> tmp=extendedGCD(a,m); return tmp.first; } int ncr(int n,int r, int p, int fact[]){ return ((fact[n] * mmiPrime(fact[r],p) % p) * mmiPrime(fact[n-r],p))%p; } /*-------------------------------------------------------------------------------------------------*/ void solve(){ int n,k; cin>>n>>k; int a[k]; int t[k]; for(int i=0;i<k;i++) cin>>a[i]; for(int i=0;i<k;i++) cin>>t[i]; vector<ll> ac(n+1,INT_MAX); for(int i=0;i<k;i++){ ac[a[i]]=t[i]; } ll L[n+1],R[n+1]; ll p=INT_MAX; for(int i=1;i<=n;i++){ p=min(p+1,ac[i]); L[i]=p; } p=INT_MAX; for(int i=n;i>0;i--){ p=min(p+1,ac[i]); R[i]=p; } for(int i=1;i<=n;i++) cout<<min(L[i],R[i])<< ; cout<< n ; } int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); #ifndef ONLINE_JUDGE freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); freopen( error.txt , w ,stderr); #endif clock_t time = clock(); int t; cin>>t; while(t--){ solve(); } time = clock() - time; #ifndef ONLINE_JUDGE cout<< time: <<time*1000/CLOCKS_PER_SEC<< miliseconds n ; #endif return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[150000], b[510000], arr[226660]; int main() { int n, x, k; cin >> n >> k >> x; int cnt = 1; int l = 0; cin >> arr[0]; for (int i = 1; i < n; i++) { cin >> arr[i]; if (arr[i] == arr[i - 1]) { cnt++; } else { a[l] = arr[i - 1]; b[l++] = cnt; cnt = 1; } } a[l] = arr[n - 1]; b[l++] = cnt; int sum = 0; for (int i = 0; i < l; i++) { int ans = 0; if (a[i] == x) { if (b[i] + 1 >= 3) { ans += b[i]; int u = i - 1; int v = i + 1; while (a[u] == a[v] && b[u] + b[v] >= 3 && u >= 0 && v < n) { ans += b[u] + b[v]; u--; v++; } sum = max(sum, ans); } } } printf( %d n , sum); }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> v[1005]; int ma, src; bool vis[1005]; int p[1005]; void dfs(int s, int pa, int d) { p[s] = pa; vis[s] = 1; if (d >= ma) { src = s; ma = d; } for (int i = 0; i < v[s].size(); i++) { int u = v[s][i]; if (u != pa) { dfs(u, s, d + 1); } } } int main() { int u = 0; ios::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } int trees = 0, ans = 0; vector<int> vvv; vector<pair<int, int> > vv; for (int i = 1; i <= n; i++) { if (!vis[i]) { ma = 0; src = i; dfs(i, -1, 0); dfs(src, -1, 0); int node = src; for (int j = 0; j < ma / 2; j++) { node = p[node]; } vv.push_back({ma, node}); trees++; u = max(u, ma); vvv.push_back((ma + 1) / 2); } } sort(vvv.begin(), vvv.end()); sort(vv.rbegin(), vv.rend()); for (int i = vvv.size() - 1; i >= max(0, (int)(vvv.size() - 2)); i--) { ans += vvv[i]; } int mi = 2; if (vvv.size() >= 3) { if (vvv[vvv.size() - 3] < vvv[vvv.size() - 1]) { mi = 1; } } ans += min(trees - 1, mi); ans = max(ans, u); cout << ans << endl; for (int i = 0; i < vv.size() - 1; i++) { cout << vv[0].second << << vv[i + 1].second << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace IO { inline bool read() { return true; } template <class T1, class... T2> bool read(T1 &a, T2 &...rest) { return (cin >> a) ? read(rest...) : 0; } template <class... T> bool read(char *a, T &...rest) { return (cin >> a) ? read(rest...) : 0; } template <class... T> bool read(char *a, char *b, T &...rest) { return (cin >> a >> b) ? read(rest...) : 0; } template <class... T> bool read(char *a, char *b, char *c, T &...rest) { return (cin >> a >> b >> c) ? read(rest...) : 0; } void put() { cout << n ; } template <class T1, class... T2> void put(const T1 num, const T2... rest) { cout << num << ; put(rest...); } void yes() { put( YES ); } void no() { put( NO ); } void ff() { cout.flush(); } } // namespace IO using namespace IO; using db = double; using vi = vector<int>; using pii = pair<int, int>; using ll = long long; using cp = complex<double>; const int mod = 998244353, inv2 = (mod + 1) / 2; const int maxn = 1e3 + 10; const int inf = 1e9 + 3; short d[41][maxn][maxn]; ll n, m, k; void prepare() {} short a[maxn][maxn]; queue<pair<short, short> > q[41]; vector<pair<short, short> > c[41]; short fff = 2e4; short dx[4] = {1, -1, 0, 0}; short dy[4] = {0, 0, 1, -1}; void bfs(int k, short (&d)[maxn][maxn], queue<pair<short, short> > &q) { vi vis(44); vis[k] = 1; while (!q.empty()) { auto x = q.front().first, y = q.front().second; q.pop(); if (!vis[a[x][y]]) for (auto g : c[a[x][y]]) { auto x1 = g.first, y1 = g.second; if (d[x1][y1] == fff) { d[x1][y1] = d[x][y] + 1; q.push(make_pair(x1, y1)); } } vis[a[x][y]] = 1; for (int i = 0; i < 4; i++) { auto xx = x + dx[i], yy = y + dy[i]; if (d[xx][yy] != fff) continue; d[xx][yy] = d[x][y] + 1; q.push(make_pair(xx, yy)); } } } void Solve(int cas = 1) { read(n, m, k); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { for (int q = 1; q <= k; q++) { d[q][i][j] = fff; } read(a[i][j]); c[a[i][j]].emplace_back(i, j); d[a[i][j]][i][j] = 0; q[a[i][j]].push(make_pair(i, j)); } } for (int i = 1; i <= k; i++) { bfs(1, d[i], q[i]); } int q; read(q); while (q--) { short r1, c1, r2, c2; read(r1, c1, r2, c2); int min1 = abs(r1 - r2) + abs(c1 - c2); for (int i = 1; i <= k; i++) { min1 = min(min1, d[i][r1][c1] + 1 + d[i][r2][c2]); } put(min1); } } void Solvem() { int T; read(T); for (int i = 1; i <= T; i++) Solve(i); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); prepare(); Solve(); return 0; }
|
/*TODO:
Test byte masks
Add timeout
Test linear burst from 0xffffffff
Add support for settings address ranges
*/
module wb_master
#(parameter aw = 32,
parameter dw = 32,
parameter VERBOSE = 0,
parameter MAX_BURST_LEN = 500)
(input wb_clk_i,
input wb_rst_i,
output [aw-1:0] wb_adr_o,
output [dw-1:0] wb_dat_o,
output [3:0] wb_sel_o,
output wb_we_o,
output wb_cyc_o,
output wb_stb_o,
output [2:0] wb_cti_o,
output [1:0] wb_bte_o,
input [dw-1:0] wb_dat_i,
input wb_ack_i,
input wb_err_i,
input wb_rty_i);
`include "wb_bfm_params.v"
vlog_functions utils();
integer SEED = 2;
integer TRANSACTIONS;
initial
if(!$value$plusargs("transaction=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
wb_bfm_master
#(.MAX_BURST_LENGTH (MAX_BURST_LEN))
bfm
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wb_adr_o),
.wb_dat_o (wb_dat_o),
.wb_sel_o (wb_sel_o),
.wb_we_o (wb_we_o),
.wb_cyc_o (wb_cyc_o),
.wb_stb_o (wb_stb_o),
.wb_cti_o (wb_cti_o),
.wb_bte_o (wb_bte_o),
.wb_dat_i (wb_dat_i),
.wb_ack_i (wb_ack_i),
.wb_err_i (wb_err_i),
.wb_rty_i (wb_rty_i));
reg [dw*MAX_BURST_LEN-1:0] write_data;
reg [dw*MAX_BURST_LEN-1:0] read_data;
reg [dw*MAX_BURST_LEN-1:0] expected_data;
integer word;
integer burst_length;
reg [2:0] burst_type;
integer transaction;
integer tmp, burst_wrap;
reg err;
reg [aw-1:0] address;
initial begin
for(transaction = 0 ; transaction < TRANSACTIONS; transaction = transaction + 1) begin
tmp = $random;
address = {20'h0000,tmp[11:0]};//FIXME Check address range against memory model
burst_length = ({$random(SEED)} % MAX_BURST_LEN) + 1;
for(word = 0; word < burst_length; word = word + 1)
write_data[dw*word+:dw] = $random;
burst_type = ({$random(SEED)} % 4);
bfm.write_burst(address, write_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
bfm.read_burst(address, read_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
case (burst_type)
LINEAR_BURST : burst_wrap = burst_length;
WRAP_4_BURST : burst_wrap = 4;
WRAP_8_BURST : burst_wrap = 8;
WRAP_16_BURST : burst_wrap = 16;
CONSTANT_BURST : burst_wrap = 1;
default : $error("%d : Illegal burst type (%b)", $time, burst_type);
endcase
tmp = burst_length-1;
for(word = burst_length-1 ; word >= 0 ; word = word - 1) begin
expected_data[dw*word+:dw] = write_data[dw*tmp+:dw];
tmp = tmp - 1;
if(tmp < burst_length - burst_wrap)
tmp = burst_length-1;
end
for(word = 0 ; word < burst_length ; word = word +1)
if(read_data[word*dw+:dw] !== expected_data[word*dw+:dw]) begin
$error("Read data mismatch on address %h (burst length=%0d, burst_type=%0d, iteration %0d)", address, burst_length, burst_type, word);
$error("Expected %h", expected_data[word*dw+:dw]);
$error("Got %h", read_data[word*dw+:dw]);
$finish;
end
if (VERBOSE) $display("Read ok from address %h (burst length=%0d, burst_type=%0d)", address, burst_length, burst_type);
utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end // for (i = 1 ; i < 10; i = i + 1)
$display("%0d : All tests passed!", $time);
#3 $finish;
end
endmodule
|
/* * * Author: Hsueh- * Date: 2021-03-05 21:34:52 * * */ #include <bits/stdc++.h> using namespace std; #define dbg(x...) do { cout << #x << -> ; err(x); } while (0) void err() { cout << endl; } template <class T, class... Ts> void err(const T &arg, const Ts &...args) { cout << arg << ; err(args...); } #define endl n #define all(A) A.begin(), A.end() using ll = long long; using db = double; using pII = pair<int, int>; const int INF = 0x3f3f3f3f; const ll INFLL = 0x3f3f3f3f3f3f3f3f; const int N = 2e5 + 10; int n, m; int a[N]; void RUN() { cin >> n >> m; map<ll, int> mp; ll sum = 0, Max = 0; for (int i = 1; i <= n; ++i) { cin >> a[i]; sum += a[i]; if (sum > Max) { Max = sum; mp[sum] = i; } } for (int i = 1; i <= m; ++i) { ll x; cin >> x; auto it = mp.lower_bound(x); ll res = 0; if (it == mp.end() && sum <= 0) { res = -1; } else if (it == mp.end()) { auto last = mp.end(); last--; ll need = (x - last->first + sum - 1) / sum; it = mp.lower_bound(x - need * sum); res = it->second + need * n - 1; } else { res = it->second - 1; } cout << res << n [i == m]; } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); cout << fixed << setprecision(20); int T; cin >> T; while (T--) { RUN(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, m, x[500010], y[500010], xx[500010], yy[500010], zz[500010]; const long long N = 2e6 + 10; struct link { long long top, fi[N], to[N], la[N], ne[N]; void clear() { top = 0, memset(fi, 0, sizeof fi), memset(la, 0, sizeof la), memset(to, 0, sizeof to), memset(ne, 0, sizeof ne); } void add(long long x, long long y) { top++, to[top] = y; if (fi[x] == 0) fi[x] = top; else ne[la[x]] = top; la[x] = top; } } L; long long fa[N], vis[N], FA[N], dep[N], need[N], cost[N], out; long long find(long long x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } void dfs(long long x) { vis[x] = 1; for (long long i = L.fi[x]; i; i = L.ne[i]) if (L.to[i] != FA[x]) { dep[L.to[i]] = dep[x] + 1; need[L.to[i]] = (i <= (k * 2)); FA[L.to[i]] = x; dfs(L.to[i]); } } signed main() { scanf( %lld%lld%lld , &n, &k, &m); L.clear(); for (long long i = 1; i <= n; i++) fa[i] = i; for (long long i = 1; i <= k; i++) { scanf( %lld%lld , &x[i], &y[i]); long long fx = find(x[i]), fy = find(y[i]); fa[fx] = fy; L.add(x[i], y[i]); L.add(y[i], x[i]); } for (long long i = 1; i <= m; i++) { scanf( %lld%lld%lld , &xx[i], &yy[i], &zz[i]); long long fx = find(xx[i]), fy = find(yy[i]); if (fx != fy) { L.add(xx[i], yy[i]); L.add(yy[i], xx[i]); fa[fx] = fy; } } dfs(1); for (long long i = 1; i <= n; i++) fa[i] = i; for (long long i = 1; i <= m; i++) { long long fx = find(xx[i]), fy = find(yy[i]); while (fx != fy) { if (dep[fx] < dep[fy]) swap(fx, fy); cost[fx] = zz[i]; fa[fx] = FA[fx]; fx = find(fx); } } for (long long i = 1; i <= n; i++) if (need[i]) { if (!cost[i]) { puts( -1 ); return 0; } out += cost[i]; } printf( %lld , out); return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<double, double> get_vec_rotate(pair<double, double> nv, double fi) { return make_pair(nv.first * cos(fi) - nv.second * sin(fi), nv.second * cos(fi) + nv.first * sin(fi)); } pair<double, double> get_normal(pair<double, double> vec) { double len = sqrt(vec.first * vec.first + vec.second * vec.second); vec.first /= len; vec.second /= len; return vec; } pair<double, double> end_p(pair<double, double> start_p, pair<double, double> nv, double len) { nv.first *= len; nv.second *= len; return make_pair(nv.first + start_p.first, nv.second + start_p.second); } double a, b, c, d; pair<double, double> p, v, ToWrite; pair<double, double> len_fi[7]; int main() { cin >> p.first >> p.second >> v.first >> v.second >> a >> b >> c >> d; v = get_normal(v); len_fi[0].first = b; len_fi[0].second = 0; len_fi[1].first = a / 2; len_fi[1].second = M_PI / 2; len_fi[2].first = c / 2; len_fi[2].second = M_PI / 2; len_fi[3].first = sqrt(c * c + 4 * d * d) / 2; len_fi[3].second = M_PI / 2 + atan(2 * d / c); len_fi[4].first = sqrt(c * c + 4 * d * d) / 2; len_fi[4].second = 3 * M_PI / 2 - atan(2 * d / c); len_fi[5].first = c / 2; len_fi[5].second = 3 * M_PI / 2; len_fi[6].first = a / 2; len_fi[6].second = 3 * M_PI / 2; cout.precision(10); for (int i = 0; i < 7; i++) { ToWrite = end_p(p, get_vec_rotate(v, len_fi[i].second), len_fi[i].first); cout << fixed << ToWrite.first << << ToWrite.second << endl; } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sw_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 9: 0] in_port;
input reset_n;
wire clk_en;
wire [ 9: 0] data_in;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0)->sync_with_stdio(0); int n; cin >> n; int sp = -1, rmv = 0, ans = 0; stack<int> st; while (n--) { int t; cin >> t; if (t == 1) { int x; cin >> x; sp = x; } else if (t == 3) { int x; cin >> x; st.push(x); } else if (t == 2) { ans += rmv; rmv = 0; } else if (t == 4) { rmv = 0; } else if (t == 5) { while (st.size()) st.pop(); } else if (t == 6) { rmv++; } while (st.size() && st.top() < sp) { st.pop(); ans++; } } cout << ans << n ; }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// ii2dcam9b.v: An indirectly-indexed 2D BCAM (II2DCAM) stage of 9-bits pattern //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module ii2dcam9b
#( parameter CDEP = 4 , // depth (k-entries, power of 2)
parameter PIPE = 1 ) // pipelined?
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CDEP)+9:0] wAddr , // write address
input [8 :0] mPatt , // match pattern
input [8 :0] wPatt , // write pattern
output [CDEP*1024-1:0] mIndc ); // match indicators
wire oldPattMultiOcc ;
wire newPattMultiOcc ;
wire [4 :0] newPattOccFLoc ;
wire [8 :0] oldPatt ;
wire [31:0] wIndc ;
wire [4 :0] oldIdx ;
wire [4 :0] newIdx ;
wire [4 :0] wIndx ;
wire [4 :0] vacFLoc ;
wire oldNewbPattWr ;
// pipelining //
wire oldPattMultiOccI;
wire newPattMultiOccI;
wire [4 :0] newPattOccFLocI ;
wire [8 :0] oldPattI ;
wire [31:0] wIndcI ;
wire [4 :0] oldIdxI ;
wire [4 :0] newIdxI ;
wire [4 :0] wIndxI ;
wire [4 :0] vacFLocI ;
wire oldNewbPattWrI ;
reg oldPattMultiOccR;
reg newPattMultiOccR;
reg [4 :0] newPattOccFLocR ;
reg [8 :0] oldPattR ;
reg [31:0] wIndcR ;
reg [4 :0] oldIdxR ;
reg [4 :0] newIdxR ;
reg [4 :0] wIndxR ;
reg [4 :0] vacFLocR ;
reg oldNewbPattWrR ;
always @(posedge clk, posedge rst)
if (rst) {oldPattMultiOccR,newPattMultiOccR,newPattOccFLocR,oldPattR,wIndcR,oldIdxR,newIdxR,wIndxR,vacFLocR,oldNewbPattWrR} <= {54{1'b0}};
else {oldPattMultiOccR,newPattMultiOccR,newPattOccFLocR,oldPattR,wIndcR,oldIdxR,newIdxR,wIndxR,vacFLocR,oldNewbPattWrR} <=
{oldPattMultiOccI,newPattMultiOccI,newPattOccFLocI,oldPattI,wIndcI,oldIdxI,newIdxI,wIndxI,vacFLocI,oldNewbPattWrI};
assign {oldPattMultiOcc ,newPattMultiOcc ,newPattOccFLoc ,oldPatt ,wIndc ,oldIdx ,newIdx ,wIndx ,vacFLoc ,oldNewbPattWr } = PIPE ?
{oldPattMultiOccR,newPattMultiOccR,newPattOccFLocR,oldPattR,wIndcR,oldIdxR,newIdxR,wIndxR,vacFLocR,oldNewbPattWrR} :
{oldPattMultiOccI,newPattMultiOccI,newPattOccFLocI,oldPattI,wIndcI,oldIdxI,newIdxI,wIndxI,vacFLocI,oldNewbPattWrI} ;
///////////////////////////////////////////////////////////////////////////////
// control signals
wire oldPattV, wEnb_iVld ,wEnb_indx, wEnb_indc, wEnb_setram, wEnb_idxram, wEnb_vacram, wIVld;
camctl
camctli ( .clk (clk ), // clock / input
.rst (rst ), // global registers reset / input
.wEnb (wEnb ), // CAM write enable / input
.oldPattV (oldPattV ), // is old (rewritten) pattern valid? / input from setram
.oldPattMultiOcc(oldPattMultiOcc ), // does old pattern has multi(other)-occurrences? / input from setram
.newPattMultiOcc(newPattMultiOcc ), // does new pattern has multi(other)-occurrences? / input from setram
.oldEqNewPatt (oldPatt==wPatt ),
.wEnb_setram (wEnb_setram ), // write enable to sets RAM / output to setram
.wEnb_idxram (wEnb_idxram ), // write enable to indices RAM / output to idxram
.wEnb_vacram (wEnb_vacram ), // write enable to vacancy RAM / output to vacram
.wEnb_indc (wEnb_indc ), // write enable / full indicators MLABs / output to iitram9b
.wEnb_indx (wEnb_indx ), // write enable / indicator index RAM / output to iitram9b
.wEnb_iVld (wEnb_iVld ), // write enable / indicator valid RAM / output to iitram9b
.wIVld (wIVld ), // write indicator validity / output to iitram9b
.oldNewbPattWr (oldNewbPattWrI )); // old pattern / new pattern (inverted) write / output
///////////////////////////////////////////////////////////////////////////////
wire [31:0] oldPattIndc;
wire [31:0] newPattIndc;
// write indicators mux; either old or new pattern indicators are written into iitram
assign wIndcI = oldNewbPattWr ? oldPattIndc : newPattIndc;
// write indicators mux;
wire [4:0] oldIdx_ = oldPattMultiOcc ? oldIdx : {5'b0} ;
wire [4:0] newIdx_ = newPattMultiOcc ? newIdx : vacFLoc;
assign wIndxI = oldNewbPattWr ? oldIdx_ : newIdx_;
///////////////////////////////////////////////////////////////////////////////
iitram9b #( .DEP (CDEP ), // depth (k-entries, power of 2)
.PIPE (PIPE )) // pipelined?
iitram9bi ( .clk (clk ), // clock / input
.rst (rst ), // global registers reset / input
.wEnb_iVld (wEnb_iVld ), // write enable / indicator valid RAM / input
.wEnb_indx (wEnb_indx ), // write enable / indicator index RAM / input
.wEnb_indc (wEnb_indc ), // write enable / full indicators MLABs / input
.mPatt (mPatt ), // match pattern / input [8 :0]
.wPatt (oldNewbPattWr ? oldPatt : wPatt), // write pattern / input [8 :0]
.wAddr_indx(wAddr[`log2(CDEP)+9:5]), // write address / index / input [4 :0]
.wAddr_indc(wIndx ), // write address / indicator (in index range) / input [4 :0]
.wIndx (wIndx ), // write index / input [4 :0]
.wIVld (wIVld ), // write indicator validity / input
.wIndc (wIndc ), // write indicator (full) / input [31 :0]
.mIndc (mIndc )); // match indicators / output [1023:0]
///////////////////////////////////////////////////////////////////////////////
setram #( .CDEP (CDEP ), // CAM depth (k-entries)
.PIPE (PIPE )) // pipelined?
setrami ( .clk (clk ), // clock / input
.rst (rst ), // global registers reset / input
.wEnb (wEnb_setram ), // write enable / input
.wPatt (wPatt ), // write pattern / input [8 :0]
.wAddr (wAddr ), // write address / input [log2(CDEP)+9:0]
.oldPatt (oldPattI ), // old (rewritten) pattern / output [8 :0]
.oldPattV (oldPattV ), // is old (rewritten) pattern valid? / output
.oldPattMultiOcc(oldPattMultiOccI ), // does old pattern has multi(other)-occurrences? / output
.newPattMultiOcc(newPattMultiOccI ), // does new pattern has multi(other)-occurrences? / output
.newPattOccFLoc (newPattOccFLocI ), // first location of a new pattern occurrence / output [4 :0]
.oldPattIndc (oldPattIndc ), // old pattern indicators / output [31 :0]
.newPattIndc (newPattIndc )); // current new pattern indicators (w/ written pattern) / output [31 :0]
///////////////////////////////////////////////////////////////////////////////
idxram #( .CDEP (CDEP ), // depth (k-entries)
.PIPE (PIPE )) // pipelined?
idxrami ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnb_idxram ), // write enable // input
.wAddr (wAddr ), // write address // input [`log2(CDEP)+9:0]
.vacFLoc (newIdx_ ), // vacancy first location // input [4 :0]
.newPattOccFLoc (newPattOccFLoc ), // first location of a new pattern occurrence // input [4 :0]
.oldIdx (oldIdxI ), // old pattern index // output [4 :0]
.newIdx (newIdxI )); // new pattern index // output [4 :0]
///////////////////////////////////////////////////////////////////////////////
vacram #( .CDEP (CDEP ), // depth (k-entries) // input
.PIPE (PIPE )) // pipelined?
vacrami ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnb_vacram ), // write enable // input
.wAddr (wAddr ), // write address // [`log2(CDEP)+9:0] input
.oldPattV (oldPattV ), // is old (rewritten) pattern valid? / input from setram
.oldPattMultiOcc(oldPattMultiOcc ), // input
.newPattMultiOcc(newPattMultiOcc ), // input
.oldIdx (oldIdx ), // [4:0] input
.vacFLoc (vacFLocI )); // [4:0] output
///////////////////////////////////////////////////////////////////////////////
endmodule
|
//======================================================================
//
// trng_debug_ctrl.v
// -----------------
// Debug and control module in the Cryptech TRNG.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module trng_debug_ctrl(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
// Debug and control ports
output wire csprng_debug_mode,
output wire [4 : 0] csprng_num_rounds,
output wire csprng_reseed,
input wire csprng_error,
output wire security_error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter CORE_NAME0 = 32'h73686132; // "sha2"
parameter CORE_NAME1 = 32'h2d323536; // "-512"
parameter CORE_VERSION = 32'h302e3830; // "0.80"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
case (address)
// Write operations.
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
case (address)
// Read operations.
ADDR_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // trng_debug_ctrl
//======================================================================
// EOF trng_debug_ctrl.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long q; cin >> q; while (q--) { long long l1, r1, l2, r2; cin >> l1 >> r1 >> l2 >> r2; if (l1 == l2) { cout << l1 << << r2 << n ; continue; } if (l1 == r2) { cout << l1 << << l2 << n ; continue; } if (r1 == l2) { cout << r1 << << r2 << n ; continue; } if (r2 == r1) { cout << r1 << << l2 << n ; continue; } cout << l1 << << l2 << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_BEHAVIORAL_PP_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This FIFO module behaves similar to scfifo in legacy mode. It has an
output latency of 1 or 2 clock cycles and does not support look ahead
mode. Unlike scfifo this FIFO allows you to write to any of the byte
lanes before committing the word. This allows you to write the full
word in multiple clock cycles and then you assert the "push" signal to
commit the data. To read data out of the FIFO assert "pop" and wait
1 or 2 clock cycles for valid data to arrive.
Version 1.1
1.0 - Uses 'altsyncram' which will not be optimized away if the
FIFO inputs are grounded. This will need to be replaced
with inferred memory once Quartus II supports inferred
with byte enables (currently it instantiates multiple
seperate memories.
1.1 - Seperated the asynchronous reset into seperate async. and sync.
resets.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
#include <bits/stdc++.h> void solve() { int n; std::cin >> n; int a = 0; std::string s; std::cin >> s; bool flag = false; int x, y; x = y = 0; if (s[0] == U ) { ++y; } else { ++x; } if (x > y) flag = true; for (size_t i = 1; i < s.size(); ++i) { if (s[i] == U ) { ++y; } else { ++x; } if (x > y && !flag) { flag = true; ++a; } else if (x < y && flag) { flag = false; ++a; } } std::cout << a; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); solve(); return 0; }
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Arguments id {A} x.
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
#[global]
Hint Unfold compose : core.
Declare Scope program_scope.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Local Open Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Arguments prod_curry_subdef {A B C} f p.
Arguments prod_uncurry_subdef {A B C} f x y.
|
#include <bits/stdc++.h> using namespace std; long long v[100005]; long long st[400005]; void init(int idx, int a, int b) { if (a == b) { st[idx] = v[a]; } else { int m = (a + b) / 2; init(idx * 2 + 1, a, m); init(idx * 2 + 2, m + 1, b); st[idx] = max(st[idx * 2 + 1], st[idx * 2 + 2]); } } long long query(int idx, int a, int b, int i, int j) { if (i > b || j < a) return -1; else if (j >= b && i <= a) return st[idx]; int m = (a + b) / 2; long long x0 = query(idx * 2 + 1, a, m, i, j); long long x1 = query(idx * 2 + 2, m + 1, b, i, j); return max(x0, x1); } int main() { int n; int qry; ios_base ::sync_with_stdio(0); cin.tie(0); char c; int x, y; cin >> n; for (int i = 0; i < n; ++i) cin >> v[i]; init(0, 0, n - 1); for (int i = 0; i < n; ++i) { long long mn = query(0, 0, n - 1, i + 1, n - 1); if (v[i] > mn) cout << 0 << ; else cout << mn - v[i] + 1 << ; } cout << n ; }
|
#include <bits/stdc++.h> using namespace std; int n, k, r, c; vector<string> grip; int main() { grip.clear(); cin >> r >> c >> n >> k; string ful = ; for (int i = 0; i < c; i++) ful += . ; for (int i = 0; i < r; i++) grip.push_back(ful); for (int i = 0; i < n; i++) { int y, x; cin >> y >> x; y--, x--; grip[y][x] = # ; } int ans = 0; for (int il = 0; il < r; il++) { for (int ir = il; ir < r; ir++) { for (int jl = 0; jl < c; jl++) { for (int jr = jl; jr < c; jr++) { int con = 0; for (int p = il; p <= ir; p++) { for (int q = jl; q <= jr; q++) if (grip[p][q] == # ) con++; } if (con >= k) ans++; } } } } cout << ans << endl; }
|
`default_nettype none
`define WIDTH 16
module stack2pipe4(
input wire clk,
output wire [`WIDTH-1:0] rd,
input wire we,
input wire [1:0] delta,
input wire [`WIDTH-1:0] wd);
parameter DEPTH = 18;
localparam BITS = (`WIDTH * DEPTH) - 1;
localparam STATESIZE = `WIDTH * (DEPTH + 1); // complete size of a stack, ie tail+head.
// there are four stacks in total, accessed always in round-robin order.
localparam STATEBITS = STATESIZE - 1; // for wire out of delay
localparam DELAYBITS = (STATESIZE * 3) - 1; // bits to hold the other three stacks.
wire move = delta[0];
wire pop = delta[1];
// these two still written to "now", ie, are the results to save from the present cycle.
reg [15:0] head;
reg [BITS:0] tail;
reg [DELAYBITS:0] delay;
wire [15:0] headN, oldhead;
wire [BITS:0] tailN, oldtail;
wire [DELAYBITS:0] delayN;
// read from the delay fifo, replaced head and tail as the place to read from the old version of current stack.
assign {oldtail, oldhead} = delay[STATEBITS:0];
assign rd = oldhead;
// note these retain old values if not move (and not we and not push). This used to be implicit, but can't be now, since head and tail will cycle through all the stacks, even if neither a move nor a write.
assign headN = we ? wd : (move ? oldtail[15:0] : oldhead);
assign tailN = move ? (pop ? {16'h55aa, oldtail[BITS:16]} : {oldtail[BITS-16:0], oldhead}) : oldtail;
// this is a clock stale already, since it takes it *from* head and tail.
// delay will delay it another three clock cycles.
assign delayN = {tail, head, delay[DELAYBITS:STATESIZE]};
always @(posedge clk) begin
// pass around the other three stacks.
delay <= delayN;
// update the current stack.
head <= headN;
tail <= tailN;
end
`ifdef VERILATOR
int depth /* verilator public_flat */;
always @(posedge clk) begin
if (delta == 2'b11)
depth <= depth - 1;
if (delta == 2'b01)
depth <= depth + 1;
end
`endif
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blk_mem_gen_v7_3.v when simulating
// the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blk_mem_gen_v7_3(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("blk_mem_gen_v7_3.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return (a.second < b.second); } int main() { vector<pair<long long int, long long int>> v; long long int n, m, k; cin >> n >> m >> k; long long int a[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; v.push_back(make_pair(a[i], i)); } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); long long int beauty = 0; for (long long int i = 0; i < m * k; i++) { beauty += v[i].first; } cout << beauty << n ; long long int j = 0, q = 0; int pos[999999]; for (int i = 0; i < n; i++) { pos[v[i].second] = i; } for (int i = 0; i < n; i++) { if (pos[i] < m * k) { j++; if (j == m) { q++; if (q < k) { cout << i + 1 << ; j = 0; } } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j; long long int prod = 1; char mat[105][105]; cin >> n >> m; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> mat[i][j]; } } for (i = 0; i < m; i++) { unordered_set<char> s; for (j = 0; j < n; j++) { if (s.find(mat[j][i]) == s.end()) s.insert(mat[j][i]); } prod = (prod * (s.size() % 1000000007)) % 1000000007; } cout << prod << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (
`ifdef T_CLK_2IN_VEC
input [1:0] clks,
`else
input c0,
input c1,
`endif
input check
);
`ifdef T_CLK_2IN_VEC
wire c0 = clks[0];
wire c1 = clks[1];
`endif
integer p0 = 0;
integer p1 = 0;
integer p01 = 0;
integer n0 = 0;
integer n1 = 0;
integer n01 = 0;
`define display_counts(text) begin \
$write("[%0t] ",$time); \
`ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \
$write(text); \
$write(": %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01); \
end
always @ (posedge c0) begin
p0 = p0 + 1; // Want blocking, so don't miss clock counts
`ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif
end
always @ (posedge c1) begin
p1 = p1 + 1;
`ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif
end
always @ (posedge c0 or posedge c1) begin
p01 = p01 + 1;
`ifdef TEST_VERBOSE `display_counts("posedge *"); `endif
end
always @ (negedge c0) begin
n0 = n0 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif
end
always @ (negedge c1) begin
n1 = n1 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif
end
always @ (negedge c0 or negedge c1) begin
n01 = n01 + 1;
`ifdef TEST_VERBOSE `display_counts("negedge *"); `endif
end
always @ (posedge check) begin
if (p0!=4) $stop;
if (p1!=4) $stop;
if (p01!=6) $stop;
if (n0!=4) $stop;
if (n1!=4) $stop;
if (n01!=6) $stop;
$write("*-* All Finished *-*\n");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int dp[50][2000], r[50], n; const int inf = 1e6; int abs(int a) { return a > 0 ? a : -a; } int getTime(int id, int k) { if (k <= 0) return 0; if (dp[id][k]) return dp[id][k]; dp[id][k] = inf; for (int i = 0; i < n; i++) { if (s[i] == s[id] or r[i] <= r[id]) continue; dp[id][k] = min(dp[id][k], abs(i - id) + getTime(i, k - r[i])); } return dp[id][k]; } int solve(int st, int k) { int ans = inf; for (int id = 0; id < n; id++) ans = min(ans, abs(st - id) + getTime(id, k - r[id])); return ans == inf ? -1 : ans; } int main() { int st, k; cin >> n >> st >> k; for (int i = 0; i < n; i++) cin >> r[i]; cin >> s; cout << solve(st - 1, k) << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005000; int A[maxn], sum[maxn][10]; int dfs(int u) { if (u < 10) return u; if (A[u]) return A[u]; int now = 1, tmp = u; while (u) { if (u % 10 != 0) now *= u % 10; u /= 10; } return A[tmp] = dfs(now); } int main() { for (int i = 1; i <= 1000000; i++) A[i] = dfs(i); for (int i = 1; i <= 1000000; i++) { for (int j = 1; j <= 9; j++) { if (A[i] == j) sum[i][j] = sum[i - 1][j] + 1; else sum[i][j] = sum[i - 1][j]; } } int Q; cin >> Q; while (Q--) { int l, r, k; scanf( %d%d%d , &l, &r, &k); cout << sum[r][k] - sum[l - 1][k] << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, m; cin >> n >> m; int a[n][m]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; int flag = 0; for (int i = n - 2; i >= 1; i--) { for (int j = m - 2; j >= 1; j--) { if ((a[i + 1][j] == a[i][j - 1]) || (a[i][j + 1] == a[i - 1][j])) { flag = 1; break; } else if (a[i][j] == 0) { a[i][j] = min(a[i + 1][j], a[i][j + 1]) - 1; } if (a[i][j] <= a[i - 1][j] || a[i][j] <= a[i][j - 1]) { flag = 1; break; } } } int sum = 0; for (int i = 0; i < n - 1; i++) { if (a[i][0] >= a[i + 1][0] || a[i][m - 1] >= a[i + 1][m - 1]) { flag = 1; break; } } for (int i = 0; i < m - 1; i++) { if (a[0][i] >= a[0][i + 1] || a[n - 1][i] >= a[n - 1][i + 1]) { flag = 1; break; } } if (flag == 1) { cout << -1 << n ; return 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) sum += a[i][j]; } cout << sum; return 0; }
|
//Connect the switches to the LEDs, inverting the signal in the ROI
//Assumes # inputs = # outputs
`include "defines.v"
module roi(input clk,
input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
parameter DIN_N = `DIN_N;
parameter DOUT_N = `DOUT_N;
wire [DIN_N-1:0] internal;
genvar i;
generate
//CLK
(* KEEP, DONT_TOUCH *)
reg clk_reg;
always @(posedge clk) begin
clk_reg <= clk_reg;
end
//DIN
for (i = 0; i < DIN_N; i = i+1) begin:ins
//Very expensive inverter
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b10)
) lut (
.I0(din[i]),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O(internal[i]));
end
//DOUT
for (i = 0; i < DOUT_N; i = i+1) begin:outs
//Very expensive buffer
(* KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'b010)
) lut (
.I0(internal[i]),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0),
.I4(1'b0),
.I5(1'b0),
.O(dout[i]));
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n], b[1000000] = {0}; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n / 2; i++) { if (a[i] - i - 1 >= 0) b[a[i] - i - 1]++; if (a[n - 1 - i] - i - 1 >= 0) b[a[n - 1 - i] - i - 1]++; } if (n % 2 && a[n / 2] - (n / 2 + 1) >= 0) { b[a[n / 2] - (n / 2 + 1)]++; } int m = -1; for (int i = 0; i < 1000000; i++) m = m > b[i] ? m : b[i]; cout << n - m; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int xi[] = {1, 1, 1, 0, 0, -1, -1, -1}; const int yi[] = {-1, 0, 1, -1, 1, -1, 0, 1}; int main() { int m, n; cin >> m >> n; char g[m][n]; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) cin >> g[i][j]; int u, v; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { if (g[i][j] == * ) continue; int cnt = 0; for (int k = 0; k < 8; k++) { u = i + xi[k]; v = j + yi[k]; if (u >= 0 && u < m && v >= 0 && v < n && g[u][v] == * ) cnt++; } if (g[i][j] == . ) { if (cnt != 0) { cout << NO n ; return 0; } } else { if (g[i][j] - 0 != cnt) { cout << NO n ; return 0; } } } } cout << YES n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int ans, sum, pro; string s, str; long long int solve(int st, int end, string z) { long long int sum2 = 0, pro2 = 1; for (int i = st; i <= end; i++) { if (z[i] == + ) { sum2 += pro2; pro2 = 1; } else if (i % 2 == 0) pro2 *= s[i] - 0 ; } return sum2 + pro2; } int main() { cin >> s; str = 1* ; str += s; str += *1 ; s = str; for (int i = 1; i < s.size(); i += 2) { if (s[i] == + ) continue; for (int j = i + 2; j < s.size(); j += 2) { if (s[j] == * ) { sum = 0, pro = 1; for (int k = 0; k < s.size(); k++) { if (k == i) pro *= solve(i + 1, j - 1, s); else if (k >= i && k <= j) continue; else if (s[k] == + ) { sum += pro; pro = 1; } else if (k % 2 == 0) pro *= s[k] - 0 ; } sum += pro; ans = max(ans, sum); } } } cout << ans << n ; }
|
module InstName (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [7:0] in;
output [7:0] out;
wire [7:0] out = ~in;
endmodule // bottm
module top (/*AUTOARG*/
// Outputs
outgo,
// Inputs
incom
);
input [31:0] incom;
output [31:0] outgo;
/* AUTO_LISP(defun getparam2 (strg)
(string-match "[^0-9]*[0-9]+[^0-9]*\\([0-9]+\\)" strg)
(match-string 1 strg))*/
/* InstName AUTO_TEMPLATE (
.out (@),
.in (@"(getparam2 vl-cell-name)"),
);
*/
InstName BT0_2 (/*AUTOINST*/
// Outputs
.out (0), // Templated
// Inputs
.in (2)); // Templated
InstName BT1_3 (/*AUTOINST*/
// Outputs
.out (1), // Templated
// Inputs
.in (3)); // Templated
InstName BT2_5 (/*AUTOINST*/
// Outputs
.out (2), // Templated
// Inputs
.in (5)); // Templated
InstName BT3_9 (/*AUTOINST*/
// Outputs
.out (3), // Templated
// Inputs
.in (9)); // Templated
endmodule
|
`include "defines.v"
`define S_IDLE 3'b000
`define S_INST 3'b010
`define S_DATA 3'b011
`define S_SB_LOAD 3'b100
`define S_SB_STORE 3'b101
module memcontrol(
input wire clk,
input wire rst,
//Input
//Data from MEM
input wire[2:0] ramOp_i,
input wire[31:0] storeData_i,
input wire[31:0] ramAddr_i,
//Instruction from PC
input wire[31:0] insAddr_i,
//Data from MMU
input wire[31:0] ramData_i,
//Exception from MMU
input wire[3:0] exception_i,
//Serial port control
input wire pauseRequest_i,
//Output
//Control
output wire pauseRequest_o,
//Data to MEM
output reg[31:0] ramData_o,
//Instruction to IF_ID
output reg[31:0] ins_o,
//Signal to MMU
output reg[2:0] ramOp_o,
output reg[31:0] storeData_o,
output reg[31:0] ramAddr_o,
//Exception to MEM
output reg[3:0] exceptionMEM_o,
//Exception to IF_ID
output reg[3:0] exceptionIF_o,
output reg[31:0] badVAddrIF_o
);
reg[2:0] memState;
reg[31:0] dataBuffer;
reg[31:0] storeByteBuffer;
reg[3:0] exceptionBuffer;
reg pauseRequest;
wire[31:0] ramAddrAligned = {ramAddr_i[31:2], 2'b00};
wire[2:0] memLastState = memState;
//Pause control (improved)
assign pauseRequest_o = pauseRequest | pauseRequest_i;
//State Machine
always @(posedge clk) begin
if (rst == `Enable) begin
memState <= `S_IDLE;
end else if (pauseRequest_i == `Enable) begin
memState <= memLastState;
end else if (memState == `S_IDLE || memState == `S_DATA || memState == `S_SB_STORE) begin
memState <= `S_INST;
end else if (memState == `S_SB_LOAD) begin
memState <= `S_SB_STORE;
end else if (ramOp_i == `MEM_NOP_OP) begin
memState <= `S_INST;
end else if (ramOp_i == `MEM_SB_OP) begin
memState <= `S_SB_LOAD;
end else begin
memState <= `S_DATA;
end
end
//Buffer
always @(posedge clk) begin
if (rst == `Enable) begin
dataBuffer <= `ZeroWord;
exceptionBuffer <= `EXC_NONE;
end else if (memState == `S_INST) begin
dataBuffer <= ramData_i;
exceptionBuffer <= exception_i;
end
end
//Bad Address to IF_ID
always @(*) begin
if (exceptionIF_o != `EXC_NONE) begin
badVAddrIF_o = insAddr_i;
end else begin
badVAddrIF_o = `ZeroWord;
end
end
//Data Buffer for SB Instruction
always @(posedge clk) begin
if (rst == `Enable) begin
storeByteBuffer <= `ZeroWord;
end else if (memState == `S_SB_LOAD) begin
if (ramAddr_i[1:0] == 2'b11) begin
storeByteBuffer <= {storeData_i[7:0], ramData_i[23:0]};
end else if (ramAddr_i[1:0] == 2'b10) begin
storeByteBuffer <= {ramData_i[31:24], storeData_i[7:0], ramData_i[15:0]};
end else if (ramAddr_i[1:0] == 2'b01) begin
storeByteBuffer <= {ramData_i[31:16], storeData_i[7:0], ramData_i[7:0]};
end else begin
storeByteBuffer <= {ramData_i[31:8], storeData_i[7:0]};
end
end
end
reg[7:0] ramByte;
wire[31:0] signData = {{24{ramByte[7]}}, ramByte[7:0]};
wire[31:0] zeroData = {24'h0, ramByte[7:0]};
//Byte choose
always @(*) begin
if (ramAddr_i[1:0] == 2'b00) begin
ramByte = ramData_i[7:0];
end else if (ramAddr_i[1:0] == 2'b01) begin
ramByte = ramData_i[15:8];
end else if (ramAddr_i[1:0] == 2'b10) begin
ramByte = ramData_i[23:16];
end else begin
ramByte = ramData_i[31:24];
end
end
always @(*) begin
if (memState == `S_IDLE) begin
//Control
pauseRequest = `Disable;
//MMU
ramOp_o = `MEM_NOP_OP;
storeData_o = `ZeroWord;
ramAddr_o = `ZeroWord;
//MEM
ramData_o = `ZeroWord;
//IF_ID
ins_o = `ZeroWord;
//Exception
exceptionMEM_o = `EXC_NONE;
exceptionIF_o = `EXC_NONE;
end else if (memState == `S_INST) begin
//Control
if (ramOp_i == `MEM_NOP_OP) begin
pauseRequest = `Disable;
end else begin
pauseRequest = `Enable;
end
//MMU
ramOp_o = `MEM_LW_OP;
storeData_o = `ZeroWord;
ramAddr_o = insAddr_i;
//MEM
ramData_o = `ZeroWord;
//IF_ID
ins_o = ramData_i;
//Exception
exceptionMEM_o = `EXC_NONE;
exceptionIF_o = exception_i;
end else if (memState == `S_SB_STORE) begin
//Control
pauseRequest = `Disable;
//MMU
ramOp_o = `MEM_SW_OP;
storeData_o = storeByteBuffer;
ramAddr_o = ramAddrAligned;
//MEM
ramData_o = `ZeroWord;
//IF_ID
ins_o = dataBuffer;
//Exception
exceptionMEM_o = exception_i;
exceptionIF_o = exceptionBuffer;
end else if (memState == `S_SB_LOAD) begin
//Control
pauseRequest = `Enable;
//MMU
ramOp_o = `MEM_LW_OP;
storeData_o = `ZeroWord;
ramAddr_o = ramAddrAligned;
//MEM
ramData_o = `ZeroWord;
//IF_ID
ins_o = dataBuffer;
//Exception
exceptionMEM_o = exception_i;
exceptionIF_o = exceptionBuffer;
end else begin
//Control
pauseRequest = `Disable;
//MMU
ramOp_o = ramOp_i;
storeData_o = storeData_i;
ramAddr_o = ramAddr_i;
//MEM
ramData_o = ramData_i;
//IF_ID
ins_o = dataBuffer;
//Exception
exceptionMEM_o = exception_i;
exceptionIF_o = exceptionBuffer;
if (ramOp_i == `MEM_LB_OP) begin
//MMU
ramOp_o = `MEM_LW_OP;
ramAddr_o = ramAddrAligned;
//MEM
ramData_o = signData;
end else if (ramOp_i == `MEM_LBU_OP) begin
//MMU
ramOp_o = `MEM_LW_OP;
ramAddr_o = ramAddrAligned;
//MEM
ramData_o = zeroData;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3fll; const int maxn = 1000010; const long long mod = 1e9 + 7; char str1[maxn], str2[maxn]; int ans[maxn]; long long L1[maxn], R1[maxn], L2[maxn], R2[maxn]; int main() { while (scanf( %s , str1 + 1) != -1) { scanf( %s , str2 + 1); int len1 = strlen(str1 + 1); int len2 = strlen(str2 + 1); if (len1 - 1 != len2) { printf( 0 n ); continue; } L1[0] = 0; L2[0] = 0; R1[len1 + 1] = 0; R2[len2 + 1] = 0; for (int i = 1; i <= len1; i++) L1[i] = (L1[i - 1] * 26 + str1[i]) % mod; for (int i = len1; i >= 1; i--) R1[i] = (R1[i + 1] * 26 + str1[i]) % mod; for (int i = 1; i <= len2; i++) L2[i] = (L2[i - 1] * 26 + str2[i]) % mod; for (int i = len2; i >= 1; i--) R2[i] = (R2[i + 1] * 26 + str2[i]) % mod; int len = 0; for (int i = 1; i <= len1; i++) { if (L1[i - 1] == L2[i - 1] && R1[i + 1] == R2[i]) ans[len++] = i; } printf( %d n , len); for (int i = 0; i < len; i++) { if (i == len - 1) printf( %d n , ans[i]); else printf( %d , ans[i]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000 * 1000 * 1000 + 7; long long n, k; vector<long long> ans; long long positive(long long n) { n %= mod; (n < 0) && (n += mod); return n; } long long gcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long g = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return g; } long long binpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % mod; a = (a * a) % mod; b >>= 1; } return ans; } void calc() { long long x = 0; ans.push_back(0); for (int i = 0; i < k + 1; ++i) { x = (x + binpow(i + 1, k)) % mod; ans.push_back(x); } } long long solve(vector<long long> ans, long long y) { long long x = 0; long long cur = 1; for (int j = 1; j < (long long)ans.size(); ++j) { cur = (cur * positive(y - j)) % mod; cur = (cur * binpow(positive(0 - j), mod - 2)) % mod; } for (int i = 0; i < (long long)ans.size(); ++i) { x = (x + (ans[i] * cur) % mod) % mod; if (i + 1 >= (long long)ans.size()) break; long long t = (positive(y - i) * binpow(positive(y - (i + 1)), mod - 2)) % mod; cur = (cur * t) % mod; long long v = (positive(i - ((long long)ans.size() - 1)) * binpow(positive(i + 1), mod - 2)) % mod; cur = (cur * v) % mod; } return x; } int main() { cin >> n >> k; calc(); if (n < ans.size()) { cout << ans[n]; } else { cout << solve(ans, n); } }
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A one bit data synchronization module, where data is synchronized
// by passing through 2 registers of the destination clock
module SyncBit (
sCLK,
sRST_N,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST_N;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
assign dD_OUT = dSyncReg2 ;
always @(posedge sCLK or negedge sRST_N)
begin
if (sRST_N ==0)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST_N ==0)
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY (sD_IN == 1'b1) ? 1'b1 : 1'b0 ;
end // if ( sEN )
end // else: !if(sRST_N ==0)
end // always @ (posedge sCLK or negedge sRST_N)
always @(posedge dCLK or negedge sRST_N)
begin
if (sRST_N ==0)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST_N ==0)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(sRST_N ==0)
end // always @ (posedge dCLK or negedge sRST_N)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
dSyncReg2 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // BitSync
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_FUNCTIONAL_PP_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int read() { int res = 0, p = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) p = -1; ch = getchar(); } while (isdigit(ch)) res = res * 10 + ch - 0 , ch = getchar(); return res * p; } const int mod = 1e9 + 7; int t; int main() { t = read(); while (t--) { long long n = read() * 2; long long x = 1; for (int i = 3; i <= n; ++i) { x = (x * i) % mod; } printf( %d n , x); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; const int mod1 = 1000000007; long long gcd(long long a, long long b) { long long c = a % b; while (c != 0) { a = b; b = c; c = a % b; } return b; } long long issub(string a, string b) { if (a.find(b) != string::npos) return 1; else return 0; } long long expo(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = res * a % mod1; a = a * a % mod1; b >>= 1; } return res; } int32_t lcm(long long n1, long long n2) { long long max = (n1 > n2) ? n1 : n2; do { if (max % n1 == 0 && max % n2 == 0) { return max; } else ++max; } while (true); } string operator*(string a, unsigned long long b) { string output = ; while (b--) output += a; return output; } bool isPerfectSquare(long long n) { for (long long i = 1; i * i <= n; i++) { if ((n % i == 0) && (n / i == i)) { return true; } } return false; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(NULL); ; long long t, a = 0, x; cin >> t; map<long long, long long> m; for (long long i = 0; i < t; i++) { cin >> x; m[x]++; a = max(a, m[x]); } cout << a; return 0; }
|
#include <bits/stdc++.h> using namespace std; double a, v, d, w, l, ans, mid, t2, t; bool check(double maxv) { return d - ((maxv + w) / 2) * (((maxv - w) * 2) / a) > 1e-8; } int main() { scanf( %lf %lf %lf %lf %lf , &a, &v, &l, &d, &w); w = min(min(w, v), sqrt(2 * a * d)); if (2 * a * d + w * w > 2 * v * v) { t = (d - v * v / a + w * w / a / 2) / v + (2 * v - w) / a; } else { t = (2 * sqrt(a * d + w * w / 2) - w) / a; } l = l - d; t2 = (v - w) / a; if (l - w * t2 - 0.5 * a * t2 * t2 > 0) { t2 = t2 + (l - w * t2 - 0.5 * a * t2 * t2) / v; } else { t2 = (-w + sqrt(w * w + 2.0 * a * l)) / a; } printf( %.10f n , t + t2); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int r, g, b, ck, maximum = 0, temp; scanf( %d %d %d , &r, &g, &b); if (r % 2 == 1) r++; r = r / 2; if (g % 2 == 1) g++; g = g / 2; if (b % 2 == 1) b++; b = b / 2; temp = 27 + r * 3; if (temp > maximum) maximum = temp; temp = 28 + g * 3; if (temp > maximum) maximum = temp; temp = 29 + b * 3; if (temp > maximum) maximum = temp; printf( %d n , maximum); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_b.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
port_b_1, // Will create p_mix_sig_1_go port
port_b_3, // Interhierachy link, will create p_mix_sig_3_go
port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
port_b_6i, // Conflicting definition
port_b_6o, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08 // VHDL intermediate needed (port name)
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
`ifdef insert_emu_mux_inst_ba
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_ba = 1'b0;
`endif
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
`ifdef insert_emu_mux_inst_bb
// Emulator Data Injection Path, generated by MIX
wire emu_mux_inst_bb = 1'b0;
`endif
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int t, n, m; long long ans; int main() { scanf( %d%d , &n, &m); if (n == 1) ans = m; else if (m == 1) ans = n; else if (n == 2) ans = ((m / 4) * 2 + min(m & 3, 2)) * 2ll; else if (m == 2) ans = ((n / 4) * 2 + min(n & 3, 2)) * 2ll; else ans = (n * 1ll * m + 1) / 2; printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; constexpr long long MOD = 1e9 + 7; long long cnt[710][710]; int a[500100]; int main() { int n; scanf( %d , &n); for (int ii = 0; ii < n; ++ii) { int t, x, y; scanf( %d%d%d , &t, &x, &y); if (t == 1) { a[x] += y; for (int i = 1; i <= 700; ++i) { cnt[i][x % i] += y; } } else { long long ans = 0; if (x > 700) { for (int i = y % x; i <= 500000; i += x) { ans += a[i]; } } else { ans = cnt[x][y % x]; } printf( %I64lld n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; map<char, long long> mp; for (long long i = 0; i < s.size(); i++) mp[s[i]]++; long long c = 0; for (auto it = mp.begin(); it != mp.end(); it++) { if (it->second & 1) c++; } if (c <= 1) cout << First ; else { if (c % 2 == 0) cout << Second ; else cout << First ; } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, mod, sumz, sumy, sum, last, first, kol, z; long long run(long long x, long long step) { long long res = 1; while (step) { if (step & 1) res = (res * x) % mod; x = x * x % mod; step >>= 1; } return res % mod; } int main() { cin >> a >> b; mod = 1000 * 1000 * 1000 + 7; sumz = (a * b) % mod; sumz = (sumz * (b - 1)) % mod; sumz = (sumz * run(2, mod - 2)) % mod; sumy = (a * (a + 1)) % mod; sumy = (sumy * b) % mod; sumy = (sumy * (b - 1)) % mod; sumy = (sumy * run(4, mod - 2)) % mod; sum = ((b * sumy) % mod + sumz) % mod; cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int test, a, sum = 0, wait = 0, counter = 0; priority_queue<int, vector<int>, greater<int> > q; queue<int> qqq; cin >> test; int num = test; while (test--) { cin >> a; sum += a; q.push(a); qqq.push(a); } while (!q.empty()) { int serve = q.top(); if (serve >= wait) counter++; else { q.pop(); continue; } wait += serve; q.pop(); } cout << counter << endl; }
|
#include <bits/stdc++.h> using namespace std; char s[200005], c; int a[200005]; int ans[26]; int main() { int n, k; int maxn = 0; cin >> n >> k; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { if (s[i] == s[i - 1]) a[i] = a[i - 1] + 1; else a[i] = 1; } for (int i = 0; i < n; i++) { if (a[i] != 0 && a[i] % k == 0) ans[(int)s[i] - a ]++; } for (int i = 0; i <= 25; i++) maxn = max(maxn, ans[i]); printf( %d , maxn); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:24:40 03/26/2015
// Design Name:
// Module Name: multiplier
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multiplier(
input clk,
input [12:0] A,
input [12:0] B,
output [26:0] Y,
output [26:0] Z
);
// [Y,Z] = [a, b; c, d] * [A; B]
reg [12:0] a = 13'b1111111111110; // -0.11
reg [12:0] b = 13'b0000000100101; // 2.3
reg [12:0] c = 13'b0000000110010; // 3.14
reg [12:0] d = 13'b1111101001100; // -11.25
//wyniki z mnozarek
wire [25:0] Aa;
wire [25:0] Bb;
wire[25:0] Ac;
wire [25:0] Bd;
multiply m1 ( // A * a
.clk(clk), // input clk
.a(A), // input [12 : 0] a
.b(a), // input [12 : 0] b
.p(Aa) // output [25 : 0] p
);
multiply m2 ( // B * b
.clk(clk), // input clk
.a(B), // input [12 : 0] a
.b(b), // input [12 : 0] b
.p(Bb) // output [25 : 0] p
);
multiply m3 ( // A * c
.clk(clk), // input clk
.a(A), // input [12 : 0] a
.b(c), // input [12 : 0] b
.p(Ac) // output [25 : 0] p
);
multiply m4 ( // B * d
.clk(clk), // input clk
.a(B), // input [12 : 0] a
.b(d), // input [12 : 0] b
.p(Bd) // output [25 : 0] p
);
//assign Y = Ac;
//assign Z = Bd;
sum s1 (
.a(Aa), // input [25 : 0] a
.b(Bb), // input [25 : 0] b
.clk(clk), // input clk
.s(Y) // output [26 : 0] s
);
sum s2 (
.a(Ac), // input [25 : 0] a
.b(Bd), // input [25 : 0] b
.clk(clk), // input clk
.s(Z) // output [26 : 0] s
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:32:20 04/26/2014
// Design Name:
// Module Name: dff2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:42:44 03/18/2013
// Design Name:
// Module Name: dff32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// 32λ´øÓÐÒì²½ÇåÁã¶ËµÄD´¥·¢Æ÷¡£
// ÊäÈëÐźţºd,clk,clrn
// Êä³öÐźţºq
// dΪÊäÈëµÄ32λÊý¾Ý£¬ÔÚclkµÄÉÏÉýÑص½À´Ê±D´¥·¢Æ÷½«DµÄÖµ´òÈëqÊä³ö£¬clrnµÄϽµÑص½À´Ê±´¥·¢Æ÷»áÊä³ö0
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dff2(d,clk,clrn,q
);
input [1:0] d;
input clk,clrn;
output [1:0] q;
reg [1:0] q;
always @ (posedge clk or negedge clrn) begin
if (clrn == 0) q <= 0;
else q <= d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long Gcd(long long a, long long b) { if (a % b == 0) return b; return Gcd(b, a % b); } long long Max(long long a, long long b) { if (a > b) return a; return b; } long long Min(long long a, long long b) { if (a < b) return a; return b; } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long modInverse(long long a, long long m) { long long x, y; long long g = gcdExtended(a, m, &x, &y); if (g != 1) return -1; else { long long res = (x % m + m) % m; return res; } } vector<int> primeFactors(int n) { vector<int> v; while (n % 2 == 0) { v.push_back(2); n = n / 2; } for (int i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { v.push_back(i); n = n / i; } } if (n > 2) v.push_back(n); return v; } long long C[2001][2000]; void binomialCoeff(long long n, long long k) { long long i, j; for (i = 0; i <= n; i++) { for (j = 0; j <= k; j++) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = (C[i - 1][j - 1] % 1000000007 + C[i - 1][j] % 1000000007) % 1000000007; } } } long long spf[100010]; void sieve() { spf[1] = 1; for (int i = 2; i < 100010; i++) spf[i] = i; for (int i = 4; i < 100010; i += 2) spf[i] = 2; for (int i = 3; i * i < 100010; i++) { if (spf[i] == i) { for (int j = i * i; j < 100010; j += i) if (spf[j] == j) spf[j] = i; } } } long long binarySearch(long long arr[], long long l, long long r, long long x) { if (r >= l) { long long mid = l + (r - l) / 2; if (arr[mid] == x) return mid; if (arr[mid] > x) return binarySearch(arr, l, mid - 1, x); return binarySearch(arr, mid + 1, r, x); } return -1; } const long long N = 100000; long long n; long long tree[2 * N]; void build(long long arr[]) { for (long long i = 0; i < n; i++) { tree[n + i] = arr[i]; } for (long long i = n - 1; i > 0; --i) { tree[i] = tree[i << 1] + tree[i << 1 | 1]; } } void updateTreeNode(long long p, long long value) { tree[p + n] = value; p = p + n; for (long long i = p; i > 1; i >>= 1) { tree[i >> 1] = tree[i] + tree[i ^ 1]; } } long long query(long long l, long long r) { long long res = 0; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) { res += tree[l++]; } if (r & 1) { res += tree[--r]; } } return res; } void dfs(std::vector<long long> v[], long long s, bool visited[]) { visited[s] = true; for (long long i = 0; i < v[s].size(); ++i) { if (!visited[v[s][i]]) { dfs(v, v[s][i], visited); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string x69; cin >> x69; long long n = x69.length(); char s[n + 1]; for (int i = 0, _n = (n); i < _n; i++) { s[i + 1] = x69[i]; } long long ev = 0; long long od = 0; long long ao = 0; long long ae = 0; long long bo = 0; long long be = 0; for (int i = (1), _b = (n); i <= _b; i++) { if (s[i] == a ) { if (i % 2) { od += ao + 1; ev += ae; } else { od += ae + 1; ev += ao; } if (i % 2) ao++; else ae++; } if (s[i] == b ) { if (i % 2) { od += bo + 1; ev += be; } else { od += be + 1; ev += bo; } if (i % 2) bo++; else be++; } } cout << ev << << od << endl; return 0; }
|
/*
* SPI_client.v client module
*
* SPI module with 16 byte buffer
* Addresses: 0 - data, 1 - control(write)/status(read)
* Control reg; bit 0 - ready to process, bit 7 - clear in/out buffers
* Status reg; CSn,0,0,master_rdy_i,outbound_full,outbound_empty,inbound_full,inbound_empty
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2016
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module spi_client #(
parameter fifo_log2 = 9
) (
// SPI client connection
input fast_clock_i, // At least 4 times faster than SPI clock of 40MHz
input mosi_i,
output miso_o,
input sck_i,
input cs_i,
// External SPI status signals
output slave_rdy_o,
input master_rdy_i,
// Bus signals
input n_reset_i,
input busclk_i,
input [3:0] A_i, // Only 2 registers, buffer(0) and status(1)
input [7:0] D_i,
output [7:0] D_o,
input nWR_i,
input nRD_i,
// Host interrupt, cleared by a read to the status register
output interrupt_o,
// DMA interface for Initial Program Load
input dma_en_i, // DMA enable
output [15:0] dma_adr_o, // DMA address
output [7:0] dma_dat_o,
output dma_wr_o // To memory
);
// Wire definitions
wire sck_rise, sck_fall, cs_rise, cs_fall, cs_active;
wire [7:0] outbound_data, inbound_data, status_reg;
wire inbound_empty, outbound_empty, outbound_full, inbound_full;
wire dma_rd, dma_reset_n;
// Inbound Registers
reg [7:0] rdr = 0;
// System vars
reg [2:0] track_sck = 3'd0, track_cs = 3'd0, track_mosi = 3'd0;
reg [2:0] cntr = 0;
reg slave_rdy = 0; // Slave ready register, active high
reg outbound_empty_reg = 1; // Register outbound because it obscures the last byte
reg rd = 0, wr = 0; // Read and write flags
reg first_write = 0; // Prevent a write happening when CS first goes low
reg clear_buffers; // Buffer reset flag
reg interrupt; // Interrupt flag
// Assignments ======================================================
// Track rise fall of two main signals
assign sck_rise = (track_sck[2:1] == 2'b01);
assign sck_fall = (track_sck[2:1] == 2'b10);
assign cs_rise = (track_cs[2:1] == 2'b01);
assign cs_fall = (track_cs[2:1] == 2'b10);
assign cs_active = !track_cs[1];
// Output assignments
assign slave_rdy_o = slave_rdy;
assign status_reg = {cs_i,2'b11,master_rdy_i,outbound_full,outbound_empty,inbound_full,inbound_empty};
assign interrupt_o = interrupt;
// Data output assignment
assign D_o = (A_i[0] == 0) ? inbound_data : status_reg; // Data register or status register based on LSB
// Module connections
// Inbound FIFO
fifo #(
.log2_addr(fifo_log2),
.data_width(8)
) inbound (
.n_reset_i(!clear_buffers & dma_reset_n), // Reset on request or DMA start
.clk_i(busclk_i),
.data_i(rdr),
.wr_i(wr),
.data_o(inbound_data),
.rd_i((!nRD_i & (A_i[0] == 0)) | dma_rd), // Read - when RD goes low
.fifo_empty_o(inbound_empty),
.fifo_full_o(inbound_full)
);
// Outbound FIFO
fifo #(
.log2_addr(fifo_log2),
.data_width(8)
) outbound (
.n_reset_i(!clear_buffers),
.clk_i(busclk_i),
.data_i(D_i),
.wr_i(!nWR_i & (A_i[0] == 0)), // Only write when addressing the outbound reg
.data_o(outbound_data),
.rd_i(rd),
.fifo_empty_o(outbound_empty),
.fifo_full_o(outbound_full)
);
// Track SCK
always @(posedge fast_clock_i)
track_sck <= {track_sck[1:0], sck_i};
// Track CS
always @(posedge fast_clock_i)
track_cs <= {track_cs[1:0], cs_i};
// Track MOSI into this clock domain
always @(posedge fast_clock_i)
track_mosi <= {track_mosi[1:0], mosi_i};
// Inbound shift registers
always @(posedge fast_clock_i)
begin
if( !cs_active )
cntr <= 3'd0;
else begin
if( sck_rise ) rdr <= {rdr[6:0],track_mosi[1]};
if( sck_fall ) cntr <= cntr + 3'd1;
end
end
// Detect a mid-cycle so the first_write flag can be reset
always @(negedge fast_clock_i)
begin
if( !cs_active ) first_write <= 1;
else
if( cntr == 3'd4 ) first_write <= 0;
end
// Write buffer handling
always @(negedge fast_clock_i) wr <= cs_active & (cntr==3'd7) & sck_fall & !first_write;
// Read buffer handling
always @(negedge fast_clock_i) rd <= (cs_active & (cntr==3'd7) & sck_fall) | cs_fall;
// Set the outbound data
assign miso_o = (!outbound_empty_reg) ? outbound_data[~cntr]: 1'b1;
// Need to register the empty flag because the read is at the start and sets the empty flag
// obscuring the last byte from transmission
always @(posedge rd) outbound_empty_reg = outbound_empty;
// ================================================================================
// Status/Data registers
// ================================================================================
reg [2:0] slow_cs;
always @(negedge busclk_i) slow_cs = {slow_cs[1:0],cs_i};
wire slow_rise = (slow_cs == 2'b01);
// Writing 0bxxxxxxx1 to address 1 will flag the device as ready
always @( posedge busclk_i )
begin
if( slow_rise )
slave_rdy <= 0;
else begin
if( !nWR_i & ( A_i[0] == 1'b1 ) )
slave_rdy <= D_i[0];
end
end
// Clear the buffers
reg [1:0] track_clear;
wire rs = !nWR_i & (A_i[0] == 1'b1) & D_i[7];
always @(negedge busclk_i) track_clear <= {track_clear[0],rs};
always @(posedge busclk_i) clear_buffers <= (track_clear == 2'b01);
// ================================================================================
// Interrupt line - registered
// ================================================================================
reg [7:0] old_reg = 0;
always @(negedge fast_clock_i) old_reg <= status_reg;
always @(posedge fast_clock_i) interrupt = (old_reg != status_reg);
// =============================================================
// Support memory DMA in from SPI - allows in-system programming
// =============================================================
support_dma support_dma(
.clk_i(/*fast_clock_i*/busclk_i),
.n_reset_o( dma_reset_n ),
.enable_i(dma_en_i),
.d_avail_i(!inbound_empty),
.data_i( inbound_data ),
.adr_o( dma_adr_o ),
.data_o( dma_dat_o ),
.wr_o(dma_wr_o),
.rd_o(dma_rd)
);
// =============================================================
endmodule
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM with byte enables
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
DO_R <= `BSV_ASSIGNMENT_DELAY DATA;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
end
`else
generate
genvar i;
for(i = 0; i < WE_WIDTH; i = i + 1) begin: porta_we
always @(posedge CLK) begin
if (EN) begin
if (WE[i]) begin
RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DI[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
end
else begin
DO_R[((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY RAM[ADDR][((i+1)*CHUNKSIZE)-1 : i*CHUNKSIZE];
end
end
end
end
endgenerate
`endif // !`ifdef __ICARUS__
// Output driver
always @(posedge CLK) begin
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule // BRAM1BE
|
#include <bits/stdc++.h> int main() { int i, j, l, x = 0; char s[100005]; gets(s); l = strlen(s); for (i = 0, j = l - 1; i < l / 2; i++, j--) { if (s[i] != s[j]) { x = 1; break; } } if (x == 1) { printf( NO n ); } else { for (i = 0; i < l; i++) { if (s[i] == A || s[i] == H || s[i] == I || s[i] == M || s[i] == O || s[i] == T || s[i] == U || s[i] == V || s[i] == W || s[i] == X || s[i] == Y ) { x = 0; } else { x = 1; break; } } if (x == 1) { printf( NO n ); } else { printf( YES n ); } } return 0; }
|
/*
-- ============================================================================
-- FILE NAME : bus_slave_mux.v
-- DESCRIPTION : oXX[u}`vNT
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "bus.h"
/********** W
[ **********/
module bus_slave_mux (
/********** `bvZNg **********/
input wire s0_cs_, // oXX[u0Ô
input wire s1_cs_, // oXX[u1Ô
input wire s2_cs_, // oXX[u2Ô
input wire s3_cs_, // oXX[u3Ô
input wire s4_cs_, // oXX[u4Ô
input wire s5_cs_, // oXX[u5Ô
input wire s6_cs_, // oXX[u6Ô
input wire s7_cs_, // oXX[u7Ô
/********** oXX[uM **********/
// oXX[u0Ô
input wire [`WordDataBus] s0_rd_data, // ÇÝoµf[^
input wire s0_rdy_, // fB
// oXX[u1Ô
input wire [`WordDataBus] s1_rd_data, // ÇÝoµf[^
input wire s1_rdy_, // fB
// oXX[u2Ô
input wire [`WordDataBus] s2_rd_data, // ÇÝoµf[^
input wire s2_rdy_, // fB
// oXX[u3Ô
input wire [`WordDataBus] s3_rd_data, // ÇÝoµf[^
input wire s3_rdy_, // fB
// oXX[u4Ô
input wire [`WordDataBus] s4_rd_data, // ÇÝoµf[^
input wire s4_rdy_, // fB
// oXX[u5Ô
input wire [`WordDataBus] s5_rd_data, // ÇÝoµf[^
input wire s5_rdy_, // fB
// oXX[u6Ô
input wire [`WordDataBus] s6_rd_data, // ÇÝoµf[^
input wire s6_rdy_, // fB
// oXX[u7Ô
input wire [`WordDataBus] s7_rd_data, // ÇÝoµf[^
input wire s7_rdy_, // fB
/********** oX}X^¤ÊM **********/
output reg [`WordDataBus] m_rd_data, // ÇÝoµf[^
output reg m_rdy_ // fB
);
/********** oXX[u}`vNT **********/
always @(*) begin
/* `bvZNgÉηéX[uÌIð */
if (s0_cs_ == `ENABLE_) begin // oXX[u0Ô
m_rd_data = s0_rd_data;
m_rdy_ = s0_rdy_;
end else if (s1_cs_ == `ENABLE_) begin // oXX[u1Ô
m_rd_data = s1_rd_data;
m_rdy_ = s1_rdy_;
end else if (s2_cs_ == `ENABLE_) begin // oXX[u2Ô
m_rd_data = s2_rd_data;
m_rdy_ = s2_rdy_;
end else if (s3_cs_ == `ENABLE_) begin // oXX[u3Ô
m_rd_data = s3_rd_data;
m_rdy_ = s3_rdy_;
end else if (s4_cs_ == `ENABLE_) begin // oXX[u4Ô
m_rd_data = s4_rd_data;
m_rdy_ = s4_rdy_;
end else if (s5_cs_ == `ENABLE_) begin // oXX[u5Ô
m_rd_data = s5_rd_data;
m_rdy_ = s5_rdy_;
end else if (s6_cs_ == `ENABLE_) begin // oXX[u6Ô
m_rd_data = s6_rd_data;
m_rdy_ = s6_rdy_;
end else if (s7_cs_ == `ENABLE_) begin // oXX[u7Ô
m_rd_data = s7_rd_data;
m_rdy_ = s7_rdy_;
end else begin // ftHgl
m_rd_data = `WORD_DATA_W'h0;
m_rdy_ = `DISABLE_;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_brams_7x.v
// Version : 1.3
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
//
// banks of brams are used for 1,2,4,8,18 brams
// brams are stacked for other values of NUM_BRAMS
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_brams_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
parameter TCQ = 1;
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
//synthesis translate_off
initial
begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_q;
reg [12:0] waddr_q;
reg [71:0] wdata_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
wen_q <= #TCQ 1'b0;
waddr_q <= #TCQ 13'b0;
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
// wdata_q <= #TCQ 72'b0;
end
else
begin
wen_q <= #TCQ wen;
waddr_q <= #TCQ waddr;
wdata_q <= #TCQ wdata;
end
end
assign wen_int = wen_q;
assign waddr_int = waddr_q;
assign wdata_int = wdata_q;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_q;
reg [12:0] raddr_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
ren_q <= #TCQ 1'b0;
raddr_q <= #TCQ 13'b0;
end
else
begin
ren_q <= #TCQ ren;
raddr_q <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_q;
assign raddr_int = raddr_q;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_q;
always @(posedge user_clk_i) begin
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
//if (reset_i)
//begin
// rdata_q <= #TCQ 72'b0;
//end
//else
//begin
rdata_q <= #TCQ rdata_int;
//end // else: !if(reset_i)
end
assign rdata = rdata_q;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar ii;
for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
pcie_7x_v1_3_pcie_bram_7x #(
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.IMPL_TARGET (IMPL_TARGET),
.DOB_REG (DOB_REG),
.WIDTH (WIDTH)
)
ram (
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.wen_i(wen_int),
.waddr_i(waddr_int),
.wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.ren_i(ren_int),
.raddr_i(raddr_int),
.rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.rce_i(rce)
);
end
endgenerate
endmodule // pcie_brams_7x
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long a[2000005]; long long sum[2000005]; int main() { long long m, n, i, j, k, ans = 0; cin >> m; for (i = 1; i <= m; i++) scanf( %lld , &a[i]); sort(a + 1, a + 1 + m); for (i = m; i >= 1; i--) sum[i] = sum[i + 1] + a[i]; for (i = 1; i <= m; i *= 4) { ans += sum[m - i + 1]; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void minn(T& a, T b) { if (a > b) a = b; } template <class T> void maxx(T& a, T b) { if (a < b) a = b; } void debug() { return; } template <class H, class... T> void debug(H a, T... b) { cerr << a; debug(b...); } void is() { return; } template <class H, class... T> void is(H& a, T&... b) { cin >> a; is(b...); } void os() { return; } template <class H, class... T> void os(H a, T... b) { cout << a; os(b...); } const int mod = 1e9 + 7; const int N = 2e5 + 5; int n, q; int nx[N], pr[N], nx100[N]; void sw(int x, int y) { swap(nx[x], nx[y]); pr[nx[x]] = x; pr[nx[y]] = y; int k = x; for (int i = 1; i <= 100; i++) k = pr[k]; for (int i = 1; i <= 105; i++) { nx100[k] = x; x = nx[x]; k = nx[k]; } k = y; for (int i = 1; i <= 100; i++) k = pr[k]; for (int i = 1; i <= 105; i++) { nx100[k] = y; y = nx[y]; k = nx[k]; } } void solve() { is(n, q); for (int i = 1; i <= n; i++) { is(nx[i]); pr[nx[i]] = i; } for (int i = 1; i <= n; i++) { int k = i; for (int j = 1; j <= 100; j++) { k = nx[k]; } nx100[i] = k; } while (q--) { int t, x, y; is(t, x, y); if (t == 2) { int k = x; while (y >= 100) { y -= 100; k = nx100[k]; } while (y--) k = nx[k]; os(k, n ); } else { sw(x, y); } } } signed main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int T = 1; while (T--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int n, m, a, b, fr, k1, k2; int dist[3005][3005]; bool flag[3005][3005]; vector<int> v[3005]; queue<int> q; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d %d , &a, &b); v[a].push_back(b); v[b].push_back(a); } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) dist[i][j] = 1e9; memset(flag, 1, sizeof(flag)); for (int k = 1; k <= n; k++) { while (!q.empty()) q.pop(); q.push(k); dist[k][k] = 0; while (!q.empty()) { fr = q.front(); q.pop(); flag[fr][fr] = false; for (int i = 0; i < v[fr].size(); i++) { if (flag[k][v[fr][i]]) { flag[k][v[fr][i]] = false; dist[k][v[fr][i]] = dist[k][fr] + 1; q.push(v[fr][i]); } } } } int s1, t1, l1, s2, t2, l2, ans = -1; scanf( %d %d %d , &s1, &t1, &l1); scanf( %d %d %d , &s2, &t2, &l2); for (int i = 1; i < n; i++) { for (int j = i + 1; j <= n; j++) { k1 = min(dist[s1][i] + dist[i][j] + dist[j][t1], dist[s1][j] + dist[i][j] + dist[i][t1]); k2 = min(dist[s2][i] + dist[i][j] + dist[j][t2], dist[s2][j] + dist[i][j] + dist[i][t2]); if (k1 <= l1 && k2 <= l2) { ans = max(ans, m - k1 - k2 + dist[i][j]); } } } if (dist[s1][t1] <= l1 && dist[s2][t2] <= l2) { ans = max(ans, m - dist[s1][t1] - dist[s2][t2]); } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = 2e5 + 5; int n, k, d, ansL = 1, ansR = 1, top1, top2; int a[MAXN], st1[MAXN], st2[MAXN]; map<int, int> lst; namespace SegmentTree { struct Tree { int l, r; int w, tag; } tree[MAXN << 2]; void update(int k) { tree[k].w = min(tree[k << 1].w, tree[k << 1 | 1].w); } void apply(int k, int val) { tree[k].w += val; tree[k].tag += val; } void down(int k) { if (tree[k].tag != 0) { apply(k << 1, tree[k].tag); apply(k << 1 | 1, tree[k].tag); tree[k].tag = 0; } } void Build(int k, int l, int r) { tree[k].l = l; tree[k].r = r; if (l == r) { tree[k].w = l; return; } int mid = (l + r) >> 1; Build(k << 1, l, mid); Build(k << 1 | 1, mid + 1, r); update(k); } void Modify(int k, int l, int r, int val) { if (tree[k].l >= l && tree[k].r <= r) { apply(k, val); return; } down(k); int mid = (tree[k].l + tree[k].r) >> 1; if (l <= mid) Modify(k << 1, l, r, val); if (r > mid) Modify(k << 1 | 1, l, r, val); update(k); } void Delete(int k, int x) { if (tree[k].l == tree[k].r) { tree[k].w = INF; return; } down(k); int mid = (tree[k].l + tree[k].r) >> 1; if (x <= mid) Delete(k << 1, x); else Delete(k << 1 | 1, x); update(k); } int Query(int k, int l, int r, int x) { if (tree[k].w > x) return INF; if (tree[k].l == tree[k].r) return tree[k].l; if (tree[k].l >= l && tree[k].r <= r) { down(k); if (tree[k << 1].w <= x) return Query(k << 1, l, r, x); else return Query(k << 1 | 1, l, r, x); } else { down(k); int mid = (tree[k].l + tree[k].r) >> 1; int res; if (l <= mid) { res = Query(k << 1, l, r, x); if (res != INF) return res; } if (r > mid) { res = Query(k << 1 | 1, l, r, x); if (res != INF) return res; } return -1; } } } // namespace SegmentTree int main() { scanf( %d%d%d , &n, &k, &d); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); a[i] += INF; } if (d == 0) { for (int i = 1; i <= n; i++) { int l = i; while (a[i] == a[i + 1] && i < n) i += 1; if (i - l + 1 > ansR - ansL + 1) { ansL = l; ansR = i; } } printf( %d %d n , ansL, ansR); return 0; } SegmentTree::Build(1, 1, n); int L = 1; for (int R = 1; R <= n; R++) { int tmp = L; if (a[R] % d == a[R - 1] % d) L = max(lst[a[R]] + 1, L); else L = R; lst[a[R]] = R; while (tmp < L) { SegmentTree::Delete(1, tmp); tmp += 1; } while (top1 && st1[top1] >= L && a[st1[top1]] >= a[R]) { SegmentTree::Modify(1, max(L, st1[top1 - 1] + 1), st1[top1], a[st1[top1]] / d); top1 -= 1; } SegmentTree::Modify(1, max(L, st1[top1] + 1), R, -a[R] / d); st1[++top1] = R; while (top2 && st2[top2] >= L && a[st2[top2]] <= a[R]) { SegmentTree::Modify(1, max(L, st2[top2 - 1] + 1), st2[top2], -a[st2[top2]] / d); top2 -= 1; } SegmentTree::Modify(1, max(L, st2[top2] + 1), R, a[R] / d); st2[++top2] = R; int pos = SegmentTree::Query(1, L, R, k + R); if (R - pos + 1 > ansR - ansL + 1) { ansL = pos; ansR = R; } } printf( %d %d n , ansL, ansR); return 0; }
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: VgaTiming
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module creates timing for vga
// VGA 640x480 60Hz 25.175MHz pixel clock, horizontal pulse - negative, vertical pulse - negative
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VgaTiming (
input wire pclk,
input wire rst,
output reg [9:0] hcount,
output reg hsync,
output reg [9:0] vcount,
output reg vsync,
output reg blnk
);
// localparam H_TOTAL_TIME = 1056;
// //localparam H_ADDR_TIME = 800;
// localparam H_BLNK_START = 800;
// //localparam H_BLNK_TIME = 160;
// localparam H_SYNC_START = 840;
// localparam H_SYNC_TIME = 128;
// localparam H_SYNC_POL = 1; //0 - negative, 1 - positive
// localparam V_TOTAL_TIME = 628;
// //localparam V_ADDR_TIME = 600;
// localparam V_BLNK_START = 600;
// //localparam V_BLNK_TIME = 28;
// localparam V_SYNC_START = 601;
// localparam V_SYNC_TIME = 4;
// localparam V_SYNC_POL = 1; //0 - negative, 1 - positive
localparam H_TOTAL_TIME = 800;
//localparam H_ADDR_TIME = 640;
localparam H_BLNK_START = 640;
//localparam H_BLNK_TIME = 160;
localparam H_SYNC_START = 656;
localparam H_SYNC_TIME = 96;
localparam H_SYNC_POL = 0; //0 - negative, 1 - positive
localparam V_TOTAL_TIME = 525;
//localparam V_ADDR_TIME = 480;
localparam V_BLNK_START = 480;
//localparam V_BLNK_TIME = 45;
localparam V_SYNC_START = 490;
localparam V_SYNC_TIME = 2;
localparam V_SYNC_POL = 0; //0 - negative, 1 - positive
reg [10:0] vcount_nxt;
reg vsync_nxt;
reg [10:0] hcount_nxt;
reg hsync_nxt;
reg vblnk, hblnk;
reg vblnk_nxt, hblnk_nxt;
always @(posedge pclk or posedge rst) begin
if (rst) begin
hcount <= #1 0;
hsync <= #1 0;
vcount <= #1 0;
vsync <= #1 0;
hblnk <= #1 0;
vblnk <= #1 0;
end
else begin
hcount <= #1 hcount_nxt;
hsync <= #1 hsync_nxt;
vcount <= #1 vcount_nxt;
vsync <= #1 vsync_nxt;
hblnk <= #1 hblnk_nxt;
vblnk <= #1 vblnk_nxt;
end
end
always @* begin
blnk = ~(hblnk | vblnk);
end
always @* begin
//horizontal
if(hcount==H_BLNK_START - 1) begin
hcount_nxt = hcount+1;
if(H_SYNC_POL) hsync_nxt=0;
else hsync_nxt = 1;
hblnk_nxt=1;
end
else if(hcount==H_SYNC_START - 1) begin
hcount_nxt = hcount+1;
if(H_SYNC_POL) hsync_nxt=1;
else hsync_nxt = 0;
hblnk_nxt=1;
end
else if (hcount==H_SYNC_START + H_SYNC_TIME - 1) begin
hcount_nxt = hcount+1;
if(H_SYNC_POL) hsync_nxt=0;
else hsync_nxt = 1;
hblnk_nxt=1;
end
else if (hcount==H_TOTAL_TIME - 1) begin
hcount_nxt = 0;
if(H_SYNC_POL) hsync_nxt=0;
else hsync_nxt = 1;
hblnk_nxt=0;
end
else begin
hcount_nxt = hcount+1;
hsync_nxt = hsync;
hblnk_nxt = hblnk;
end
//vertical
if(hcount==H_TOTAL_TIME - 1) begin
if(vcount==V_BLNK_START - 1) begin
vcount_nxt = vcount+1;
if(V_SYNC_POL) vsync_nxt=0;
else vsync_nxt = 1;
vblnk_nxt=1;
end
else if (vcount==V_SYNC_START - 1) begin
vcount_nxt = vcount+1;
if(V_SYNC_POL) vsync_nxt=1;
else vsync_nxt = 0;
vblnk_nxt = 1;
end
else if (vcount==V_SYNC_START + V_SYNC_TIME - 1) begin
vcount_nxt = vcount+1;
if(V_SYNC_POL) vsync_nxt=0;
else vsync_nxt = 1;
vblnk_nxt = 1;
end
else if (vcount==V_TOTAL_TIME - 1) begin
vcount_nxt = 0;
if(V_SYNC_POL) vsync_nxt=0;
else vsync_nxt = 1;
vblnk_nxt = 0;
end
else begin
vcount_nxt = vcount+1;
vsync_nxt = vsync;
vblnk_nxt = vblnk;
end
end
else begin
vcount_nxt = vcount;
vsync_nxt = vsync;
vblnk_nxt = vblnk;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sin_taylor_seriescud
#(parameter
ID = 5,
NUM_STAGE = 6,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
//------------------------Instantiation------------------
sin_taylor_series_ap_sitodp_4_no_dsp_32 sin_taylor_series_ap_sitodp_4_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); int c = 0; for (int i = 0; i < n; i++) { if (i == 0 && a[0] > 0) { c++; } if (i > 0 && a[i] != 0 && a[i] != a[i - 1]) { c++; } } cout << c << endl; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd3;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
read_safe_counter <= 3'd5;
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 3'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 3'd4;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 3'd1;
end
end
end
reg [1:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 2'd0;
end else begin
if(write)
counter_writedirection <= 2'd3;
else if(|counter_writedirection)
counter_writedirection <= counter_writedirection - 2'd1;
end
end
reg direction0;
always @(posedge sys_clk) begin
direction0 <= ~(write | (|counter_writedirection));
direction <= direction0;
end
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]), .precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule
|
#include <bits/stdc++.h> double p[1010][1010]; int a[1010]; int n, m; int main() { double t, ans; int i, j, x, y; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) if (a[i] > a[j]) p[i][j] = 1; else p[i][j] = 0; for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); p[x][y] = 0.5; p[y][x] = 0.5; for (j = 1; j <= n; j++) if ((j != x) && (j != y)) { t = (p[j][x] + p[j][y]) * 0.5; p[j][x] = t; p[x][j] = 1 - t; p[j][y] = t; p[y][j] = 1 - t; } } ans = 0; for (i = 1; i <= n - 1; i++) for (j = i + 1; j <= n; j++) ans += p[i][j]; printf( %.10lf n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int abs(int a, int b) { if (a > b) return a - b; else return b - a; } int main() { int n, c, i, b, count = 0, index1 = 1, index2 = 1, flag = 0; cin >> n >> c; char *s; s = new char[n + 2]; for (i = 1; i <= n; i++) { cin >> s[i]; } int *d = new int[n + 1]; for (i = 1; i <= n / 2; i++) { b = abs((int)s[i], (int)s[n - i + 1]); if (b < 13) d[i] = d[n - i + 1] = b; else d[i] = d[n - i + 1] = 26 - b; } if (c > n / 2) c = 1 + n - c; for (i = 1; i <= n / 2; i++) { if (d[i] > 0) { index1 = i; break; } } for (i = n / 2; i >= 1; i--) { if (d[i] > 0) { index2 = i; flag = 1; break; } } if (c <= index1) { count = index2 - c; } else if (c <= index2) { if (c - index1 > index2 - c) count = 2 * (index2 - c) + c - index1; else count = 2 * (c - index1) + index2 - c; } else count = c - index1; for (i = index1; i <= index2; i++) { count += d[i]; } if (flag == 1) cout << count; else cout << 0; return 0; }
|
// $Id: c_shift_reg.v 1621 2009-10-28 04:33:50Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// shift register
module c_shift_reg
(clk, reset, enable, data_in, data_out);
`include "c_constants.v"
// width of register
parameter width = 32;
// depth of register (number of levels)
parameter depth = 2;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// perform shift
input enable;
// data input
input [0:width-1] data_in;
// data output
output [0:width-1] data_out;
wire [0:width-1] data_out;
genvar level;
wire [0:(depth+1)*width-1] data;
assign data[0:width-1] = data_in;
generate
for(level = 0; level < depth; level = level + 1)
begin:levels
wire [0:width-1] data_s, data_q;
assign data_s
= enable ? data[level*width:(level+1)*width-1] : data_q;
c_dff
#(.width(width),
.reset_type(reset_type))
dataq
(.clk(clk),
.reset(reset),
.d(data_s),
.q(data_q));
assign data[(level+1)*width:(level+2)*width-1] = data_q;
end
endgenerate
assign data_out = data[depth*width:(depth+1)*width-1];
endmodule
|
#include <bits/stdc++.h> const long long mod = 1e9 + 7; using namespace std; vector<int> par, rnk; void make_set(int n) { par[n] = n; rnk[n] = 0; } int find_set(int a) { if (par[a] == a) return a; return par[a] = find_set(par[a]); } void union_set(int a, int b) { a = find_set(a); b = find_set(b); if (a == b) return; if (rnk[a] > rnk[b]) { par[b] = a; } else if (rnk[a] < rnk[b]) { par[a] = b; } else { par[b] = a; rnk[a]++; } } void solve() { int n, a, b; cin >> n >> a >> b; par.assign(n, 0); rnk.assign(n, 0); if (a != 1 && b != 1) { cout << NO n ; return; } if (a == 1 && b == 1) { if (n == 2 || n == 3) { cout << NO n ; return; } cout << YES n ; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (abs(i - j) == 1) cout << 1 ; else cout << 0 ; } cout << endl; } return; } for (int i = 0; i < n; i++) make_set(i); for (int i = 0; i < n - (max(a, b)); i++) { union_set(i, i + 1); } int flag = 0; if (a > 1) flag = 1; cout << YES n ; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) cout << 0 ; else if (flag) { if (find_set(i) == find_set(j)) cout << 1 ; else cout << 0 ; } else { if (find_set(i) != find_set(j)) cout << 1 ; else cout << 0 ; } } cout << endl; } } int main() { int t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; int v1[10], v2[10]; int main() { memset(v1, 0, sizeof(v1)); memset(v2, 0, sizeof(v2)); int n; scanf( %d , &n); for (int i = 0, a; i < n; i++) { scanf( %d , &a); v1[a]++; } for (int i = 0, a; i < n; i++) { scanf( %d , &a); v2[a]++; } int ans = 0; bool flag = true; for (int i = 1; i <= 5 && flag; i++) { if ((v1[i] + v2[i]) & 1) { flag = false; } ans += abs(v1[i] - v2[i]) / 2; } if (flag) printf( %d n , ans / 2); else { printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long T, n, tempur; int t[105], l[105], h[105]; int main() { cin >> T; while (T--) { memset(t, 0, sizeof t); memset(h, 0, sizeof h); memset(l, 0, sizeof l); cin >> n >> tempur; int maxn = tempur, minn = tempur; for (int i = 1; i <= n; i++) { cin >> t[i] >> l[i] >> h[i]; } int f = 0; for (int i = 1; i <= n; i++) { maxn += t[i] - t[i - 1]; minn -= t[i] - t[i - 1]; if ((h[i] >= minn && l[i] <= maxn) || (h[i] <= maxn && l[i] >= minn)) { maxn = min(maxn, h[i]); minn = max(minn, l[i]); } else { f = 1; break; } } if (!f) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, m; cin >> n >> m; char t[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> t[i][j]; } } bool check = true; int count = 0, r, l; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (t[i][j] == B ) { count++; if (check) { l = j; check = false; } } } if (count) { r = i + 1 + count / 2; l = l + 1 + count / 2; cout << r << << l; return 0; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; const int MOD = 998244353; int fact[N], factinv[N]; int lgcput(int b, int p) { int a = 1; while (p) { if (p & 1) { a = (1LL * a * b) % MOD; } b = (1LL * b * b) % MOD; p /= 2; } return a; } int inv(int x) { return lgcput(x, MOD - 2); } int main() { int n, k; cin >> n >> k; fact[0] = factinv[0] = 1; for (int i = 1; i <= n; i++) { fact[i] = (1LL * i * fact[i - 1]) % MOD; factinv[i] = (1LL * inv(i) * factinv[i - 1]) % MOD; } int c = n - k; if (k >= n) { cout << 0 ; return 0; } int ans = 0; for (int i = 0; i <= c; i++) { int dead = (1LL * ((1LL * ((1LL * fact[c] * factinv[i]) % MOD) * factinv[c - i]) % MOD) * lgcput(c - i, n)) % MOD; if (i & 1) ans -= dead; else ans += dead; if (ans < 0) ans += MOD; if (ans >= MOD) ans -= MOD; } ans = (1LL * (1LL * (1LL * ans * fact[n] % MOD) * factinv[c] % MOD) * factinv[n - c]) % MOD; if (k == 0) { cout << ans; return 0; } ans *= 2; ans %= MOD; cout << ans; return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fast_spi_rx_core #(
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001
) (
input wire SCLK,
input wire SDI,
input wire SEN,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 0;
//output format #ID (as parameter IDENTIFIER + 12 id-frame + 16 bit data)
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
end
end
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SCLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire CONF_EN_SYNC;
assign CONF_EN_SYNC = CONF_EN;
reg [7:0] sync_cnt;
always @(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
reg [11:0] frame_cnt;
wire SEN_START, SEN_FINISH;
reg SEN_DLY;
always @(posedge SCLK) begin
SEN_DLY <= SEN;
end
assign SEN_START = (SEN_DLY ==0 && SEN == 1);
assign SEN_FINISH = (SEN_DLY ==1 && SEN == 0);
always @(posedge SCLK) begin
if(RST_SYNC)
frame_cnt <= 0;
else if(SEN_FINISH && CONF_EN_SYNC)
frame_cnt <= frame_cnt + 1;
end
wire cdc_fifo_write;
reg [4:0] bit_cnt;
always @(posedge SCLK) begin
if(RST_SYNC | SEN_START)
bit_cnt <= 0;
else if(cdc_fifo_write)
bit_cnt <= 0;
else if(SEN)
bit_cnt <= bit_cnt + 1;
end
assign cdc_fifo_write = ( (bit_cnt == 15) || SEN_FINISH ) && CONF_EN_SYNC;
reg [15:0] spi_data;
always @(posedge SCLK) begin
if(RST_SYNC | SEN_FINISH)
spi_data <= 0;
else if(cdc_fifo_write)
spi_data <= {15'b0, SDI};
else if(SEN)
spi_data <= {spi_data[14:0], SDI};
end
wire fifo_full,cdc_fifo_empty;
wire wfull;
always @(posedge SCLK) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != 8'b1111_1111)
LOST_DATA_CNT <= LOST_DATA_CNT + 1;
end
wire [31:0] cdc_data;
assign cdc_data = {IDENTIFIER, frame_cnt[11:0], spi_data};
wire [31:0] cdc_data_out;
cdc_syncfifo #(
.DSIZE(32),
.ASIZE(2)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data),
.winc(cdc_fifo_write),
.wclk(SCLK),
.wrst(RST_LONG),
.rinc(!fifo_full),
.rclk(BUS_CLK),
.rrst(RST_LONG)
);
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(1024)
) fifo_i (
.clk(BUS_CLK),
.reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]),
.size()
);
//assign FIFO_DATA[31:30] = 0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim
( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
parameter bw = 16;
parameter N = 4;
parameter log2_of_max_rate = 7;
parameter maxbitgain = N * log2_of_max_rate;
input clock;
input reset;
input enable;
input [7:0] rate;
input strobe_in,strobe_out;
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
wire [bw-1:0] signal_out_unreg;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
reg [bw+maxbitgain-1:0] sampler;
integer i;
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
always @(posedge clock)
if(reset)
for(i=0;i<N;i=i+1)
integrator[i] <= #1 0;
else if (enable && strobe_in)
begin
integrator[0] <= #1 integrator[0] + signal_in_ext;
for(i=1;i<N;i=i+1)
integrator[i] <= #1 integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset)
begin
sampler <= #1 0;
for(i=0;i<N;i=i+1)
begin
pipeline[i] <= #1 0;
differentiator[i] <= #1 0;
end
end
else if (enable && strobe_out)
begin
sampler <= #1 integrator[N-1];
differentiator[0] <= #1 sampler;
pipeline[0] <= #1 sampler - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= #1 pipeline[i-1];
pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
end
end // if (enable && strobe_out)
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
always @(posedge clock)
signal_out <= #1 signal_out_unreg;
endmodule // cic_decim
|
#include <bits/stdc++.h> using namespace std; string op; bool check(int l, int r) { char c; cout << ? << l << << r << endl; cin >> c; return c == x ; } int main() { while (cin >> op) { if (op == end ) { return 0; } int l = 1, r = 2; while (1) { if (check(l, r)) break; l <<= 1, r <<= 1; } while (l + 1 < r) { int mid = (l + r) >> 1; if (check(l - 1, mid)) r = mid; else l = mid + 1; } if (l == 1 && r == 2) { if (check(2, 3)) cout << ! 1 << endl; else cout << ! 2 << endl; } else { if (l == r) cout << ! << l << endl; else { if (check(l, l + 1)) cout << ! << l + 1 << endl; else cout << ! << l << endl; } } } }
|
`ifndef _MUX
`define _MUX
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module mux16x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x2(data0, data1, selectInput, out); // 2-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1;
input selectInput;
always@(data0 or data1 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
endcase
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int N = 200001; long long a[N + 1], tree[4 * N], lazy[4 * N]; void build(int idx, int l, int r) { if (l == r) tree[idx] = a[l]; else { int m = (l + r) / 2; build(2 * idx, l, m); build(2 * idx + 1, m + 1, r); tree[idx] = min(tree[2 * idx], tree[2 * idx + 1]); } } void push(int idx) { tree[2 * idx] += lazy[idx]; lazy[2 * idx] += lazy[idx]; tree[2 * idx + 1] += lazy[idx]; lazy[2 * idx + 1] += lazy[idx]; lazy[idx] = 0; } void update(int idx, int l, int r, int ql, int qr, long long val) { if (ql > qr) return; if (l == ql && r == qr) { tree[idx] += val; lazy[idx] += val; } else { push(idx); int m = (l + r) / 2; update(2 * idx, l, m, ql, min(qr, m), val); update(2 * idx + 1, m + 1, r, max(ql, m + 1), qr, val); tree[idx] = min(tree[2 * idx], tree[2 * idx + 1]); } } long long query(int idx, int l, int r, int ql, int qr) { if (ql > qr) return 1000000000000000000; if (l == ql && r == qr) return tree[idx]; else { push(idx); int m = (l + r) / 2; return min(query(2 * idx, l, m, ql, min(qr, m)), query(2 * idx + 1, m + 1, r, max(ql, m + 1), qr)); } } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); build(1, 1, n); int m; scanf( %d , &m); while (m--) { char c[105]; fgets(c, 100, stdin); int id = 0; long long now[3], temp = 0; bool b = 0; for (int i = 0;; i++) { if (c[i] == - ) { b = 1; continue; } if (c[i] == || c[i] == n ) { now[id++] = temp; temp = 0; } else temp = 10 * temp + (c[i] - 0 ); if (c[i] == n ) break; } if (b) now[2] *= -1; now[0]++; now[1]++; if (id == 2) { long long res; if (now[0] <= now[1]) res = query(1, 1, n, now[0], now[1]); else res = min(query(1, 1, n, 1, now[1]), query(1, 1, n, now[0], n)); printf( %I64d n , res); } else { if (now[0] <= now[1]) update(1, 1, n, now[0], now[1], now[2]); else { update(1, 1, n, 1, now[1], now[2]); update(1, 1, n, now[0], n, now[2]); } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long n, p, a[N], C[N], st, End; void in() { cin >> n >> p; for (long long i = 0; i <= n - 1; i++) cin >> a[i]; sort(a, a + n); } long long bns(long long lim) { long long low = 0, high = n - 1, res = -1; while (low <= high) { long long mid = (low + high) / 2; if (a[mid] <= lim) low = mid + 1, res = mid; else high = mid - 1; } return res + 1; } long long bns_low() { long long low = 1, high = 1e15, res = -1; while (low <= high) { long long mid = (low + high) / 2; bool kq = true; for (long long i = 0; i <= n - 1; i++) if (mid + i >= a[i]) ; else kq = false; if (kq) high = mid - 1, res = mid; else low = mid + 1; } return res; } long long bns_high() { long long low = st, high = 1e15, res = -1; while (low <= high) { long long mid = (low + high) / 2; bool kq = true; for (long long i = 0; i <= n - 1; i++) { C[i] = bns(i + mid) - i; if (C[i] <= 0 || C[i] >= p) kq = false; } if (kq) low = mid + 1, res = mid; else high = mid - 1; } return res; } void process() { st = bns_low(); End = bns_high(); if (st == -1 || End == -1) { cout << 0; exit(0); } cout << End - st + 1 << n ; for (long long i = st; i <= End; i++) cout << i << ; } int main() { if (fopen( trash.inp , r )) freopen( trash.inp , r , stdin), freopen( trash.out , w , stdout); ios ::sync_with_stdio(0), cin.tie(0), cout.tie(0); in(); process(); }
|
#include <bits/stdc++.h> using namespace std; using INT = long long; int n; int a[200010]; vector<int> B[200010]; void add(int u, int val) { for (; u <= n; u += u & -u) B[u].push_back(val); } int calc(int u, int val) { int ans = 0; for (; u; u -= u & -u) { int id = lower_bound(B[u].begin(), B[u].end(), val) - B[u].begin(); ans += B[u].size() - id; } return ans; } int calc(int l, int r, int val) { if (l > r) return 0; return calc(r, val) - calc(l - 1, val); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) add(i, min(a[i], n)); for (int i = 1; i <= n; i++) sort(B[i].begin(), B[i].end()); INT ans = 0; for (int i = 1; i < n; i++) { ans += calc(i + 1, min(n, a[i]), i); } cout << ans << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:35 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: channel_error_detect.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANNEL_ERROR_DETECT
//
//
// Description: the CHANNEL_ERROR_DETECT module monitors the error signals
// from the Aurora Lanes in the channel. If one or more errors
// are detected, the error is reported as a channel error. If
// a hard error is detected, it sends a message to the channel
// initialization state machine to reset the channel.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_201_CHANNEL_ERROR_DETECT
(
// Aurora Lane Interface
SOFT_ERROR,
HARD_ERROR,
LANE_UP,
// System Interface
USER_CLK,
POWER_DOWN,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR,
// Channel Init SM Interface
RESET_CHANNEL
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input SOFT_ERROR;
input HARD_ERROR;
input LANE_UP;
//System Interface
input USER_CLK;
input POWER_DOWN;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//Channel Init SM Interface
output RESET_CHANNEL;
//*****************************External Register Declarations*************************
reg CHANNEL_SOFT_ERROR;
reg CHANNEL_HARD_ERROR;
reg RESET_CHANNEL;
//***************************Internal Register Declarations***************************
reg soft_error_r;
reg hard_error_r;
//*********************************Wire Declarations**********************************
wire channel_soft_error_c;
wire channel_hard_error_c;
wire reset_channel_c;
//*********************************Main Body of Code**********************************
// Register all of the incoming error signals. This is neccessary for timing.
always @(posedge USER_CLK)
begin
soft_error_r <= `DLY SOFT_ERROR;
hard_error_r <= `DLY HARD_ERROR;
end
// Assert Channel soft error if any of the soft error signals are asserted.
initial
CHANNEL_SOFT_ERROR = 1'b1;
assign channel_soft_error_c = soft_error_r;
always @(posedge USER_CLK)
CHANNEL_SOFT_ERROR <= `DLY channel_soft_error_c;
// Assert Channel hard error if any of the hard error signals are asserted.
initial
CHANNEL_HARD_ERROR = 1'b1;
assign channel_hard_error_c = hard_error_r;
always @(posedge USER_CLK)
CHANNEL_HARD_ERROR <= `DLY channel_hard_error_c;
// "reset_channel_r" is asserted when any of the LANE_UP signals are low.
initial
RESET_CHANNEL = 1'b1;
assign reset_channel_c = !LANE_UP;
always @(posedge USER_CLK)
RESET_CHANNEL <= `DLY reset_channel_c | POWER_DOWN;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, w, s, a[110]; int in[110], out[110]; int main() { scanf( %d%d , &n, &w); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); s += a[i]; } if (n == 1 && w == a[0]) { puts( Yes ); for (int i = 0; i < w * 2; i++) { printf( 1 ); } } else if (n >= 2 && w >= 2 && w <= s) { in[0] = a[0] - 1; in[1] = a[1] - 1; for (int i = 2; i < n; i++) { in[i] = a[i]; } for (int i = 0; i < n; i++) { int x = min(w - 2, in[i]); in[i] -= x; out[i] += x; w -= x; } puts( Yes ); for (int i = 0; i < n; i++) { for (int j = 0; j < out[i] * 2; j++) { printf( %d , i + 1); } } printf( 1 ); for (int i = 1; i < n; i++) { for (int j = 0; j < in[i] * 2; j++) { printf( %d , i + 1); } } printf( 1 2 ); for (int i = 0; i < in[0] * 2; i++) { printf( 1 ); } puts( 2 ); } else if (n >= 2 && w == 1) { int k = 0; while (k < n && a[k] != 1) { k++; } if (k == n) { puts( No ); } else { puts( Yes ); printf( %d , k + 1); for (int i = 0; i < n; i++) { if (i == k) { continue; } for (int j = 0; j < a[i] * 2; j++) { printf( %d , i + 1); } } printf( %d n , k + 1); } } else { puts( No ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, tot; long long ans, sum; char s[100010], t[100010]; void print(int x, int opt) { tot++; printf( %d %d n , x, opt); if (tot == 100000) exit(0); } bool check(int i, int opt) { if (i == n) return 0; if (opt == -1) { if (s[i + 1] > 0 ) return s[i]--, s[i + 1]--, print(i, -1), 1; if (check(i + 1, 1)) return s[i]--, s[i + 1]--, print(i, -1), 1; return 0; } if (opt == 1) { if (s[i + 1] < 9 ) return s[i]++, s[i + 1]++, print(i, 1), 1; if (check(i + 1, -1)) return s[i]++, s[i + 1]++, print(i, 1), 1; return 0; } } int main() { scanf( %d%s%s , &n, s + 1, t + 1); for (int i = 1; i < n; i++) { int S = sum + s[i] - a , T = t[i] - a ; ans += abs(S - T), sum = T - S; } if (sum + s[n] - a != t[n] - a ) return puts( -1 ), 0; printf( %lld n , ans); for (int i = 1; i < n; i++) { while (s[i] > t[i]) if (!check(i, -1)) return puts( -1 ), 0; while (s[i] < t[i]) if (!check(i, 1)) return puts( -1 ), 0; } return 0; }
|
module RegisterTestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] test_in;
reg test_clk,test_reset,test_load;
wire [31:0] test_out;
Register test_reg(.IN(test_in),
.Clk(test_clk),
.Reset(test_reset),
.Load(test_load),
.OUT(test_out));
reg Clk,Reset;
/*
generate
genvar i;
for (i=0; i<15; i=i+1) begin : dff
custom i_custom(
.clk(clk)
,.input(DFF_i[i])
,.output(DFF_o[i])
);
end
endgenerate
*/
initial fork
test_in=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ;
#1 test_in=1; #1 test_clk=1 ; #1 test_reset=0 ; #1 test_load=1 ;
#2 test_in=1; #2 test_clk=0 ; #2 test_reset=0 ; #2 test_load=1 ;
#3 test_in=0; #3 test_clk=1 ; #3 test_reset=0 ; #3 test_load=0 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish; //Especifica cuando termina la simulacion
initial begin
$dumpfile("RegisterTestBench.vcd");
$dumpvars(0,RegisterTestBench);
$display(" Test Results" ); // imprime header
$monitor("T = %d,test_out = %d,test_in = %d,test_clk = %d,test_reset = %d,test_load = %d",$time,test_out,test_in,test_clk,test_reset,test_load ); //imprime se~ales
end
endmodule
//iverilog Register.v RegisterTestBench.v
//gtkwave RegisterTestBench.vcd
|
#include <bits/stdc++.h> using namespace std; using LL = long long; const int N = 100005; LL a[N]; int main() { int t; scanf( %d , &t); while (t--) { int n; LL sum = 0; LL x; scanf( %d%lld , &n, &x); LL q = n; for (int i = 1; i <= n; ++i) { scanf( %lld , &a[i]); sum += a[i]; } sort(a + 1, a + n + 1); bool flag = true; for (int i = 1; i <= n; ++i) { if (sum * 1.0 / q * 1.0 >= x * 1.0) { printf( %lld n , q); flag = false; break; } sum -= a[i], --q; } if (flag) printf( %lld n , q); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, l[N], r[N], id[N]; bool cmp(int x, int y) { return r[x] == r[y] ? l[x] < l[y] : r[x] < r[y]; } int main() { cin >> n; for (int x, w, i = 1; i <= n; ++i) { cin >> x >> w; l[i] = x - w, r[i] = x + w, id[i] = i; } sort(id + 1, id + n + 1, cmp); int ans = 0, las = -2e9; for (int i = 1; i <= n; ++i) if (las <= l[id[i]]) ++ans, las = r[id[i]]; cout << ans; return 0; }
|
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