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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input in; // inputs don't get flagged as undriven
output out; // outputs don't get flagged as unused
sub sub ();
// Check we don't warn about unused UDP signals
udp_mux2 udpsub (out, in, in, in);
// Check ignoreds mark as used
reg sysused;
initial $bboxed(sysused);
// Check file IO. The fopen is the "driver" all else a usage.
integer infile;
integer outfile;
initial begin
outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w");
$fwrite(outfile, "1\n");
$fclose(outfile);
infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "r");
if ($fgetc(infile) != "1") begin end
end
wire _unused_ok;
endmodule
module sub;
wire pub /*verilator public*/; // Ignore publics
endmodule
primitive udp_mux2 (q, a, b, s);
output q;
input a, b, s;
table
//a b s : out
1 ? 0 : 1 ;
0 ? 0 : 0 ;
? 1 1 : 1 ;
? 0 1 : 0 ;
0 0 x : 0 ;
1 1 x : 1 ;
endtable
endprimitive
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_FUNCTIONAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx2mb.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* ccx2mb.v: An interface that connects the CCX interface of the SPARC
* core with the MicroBlaze FSL FIFO. This block contains an
* interface for each direction:
* 1. A processor/cache interface (PCX) to FSL block.
* 2. An FSL to cache/processor interface (CPX) block.
*
* $Id: $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module ccx2mb (
// Outputs
pcx_spc_grant_px,
pcx_fsl_m_control,
pcx_fsl_m_data,
pcx_fsl_m_write,
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2,
cpx_fsl_s_read,
// Inputs
gclk,
reset_l,
spc_pcx_data_pa,
spc_pcx_atom_pq,
spc_pcx_req_pq,
fsl_pcx_m_full,
fsl_cpx_s_exists,
fsl_cpx_s_control,
fsl_cpx_s_data
);
parameter C_EXT_RESET_HIGH = 0;
//=============================================
// Outputs
// SPARC/PCX interface
output [4:0] pcx_spc_grant_px;
// PCX/FSL interface
output pcx_fsl_m_control;
output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
output pcx_fsl_m_write;
// SPARC/CPX interface
output cpx_spc_data_rdy_cx2;
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
// MicroBlaze FSL Interface
output cpx_fsl_s_read;
//=============================================
// Inputs
input gclk;
input reset_l;
// SPARC/PCX interface
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input spc_pcx_atom_pq;
input [4:0] spc_pcx_req_pq;
// PCX/FSL interface
input fsl_pcx_m_full;
// MicroBlaze FSL Interface
input fsl_cpx_s_exists;
input fsl_cpx_s_control;
input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;
//=============================================
// Wire definitions for outputs
// SPARC/PCX interface
wire [4:0] pcx_spc_grant_px;
// PCX/FSL interface
wire pcx_fsl_m_control;
wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
wire pcx_fsl_m_write;
// SPARC/CPX interface
wire cpx_spc_data_rdy_cx2;
wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
// MicroBlaze FSL Interface
wire cpx_fsl_s_read;
wire reset_l_int;
reg reset_l_sync;
reg sync;
// Synchronize the incoming reset net into the gclk domain
always @(posedge gclk) begin
{reset_l_sync, sync} <= {sync, reset_l};
end
assign reset_l_int = C_EXT_RESET_HIGH ? ~reset_l_sync : reset_l_sync;
//=============================================
// Do we need to put a clock cluster header here?
// For now, we will have no clock gating.
wire rclk;
assign rclk = gclk;
//=============================================
// Instantiate pcx2mb
pcx2mb pcx (
// Outputs
.pcx_spc_grant_px(pcx_spc_grant_px),
.pcx_fsl_m_control(pcx_fsl_m_control),
.pcx_fsl_m_data(pcx_fsl_m_data),
.pcx_fsl_m_write(pcx_fsl_m_write),
// Inputs
.rclk(rclk),
.reset_l(reset_l_int),
.spc_pcx_data_pa(spc_pcx_data_pa),
.spc_pcx_atom_pq(spc_pcx_atom_pq),
.spc_pcx_req_pq(spc_pcx_req_pq),
.fsl_pcx_m_full(fsl_pcx_m_full)
);
//=============================================
// Instantiate mb2cpx
mb2cpx cpx (
// Outputs
.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2(cpx_spc_data_cx2),
.cpx_fsl_s_read(cpx_fsl_s_read),
// Inputs
.rclk(rclk),
.reset_l(reset_l_int),
.fsl_cpx_s_exists(fsl_cpx_s_exists),
.fsl_cpx_s_control(fsl_cpx_s_control),
.fsl_cpx_s_data(fsl_cpx_s_data)
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:100000000 ) using namespace std; const int N = 155; const int INF = 1000000000; struct Edge { int to, flow, cap, cost; Edge() {} Edge(int to, int flow, int cap, int cost) : to(to), flow(flow), cap(cap), cost(cost) {} }; vector<Edge> g[N]; void add_edge(int from, int to, int cap, int cost) { g[from].push_back(Edge(to, 0, cap, cost)); g[to].push_back(Edge(from, cap, cap, -cost)); } int* count_letters(string s) { int* a = new int[26]; memset(a, 0, 26 * sizeof(int)); for (int(i) = 0; (i) < ((int)(s).size()); (i)++) a[s[i] - a ]++; return a; } int d[N], p[N], id[N]; void find_flow(int src, int goal, int need) { int flow = 0, n = goal + 1, cost = 0; while (flow < need) { for (int(i) = 0; (i) < (n); (i)++) d[i] = INF, p[i] = id[i] = -1; d[src] = 0; for (int(i) = 0; (i) < (n - 1); (i)++) { for (int(a) = 0; (a) < (n); (a)++) { for (int(j) = 0; (j) < ((int)(g[a]).size()); (j)++) { int b = g[a][j].to; if (g[a][j].flow < g[a][j].cap && d[b] > d[a] + g[a][j].cost) { d[b] = d[a] + g[a][j].cost; p[b] = a; id[b] = j; } } } } if (d[goal] == INF) { puts( -1 ); return; } int push = INF, cur = goal; while (cur != src) { push = min(push, g[p[cur]][id[cur]].cap - g[p[cur]][id[cur]].flow); cur = p[cur]; } cur = goal; flow += push; while (cur != src) { g[p[cur]][id[cur]].flow += push; cost += push * g[p[cur]][id[cur]].cost; for (int(i) = 0; (i) < ((int)(g[cur]).size()); (i)++) { if (g[cur][i].to == p[cur]) { g[cur][i].flow -= push; break; } } cur = p[cur]; } } printf( %d n , cost); } int main() { string t; cin >> t; int* a = count_letters(t); int n; cin >> n; for (int(i) = 0; (i) < (26); (i)++) add_edge(n + 1 + i, n + 27, a[i], 0); for (int(i) = 0; (i) < (n); (i)++) { string s; int cap; cin >> s >> cap; int* b = count_letters(s); add_edge(0, i + 1, cap, i + 1); for (int(j) = 0; (j) < (26); (j)++) add_edge(i + 1, n + 1 + j, b[j], 0); } find_flow(0, n + 27, (int)(t).size()); return 0; }
|
// --------------------------------------------------------------------
// Copyright (c) 2010 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: Master Controller Module for extern PLL.
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Rosaline Lin :| 10/03/31 :| Initial Revision
// --------------------------------------------------------------------
module ext_pll_ctrl
(
// system input
osc_50,
rstn,
// device 1
clk1_set_wr,
clk1_set_rd,
// device 2
clk2_set_wr,
clk2_set_rd,
// device 3
clk3_set_wr,
clk3_set_rd,
// setting trigger
conf_wr, // postive edge
conf_rd, // postive edge
// status
conf_ready, // high level
// 2-wire interface
max_sclk,
max_sdat
);
//=======================================================
// Port declarations
//=======================================================
// system input
input osc_50;
input rstn;
// device 1
input [3:0] clk1_set_wr;
output [3:0] clk1_set_rd;
// device 2
input [3:0] clk2_set_wr;
output [3:0] clk2_set_rd;
// device 3
input [3:0] clk3_set_wr;
output [3:0] clk3_set_rd;
// setting trigger
input conf_wr;
input conf_rd;
// status
output conf_ready;
// 2-wire interface
output max_sclk;
inout max_sdat;
//=======================================================
// Parameter declarations
//=======================================================
//=======================================================
// Signal declarations
//=======================================================
reg [2:0] conf_wr_d, conf_rd_d;
reg [7:0] slow_counter;
reg slow_counter_d;
wire clk_enable;
wire conf_wr_trigger, conf_rd_trigger;
reg conf_ready;
reg conf_wr_p2s;
wire [13:0] conf_data;
reg [4:0] conf_counter;
reg conf_end;
reg p2s;
reg s2p_act_pre;
reg [1:0] s2p_act;
reg [11:0] s2p;
reg sclk;
reg sclk_mask;
//=======================================================
// Structural coding
//=======================================================
assign clk1_set_rd = s2p[3:0];
assign clk2_set_rd = s2p[7:4];
assign clk3_set_rd = s2p[11:8];
assign max_sclk = sclk || (sclk_mask ? slow_counter[7] : 1'b0);
assign max_sdat = (s2p_act_pre || s2p_act[1]) ? 1'bz : p2s;
assign clk_enable = slow_counter_d && !slow_counter[7];
assign conf_wr_trigger = !conf_wr_d[2] && conf_wr_d[1];
assign conf_rd_trigger = !conf_rd_d[2] && conf_rd_d[1];
assign conf_data = conf_wr_p2s ? {2'b10, clk3_set_wr, clk2_set_wr, clk1_set_wr} : 14'hfff;
//--- pipe delay ---//
always @ (posedge osc_50 or negedge rstn)
if(!rstn)
begin
conf_wr_d <= 3'b0;
conf_rd_d <= 3'b0;
end
else
begin
conf_wr_d <= {conf_wr_d[1:0], conf_wr};
conf_rd_d <= {conf_rd_d[1:0], conf_rd};
end
//--- clock slow down enable ---//
always @ (posedge osc_50 or negedge rstn)
if(!rstn)
begin
slow_counter <= 8'b0;
slow_counter_d <= 1'b0;
end
else
begin
slow_counter <= slow_counter + 1;
slow_counter_d <= slow_counter[7];
end
//--- config status ---//
always @ (posedge osc_50 or negedge rstn)
if(!rstn)
conf_ready <= 1'b1;
else if (conf_wr_trigger || conf_rd_trigger)
begin
conf_ready <= 1'b0;
conf_wr_p2s <= conf_wr_trigger;
end
else if (clk_enable && conf_end)
conf_ready <= 1'b1;
//--- config counter ---//
always @ (posedge osc_50 or negedge rstn)
if(!rstn)
conf_counter <= 5'b0;
else if (conf_ready)
conf_counter <= 5'b0;
else if (clk_enable)
conf_counter <= conf_counter + 1;
//--- p2s convert ---//
always @ (posedge osc_50 or negedge rstn)
if (!rstn)
begin
sclk <= 1'b1; p2s <= 1'b1; sclk_mask <= 1'b0; conf_end <= 1'b0; s2p_act_pre <= 1'b0;
end
else if (clk_enable)
case (conf_counter)
5'd1 : p2s <= 1'b0;
5'd2 : sclk <= 1'b0;
5'd3 : begin p2s <= conf_data[13]; sclk_mask <= 1'b1; end
5'd4 : begin p2s <= conf_data[12]; s2p_act_pre <= !conf_wr_p2s; end
5'd5 : p2s <= conf_data[11];
5'd6 : p2s <= conf_data[10];
5'd7 : p2s <= conf_data[9];
5'd8 : p2s <= conf_data[8];
5'd9 : p2s <= conf_data[7];
5'd10 : p2s <= conf_data[6];
5'd11 : p2s <= conf_data[5];
5'd12 : p2s <= conf_data[4];
5'd13 : p2s <= conf_data[3];
5'd14 : p2s <= conf_data[2];
5'd15 : p2s <= conf_data[1];
5'd16 : begin p2s <= conf_data[0]; s2p_act_pre <= 1'b0; end
5'd17 : begin sclk <= 1'b0; p2s <= 1'b0; sclk_mask <= 1'b0; end
5'd18 : sclk <= 1'b1;
5'd19 : begin p2s <= 1'b1; conf_end <= 1'b1; end
default : begin sclk <= 1'b1; p2s <= 1'b1; sclk_mask <= 1'b0; conf_end <= 1'b0; s2p_act_pre <= 1'b0; end
endcase
//--- s2p convert ---//
always @ (posedge max_sclk)
if (s2p_act[0])
s2p <= {s2p[10:0], max_sdat};
always @ (posedge osc_50 or negedge rstn)
if (!rstn)
s2p_act <= 2'b0;
else if (clk_enable)
s2p_act <= {s2p_act[0], s2p_act_pre};
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> d; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, u; cin >> n >> u; d.resize(n); for (int i = 0; i < n; i++) { cin >> d[i]; } double ans = -1.0; for (int k = 2; k < n; k++) { int i = lower_bound(d.begin(), d.end(), d[k] - u) - d.begin(); int j = i + 1; if (i == j || j == k || k == i) continue; double res = double(d[k] - d[j]) / double(d[k] - d[i]); ans = max(ans, res); } for (int i = 0; i < n - 2; i++) { int j = i + 1; int k = upper_bound(d.begin(), d.end(), u + d[i]) - d.begin(); k--; if (i == j || j == k || k == i) continue; double res = double(d[k] - d[j]) / double(d[k] - d[i]); ans = max(ans, res); } cout.precision(15); cout.fixed; cout << ans; return 0; }
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* Uniform random traffic testbench
*
* Instantiates network and random traffic sources
*
*/
`timescale 1 ps/ 1 ps
`include "types.v"
`include "LAG_functions.v"
`include "parameters.v"
module LAG_test_random ();
//`include "parameters.v"
parameter CLOCK_PERIOD = 8_000;
flit_t [network_x-1:0][network_y-1:0] flit_in_;
flit_t [network_x-1:0][network_y-1:0][router_num_pls_on_exit-1:0] flit_out_;
logic [network_x-1:0][network_y-1:0][router_num_pls_on_entry-1:0] input_full_flag_;
chan_cntrl_t [network_x-1:0][network_y-1:0] cntrl_in_;
logic [network_x*network_y*$bits(chan_cntrl_t) - 1 : 0] cntrl_in;
logic [network_x*network_y*$bits(flit_t) - 1 : 0] flit_in;
logic [network_x*network_y*router_num_pls_on_exit*$bits(flit_t) - 1 : 0] flit_out;
logic [network_x*network_y*router_num_pls_on_entry - 1 : 0] input_full_flag;
integer rec_count [network_x-1:0][network_y-1:0];
sim_stats_t stats [network_x-1:0][network_y-1:0];
real av_lat[network_x-1:0][network_y-1:0];
genvar x,y,c;
integer i,j,k;
integer sys_time, total_packets, total_hops, min_latency, max_latency, total_latency;
integer min_hops, max_hops;
integer total_rec_count;
integer total_lat_for_hop_count [(network_x+network_y):0];
integer total_packets_with_hop_count[(network_x+network_y):0];
integer hc_total_packets, hc_total_latency;
integer lat_freq[100:0];
logic clk, rst_n;
generate
for (y=0; y<network_y; y=y+1) begin:ycg
for (x=0; x<network_x; x=x+1) begin:xcg
assign flit_in[$bits(flit_t)*(x*network_y + y + 1) - 1 : $bits(flit_t)*(x*network_y + y)] = flit_in_[x][y];
for (c=0; c<router_num_pls_on_exit; c++) begin:network_out_to_sink
assign flit_out_[x][y][c] = flit_out[$bits(flit_t)*(x*network_y*router_num_pls_on_exit + y*router_num_pls_on_exit + c + 1) - 1 : $bits(flit_t)*(x*network_y*router_num_pls_on_exit + y*router_num_pls_on_exit + c)];
end
assign cntrl_in[$bits(chan_cntrl_t)*(x*network_y + y + 1) - 1 : $bits(chan_cntrl_t)*(x*network_y + y)] = cntrl_in_[x][y];
assign input_full_flag_[x][y] = input_full_flag[router_num_pls_on_entry*(x*network_y + y + 1) - 1 : router_num_pls_on_entry*(x*network_y + y)];
end
end
endgenerate
// clock generator
/*initial begin
clk=0;
end
always #(CLOCK_PERIOD/2) clk = ~clk; */
initial begin
clk <= 0;
forever #(CLOCK_PERIOD/2) clk <= ~clk;
end
always@(posedge clk) begin
if (!rst_n) begin
sys_time=0;
end else begin
sys_time++;
end
/*
for (i=0; i<xdim; i++) begin
for (j=0; j<network_y; j++) begin
$write ("%b", input_full_flag[i][j]);
end
end
$display ("");
*/
end
// ########################
// Network
// ########################
LAG_mesh_network network (flit_in, flit_out,
input_full_flag,
cntrl_in,
clk, rst_n);
// ########################
// Traffic Sources
// ########################
generate
for (x=0; x<network_x; x++) begin:xl
for (y=0; y<network_y; y++) begin:yl
LAG_random_traffic_source #(.nv(router_num_pls_on_entry),
.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y),
.packet_length(sim_packet_length),
.rate(sim_injection_rate)
)
traf_src (.flit_out(flit_in_[x][y]),
.network_ready(~input_full_flag_[x][y]),
.clk, .rst_n);
end
end
endgenerate
// ########################
// Traffic Sinks
// ########################
generate
for (x=0; x<network_x; x++) begin:xl2
for (y=0; y<network_y; y++) begin:yl2
LAG_traffic_sink #(.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y),
.warmup_packets(sim_warmup_packets), .measurement_packets(sim_measurement_packets),
.router_num_pls_on_exit(router_num_pls_on_exit))
traf_sink (.flit_in(flit_out_[x][y]),
.cntrl_out(cntrl_in_[x][y]),
.rec_count(rec_count[x][y]),
.stats(stats[x][y]),
.clk, .rst_n);
end
end
endgenerate
//
// All measurement packets must be received before we end the simulation
// (this includes a drain phase)
//
always@(posedge clk) begin
total_rec_count=0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
total_rec_count=total_rec_count+rec_count[i][j];
end
end
end
initial begin
`ifdef DUMPTRACE
$dumpfile ("wave.pld");
$dumpvars (4);
`endif
$display ("*******************************************************");
$display ("* Wormhole NoC with LAG - Uniform Random Traffic Test *");
$display ("*******************************************************");
total_hops=0;
total_latency=0;
//
// reset
//
rst_n=0;
// reset
repeat(20) @(negedge clk);
rst_n=1;
$display ("-- Reset Complete");
$display ("-- Entering warmup phase (%1d packets per node)", sim_warmup_packets);
// #################################################################
// wait for all traffic sinks to rec. all measurement packets
// #################################################################
wait (total_rec_count==sim_measurement_packets*network_x*network_y);
$display ("** Simulation End **\n");
total_packets = sim_measurement_packets*network_x*network_y;
min_latency=stats[0][0].min_latency;
max_latency=stats[0][0].max_latency;
min_hops=stats[0][0].min_hops;
max_hops=stats[0][0].max_hops;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
av_lat[i][j] = $itor(stats[i][j].total_latency)/$itor(rec_count[i][j]);
total_latency = total_latency + stats[i][j].total_latency;
total_hops=total_hops+stats[i][j].total_hops;
min_latency = min(min_latency, stats[i][j].min_latency);
max_latency = max(max_latency, stats[i][j].max_latency);
end
end
for (k=0; k<=100; k++) lat_freq[k]=0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
for (k=0; k<=100; k++) begin
lat_freq[k]=lat_freq[k]+stats[i][j].lat_freq[k];
end
end
end
$display ("***********************************************************************************");
$display ("-- Channel Latency = %1d", channel_latency);
$display ("***********************************************************************************");
$display ("-- Packet Length = %1d", sim_packet_length);
$display ("-- Injection Rate = %1.4f (flits/cycle/node)", sim_injection_rate);
$display ("-- Average Latency = %1.2f (cycles)", $itor(total_latency)/$itor(total_packets));
$display ("-- Min. Latency = %1d, Max. Latency = %1d", min_latency, max_latency);
$display ("-- Average no. of hops taken by packet = %1.2f hops (min=%1d, max=%1d)",
$itor(total_hops)/$itor(total_packets), min_hops, max_hops);
$display ("***********************************************************************************");
$display ("\n");
$display ("Average Latencies for packets rec'd at nodes [x,y] and (no. of packets received)");
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y;j++) $write ("%1.2f (%1d)\t", av_lat[i][j], rec_count[i][j]);
$display ("");
end
$display ("Flits/cycle received at each node: (should approx. injection rate)");
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
$write ("%1.2f\t", $itor(stats[i][j].flit_count)/$itor(stats[i][j].measure_end-stats[i][j].measure_start));
end
$display ("");
end
$display ("");
$display ("Distribution of packet latencies: ");
$display ("Latency : Frequency (as percentage of total)");
$display ("-------------------");
for (k=0; k<100; k++) begin
$display ("%1d %1.2f", k, $itor(lat_freq[k]*100)/$itor(total_packets));
end
$display ("100+ %1.2f", $itor(lat_freq[k]*100)/$itor(total_packets));
$finish;
end
endmodule // LAG_test_random
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module master #(
parameter id = 0,
parameter nreads = 128,
parameter nwrites = 128,
parameter p = 4
) (
input sys_clk,
input sys_rst,
output reg [31:0] dat_w,
input [31:0] dat_r,
output reg [31:0] adr,
output [2:0] cti,
output reg we,
output reg [3:0] sel,
output cyc,
output stb,
input ack,
output reg tend
);
integer rcounter;
integer wcounter;
reg active;
assign cyc = active;
assign stb = active;
assign cti = 0;
always @(posedge sys_clk) begin
if(sys_rst) begin
dat_w = 0;
adr = 0;
we = 0;
sel = 0;
active = 0;
rcounter = 0;
wcounter = 0;
tend = 0;
end else begin
if(ack) begin
if(~active)
$display("[M%d] Spurious ack", id);
else begin
if(we)
$display("[M%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
else
$display("[M%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
end
active = 1'b0;
end else if(~active) begin
if(($random % p) == 0) begin
adr = $random;
adr = adr % 5;
adr = (adr << (32-3)) + id;
sel = sel + 1;
active = 1'b1;
if(($random % 2) == 0) begin
/* Read */
we = 1'b0;
rcounter = rcounter + 1;
end else begin
/* Write */
we = 1'b1;
dat_w = ($random << 16) + id;
wcounter = wcounter + 1;
end
end
end
tend = (rcounter >= nreads) && (wcounter >= nwrites);
end
end
endmodule
|
/*
This code was adapted from
http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
*/
//A parameterized inverable, dual-clock block ram
`timescale 1ns/1ps
module dpb #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10,
parameter MEM_FILE = "NOTHING",
parameter MEM_FILE_LENGTH = 0,
parameter INITIALIZE = 0
) (
input clka,
input wea,
input wire [ADDR_WIDTH - 1: 0] addra,
input wire [DATA_WIDTH - 1: 0] dina,
output reg [DATA_WIDTH - 1: 0] douta = 0,
input clkb,
input web,
input wire [ADDR_WIDTH - 1: 0] addrb,
input wire [DATA_WIDTH - 1: 0] dinb,
output reg [DATA_WIDTH - 1: 0] doutb = 0
);
//Shared Memory
reg [DATA_WIDTH - 1: 0] mem [(1 << ADDR_WIDTH) - 1: 0];
integer i;
generate
if (MEM_FILE != "NOTHING") begin
initial begin
$readmemh(MEM_FILE, mem, 0, MEM_FILE_LENGTH - 1);
end
end
else begin
initial begin
if (INITIALIZE == 1) begin
for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) begin
mem[i] <= 0;
end
end
end
end
endgenerate
//Port A
always @ (posedge clka) begin
douta <= mem[addra];
if (wea) begin
douta <= dina;
mem[addra] <= dina;
end
end
//Port B
always @ (posedge clkb) begin
doutb <= mem[addrb];
if (web) begin
doutb <= dinb;
mem[addrb] <= dinb;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> tree[500001]; bool intree[500001]; vector<int> tmp(0); bool isleaf(int node) { if (tree[node].size() == 1 && intree[(tree[node])[0]]) return true; return false; } void DFS(int lvl, int node) { intree[node] = true; if (isleaf(node)) { tmp.push_back(lvl); } for (int i = 0; i < tree[node].size(); i++) { if (!intree[(tree[node])[i]]) { DFS(lvl + 1, (tree[node])[i]); } } } int main() { ios_base::sync_with_stdio(false); int N; cin >> N; for (int i = 1; i <= N; i++) intree[i] = false; int x, y; for (int i = 0; i < N - 1; i++) { cin >> x >> y; tree[x].push_back(y); tree[y].push_back(x); } intree[1] = true; int ans = 0, c; for (int i = 0; i < (tree[1]).size(); i++) { tmp.clear(); DFS(0, (tree[1])[i]); sort(tmp.begin(), tmp.end()); c = tmp.size(); for (int j = 0; j < c; j++) { ans = max(ans, tmp[j] + c - j); } } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFBBN_PP_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_PP_BLACKBOX_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The IRQ and Event Sync module
//
// ====================================================================
`include "e203_defines.v"
module e203_irq_sync #(
parameter MASTER = 1
) (
input clk,
input rst_n,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
input dbg_irq_a,
output ext_irq_r,
output sft_irq_r,
output tmr_irq_r,
output dbg_irq_r
);
generate
if(MASTER == 1) begin:master_gen
`ifndef E203_HAS_LOCKSTEP//{
`ifdef E203_IRQ_NEED_SYNC//{
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_dbg_irq_sync(
.din_a (dbg_irq_a),
.dout (dbg_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_ext_irq_sync(
.din_a (ext_irq_a),
.dout (ext_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_sft_irq_sync(
.din_a (sft_irq_a),
.dout (sft_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_tmr_irq_sync(
.din_a (tmr_irq_a),
.dout (tmr_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
`else//}{
assign ext_irq_r = ext_irq_a;
assign sft_irq_r = sft_irq_a;
assign tmr_irq_r = tmr_irq_a;
assign dbg_irq_r = dbg_irq_a;
`endif//}
`endif//}
end
else begin:slave_gen
// Just pass through for slave in lockstep mode
assign ext_irq_r = ext_irq_a;
assign sft_irq_r = sft_irq_a;
assign tmr_irq_r = tmr_irq_a;
assign dbg_irq_r = dbg_irq_a;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O31A_FUNCTIONAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int pot(int n) { if (n == (n & -n)) return n; return (n - (n & -n)); } int main() { int n, b, p; cin >> n >> b >> p; int ans1 = 0, ans2 = p * n; while (n != 1) { int d = pot(n); int e = n - d; n -= (d / 2); ans1 += (d * b + (d / 2)); } cout << ans1 << << ans2; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 11:48:22 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_rx_inst/fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module fifo_generator_rx_inst(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
module ARM(input clk,input reset,input [31:0] inst,input [31:0]ReadData,output [31:0] DataAdr ,
output [31:0] WriteData,
output Write_Enable,output reg [31:0] PC);
wire[3:0] ALUFlags;
wire PCSrc,MemtoReg,MemWrite;
wire [1:0]ALUControl;
wire ALUSrc;
wire [1:0]ImmSrc;
wire RegWrite;
wire [1:0]RegSrc;
//reg [31:0] PC;
initial
PC=32'b0;
wire [31:0] PCPlus4,PCPlus8,PC_dash;
assign PCPlus4=PC+4;
assign PCPlus8=PCPlus4+4;
wire [31:0] Result;
assign PC_dash=(PCSrc==1)?Result:PCPlus4;
always @(posedge clk,posedge reset)begin
if(reset)
PC=32'b0;
else
PC<=PC_dash;
end
control_unit Cu(clk,reset,inst[31:28],inst[27:26],inst[25:20],inst[15:12],ALUFlags,PCSrc,
MemtoReg,MemWrite,
ALUControl,ALUSrc,ImmSrc,RegWrite,RegSrc);
wire [3:0] RA1;
assign RA1=(RegSrc[0]==1)?4'd15:inst[19:16];
wire [3:0] RA2;
assign RA2=(RegSrc[1]==1)? inst[15:12]:inst[3:0];
wire [3:0] RA3;
assign RA3=inst[15:12];
wire [31:0] ALUResult;
wire [31:0] RD1,RD2;
assign DataAdr = ALUResult;
assign WriteData=RD2;
assign Result=(MemtoReg==1)?ReadData:ALUResult;
register_file R_F(clk,RegWrite,RA1,RA2,RA3,Result,PCPlus8,RD1,RD2);
wire [31:0] SrcA,SrcB,ExtImm;
assign SrcA=RD1;
assign SrcB=(ALUSrc==1)?ExtImm:RD2;
alu2 alu(SrcA,SrcB,ALUControl,ALUResult,ALUFlags);
extend ex(ImmSrc,inst[23:0],ExtImm);
assign Write_Enable=MemWrite;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); int t; cin >> t; while (t--) { int n; cin >> n; for (int pw = 2; pw < 30; ++pw) { int val = (1 << pw) - 1; if (n % val == 0) { cout << n / val << endl; break; } } } }
|
#include <bits/stdc++.h> using namespace std; uint64_t rnd_data = 0xDEADBEEFDULL; inline void my_srand(int seed) { rnd_data = ((uint64_t)seed << 16) | 0x330E; } inline int my_rand() { rnd_data = rnd_data * 0x5DEECE66DULL + 0xB; return (rnd_data >> 17) & 0x7FFFFFFF; } template <typename T> void my_random_shuffle(T b, T e) { for (int i = (1); i <= (int)((int)(e - b) - 1); i++) { swap(b[i], b[my_rand() % (i + 1)]); } } template <class _T> inline _T sqr(const _T &x) { return x * x; } template <typename type_t, typename less_t = std::less<type_t>> inline bool uin(type_t &a, const type_t &b, const less_t &ls = less_t()) { return ls(b, a) ? a = b, true : false; } template <typename type_t, typename less_t = std::less<type_t>> inline bool uax(type_t &a, const type_t &b, const less_t &ls = less_t()) { return ls(a, b) ? a = b, true : false; } const long double PI = 3.1415926535897932384626433832795L; const long double EPS = 1e-9; const int MAXN = 1 << 17; int n, k; int a[MAXN]; bool g[MAXN]; int d[MAXN * 2][2][2]; int main() { scanf( %d%d , &n, &k); memset((g), 0, sizeof(g)); for (int i = 0; i < (int)(k); i++) { scanf( %d , &a[i]); g[a[i] - 1] = true; } memset(d, 0x80, sizeof(d)); int z = 1 << (n - 1); for (int i = 0; i < (int)(z); i++) { int x = i << 1; int y = x + 1; d[z + i][g[x]][g[y]] = g[x] || g[y]; d[z + i][g[y]][g[x]] = g[x] || g[y]; } for (int i = (z - 1); i >= (int)(1); i--) { int x = i * 2; int y = x + 1; for (int xw = 0; xw < (int)(2); xw++) { for (int xl = 0; xl < (int)(2); xl++) { if (d[x][xw][xl] < 0) continue; for (int yw = 0; yw < (int)(2); yw++) { for (int yl = 0; yl < (int)(2); yl++) { if (d[y][yw][yl] < 0) continue; int gw[2] = {xw, yw}; bool ggl = xl || yl; for (int t = 0; t < (int)(2); t++) { int cur = (xw || yw) + ggl; int nw = gw[t]; int nl0 = gw[t ^ 1]; int nl = nl0 || ggl; cur += nl; uax(d[i][nw][nl], d[x][xw][xl] + d[y][yw][yl] + cur); } } } } } } int ans = 0; for (int i = 0; i < (int)(2); i++) { for (int j = 0; j < (int)(2); j++) { int add = (i || j); uax(ans, d[1][i][j] + add); } } printf( %d n , ans); return 0; }
|
`include "register_file.v"
module test;
reg clk_reg = 1'b0;
wire clk;
assign clk = clk_reg;
always #5 clk_reg <= ~clk_reg;
reg write = 1'b0;
wire[31:0] r_out[1:0];
wire[4:0] r_ctrl[1:0];
reg[4:0] r_ctrl_reg[1:0];
assign r_ctrl[0] = r_ctrl_reg[0];
assign r_ctrl[1] = r_ctrl_reg[1];
reg[31:0] w_data;
reg[4:0] w_ctrl;
integer tests = 0;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
write = 0;
r_ctrl_reg[0] = 0;
r_ctrl_reg[1] = 0;
w_data = 0;
w_ctrl = 0;
end
register_file uut(clk, write, r_ctrl[0], r_out[0], r_ctrl[1], r_out[1], w_ctrl, w_data);
integer test_val = 0;
always @(posedge clk) begin
write = 1;
w_ctrl = w_ctrl+1;
w_data = w_data+1;
tests = tests + 1;
r_ctrl_reg[0] = w_ctrl-1;
r_ctrl_reg[1] = w_ctrl-1;
$display("ctrl0 = %d out0 = %d, ctrl1 = %d out1 = %d", r_ctrl[0], r_out[0], r_ctrl[1], r_out[1]);
if (tests+1 >= 16)
#20 $finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the +1364-1995ext+ and +systemverilogext+ flags.
//
// This source code contains constructs that are valid in SystemVerilog 2009
// but not in Verilog 1995. So it should fail if we set the language to be
// Verilog 1995, but not SystemVerilog 2009.
//
// Compile only test, so no need for "All Finished" output.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] res;
// Instantiate the test
test test_i (/*AUTOINST*/
// Outputs
.res (res),
// Inputs
.clk (clk),
.in (1'b1));
endmodule
module test (// Outputs
res,
// Inputs
clk,
in
);
output [1:0] res;
input clk;
input in;
// This is a SystemVerilog 2009 only test
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
unique0 case (i)
0: res[0:0] <= in;
1: res[1:1] <= in;
endcase
end
end
endgenerate
endmodule
|
// STD 10-30-16
//
// Synchronous 1-port ram with byte masking
// Only one read or one write may be done per cycle.
//
module bsg_mem_1rw_sync_mask_write_byte
#(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
// TSMC 180 1024x32 Byte Mask
if ((els_p == 1024) & (data_width_p == 32))
begin : macro
wire [3:0] wen = {~(w_i & write_mask_i[3])
,~(w_i & write_mask_i[2])
,~(w_i & write_mask_i[1])
,~(w_i & write_mask_i[0])};
tsmc180_1rw_lg10_w32_m8_byte mem
(.Q (data_o)
,.CLK (clk_i)
,.CEN (~v_i)
,.WEN (wen)
,.A (addr_i)
,.D (data_i)
// 1=tristate output
,.OEN (1'b0)
);
end
// no hardened version found
else
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth
#(.els_p(els_p), .data_width_p(data_width_p))
synth (.*);
end
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) v.push_back(move(x)); return move(v); } void err(vector<string>::iterator it) {} template <typename T, typename... Args> void err(vector<string>::iterator it, T a, Args... args) { cerr << it->substr((*it)[0] == , it->length()) << = << a << n ; err(++it, args...); } int N, M; int S[300013]; set<int> flv[300013]; vector<int> adj[300013]; int ans = 1; int color[300013]; void dfs(int n, int p = 0) { set<int> s; int cur = 1; for (int x : flv[n]) { if (color[x]) { s.insert(color[x]); } } for (int x : flv[n]) { if (!color[x]) { while (s.count(cur)) cur++; color[x] = cur++; } } for (int v : adj[n]) { if (v != p) { dfs(v, n); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> N >> M; for (int i = 1; i <= N; i++) { cin >> S[i]; ans = max(ans, S[i]); for (int j = 0; j < S[i]; j++) { int k; cin >> k; flv[i].insert(k); } } for (int i = 1; i < N; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1); cout << ans << endl; for (int i = 1; i <= M; i++) { cout << (color[i] ? color[i] : 1) << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[100005][2]; int dp[100005][3]; enum direction { n, l, r, }; int main() { int N; cin >> N; for (size_t i = 1; i <= N; i++) { cin >> a[i][0] >> a[i][1]; dp[i][n] = dp[i][l] = dp[i][r] = 0; } a[0][0] = -1e18; a[0][1] = 0; dp[0][l] = dp[0][r] = dp[0][n] = 0; a[N + 1][0] = 1e18; a[N + 1][1] = 0; for (size_t i = 0; i <= N; i++) { if (a[i + 1][0] - a[i][0] > a[i + 1][1] + a[i][1]) { dp[i + 1][l] = 1 + max(max(dp[i][l], dp[i][r]), dp[i][n]); dp[i + 1][n] = max(max(dp[i][l], dp[i][r]), dp[i][n]); } else if (a[i + 1][0] - a[i][0] > a[i + 1][1]) { dp[i + 1][l] = 1 + max(dp[i][l], dp[i][n]); dp[i + 1][n] = max(dp[i][l], max(dp[i][n], dp[i][r])); } if (a[i + 2][0] - a[i + 1][0] > a[i + 2][1] + a[i + 1][1]) { dp[i + 1][r] = 1 + max(max(dp[i][l], dp[i][r]), dp[i][n]); dp[i + 1][n] = max(max(dp[i][l], dp[i][r]), dp[i][n]); } else if (a[i + 2][0] - a[i + 1][0] > a[i + 1][1]) { dp[i + 1][r] = 1 + max(dp[i][r], max(dp[i][n], dp[i][l])); dp[i + 1][n] = max(max(dp[i][n], dp[i][r]), dp[i][l]); } if (!(a[i + 2][0] - a[i + 1][0] > a[i + 1][1]) && !(a[i + 1][0] - a[i][0] > a[i + 1][1])) { dp[i + 1][n] = max(max(dp[i][l], dp[i][r]), dp[i][n]); } } cout << max(max(dp[N][1], dp[N][0]), dp[N][2]); }
|
#include <bits/stdc++.h> int dp[2][1005]; int main() { char start[2 * 1005], end[1005]; int i, j, k, K; while (scanf( %s %s %d , start, end, &K) != EOF) { memset(dp, 0, sizeof(dp)); int n = strlen(start); for (i = n; i < 2 * n; i++) start[i] = start[i - n]; dp[0][0] = 1; int cur = 1; long long sum[2]; sum[0] = 1, sum[1] = 0; for (k = 0; k < K; k++) { sum[cur] = 0; for (i = 0; i < n; i++) { dp[cur][i] = (sum[cur ^ 1] - dp[cur ^ 1][i] + 1000000007); if (dp[cur][i] >= 1000000007) dp[cur][i] -= 1000000007; sum[cur] = (sum[cur] + dp[cur][i]); if (sum[cur] >= 1000000007) sum[cur] -= 1000000007; } cur ^= 1; } int ans = 0; for (i = 0; i < n; i++) if (strncmp(start + i, end, n) == 0) ans += dp[cur ^ 1][i], ans %= 1000000007; printf( %d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; const int M = 2e6 + 2e5; const int N = M >> 1; const int MX = 2e6; const int D = 1e6; double L[M], R[M]; int g[M]; struct pnt { int x, y; void input() { scanf( %d %d , &x, &y); } } p[N]; int n; double ans; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { p[i].input(); p[i].x += D, p[i].y += D; } function<void(int, double)> update = [&](int y, double x) { L[y] = min(L[y], x); R[y] = max(R[y], x); }; for (int step = 0; step < 2; step++) { for (int i = 0; i <= MX; i++) L[i] = M, R[i] = -1; for (int i = 1; i <= n; i++) { update(p[i].y, p[i].x); int ni = i == n ? 1 : i + 1; if (p[i].y == p[ni].y) continue; double d = (p[ni].x - p[i].x) * 1.0 / (p[ni].y - p[i].y); double cur; cur = p[i].x; for (int j = p[i].y + 1; j < p[ni].y; j++) { cur += d; update(j, cur); } cur = p[ni].x; for (int j = p[ni].y + 1; j < p[i].y; j++) { cur += d; update(j, cur); } } long long tot = 0; for (int i = 0; i <= MX; i++) { int lx = L[i] + 0.9999999; int rx = R[i] + 0.0000001; g[i] = rx >= lx ? rx - lx + 1 : 0; tot += g[i]; } double c = 0, d = 0, dd = 0; for (int i = 0; i < MX; i++) { double r = g[i] * 1.0 / (tot - 1); d = d + dd + r; dd = dd + r + r; c = c + d; ans += 1.0 * g[i + 1] / tot * c; } for (int i = 1; i <= n; i++) swap(p[i].x, p[i].y); } cout << fixed << setprecision(10) << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long f[5020][5020], a[5020], powk[5020], ans, ans2, invn; int n, k; inline long long power(long long x, long long y) { long long res = 1; while (y) { if (y & 1) res = res * x % mod; x = x * x % mod; y >>= 1; } return res; } void init() { powk[0] = 1; for (register int i = 1; i <= n; i++) powk[i] = powk[i - 1] * (k - i + 1) % mod; invn = mod - power(n, mod - 2); } int main() { scanf( %d %d , &n, &k); init(); ans = 1; for (register int i = 1; i <= n; i++) scanf( %lld , &a[i]), ans = ans * a[i] % mod; f[0][0] = 1; for (register int i = 1; i <= n; i++) { f[i][0] = 1; for (register int j = 1; j <= i; j++) { f[i][j] = (f[i - 1][j] + f[i - 1][j - 1] * a[i]) % mod; } } for (register int i = 0; i <= n; i++) { ans2 = (ans2 + f[n][i] * power(invn, n - i) % mod * powk[n - i]) % mod; } cout << (ans - ans2 + mod) % mod << endl; }
|
//---------------------------------------------------------------------//
// Name: addrgen.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Generates addresses.
//---------------------------------------------------------------------//
module addrgen(
clk,
nrst,
start,
n,
wraddr,
wren,
rdaddr,
vexaddr
);
input clk;
input nrst;
input start;
input [15:0]n;
output [10:0]wraddr;
output [10:0]rdaddr;
output [13:0]vexaddr;
output wren;
reg [15:0]counter1;
reg [15:0]counter2;
reg [15:0]counter3;
reg [15:0]counter4;
reg [15:0]timer1;
reg [15:0]timer2;
reg [15:0]timer3;
reg [29:0]t1_exp_dly;
reg [29:0]t2_exp_dly;
reg [29:0]start_dly;
wire t1_expire = timer1[15];
wire t2_expire = timer2[15];
wire t3_expire = timer3[15];
assign rdaddr = counter1[10:0];
assign vexaddr = counter3[13:0];
assign wraddr = counter4[10:0];
//---------------------------------------------------------------------//
// Timers
//---------------------------------------------------------------------//
// Timer T1
// - Loads 'n' on start.
// - Stops counting when it reaches -1.
// - Decrements on t2_expire;
always @(posedge clk)
if (~nrst) timer1 <= -1;
else if(start) timer1 <= {1'b0,n[14:0]};
else if(!t1_expire && t2_expire) timer1 <= timer1 - 1;
// Timer T2
// - Counts down from T1 divided by 4.
// - Resets when it hits -1.
// - Stops decrementing the initial input once t3 expires.
wire [15:0] t2_startval = {3'b0, n[15:2]} - 1;
wire [15:0] t1_minus = timer1 - 5;
always @(posedge clk)
if (~nrst) timer2 <= -1;
else if(start) timer2 <= t2_startval;
else if(!t1_expire && t2_expire && !t3_expire) timer2 <= {3'b0, t1_minus[15:2]};
else if(!t1_expire && t2_expire && t3_expire) timer2 <= 30;
else if(!t1_expire && !t2_expire) timer2 <= timer2 - 1;
// Timer T3
always @(posedge clk)
if(~nrst) timer3 <= -1;
else if(start) timer3 <= n-128; // For a 30 cycle pipeline.
else if(!t3_expire && t2_expire) timer3 <= timer3 - 1;
// Shift registers for delayed counting.
always@(posedge clk)
if (~nrst) t1_exp_dly <= 0;
else t1_exp_dly <= {t1_exp_dly[28:0], t1_expire};
always@(posedge clk)
if(~nrst) t2_exp_dly <= 0;
else t2_exp_dly <= {t2_exp_dly[28:0], t2_expire};
always@(posedge clk)
if(~nrst) start_dly <= 0;
else start_dly <= {start_dly[28:0], start};
wire sig_a = t1_exp_dly[24];
wire sig_b = t2_exp_dly[24];
wire sig_c = start_dly[24];
wire sig_d = t1_exp_dly[29];
wire sig_e = t2_exp_dly[29];
wire sig_f = start_dly[29];
assign wren = !sig_d;
//---------------------------------------------------------------------//
// Logic for generating rdaddr.
//---------------------------------------------------------------------//
// Counter C1
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter1 <= -1;
else if(start) counter1 <= 0;
else if(!t1_expire && t2_expire) counter1 <= 0;
else if(!t1_expire && !t2_expire) counter1 <= counter1 + 1;
//---------------------------------------------------------------------//
// Logic for generating vex_addr.
//---------------------------------------------------------------------//
// Counter C2
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t4 expires.
always @(posedge clk)
if(~nrst) counter2 <= -1;
else if(sig_c) counter2 <= 0;
else if(!sig_a && sig_b) counter2 <= counter2 + 1;
// Counter C3
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t1 expires.
always @(posedge clk)
if(~nrst) counter3 <= -1;
else if(sig_c) counter3 <= 0;
else if(!sig_a && sig_b) counter3 <= counter2 + 1;
else if(!sig_a && !sig_b) counter3 <= counter3 + 8;
//---------------------------------------------------------------------//
// Logic for generating wraddr.
//---------------------------------------------------------------------//
// Counter C4
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter4 <= -1;
else if(sig_f) counter4 <= 0;
else if(!sig_d && sig_e) counter4 <= 0;
else if(!sig_d && !sig_e) counter4 <= counter4 + 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int size = 110000, mod = 1000000007, inf = 0x3f3f3f3f; const double pi = acos(-1.0); int month[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int nex[2][4] = {0, 1, 0, -1, 1, 0, -1, 0}; long long cal(long long a, int n) { long long s = 1 % mod; while (n) { if (n & 1) s = (s * a) % mod; a = (a * a) % mod; n /= 2; } return s; } int n, ar[size]; long long ans; vector<int> fac, fac2; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> ar[i]; sort(ar, ar + n); for (int i = ar[n - 1]; i >= 1; i--) { long long t = 1; fac.clear(); for (int j = 1; j * j <= i; j++) if (i % j == 0) { fac.push_back(j); if (j * j != i) fac.push_back(i / j); } sort(fac.begin(), fac.end()); int pre = 0; for (int j = 1; j < fac.size(); j++) { int num = lower_bound(ar, ar + n, fac[j]) - ar; t = t * cal(j, num - pre) % mod; pre = num; } t = t * (cal(fac.size(), n - pre) - cal(fac.size() - 1, n - pre)) % mod; ans = (ans + t) % mod; } cout << (ans + mod) % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long getint() { long long _x = 0, _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x *= 10, _x += (_tc - 0 ), _tc = getchar(); return _x * _tmp; } inline long long add(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x + _y; if (_ >= _mod) _ -= _mod; return _; } inline long long sub(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x - _y; if (_ < 0) _ += _mod; return _; } inline long long mul(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x * _y; if (_ >= _mod) _ %= _mod; return _; } long long mypow(long long _a, long long _x, long long _mod) { if (_x == 0) return 1ll; long long _tmp = mypow(_a, _x / 2, _mod); _tmp = mul(_tmp, _tmp, _mod); if (_x & 1) _tmp = mul(_tmp, _a, _mod); return _tmp; } long long mymul(long long _a, long long _x, long long _mod) { if (_x == 0) return 0ll; long long _tmp = mymul(_a, _x / 2, _mod); _tmp = add(_tmp, _tmp, _mod); if (_x & 1) _tmp = add(_tmp, _a, _mod); return _tmp; } inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } int __ = 1, _cs; void build() {} long long n, m, a, b; void init() { n = getint(); m = getint(); a = getint() - 1; b = getint() - 1; } void solve() { long long ai = a / m, aj = a % m; long long bi = b / m, bj = b % m; if (ai == bi || (a == 0 && b == n - 1) || m == 1) { puts( 1 ); exit(0); } if (aj == 0 && (bj == m - 1 || b == n - 1)) { puts( 1 ); exit(0); } if (aj == 0 || bj == m - 1 || bi == ai + 1 || bj + 1 == aj || b == n - 1) { puts( 2 ); exit(0); } puts( 3 ); } int main() { build(); while (__--) { init(); solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int FFTMOD = 119 << 23 | 1; const int INF = (int)1e9 + 23111992; const long long LINF = (long long)1e18 + 23111992; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> inline int chkmin(T& a, const T& val) { return val < a ? a = val, 1 : 0; } template <class T> inline int chkmax(T& a, const T& val) { return a < val ? a = val, 1 : 0; } inline unsigned long long isqrt(unsigned long long k) { unsigned long long r = sqrt(k) + 1; while (r * r > k) r--; return r; } inline long long icbrt(long long k) { long long r = cbrt(k) + 1; while (r * r * r > k) r--; return r; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } inline int sign(long double x) { return x < -EPS ? -1 : x > +EPS; } inline int sign(long double x, long double y) { return sign(x - y); } mt19937 mt(chrono::high_resolution_clock::now().time_since_epoch().count()); inline int mrand() { return abs((int)mt()); } inline int mrand(int k) { return abs((int)mt()) % k; } void chemthan() { int C = 1e5 + 5; vector<int> sp(C); for (int i = (1); i < (C); ++i) sp[i] = i; for (int i = (2); i < (C); ++i) if (sp[i] == i) { for (int j = i + i; j < C; j += i) { chkmin(sp[j], i); } } vector<int> mob(C, 1); for (int i = (2); i < (C); ++i) { int t = i; int pv = -1; while (1 < t) { if (pv == sp[t]) { mob[i] = 0; } mob[i] *= -1; pv = sp[t]; t /= sp[t]; } } vector<vector<int> > dvs(C); vector<vector<int> > dvs2(C); for (int i = (1); i < (C); ++i) { for (int j = i; j < C; j += i) { dvs[j].push_back(i); if (mob[j / i]) dvs2[j].push_back(i); } } int n; cin >> n; vector<int> a(n); vector<vector<int> > g(C); for (int i = (0); i < (n); ++i) { cin >> a[i]; for (int d : dvs[i + 1]) { g[d].push_back(a[i]); } } vector<int> c(C); vector<int> f(C); vector<int> x(C); vector<int> y(C); int res = 0; for (int i = (1); i < (C); ++i) if (int((g[i]).size())) { vector<int> tmp2; vector<int> tmp; for (int u : g[i]) { c[u] = 0; } for (int u : g[i]) { if (!c[u]++) { tmp2.push_back(u); } } for (int u : tmp2) { for (int d : dvs[u]) { if (!f[d]) { tmp.push_back(d); } f[d] += c[u]; } } for (int u : tmp) { f[u] = mult(f[u], f[u]); } int sum = 0; for (int u : tmp) { for (int v : dvs2[u]) { if (mob[u / v]) { if (mob[u / v] == 1) { addmod(x[v], f[u]); } else { submod(x[v], f[u]); } } } } for (int u : tmp) { addmod(sum, mult(x[u], u)); } y[i] = sum; for (int u : tmp) f[u] = x[u] = 0; } for (int i = (C)-1; i >= (1); --i) { for (int j = i + i; j < C; j += i) { submod(y[i], y[j]); } addmod(res, mult(i, y[i])); } cout << res << n ; } int32_t main(int32_t argc, char* argv[]) { ios_base::sync_with_stdio(0), cin.tie(0); if (argc > 1) { assert(freopen(argv[1], r , stdin)); } if (argc > 2) { assert(freopen(argv[2], wb , stdout)); } chemthan(); cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; }
|
/*
ORSoC GFX accelerator core
Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
INTERPOLATION MODULE - DIVIDER
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module interpolates by using div_uu division units
One division takes exactly point_width+1 ticks to complete, but many divisions can be pipelined at the same time.
*/
module gfx_interp(clk_i, rst_i,
ack_i, ack_o,
write_i,
// Variables needed for interpolation
edge0_i, edge1_i, area_i,
// Raster position
x_i, y_i, x_o, y_o,
factor0_o, factor1_o,
write_o
);
parameter point_width = 16;
parameter delay_width = 5;
parameter div_delay = point_width+1;
parameter result_width = 4;
input clk_i;
input rst_i;
input ack_i;
output reg ack_o;
input write_i;
input [2*point_width-1:0] edge0_i;
input [2*point_width-1:0] edge1_i;
input [2*point_width-1:0] area_i;
input [point_width-1:0] x_i;
input [point_width-1:0] y_i;
output [point_width-1:0] x_o;
output [point_width-1:0] y_o;
// Generated pixel coordinates
output [point_width-1:0] factor0_o;
output [point_width-1:0] factor1_o;
// Write pixel output signal
output write_o;
// calculates factor0
wire [point_width-1:0] interp0_quotient; // result
wire [point_width-1:0] interp0_reminder;
wire interp0_div_by_zero;
wire interp0_overflow;
// calculates factor1
wire [point_width-1:0] interp1_quotient; // result
wire [point_width-1:0] interp1_reminder;
wire interp1_div_by_zero;
wire interp1_overflow;
reg [delay_width-1:0] phase_counter;
wire division_enable;
always @(posedge clk_i or posedge rst_i)
if(rst_i)
phase_counter <= 1'b0;
else if(division_enable)
phase_counter <= (phase_counter + 1'b1 == div_delay) ? 1'b0 : phase_counter + 1'b1;
// State machine
reg state;
parameter wait_state = 1'b0,
write_state = 1'b1;
// Manage states
always @(posedge clk_i or posedge rst_i)
if(rst_i)
state <= wait_state;
else
case (state)
wait_state:
if(write_o)
state <= write_state;
write_state:
if(ack_i)
state <= wait_state;
endcase
always @(posedge clk_i or posedge rst_i)
begin
// Reset
if(rst_i)
ack_o <= 1'b0;
else
case (state)
wait_state:
ack_o <= 1'b0;
write_state:
if(ack_i)
ack_o <= 1'b1;
endcase
end
wire [point_width-1:0] zeroes = 1'b0;
// division unit 0
div_uu #(2*point_width) dut0 (
.clk (clk_i),
.ena (division_enable),
.z ({edge0_i[point_width-1:0], zeroes}),
.d (area_i[point_width-1:0]),
.q (interp0_quotient),
.s (interp0_reminder),
.div0 (interp0_div_by_zero),
.ovf (interp0_overflow)
);
// division unit 1
div_uu #(2*point_width) dut1 (
.clk (clk_i),
.ena (division_enable),
.z ({edge1_i[point_width-1:0], zeroes}),
.d (area_i[point_width-1:0]),
.q (interp1_quotient),
.s (interp1_reminder),
.div0 (interp1_div_by_zero),
.ovf (interp1_overflow)
);
wire result_full;
wire result_valid;
wire [result_width:0] result_count;
wire result_deque = result_valid & (state == wait_state);
assign write_o = result_deque;
assign division_enable = ~result_full;
wire delay_valid;
wire [delay_width-1:0] delay_phase_counter;
wire division_complete = division_enable & delay_valid & (phase_counter == delay_phase_counter);
wire [point_width-1:0] delay_x, delay_y;
// Fifo for finished results
basic_fifo result_fifo(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( {interp0_quotient, interp1_quotient, delay_x, delay_y} ),
.enq_i ( division_complete ),
.full_o ( result_full ), // TODO: use?
.count_o ( result_count ),
.data_o ( {factor0_o, factor1_o, x_o, y_o} ),
.valid_o ( result_valid ),
.deq_i ( result_deque )
);
defparam result_fifo.fifo_width = 4*point_width;
defparam result_fifo.fifo_bit_depth = result_width;
// Another Fifo for current calculations
basic_fifo queue_fifo(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( {phase_counter, x_i, y_i} ),
.enq_i ( write_i ),
.full_o ( ), // TODO: use?
.count_o ( ),
.data_o ( {delay_phase_counter, delay_x, delay_y} ),
.valid_o ( delay_valid ),
.deq_i ( division_complete )
);
defparam queue_fifo.fifo_width = delay_width + 2*point_width;
defparam queue_fifo.fifo_bit_depth = delay_width;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ans1, ans2; int n; char s[111111]; long long a[111111], pa[111111], b[111111], pb[111111]; inline long long get(long long x, int first) { long long t = first, ans = 0; while (t <= x) { ans += (x + 1 - t); t += 2; } return ans; } inline void solve(long long *a, long long *b, int n) { long long sum1 = 0, sum2 = 0; for (int i = 1; i <= n; i++) { if (b[i] % 2 == 0) { int r = b[i] + a[i] - 1; if (r % 2 == 0) sum1 += a[i] / 2, sum2 += a[i] / 2 + 1; else if (r % 2 == 1) sum1 += a[i] / 2, sum2 += a[i] / 2; } else if (b[i] % 2 == 1) { int r = b[i] + a[i] - 1; if (r % 2 == 0) sum1 += a[i] / 2, sum2 += a[i] / 2; else if (r % 2 == 1) sum1 += a[i] / 2 + 1, sum2 += a[i] / 2; } } for (int i = 1; i <= n; i++) { int r = b[i] + a[i] - 1; if (b[i] % 2 == 0) { if (r % 2 == 0) sum1 -= a[i] / 2, sum2 -= a[i] / 2 + 1; else if (r % 2 == 1) sum1 -= a[i] / 2, sum2 -= a[i] / 2; } else if (b[i] % 2 == 1) { if (r % 2 == 0) sum1 -= a[i] / 2, sum2 -= a[i] / 2; else if (r % 2 == 1) sum1 -= a[i] / 2 + 1, sum2 -= a[i] / 2; } if (b[i] % 2 == 0) { if (r % 2 == 0) ans2 += (a[i] / 2) * sum2, ans2 += (a[i] / 2 + 1) * sum1, ans1 += (a[i] / 2) * sum1, ans1 += (a[i] / 2 + 1) * sum2; else if (r % 2 == 1) ans2 += (a[i] / 2) * sum2, ans2 += (a[i] / 2) * sum1, ans1 += (a[i] / 2) * sum1, ans1 += (a[i] / 2) * sum2; } else if (b[i] % 2 == 1) { if (r % 2 == 0) ans2 += (a[i] / 2) * sum2, ans2 += (a[i] / 2) * sum1, ans1 += (a[i] / 2) * sum1, ans1 += (a[i] / 2) * sum2; else if (r % 2 == 1) ans2 += (a[i] / 2) * sum1, ans2 += (a[i] / 2 + 1) * sum2, ans1 += (a[i] / 2) * sum2, ans1 += (a[i] / 2 + 1) * sum1; } ans1 += get(a[i], 1); ans2 += get(a[i], 2); } } int main() { scanf( %s , s); int len = strlen(s); int t = 1; a[1] = 1; pa[1] = 0; for (int i = 1; i < len; i++) if (s[i - 1] == s[i]) a[t]++; else a[++t] = 1, pa[t] = i; int t1 = 0; for (int i = 1; i <= t; i++) if (i % 2 == 1) b[++t1] = a[i], pb[t1] = pa[i]; ans1 = 0, ans2 = 0; solve(b, pb, t1); t1 = 0; for (int i = 1; i <= t; i++) if (i % 2 == 0) b[++t1] = a[i], pb[t1] = pa[i]; solve(b, pb, t1); cout << ans2 << << ans1 << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( O3 ) using namespace std; const int N = 1e6 + 5; int n, p = 1, pa[N]; int ch[N][26]; vector<int> cnt[N][2]; vector<pair<int, int> > as; long long ans; inline void dfs(int u, int dep) { for (register int i = 0; i <= 25; ++i) { int v = ch[u][i]; if (v) { dfs(v, dep + 1); for (register int j = 0; j < cnt[v][0].size(); ++j) cnt[u][0].push_back(cnt[v][0][j]); for (register int j = 0; j < cnt[v][1].size(); ++j) cnt[u][1].push_back(cnt[v][1][j]); } } ans += min(cnt[u][0].size(), cnt[u][1].size()) * dep; for (register int i = min(cnt[u][0].size(), cnt[u][1].size()) - 1; i > -1; --i) { as.push_back( {cnt[u][0][cnt[u][0].size() - 1], cnt[u][1][cnt[u][1].size() - 1]}); cnt[u][0].pop_back(); cnt[u][1].pop_back(); } } string a; int main() { cin >> n; for (register int id = 1; id <= n; ++id) { cin >> a; int u = 1; for (register int i = 0; i < a.size(); ++i) { int c = a[i] - a ; if (ch[u][c] == 0) ch[u][c] = ++p; u = ch[u][c]; } cnt[u][0].push_back(id); } for (register int id = 1; id <= n; ++id) { cin >> a; int u = 1; for (int i = 0; i < a.size(); ++i) { int c = a[i] - a ; if (!ch[u][c]) ch[u][c] = ++p; u = ch[u][c]; } cnt[u][1].push_back(id); } dfs(1, 0); printf( %d n , ans); for (register int i = 0; i <= n - 1; ++i) printf( %d %d n , as[i].first, as[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int l[300005], r[300005]; int main() { int n; scanf( %d , &n); int lm = -1, rm = 0x3f3f3f3f; int ansl = 0, ansr = 0; for (int i = 1; i <= n; i++) { scanf( %d%d , &l[i], &r[i]); if (l[i] > lm) { ansl = i; lm = l[i]; } if (r[i] < rm) { ansr = i; rm = r[i]; } } int lmm = 0x3f3f3f3f, rmm = -1; for (int i = 1; i <= n; i++) { if (l[i] == lm && lmm > r[i]) { lmm = r[i]; ansl = i; } if (r[i] == rm && rmm < l[i]) { rmm = l[i]; ansr = i; } } if (ansl == ansr) { int lll = -1, rrr = 0x3f3f3f3f; for (int i = 1; i <= n; i++) { if (i == ansl) continue; lll = max(lll, l[i]); rrr = min(rrr, r[i]); } if (rrr <= lll) { printf( 0 n ); } else printf( %d n , rrr - lll); } else { int ll1 = -1, rr1 = 0x3f3f3f3f; for (int i = 1; i <= n; i++) { if (i == ansl) continue; ll1 = max(ll1, l[i]); rr1 = min(rr1, r[i]); } int ll2 = -1, rr2 = 0x3f3f3f3f; for (int i = 1; i <= n; i++) { if (i == ansr) continue; ll2 = max(ll2, l[i]); rr2 = min(rr2, r[i]); } if (ll2 >= rr2 && ll1 >= rr1) printf( 0 n ); else { int ans = max(rr2 - ll2, rr1 - ll1); printf( %d n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int f[1100000], p[1100000], n, m, a[110], b[30], c[30]; char cc; bool cmp(int a, int b) { return a > b; } void init() { scanf( %d , &n); for (int i = (1); i <= (n); ++i) scanf( %d , &a[i]); sort(a + 1, a + 1 + n, cmp); scanf( %d n , &n); for (int i = (0); i <= (n - 1); ++i) { scanf( %c%d n , &cc, &b[i]); c[i] = (cc == p ); } m = (1 << n) - 1; p[0] = 0; for (int i = (1); i <= (m); ++i) p[i] = p[i >> 1] + (i & 1); } void work() { int x, y; f[m] = 0; for (int i = (m - 1); i >= (0); --i) { x = p[i]; f[i] = b[x] == 2 ? 100000000 : -100000000; for (int j = (1); j <= (n); ++j) { y = 1 << (j - 1); if (i & y) continue; if (b[x] == 1) { if (c[x]) f[i] = max(f[i], a[j] + f[i ^ y]); else f[i] = max(f[i], f[i ^ y]); } else { if (c[x]) f[i] = min(f[i], f[i ^ y] - a[j]); else f[i] = min(f[i], f[i ^ y]); } } } cout << f[0]; } int main() { init(); work(); return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac2_tx(
input phy_tx_clk,
input tx_start,
output reg tx_done,
input [10:0] tx_count,
input [7:0] txb_dat,
output [10:0] txb_adr,
output reg phy_tx_en,
output reg [3:0] phy_tx_data
);
reg phy_tx_en_r;
reg phy_tx_data_sel;
wire [3:0] phy_tx_data_r = phy_tx_data_sel ? txb_dat[7:4] : txb_dat[3:0];
always @(posedge phy_tx_clk) begin
phy_tx_en <= phy_tx_en_r;
phy_tx_data <= phy_tx_data_r;
end
reg [10:0] byte_count;
reg byte_count_reset;
reg byte_count_inc;
always @(posedge phy_tx_clk) begin
if(byte_count_reset)
byte_count <= 11'd0;
else if(byte_count_inc)
byte_count <= byte_count + 11'd1;
end
assign txb_adr = byte_count;
wire byte_count_max = byte_count == tx_count;
parameter IDLE = 2'd0;
parameter SEND_LO = 2'd1;
parameter SEND_HI = 2'd2;
parameter TERMINATE = 2'd3;
reg [1:0] state;
reg [1:0] next_state;
initial state <= IDLE;
always @(posedge phy_tx_clk)
state <= next_state;
always @(*) begin
phy_tx_en_r = 1'b0;
phy_tx_data_sel = 1'b0;
byte_count_reset = 1'b0;
byte_count_inc = 1'b0;
tx_done = 1'b0;
next_state = state;
case(state)
IDLE: begin
byte_count_reset = 1'b1;
if(tx_start)
next_state = SEND_LO;
end
SEND_LO: begin
byte_count_inc = 1'b1;
phy_tx_en_r = 1'b1;
phy_tx_data_sel = 1'b0;
next_state = SEND_HI;
end
SEND_HI: begin
phy_tx_en_r = 1'b1;
phy_tx_data_sel = 1'b1;
if(byte_count_max)
next_state = TERMINATE;
else
next_state = SEND_LO;
end
TERMINATE: begin
byte_count_reset = 1'b1;
tx_done = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long R[10 << 10][1 << 10]; int A[10 << 10]; int n, m, g, r; int main() { cin >> n >> m; int i, j; for (i = (0); i < (m); ++i) cin >> A[i]; cin >> g >> r; sort(A, A + m); for (i = (0); i < (m); ++i) for (j = (0); j < (g + 1); ++j) R[i][j] = (1LL << 60); R[0][0] = 0; deque<pair<long long, pair<int, int>>> q; q.push_front(make_pair(R[0][0], pair<int, int>(0, 0))); long long res = (1LL << 60); while (!q.empty()) { int pos = q.front().second.first; int rem = q.front().second.second; long long val = q.front().first; q.pop_front(); if (R[pos][rem] != val) continue; if (pos == m - 1) res = min(res, val); int p[] = {pos - 1, pos + 1}; int d[] = {pos == 0 ? -1 : A[pos] - A[pos - 1], pos + 1 == m ? -1 : A[pos + 1] - A[pos]}; for (i = (0); i < (2); ++i) if (0 <= p[i] && p[i] < m && d[i] > 0 && rem + d[i] <= g) { int pos2 = p[i]; int rem2 = rem + d[i]; int val2 = val + d[i]; if (R[pos2][rem2] > val2) { R[pos2][rem2] = val2; q.push_front(make_pair(R[pos2][rem2], pair<int, int>(pos2, rem2))); } } if (rem == g) { int pos2 = pos; int rem2 = 0; int val2 = val + r; if (R[pos2][rem2] > val2) { R[pos2][rem2] = val2; q.push_back(make_pair(R[pos2][rem2], pair<int, int>(pos2, rem2))); } } } if (res == (1LL << 60)) res = -1; cout << res << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_2_V
`define SKY130_FD_SC_LP__DFBBN_2_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfbbn_2 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_2_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:13:38 12/14/2015
// Design Name: uart_rx
// Module Name: H:/Firmware/font5_base_new/font5_base/font5-firmware/UART_RX_TB.v
// Project Name: font5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart_rx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module UART_RX_TB;
// Inputs
reg reset;
reg clk = 0;
reg [1:0] baud_rate = 2 ;
//reg uld_rx_data;
reg rx_enable = 1;
reg rx_in;
// Outputs
wire [7:0] rx_data;
//wire rx_empty;
wire byte_rdy;
wire uart_rx_unload;
//localparam real BAUD_PERIOD = 2170.139; // 460.8 kBaud
localparam real BAUD_PERIOD = 104166.667; // 9600 Baud
//localparam real BAUD_PERIOD = 8680.556; // 115.2 kBaud
// Instantiate the Unit Under Test (UUT)
/*uart uut ( // Original version of the UART from FBFW (Ben)
.reset(reset),
.txclk(),
.ld_tx_data(),
.tx_data(),
.tx_enable(),
.tx_out(),
.tx_empty(),
.rxclk(clk),
.uld_rx_data(uart_rx_unload),
.rx_data(rx_data),
.rx_enable(rx_enable),
.rx_in(rx_in),
.rx_empty(rx_empty)
);*/
uart2_rx #(8, 9600) uut1 ( // new variable Baud UART_RX
.reset(reset),
.clk(clk),
.uld_rx_data(uart_rx_unload),
.rx_data(rx_data),
.rx_enable(rx_enable),
.rx_in(rx_in),
.byte_rdy(byte_rdy)
);
/*uart_rx uut1( // original UART_RX from FONT5_base
.reset(reset),
.clk(clk),
.baud_rate(baud_rate),
.uld_rx_data(uart_rx_unload),
.rx_data(rx_data),
.rx_enable(rx_enable),
.rx_in(rx_in),
.rx_empty(byte_rdy)
);*/
wire [6:0] ctrl_reg_addr;
wire ctrl_reg_strb;
wire [6:0] ctrl_reg_data;
wire [14:0] gainlut_ld_addr;
wire [4:0] gainlut_ld_select;
wire [6:0] gainlut_ld_data;
wire gainlut_ld_en;
wire full_rst_trig;
wire delay_trig1;
wire delay_trig2;
wire delay_trig3;
wire clk357_idelay_rst;
wire clk357_idelay_trig;
wire trim_dac_trig;
wire poll_uart;
wire pulse_ctr_rst;
uart_decoder3 uut2 (
.clk(clk),
.rst(reset),
.data_in(rx_data),
.byte_rdy(byte_rdy),
.byte_uld(uart_rx_unload),
.current_addr(ctrl_reg_addr),
.data_strobe(ctrl_reg_strb),
.data_out(ctrl_reg_data),
.ram_addr(gainlut_ld_addr),
.ram_select(gainlut_ld_select),
.ram_data(gainlut_ld_data),
.ram_data_strobe(gainlut_ld_en),
.full_reset(full_rst_trig),
.p1_delay_trig(delay_trig1),
.p2_delay_trig(delay_trig2),
.p3_delay_trig(delay_trig3),
.clk357_idelay_rst(clk357_idelay_rst),
.clk357_idelay_trig(clk357_idelay_trig),
.trim_dac_trig(trim_dac_trig),
.poll_uart(poll_uart),
.pulse_ctr_rst(pulse_ctr_rst)
);
initial begin
// Initialize Inputs
reset = 0;
//clk = 0;
//baud_rate = 0;
//uld_rx_data = 0;
//rx_enable = 0;
rx_in = 1;
// Wait 100 ns for global reset to finish
#100 reset = 1;
#100 reset = 0;
#50 rx_in = 0; //start bit
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1; //stop bit
// Add stimulus here
end
initial forever #12.5 clk = ~clk;
endmodule
|
`default_nettype none
module scheduler2_allocate_rsv_station #(
parameter P_ALU2_PRIORITY_LEVEL = 4'h0
)(
//Register
input wire iORDER_LOCK,
input wire iORDER_0_VALID,
input wire iORDER_0_EX_SYS_REG,
input wire iORDER_0_EX_SYS_LDST,
input wire iORDER_0_EX_LOGIC,
input wire iORDER_0_EX_SHIFT,
input wire iORDER_0_EX_ADDER,
input wire iORDER_0_EX_MUL,
input wire iORDER_0_EX_SDIV,
input wire iORDER_0_EX_UDIV,
input wire iORDER_0_EX_LDST,
input wire iORDER_0_EX_BRANCH,
input wire iORDER_1_VALID,
input wire iORDER_1_EX_SYS_REG,
input wire iORDER_1_EX_SYS_LDST,
input wire iORDER_1_EX_LOGIC,
input wire iORDER_1_EX_SHIFT,
input wire iORDER_1_EX_ADDER,
input wire iORDER_1_EX_MUL,
input wire iORDER_1_EX_SDIV,
input wire iORDER_1_EX_UDIV,
input wire iORDER_1_EX_LDST,
input wire iORDER_1_EX_BRANCH,
//RS-INFO
input wire [3:0] iRS1_COUNT,
input wire [3:0] iRS2_COUNT,
//Output
output wire oRS0_0_VALID,
output wire oRS1_0_VALID,
output wire oRS2_0_VALID,
output wire oRS3_0_VALID,
output wire oRS0_1_VALID,
output wire oRS1_1_VALID,
output wire oRS2_1_VALID,
output wire oRS3_1_VALID
);
//ALU1, 2
wire rs1_0_select;
wire rs1_1_select;
wire rs2_0_select;
wire rs2_1_select;
/*
reg b_alu_last;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_alu_last <= 1'b0;
end
else if(iRESET_SYNC)begin
b_alu_last <= 1'b0;
end
else begin
if(rs1_0_select)begin
b_alu_last <= 1'b0;
end
else if(rs2_0_select)begin
b_alu_last <= 1'b1;
end
else begin
b_alu_last <= b_alu_last;
end
end
end
*/
localparam PL_ALU_SEL_ALU1 = 1'h0;
localparam PL_ALU_SEL_ALU2 = 1'h1;
//[1]Valid bit, [0]0=Rs1/1=Rs2
function [1:0] func_alu_select;
//input func_alu_last;
input [3:0] func_alu1_cnt;
input [3:0] func_alu2_cnt;
input func_valid;
input func_ex_mul; //only ALU1
input func_ex_sdiv; //only ALU1
input func_ex_udiv; //only ALU1
input func_ex_logic;
input func_ex_shift;
input func_ex_adder;
input func_ex_sys_reg;
begin
if(!func_valid)begin
func_alu_select = 2'h0;
end
else begin
if(func_ex_mul || func_ex_sdiv || func_ex_udiv)begin
func_alu_select = {1'b1, PL_ALU_SEL_ALU1};
end
else if(func_ex_logic || func_ex_shift || func_ex_adder || func_ex_sys_reg)begin
if(func_alu1_cnt < (func_alu2_cnt-P_ALU2_PRIORITY_LEVEL))begin
func_alu_select = {1'b1, PL_ALU_SEL_ALU1};
end
else begin
func_alu_select = {1'b1, PL_ALU_SEL_ALU2};
end
end
else begin
func_alu_select = 2'h0;
end
end
end
endfunction
wire pipe0_alu_valid;
wire pipe0_alu_valid_number;
assign {pipe0_alu_valid, pipe0_alu_valid_number} = func_alu_select(
iRS1_COUNT,
iRS2_COUNT,
(!iORDER_LOCK && iORDER_0_VALID),
iORDER_0_EX_MUL,
iORDER_0_EX_SDIV,
iORDER_0_EX_UDIV,
iORDER_0_EX_LOGIC,
iORDER_0_EX_SHIFT,
iORDER_0_EX_ADDER,
iORDER_0_EX_SYS_REG
);
wire pipe1_alu_valid;
wire pipe1_alu_valid_number;
assign {pipe1_alu_valid, pipe1_alu_valid_number} = func_alu_select(
iRS1_COUNT,
iRS2_COUNT,
(!iORDER_LOCK && iORDER_1_VALID),
iORDER_1_EX_MUL,
iORDER_1_EX_SDIV,
iORDER_1_EX_UDIV,
iORDER_1_EX_LOGIC,
iORDER_1_EX_SHIFT,
iORDER_1_EX_ADDER,
iORDER_1_EX_SYS_REG
);
//RS0
assign oRS0_0_VALID = !iORDER_LOCK && iORDER_0_VALID && iORDER_0_EX_BRANCH;
assign oRS0_1_VALID = !iORDER_LOCK && iORDER_1_VALID && iORDER_1_EX_BRANCH;
/*
//RS1
assign oRS1_0_VALID = !iORDER_LOCK && iORDER_0_VALID && (iORDER_0_EX_MUL || iORDER_0_EX_SDIV || iORDER_0_EX_UDIV || ((iRS1_COUNT < iRS2_COUNT)? iORDER_0_EX_LOGIC || iORDER_0_EX_SHIFT || iORDER_0_EX_ADDER || iORDER_0_EX_SYS_REG : 1'b0));
assign oRS1_1_VALID = !iORDER_LOCK && iORDER_1_VALID && (iORDER_1_EX_MUL || iORDER_1_EX_SDIV || iORDER_1_EX_UDIV || ((iRS1_COUNT < iRS2_COUNT)? iORDER_1_EX_LOGIC || iORDER_1_EX_SHIFT || iORDER_1_EX_ADDER || iORDER_1_EX_SYS_REG : 1'b0));
//RS2
assign oRS2_0_VALID = !iORDER_LOCK && iORDER_0_VALID && ((iRS1_COUNT < iRS2_COUNT)? 1'b0 : iORDER_0_EX_LOGIC || iORDER_0_EX_SHIFT || iORDER_0_EX_ADDER || iORDER_0_EX_SYS_REG);
assign oRS2_1_VALID = !iORDER_LOCK && iORDER_1_VALID && ((iRS1_COUNT < iRS2_COUNT)? 1'b0 : iORDER_1_EX_LOGIC || iORDER_1_EX_SHIFT || iORDER_1_EX_ADDER || iORDER_1_EX_SYS_REG);
*/
//RS1
assign oRS1_0_VALID = pipe0_alu_valid && (pipe0_alu_valid_number == PL_ALU_SEL_ALU1); //rs1_0_select;
assign oRS1_1_VALID = pipe1_alu_valid && (pipe1_alu_valid_number == PL_ALU_SEL_ALU1); //rs1_1_select;
//RS2
assign oRS2_0_VALID = pipe0_alu_valid && (pipe0_alu_valid_number == PL_ALU_SEL_ALU2); //rs2_0_select;
assign oRS2_1_VALID = pipe1_alu_valid && (pipe1_alu_valid_number == PL_ALU_SEL_ALU2); //rs2_1_select;
//RS3
assign oRS3_0_VALID = !iORDER_LOCK && iORDER_0_VALID && (iORDER_0_EX_LDST || iORDER_0_EX_SYS_LDST);
assign oRS3_1_VALID = !iORDER_LOCK && iORDER_1_VALID && (iORDER_1_EX_LDST || iORDER_1_EX_SYS_LDST);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; template <typename T> bool chkmax(T &x, T y) { return x < y ? x = y, true : false; } template <typename T> bool chkmin(T &x, T y) { return x > y ? x = y, true : false; } int readint() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, k; int a[20]; bitset<2001> d[66000]; multiset<pair<int, int> > s; void solve(int now, int cs, int r) { if (!now) return; while (cs <= 2000) { for (int i = 1; i <= n; i++) { if (((now >> (i - 1)) & 1) && cs >= a[i] && d[now ^ (1 << (i - 1))][cs - a[i]]) { s.insert(make_pair(-r, a[i])); solve(now ^ (1 << (i - 1)), cs - a[i], r); return; } } cs = cs * k, r++; } assert(0); } int main() { n = readint(); k = readint(); for (int i = 1; i <= n; i++) a[i] = readint(); d[0][0] = 1; for (int i = 1; i < (1 << n); i++) { for (int j = 1; j <= n; j++) if ((i >> (j - 1)) & 1) d[i] |= d[i ^ (1 << (j - 1))] << a[j]; for (int j = 2000 / k; j >= 1; j--) if (d[i][j * k]) d[i][j] = 1; } if (!d[(1 << n) - 1][1]) return printf( NO n ), 0; printf( YES n ); solve((1 << n) - 1, 1, 0); while (s.size() > 1) { auto it1 = s.begin(), it2 = it1; it2++; assert(it1->first == it2->first); printf( %d %d n , it1->second, it2->second); int tmp = it1->second + it2->second, dep = -it1->first; while (tmp % k == 0) tmp /= k, dep--; s.erase(it1); s.erase(it2); s.insert(make_pair(-dep, tmp)); } return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module changes the alpha value of every pixel of a specific color. *
* *
******************************************************************************/
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Set_Black_Transparent (
// Global Signals
clk,
reset,
// Input Stream
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_in_ready,
// Output Stream
stream_out_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 29; // Frame's Data Width (color portion only)
parameter DW = 39; // Frame's Data Width
parameter COLOR = 30'd0; // Color to apply alpha value
parameter ALPHA = 10'd0; // The alpha value to apply
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Global Signals
input clk;
input reset;
// Input Stream
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
output stream_in_ready;
// Output Stream
input stream_out_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign converted_data = (stream_in_data[CW:0] == COLOR) ?
{ALPHA, stream_in_data[CW:0]} :
stream_in_data;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, cc = 0; cin >> a >> b >> c; if (a < 0 || b < 2 || c < 4) cout << 0 << endl; else { while (a >= 1 && b >= 2 && c >= 4) { cc++; a--; b -= 2; c -= 4; } cout << cc * 7 << endl; } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_hc(clock, resetn, dataa, datab, result, valid_in, valid_out, stall_in, stall_out);
// This is a version of the adder with reduced latency.
input clock, resetn;
input valid_in, stall_in;
output valid_out, stall_out;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(valid_in),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_out),
.enable());
defparam core.HIGH_LATENCY = 1;
defparam core.HIGH_CAPACITY = 1;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g_gmii
*/
module test_eth_mac_1g_gmii;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg gtx_clk = 0;
reg gtx_rst = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg gmii_rx_clk = 0;
reg [7:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg mii_tx_clk = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire rx_clk;
wire rx_rst;
wire tx_clk;
wire tx_rst;
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire gmii_tx_clk;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire tx_error_underflow;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire [1:0] speed;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
gtx_clk,
gtx_rst,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
gmii_rx_clk,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
mii_tx_clk,
ifg_delay
);
$to_myhdl(
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tready,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_tx_clk,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
tx_error_underflow,
rx_error_bad_frame,
rx_error_bad_fcs,
speed
);
// dump file
$dumpfile("test_eth_mac_1g_gmii.lxt");
$dumpvars(0, test_eth_mac_1g_gmii);
end
eth_mac_1g_gmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.gtx_clk(gtx_clk),
.gtx_rst(gtx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(gmii_rx_clk),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_tx_clk(gmii_tx_clk),
.mii_tx_clk(mii_tx_clk),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.speed(speed),
.ifg_delay(ifg_delay)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int l, d, v, g, r, tmu; double tm, tmod; scanf( %d%d%d%d%d , &l, &d, &v, &g, &r); tmu = (int)((long double)(d / v) / (g + r)); tmod = (double)d / v - tmu * (g + r); if (tmod < g) tm = (double)l / v; else tm = (double)l / v + (r - tmod + g); printf( %.8f n , tm); return 0; }
|
/*
* FrameWriter.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1ns / 1ps
module FrameWriter (
input clk,
input rst,
input [23:0] din_data,
input din_valid,
output wire din_ready,
input wire din_sop,
input wire din_eop,
output wire [DATA_WIDTH-1:0] data_fifo_out,
output wire data_valid_fifo_out,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out,
input start,
output endf
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg video_reg;
wire set_video;
wire reset_video;
reg [1:0] run;
always @ (posedge clk) begin
if (start == 1) begin
video_reg <= 0;
end else begin
if (reset_video == 1) begin
video_reg <= 0;
end
if (set_video == 1) begin
video_reg <= 1;
end
end
end
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (reset_video == 1) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
assign set_video = (din_sop == 1) & (din_data == 0) & (din_valid == 1) & (run == 1);
assign reset_video = (din_eop == 1) & (din_valid == 1) & (video_reg == 1);
assign data_fifo_out = {8'd0, din_data};
assign data_valid_fifo_out = (video_reg == 1) & (din_valid == 1) & (run == 1);
assign din_ready = (usedw_fifo_out < (FIFO_DEPTH - 1));
assign endf = (run == 2);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<string, string> mp; set<string> s; for (int i = 0; i < n; i++) { string old, edg; cin >> old >> edg; mp[old] = edg; s.insert(edg); } map<string, string>::iterator p; p = mp.begin(); vector<pair<string, string>> a; for (p; p != mp.end(); p++) { if (s.count(p->first)) continue; string cur; cur = p->first; while (mp.count(cur)) { cur = mp[cur]; } a.push_back(make_pair(p->first, cur)); } cout << a.size() << n ; for (int i = 0; i < a.size(); i++) cout << a[i].first << << a[i].second << n ; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gsu_state.v when simulating
// the core, gsu_state. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gsu_state(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
// The Arithmetic/Logic Unit (ALU) is responsible for performing the arithmetic
// and bitwise logical operations the computer depends upon to calculate
// everything from effective addresses for looking stuff up in memory, all the
// way to medical imaging. (OK, the latter might have some help from floating
// point units later on, but I digress.)
module alu(
input [63:0] inA_i,
input [63:0] inB_i,
input cflag_i,
input sum_en_i,
input and_en_i,
input xor_en_i,
input invB_en_i,
input lsh_en_i,
input rsh_en_i,
input ltu_en_i, // See issue https://github.com/KestrelComputer/polaris/issues/18
input lts_en_i, // See issue https://github.com/KestrelComputer/polaris/issues/18
output [63:0] out_o,
output cflag_o,
output vflag_o,
output zflag_o
);
wire [63:0] b = inB_i ^ ({64{invB_en_i}});
wire [63:0] sumL = inA_i[62:0] + b[62:0] + {62'b0, cflag_i};
wire c62 = sumL[63];
wire [64:63] sumH = inA_i[63] + b[63] + c62;
wire [63:0] rawSums = {sumH[63], sumL[62:0]};
wire [63:0] sums = sum_en_i ? rawSums : 64'd0;
assign zflag_o = ~(|out_o);
assign vflag_o = sumH[64] ^ sumL[63];
assign cflag_o = sumH[64];
wire [63:0] ands = and_en_i ? (inA_i & b) : 64'd0;
wire [63:0] xors = xor_en_i ? (inA_i ^ b) : 64'd0;
wire [63:0] lsh32 = inB_i[5] ? {inA_i[31:0], 32'd0} : inA_i;
wire [63:0] lsh16 = inB_i[4] ? {lsh32[47:0], 16'd0} : lsh32;
wire [63:0] lsh8 = inB_i[3] ? {lsh16[55:0], 8'd0} : lsh16;
wire [63:0] lsh4 = inB_i[2] ? {lsh8[59:0], 4'd0} : lsh8;
wire [63:0] lsh2 = inB_i[1] ? {lsh4[61:0], 2'd0} : lsh4;
wire [63:0] lsh1 = inB_i[0] ? {lsh2[62:0], 1'd0} : lsh2;
wire [63:0] lshs = lsh_en_i ? lsh1 : 0;
wire [63:32] sx5 = cflag_i ? {32{inA_i[63]}} : 0;
wire [63:0] rsh32 = inB_i[5] ? {sx5, inA_i[63:32]} : inA_i;
wire [63:48] sx4 = cflag_i ? {16{rsh32[63]}} : 0;
wire [63:0] rsh16 = inB_i[4] ? {sx4, rsh32[63:16]} : rsh32;
wire [63:56] sx3 = cflag_i ? {8{rsh16[63]}} : 0;
wire [63:0] rsh8 = inB_i[3] ? {sx3, rsh16[63:8]} : rsh16;
wire [63:60] sx2 = cflag_i ? {4{rsh8[63]}} : 0;
wire [63:0] rsh4 = inB_i[2] ? {sx2, rsh8[63:4]} : rsh8;
wire [63:62] sx1 = cflag_i ? {2{rsh4[63]}} : 0;
wire [63:0] rsh2 = inB_i[1] ? {sx1, rsh4[63:2]} : rsh4;
wire sx0 = cflag_i & rsh2[63];
wire [63:0] rsh1 = inB_i[0] ? {sx0, rsh2[63:1]} : rsh2;
wire [63:0] rshs = rsh_en_i ? rsh1 : 0;
wire [63:0] isLTS = lts_en_i ? {63'd0, rawSums[63] ^ vflag_o} : 0;
wire [63:0] isLTU = ltu_en_i ? {63'd0, ~cflag_o} : 0;
assign out_o = sums | ands | xors | lshs | rshs | isLTS | isLTU;
endmodule
|
module D_posedge_async(output Q, Qn, input clr_l, pre_l, D, clk);
wire [3:0]n_out; /* level 1 nand outputs */
/* level 1 nands */
nand lnand0(n_out[0], pre_l, n_out[1], n_out[3]),
lnand1(n_out[1], n_out[0], clk, clr_l),
lnand2(n_out[2], n_out[1], clk, n_out[3]),
lnand3(n_out[3], D, n_out[2], clr_l);
/* level 2 nands */
nand unand0(Q, n_out[1], pre_l, Qn),
unand1(Qn, n_out[2], Q, clr_l);
endmodule
module mux2(output Q, input X, Y, sel);
not(sel_l, sel);
and(d1, X, sel_l);
and(d2, Y, sel);
or (Q,d1,d2);
endmodule
module r4(output [3:0]Q, input dir, clk, reset_l);
wire [2:0]ex;
nor(Q[3], Q[0], Q[1], Q[2]);
mux2 m0(ex[0], Q[3] , Q[1], dir),
m1(ex[1], Q[0], Q[2], dir),
m2(ex[2], Q[1], Q[3], dir);
D_posedge_async d0(Q[0], , reset_l, 1, ex[0], clk),
d1(Q[1], , reset_l, 1, ex[1], clk),
d2(Q[2], , reset_l, 1, ex[2], clk);
endmodule
module p17_tb();
wire [3:0]Q;
reg clk, dir, reset_l;
integer i;
r4 device(Q, dir, clk, reset_l);
initial begin
$dumpfile("p17.vcd");
$dumpvars(0,device);
clk = 0;
dir = 0;
#5 reset_l = 0;
#5 reset_l = 1;
for (i = 0; i < 10; i = i + 1) begin
#10
clk = 1;
#10
clk = 0;
end
dir = 1;
for (i = 0; i < 10; i = i + 1) begin
#10
clk = 1;
#10
clk = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, Q; string s[200200]; int ep[200200]; int len[200200]; struct data { int to, nxt; } mp[400400]; int head[200200], cnt; void link(int x, int y) { mp[++cnt].to = y; mp[cnt].nxt = head[x]; head[x] = cnt; } int id[200200], clk; int siz[200200]; void dfs(int x) { id[x] = ++clk; siz[x] = 1; for (int i = head[x]; i; i = mp[i].nxt) dfs(mp[i].to), siz[x] += siz[mp[i].to]; } struct Bit { int C[200200]; int ma; int lb(int x) { return x & (-x); } void ins(int x) { while (x <= ma) C[x]++, x += lb(x); } int ask(int x) { int r = 0; while (x) r += C[x], x -= lb(x); return r; } int query(int l, int r) { return ask(r) - ask(l - 1); } } bit; struct AC_AM { int ch[200200][26], tot; void ins(int x) { int u = 1, c; for (int i = 0; i < len[x]; ++i) { c = s[x][i] - a ; if (!ch[u][c]) { ch[u][c] = ++tot; } u = ch[u][c]; } ep[x] = u; } queue<int> q; int fail[200200]; void getfail() { for (int i = 0; i < 26; ++i) if (ch[1][i]) q.push(ch[1][i]), fail[ch[1][i]] = 1; int u, v; while (!q.empty()) { u = q.front(); q.pop(); for (int c = 0; c < 26; ++c) { v = ch[u][c]; if (!v) ch[u][c] = max(ch[fail[u]][c], 1); else { fail[v] = max(ch[fail[u]][c], 1); q.push(v); } } } for (int i = 2; i <= tot; ++i) link(fail[i], i); } void in(int x) { int u = 1, c; for (int i = 0; i < len[x]; ++i) { bit.ins(id[u]); c = s[x][i] - a ; u = ch[u][c]; } bit.ins(id[u]); } } AC; struct Que { int k, p, sym, id; bool operator<(const Que &o) const { return p < o.p; } } que[1000100]; int tq; int ans[500500]; int calc(int x) { return bit.query(id[ep[x]], id[ep[x]] + siz[ep[x]] - 1); } int main() { scanf( %d%d , &n, &Q); AC.tot = 1; for (int i = 1; i <= n; ++i) { cin >> s[i]; len[i] = s[i].size(); AC.ins(i); } AC.getfail(); dfs(1); int xx, yy, kk; for (int i = 1; i <= Q; ++i) { scanf( %d%d%d , &xx, &yy, &kk); que[++tq] = (Que){kk, xx - 1, -1, i}; que[++tq] = (Que){kk, yy, 1, i}; } sort(que + 1, que + tq + 1); int cur = 1; while (que[cur].p == 0) cur++; bit.ma = AC.tot; for (int i = 1; i <= n; ++i) { AC.in(i); while (que[cur].p == i && cur <= tq) { ans[que[cur].id] += que[cur].sym * calc(que[cur].k), cur++; } } for (int i = 1; i <= Q; ++i) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> const int N = 123456; int arr[N], i, j; using namespace std; int main() { long long n, k, a, b, ans1 = 0, ans2 = 0, ans = 0; scanf( %lld %lld , &n, &k); scanf( %lld %lld , &a, &b); ans1 = (n - 1) * a; if (k == 1) return cout << ans1 << endl, 0; while (n != 0 && n != 1) { if (n % k == 0) { if (b < a * (n - n / k)) ans += b; else ans += a * (n - n / k); n = n / k; } else { ans += ((n % k) * a); n = n - (n % k); } } if (n == 0) ans -= a; printf( %lld n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLRBP_BEHAVIORAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; void main2() { long long int n, m, sum = 0, t = INT_MAX, temp, r = 0; cin >> n >> m; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { cin >> temp; if (temp < 0) r++; sum += abs(temp); t = min(t, abs(temp)); } } if (r % 2 == 0) cout << sum << n ; else cout << sum - 2 * t << n ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; cin >> t; while (t--) { main2(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_TB_V
`define SKY130_FD_SC_LS__O31AI_TB_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n; int a[n][2]; for (int i = 0; i < n; ++i) cin >> a[i][0] >> a[i][1]; cin >> k; for (int i = 0; i < n; ++i) { if (a[i][0] <= k && k <= a[i][1]) { cout << n - i; return 0; } } }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Test_Line.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Test_Line (
address,
clock,
q);
input [0:0] address;
input clock;
output [7:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "line"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Test_Line.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Test_Line.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=line"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_Line_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { char ch; int n, cnt = 0; long long x, a; scanf( %d%I64d , &n, &x); for (int i = 0; i < n; i++) { while (isspace(ch = getchar())) ; scanf( %I64d , &a); if (ch == + ) x += a; else { if (x < a) cnt++; else x -= a; } } cout << x << << cnt << endl; return 0; }
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#include <bits/stdc++.h> int main() { long long b; scanf( %lld , &b); long long flag = 0; for (long long i = 1; i < sqrt(b); i++) if (b % i == 0) flag = flag + 1; flag = 2 * flag; long long a = sqrt(b); if (a * a == b) flag = flag + 1; printf( %lld , flag); }
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#include <bits/stdc++.h> using namespace std; int a[300005], b[300005]; int main() { int i, k, t, x, y, n, q, num1, num2; string s; scanf( %d , &t); for (i = 0; i < t; i++) { scanf( %d %d , &n, &q); cin >> s; s = + s; for (k = 0; k <= n; k++) a[k] = b[k] = 0; if (s[1] == + ) a[1] = a[2] = 1; else a[1] = a[2] = -1; if (s[2] == + ) b[2] = 1; else b[2] = -1; for (k = 3; k <= n; k++) { if (k % 2 == 1) { if (s[k] == + ) a[k] = a[k - 2] + 1; else a[k] = a[k - 2] - 1; b[k] = b[k - 1]; } else { if (s[k] == + ) b[k] = b[k - 2] + 1; else b[k] = b[k - 2] - 1; a[k] = a[k - 1]; } } for (k = 0; k < q; k++) { scanf( %d %d , &x, &y); num1 = a[y] - a[x - 1]; num2 = b[y] - b[x - 1]; if (abs(num1 - num2) > 2) { if (abs(num1 - num2) % 2 == 1) printf( 1 n ); else printf( 2 n ); } else printf( %d n , abs(num1 - num2)); } } return 0; }
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; const int INFINITE = 0x3f3f3f3f; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline T lowbit(T n) { return (n ^ (n - 1)) & n; } template <class T> inline int countbit(T n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } typedef vector<int> VI; typedef vector<VI> VII; typedef vector<string> VS; const long long MAXP = 1000000LL; long long add(string a, string b, string c) { if (a.size() == 0 || b.size() == 0 || c.size() == 0) return -1LL * INFINITE; if ((a.size() > 1 && a[0] == 0 ) || (b.size() > 1 && b[0] == 0 ) || (c.size() > 1 && c[0] == 0 )) return -1LL * INFINITE; if (a.size() > 7 || b.size() > 7 || c.size() > 7) return -1LL * INFINITE; long long aa = 0; for (int i = (int)(0); i < (int)(a.size()); i++) aa = aa * 10 + (a[i] - 0 ); if (aa > MAXP) return -1LL * INFINITE; long long bb = 0; for (int i = (int)(0); i < (int)(b.size()); i++) bb = bb * 10 + (b[i] - 0 ); if (bb > MAXP) return -1LL * INFINITE; long long cc = 0; for (int i = (int)(0); i < (int)(c.size()); i++) cc = cc * 10LL + (c[i] - 0 ); if (cc > MAXP) return -1LL * INFINITE; return (aa + bb + cc); } int main() { ios::sync_with_stdio(false); string s; cin >> s; int l = (int)s.size(); long long maxm = -1LL * INFINITE; for (int i = (int)(0); i < (int)(l - 2); i++) for (int j = (int)(i + 1); j < (int)(l - 1); j++) { string a = s.substr(0, i + 1); string b = s.substr(i + 1, j - i); string c = s.substr(j + 1); checkmax(maxm, add(a, b, c)); } if (maxm == -1LL * INFINITE) cout << -1 n ; else cout << maxm << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void run() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int32_t main() { run(); vector<long long> dp((long long)(3e6), 0); dp[3] = 4; for (long long i = 4; i < (long long)(3e6); i++) { long long temp1 = (2 * dp[i - 2] + dp[i - 1]); long long temp2 = 4 + (4 * dp[i - 4] + 4 * dp[i - 3] + dp[i - 2]); if (i % 3 == 0) { dp[i] = temp2; } else { dp[i] = temp1; } dp[i] %= (long long)(1e9 + 7); } long long t; cin >> t; while (t--) { long long n; cin >> n; cout << dp[n] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; char b[1000001]; int main() { int n, i, c = 0, k = 0, f1 = 0; long int z = 0; cin >> n; int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 0) c++; } while (c != n) { if (k == 0) { for (i = 0; i < n; i++) { f1 = 0; if (a[i] != 0) { b[z] = P ; z++; a[i]--; if (a[i] == 0) { c++; f1 = 1; } if (i == n - 1 && c != n) { b[z] = L ; z++; } else if (c != n) { b[z] = R ; z++; } } if (c == n) break; if (a[i] == 0 && f1 == 0 && i == n - 1) { b[z] = L ; z++; } else if (a[i] == 0 && f1 == 0) { b[z] = R ; z++; } } k = 1; } else { for (i = n - 2; i > 0; i--) { f1 = 0; if (a[i] != 0) { b[z] = P ; z++; a[i]--; if (a[i] == 0) { f1 = 1; c++; } if (c != n) { b[z] = L ; z++; } } if (c == n) break; if (a[i] == 0 && f1 == 0) { b[z] = L ; z++; } } k = 0; } } cout << b; return 0; }
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// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: digilentinc.com:ip:pmod_bridge:1.0
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PmodJSTK_pmod_bridge_0_0 (
in0_I,
in1_I,
in2_I,
in3_I,
in0_O,
in1_O,
in2_O,
in3_O,
in0_T,
in1_T,
in2_T,
in3_T,
out0_I,
out1_I,
out2_I,
out3_I,
out4_I,
out5_I,
out6_I,
out7_I,
out0_O,
out1_O,
out2_O,
out3_O,
out4_O,
out5_O,
out6_O,
out7_O,
out0_T,
out1_T,
out2_T,
out3_T,
out4_T,
out5_T,
out6_T,
out7_T
);
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_I" *)
output wire in0_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_I" *)
output wire in1_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_I" *)
output wire in2_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_I" *)
output wire in3_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_O" *)
input wire in0_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_O" *)
input wire in1_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_O" *)
input wire in2_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_O" *)
input wire in3_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_T" *)
input wire in0_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_T" *)
input wire in1_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_T" *)
input wire in2_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_T" *)
input wire in3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_I" *)
input wire out0_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_I" *)
input wire out1_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_I" *)
input wire out2_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_I" *)
input wire out3_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_I" *)
input wire out4_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_I" *)
input wire out5_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_I" *)
input wire out6_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_I" *)
input wire out7_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_O" *)
output wire out0_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_O" *)
output wire out1_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_O" *)
output wire out2_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_O" *)
output wire out3_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_O" *)
output wire out4_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_O" *)
output wire out5_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_O" *)
output wire out6_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_O" *)
output wire out7_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_T" *)
output wire out0_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_T" *)
output wire out1_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_T" *)
output wire out2_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_T" *)
output wire out3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_T" *)
output wire out4_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_T" *)
output wire out5_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_T" *)
output wire out6_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_T" *)
output wire out7_T;
pmod_concat #(
.Top_Row_Interface("SPI"),
.Bottom_Row_Interface("Disabled")
) inst (
.in_top_bus_I(),
.in_top_bus_O(4'B0),
.in_top_bus_T(4'B0),
.in_top_uart_gpio_bus_I(),
.in_top_uart_gpio_bus_O(2'B1),
.in_top_uart_gpio_bus_T(2'B1),
.in_top_i2c_gpio_bus_I(),
.in_top_i2c_gpio_bus_O(2'B1),
.in_top_i2c_gpio_bus_T(2'B1),
.in_bottom_bus_I(),
.in_bottom_bus_O(4'B1),
.in_bottom_bus_T(4'B1),
.in_bottom_uart_gpio_bus_I(),
.in_bottom_uart_gpio_bus_O(2'B1),
.in_bottom_uart_gpio_bus_T(2'B1),
.in_bottom_i2c_gpio_bus_I(),
.in_bottom_i2c_gpio_bus_O(2'B1),
.in_bottom_i2c_gpio_bus_T(2'B1),
.in0_I(in0_I),
.in1_I(in1_I),
.in2_I(in2_I),
.in3_I(in3_I),
.in4_I(),
.in5_I(),
.in6_I(),
.in7_I(),
.in0_O(in0_O),
.in1_O(in1_O),
.in2_O(in2_O),
.in3_O(in3_O),
.in4_O(1'B1),
.in5_O(1'B1),
.in6_O(1'B1),
.in7_O(1'B1),
.in0_T(in0_T),
.in1_T(in1_T),
.in2_T(in2_T),
.in3_T(in3_T),
.in4_T(1'B1),
.in5_T(1'B1),
.in6_T(1'B1),
.in7_T(1'B1),
.out0_I(out0_I),
.out1_I(out1_I),
.out2_I(out2_I),
.out3_I(out3_I),
.out4_I(out4_I),
.out5_I(out5_I),
.out6_I(out6_I),
.out7_I(out7_I),
.out0_O(out0_O),
.out1_O(out1_O),
.out2_O(out2_O),
.out3_O(out3_O),
.out4_O(out4_O),
.out5_O(out5_O),
.out6_O(out6_O),
.out7_O(out7_O),
.out0_T(out0_T),
.out1_T(out1_T),
.out2_T(out2_T),
.out3_T(out3_T),
.out4_T(out4_T),
.out5_T(out5_T),
.out6_T(out6_T),
.out7_T(out7_T)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A41OI_BEHAVIORAL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41OI_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; string s[1005]; long long int M[1005][1005], T[1005][1005]; queue<pair<long long int, long long int> > q; long long int xr[] = {0, 0, -1, 1}; long long int xc[] = {-1, 1, 0, 0}; int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); long long int p, t, n, m, i, j, k, x, y, z, a, b, c; cin >> n >> m >> t; for (i = 0; i < n; ++i) cin >> s[i]; for (i = 0; i < n; ++i) { for (j = 0; j < m; ++j) { a = 0; for (k = 0; k < 4; ++k) { x = i + xr[k]; y = j + xc[k]; if (x < 0 || x >= n || y < 0 || y >= m) continue; a += (s[x][y] == s[i][j]); } if (a) { q.push(make_pair(i, j)); M[i][j] = 1; } else T[i][j] = LLONG_MAX; } } while (!q.empty()) { auto it = q.front(); q.pop(); i = it.first; j = it.second; a = b = c = 0; for (k = 0; k < 4; ++k) { x = i + xr[k]; y = j + xc[k]; if (x < 0 || x >= n || y < 0 || y >= m || M[x][y]) continue; if (s[x][y] != s[i][j]) { q.push(make_pair(x, y)); M[x][y] = 1; T[x][y] = T[i][j] + 1; } } } while (t--) { cin >> i >> j >> p; i -= 1; j -= 1; if (T[i][j] > p) cout << s[i][j] << endl; else cout << (((p - T[i][j]) & 1) ^ (s[i][j] - 0 )) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T, class V> T power(T t, V v) { T second = 1; while (v--) second *= t; return second; } void _print(long long t) { cerr << t; } void _print(int t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { int n = v.size(); cerr << [ ; for (T i : v) { _print(i); n--; cerr << (n ? , : ); } cerr << ] ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { int n = v.size(); cerr << { ; for (auto p : v) { cerr << [ ; _print(p.first); cerr << ]= ; _print(p.second); n--; cerr << (n ? , : ); } cerr << } ; } void go() { int n; cin >> n; string a; string b; cin >> a >> b; int sz = 0, so = 0, nsz = 0, nso = 0; for (int i = 0; i < n; i++) { if (a[i] == b[i]) { if (a[i] == 0 ) sz++; else so++; } else if (a[i] == 0 ) nsz++; else nso++; } int N = 100000000; int ans = N; if (so - sz == 1) ans = min(ans, so + sz); if (nsz == nso) ans = min(ans, nsz + nso); if (ans == N) cout << -1 n ; else cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; cin >> t; while (t--) { go(); } return 0; }
|
`timescale 1ns / 1ps
//File Name: VGA7SegDisplay.v
//Author: Chris Miller
//Date: April, 2015
//Purpose: Generate seven-segment display with pixels on VGA display
//input:
// (digitXPosition, digitYPosition): upper left corner of the display
// (xpos, ypos): screen position where pixel digitpixel is located
// digit: decimal number to be displayed
// output
// digitpixel: 1-bit ON or OFF flag for pixel at (xpos, ypos)
module VGA7SegDisplay(input [9:0] digitXPosition, digitYPosition, xpos, ypos,
input [3:0] digit,
output reg digitpixel
);
//
parameter SegmentWidth = 10'd20, SegmentHeight = 10'd28, lineWidth = 10'd4;
wire segmentA = (xpos >= digitXPosition+lineWidth && xpos <= digitXPosition+SegmentWidth-4 && ypos >= digitYPosition && ypos <= digitYPosition+lineWidth-1);
wire segmentB = (xpos >= digitXPosition+SegmentWidth-lineWidth && xpos <= digitXPosition+SegmentWidth-1 && ypos >= digitYPosition && ypos <= digitYPosition+SegmentHeight/2-2);
wire segmentC = (xpos >= digitXPosition+SegmentWidth-lineWidth && xpos <= digitXPosition+SegmentWidth-1 && ypos >= digitYPosition+SegmentHeight/2+2 && ypos <= digitYPosition+SegmentHeight-1);
wire segmentD = (xpos >= digitXPosition+lineWidth && xpos <= digitXPosition+SegmentWidth-4 && ypos >= digitYPosition+SegmentHeight-lineWidth && ypos <= digitYPosition+SegmentHeight-1);
wire segmentE = (xpos >= digitXPosition && xpos <= digitXPosition+lineWidth-1 && ypos >= digitYPosition+SegmentHeight/2+2 && ypos <= digitYPosition+SegmentHeight-1);
wire segmentF = (xpos >= digitXPosition && xpos <= digitXPosition+lineWidth-1 && ypos >= digitYPosition && ypos <= digitYPosition+SegmentHeight/2-2);
wire segmentG = (xpos >= digitXPosition+lineWidth && xpos <= digitXPosition+SegmentWidth-1 && ypos >= digitYPosition+(SegmentHeight-lineWidth)/2 && ypos <= digitYPosition+(SegmentHeight+lineWidth)/2);
always @(digit,segmentA,segmentA,segmentB,segmentC,segmentD,segmentE,segmentF,segmentG)
case (digit)
0: digitpixel <= (segmentA | segmentB | segmentC | segmentD | segmentE | segmentF );
1: digitpixel <= (segmentB | segmentC );
2: digitpixel <= (segmentA | segmentB | segmentD | segmentE | segmentG );
3: digitpixel <= (segmentA | segmentB | segmentC | segmentD | segmentG );
4: digitpixel <= (segmentB | segmentC | segmentF | segmentG );
5: digitpixel <= (segmentA | segmentC | segmentD | segmentF | segmentG );
6: digitpixel <= (segmentA | segmentC | segmentD | segmentE | segmentF | segmentG );
7: digitpixel <= (segmentA | segmentB | segmentC );
8: digitpixel <= (segmentA | segmentB | segmentC | segmentD | segmentE | segmentF | segmentG );
9: digitpixel <= (segmentA | segmentB | segmentC | segmentD | segmentF | segmentG );
10: digitpixel <= (segmentA | segmentB | segmentC | segmentE | segmentF | segmentG );
default: digitpixel <= 0;
endcase
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-----------------------------------------------------------------------------------------------------------------------------
// Filename : cu_binari_tree.v
// Author : chewein
// Created : 2014-9-20
// Description : binarization the nxn block coeff
//-----------------------------------------------------------------------------------------------------------------------------
`include"enc_defines.v"
module cabac_binari_get_sig_ctx(
pattern_sig_ctx_i ,
scan_idx_i ,
pos_x_i ,
pos_y_i ,
tu_depth_i ,
coeff_type_i ,
ctx_pair_scf_addr_o
);
//-----------------------------------------------------------------------------------------------------------------------------
//
// input and output signals declaration
//
//-----------------------------------------------------------------------------------------------------------------------------
input [ 1:0 ] pattern_sig_ctx_i ;
input [ 1:0 ] scan_idx_i ;
input [ 4:0 ] pos_x_i ;
input [ 4:0 ] pos_y_i ;
input [ 1:0 ] tu_depth_i ;
input [ 1:0 ] coeff_type_i ;
output [ 7:0 ] ctx_pair_scf_addr_o ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// calculation sig_ctx_inc : calculation ctxIndMap
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [ 3:0 ] ctxIndMap_r ;
wire [ 3:0 ] ctxIndMap_index_w ;
assign ctxIndMap_index_w = (pos_y_i[1:0]<<2) + pos_x_i[1:0] ;
always @* begin
case(ctxIndMap_index_w)
6'd0 : ctxIndMap_r = 4'd0 ;
6'd1 : ctxIndMap_r = 4'd1 ;
6'd2 : ctxIndMap_r = 4'd4 ;
6'd3 : ctxIndMap_r = 4'd5 ;
6'd4 : ctxIndMap_r = 4'd2 ;
6'd5 : ctxIndMap_r = 4'd3 ;
6'd6 : ctxIndMap_r = 4'd4 ;
6'd7 : ctxIndMap_r = 4'd5 ;
6'd8 : ctxIndMap_r = 4'd6 ;
6'd9 : ctxIndMap_r = 4'd6 ;
6'd10 : ctxIndMap_r = 4'd8 ;
6'd11 : ctxIndMap_r = 4'd8 ;
6'd12 : ctxIndMap_r = 4'd7 ;
6'd13 : ctxIndMap_r = 4'd7 ;
6'd14 : ctxIndMap_r = 4'd8 ;
6'd15 : ctxIndMap_r = 4'd8 ;
endcase
end
//-----------------------------------------------------------------------------------------------------------------------------
//
// calculation sig_ctx_inc : calculation base , cnt and offset
//
//-----------------------------------------------------------------------------------------------------------------------------
wire [ 1:0 ] base_w ;
wire [ 4:0 ] offset_w ;
reg [ 1:0 ] cnt_r ;
wire [ 1:0 ] pos_x_inSubset_w ;
wire [ 1:0 ] pos_y_inSubset_w ;
wire [ 2:0 ] pos_xy_sum_w ;
assign base_w = coeff_type_i[1] &&(pos_x_i[4:2]||pos_y_i[4:2])? 2'd3:2'd0 ;
assign offset_w = (tu_depth_i == 2'd2) ? ( scan_idx_i==`SCAN_DIAG ? 5'd9 : 5'd15) :(coeff_type_i[1] ? 5'd21 : 5'd12);
// cnt_r
always @* begin
if(pattern_sig_ctx_i==2'd0)
cnt_r = pos_xy_sum_w < 3'd3 ? (pos_xy_sum_w==3'd0 ? 2'd2 : 2'd1):2'd0 ;
else if(pattern_sig_ctx_i==2'd1)
cnt_r = pos_y_inSubset_w[1] ? 2'd0 : (pos_y_inSubset_w ? 2'd1 : 2'd2) ;
else if(pattern_sig_ctx_i==2'd2)
cnt_r = pos_x_inSubset_w[1] ? 2'd0 : (pos_x_inSubset_w ? 2'd1 : 2'd2) ;
else
cnt_r = 2'd2 ;
end
assign pos_x_inSubset_w = pos_x_i[1:0] ;
assign pos_y_inSubset_w = pos_y_i[1:0] ;
assign pos_xy_sum_w = pos_x_i[1:0] + pos_y_i[1:0] ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// calculation sig_ctx_inc
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [ 5:0 ] sig_ctx_r ;
always @* begin
if( (pos_x_i==5'd0) && (pos_y_i == 5'd0) )
sig_ctx_r = coeff_type_i[1] ? 6'd0 : 6'd27 ;
else if(tu_depth_i==2'd3) //4x4
sig_ctx_r = coeff_type_i[1] ? ctxIndMap_r : ctxIndMap_r + 6'd27 ;
else
sig_ctx_r = coeff_type_i[1] ? base_w + cnt_r + offset_w : base_w + cnt_r + offset_w + 6'd27 ;
end
//-----------------------------------------------------------------------------------------------------------------------------
//
// calculation ctx_pair_scf_addr_o : look up table
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [ 7:0 ] ctx_pair_scf_addr_r ;
always @* begin
case(sig_ctx_r)
6'd0 : ctx_pair_scf_addr_r = {3'd3 , 5'd31 } ;
6'd1 : ctx_pair_scf_addr_r = {3'd2 , 5'd17 } ;
6'd2 : ctx_pair_scf_addr_r = {3'd2 , 5'd16 } ;
6'd3 : ctx_pair_scf_addr_r = {3'd4 , 5'd8 } ;
6'd4 : ctx_pair_scf_addr_r = {3'd1 , 5'd17 } ;
6'd5 : ctx_pair_scf_addr_r = {3'd4 , 5'd7 } ;
6'd6 : ctx_pair_scf_addr_r = {3'd4 , 5'd9 } ;
6'd7 : ctx_pair_scf_addr_r = {3'd1 , 5'd18 } ;
6'd8 : ctx_pair_scf_addr_r = {3'd2 , 5'd18 } ;
6'd9 : ctx_pair_scf_addr_r = {3'd0 , 5'd16 } ;
6'd10 : ctx_pair_scf_addr_r = {3'd4 , 5'd1 } ;
6'd11 : ctx_pair_scf_addr_r = {3'd2 , 5'd10 } ;
6'd12 : ctx_pair_scf_addr_r = {3'd0 , 5'd17 } ;
6'd13 : ctx_pair_scf_addr_r = {3'd4 , 5'd2 } ;
6'd14 : ctx_pair_scf_addr_r = {3'd2 , 5'd11 } ;
6'd15 : ctx_pair_scf_addr_r = {3'd0 , 5'd18 } ;
6'd16 : ctx_pair_scf_addr_r = {3'd4 , 5'd3 } ;
6'd17 : ctx_pair_scf_addr_r = {3'd2 , 5'd12 } ;
6'd18 : ctx_pair_scf_addr_r = {3'd0 , 5'd19 } ;
6'd19 : ctx_pair_scf_addr_r = {3'd4 , 5'd4 } ;
6'd20 : ctx_pair_scf_addr_r = {3'd2 , 5'd13 } ;
6'd21 : ctx_pair_scf_addr_r = {3'd0 , 5'd20 } ;
6'd22 : ctx_pair_scf_addr_r = {3'd4 , 5'd5 } ;
6'd23 : ctx_pair_scf_addr_r = {3'd2 , 5'd14 } ;
6'd24 : ctx_pair_scf_addr_r = {3'd0 , 5'd21 } ;
6'd25 : ctx_pair_scf_addr_r = {3'd4 , 5'd6 } ;
6'd26 : ctx_pair_scf_addr_r = {3'd2 , 5'd15 } ;
6'd27 : ctx_pair_scf_addr_r = {3'd3 , 5'd16 } ;
6'd28 : ctx_pair_scf_addr_r = {3'd2 , 5'd8 } ;
6'd29 : ctx_pair_scf_addr_r = {3'd0 , 5'd14 } ;
6'd30 : ctx_pair_scf_addr_r = {3'd3 , 5'd30 } ;
6'd31 : ctx_pair_scf_addr_r = {3'd1 , 5'd16 } ;
6'd32 : ctx_pair_scf_addr_r = {3'd4 , 5'd0 } ;
6'd33 : ctx_pair_scf_addr_r = {3'd5 , 5'd0 } ;
6'd34 : ctx_pair_scf_addr_r = {3'd5 , 5'd1 } ;
6'd35 : ctx_pair_scf_addr_r = {3'd2 , 5'd9 } ;
6'd36 : ctx_pair_scf_addr_r = {3'd4 , 5'd10 } ;
6'd37 : ctx_pair_scf_addr_r = {3'd1 , 5'd19 } ;
6'd38 : ctx_pair_scf_addr_r = {3'd2 , 5'd19 } ;
6'd39 : ctx_pair_scf_addr_r = {3'd4 , 5'd11 } ;
6'd40 : ctx_pair_scf_addr_r = {3'd1 , 5'd20 } ;
6'd41 : ctx_pair_scf_addr_r = {3'd2 , 5'd20 } ;
default : ctx_pair_scf_addr_r = {3'd5 , 5'h1f } ;
endcase
end
assign ctx_pair_scf_addr_o = ctx_pair_scf_addr_r ;
endmodule
|
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description: Full client for the Focus Robotics Control Interconnect
* that supports reads and writes made to us from another block as well as reads
* and writes originating from this block made to another block.
*
* Functionality:
*
* Issues:
* - The interface currently seems a little clumsy. I am hoping to clean it up
* to be a little more compact and general as I work with it.
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_client
(
clk,
rst,
fric_in,
fric_out,
slave_addr, // addr out for read or write requests sent to this block
slave_wdat,
slave_wstb,
slave_rdat, // replay data in to reply to a read request made to us
master_type,
master_port,
master_addr, // type, port, and addr in for reads or writes from this block
master_wdat, // write data sent from this block
master_tstb, // transaction strobe -- initiate based on above
master_trdy, // flow control, tstb may only be asserted when this is already high
master_rstb, // reply strobe out to alert block that reply has arrived
master_rdat // reply data out
);
// Input/Output Declarations
input clk;
input rst;
input [7:0] fric_in;
output [7:0] fric_out;
output [7:0] slave_addr;
output [15:0] slave_wdat;
output slave_wstb;
input [15:0] slave_rdat;
input [3:0] master_type;
input [3:0] master_port;
input [7:0] master_addr;
input [15:0] master_wdat;
input master_tstb;
output master_trdy;
output master_rstb;
output [15:0] master_rday;
// Parameter Declarations
// Wire and Reg Declarations
// RTL
/****************************************************************************
* Fric In Sequencer (fis)
*
* The FSM in this subblock must accept any type of incoming packet, both new
* requests from other blocks and acks for requests we have previously made.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Fric Out Sequencer (fos)
*
* The Fric output sequencer must be able to send both new requests and acks
* for requests previously made to us.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Fric Reply Generator (frg)
*
* This subblock monitors requests made of us and forms the appropriate reply
* packets. This subblock controls the slave interface.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Fric Request Muxer (frm)
*
* This subblock controls the master interface and allows both the master
* interface and the FRG to send outgoing data to the fos.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Subblock
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_client
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long n, a[100010]; int main() { long long n, mx = 0, sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > mx) mx = a[i]; sum += a[i]; } long long s = (sum + n - 2) / (n - 1); if (mx > s) s = mx; cout << s << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; vector<int> x(n); vector<int> p(n); for (int i = (0); i < ((n)); ++i) { cin >> x[i]; --x[i]; p[x[i]] = i; } int const MAX_SUM = 100001; vector<int> primes; for (int k = (2); k < (2 * n + 1); ++k) { bool isPrime = true; for (int j = 2; j * j <= k; ++j) { if (k % j == 0) { isPrime = false; break; } } if (isPrime) { primes.push_back(k); } } vector<pair<int, int> > res; for (int i = (0); i < ((n)); ++i) { int const pos1 = p[i]; int const pos2 = i; int p1 = min(pos1, pos2); int const p2 = max(pos1, pos2); vector<int> positions; positions.push_back(p1); while (p1 != p2) { int const diff = p2 - p1 + 1; auto it = lower_bound(primes.begin(), primes.end(), diff); if (it == primes.end() || *it > diff) --it; int const usedPrime = *it; p1 += usedPrime - 1; positions.push_back(p1); } if (pos1 > pos2) reverse(positions.begin(), positions.end()); for (int j = (0); j < (((int)positions.size() - 1)); ++j) { int const p1 = positions[j]; int const p2 = positions[j + 1]; swap(x[p1], x[p2]); p[x[p1]] = p1; p[x[p2]] = p2; res.push_back(make_pair(min(p1, p2), max(p1, p2))); } } vector<int> orig(n); for (int i = (0); i < ((n)); ++i) orig[i] = i; if (orig != x) { cout << FAILED! n ; throw 10; } cout << (int)res.size() << endl; for (int i = (0); i < (((int)res.size())); ++i) { cout << res[i].first + 1 << << res[i].second + 1 << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_TB_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool ylmin(T &a, T b) { return a < b ? 0 : (a = b, 1); } template <class T> inline bool ylmax(T &a, T b) { return a > b ? 0 : (a = b, 1); } template <class T> inline T abs(T x) { return x < 0 ? -x : x; } inline char read() { static const int IO_LEN = 1024 * 1024; static char buf[IO_LEN], *ioh, *iot; if (ioh == iot) { iot = (ioh = buf) + fread(buf, 1, IO_LEN, stdin); if (ioh == iot) return -1; } return *ioh++; } template <class T> inline void read(T &x) { static int iosig; static char ioc; for (iosig = 0, ioc = read(); !isdigit(ioc); ioc = read()) if (ioc == - ) iosig = 1; for (x = 0; isdigit(ioc); ioc = read()) x = (x << 1) + (x << 3) + (ioc ^ 0 ); if (iosig) x = -x; } const int MAXN = 2e5 + 10; long long T, n, a[MAXN], b[MAXN], id[MAXN]; inline bool cmp(int x, int y) { return a[x] < a[y]; } int main() { for (read(T); T; T--) { read(n); for (int i = (1); i <= (n); i++) read(a[i]), id[i] = i; for (int i = (1); i <= (n); i++) read(b[i]); sort(id + 1, id + n + 1, cmp); long long sum = 0, ans = 1e9; for (int i = (1); i <= (n); i++) sum += b[i]; for (int i = (0); i <= (n); i++) { sum -= b[id[i]]; ylmin(ans, max(a[id[i]], sum)); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int MAX = 5000001; unsigned int arr[MAX], P[MAX]; void sieve() { unsigned int i, j, t, k; arr[0] = arr[1] = 0; for (i = 2; i < MAX; i++) arr[i] = i; for (i = 4; i < MAX; i += 2) arr[i] = 2; for (i = 3; i * i <= MAX; i += 2) if (arr[i] == i) for (j = i * i; j < MAX; j += 2 * i) if (arr[j] == j) arr[j] = i; for (i = 2; i < 5000001; i++) P[i] = P[i / arr[i]] + 1; for (i = 2; i < 5000001; i++) P[i] += P[i - 1]; } int main(void) { sieve(); unsigned int tc, i, a, b; scanf( %u , &tc); for (i = 1; i <= tc; i++) { scanf( %u %u , &a, &b); printf( %u n , P[a] - P[b]); } return 0; }
|
module x;
reg [31:0] mb_reg_output;
// 16 registers max, register 15 is always the version number, so 15 are useable
// NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
parameter NUMBER_INTERFACE_REGS = 16;
parameter MB_REG_START = 3; // start at 4th register location 'h0010
parameter CMD_REG_0_ADDR = MB_REG_START;
parameter CMD_REG_1_ADDR = MB_REG_START+1;
parameter CMD_REG_2_ADDR = MB_REG_START+2;
parameter CMD_REG_3_ADDR = MB_REG_START+3;
parameter CMD_REG_4_ADDR = MB_REG_START+4;
parameter CMD_REG_5_ADDR = MB_REG_START+5;
parameter CMD_REG_6_ADDR = MB_REG_START+6;
parameter CMD_REG_7_ADDR = MB_REG_START+7;
parameter CMD_REG_8_ADDR = MB_REG_START+8;
parameter CMD_REG_9_ADDR = MB_REG_START+9;
parameter CMD_REG_10_ADDR = MB_REG_START+10;
// mode regs
parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
// Absolute register 14 is Error counter
parameter CMD_REG_14_ADDR = 14;
parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
// ------------ VERSION register is 15
parameter VERSION_REG_ADDR = 15;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
wire [31:0] interface_from_core_fp;
assign
mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
integer mb_loop;
always @(/*AUTOSENSE*/ /*memory or*/ interface_from_core_fp or mb_reg_rwn or mb_reg_select)
begin: MB_READ_WRITE_SEL_P
mb_reg_wr = 'h0;
mb_reg_rd = 'h0;
mb_reg_output = interface_from_core_fp;
for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
begin
if(mb_reg_select[mb_loop] == 1'b1)
begin
mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
mb_reg_output = mb_reg_out_w[mb_loop];
end
end
end
endmodule // x
|
#include <bits/stdc++.h> using namespace std; vector<vector<pair<int, char> > > adj(201); int dp[101][101][26][2]; bool solve(int i, int j, char round, bool turn) { if (dp[i][j][(int)(round - a )][turn] != -1) return dp[i][j][(int)(round - a )][turn]; int ret = 0; if (!turn) { for (int k = 0; k < adj[i].size(); k++) { if (adj[i][k].second >= round) if (!solve(adj[i][k].first, j, adj[i][k].second, !turn)) ret = 1; } } else { for (int k = 0; k < adj[j].size(); k++) { if (adj[j][k].second >= round) if (!solve(i, adj[j][k].first, adj[j][k].second, !turn)) ret = 1; } } return dp[i][j][(int)(round - a )][turn] = ret; } int main() { memset(dp, -1, sizeof dp); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; char z; cin >> x >> y >> z; adj[x].push_back({y, z}); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { int h = solve(i, j, a , 0); if (h == 1) cout << A ; else cout << B ; } cout << endl; } return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.12 2009-01-19 20:29:26 rherveille Exp $
//
// $Date: 2009-01-19 20:29:26 $
// $Revision: 1.12 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_we_i & wb_ack_o;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsys parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsys parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
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#include <bits/stdc++.h> using namespace std; using ll = long long; const ll MOD = 1e9 + 7; void dfs(int node, vector<vector<pair<int, int>>>& adj, vector<bool>& vu, ll& cnt) { for (auto& p : adj[node]) { if (!vu[p.first] and p.second == 0) { vu[p.first] = true; ++cnt; dfs(p.first, adj, vu, cnt); } } } ll getPow(ll a, ll p) { ll ret = 1, cp = a; while (p) { if (p & 1) ret = (ret * cp) % MOD; p >>= 1; cp = (cp * cp) % MOD; } return ret; } int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k, a, b, c; cin >> n >> k; vector<vector<pair<int, int>>> adj(n + 1); for (int i = 1; i < n; ++i) { cin >> a >> b >> c; adj[a].emplace_back(b, c); adj[b].emplace_back(a, c); } vector<bool> vu(n + 1); ll ans = getPow(n, k); for (int i = 1; i <= n; ++i) { if (!vu[i]) { ll tmp = 1; vu[i] = true; dfs(i, adj, vu, tmp); ans = (ans - getPow(tmp, k)) % MOD; } } cout << (ans + MOD) % MOD; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename float_t> struct _complex_ { float_t x, y; _complex_<float_t>(float_t _x = 0, float_t _y = 0) : x(_x), y(_y) {} float_t real() const { return x; } void real(float_t _x) { x = _x; } float_t imag() const { return y; } void imag(float_t _y) { y = _y; } _complex_<float_t> &operator+=(const _complex_<float_t> &other) { x += other.x; y += other.y; return *this; } _complex_<float_t> &operator-=(const _complex_<float_t> &other) { x -= other.x; y -= other.y; return *this; } _complex_<float_t> operator+(const _complex_<float_t> &other) const { return _complex_<float_t>(*this) += other; } _complex_<float_t> operator-(const _complex_<float_t> &other) const { return _complex_<float_t>(*this) -= other; } _complex_<float_t> operator*(const _complex_<float_t> &other) const { return {x * other.x - y * other.y, x * other.y + other.x * y}; } _complex_<float_t> operator*(float_t mult) const { return {x * mult, y * mult}; } }; template <typename float_t> _complex_<float_t> conj(const _complex_<float_t> &c) { return {c.x, -c.y}; } template <typename float_t> _complex_<float_t> polar(float_t magnitude, float_t angle) { return {magnitude * cos(angle), magnitude * sin(angle)}; } template <typename float_t> ostream &operator<<(ostream &stream, const _complex_<float_t> &c) { return stream << ( << c.x << , << c.y << ) ; } const int mod = 1e9 + 7; const long long inf = 9223372036854775807; struct query { int y, pos, type; query(int a, int b, int c) { y = a, pos = b, type = c; } }; bool query_sort(const query &a, const query &b) { if ((a.y ^ b.y)) { return (a.y < b.y); } return (a.pos ^ b.pos) ? (a.pos < b.pos) : (a.type < b.type); } int n, k; int x_coor[300 * 100001], y_coor[300 * 100001], sorted_x[100001]; long long ans[100001]; map<int, int> pos; signed main() { cin >> n >> k; for (int i = 0; i < n; ++i) { cin >> x_coor[i] >> y_coor[i]; sorted_x[i] = x_coor[i]; } sort(sorted_x, sorted_x + n); int oniichan = 0; sorted_x[n] = mod; for (int i = 0; i < n; ++i) { if (sorted_x[i] ^ sorted_x[i + 1]) { pos[sorted_x[i]] = oniichan + 1; oniichan += min(sorted_x[i] + k, sorted_x[i + 1]) - sorted_x[i]; } } vector<query> q; for (int i = 0; i < n; ++i) { q.push_back(query(y_coor[i], pos[x_coor[i]], 1)); q.push_back(query(y_coor[i] + k, pos[x_coor[i]], -1)); } sort((q).begin(), (q).end(), query_sort); memset(x_coor, 0, sizeof(x_coor)); memset(y_coor, 0, sizeof(y_coor)); for (query &i : q) { for (int j = i.pos; j < i.pos + k; ++j) { ans[y_coor[j]] += i.y - x_coor[j]; y_coor[j] += i.type; x_coor[j] = i.y; } } for (int i = 1; i < n + 1; ++i) cout << ans[i] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; using cd = complex<double>; const double PI = acos(-1); int reverse(int num, int lg_n) { int res = 0; for (int i = 0; i < lg_n; i++) { if (num & (1 << i)) res |= 1 << (lg_n - 1 - i); } return res; } void fft(vector<cd> &a, bool invert) { int n = a.size(); int lg_n = 0; while ((1 << lg_n) < n) lg_n++; for (int i = 0; i < n; i++) { if (i < reverse(i, lg_n)) swap(a[i], a[reverse(i, lg_n)]); } for (int len = 2; len <= n; len <<= 1) { double ang = 2 * PI / len * (invert ? -1 : 1); cd wlen(cos(ang), sin(ang)); for (int i = 0; i < n; i += len) { cd w(1); for (int j = 0; j < len / 2; j++) { cd u = a[i + j], v = a[i + j + len / 2] * w; a[i + j] = u + v; a[i + j + len / 2] = u - v; w *= wlen; } } } if (invert) { for (cd &x : a) x /= n; } } vector<int> mult(vector<cd> &a, vector<cd> &b) { vector<cd> fa(a.begin(), a.end()), fb(b.begin(), b.end()); int n = 1; while (n < a.size() + b.size()) n <<= 1; fa.resize(n); fb.resize(n); fft(fa, false); fft(fb, false); for (int i = 0; i < n; i++) fa[i] *= fb[i]; fft(fa, true); vector<int> result(n); for (int i = 0; i < n; i++) { result[i] = round(fa[i].real()); } return result; } long long mdp[1000010]; void crive() { for (long long i = 2; i <= 1000000; i++) { if (mdp[i] == 0) { mdp[i] = i; for (long long j = i * i; j <= 1000000; j += i) { if (mdp[j] == 0) mdp[j] = i; } } } } vector<long long> div(int l) { vector<long long> ans = {1}; int sz = 1; while (l > 1) { long long p = mdp[l]; long long it = p; while (l % it == 0) { for (int j = 0; j < sz; j++) ans.push_back(it * ans[j]); it *= p; } it /= p; sz = ans.size(); l /= it; } sort(ans.begin(), ans.end()); return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); crive(); long long n, x, y; cin >> n >> x >> y; vector<cd> a(x + 1), b(x + 1); for (int i = 0; i < n + 1; i++) { int num; cin >> num; a[x - num] = 1; b[num] = 1; } vector<int> c = mult(a, b); int q; cin >> q; for (int i = 0; i < q; i++) { int l; cin >> l; vector<long long> d = div(l); long long resp = -1; for (int i = d.size() - 1; i >= 0 && d[i] > 2 * y; i--) { long long u = d[i]; if (u & 1) continue; if ((u - 2 * y) / 2 + x < c.size() && c[(u - 2 * y) / 2 + x]) resp = u, i = -1; } cout << resp << ; } cout << endl; }
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#include <bits/stdc++.h> using namespace std; vector<int> s; vector<vector<int> > t; bool sortFunc(vector<int> a, vector<int> b) { if (a.size() == 0) return false; if (b.size() == 0) return true; return a.size() < b.size(); } int main() { cin.sync_with_stdio(false); cin.tie(0); int n; cin >> n; s.resize(n + 1); for (int i = 1; i <= n; i++) cin >> s[i]; vector<bool> was(n + 1, false); int index = 0; t.push_back(vector<int>()); for (int i = 1; i <= n; i++) { if (was[i]) continue; int ind = i; while (!was[ind]) { was[ind] = true; t[index].push_back(ind); ind = s[ind]; } t.push_back(vector<int>()); index++; } vector<int> sol(n + 1); sort(t.begin(), t.end(), sortFunc); bool poss = true; for (int i = 0; i < index; i++) { vector<int> real; if (t[i].size() % 2 == 1) { real.resize(t[i].size()); for (int j = 0; j < t[i].size() / 2; j++) { real[j * 2] = t[i][j]; int b = t[i].size() / 2 + 1 + j; real[j * 2 + 1] = t[i][b]; } int b = t[i].size() / 2; real[t[i].size() - 1] = t[i][b]; } else if (t[i + 1].size() == t[i].size()) { real.resize(2 * t[i].size()); for (int j = 0; j < t[i].size(); j++) { real[2 * j] = t[i][j]; real[2 * j + 1] = t[i + 1][j]; } i++; } else poss = false; for (int j = 0; j < real.size(); j++) { sol[real[j]] = real[(j + 1) % real.size()]; } } if (poss) { for (int i = 1; i <= n; i++) { cout << sol[i] << ; } cout << n ; } else { cout << -1 n ; } }
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#include <bits/stdc++.h> int a[5005]; int solve(int i, int j) { int k, vans, hans, mini, s, t; vans = j - i + 1; mini = a[i]; for (k = i + 1; k <= j; k++) if (mini > a[k]) mini = a[k]; hans = mini; for (k = i; k <= j; k++) a[k] -= mini; hans = mini; for (k = i; k <= j;) { if (a[k] == 0) { k++; } else { s = k; t = s; while (t <= j && a[t] != 0) t++; hans += solve(s, t - 1); k = t; } } if (vans < hans) return vans; else return hans; } int main() { int n, i; int vans, hans; int ans; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); ans = solve(1, n); printf( %d n , ans); }
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#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops,no-stack-protector ) #pragma GCC target( sse,sse2,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const int MOD = 1e9 + 7; const int INF32 = 1 << 30; const long long INF64 = 1LL << 60; const long double pi = acos(-1); long long gcd(long long a, long long b) { return (!b ? a : gcd(b, a % b)); } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } long long mul(long long a, long long b) { return a * b % MOD; } long long modpow(long long b, long long i) { long long s = 1; while (i) { if (i % 2) s = (s * b) % MOD; b = (b * b) % MOD; i /= 2; } return s; } long long inv(long long a) { return modpow(a, MOD - 2); } void solve() { int xa, ya, xb, yb; cin >> xa >> ya >> xb >> yb; cout << (xa + ya <= max(xb, yb) || (xa <= xb && ya <= yb) ? Polycarp : Vasiliy ); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int t, num[30], ans; char s[100005]; int main() { cin >> t; while (t--) { ans = 0; memset(num, 0, sizeof(num)); scanf( %s , s + 1); int len = strlen(s + 1); for (int i = 1; i <= len; i++) { num[s[i] - A + 1]++; } if (num[ L - A + 1] != 0 && num[ R - A + 1] != 0 && (num[ U - A + 1] == 0 || num[ D - A + 1] == 0)) { printf( 2 n ); printf( LR n ); } else if (num[ U - A + 1] != 0 && num[ D - A + 1] != 0 && (num[ L - A + 1] == 0 || num[ R - A + 1] == 0)) { printf( 2 n ); printf( UD n ); } else if (num[ L - A + 1] != 0 && num[ R - A + 1] != 0 && num[ U - A + 1] != 0 && num[ D - A + 1] != 0) { ans += min(num[ L - A + 1], num[ R - A + 1]) * 2; ans += min(num[ U - A + 1], num[ D - A + 1]) * 2; printf( %d n , ans); for (int i = 1; i <= min(num[ L - A + 1], num[ R - A + 1]); i++) { printf( L ); } for (int i = 1; i <= min(num[ U - A + 1], num[ D - A + 1]); i++) { printf( U ); } for (int i = 1; i <= min(num[ L - A + 1], num[ R - A + 1]); i++) { printf( R ); } for (int i = 1; i <= min(num[ U - A + 1], num[ D - A + 1]); i++) { printf( D ); } printf( n ); } else { printf( 0 n n ); } } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_BLACKBOX_V
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`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
always @ ( iAddress )
begin
case (iAddress)
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO , `R7,16'b0001 };
2: oInstruction = { `STO ,`R3,16'h1 };
3: oInstruction = { `STO, `R4,16'd1000 };
4: oInstruction = { `STO, `R5,16'd0 }; //j
//LOOP2:
5: oInstruction = { `LED ,8'b0,`R7,8'b0 };
6: oInstruction = { `STO ,`R1,16'h0 };
7: oInstruction = { `STO ,`R2,16'd5000 };
//LOOP1:
8: oInstruction = { `ADD ,`R1,`R1,`R3 };
9: oInstruction = { `BLE ,`LOOP1,`R1,`R2 };
10: oInstruction = { `ADD ,`R5,`R5,`R3 };
11: oInstruction = { `BLE ,`LOOP2,`R5,`R4 };
12: oInstruction = { `NOP ,24'd4000 };
13: oInstruction = { `SUB ,`R7,`R7,`R3 };
14: oInstruction = { `JMP , 8'd2,16'b0 };
/* 0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO ,`R1, 16'h0002};
2: oInstruction = { `STO ,`R2, 16'h0005};
3: oInstruction = { `STO ,`R3, 16'h0000};
4: oInstruction = { `ADD ,`R3,`R1,`R2 };
5: oInstruction = { `ADD ,`R4,`R1,`R3 };
6: oInstruction = { `NOP ,24'd4000 };
7: oInstruction = { `NOP ,24'd4000 };
8: oInstruction = { `JMP , 8'd7,16'b0 };*/
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; struct Data { int u, v, w; Data() {} Data(int x, int y, int z) : u(x), v(y), w(z) {} }; int n; vector<Data> edge, ans; vector<int> neighbor[N]; void dfs(int u, int par, vector<int> &leaf) { if (neighbor[u].size() == 1) { leaf.push_back(u); return; } for (auto v : neighbor[u]) if (v != par) dfs(v, u, leaf); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i < n; i++) { int x, y, w; cin >> x >> y >> w; edge.push_back(Data(x, y, w)); neighbor[x].push_back(y); neighbor[y].push_back(x); } for (int i = 1; i <= n; i++) if (neighbor[i].size() == 2) return cout << NO , 0; cout << YES n ; for (auto Q : edge) { int u = Q.u, v = Q.v, w = Q.w; vector<int> Uleaf, Vleaf; dfs(u, v, Uleaf); dfs(v, u, Vleaf); int u1 = Uleaf.front(), u2 = Uleaf.back(); int v1 = Vleaf.front(), v2 = Vleaf.back(); ans.push_back(Data(u1, v1, w / 2)); ans.push_back(Data(u2, v2, w / 2)); if (u1 != u2) ans.push_back(Data(u1, u2, -w / 2)); if (v1 != v2) ans.push_back(Data(v1, v2, -w / 2)); } cout << ans.size() << n ; for (auto Q : ans) { int u = Q.u, v = Q.v, w = Q.w; cout << u << << v << << w << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__FAHCON_PP_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFSTP_PP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int64_t MOD = 998244353; const int64_t N = 2e5 + 5; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int64_t mpow(int64_t x, int64_t y) { if (y == 0) return 1; int64_t temp = mpow(x, y / 2); temp *= temp; temp %= MOD; if (y & 1) return (x * temp) % MOD; return temp; } int64_t inverse(int64_t x) { return mpow(x, MOD - 2); } int64_t fact[N], ifact[N]; int64_t nCr(int64_t n, int64_t r) { int64_t ans = fact[n]; ans *= ifact[r]; ans %= MOD; ans *= ifact[n - r]; ans %= MOD; return ans; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); fact[0] = 1; ifact[0] = 1; for (int64_t i = 1; i < N; i++) { fact[i] = fact[i - 1] * i; fact[i] %= MOD; ifact[i] = inverse(fact[i]); } int64_t n, k; cin >> n >> k; int64_t arr[n]; for (int64_t i = 0; i < n; i++) { cin >> arr[i]; } int64_t equal = 0; for (int64_t i = 0; i < n; i++) { if (arr[i] == arr[(i + 1) % n]) equal++; } int64_t ans = mpow(k, equal); int64_t ans2 = 0; for (int64_t i = 0; i <= n - equal - 1; i++) { int64_t lol = mpow(k - 2, i); if ((n - equal - i) % 2 == 1) { lol *= mpow(2, n - equal - i - 1); lol %= MOD; } else { int64_t rem = mpow(2, n - equal - i); rem -= nCr(n - equal - i, (n - equal - i + 1) / 2); rem = rem + 10 * MOD; rem %= MOD; rem *= inverse(2); rem %= MOD; lol *= rem; lol %= MOD; } lol *= nCr(n - equal, i); lol %= MOD; ans2 += lol; ans2 %= MOD; } ans *= ans2; ans %= MOD; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; const int inf = INT_MAX; const long long inff = 1e18; const int mod = 1e9 + 7; long long a[50]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); a[0] = 0; for (long long i = 1; i <= 31; i++) { a[i] = 4 * a[i - 1] + 1; } long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; if (n <= 30 && k > a[n]) cout << NO << endl; else if (k < 5) { if (k == 3 && n == 2) cout << NO << endl; else if (n == 2) { if (k == 1 || k == 2) cout << YES 1 << endl; else cout << YES 0 << endl; } else { cout << YES << n - 1 << endl; } } else { cout << YES ; long long now; for (long long i = 1; i <= 31; i++) { if (a[i] >= k) { now = i; break; } } now--; if (a[now + 1] - k <= (((1ll << now) - 1) * ((1ll << now) - 1))) cout << n - now - 1 << endl; else cout << n - now << endl; } } }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Graphics mode CRT Cycle
// File : sm_graphic_crt.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This state machine is active when crt_cycle is active in graphics mode
// and crtfifo is writable. This state machine generates an svga_req to the
// memory module and waits for the acknowledge. transfers the data after
// the acknowledge is confirmed.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module sm_graphic_crt
(
input sync_c_crt_line_end,
input hreset_n,
input ff_writeable_crt,
input crt_gnt,
input svga_ack,
input mem_clk,
input graphic_mode,
input data_complete,
input [7:0] c_hde,
input color_256_mode,
output gra_crt_svga_req,
output enrd_gra_addr,
output gra_cnt_inc,
output [30:0] probe
);
//
// Define variables
//
reg [2:0] current_state;
reg [2:0] next_state;
reg [3:0] gra_cnt_qout;
reg gra_s1;
reg gra_s1x, gra_s2;
reg gra_s2x, gra_s3;
reg [4:0] char_count;
wire gra_cnt_0;
wire cnt_inc;
wire char_done;
assign probe = {data_complete, char_done, cnt_inc, ff_writeable_crt,
crt_gnt, svga_ack, graphic_mode, color_256_mode,
gra_crt_svga_req, enrd_gra_addr, gra_cnt_inc,
char_count, c_hde, current_state, gra_cnt_qout};
//
// Define state machine variables
//
parameter gra_crt_state0 = 3'b000,
gra_crt_state1x = 3'b001,
gra_crt_state2 = 3'b011,
gra_crt_state1 = 3'b111,
gra_crt_state2x = 3'b110,
gra_crt_state3 = 3'b010;
// In standard graphics modes we always increment by 1 character per piece
// of data read
always @ (posedge mem_clk or negedge hreset_n)
if (!hreset_n) char_count <= 5'b0;
else if (sync_c_crt_line_end) char_count <= 5'b0;
else if (data_complete) char_count <= char_count + 1;
// Need to add in extra characters for panning (can pan up to 3)
assign char_done = {char_count, 4'b0} >= (c_hde + 4);
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) current_state <= gra_crt_state0;
else if (sync_c_crt_line_end) current_state <= gra_crt_state0;
else current_state <= next_state;
end
always @* begin
gra_s1 = 1'b0;
gra_s1x = 1'b0;
gra_s2 = 1'b0;
gra_s2x = 1'b0;
gra_s3 = 1'b0;
case (current_state) // synopsys parallel_case
gra_crt_state0: begin
if (crt_gnt && ff_writeable_crt & graphic_mode && ~char_done)
next_state = gra_crt_state1x;
else
next_state = gra_crt_state0;
end
gra_crt_state1x: begin
gra_s1x = 1'b1;
if (svga_ack)
next_state = gra_crt_state2;
else
next_state = gra_crt_state1x;
end
gra_crt_state2: begin
gra_s2 = 1'b1;
if (~gra_cnt_0 )
next_state = gra_crt_state1;
else if (gra_cnt_0 )
next_state = gra_crt_state2x;
else
next_state = gra_crt_state2;
end
gra_crt_state1: begin
gra_s1 = 1'b1;
if (svga_ack)
next_state = gra_crt_state2;
else
next_state = gra_crt_state1;
end
gra_crt_state2x: begin
gra_s2x = 1'b1;
next_state = gra_crt_state3;
end
gra_crt_state3: begin
gra_s3 = 1'b1;
if (data_complete)
next_state = gra_crt_state0;
else
next_state = gra_crt_state3;
end
endcase
end
assign enrd_gra_addr = (gra_s2 );
assign gra_crt_svga_req = gra_s1x | ((gra_s1 | gra_s2) & ~gra_cnt_0);
assign gra_cnt_inc = (svga_ack & (gra_s2 | gra_s1)) | gra_s2x;
assign cnt_inc = svga_ack & (gra_s1x | gra_s2 | gra_s1);
assign gra_cnt_0 = (~gra_cnt_qout[3] & ~gra_cnt_qout[2] & ~gra_cnt_qout[1] & ~gra_cnt_qout[0] ) ;
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) gra_cnt_qout <= 4'b0;
else if (sync_c_crt_line_end) gra_cnt_qout <= 4'b0;
else if (cnt_inc) gra_cnt_qout <= gra_cnt_qout + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int chr[1000006]; long long int freq[1000006]; long long int Z[2000006]; void Zalgo(int end) { int l = 1, r = 1; for (int i = 2; i < end; ++i) { if (r > i) { int pre = Z[i - l + 1]; if (pre + i < r) { Z[i] = pre; } else { l = i; while (r < end && chr[r] == chr[r - i + 1] && freq[r] == freq[r - i + 1]) { ++r; } Z[i] = r - l; } } else { l = r = i; while (r < end && chr[r] == chr[r - i + 1] && freq[r] == freq[r - i + 1]) { ++r; } Z[i] = r - l; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; string s, t; cin >> n >> m; chr[0] = -1; freq[0] = 0; int index = 1; for (int i = 1; i <= n; ++i) { string s; cin >> s; if (s[s.size() - 1] - a == chr[index - 1]) { freq[index - 1] += stoi(s, nullptr, 10); } else { chr[index] = s[s.size() - 1] - a ; freq[index] += stoi(s, nullptr, 10); ++index; } } int mid = index; chr[index] = -1; freq[index++] = 0; for (int i = 1; i <= m; ++i) { string s; cin >> s; if (s[s.size() - 1] - a == chr[index - 1]) { freq[index - 1] += stoi(s, nullptr, 10); } else { chr[index] = s[s.size() - 1] - a ; freq[index] += stoi(s, nullptr, 10); ++index; } } reverse(chr, chr + index); reverse(freq, freq + index); mid = index - mid - 1; index--; Zalgo(index); long long int ans = 0; chr[index] = -1; freq[index] = 0; for (int i = mid + 1; i <= index; ++i) { if (Z[i] == mid - 1 && chr[0] == chr[i - 1] && freq[0] <= freq[i - 1]) { if (mid == 1) { ans += freq[i - 1] - freq[0] + 1; } else { ++ans; } } else if (Z[i] == mid - 2 && chr[0] == chr[i - 1] && freq[0] <= freq[i - 1] && chr[mid - 1] == chr[i + mid - 2] && freq[mid - 1] <= freq[i + mid - 2]) { ++ans; } } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/16 11:09:41
// Design Name:
// Module Name: Chip_Decoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Chip_Decoder(
input A9,A8,F,A3,A2,AEN,IORbar,IOWbar,
output reg [3:0] CSbar,
output reg Ebar,DIR
);
reg [1:0] A;
parameter S0 = 0,S1 = 1,S2 = 2,S3 = 3;
always @(A9 or A8 or AEN or F or IORbar or IOWbar)
begin
if((A9 == 1) & (A8 == 1) & (AEN == 0) & F & (IORbar != IOWbar))
Ebar = 0;
else
Ebar = 1;
if((IORbar == 0) & (IOWbar ==1))
DIR = 0;
else
DIR = 1;
end
always @(A3 or A2)
begin
A = {A3,A2};
case(A)
S0 : CSbar = 4'b1110;
S1 : CSbar = 4'b1101;
S2 : CSbar = 4'b1011;
S3 : CSbar = 4'b0111;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_TB_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_TB_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbufhv2lv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg LVPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LVPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 LVPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 LVPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 LVPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 LVPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__lsbufhv2lv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .LVPWR(LVPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 205; int n; char s[N]; bool ck(int l, int r) { int a = 0, b = 0, c = 0, d = 0; for (int i = l; i <= r; i++) { if (s[i] == U ) a++; else if (s[i] == D ) b++; else if (s[i] == L ) c++; else d++; } if (a == b && c == d) return 1; else return 0; } int main() { scanf( %d , &n); scanf( %s , s); int ans = 0; for (int i = 0; i < n; i++) for (int j = i; j < n; j++) ans += ck(i, j); cout << ans << endl; return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module offset_to_mask
#(parameter C_MASK_SWAP = 1,
parameter C_MASK_WIDTH = 4)
(
input OFFSET_ENABLE,
input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
output [C_MASK_WIDTH-1:0] MASK
);
`include "functions.vh"
reg [7:0] _rMask,_rMaskSwap;
wire [3:0] wSelect;
assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
always @(*) begin
_rMask = 0;
_rMaskSwap = 0;
/* verilator lint_off CASEX */
casex(wSelect)
default: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b1111_1111;
end
4'b1000: begin
_rMask = 8'b0000_0001;
_rMaskSwap = 8'b1111_1111;
end
4'b1001: begin
_rMask = 8'b0000_0011;
_rMaskSwap = 8'b0111_1111;
end
4'b1010: begin
_rMask = 8'b0000_0111;
_rMaskSwap = 8'b0011_1111;
end
4'b1011: begin
_rMask = 8'b0000_1111;
_rMaskSwap = 8'b0001_1111;
end
4'b1100: begin
_rMask = 8'b0001_1111;
_rMaskSwap = 8'b0000_1111;
end
4'b1101: begin
_rMask = 8'b0011_1111;
_rMaskSwap = 8'b0000_0111;
end
4'b1110: begin
_rMask = 8'b0111_1111;
_rMaskSwap = 8'b0000_0011;
end
4'b1111: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b0000_0001;
end
endcase // casez ({OFFSET_MASK,OFFSET})
/* verilator lint_on CASEX */
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, t, x, y; long long pos_ji, pos_ou; while (~scanf( %lld%lld , &n, &t)) { while (t--) { scanf( %lld%lld , &x, &y); long long ji = n / 2 * n + (n + 1) / 2 + 1; long long ou = n / 2 * n + 1; pos_ji = (x - 1) * n + y; if (n % 2 != 0) { if (pos_ji % 2 == 0) printf( %lld n , ji + (pos_ji - 1) / 2); else printf( %lld n , (pos_ji + 1) / 2); } else { if (x % 2 != 0 && y % 2 != 0) { printf( %lld n , (x / 2) * n + (y + 1) / 2); } else if (x % 2 != 0 && y % 2 == 0) { printf( %lld n , ou + (x / 2) * n + (y - 1) / 2); } else if (x % 2 == 0 && y % 2 != 0) { printf( %lld n , ou + n / 2 + (x - 2) / 2 * n + y / 2); } else printf( %lld n , n / 2 + (x - 2) / 2 * n + y / 2); } } } return 0; }
|
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