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#include <bits/stdc++.h> using namespace std; int a[300001]; long long an[300001], dp[300001]; struct data { int x, y, No; void scan() { scanf( %d%d , &x, &y); } bool operator<(data b) const { if (y < b.y) return 0; if (y > b.y) return 1; int r1 = x % y, r2 = b.x % y; if (r1 < r2) return 0; if (r1 > r2) return 1; return No < b.No; } } d[300001]; int main() { int n, i, j, k, mi, p; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &p); for (i = 0; i < p; i++) d[i].scan(), d[i].No = i; sort(d, d + p); for (i = 0; i < p; i += j) { int tmp = d[i].x % d[i].y; mi = n; for (j = 0; i + j < p; j++) { if (d[i].y != d[i + j].y || d[i + j].x % d[i].y != tmp) break; mi = min(mi, d[i + j].x); } k = d[i].x + (n - d[i].x) / d[i].y * d[i].y; dp[k] = a[k]; for (k -= d[i].y; k >= mi; k -= d[i].y) dp[k] = a[k] + dp[k + d[i].y]; for (k = 0; k < j; k++) an[d[i + k].No] = dp[d[i + k].x]; } for (i = 0; i < p; i++) printf( %I64d n , an[i]); }
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//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_gt_rx_valid_filter_7x.v
// Version : 1.3
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
module pcie_7x_v1_3_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { char c; char prev; vector<int> A; int i = 0, count = 1; scanf( %c , &prev); A.push_back(1); while (scanf( %c , &c) != EOF) { if (c != + && c != - ) continue; if (c == prev) { A[i]++; } else { if (!(A[i] & 1)) { if (i != 0) { A[i - 1] += A[i]; A.erase(A.begin() + i); i--; } A[i]++; prev = c; } else { A.push_back(1); i++; prev = c; } } } int flag = 0; while (flag == 0 && A.size() != 1) { flag = 1; for (vector<int>::iterator it = A.begin(); it != A.end(); it++) { if (!((*it) & 1)) { flag = 0; if (it != A.begin()) { *it += *(it - 1); } if ((it + 1) != A.end()) { *it += *(it + 1); } if ((it + 1) != A.end()) A.erase(it + 1); if (it != A.begin()) A.erase(it - 1); break; } } } if (A.size() == 1 && !(A[0] & 1)) cout << Yes n ; else cout << No n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<vector<int>> grid(n, vector<int>(m, 0)); vector<vector<int>> up(n, vector<int>(m, 0)); vector<vector<int>> down(n, vector<int>(m, 0)); vector<vector<int>> left(n, vector<int>(m, 0)); vector<vector<int>> right(n, vector<int>(m, 0)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> grid[i][j]; } } for (int i = 0; i < n; i++) { left[i][0] = grid[i][0]; for (int j = 1; j < m; j++) { left[i][j] = left[i][j - 1] + grid[i][j]; } } for (int i = 0; i < n; i++) { right[i][m - 1] = grid[i][m - 1]; for (int j = m - 2; j >= 0; j--) { right[i][j] = right[i][j + 1] + grid[i][j]; } } for (int j = 0; j < m; j++) { up[0][j] = grid[0][j]; for (int i = 1; i < n; i++) { up[i][j] = up[i - 1][j] + grid[i][j]; } } for (int j = 0; j < m; j++) { down[n - 1][j] = grid[n - 1][j]; for (int i = n - 2; i >= 0; i--) { down[i][j] = down[i + 1][j] + grid[i][j]; } } int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (grid[i][j] == 1) continue; if (up[i][j] - grid[i][j] > 0) ans++; if (down[i][j] - grid[i][j] > 0) ans++; if (left[i][j] - grid[i][j] > 0) ans++; if (right[i][j] - grid[i][j] > 0) ans++; } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; string vow = aeiou ; const int dxhorse[] = {-2, -2, -1, -1, 1, 1, 2, 2}; const int dyhorse[] = {1, -1, 2, -2, 2, -2, 1, -1}; const int dx[] = {-1, 0, 0, 1}; const int dy[] = {0, -1, 1, 0}; const long double pie = 3.14159265358979; const long long mod = 1e9 + 7; void solve(int test_case) { int k; cin >> k; string s; cin >> s; int n = s.size(); vector<int> pref(n + 1); for (int i = 1; i < n + 1; i++) pref[i] = pref[i - 1] + s[i - 1] - 0 ; long long ans = 0; for (int i = 0; i < n; i++) { int x = pref[i + 1]; int val = x - k; if (val < 0) continue; ; int ans_indx = -1; for (int lo = 0, hi = i; lo <= hi;) { int mid = lo + hi >> 1; if (pref[mid] > val) hi = mid - 1; else if (pref[mid] == val) ans_indx = mid, hi = mid - 1; else lo = mid + 1; } if (ans_indx == -1) continue; ; long long L = ans_indx; ans_indx = -1; for (int lo = 0, hi = i; lo <= hi;) { int mid = lo + hi >> 1; if (pref[mid] == val) ans_indx = mid, lo = mid + 1; else if (pref[mid] < val) lo = mid + 1; else hi = mid - 1; } if (ans_indx == -1) continue; ; long long R = ans_indx; ans += R - L + 1; } cout << ans; cout << n ; } int main() { int t = 1; for (int i = 0; i < t; i++) solve(i); return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long max(long long a, long long b) { return a > b ? a : b; } inline long long min(long long a, long long b) { return a > b ? b : a; } template <typename T> inline int read(T& res) { long long x = 0, f = 1, flag = 0; char ch; flag = ch = getchar(); if (flag == -1) return -1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; flag = ch = getchar(); if (flag == -1) return -1; } while (ch >= 0 && ch <= 9 && flag != -1) { x = (x << 1) + (x << 3) + (ch ^ 48); flag = ch = getchar(); } res = x * f; return flag; } template <typename T, typename... Args> inline int read(T& t, Args&... a) { int res; res = read(t); if (res == -1) return -1; res = read(a...); return res; } const int maxn = 5511, mod = 1e9 + 9; long long n, m, k; long long qpow(long long x, long long y) { long long ans = 1; while (y) { if (y & 1) ans = (ans * x) % mod; y >>= 1; x = (x * x) % mod; } return ans % mod; } long long A1, A2, C1[maxn], C2[maxn], w, b; inline void solve() { long long ans = 0, mx = max(w, b); A1 = A2 = 1; for (int i = 2; i <= w; i++) A1 = (A1 * i) % mod; for (int i = 2; i <= b; i++) A2 = (A2 * i) % mod; C1[2] = w - 1; C2[2] = b - 1; C1[1] = C2[1] = 1; for (int i = 3; i <= mx; i++) { long long inv = qpow(i - 1, mod - 2); C1[i] = (C1[i - 1] * (w - i + 1) % mod * inv) % mod, C2[i] = (C2[i - 1] * (b - i + 1) % mod * inv) % mod; } int lim = max(1, n - w); for (int x = min(n - 2, b); x >= lim; x--) { ans = (ans + (((((n - x - 1) * A1 % mod) * C1[n - x] % mod) * A2) % mod) * C2[x]) % mod; } cout << ans << endl; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1; while (cin >> n >> w >> b) solve(); }
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#include <bits/stdc++.h> using namespace std; struct st { int x, y; bool operator<(const st o) const { return y < o.y || (y == o.y && x < o.x); } }; long long a[1000000][2]; long long n, m, x, y; long long M[1000000][2]; int main() { cin >> n >> m; cin >> M[0][0] >> M[0][1]; for (int i = 0; i < (int)(n); i++) { for (int j = 0; j < (int)(2); j++) { cin >> a[i][j]; } } for (int i = 1; i < 2 * n; i++) { for (int j = 0; j < (int)(2); j++) { M[i][j] = 2 * (a[(i - 1) % n][j]) - M[i - 1][j]; } } cout << M[m % (2 * n)][0] << << M[m % (2 * n)][1]; return 0; }
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#include <bits/stdc++.h> using namespace std; signed main() { long long int t; cin >> t; while (t--) { long long int n, x, i; cin >> n >> x; long long int second = 0; long long int a[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (i = n - 1; i >= 0; i--) { second += a[i]; if (second / (n - i) < x) break; } cout << n - (i + 1) << endl; } }
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:48:40 05/03/2015
// Design Name: control_unit
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_control_with_fetch.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: control_unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_control_with_fetch;
// Inputs
wire [15:0] IR;
//wire [15:0] IRR;
reg clock;
reg PC_source;
reg [11:0] PC_offset;
// Outputs
wire [2:0] reg_read_adr1;
wire [2:0] reg_read_adr2;
wire [2:0] reg_write_adr_d;
wire reg_write_d;
wire ALU_source2_d;
wire [7:0] ALU_con_d;
wire [15:0] offset_register;
wire mem_write_d;
wire mem_to_reg_d;
wire branch_d;
wire [3:0] branch_condition_d;
wire IEN;
// Instantiate the Unit Under Test (UUT)
control_unit uut (
.IR(IR),
.reg_read_adr1(reg_read_adr1),
.reg_read_adr2(reg_read_adr2),
.reg_write_adr_d(reg_write_adr_d),
.reg_write_d(reg_write_d),
.ALU_source2_d(ALU_source2_d),
.ALU_con_d(ALU_con_d),
.offset_register(offset_register),
.mem_write_d(mem_write_d),
.mem_to_reg_d(mem_to_reg_d),
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.IEN(IEN)
);
IR_fetch uutfetch (
.clock(clock),
.PC_source(PC_source),
.PC_offset(PC_offset),
.IR(IR)
);
initial begin
// Initialize Inputs
clock = 0;
PC_source = 0;
PC_offset = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
end
always #1 clock = !clock;
endmodule
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 550; struct DDF { int n; int v[maxn]; int dp[maxn][maxn]; int dfs(int l, int r) { if (l >= r) return dp[l][r] = 1; if (~dp[l][r]) return dp[l][r]; long long ans = dfs(l + 1, r); for (int i = l + 1; i <= r; i++) { if (v[l + 1] < v[i + 1]) { ans += 1LL * dfs(l + 1, i - 1) * (dfs(i, r)); ans %= mod; } } return dp[l][r] = ans; } void solve() { memset(dp, -1, sizeof dp); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); printf( %d n , dfs(1, n)); } } solver; int main() { solver.solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int h, n; cin >> n >> h; for (int i = 1; i <= n; i++) { if (i % 2 == 1) { for (int j = 1; j <= h; j++) { cout << # ; } } else { if ((i / 2) % 2 == 1) { for (int j = 1; j <= h - 1; j++) { cout << . ; } cout << # ; } else { cout << # ; for (int j = 1; j <= h - 1; j++) { cout << . ; } } } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long int; ll hell = 998244353; int main() { ll n; cin >> n; vector<ll> v[n]; for (ll i = 0; i < n; ++i) { ll x; cin >> x; for (ll j = 0; j < x; ++j) { ll y; cin >> y; v[i].push_back(y); } v[i].push_back(100009); sort(v[i].begin(), v[i].end()); } ll ans = 0; for (ll i = 0; i < n; ++i) { ll e = (i != 0) ? i - 1 : n - 1; ll f = (i != n - 1) ? i + 1 : 0; for (ll j = 1; j < v[i].size() - 1; ++j) { ll v1 = v[i][j]; ll v2 = v[i][j - 1]; ll c1 = lower_bound(v[e].begin(), v[e].end(), v1) - lower_bound(v[e].begin(), v[e].end(), v2); ll c2 = lower_bound(v[f].begin(), v[f].end(), v1) - lower_bound(v[f].begin(), v[f].end(), v2); if (c1 != c2) ans++; } } cout << ans << endl; return 0; }
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// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: COUNTER.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module COUNTER (
aclr,
clock,
cnt_en,
q);
input aclr;
input clock;
input cnt_en;
output [13:0] q;
wire [13:0] sub_wire0;
wire [13:0] q = sub_wire0[13:0];
lpm_counter LPM_COUNTER_component (
.aclr (aclr),
.clock (clock),
.cnt_en (cnt_en),
.q (sub_wire0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.clk_en (1'b1),
.cout (),
.data ({14{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 14;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "14"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: q 0 0 14 0 OUTPUT NODEFVAL "q[13..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: q 0 0 14 0 @q 0 0 14 0
// Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const int maxn = 400050; int n, x; long long w; vector<long long> val[4]; int Abs(int a) { return a < 0 ? -a : a; } int main() { scanf( %d , &n); long long sum = 0; for (int i = 0; i < n; i++) { scanf( %d%I64d , &x, &w); if (x == 11) val[0].push_back(w), sum += w; else if (x == 1) val[1].push_back(w), sum += w; else if (x == 10) val[2].push_back(w), sum += w; else val[3].push_back(w); } int len = val[3].size(); int cnt = n - len; int num = min(val[1].size(), val[2].size()); num += val[0].size(); for (int i = 0; i < 4; i++) sort(val[i].begin(), val[i].end()); long long ans = sum; int now1 = 0, now2 = 0; if (num * 2 < cnt) { ans = 0; int no = Abs(val[1].size() - val[2].size()); if (val[2].size() < val[1].size()) { for (int i = 0; i < no; i++) { if (num * 2 >= cnt) break; sum -= val[1][i]; cnt--; now1++; if (num * 2 >= cnt) ans = max(ans, sum); } } else { for (int i = 0; i < no; i++) { if (num * 2 >= cnt) break; sum -= val[2][i]; cnt--; now2++; if (num * 2 >= cnt) ans = max(ans, sum); } } if (num * 2 >= cnt) ans = max(ans, sum); } if (num * 2 > cnt) { ans = sum; int pos = 1; while (num * 2 >= cnt) { if (pos > len) break; if (num * 2 >= (cnt + 1)) { sum += val[3][len - pos]; ans = max(ans, sum); cnt++; } else break; pos++; } if (num * 2 >= cnt) ans = max(ans, sum); int no = Abs(val[2].size() - val[1].size()); if (val[2].size() > val[1].size()) { for (int i = now2; i < no; i++) { if (pos + i - now2 > len) break; sum -= val[2][i]; sum += val[3][len - i + now2 - pos]; if (num * 2 >= cnt) ans = max(ans, sum); } } else { for (int i = now1; i < no; i++) { if (pos + i - now1 > len) break; sum -= val[1][i]; sum += val[3][len - i + now1 - pos]; if (num * 2 >= cnt) ans = max(ans, sum); } } } else if (num * 2 == cnt) { int no = Abs(val[2].size() - val[1].size()); if (val[2].size() > val[1].size()) { for (int i = now2; i < no; i++) { if (i - now2 >= len) break; sum -= val[2][i]; sum += val[3][len - i + now2 - 1]; if (num * 2 >= cnt) ans = max(ans, sum); } } else { for (int i = now1; i < no; i++) { if (i - now1 >= len) break; sum -= val[1][i]; sum += val[3][len - i + now1 - 1]; if (num * 2 >= cnt) ans = max(ans, sum); } } } printf( %I64d n , ans); return 0; }
|
/* Basic Gates */
module or2(output Z, input A, B);
wire i;
not(Z, i);
nor(i, A, B);
endmodule
module or4(output Z, input A, B, C, D);
wire [1:0]i;
or2 o0(i[0], A, B),
o1(i[1], C, D),
o2(Z, i[0], i[1]);
endmodule
module and2(output Z, input A, B);
nand(nz, A, B);
not(Z, nz);
endmodule
module and3(output Z, input A, B, C);
wire i;
and2 a0(i, A, B),
a1(Z, i, C);
endmodule
module xnor2(output Z, input A, B);
wire [1:0]i;
not(na, A);
not(nb, B);
and2 a0(i[0], A, B),
a1(i[1], na, nb);
or2 o0(Z, i[0], i[1]);
endmodule
module xor2(output Z, input A, B);
wire [1:0]i;
not (na, A);
not (nb, B);
and2 a0(i[0], A, nb),
a1(i[1], na, B);
or2 o0(Z, i[0], i[1]);
endmodule
/* ALU OP Codes */
module op_00(output Z, input A, B);
or2 o(Z, A, B);
endmodule
module op_01(output Z, input A, B);
xor2 x(Z, A, B);
endmodule
module op_10(output Z, input A, B, C);
wire i;
xnor2 x(i, B, C);
and2 a(Z, i, A);
endmodule
module op_11(output Z, input A, B, C);
wire i;
xor2 x(i, A, B);
nand n(Z, i, C);
endmodule
/* Mux (4) */
module mux_4_1(output Z, input [1:0] sel, input [3:0] i);
wire [1:0]n_s;
wire [3:0]a;
not(n_s[0], sel[0]);
not(n_s[1], sel[1]);
and3 a0(a[0], n_s[1], n_s[0], i[0]),
a1(a[1], n_s[1], sel[0], i[1]),
a2(a[2], sel[1], n_s[0], i[2]),
a3(a[3], sel[1], sel[0], i[3]);
or4 o0(Z, a[0], a[1], a[2], a[3]);
endmodule
/* ALUs */
module alu_01(output Z, input [1:0]op, input A, B, C);
wire [3:0]op_z;
op_00 op00(op_z[0], A, B);
op_01 op01(op_z[1], A, B);
op_10 op10(op_z[2], A, B, C);
op_11 op11(op_z[3], A, B, C);
mux_4_1 mux(Z, op, op_z);
endmodule
module alu_02(output [1:0]Z, input [1:0]op, input [1:0] A, B, C);
alu_01 a0(Z[0], op, A[0], B[0], C[0]),
a1(Z[1], op, A[1], B[1], C[1]);
endmodule
module alu_04(output [3:0]Z, input [1:0]op, input [3:0] A, B, C);
alu_02 a0(Z[1:0], op, A[1:0], B[1:0], C[1:0]),
a1(Z[3:2], op, A[3:2], B[3:2], C[3:2]);
endmodule
module alu_08(output [7:0]Z, input [1:0]op, input [7:0] A, B, C);
alu_04 a0(Z[3:0], op, A[3:0], B[3:0], C[3:0]),
a1(Z[7:4], op, A[7:4], B[7:4], C[7:4]);
endmodule
module alu_16(output [15:0]Z, input [1:0]op, input [15:0] A, B, C);
alu_08 a0(Z[7:0], op, A[7:0], B[7:0], C[7:0]),
a1(Z[15:8], op, A[15:8], B[15:8], C[15:8]);
endmodule
module alu_32(output [31:0]Z, input [1:0]op, input [31:0] A, B, C);
alu_16 a0(Z[15:0], op, A[15:0], B[15:0], C[15:0]),
a1(Z[31:16], op, A[31:16], B[31:16], C[31:16]);
endmodule
/* Testbench */
module p2_tb();
reg [31:0]A, B, C;
reg [1:0]op;
wire [31:0] Z;
alu_32 device(Z, op, A, B, C);
integer op_i, val_i;
initial begin
$dumpfile("p2.vcd");
$dumpvars(0, device);
$monitor("op(%b) A=%b B=%b C=%b => %b", op, A, B, C, Z);
for( op_i = 0; op_i <= 'b11; op_i = op_i + 1) begin
op = op_i[1:0];
for(val_i = 0; val_i <= 'b111; val_i = val_i + 1) begin
A = {32{val_i[2]}};
B = {32{val_i[1]}};
C = {32{val_i[0]}};
#10;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, k; cin >> n >> m >> k; int a[m + 1]; for (int i = 0; i < m + 1; i++) { cin >> a[i]; } int ans = 0; for (int i = 0; i < m; i++) { int count = 0; for (int j = 0; j < n; j++) { if (((a[m] >> j) & 1) != ((a[i] >> j) & 1)) { count++; } } if (count <= k) ans++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int n, v; int main() { cin >> n >> v; int ans = 0; int p = 1; int cur = 0; for (int i = n - 1; i >= 0; i--, p++) { if (cur >= i) continue; ans += p * (min(i, v - cur)); cur = cur + min(i, v - cur) - 1; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int k[3], n, pos[200005]; int dp[200005][3]; int main() { ios::sync_with_stdio(0); for (int i = 0; i < 3; i++) cin >> k[i], n += k[i]; for (int t, p = 0; p < 3; p++) for (int i = 1; i <= k[p]; i++) { cin >> t, pos[t] = p; } for (int i = 1; i <= n; i++) { dp[i][0] = dp[i - 1][0] + (pos[i] != 0); dp[i][1] = ((dp[i - 1][0]) < (dp[i - 1][1]) ? (dp[i - 1][0]) : (dp[i - 1][1])) + (pos[i] != 1); dp[i][2] = ((dp[i - 1][0]) < (((dp[i - 1][1]) < (dp[i - 1][2]) ? (dp[i - 1][1]) : (dp[i - 1][2]))) ? (dp[i - 1][0]) : (((dp[i - 1][1]) < (dp[i - 1][2]) ? (dp[i - 1][1]) : (dp[i - 1][2])))) + (pos[i] != 2); } cout << ((dp[n][0]) < (((dp[n][1]) < (dp[n][2]) ? (dp[n][1]) : (dp[n][2]))) ? (dp[n][0]) : (((dp[n][1]) < (dp[n][2]) ? (dp[n][1]) : (dp[n][2])))); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_zckgatedcap_h.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_zckgatedcap_h (/*AUTOARG*/
// Inputs
ld
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
inout ld; //
endmodule
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk2_divide_by=25000 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=my_altpll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:23:18:05:48:SJ cbx_altiobuf_bidir 2013:10:23:18:05:48:SJ cbx_altiobuf_in 2013:10:23:18:05:48:SJ cbx_altiobuf_out 2013:10:23:18:05:48:SJ cbx_altpll 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_counter 2013:10:23:18:05:48:SJ cbx_lpm_decode 2013:10:23:18:05:48:SJ cbx_lpm_mux 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_stratixiii 2013:10:23:18:05:48:SJ cbx_stratixv 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
//CBXI_INSTANCE_NAME="Labx1_my_altpll_my_altpll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module my_altpll_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 1,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk2_divide_by = 25000,
pll1.clk2_duty_cycle = 50,
pll1.clk2_multiply_by = 1,
pll1.clk2_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //my_altpll_altpll
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; long long i, j, m, n, p, q, r, ans, l, ch = 1; string s; int f; vector<long long> v; int main() { cin >> s; l = s.size(); f = s.find( bear , 0); while (f >= 0) { p = f + 1; ch = abs(p - ch) + 1; q = p + 3; r = (l - q) + 1; ans += (r * ch); ch = p + 1; f = s.find( bear , ch); } cout << ans; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dma_write_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
reg req_valid = 1'b1;
wire req_ready;
reg [23:0] req_length = 'h03;
wire awvalid;
wire awready;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire [2:0] awprot;
wire [3:0] awcache;
wire wlast;
wire wvalid;
wire wready;
wire [3:0] wstrb;
wire [31:0] wdata;
reg [31:0] fifo_wr_din = 'b0;
reg fifo_wr_rq = 'b0;
wire fifo_wr_xfer_req;
wire bready;
wire bvalid;
wire [1:0] bresp;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
req_length <= req_length + 'h4;
end
end
axi_write_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.awvalid(awvalid),
.awready(awready),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awprot(awprot),
.awcache(awcache),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.bvalid(bvalid),
.bready(bready),
.bresp(bresp)
);
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32)
) i_transfer (
.m_dest_axi_aclk (clk),
.m_dest_axi_aresetn(resetn),
.m_axi_awvalid(awvalid),
.m_axi_awready(awready),
.m_axi_awaddr(awaddr),
.m_axi_awlen(awlen),
.m_axi_awsize(awsize),
.m_axi_awburst(awburst),
.m_axi_awprot(awprot),
.m_axi_awcache(awcache),
.m_axi_wready(wready),
.m_axi_wvalid(wvalid),
.m_axi_wdata(wdata),
.m_axi_wstrb(wstrb),
.m_axi_wlast(wlast),
.m_axi_bvalid(bvalid),
.m_axi_bready(bready),
.m_axi_bresp(bresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(1'b1),
.ctrl_pause(1'b0),
.req_eot(eot),
.req_response_ready(1'b1),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(30'h7e09000),
.req_x_length(req_length),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.fifo_wr_clk(clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(1'b1),
.fifo_wr_xfer_req(fifo_wr_xfer_req)
);
always @(posedge clk) begin
if (reset) begin
fifo_wr_din <= 'b0;
fifo_wr_rq <= 'b0;
end else begin
if (fifo_wr_en) begin
fifo_wr_din <= fifo_wr_din + 'h4;
end
fifo_wr_rq <= (($random % 4) == 0);
end
end
assign fifo_wr_en = fifo_wr_rq & fifo_wr_xfer_req;
always @(posedge clk) begin
if (reset) begin
failed <= 'b0;
end else begin
failed <= failed |
i_write_slave.failed |
fifo_wr_overflow;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n = 0, c = 0; float y = 0; int main() { if (!n) { scanf( %d , &n); main(); } else if (c == n) { printf( %.3f , 5 + y / n); return 0; } else { float x; scanf( %*f %f , &x); y += x; c++; main(); } }
|
// file: dacclk_mmcm_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module dacclk_mmcm_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [5:1] CLK_OUT,
// High bits of counters driven by clocks
output [5:1] COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 5;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
dacclk_mmcm clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
.CLK_OUT4 (clk_int[4]),
.CLK_OUT5 (clk_int[5]),
// Status and control signals
.LOCKED (LOCKED));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
BUFG clkout1_buf
(.O (clk[1]),
.I (clk_int[1]));
BUFG clkout2_buf
(.O (clk[2]),
.I (clk_int[2]));
BUFG clkout3_buf
(.O (clk[3]),
.I (clk_int[3]));
BUFG clkout4_buf
(.O (clk[4]),
.I (clk_int[4]));
BUFG clkout5_buf
(.O (clk[5]),
.I (clk_int[5]));
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000; int fs[100], ft[100]; char c[1050], s[100], t[100]; int dp[1050][100][100]; void GetNextval(char* p, int next[]) { int pLen = strlen(p); next[0] = -1; int k = -1; int j = 0; while (j < pLen) { if (k == -1 || p[j] == p[k]) { ++j; ++k; if (p[j] != p[k]) next[j] = k; else next[j] = next[k]; } else { k = next[k]; } } } int main() { scanf( %s%s%s , c, s, t); GetNextval(s, fs); GetNextval(t, ft); int nc = strlen(c); int ns = strlen(s); int nt = strlen(t); for (int i = 0; i <= nc; i++) for (int j = 0; j <= ns; j++) for (int k = 0; k <= nt; k++) dp[i][j][k] = -1e9; dp[0][0][0] = 0; for (int i = 0; i <= nc; i++) { for (char ch = a ; ch <= z ; ch++) { if (c[i] != * && ch != c[i]) continue; for (int j = 0; j <= ns; j++) { for (int k = 0; k <= nt; k++) { if (dp[i][j][k] == -1e9) continue; int jj = j; int kk = k; while (jj && ch != s[jj]) jj = fs[jj]; while (kk && ch != t[kk]) kk = ft[kk]; int f = 0; if (s[jj] == ch) jj++; if (t[kk] == ch) kk++; if (jj == ns) f++; if (kk == nt) f--; dp[i + 1][jj][kk] = max(dp[i + 1][jj][kk], dp[i][j][k] + f); } } } } int sum = -1e9; for (int j = 0; j <= ns; j++) for (int k = 0; k <= nt; k++) sum = max(sum, dp[nc][j][k]); printf( %d n , sum); }
|
#include <bits/stdc++.h> using namespace std; long long n, len, lcm, g, mod; long long a[266666], b[266666], c[266666], d[266666], e[266666], f[266666]; long long pw[266666], tmp[266666], w[2][266666], rev[266666]; long long mul(long long a, long long b) { return (a * b - (long long)(((long double)a * b + 0.5) / mod) * mod + mod) % mod; } long long qp(long long a, long long b) { long long c = 1; for (; b; b >>= 1, a = mul(a, a)) if (b & 1) c = mul(c, a); return c; } long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } void init() { for (len = 1; len <= 2 * n; len <<= 1) ; lcm = len / gcd(len, n) * n; mod = lcm + 1; while (mod < 5000000) mod += lcm; for (;; mod += lcm) { long long flag = 0; for (long long i = 2; i * i <= mod; i++) if (mod % i == 0) { flag = 1; break; } if (!flag) break; } for (g = 3;; g++) { long long flag = 0; for (long long i = 2; i * i <= mod - 1; i++) if ((mod - 1) % i == 0) { if (qp(g, i) == 1) { flag = 1; break; } if (qp(g, (mod - 1) / i) == 1) { flag = 1; break; } } if (!flag) break; } long long dan = qp(g, (mod - 1) / n); w[0][0] = w[1][0] = 1; for (long long i = 1; i < n; i++) w[0][i] = mul(w[0][i - 1], dan); for (long long i = 1; i < n; i++) w[1][i] = w[0][n - i]; for (long long i = 0; i < len; i++) { if (i & 1) rev[i] = (rev[i >> 1] >> 1) | (len >> 1); else rev[i] = rev[i >> 1] >> 1; } } void fft(long long *a, long long o) { for (long long i = 0; i < len; i++) if (i < rev[i]) swap(a[i], a[rev[i]]); for (long long k = 2, dan, now, t; k <= len; k <<= 1) { dan = qp(g, (o ? (mod - 1 - (mod - 1) / k) : (mod - 1) / k)); for (long long i = 0; i < len; i += k) { now = 1; for (long long j = 0; j < (k >> 1); j++, now = mul(now, dan)) { t = mul(a[i + j + (k >> 1)], now); a[i + j + (k >> 1)] = (a[i + j] - t + mod) % mod; a[i + j] = (a[i + j] + t) % mod; } } } if (o) { long long inv = qp(len, mod - 2); for (long long i = 0; i < len; i++) a[i] = mul(a[i], inv); } } void init(long long o) { for (long long i = 0; i < 2 * n; i++) pw[i] = w[o][(i * (i - 1) / 2) % n]; for (long long i = 2 * n; i < len; i++) pw[i] = 0; reverse(pw, pw + 2 * n); fft(pw, 0); } void dft(long long *a, long long o) { for (long long i = 0; i < n; i++) tmp[i] = mul(a[i], w[o][(n - (i * (i - 1) / 2) % n) % n]); for (long long i = n; i < len; i++) tmp[i] = 0; fft(tmp, 0); for (long long i = 0; i < len; i++) tmp[i] = mul(tmp[i], pw[i]); fft(tmp, 1); reverse(tmp, tmp + 2 * n); for (long long i = 0; i < n; i++) a[i] = mul(tmp[i], w[o][(n - (i * (i - 1) / 2) % n) % n]); if (o) { long long inv = qp(n, mod - 2); for (long long i = 0; i < n; i++) a[i] = mul(a[i], inv); } } long long ans[5], ans_cnt; signed main() { scanf( %lld , &n); init(); for (long long i = 0; i < n; i++) scanf( %lld , &b[i]); for (long long i = 0; i < n; i++) scanf( %lld , &c[i]); for (long long i = 0, inv = qp(mod - 2, mod - 2); i < n; i++) d[i] = mul((c[(i + 1) % n] - c[i] + mod) % mod, inv), e[i] = b[i]; init(0); dft(d, 0); reverse(e + 1, e + n); dft(e, 0); for (long long i = 0; i < n; i++) f[i] = mul(d[i], qp(e[i], mod - 2)); init(1); dft(f, 1); long long x2 = 0, x1 = 0, x0 = -c[0]; for (long long i = 0, now = 0, k; i < n; i++) { k = b[i] - now; x2++; x1 -= 2 * k; x0 += k * k; a[i] = ((f[i] < mod - f[i]) ? f[i] : f[i] - mod); if (a[i] > 1000000) { puts( 0 ); return 0; } now = now + a[i]; } long long det = x1 * x1 - 4 * x2 * x0, sq = sqrt(det); if (det < 0 || sq * sq != det) { puts( 0 ); return 0; } if (((-x1 - sq) % (2 * x2)) == 0) ans[++ans_cnt] = (-x1 - sq) / (2 * x2); if (((-x1 + sq) % (2 * x2)) == 0 && (!ans_cnt || sq)) ans[++ans_cnt] = (-x1 + sq) / (2 * x2); printf( %lld n , ans_cnt); if (!ans_cnt) return 0; for (long long t = 1, now; t <= ans_cnt; t++) { now = ans[t]; printf( %lld , now); for (long long i = 0; i < n - 1; i++) { now = now + a[i]; printf( %lld , now); } puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 80005, maxe = 3000005, maxs = 80005, INF = 0x3f3f3f3f; int n, q, N, m, S, T, a[maxn]; struct event { int x, l, r, f; event(int _x = 0, int _l = 0, int _r = 0, int _f = 0) : x(_x), l(_l), r(_r), f(_f) {} bool operator<(const event &b) const { return x < b.x || x == b.x && f > b.f; } } E[maxs]; int son[maxe], nxt[maxe], lnk[maxn], flw[maxe], cap[maxe], tot = 1; inline void add(int x, int y, int f) { son[++tot] = y; nxt[tot] = lnk[x]; lnk[x] = tot; flw[tot] = 0; cap[tot] = f; son[++tot] = x; nxt[tot] = lnk[y]; lnk[y] = tot; flw[tot] = 0; cap[tot] = 0; } int d[maxn], que[maxn], pos[maxn]; bool bfs() { memset(d, 63, sizeof(d)); int hed = 0, til = 1; que[1] = S; d[S] = 0; while (hed != til) { int x = que[++hed]; for (int j = lnk[x]; j; j = nxt[j]) if (d[son[j]] == INF && flw[j] < cap[j]) d[que[++til] = son[j]] = d[x] + 1; } return d[T] != INF; } int dfs(int x, int flow) { if (x == T || flow == 0) return flow; int res = 0, f; for (int &j = pos[x]; j; j = nxt[j]) if (d[son[j]] == d[x] + 1 && (f = dfs(son[j], min(flow, cap[j] - flw[j]))) > 0) { flw[j] += f; flw[j ^ 1] -= f; res += f; flow -= f; if (flow == 0) break; } return res; } int dinic() { int ans = 0; while (bfs()) { memcpy(pos, lnk, sizeof(lnk)); ans += dfs(S, INF); } return ans; } int ls[maxs], rs[maxs], Rx, Ry; void build(int &x, int l, int r, int d) { x = ++N; if (l == r) { if (d) add(x, T, 1); else add(S, x, 1); return; } int mid = l + r >> 1; build(ls[x], l, mid, d); build(rs[x], mid + 1, r, d); if (d) add(x, ls[x], INF), add(x, rs[x], INF); else add(ls[x], x, INF), add(rs[x], x, INF); } void qry(int x, int l, int r, int ql, int qr, int z, int d) { if (ql <= l && r <= qr) { if (d) add(z, x, INF); else add(x, z, INF); return; } if (qr < l || r < ql) return; int mid = l + r >> 1; qry(ls[x], l, mid, ql, qr, z, d); qry(rs[x], mid + 1, r, ql, qr, z, d); } void cover(int x, int l, int r) { for (int i = l; i <= r; i++) a[i] = x; } void work(int x, int l, int r) { for (int i = l, j = l; i <= r; i = j) { while (j <= r && a[i] == a[j]) j++; N++; qry(Rx, 1, n, a[i] + 1, x, N, 0); qry(Ry, 1, n, i, j - 1, N, 1); } } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= q; i++) { int x, y, xx, yy; scanf( %d%d%d%d , &x, &y, &xx, &yy); E[++m] = event(x - 1, y, yy, 0); E[++m] = event(xx, y, yy, 1); } S = ++N; T = ++N; build(Rx, 1, n, 0); build(Ry, 1, n, 1); sort(E + 1, E + 1 + m); for (int i = 1; i <= m; i++) if (E[i].f) cover(E[i].x, E[i].l, E[i].r); else work(E[i].x, E[i].l, E[i].r); work(n, 1, n); printf( %d , dinic()); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 11:10:00 10/17/2016
// Module Name: PIPELINE
// Project Name: MIPS
// Description: MIPS pipeline.
//
// Dependencies: I_FETCH.v, I_DECODE.v, I_EXECUTE.v, MEM.v, WB.v
//
////////////////////////////////////////////////////////////////////////////////
module PIPELINE(input clk);
// I_FETCH output wires.
wire [31:0] IF_ID_IR;
wire [31:0] IF_ID_NPC;
// I_DECODE output wires.
wire [1:0] ID_EX_WB_wire;
wire [2:0] ID_EX_M_wire;
wire [3:0] ID_EX_EX_wire;
wire [31:0] ID_EX_NPC_wire;
wire [31:0] ID_EX_rdata1out_wire;
wire [31:0] ID_EX_rdata2out_wire;
wire [31:0] ID_EX_IR_wire;
wire [4:0] ID_EX_instrout_2016_wire;
wire [4:0] ID_EX_instrout_1511_wire;
// Forwarding
wire [4:0] ID_EX_instrout_2521_wire;
// I_EXECUTE output wires.
wire [1:0] EX_MEM_wb_ctlout_wire;
wire [2:0] EX_MEM_m_ctlout_wire;
wire [31:0] EX_MEM_add_result_wire;
wire EX_MEM_zero_wire;
wire [31:0] EX_MEM_alu_result_wire;
wire [31:0] EX_MEM_rdata2out_wire;
wire [4:0] EX_MEM_five_bit_muxout_wire;
// MEM output wires.
wire PCSrc_wire;
wire [4:0] mem_Write_reg_wire;
wire [1:0] mem_control_wb_wire;
wire [31:0] Read_data_wire;
wire [31:0] mem_ALU_result_wire;
// WB output wires.
wire [31:0] wb_data_wire;
// Forwarding Unit wires.
wire [1:0] forward_a_sel_wire;
wire [1:0] forward_b_sel_wire;
I_FETCH FETCH(
// Inputs
.clk(clk),
.PCSrc(PCSrc_wire),
.EX_MEM_NPC(EX_MEM_add_result_wire),
// Outputs
.IF_ID_IR(IF_ID_IR),
.IF_ID_NPC(IF_ID_NPC));
I_DECODE DECODE(
// Inputs
.clk(clk),
.RegWrite(mem_control_wb_wire[1]),
.IF_ID_Instr(IF_ID_IR),
.IF_ID_NPC(IF_ID_NPC),
.MEM_WB_Writereg(mem_Write_reg_wire),
.MEM_WB_Writedata(wb_data_wire),
// Outputs
.WB(ID_EX_WB_wire),
.M(ID_EX_M_wire),
.EX(ID_EX_EX_wire),
.NPC(ID_EX_NPC_wire),
.rdata1out(ID_EX_rdata1out_wire),
.rdata2out(ID_EX_rdata2out_wire),
.IR(ID_EX_IR_wire),
.instrout_2016(ID_EX_instrout_2016_wire),
.instrout_1511(ID_EX_instrout_1511_wire),
// Forwarding
.instrout_2521(ID_EX_instrout_2521_wire));
I_EXECUTE EXECUTE(
// Inputs
.clk(clk),
.WB(ID_EX_WB_wire),
.M(ID_EX_M_wire),
.EX(ID_EX_EX_wire),
.NPC(ID_EX_NPC_wire),
.rdata1in(ID_EX_rdata1out_wire),
.rdata2in(ID_EX_rdata2out_wire),
.IR(ID_EX_IR_wire),
.instrout_2016(ID_EX_instrout_2016_wire),
.instrout_1511(ID_EX_instrout_1511_wire),
// Outputs
.wb_ctlout(EX_MEM_wb_ctlout_wire),
.m_ctlout(EX_MEM_m_ctlout_wire),
.add_result(EX_MEM_add_result_wire),
.zero(EX_MEM_zero_wire),
.alu_result(EX_MEM_alu_result_wire),
.rdata2out(EX_MEM_rdata2out_wire),
.five_bit_muxout(EX_MEM_five_bit_muxout_wire),
// Forwarding
.forward_a_sel(forward_a_sel_wire),
.forward_b_sel(forward_b_sel_wire),
.wb_data(wb_data_wire),
.mem_alu_result(EX_MEM_alu_result_wire));
MEM MEMORY(
// Inputs
.clk(clk),
.m_ctlout(EX_MEM_m_ctlout_wire[2]),
.zero(EX_MEM_zero_wire),
.MemWrite(EX_MEM_m_ctlout_wire[0]),
.MemRead(EX_MEM_m_ctlout_wire[1]),
.Write_data(EX_MEM_rdata2out_wire),
.control_wb_in(EX_MEM_wb_ctlout_wire),
.ALU_result_in(EX_MEM_alu_result_wire),
.Write_reg_in(EX_MEM_five_bit_muxout_wire),
// Outputs
.PCSrc(PCSrc_wire),
.mem_control_wb(mem_control_wb_wire),
.Read_data(Read_data_wire),
.mem_ALU_result(mem_ALU_result_wire),
.mem_Write_reg(mem_Write_reg_wire));
WB WRITEBACK(
// Inputs
.MemtoReg(mem_control_wb_wire[0]),
.ReadData(Read_data_wire),
.ALUResult(mem_ALU_result_wire),
// Outputs
.WriteData(wb_data_wire));
// Forwarding
FORWARDING_UNIT FU(
// Inputs
.rs(ID_EX_instrout_2521_wire),
.rt(ID_EX_instrout_2016_wire),
.five_bit_mux_out(EX_MEM_five_bit_muxout_wire),
.ex_mem_wb(EX_MEM_wb_ctlout_wire),
.mem_Write_reg(mem_Write_reg_wire),
.mem_wb_wb(mem_control_wb_wire),
// Outputs
.forward_a_sel(forward_a_sel_wire),
.forward_b_sel(forward_b_sel_wire));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_TB_V
`define SKY130_FD_SC_LP__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int NN = 1010; const int MM = 101010; struct Node { int id; int x, y; } Q[MM]; int a[NN][NN]; vector<int> adj[MM]; int ans[MM], f[MM]; int n, m, k; void dfs(int u, int fa = 0, int crr = 0) { if (Q[u].id == 1) { int x = Q[u].x, y = Q[u].y; if (!a[x][y]) { a[x][y] = 1; crr++; f[u] = 1; } } else if (Q[u].id == 2) { int x = Q[u].x, y = Q[u].y; if (a[x][y]) { a[x][y] = 0; crr--; f[u] = 1; } } else if (Q[u].id == 3) { int x = Q[u].x; for (int i = 1; i <= m; i++) { if (a[x][i]) crr--; else crr++; a[x][i] ^= 1; } } ans[u] = crr; for (int v : adj[u]) { if (v == fa) continue; dfs(v, u, ans[u]); } if (Q[u].id == 1) { int x = Q[u].x, y = Q[u].y; if (f[u]) a[x][y] = 0; } else if (Q[u].id == 2) { int x = Q[u].x, y = Q[u].y; if (f[u]) a[x][y] = 1; } else if (Q[u].id == 3) { int x = Q[u].x; for (int i = 1; i <= m; i++) a[x][i] ^= 1; } } int main() { cin >> n >> m >> k; for (int i = 1; i <= k; i++) { int id, x, y; scanf( %d , &id); if (id < 3) { scanf( %d %d , &x, &y); Q[i] = {id, x, y}; adj[i - 1].push_back(i); adj[i].push_back(i - 1); continue; } scanf( %d , &x); if (id == 4) { adj[x].push_back(i); adj[i].push_back(x); } else { adj[i - 1].push_back(i); adj[i].push_back(i - 1); } Q[i] = {id, x, 0}; } dfs(0); for (int i = 1; i <= k; i++) { printf( %d n , ans[i]); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_TB_V
`define SKY130_FD_SC_MS__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 09:06:21 2017
// Host : Shaun running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_stub.v
// Design : output_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module output_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[11:0],wr_en,rd_en,dout[11:0],full,empty" */;
input clk;
input srst;
input [11:0]din;
input wr_en;
input rd_en;
output [11:0]dout;
output full;
output empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int dr8[] = {0, 0, 1, -1, 1, 1, -1, -1}; int dc8[] = {1, -1, 0, 0, -1, 1, -1, 1}; int dr4[] = {0, 1, -1, 0}; int dc4[] = {1, 0, 0, -1}; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; int on = 1023; cin >> n; int z = 0; string s; for (int i = 0; i < n; i++) { cin >> s; int w; cin >> w; if (s[0] == | ) { z = z | w; on = on | w; } else if (s[0] == ^ ) { z = z ^ w; on = on ^ w; } else { z = z & w; on = on & w; } } int a[10]; int x1 = 0, x2 = 1023, x3 = 0; for (int i = 0; i < 10; i++) { if (z % 2 == on % 2 && on % 2 == 1) { a[i] = 1; x1 = x1 ^ (1 << i); } else if (z % 2 == on % 2 && on % 2 == 0) { a[i] = 0; x2 = x2 ^ (1 << i); } else if (z % 2 == 1 && on % 2 == 0) x3 = x3 ^ (1 << i); z = z / 2; on = on / 2; } cout << 3 << endl; cout << | << x1 << endl; cout << & << x2 << endl; cout << ^ << x3 << endl; }
|
#include <bits/stdc++.h> using namespace std; int const MAX = 200 * 1000 + 41; long double const EPS = 1e-12; bool eq(long double a, long double b) { return abs(a - b) < EPS; } bool leq(long double a, long double b) { return (a < b || eq(a, b)); } int n, w; int x[MAX]; int v[MAX]; pair<long double, long double> a[MAX]; pair<int, int> b[MAX]; int const ADD = 0; int const ASK = 1; struct Event { int y, s, t; Event(){}; Event(int y, int s, int t) : y(y), s(s), t(t){}; bool operator<(const Event &a) const { if (t != a.t) return t < a.t; return y < a.y; }; }; vector<Event> e[MAX]; int gethash(vector<long double> &v, long double x) { int l = -1; int r = (int)v.size(); while (r - l > 1) { int h = (l + r) / 2; if (leq(v[h], x)) { l = h; } else { r = h; } } return l; } void init() { vector<long double> tmp; for (int i = 1; i <= n; i++) { long double l = (long double)v[i] / x[i] - (long double)w / x[i]; long double r = (long double)v[i] / x[i] + (long double)w / x[i]; a[i] = make_pair(l, r); tmp.push_back(l); tmp.push_back(r); } sort(tmp.begin(), tmp.end()); for (int i = 1; i <= n; i++) { b[i] = make_pair(gethash(tmp, a[i].first), gethash(tmp, a[i].second)); } for (int i = 1; i <= n; i++) { int x = b[i].first; int y = b[i].second; e[x].push_back(Event(y, 41, ADD)); e[x].push_back(Event(y, -1, ASK)); e[MAX - 1].push_back(Event(y, 1, ASK)); } } namespace Fen { int F[MAX]; void upd(int x, int v) { while (x < MAX) { F[x] += v; x |= (x + 1); } } int get(int x) { int res = 0; while (x >= 0) { res += F[x]; x = (x & (x + 1)) - 1; } return res; } }; // namespace Fen long long ans; void solve() { init(); for (int i = 1; i <= n; i++) { while (false) { }; } for (int i = 0; i <= MAX - 1; i++) { sort(e[i].begin(), e[i].end()); for (Event z : e[i]) { if (z.t == ADD) { Fen::upd(z.y, 1); } else { int q = Fen::get(z.y); ans += q * z.s; } } } unordered_map<int, int> ql; for (int i = 1; i <= n; i++) { ql[b[i].first]++; ans += ql[b[i].first] - 1; } printf( %lld n , ans); } int main() { scanf( %d %d , &n, &w); for (int i = 1; i <= n; i++) { scanf( %d %d , &x[i], &v[i]); } solve(); return 0; }
|
module EX_MEM_Seg(
input Clk,
input stall,
input flush,
input [31:0] Branch_addr,PC_add,
input [2:0] Condition,
input Branch,
input [2:0]PC_write,
input [3:0]Mem_Byte_Write,Rd_Write_Byte_en,
input MemWBSrc,OverflowEn,
input [31:0] MemData,WBData,
input Less,Zero,Overflow,
input [4:0]Rd,
output reg [31:0] Branch_addr_out,PC_add_out,
output reg [2:0] Condition_out,
output reg Branch_out,
output reg [2:0]PC_write_out,
output reg [3:0]Mem_Byte_Write_out,Rd_Write_Byte_en_out,
output reg MemWBSrc_out,OverflowEn_out,
output reg [31:0] MemData_out,WBData_out,
output reg Less_out,Zero_out,Overflow_out,
output reg [4:0]Rd_out
);
always@(posedge Clk)
begin
if(flush)
begin
OverflowEn_out <= 1'b0;
Branch_addr_out <= 32'b0;
PC_add_out <= 32'b0;
Condition_out <= 3'b0;
Branch_out <= 1'b0;
PC_write_out =3'b0;
Mem_Byte_Write_out <= 4'b0;
Rd_Write_Byte_en_out <= 4'b0;
MemWBSrc_out <= 1'b0;
MemData_out <= 32'h0;
WBData_out <= 32'b0;
Less_out <= 1'b0;
Zero_out <= 1'b0;
Overflow_out <= 1'b0;
Rd_out <= 5'b0;
end
else if(~stall)
begin
OverflowEn_out <= OverflowEn;
Branch_addr_out <= Branch_addr;
PC_add_out <= PC_add;
Condition_out <= Condition;
Branch_out <= Branch;
PC_write_out = PC_write;
Mem_Byte_Write_out <= Mem_Byte_Write;
Rd_Write_Byte_en_out <= Rd_Write_Byte_en;
MemWBSrc_out <= MemWBSrc;
MemData_out <= MemData;
WBData_out <= WBData;
Less_out <= Less;
Zero_out <= Zero;
Overflow_out <= Overflow;
Rd_out <= Rd;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_TB_V
`define SKY130_FD_SC_HDLL__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_TB_V
|
module rfid_reader_rx (
// basic connections
reset, clk, tag_backscatter,
// logistics
rx_done, rx_timeout,
// modulation infomation
miller, trext, divide_ratio,
// timing information
rtcal_counts, trcal_counts, tari_counts,
// received data
rx_data, rx_dataidx
);
input reset, clk, tag_backscatter;
output rx_done, rx_timeout;
input [2:0] miller;
input trext;
input divide_ratio;
input [15:0] tari_counts;
input [15:0] rtcal_counts;
input [15:0] trcal_counts;
output [1023:0] rx_data;
output [9:0] rx_dataidx;
reg [1023:0] rx_data;
reg [9:0] rx_dataidx;
reg rx_done;
// clock and recovery
reg [15:0] rx_period;
reg [15:0] rx_counter;
// timeout detector
assign rx_timeout = (rx_counter > rtcal_counts<<2);
// modulator edge detector -> clock generator for bit slicer
reg previousbit;
reg edgeclk;
reg [15:0] count;
always @ (posedge clk or posedge reset) begin
if (reset) begin
previousbit <= 0;
edgeclk <= 0;
count <= 0;
rx_counter <= 0;
end else begin
if (tag_backscatter != previousbit) begin
edgeclk <= 1;
previousbit <= tag_backscatter;
count <= 0;
end else begin
edgeclk <= 0;
count <= count + 1;
rx_counter <= count + 1;
end
end
end
reg [4:0] rx_state;
parameter STATE_CLK_UP = 0;
parameter STATE_CLK_DN = 1;
parameter STATE_PREAMBLE = 2;
parameter STATE_DATA1 = 3;
parameter STATE_DATA2 = 4;
parameter STATE_DATA3 = 5;
parameter STATE_DATA4 = 6;
parameter STATE_DATA5 = 7;
parameter STATE_DATA6 = 8;
parameter STATE_DATA7 = 9;
parameter STATE_DATA8 = 10;
wire isfm0, ism2, ism4, ism8;
assign isfm0 = (miller == 0);
assign ism2 = (miller == 1);
assign ism4 = (miller == 2);
assign ism8 = (miller == 3);
wire count_lessthan_period;
assign count_lessthan_period = (rx_counter <= rx_period);
wire fm0_preamble_done;
assign fm0_preamble_done = (rx_dataidx >= 5);
wire [15:0] rx_counter_by2;
assign rx_counter_by2 = rx_counter >> 1;
// bit slicer / parser
always @ (posedge edgeclk or posedge reset) begin
if (reset) begin
rx_state <= 0;
rx_dataidx <= 0;
rx_data <= 0;
end else begin
case(rx_state)
STATE_CLK_UP: begin
rx_state <= STATE_CLK_DN;
rx_dataidx <= 0;
rx_data <= 0;
end
STATE_CLK_DN: begin
if(isfm0 & ~trext) rx_period <= rx_counter_by2;
else rx_period <= rx_counter;
rx_state <= STATE_PREAMBLE;
end
STATE_PREAMBLE: begin
if(isfm0) begin
if( fm0_preamble_done ) begin
rx_state <= STATE_DATA1;
rx_dataidx <= 0;
end else begin
rx_dataidx <= rx_dataidx + 1;
end
end
end
STATE_DATA1: begin
if(isfm0) begin
// data 0
if( count_lessthan_period ) begin
rx_state <= STATE_DATA2;
rx_data[rx_dataidx] <= 0;
rx_dataidx <= rx_dataidx + 1;
// data 1
end else begin
rx_data[rx_dataidx] <= 1;
rx_dataidx <= rx_dataidx + 1;
end
end else begin // todo:
// data 0
if( count_lessthan_period ) begin
rx_state <= STATE_DATA2;
rx_data[rx_dataidx] <= 0;
rx_dataidx <= rx_dataidx + 1;
// data 1
end else begin
rx_data[rx_dataidx] <= 1;
rx_dataidx <= rx_dataidx + 1;
end
end
end
STATE_DATA2: begin
if(isfm0) begin
rx_state <= STATE_DATA1;
end else begin
rx_state <= STATE_DATA1; // todo:
end
end
default begin
rx_state <= 0;
end
endcase
end
end
endmodule
|
/*
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| eg_step/ | | 3/3 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_step |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
*/
module eg_step(
input [2:0] state_V,
input [5:0] rate_V,
input [2:0] cnt_V,
output reg step_V
);
localparam ATTACK=3'd0, DECAY1=3'd1, DECAY2=3'd2, RELEASE=3'd7, HOLD=3'd3;
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate_V[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate_V[5:2]==4'hf && state_V == ATTACK)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate_V[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate_V[5:2]==4'd0 && state_V != ATTACK)
step_idx = 8'b11111110; // limit slowest decay rate_IV
else
case( rate_V[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate_IV of zero keeps the level still
step_V = rate_V[5:1]==5'd0 ? 1'b0 : step_idx[ cnt_V ];
end
endmodule // eg_step
|
module test_lut_n();
//This is a test-bench for the look-up table. The point is to make sure that different instances of lut_n can
//reference different lookup tables stored in the (`include-d) file, cornerNclk.v.
//
//Ted Golfinopoulos, 13 Mar 2012
reg clk;
reg [13:0] n_clk_cnts; //Holds (imagined) clock counter - number of clock periods.
wire [6:0] stateSer, statePar; //Register variables for outputs from lut_n.
//Instantiate a series and parallel lut_n
lut_n serLut(clk, n_clk_cnts, stateSer);
lut_n parLut(clk, n_clk_cnts, statePar);
//Tell each lut_n module instance to look at different look-up table.
defparam serLut.LOOKUP_ID=1;
defparam parLut.LOOKUP_ID=2;
//Don't dump variables.
//initial begin
// $dumpfile ("test_lut_n_output.vcd");
// $dumpvars;
//end
initial begin
$display("\tTime\tState Ser\tState Par");
$monitor("\t%d\t%b\t%b",$time, stateSer, statePar);
end
initial begin
#0 clk=0; //Initialize clock.
n_clk_cnts=1'b0; //Initialize period counter
end
//Main simulation block
initial begin
#10 //Wait five clock cycles (10 inversions of clock state).
//Sweep up in frequency => down in n_clk_cnts
//From 40 kHz to 300 kHz => (#sync counts)/(input freq) * clk_freq = 50/40E3*4E6 = 1001110001000; 50/300E3*4E6=
for (n_clk_cnts=14'b1001110001000; n_clk_cnts>=14'b1010011010; n_clk_cnts=n_clk_cnts-1'b1) begin
#2; //Delay one full clock cycle
//if(n_clk_cnts % 10000==0) $display(n_clk_cnts);
end
//Sweep down in frequency => up in n_clk_cnts
for (n_clk_cnts=14'b1010011010; n_clk_cnts<=14'b1001110001000; n_clk_cnts=n_clk_cnts+1'b1) begin
#2; //Delay one full clock cycle
// if(n_clk_cnts % 10000==0) $display(n_clk_cnts);
end
#5 $finish; //Stop simulation.
end
always begin
#1
clk=~clk;
end
endmodule
|
module I2C_AV_Config ( // Host Side
iCLK,
iRST_N,
o_I2C_END,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input iCLK;
input iRST_N;
output o_I2C_END;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
reg o_I2C_END;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 50;
// Audio Data Index
parameter SET_LIN_L = 0;
parameter SET_LIN_R = 1;
parameter SET_HEAD_L = 2;
parameter SET_HEAD_R = 3;
parameter A_PATH_CTRL = 4;
parameter D_PATH_CTRL = 5;
parameter POWER_ON = 6;
parameter SET_FORMAT = 7;
parameter SAMPLE_CTRL = 8;
parameter SET_ACTIVE = 9;
// Video Data Index
parameter SET_VIDEO = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
o_I2C_END <= 0 ;
case(mSetup_ST)
0: begin
if(LUT_INDEX<SET_VIDEO)
mI2C_DATA <= {8'h34,LUT_DATA};
else
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
else begin
o_I2C_END <= 1 ;end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
SET_LIN_L : LUT_DATA <= 16'h001A;
SET_LIN_R : LUT_DATA <= 16'h021A;
SET_HEAD_L : LUT_DATA <= 16'h047B;
SET_HEAD_R : LUT_DATA <= 16'h067B;
A_PATH_CTRL : LUT_DATA <= 16'h08F8;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E01;
SAMPLE_CTRL : LUT_DATA <= 16'h1002;
SET_ACTIVE : LUT_DATA <= 16'h1201;
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0b00;
SET_VIDEO+31: LUT_DATA <= 16'h0a20;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df2;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
default: LUT_DATA <= 16'hxxxx;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_TB_V
`define SKY130_FD_SC_LP__A41OI_TB_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a41oi dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; long long mod = (1e9 + 7); int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } bool is_vowel(char c) { if (c == a || c == e || c == i || c == o || c == u ) return 1; return 0; } double getDistance(double x1, double y1, double x2, double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } long long extended_euclidean(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long g = extended_euclidean(b, a % b, y, x); y -= (a / b) * x; return g; } long long power(long long base, long long p) { if (p == 1) return base; if (!p) return 1ll; long long ret = power(base, p / 2); ret *= ret; ret %= mod; if (p & 1) ret *= base; return ret % mod; } vector<int> v; map<int, int> mp; int n; int solve(long long sum, long long a, long long b, long long c) { v.clear(); int mn = n, A = 0, B = 0, C = 0; for (int i = (0); i <= (n); ++i) { long long cur = sum - a * i; int cost = min(i, mp[a]); long long mx = c * (n - i); int taken2 = n - i; int taken1 = 0; if (mx > cur) { long long delta = mx - cur; taken2 -= delta; taken1 += delta; mx = cur; } if (mx == cur && taken1 + taken2 == n - i && taken1 >= 0 && taken2 >= 0) { cost += min(mp[b], taken1); cost += min(mp[c], taken2); mn = min(mn, cost); if (mn == cost) { A = i; B = taken1; C = taken2; } } } while (A--) v.push_back(a); while (B--) v.push_back(b); while (C--) v.push_back(c); return mn; } int main() { scanf( %d , &n); set<long long> st; long long sum = 0; vector<int> z; for (int i = (0); i <= (n - 1); ++i) { int a; scanf( %d , &a); st.insert(a); mp[a]++; sum += a; z.push_back(a); } vector<long long> x(st.begin(), st.end()); long long mn = *(st.begin()); long long mx = *(--st.end()); int sol = n; if (abs(mn - mx) < 2) { cout << n << endl; for (int i = (0); i <= (n - 1); ++i) { cout << z[i] << ; } return 0; } sol = solve(sum, mn, mn + 1, mn + 2); cout << sol << endl; for (int i = (0); i <= (n - 1); ++i) cout << v[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; cout << 1 + 6 * (n) * (n + 1) / 2 << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long int inf = 1e9 + 7; const long long int mod = 998244353; long long int mini(long long int a, long long int b) { if (a >= b) return b; return a; } long long int maxi(long long int a, long long int b) { if (a >= b) return a; return b; } const long long int MAXN = 300002; long long int factorial[MAXN + 1], inverse[MAXN + 1]; long long int binpow(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b % 2 == 1) { res = (res * a) % mod; } a = (a * a) % mod; b >>= 1; } return res; } long long int nCk(long long int n, long long int k) { if (k < 0 || k > n) { return 0; } long long int ans = factorial[n]; ans = (ans * inverse[n - k]) % mod; ans = (ans * inverse[k]) % mod; return ans; } void preCompute() { long long int fact = 1; factorial[0] = 1; inverse[0] = 1; for (long long int i = 1; i <= MAXN; i++) { fact = (fact * i) % mod; factorial[i] = fact; inverse[i] = binpow(factorial[i], mod - 2); } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); preCompute(); long long int n; cin >> n; long long int sumr = 0, suml = 0; vector<long long int> A(2 * n); for (long long int i = 0; i <= 2 * n - 1; i++) cin >> A[i]; sort(A.begin(), A.end()); for (long long int i = 0; i <= n - 1; i++) suml += A[i], suml %= mod; for (long long int i = n; i <= 2 * n - 1; i++) sumr += A[i], sumr %= mod; long long int tot = (mod + sumr - suml) % mod; long long int a = nCk(2 * n, n); long long int ans = (a * tot) % mod; cout << ans; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 14:48:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_pll_0_0 -prefix
// system_vga_pll_0_0_ system_vga_pll_0_0_sim_netlist.v
// Design : system_vga_pll_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_pll_0_0,vga_pll,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_pll,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_pll_0_0
(clk_100,
clk_50,
clk_25,
clk_12_5,
clk_6_25);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_100 CLK" *) input clk_100;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_50 CLK" *) output clk_50;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_25 CLK" *) output clk_25;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_12_5 CLK" *) output clk_12_5;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_6_25 CLK" *) output clk_6_25;
wire clk_100;
wire clk_12_5;
wire clk_25;
wire clk_50;
wire clk_6_25;
system_vga_pll_0_0_vga_pll U0
(.clk_100(clk_100),
.clk_12_5(clk_12_5),
.clk_25(clk_25),
.clk_50(clk_50),
.clk_6_25(clk_6_25));
endmodule
module system_vga_pll_0_0_vga_pll
(clk_50,
clk_25,
clk_12_5,
clk_6_25,
clk_100);
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
input clk_100;
wire clk_100;
wire clk_12_5;
wire clk_12_5_s_i_1_n_0;
wire clk_25;
wire clk_25_s_i_1_n_0;
wire clk_50;
wire clk_6_25;
wire clk_6_25_s_i_1_n_0;
wire p_0_in;
LUT1 #(
.INIT(2'h1))
clk_12_5_s_i_1
(.I0(clk_12_5),
.O(clk_12_5_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_12_5_s_reg
(.C(clk_25),
.CE(1'b1),
.D(clk_12_5_s_i_1_n_0),
.Q(clk_12_5),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_25_s_i_1
(.I0(clk_25),
.O(clk_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_25_s_reg
(.C(clk_50),
.CE(1'b1),
.D(clk_25_s_i_1_n_0),
.Q(clk_25),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_50_s_i_1
(.I0(clk_50),
.O(p_0_in));
FDRE #(
.INIT(1'b0))
clk_50_s_reg
(.C(clk_100),
.CE(1'b1),
.D(p_0_in),
.Q(clk_50),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_6_25_s_i_1
(.I0(clk_6_25),
.O(clk_6_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_6_25_s_reg
(.C(clk_6_25),
.CE(1'b1),
.D(clk_6_25_s_i_1_n_0),
.Q(clk_6_25),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; string name[7]; int a, b, c, n, max_p, dexp, was[7]; bool p[7][7]; void perebor(int point, int num); int main() { name[0] = Anka ; name[1] = Chapay ; name[2] = Cleo ; name[3] = Troll ; name[4] = Dracul ; name[5] = Snowy ; name[6] = Hexadecimal ; cin >> n; for (int i = 0; i < n; i++) { int a, b; string name1, name2, s; cin >> name1 >> s >> name2; for (int j = 0; j < 7; j++) { if (name[j] == name1) a = j; if (name[j] == name2) b = j; } p[a][b] = true; } cin >> a >> b >> c; dexp = (int)1e9 * 2 + 1; max_p = -1; perebor(1, 0); cout << dexp << << max_p; return 0; } void perebor(int point, int num) { if (point == 4 && num != 7) return; if (num == 7) { int c_p = 0, t[4], ans; for (int i = 0; i < 4; i++) t[i] = 0; for (int i = 0; i < 7; i++) { t[was[i]]++; for (int j = 0; j < 7; j++) if (was[i] == was[j] && p[i][j] == true && i != j) c_p++; } if (!(t[1] && t[2] && t[3])) return; else { ans = max(ceil(a / t[1]), max(ceil(b / t[2]), ceil(c / t[3]))) - min(ceil(a / t[1]), min(ceil(b / t[2]), ceil(c / t[3]))); if (ans <= dexp) { if (ans < dexp) max_p = 0; dexp = ans; if (max_p < c_p) max_p = c_p; } } return; } for (int i = 0; i < 7; i++) if (was[i] == 0) { was[i] = point; perebor(point, num + 1); perebor(point + 1, num + 1); was[i] = 0; } return; }
|
#include <bits/stdc++.h> using namespace std; int c[3]; void solve() { int m, n; cin >> m >> n; vector<vector<int>> matrix(m, vector<int>(n)); for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cin >> matrix[i][j]; } } for (int i = m - 1; i >= 0; --i) { for (int j = n - 1; j >= 0; --j) { if (matrix[i][j] != 0) { continue; } else { int check; check = matrix[i][j + 1] - 1; if (check >= matrix[i + 1][j]) check = matrix[i + 1][j] - 1; matrix[i][j] = check; } } } for (int i = m - 1; i >= 0; --i) { for (int j = n - 1; j >= 0; --j) { if (i != 0 && j != 0) { if ((matrix[i][j] <= matrix[i][j - 1]) || (matrix[i][j] <= matrix[i - 1][j])) { cout << -1 << endl; return; } } } } int sum = 0; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { sum += matrix[i][j]; } } cout << sum << endl; return; } int main() { solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EBUFN_PP_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_TB_V
`define SKY130_FD_SC_LP__OR2_TB_V
/**
* or2: 2-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_TB_V
|
`timescale 1ns / 1ps
module Approx_adder
#(parameter W=26, parameter LowL=16) (
input wire add_sub,
input wire [W-1:0] in1,
input wire [W-1:0] in2,
output wire [W:0] res
);
wire [W-1:0] in2_signed;
wire [LowL-1:0] lower_res;
wire approx_cout;
`ifdef ACAIN16Q4
assign in2_signed = (add_sub) ? ~in2 : in2;
ACA_I_N16_Q4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ETAIIN16Q4
assign in2_signed = (add_sub) ? ~in2 : in2;
ETAII_N16_Q4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ETAIIN16Q8
assign in2_signed = (add_sub) ? ~in2 : in2;
ETAII_N16_Q8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ACAIIN16Q4
assign in2_signed = (add_sub) ? ~in2 : in2;
ACA_II_N16_Q4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ACAIIN16Q8
assign in2_signed = (add_sub) ? ~in2 : in2;
ACA_II_N16_Q8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GDAN16M4P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GDA_St_N16_M4_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GDAN16M4P8
assign in2_signed = (add_sub) ? ~in2 : in2;
GDA_St_N16_M4_P8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R2P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R2_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R4P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R4_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R4P8
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R4_P8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL4
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(4), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL5
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(5), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL6
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(6), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL7
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(7), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL8
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(8), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL9
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(9), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL10
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(10), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL11
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(11), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL12
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(12), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL13
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(13), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R6P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R6_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`else
assign res = (add_sub) ? (in1 - in2) : (in1 + in2);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = std::numeric_limits<int>::max() / 3; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } int dp[6000][6000]; long long sum[1000000]; long long min(long long a, long long b) { return a < b ? a : b; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, k; cin >> n >> k; vector<long long> a; for (int i = 0, t; i < n; ++i) { cin >> t; a.push_back(t); } sort(a.begin(), a.end()); int sz = n / k; int A = (n % k); int B = k - A; sum[0] = 0; for (int i = 1; i < n; ++i) sum[i] = sum[i - 1] + a[i] - a[i - 1]; for (int i = 0; i <= A; ++i) for (int j = 0; j <= B; ++j) dp[i][j] = 2e9 + 1; dp[0][0] = 0; for (int i = 0; i <= A; ++i) { for (int j = 0; j <= B; ++j) { int x = (i + j) * sz + i; if (i < A) { long long t = dp[i][j] + sum[x + sz] - sum[x]; dp[i + 1][j] = min(dp[i + 1][j] * 1LL, t); } if (j < B) { long long t = dp[i][j] + sum[x + sz - 1] - sum[x]; dp[i][j + 1] = min(dp[i][j + 1] * 1LL, t); } } } cout << dp[A][B] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 200015; const int nil = 100005; int n; set<pair<int, int> > S; set<pair<int, int> > T; int w[Maxn]; vector<pair<int, int> > cand[Maxn]; pair<int, int> res[Maxn]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { int x, y; scanf( %d %d , &x, &y); S.insert(pair<int, int>(x, y)); } for (int i = 1; i <= n; i++) scanf( %d , &w[i]); for (set<pair<int, int> >::iterator it = S.begin(); it != S.end(); it++) { pair<int, int> p = *it; if (S.find(pair<int, int>(p.first + 1, p.second)) == S.end() && S.find(pair<int, int>(p.first, p.second + 1)) == S.end()) { cand[p.second - p.first + nil].push_back(p); T.insert(p); } } for (int i = n; i >= 1; i--) { int diag = w[i] + nil; if (cand[diag].empty()) { printf( NO n ); return 0; } pair<int, int> p = cand[diag].back(); cand[diag].pop_back(); res[i] = p; pair<int, int> u = pair<int, int>(p.first - 1, p.second); if (S.find(u) != S.end() && T.find(u) == T.end()) { cand[u.second - u.first + nil].push_back(u); T.insert(u); } u = pair<int, int>(p.first, p.second - 1); if (S.find(u) != S.end() && T.find(u) == T.end()) { cand[u.second - u.first + nil].push_back(u); T.insert(u); } } printf( YES n ); for (int i = 1; i <= n; i++) printf( %d %d n , res[i].first, res[i].second); return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module sysctl #(
parameter csr_addr = 4'h0,
parameter ninputs = 16,
parameter noutputs = 16,
parameter clk_freq = 32'h00000000,
parameter systemid = 32'habadface
) (
input sys_clk,
input sys_rst,
/* Interrupts */
output reg gpio_irq,
output reg timer0_irq,
output reg timer1_irq,
/* CSR bus interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
/* GPIO */
input [ninputs-1:0] gpio_inputs,
output reg [noutputs-1:0] gpio_outputs,
input [31:0] capabilities,
output reg debug_write_lock,
output reg bus_errors_en,
output reg hard_reset
);
/*
* GPIO
*/
/* Synchronize the input */
reg [ninputs-1:0] gpio_in0;
reg [ninputs-1:0] gpio_in;
always @(posedge sys_clk) begin
gpio_in0 <= gpio_inputs;
gpio_in <= gpio_in0;
end
/* Detect level changes and generate IRQs */
reg [ninputs-1:0] gpio_inbefore;
always @(posedge sys_clk) gpio_inbefore <= gpio_in;
wire [ninputs-1:0] gpio_diff = gpio_inbefore ^ gpio_in;
reg [ninputs-1:0] gpio_irqen;
always @(posedge sys_clk) begin
if(sys_rst)
gpio_irq <= 1'b0;
else
gpio_irq <= |(gpio_diff & gpio_irqen);
end
/*
* Dual timer
*/
reg en0, en1;
reg ar0, ar1;
reg [31:0] counter0, counter1;
reg [31:0] compare0, compare1;
wire match0 = (counter0 == compare0);
wire match1 = (counter1 == compare1);
/*
* ICAP
*/
wire icap_ready;
wire icap_we;
sysctl_icap icap(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ready(icap_ready),
.we(icap_we),
.d(csr_di[15:0]),
.ce(csr_di[16]),
.write(csr_di[17])
);
/*
* Debug scrachpad register
*/
reg [7:0] debug_scratchpad;
/*
* Logic and CSR interface
*/
wire csr_selected = csr_a[13:10] == csr_addr;
assign icap_we = csr_selected & csr_we & (csr_a[4:0] == 5'b10000);
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
timer0_irq <= 1'b0;
timer1_irq <= 1'b0;
gpio_outputs <= {noutputs{1'b0}};
gpio_irqen <= {ninputs{1'b0}};
en0 <= 1'b0;
en1 <= 1'b0;
ar0 <= 1'b0;
ar1 <= 1'b0;
counter0 <= 32'd0;
counter1 <= 32'd0;
compare0 <= 32'hFFFFFFFF;
compare1 <= 32'hFFFFFFFF;
hard_reset <= 1'b0;
debug_scratchpad <= 8'd0;
debug_write_lock <= 1'b0;
bus_errors_en <= 1'b0;
end else begin
timer0_irq <= 1'b0;
timer1_irq <= 1'b0;
/* Handle timer 0 */
if( en0 & ~match0) counter0 <= counter0 + 32'd1;
if( en0 & match0) timer0_irq <= 1'b1;
if( ar0 & match0) counter0 <= 32'd1;
if(~ar0 & match0) en0 <= 1'b0;
/* Handle timer 1 */
if( en1 & ~match1) counter1 <= counter1 + 32'd1;
if( en1 & match1) timer1_irq <= 1'b1;
if( ar1 & match1) counter1 <= 32'd1;
if(~ar1 & match1) en1 <= 1'b0;
csr_do <= 32'd0;
if(csr_selected) begin
/* CSR Writes */
if(csr_we) begin
case(csr_a[4:0])
/* GPIO registers */
// 00000 is GPIO IN and is read-only
5'b00001: gpio_outputs <= csr_di[noutputs-1:0];
5'b00010: gpio_irqen <= csr_di[ninputs-1:0];
/* Timer 0 registers */
5'b00100: begin
en0 <= csr_di[0];
ar0 <= csr_di[1];
end
5'b00101: compare0 <= csr_di;
5'b00110: counter0 <= csr_di;
/* Timer 1 registers */
5'b01000: begin
en1 <= csr_di[0];
ar1 <= csr_di[1];
end
5'b01001: compare1 <= csr_di;
5'b01010: counter1 <= csr_di;
/* ICAP */
// 10000 is ICAP and is handled separately
/* Debug monitor (gdbstub) */
5'b10100: debug_scratchpad <= csr_di[7:0];
5'b10101: begin
if(csr_di[0])
debug_write_lock <= 1'b1;
bus_errors_en <= csr_di[1];
end
// 11101 is clk_freq and is read-only
// 11110 is capabilities and is read-only
5'b11111: hard_reset <= 1'b1;
endcase
end
/* CSR Reads */
case(csr_a[4:0])
/* GPIO registers */
5'b00000: csr_do <= gpio_in;
5'b00001: csr_do <= gpio_outputs;
5'b00010: csr_do <= gpio_irqen;
/* Timer 0 registers */
5'b00100: csr_do <= {ar0, en0};
5'b00101: csr_do <= compare0;
5'b00110: csr_do <= counter0;
/* Timer 1 registers */
5'b01000: csr_do <= {ar1, en1};
5'b01001: csr_do <= compare1;
5'b01010: csr_do <= counter1;
/* ICAP */
5'b10000: csr_do <= icap_ready;
/* Debug monitor (gdbstub) */
5'b10100: csr_do <= debug_scratchpad;
5'b10101: csr_do <= {bus_errors_en, debug_write_lock};
/* Read only SoC properties */
5'b11101: csr_do <= clk_freq;
5'b11110: csr_do <= capabilities;
5'b11111: csr_do <= systemid;
endcase
end
end
end
endmodule
|
/* ltcminer.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`ifdef NOLEDS
module ltcminer (osc_clk); // Version without LEDs for DE2-115
`else
module ltcminer (osc_clk, LEDS_out);
`endif
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25;
`endif
// LOCAL_MINERS determines the number of cores (the terminology is consistent with the LX150 port)
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 1;
`endif
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
`ifdef ADDRBITS
parameter ADDRBITS = `ADDRBITS; // Override for simulation
`else
parameter ADDRBITS = 12 - clog2(LOCAL_MINERS); // Automatically selects largest RAM that will fit into 4MBit
`endif
localparam SBITS = 8; // Shift data path width
input osc_clk;
`ifndef NOLEDS
output reg [7:0]LEDS_out; // Optional progress indicator
`endif
wire hash_clk;
`ifndef SIM
main_pll #(.SPEED_MHZ(SPEED_MHZ)) pll_blk (osc_clk, hash_clk);
`else
assign hash_clk = osc_clk;
`endif
// Virtual wire is now done here rather than in hashcore so as to support MULTICORE
`ifndef SIM
// 80 byte block header (NB this implimetation does not use midstate)
reg [255:0] data1 = 256'd0;
reg [255:0] data2 = 256'd0;
reg [127:0] data3 = 128'd0;
// final_hash=553a4b69b43913a61b42013ce210f713eaa7332e48cda1bdf3b93b10161d0876 (NOT a match)
`else
// Test data (MATCH nonce 0000318f)
reg [255:0] data1 = 256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg [255:0] data2 = 256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756;
reg [127:0] data3 = 128'h0000318f7e71441b141fe951b2b0c7df; // NB 0000318f is loaded into nonce
// final_hash=b303000066bd9f068aa115339cfd01cd94121ef65b2ff4d7d3796b738a174f7b (MATCH at target=000007ff/diff=32)
`endif
reg [31:0] target = 31'h000007ff; // Default to diff=32 for sane startup, this is overwritten by virtual_wire
wire [31:0]golden_nonce_out;
wire [31:0] nonce_out;
wire loadnonce = 1'b0; // Ought to strobe this when data changes, but this is not trivial as
// the virtual_wire channels do not seem to update deterministically
wire [LOCAL_MINERS*32-1:0] golden_nonce_i;
wire [LOCAL_MINERS-1:0] golden_nonce_match;
wire pbkdf_clk = hash_clk; // Use same clock for now
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
begin: miners
wire [31:0] nonce_out_i;
wire [3:0] nonce_core = i;
wire gn_match;
wire salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
wire [SBITS-1:0] salsa_din;
wire [SBITS-1:0] salsa_dout;
wire [3:0] dummy; // So we can ignore top 4 bits of slave_debug_sr
// Currently one pbkdfengine per salsaengine - TODO share the pbkdfengine for several salsaengines
pbkdfengine #(.SBITS(SBITS)) P
(.hash_clk(hash_clk), .pbkdf_clk(pbkdf_clk), .data1(data1), .data2(data2), .data3(data3), .target(target),
.nonce_msb({nonce_core}), .nonce_out(nonce_out_i), .golden_nonce_out(golden_nonce_i[(i+1)*32-1:i*32]),
.golden_nonce_match(golden_nonce_match[i]), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S
(.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout),
.shift(salsa_shift), .start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
if (i==0)
assign nonce_out = nonce_out_i; // NB mining script will under-report hash rate by factor of LOCAL_MINERS
// TODO correctabe by a simple shift here of log2(LOCAL-MINERS)
end // for
endgenerate
// Simple queue as virtual_wire just reports current value of golden_nonce
// What I want here is a parameterised, one-hot (priority) selected multiplexor, but since
// my verilog is not very good, I'll just reuse the hub_core code instead
reg [LOCAL_MINERS-1:0]new_nonces_flag = 0;
reg [clog2(LOCAL_MINERS)+1:0] port_counter = 0;
reg [LOCAL_MINERS*32-1:0] nonces_shifted = 0;
assign golden_nonce_out = nonces_shifted[31:0];
// Mark nonces to be cleared during next clock cycle
reg [LOCAL_MINERS-1:0] clear_nonces = 0;
always @(posedge pbkdf_clk)
begin
// Raise flags when new nonces appear; lower those that have been sent
new_nonces_flag <= (new_nonces_flag & ~clear_nonces) | golden_nonce_match;
if (port_counter == LOCAL_MINERS-1)
port_counter <= 0;
else
port_counter <= port_counter + 1'd1;
// kramble - the optimiser removes all but the low 32 bits of nonces_shifted since
// the following code implements a multiplexor on nonces input, NOT an actual shifter.
if (new_nonces_flag[port_counter])
begin
nonces_shifted <= golden_nonce_i >> port_counter*32;
clear_nonces[port_counter] <= 1;
end
else
begin
clear_nonces <= 0;
end
end
`ifndef SIM
//// Virtual Wire Control
wire [255:0] data1_vw;
wire [255:0] data2_vw;
wire [127:0] data3_vw; // 96 bits actually used, the extra 32 are the nonce, normally all zeros but for
// testing we can supply a nonce which will be loaded. Some pools set a non-zero nonce
// in getwork (which we will load), but this is of no consequence to live mining.
wire [31:0] target_vw; // This depends on the pool, variable diff pools will update the target dynamically
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT1")) data1_vw_blk(.probe(), .source(data1_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(128), .INSTANCE_ID("DAT3")) data3_vw_blk(.probe(), .source(data3_vw));
virtual_wire # (.PROBE_WIDTH(0), .WIDTH(32), .INSTANCE_ID("TARG")) target_vw_blk(.probe(), .source(target_vw));
always @ (posedge pbkdf_clk)
begin
data1 <= data1_vw;
data2 <= data2_vw;
data3 <= data3_vw;
target <= target_vw;
end
//// Virtual Wire Output
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce_out), .source());
virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("NONC")) nonce_vw_blk (.probe(nonce_out), .source());
`endif
`ifndef NOLEDS
// Optional LED progress indicator
always @(posedge pbkdf_clk) begin
`ifdef INVERTLEDS
LEDS_out <= ~nonce_out[15:8]; // Inverted for BeMicro
`else
LEDS_out <= nonce_out[15:8];
`endif
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 3; const long long linf = (long long)inf * inf + 2; int N, K; struct TrieNode { TrieNode *children[26]; bool canWin, canLose; TrieNode() { canWin = canLose = false; for (int i = 0; i < 26; ++i) children[i] = nullptr; } }; TrieNode *root; struct Trie { Trie() { root = new TrieNode(); } void insert(string &key, int idx = 0, TrieNode *pCrawl = root) { if (idx == (int)key.length()) return; int charId = key[idx] - a ; if (pCrawl->children[charId] == nullptr) pCrawl->children[charId] = new TrieNode(); insert(key, idx + 1, pCrawl->children[charId]); } void precompute(TrieNode *pCrawl = root) { bool hasChildren = false; for (int i = 0; i < 26; ++i) if (pCrawl->children[i] != nullptr) { hasChildren = true; precompute(pCrawl->children[i]); if (!pCrawl->children[i]->canWin) pCrawl->canWin = true; if (!pCrawl->children[i]->canLose) pCrawl->canLose = true; } if (!hasChildren) pCrawl->canLose = true; } }; int main() { ios_base::sync_with_stdio(false); cin >> N >> K; Trie myTrie = Trie(); string str; for (int i = 0; i < N; ++i) { cin >> str; myTrie.insert(str); } myTrie.precompute(); bool canForceWin = root->canWin, canForceLose = root->canLose; if (canForceWin && canForceLose) cout << First n ; else if (canForceWin) cout << (K % 2 ? First n : Second n ); else cout << Second n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND4B_PP_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_PP_BLACKBOX_V
|
// Example module that doesn't instantiate
module appendix1 (/*AUTOARG*/
// Outputs
z,
// Inputs
i
);
input i;
output z;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg z;
// End of automatics
/*AUTOWIRE*/
always @ (/*AUTOSENSE*/i) begin
z = i;
end
endmodule
// Example module that does instantiate
module appendix2 (/*AUTOARG*/
// Outputs
z,
// Inputs
i
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i; // To apx10 of appendix1.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [11:10] z; // From apx10 of appendix1.v, ...
// End of automatics
/*AUTOREG*/
/*AUTOWIRE*/
/*
appendix1 AUTO_TEMPLATE (
.z (z[@]),
);
*/
appendix1 apx10 (/*AUTOINST*/
// Outputs
.z (z[10]), // Templated
// Inputs
.i (i));
appendix1 apx11 (/*AUTOINST*/
// Outputs
.z (z[11]), // Templated
// Inputs
.i (i));
endmodule
|
// alu.v
//
// AVM alu in Verilog
//
// This is an implementation of AVM in C for experimenation purposes.
// It is both an AVM interpretr and an assembler for the instruction set.
//
// (C) 2016 David J. Goehrig
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE.
//
`include "avm.vh"
module alu (
input clock,
input [7:0] opcode,
input [`BITS-1:0] tos,
input [`BITS-1:0] nos,
output [`BITS-1:0] alu_tos,
output [`BITS-1:0] alu_nos);
reg [`BITS-1:0] _tos;
reg [`BITS-1:0] _nos;
reg [`BITS*2-1:0] _mul;
assign alu_tos = _tos;
assign alu_nos = _nos;
always @(posedge clock) begin
case(opcode)
// math
8'b0000_0100:
_tos <= - tos;
8'b0000_0101:
_tos <= nos + tos;
8'b0000_0110:
begin
_mul = nos * tos;
_tos <= _mul[`BITS-1:0];
_nos <= _mul[(`BITS*2)-1:`BITS];
end
8'b0000_0111:
begin
_tos <= nos / tos;
_nos <= nos % tos;
end
// logic
8'b0000_1000:
_tos <= ~ tos;
8'b0000_1001:
_tos <= nos & tos;
8'b0000_1010:
_tos <= nos | tos;
8'b0000_1011:
_tos <= nos ^ tos;
default:
_tos <= tos;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:05 12/03/2016
// Design Name:
// Module Name: animation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module animationV(clk, rst, height, ram_address, ram_data, mode, on_off);
input clk, rst, mode, on_off; //0 is home mode; 1 is party mode
input [8:0] ram_address;
output reg [47:0] ram_data;
reg [23:0] top, bottom;
input[3:0] height;
reg [4:0] inner_height;
reg [23:0] color;
//parameter height = 9;
initial begin
top<=0;
bottom<=0;
ram_data <=0;
inner_height<=0;
color<=0;
end
//Top half of panel is controlled by last 24 bits of ram_data
always @ (posedge clk) begin
if ( mode == 1'b1) begin
if (ram_address == 0) begin
color<= color+1'b1;
inner_height<={0,height};
end
bottom <= {24{1'b0}};
top <= {24{1'b0}};
if (ram_address > 512 - 1 - $unsigned(inner_height)* 32 ) begin
top <= color;
//bottom <= {24{1'b0}};
end
if (ram_address < $unsigned(inner_height) * 32) begin
//top <= {24{1'b0}};
bottom <= color;
end
ram_data <= {bottom, top};
end
else begin
if (on_off == 1'b1) begin
ram_data <= {8'd179, 8'd255, 8'd255, 8'd179, 8'd255, 8'd255};
end
else begin
ram_data <= 48'b0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, last[28], tmp[28]; long long ans[28]; char s[300005]; int main() { scanf( %s , s); for (i = 0; i <= 26; i++) last[i] = -1; int length = strlen(s); for (i = 0; i < length; i++) { last[s[i] - a ] = i; for (int j = 0; j <= 26; j++) tmp[j] = last[j]; sort(tmp, tmp + 27); for (int j = 26; j; j--) ans[26 - j + 1] += tmp[j] - tmp[j - 1]; } for (i = 1; i <= 26; i++) if (!ans[i]) break; printf( %d n , i - 1); for (int j = 1; j < i; j++) printf( %I64d n , ans[j]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_6_V
`define SKY130_FD_SC_LS__DECAPHE_6_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog wrapper for decaphe with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_6 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_6 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_6_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr72(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [71:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 72'hAAF0F0AA55F0F0AA55;
end
else if(ena) begin
word[71] <= word[0];
word[70:66] <= word[71:67];
word[65] <= word[66] ^ word[0];
word[64:25] <= word[65:26];
word[24] <= word[25] ^ word[0];
word[23:19] <= word[24:20];
word[18] <= word[19] ^ word[0];
word[17:0] <= word[18:1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_2_V
`define SKY130_FD_SC_HDLL__A2BB2OI_2_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_2_V
|
#include <bits/stdc++.h> using namespace std; int dist(int a, int b) { return min(abs(a - b), 360 - abs(a - b)); } long long d; int main() { scanf( %I64d , &d); d = (d % 360 + 360) % 360; int ans = 1000; for (int i = 0; i < 4; i++) ans = min(ans, dist(d, 90 * i)); for (int i = 0; i < 4; i++) { if (dist(d, 90 * i) == ans) { printf( %d n , i); return 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int A[2][2]; int main() { int d, i, n; cin >> n; int k = n; int cd = 0, ud = 0, c_i = 0, u_i = 0; while (k--) { cin >> i >> d; if (i == 0) c_i++; else u_i++; if (d == 0) cd++; else ud++; } cout << min(c_i, u_i) + min(cd, ud) << endl; return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_idelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:17 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the IDELAYCTRL primitive of the Virtex-5 device
// which continuously calibrates the IDELAY elements in the region in case of
// varying operating conditions. It takes a 200MHz clock as an input
//Reference:
//Revision History:
// Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed
// since tools will replicate idelactrl primitives.PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_idelay_ctrl #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter IODELAY_GRP = "IODELAY_MIG"
)
(
input clk200,
input rst200,
output idelay_ctrl_rdy
);
/*
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY(idelay_ctrl_rdy),
.REFCLK(clk200),
.RST(rst200)
);
*/
assign idelay_ctrl_rdy = 1'b1; //FIXME
endmodule
|
/*
* Copyright (c) 2014 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
class test_t;
reg [1:0] a;
reg [2:0] b;
function new (int ax, int bx);
begin
a = ax;
b = bx;
end
endfunction // new
endclass // test_t
module main;
class container_t;
test_t foo [0:3][0:7];
function new();
bit [3:0] idx1, idx2;
begin
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
foo[idx1][idx2] = new(idx1,idx2);
end
end
endfunction // new
task run();
bit [3:0] idx1, idx2;
test_t tmp;
foreach (foo[ia,ib]) begin
if (ia > 3 || ib > 7) begin
$display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
$finish;
end
tmp = foo[ia][ib];
if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
$display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
$finish;
end
foo[ia][ib] = null;
end
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
if (foo[idx1][idx2] != null) begin
$display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
$finish;
end
end
endtask // run
endclass
container_t dut;
initial begin
dut = new;
dut.run;
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; using namespace std; int M1(int x) { return x >= 1000000007 ? x - 1000000007 : x; } int M2(int x) { return x >= 1000000009 ? x - 1000000009 : x; } struct Hash { int a, b; Hash() { a = b = 0; } Hash(int a, int b) : a(a), b(b) {} Hash(int a) : a(a), b(a) {} bool operator<(const Hash& h) const { return a == h.a ? b < h.b : a < h.a; } bool operator!=(const Hash& h) const { return a != h.a || b != h.b; } bool operator==(const Hash& h) const { return a == h.a && b == h.b; } Hash operator+(const Hash& h) const { return Hash(M1(a + h.a), M2(b + h.b)); } Hash operator-(const Hash& h) const { return Hash(M1(a - h.a + 1000000007), M2(b - h.b + 1000000009)); } Hash operator*(const Hash& h) const { return Hash(((long long)a * h.a) % 1000000007, ((long long)b * h.b) % 1000000009); } Hash inv() const { return Hash(M1(1000000007 - a), M2(1000000009 - b)); } }; struct Hash_map { Hash v[11009989 + 1]; int val[11009989 + 1], head[11009989 + 1], nxt[11009989 + 1], ptr; void clear() { ptr = 0; } void insert(Hash a) { int x = (19260817ll * a.a + a.b) % 11009989; for (int y = head[x]; y; y = nxt[y]) if (v[y] == a) return; v[++ptr] = a, nxt[ptr] = head[x], head[x] = ptr; } int count(Hash a) { int x = (19260817ll * a.a + a.b) % 11009989; for (int y = head[x]; y; y = nxt[y]) if (v[y] == a) return true; return false; } int& operator[](Hash a) { int x = (19260817ll * a.a + a.b) % 11009989; for (int y = head[x]; y; y = nxt[y]) if (v[y] == a) return val[y]; v[++ptr] = a, nxt[ptr] = head[x], head[x] = ptr; return val[ptr]; } } st; Hash pw[100100], _pw[100100]; struct Data { int len, id; Hash h; }; int anses[100100], prec[100100], dep[100100], fa[21][100100], n, m; vector<pair<int, int> > G[100100]; vector<Data> Q[100100]; void dfs(int u, int f) { fa[0][u] = f; for (auto c : G[u]) if (c.first != f) { dep[c.first] = dep[u] + 1; pw[c.first] = pw[u] * Hash(19260817, 20010911) + Hash(c.second, c.second); prec[c.first] = c.second; dfs(c.first, u); } } Hash get(int l, int r) { return pw[l] - pw[r] * _pw[dep[l] - dep[r]]; } int lca(int u, int v) { if (dep[u] < dep[v]) swap(u, v); int d = dep[u] - dep[v]; for (int i = 0; d >> i; i++) if (d >> i & 1) u = fa[i][u]; if (u == v) return u; for (int i = 19; i >= 0; --i) if (fa[i][u] ^ fa[i][v]) u = fa[i][u], v = fa[i][v]; return fa[0][u]; } int jmp(int u, int d) { for (int i = 0; d >> i; i++) if (d >> i & 1) u = fa[i][u]; return u; } Hash geth(char* s) { Hash ret = 0; for (int i = 0; s[i]; i++) ret = ret * Hash(19260817, 20010911) + (s[i]); return ret; } int kmp(char* t, char* s) { static int f[100100]; int ns = strlen(s); for (int i = 0; i < ns; ++i) f[i] = 0; f[0] = -1; for (int i = 1; s[i]; i++) { int j = f[i - 1]; while (j != -1 && s[j + 1] != s[i]) j = f[j]; if (s[j + 1] == s[i]) j++; f[i] = j; } int ans = 0; for (int i = 0, x = -1; t[i]; i++) { while (x != -1 && s[x + 1] != t[i]) x = f[x]; if (s[x + 1] == t[i]) x++; if (x == ns - 1) ans++; } return ans; } void dfs2(int u, int f) { for (int i = 1, x = f; i <= 100 && x; i++) { st[get(u, x)]++; x = fa[0][x]; } for (auto c : Q[u]) { anses[abs(c.id)] += (c.id > 0 ? 1 : -1) * st[c.h]; } for (auto c : G[u]) if (c.first != f) dfs2(c.first, u); for (int i = 1, x = f; i <= 100 && x; i++) st[get(u, x)]--, x = fa[0][x]; } int main() { scanf( %d , &n); _pw[0] = Hash(1, 1); for (int i = 1; i <= n; ++i) _pw[i] = _pw[i - 1] * Hash(19260817, 20010911); for (int i = 2, u, v; i <= n; ++i) { char s[2]; scanf( %d%d%s , &u, &v, s); G[u].push_back(pair<int, int>(v, s[0])); G[v].push_back(pair<int, int>(u, s[0])); } dfs(1, 0); for (int i = 1; i < 20; ++i) for (int j = 1; j <= n; ++j) fa[i][j] = fa[i - 1][fa[i - 1][j]]; scanf( %d , &m); for (int i = 1, u, v; i <= m; ++i) { char s[200], t[300]; int tp = 0; scanf( %d%d%s , &u, &v, s); int lc = lca(u, v), len = strlen(s); int zu = jmp(u, max(0, dep[u] - dep[lc] - len)); int zv = jmp(v, max(0, dep[v] - dep[lc] - len)); Q[zv].push_back(Data{len, -i, geth(s)}); Q[v].push_back(Data{len, i, geth(s)}); reverse(s, s + len); Q[zu].push_back(Data{len, -i, geth(s)}); Q[u].push_back(Data{len, i, geth(s)}); reverse(s, s + len); while (zu != lc) t[tp++] = prec[zu], zu = fa[0][zu]; int xp = tp; while (zv != lc) t[tp++] = prec[zv], zv = fa[0][zv]; reverse(t + xp, t + tp); t[tp] = 0; anses[i] = kmp(t, s); } dfs2(1, 0); for (int i = 1; i <= m; ++i) printf( %d n , anses[i]); }
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module data_path(clk,
reset,
MIO_ready,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq,
ALU_operation,
PC_Current,
data2CPU,
Inst_R,
data_out,
M_addr,
zero,
overflow,
CauseWrite,
IntCause,
EPCWrite,
Co0Write,
);
input clk,reset;
input MIO_ready,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq,CauseWrite,EPCWrite,Co0Write;
input [1:0] RegDst,ALUSrcB,IntCause;
input [2:0]ALU_operation,MemtoReg,PCSource;
input [31:0] data2CPU;
output [31:0] Inst_R,M_addr,data_out,PC_Current; //
output zero,overflow;
reg [31:0] Inst_R,ALU_Out,MDR,PC_Current,w_reg_data;
wire [1:0] RegDst,ALUSrcB,IntCause;
wire [31:0] reg_outA,reg_outB,r6out, epc_out; //regs
wire reset,rst,zero,overflow,IRWrite,MIO_ready,RegWrite,Beq,modificative,CauseWrite,EPCWrite,Co0Write;
//ALU
wire IorD,ALUSrcA,PCWrite,PCWriteCond;
wire [31:0] Alu_A,Alu_B,res;
wire [31:0] rdata_A, rdata_B, data_out, data2CPU,M_addr, rdata_co0;
wire [2:0] ALU_operation, MemtoReg, PCSource;
wire [15:0] imm;
wire [4:0] reg_Rs_addr_A,reg_Rt_addr_B,reg_rd_addr,reg_Wt_addr;
assign rst=reset;
// locked inst form memory
always @(posedge clk or posedge rst)begin
if(rst) begin
Inst_R<=0; end
else begin
if (IRWrite && MIO_ready) Inst_R<=data2CPU; else Inst_R<=Inst_R;
if (MIO_ready) MDR<=data2CPU;
ALU_Out<=res;
end
end
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
alu x_ALU(
.A(Alu_A),
.B(Alu_B),
.ALU_operation(ALU_operation),
.res(res),
.zero(zero),
.overflow(overflow) );
Regs reg_files( .clk(clk),
.rst(rst),
.reg_R_addr_A(reg_Rs_addr_A),
.reg_R_addr_B(reg_Rt_addr_B),
.reg_W_addr(reg_Wt_addr),
.wdata(w_reg_data),
.reg_we(RegWrite),
.rdata_A(rdata_A),
.rdata_B(rdata_B));
Coprocessor coprocessor0 (
.clk(clk),
.rst(rst),
.reg_R_addr(reg_Rt_addr_B),
.reg_W_addr(reg_W_addr),
.wdata(w_reg_data),
.pc_i(res),
.reg_we(Co0Write),
.EPCWrite(EPCWrite),
.CauseWrite(CauseWrite),
.IntCause(IntCause),
.rdata(rdata_co0),
.epc_o(epc_out)
);
//path with MUX++++++++++++++++++++++++++++++++++++++++++++++++++++++
// reg path
assign reg_Rs_addr_A=Inst_R[25:21]; //REG Source 1 rs
assign reg_Rt_addr_B=Inst_R[20:16]; //REG Source 2 or Destination rt
assign reg_rd_addr=Inst_R[15:11]; //REG Destination rd
assign imm=Inst_R[15:0]; //Immediate
// reg write data
always @(*)
case(MemtoReg)
3'b000: w_reg_data<=ALU_Out;
3'b001: w_reg_data<=MDR;
3'b010: w_reg_data<={imm,16'h0000};
3'b011: w_reg_data<=PC_Current;
3'b100: w_reg_data<=rdata_co0;
endcase
// reg write port addr
mux4to1_5 mux_w_reg_addr (
.a(reg_Rt_addr_B), //reg addr=IR[21:16]
.b(reg_rd_addr), //reg addr=IR[15:11], LW or lui
.c(5'b11111), //reg addr=$Ra(31) jr
.d(5'b00000), // not use
.sel(RegDst),
.o(reg_Wt_addr)
);
//---------------ALU path
mux2to1_32 mux_Alu_A (
.a(rdata_A), // reg out A
.b(PC_Current), // PC
.sel(ALUSrcA),
.o(Alu_A)
);
mux4to1_32 mux_Alu_B(
.a(rdata_B), //reg out B
.b(32'h00000004), //4 for PC+4
.c({{16{imm[15]}},imm}), //imm
.d({{14{imm[15]}},imm,2'b00}),// offset
.sel(ALUSrcB),
.o(Alu_B)
);
//pc Generator
//+++++++++++++++++++++++++++++++++++++++++++++++++
assign modificative=PCWrite||(PCWriteCond&&(~(zero||Beq)|(zero&&Beq)));
//(PCWriteCond&&zero)
always @(posedge clk or posedge reset)
begin
if (reset==1) // reset
PC_Current<=32'h30000000;
else if (modificative==1)begin
case(PCSource)
3'b000: if (MIO_ready) PC_Current <=res; // PC+4
3'b001: PC_Current <=ALU_Out; // branch
3'b010: PC_Current <={PC_Current[31:28],Inst_R[25:0],2'b00}; // jump
3'b011: PC_Current <=32'h30000180; // j$r
3'b100: PC_Current <=epc_out;
endcase
end
end
/* mux4to1_32 mux_pc_next(
.a(pc_4),
.b(branch_pc),
.c(jump_pc),
.d(jump_pc),
.sel({jump,zero&Beq}),
.o(pc_next)
);
*/
//---------------memory path
assign data_out=rdata_B; //data to store memory or IO
mux2to1_32 mux_M_addr (
.a(ALU_Out), //access memory
.b(PC_Current), //IF
.sel(IorD),
.o(M_addr)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 1e9; const long long N = 1000 + 5; long long ar[N], done[N], cnt[N]; long long n; long long mex() { for (long long i = 0; i < n; i++) cnt[i] = 0; for (long long i = 0; i < n; i++) cnt[ar[i]] = 1; long long mex = 0; while (cnt[mex]) mex++; return mex; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; cin >> t; while (t--) { cin >> n; for (long long i = 0; i < n; i++) { cin >> ar[i]; } vector<long long> ans; while (1) { long long m = mex(); if (m < n) { ar[m] = m; ans.push_back(m + 1); } else { long long ind = 0; while (ind < n && ar[ind] == ind) ind++; if (ind == n) break; long long p = -1; for (long long i = 0; i < n && p == -1; i++) if (ar[i] == ind) p = i; ar[p] = n; ans.push_back(p + 1); } } cout << ans.size() << n ; for (auto &inx : ans) cout << inx << ; cout << n ; } }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sin_taylor_seriesdEe
#(parameter
ID = 7,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
sin_taylor_series_ap_dadd_3_full_dsp_64 sin_taylor_series_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isPrime(int n) { for (int i = 2; (i * i) <= n; i++) { if (n % i == 0) return 0; } return 1; } int nerPr(int n) { for (int i = n;; i++) { if (isPrime(i)) return i; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a; int mn = (int)1e9; for (int i = 0; i < n; i++) { int d; cin >> d; a.push_back(d); mn = min(mn, d); if (d == 1) { cout << -1 n ; exit(0); } } cout << 1; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> moebius(int n) { map<int, int> res; vector<int> primes; for (int i = 2; i * i <= n; i++) { if (n % i == 0) { primes.push_back(i); while (n % i == 0) n /= i; } } if (n != 1) primes.push_back(n); int m = primes.size(); for (int i = 0; i < (1 << m); i++) { int mu = 1; int d = 1; for (int j = 0; j < m; j++) { if (i >> j & 1) { mu *= -1; d *= primes[j]; } } res[d] = mu; } return res; } int digCnt(long long n) { int cnt = 0; while (n) { cnt++; n /= 2; } return cnt; } int isPrime(int a) { if (a <= 1) return false; for (int i = 2; i * i <= a; i++) if (a % i == 0) return false; return true; } const int mu[] = {0, 1, -1, -1, 0, -1, 1, -1, 0, 0, 1, -1, 0, -1, 1, 1, 0, -1, 0, -1, 0, 1, 1, -1, 0, 0, 1, 0, 0, -1, -1, -1, 0, 1, 1, 1, 0, -1, 1, 1, 0, -1, -1, -1, 0, 0, 1, -1, 0, 0, 0, 1, 0, -1, 0, 1, 0, 1, 1, -1, 0, -1, 1, 0, 0, 1, -1, -1, 0, 1, -1, -1, 0, -1, 1, 0, 0, 1}; long long getNum(long long n) { long long res = 0; if (n <= 0) return res; int digs = digCnt(n); vector<int> v; long long tmp = n; while (tmp) { v.push_back(tmp % 2); tmp /= 2; } reverse(v.begin(), v.end()); for (int i = 2; i < digs; i++) { map<int, int> m = moebius(i); for (int k = 1; k < i; k++) if (i % k == 0) { res -= (1LL << (k - 1)) * (long long)m[i / k]; } } map<int, int> m = moebius(digs); for (int k = 1; k < digs; k++) { if (digs % k == 0) { long long cand = 0; for (int i = 0; i < k; i++) { if (i != 0 && v[i]) { cand += (1LL << (k - i - 1)); } } long long num = 0; for (int i = 0; i < k; i++) { if (v[i]) { for (int j = i; j < digs; j += k) num |= (1LL << (digs - 1 - j)); } } if (num <= n) cand++; res -= m[digs / k] * cand; } } return res; } int main() { long long l, r; while (cin >> l >> r) { cout << getNum(r) - getNum(l - 1) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void p(double t) { cout << fixed << setprecision(13) << t << endl; exit(0); } struct tank { int hp, time, lo, hi, prob; void scan() { cin >> hp >> time >> lo >> hi >> prob; prob = 100 - prob; } }; int moven; vector<int> moves; tank tanks[2]; double dp[201][201][70]; double curdp[70]; int main() { for (int i = 0; i < 2; i++) { tanks[i].scan(); } if (tanks[0].prob == 0) { p(0); } if (tanks[1].prob == 0) { p(1); } for (int movet = 0; movet < tanks[0].time * tanks[1].time; movet++) { for (int i = 0; i < 2; i++) { if (movet % tanks[i].time == 0) { moves.push_back(i); moven++; } } } dp[tanks[0].hp][tanks[1].hp][0] = 1.; for (int i = tanks[0].hp; i > 0; i--) { for (int j = tanks[1].hp; j > 0; j--) { memset(curdp, 0, sizeof(curdp)); double cursum = 0; double ratio = 1; for (int k = 0; k < moven; k++) { int cur = moves[k]; cursum += dp[i][j][k]; dp[i][j][k] = 0; curdp[k] += cursum; cursum *= ((100 - tanks[cur].prob) * 0.01); ratio *= ((100 - tanks[cur].prob) * 0.01); } for (int k = 0; k < moven; k++) { int cur = moves[k]; curdp[k] += cursum / (1 - ratio); cursum *= ((100 - tanks[cur].prob) * 0.01); } for (int k = 0; k < moven; k++) { int nk = (k + 1) % moven; int cur = moves[k]; double p = curdp[k] * (tanks[cur].prob * 0.01 / (tanks[cur].hi - tanks[cur].lo + 1)); if (cur == 0) { for (int amt = tanks[cur].lo; amt <= tanks[cur].hi; amt++) { dp[i][max(0, j - amt)][nk] += p; } } else { for (int amt = tanks[cur].lo; amt <= tanks[cur].hi; amt++) { dp[max(0, i - amt)][j][nk] += p; } } } } } double ans = 0; for (int i = 1; i <= tanks[0].hp; i++) { for (int k = 0; k < moven; k++) { ans += dp[i][0][k]; } } p(ans); }
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:32 EST 2014
//
//
// Ports:
// Name I/O size props
// c_request_get O 153
// RDY_c_request_get O 1
// RDY_c_response_put O 1
// RDY_s0_request_put O 1
// s0_response_get O 153
// RDY_s0_response_get O 1
// RDY_s1_request_put O 1
// s1_response_get O 153
// RDY_s1_response_get O 1
// pfk I 14
// CLK I 1 clock
// RST_N I 1 reset
// c_response_put I 153
// s0_request_put I 153
// s1_request_put I 153
// EN_c_response_put I 1
// EN_s0_request_put I 1
// EN_s1_request_put I 1
// EN_c_request_get I 1
// EN_s0_response_get I 1
// EN_s1_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLPCM(pfk,
CLK,
RST_N,
EN_c_request_get,
c_request_get,
RDY_c_request_get,
c_response_put,
EN_c_response_put,
RDY_c_response_put,
s0_request_put,
EN_s0_request_put,
RDY_s0_request_put,
EN_s0_response_get,
s0_response_get,
RDY_s0_response_get,
s1_request_put,
EN_s1_request_put,
RDY_s1_request_put,
EN_s1_response_get,
s1_response_get,
RDY_s1_response_get);
input [13 : 0] pfk;
input CLK;
input RST_N;
// actionvalue method c_request_get
input EN_c_request_get;
output [152 : 0] c_request_get;
output RDY_c_request_get;
// action method c_response_put
input [152 : 0] c_response_put;
input EN_c_response_put;
output RDY_c_response_put;
// action method s0_request_put
input [152 : 0] s0_request_put;
input EN_s0_request_put;
output RDY_s0_request_put;
// actionvalue method s0_response_get
input EN_s0_response_get;
output [152 : 0] s0_response_get;
output RDY_s0_response_get;
// action method s1_request_put
input [152 : 0] s1_request_put;
input EN_s1_request_put;
output RDY_s1_request_put;
// actionvalue method s1_response_get
input EN_s1_response_get;
output [152 : 0] s1_response_get;
output RDY_s1_response_get;
// signals for module outputs
wire [152 : 0] c_request_get, s0_response_get, s1_response_get;
wire RDY_c_request_get,
RDY_c_response_put,
RDY_s0_request_put,
RDY_s0_response_get,
RDY_s1_request_put,
RDY_s1_response_get;
// ports of submodule pktFork
wire [152 : 0] pktFork_iport_put, pktFork_oport0_get, pktFork_oport1_get;
wire pktFork_EN_iport_put,
pktFork_EN_oport0_get,
pktFork_EN_oport1_get,
pktFork_RDY_iport_put,
pktFork_RDY_oport0_get,
pktFork_RDY_oport1_get;
// ports of submodule pktMerge
wire [152 : 0] pktMerge_iport0_put, pktMerge_iport1_put, pktMerge_oport_get;
wire pktMerge_EN_iport0_put,
pktMerge_EN_iport1_put,
pktMerge_EN_oport_get,
pktMerge_RDY_iport0_put,
pktMerge_RDY_iport1_put,
pktMerge_RDY_oport_get;
// remaining internal signals
reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1;
wire [13 : 0] x__h110;
// actionvalue method c_request_get
assign c_request_get = pktMerge_oport_get ;
assign RDY_c_request_get = pktMerge_RDY_oport_get ;
// action method c_response_put
assign RDY_c_response_put = pktFork_RDY_iport_put ;
// action method s0_request_put
assign RDY_s0_request_put = pktMerge_RDY_iport0_put ;
// actionvalue method s0_response_get
assign s0_response_get = pktFork_oport0_get ;
assign RDY_s0_response_get = pktFork_RDY_oport0_get ;
// action method s1_request_put
assign RDY_s1_request_put = pktMerge_RDY_iport1_put ;
// actionvalue method s1_response_get
assign s1_response_get = pktFork_oport1_get ;
assign RDY_s1_response_get = pktFork_RDY_oport1_get ;
// submodule pktFork
mkPktFork pktFork(.pfk(x__h110),
.CLK(CLK),
.RST_N(RST_N),
.iport_put(pktFork_iport_put),
.EN_iport_put(pktFork_EN_iport_put),
.EN_oport0_get(pktFork_EN_oport0_get),
.EN_oport1_get(pktFork_EN_oport1_get),
.RDY_iport_put(pktFork_RDY_iport_put),
.oport0_get(pktFork_oport0_get),
.RDY_oport0_get(pktFork_RDY_oport0_get),
.oport1_get(pktFork_oport1_get),
.RDY_oport1_get(pktFork_RDY_oport1_get));
// submodule pktMerge
mkPktMerge pktMerge(.CLK(CLK),
.RST_N(RST_N),
.iport0_put(pktMerge_iport0_put),
.iport1_put(pktMerge_iport1_put),
.EN_iport0_put(pktMerge_EN_iport0_put),
.EN_iport1_put(pktMerge_EN_iport1_put),
.EN_oport_get(pktMerge_EN_oport_get),
.RDY_iport0_put(pktMerge_RDY_iport0_put),
.RDY_iport1_put(pktMerge_RDY_iport1_put),
.oport_get(pktMerge_oport_get),
.RDY_oport_get(pktMerge_RDY_oport_get));
// submodule pktFork
assign pktFork_iport_put = c_response_put ;
assign pktFork_EN_iport_put = EN_c_response_put ;
assign pktFork_EN_oport0_get = EN_s0_response_get ;
assign pktFork_EN_oport1_get = EN_s1_response_get ;
// submodule pktMerge
assign pktMerge_iport0_put = s0_request_put ;
assign pktMerge_iport1_put = s1_request_put ;
assign pktMerge_EN_iport0_put = EN_s0_request_put ;
assign pktMerge_EN_iport1_put = EN_s1_request_put ;
assign pktMerge_EN_oport_get = EN_c_request_get ;
// remaining internal signals
assign x__h110 =
{ CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1,
pfk[11:0] } ;
always@(pfk)
begin
case (pfk[13:12])
2'd0, 2'd1, 2'd2:
CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12];
2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3;
endcase
end
endmodule // mkTLPCM
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_hdll__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hdll__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double net, res; int d, h, vel, e; cin >> d >> h >> vel >> e; net = e - (vel / (3.14159265358979323846 * d * d / 4.0)); res = -h / net; if (res <= 0 || res > 10000) cout << NO n ; else cout << YES n << fixed << setprecision(12) << res << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_cols_V_channel4_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_cols_V_channel4 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_cols_V_channel4_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_cols_V_channel4_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_SYMBOL_V
`define SKY130_FD_SC_LS__A2111OI_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_SYMBOL_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module dcache
#(parameter AWIDTH=14,
parameter CWIDTH=6)
(input wb_clk_i,
input wb_rst_i,
input [AWIDTH-1:0] dwb_adr_i,
input dwb_stb_i,
input dwb_we_i,
input [3:0] dwb_sel_i,
input [31:0] dwb_dat_i,
output [31:0] dwb_dat_o,
output dwb_ack_o,
input [31:0] dram_dat_i,
output [31:0] dram_dat_o,
output [AWIDTH-1:0] dram_adr_o,
output dram_we_o,
output dram_en_o,
output [3:0] dram_sel_o );
localparam TAGWIDTH = AWIDTH-CWIDTH-2;
reg stb_d1, ack_d1, miss_d1;
reg [AWIDTH-1:0] held_addr;
reg [31:0] ddata [0:(1<<CWIDTH)-1];
reg [TAGWIDTH-1:0] dtags [0:(1<<CWIDTH)-1];
reg dvalid [0:(1<<CWIDTH)-1];
wire [CWIDTH-1:0] rd_line, wr_line;
wire [TAGWIDTH-1:0] wr_tags;
wire cache_write, invalidate;
wire [31:0] wr_data;
// /////////////////////////////////////
// Write into cache
integer i;
always @(posedge wb_clk_i)
if(wb_rst_i)
for(i=0;i<(1<<CWIDTH);i=i+1)
dvalid[i] <= 0;
else
if(invalidate)
dvalid[wr_line] <= 1'b0;
else if(cache_write)
dvalid[wr_line] <= 1'b1;
always @(posedge wb_clk_i)
if(cache_write)
begin
ddata[wr_line] <= wr_data;
dtags[wr_line] <= wr_tags;
end
// //////////////////////////////////////
// Read from Cache
wire [TAGWIDTH-1:0] tag_out = dtags[rd_line];
wire valid_out = dvalid[rd_line];
wire [31:0] data_out = ddata[rd_line];
wire cache_hit = valid_out & (tag_out == dwb_adr_i[AWIDTH-1:CWIDTH+2]);
wire cache_miss = ~cache_hit;
// //////////////////////////////////////
// Handle 1-cycle delay of Block-RAM
always @(posedge wb_clk_i)
if(wb_rst_i)
stb_d1 <= 0;
else
stb_d1 <= dwb_stb_i;
always @(posedge wb_clk_i)
if(wb_rst_i)
held_addr <= 0;
else
held_addr <= dwb_adr_i;
always @(posedge wb_clk_i)
if(wb_rst_i)
ack_d1 <= 1'b0;
else
ack_d1 <= dwb_ack_o;
always @(posedge wb_clk_i)
if(wb_rst_i)
miss_d1 <= 0;
else
miss_d1 <= cache_miss;
`define DC_NOCACHE
//`define DC_BASIC
//`define DC_FORWARDING_DP
//`define DC_FORWARDING_SP
//`define DC_PREFETCH
`ifdef DC_NOCACHE
assign dwb_dat_o = dram_dat_i;
assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
assign dram_adr_o = dwb_adr_i;
assign dram_en_o = dwb_stb_i;
assign dram_dat_o = dwb_dat_i;
assign dram_we_o = dwb_we_i;
assign dram_sel_o = dwb_sel_i;
assign rd_line = 0;
assign wr_line = 0;
assign wr_tags = 0;
assign wr_data = 0;
assign cache_write = 0;
assign invalidate = 0;
`endif
`ifdef DC_BASIC // Very basic, no forwarding, 2 wait states on miss
assign dwb_dat_o = data_out;
assign dwb_ack_o = dwb_stb_i & cache_hit;
assign dram_adr_o = dwb_adr_i;
assign dram_en_o = dwb_stb_i;
assign dram_dat_o = dwb_dat_i;
assign dram_we_o = dwb_we_i;
assign dram_sel_o = dwb_sel_i;
assign rd_line = dwb_adr_i[CWIDTH+1:2];
assign wr_line = rd_line;
assign wr_tags = dwb_adr_i[AWIDTH-1:CWIDTH+2];
assign wr_data = dwb_we_i ? dwb_dat_i : dram_dat_i;
assign cache_write = dwb_stb_i & (dwb_we_i | (stb_d1 & miss_d1));
assign invalidate = dwb_we_i & ~(&dwb_sel_i);
`endif
`ifdef DC_FORWARDING_DP // Simple forwarding, 1 wait state on miss, dual-port ram
assign dwb_dat_o = cache_hit ? data_out : dram_dat_i;
assign dwb_ack_o = dwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
assign dram_adr_o = dwb_adr_i;
assign dram_en_o = 1'b1;
assign dram_dat_o = dwb_dat_i;
assign dram_we_o = dwb_we_i;
assign dram_sel_o = dwb_sel_i;
assign rd_line = dwb_adr_i[CWIDTH+1:2];
assign wr_line = held_addr[CWIDTH+1:2];
assign wr_tags = held_addr[AWIDTH-1:CWIDTH+2];
assign wr_data = dram_dat_i;
assign cache_write = dwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
assign invalidate = 0;
`endif
`ifdef DC_FORWARDING_SP // Simple forwarding, 1 wait state on miss, single-port ram
assign dwb_dat_o = cache_hit ? data_out : dram_dat_i;
assign dwb_ack_o = dwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
assign dram_adr_o = dwb_adr_i;
assign dram_en_o = 1'b1;
assign dram_dat_o = dwb_dat_i;
assign dram_we_o = dwb_we_i;
assign dram_sel_o = dwb_sel_i;
assign rd_line = dwb_adr_i[CWIDTH+1:2];
assign wr_line = rd_line;
assign wr_tags = dwb_adr_i[AWIDTH-1:CWIDTH+2];
assign wr_data = dram_dat_i;
assign cache_write = dwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
assign invalidate = 0;
`endif
`ifdef DC_PREFETCH // Forwarding plus prefetch
`endif
endmodule // dcache
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:35:15 04/02/2016
// Design Name:
// Module Name: ALU_32bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_32bit
(
// Input
input [31:0] a_in,
input [31:0] b_in,
input [3:0] op,
// Output
output wire [31:0] result,
output wire zero,
output wire overflow
);
// Internal_variables
reg [31:0] mux_out;
wire [31:1] c_in; // c_out of alu[i-1] to c_in of alu[i]
wire less0; // set to less of alu[0]
wire gnd;
wire [31:0] alu_out;
// Assign
assign gnd = 1'b0; // Ground
assign zero = !( |result ); // beq operation
assign result = mux_out;
// Submodule
ALU_1bit alu00
(
.a_in ( a_in[0] ),
.b_in ( b_in[0] ),
.carry_in ( op[2] ),
.b_invert ( op[2] ),
.less ( less0 ),
.op ( op[1:0] ),
.result ( alu_out[0] ),
.carry_out ( c_in[1] )
); // LSB
ALU_1bit alu[30:1]
(
.a_in ( a_in[30:1] ),
.b_in ( b_in[30:1] ),
.carry_in ( c_in[30:1] ),
.b_invert ( op[2] ),
.less ( gnd ),
.op ( op[1:0] ),
.result ( alu_out[30:1] ),
.carry_out ( c_in[31:2] )
);
ALU_1bit_overflow alu31
(
.a_in ( a_in[31] ),
.b_in ( b_in[31] ),
.carry_in ( c_in[31] ),
.b_invert ( op[2] ),
.less ( gnd ),
.op ( op[1:0] ),
.result ( alu_out[31] ),
.carry_out ( ),
.set ( less0 ),
.overflow ( overflow )
); // MSB
always @( * )
if ( op == 4 ) // NOT OP = 4
mux_out[31:0] = ~ a_in[31:0];
else
mux_out[31:0] = alu_out[31:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; template <class t> using V = vector<t>; constexpr ll INF = 1e16; int n, m; ll dp[1502][1502]; int tab[1502][1502]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) for (int k = 1; k <= m; ++k) scanf( %d , &tab[i][k]); for (int i = 1; i <= n; ++i) for (int k = 1; k <= m; ++k) tab[i][k] += tab[i][k - 1]; for (int i = 1; i <= n + 1; ++i) for (int k = 0; k <= m + 1; ++k) dp[i][k] = -INF; for (int i = 1; i <= n; ++i) { if (i & 1) { for (int k = 1; k <= m; ++k) dp[i - 1][k] = max(dp[i - 1][k - 1], dp[i - 1][k]); for (int k = 2; k <= m; ++k) dp[i][k] = dp[i - 1][k - 1] + tab[i][k]; } else { for (int k = m; k >= 1; --k) dp[i - 1][k] = max(dp[i - 1][k], dp[i - 1][k + 1]); for (int k = 1; k <= m - 1; ++k) dp[i][k] = dp[i - 1][k + 1] + tab[i][k]; } } ll res = -INF; for (int i = 1; i <= m; ++i) res = max(res, dp[n][i]); printf( %lld n , res); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests signal initializers.
module vhdl_init_testbench;
vhdl_init dut();
initial begin
// Simply check if the assigned values are correct
if (dut.a !== 'b11101001) begin
$display("FAILED #1: expected 11101001, got %b", dut.a);
$finish;
end
if (dut.b !== 'b1010) begin
$display("FAILED #2: expected 1010, got %b", dut.b);
$finish;
end
if (dut.c !== 'b1000) begin
$display("FAILED #3: expected 1000, got %b", dut.c);
$finish;
end
$display("PASSED");
end
endmodule
|
(** Extraction : tests of optimizations of pattern matching *)
Require Coq.extraction.Extraction.
(** First, a few basic tests *)
Definition test1 b :=
match b with
| true => true
| false => false
end.
Extraction test1. (** should be seen as the identity *)
Definition test2 b :=
match b with
| true => false
| false => false
end.
Extraction test2. (** should be seen a the always-false constant function *)
Inductive hole (A:Set) : Set := Hole | Hole2.
Definition wrong_id (A B : Set) (x:hole A) : hole B :=
match x with
| Hole _ => @Hole _
| Hole2 _ => @Hole2 _
end.
Extraction wrong_id. (** should _not_ be optimized as an identity *)
Definition test3 (A:Type)(o : option A) :=
match o with
| Some x => Some x
| None => None
end.
Extraction test3. (** Even with type parameters, should be seen as identity *)
Inductive indu : Type := A : nat -> indu | B | C.
Definition test4 n :=
match n with
| A m => A (S m)
| B => B
| C => C
end.
Extraction test4. (** should merge branchs B C into a x->x *)
Definition test5 n :=
match n with
| A m => A (S m)
| B => B
| C => B
end.
Extraction test5. (** should merge branches B C into _->B *)
Inductive indu' : Type := A' : nat -> indu' | B' | C' | D' | E' | F'.
Definition test6 n :=
match n with
| A' m => A' (S m)
| B' => C'
| C' => C'
| D' => C'
| E' => B'
| F' => B'
end.
Extraction test6. (** should merge some branches into a _->C' *)
(** NB : In Coq, "| a => a" corresponds to n, hence some "| _ -> n" are
extracted *)
Definition test7 n :=
match n with
| A m => Some m
| B => None
| C => None
end.
Extraction test7. (** should merge branches B,C into a _->None *)
(** Script from bug #2413 *)
Set Implicit Arguments.
Section S.
Definition message := nat.
Definition word := nat.
Definition mode := nat.
Definition opcode := nat.
Variable condition : word -> option opcode.
Section decoder_result.
Variable inst : Type.
#[universes(template)] Inductive decoder_result : Type :=
| DecUndefined : decoder_result
| DecUnpredictable : decoder_result
| DecInst : inst -> decoder_result
| DecError : message -> decoder_result.
End decoder_result.
Definition decode_cond_mode (mode : Type) (f : word -> decoder_result mode)
(w : word) (inst : Type) (g : mode -> opcode -> inst) :
decoder_result inst :=
match condition w with
| Some oc =>
match f w with
| DecInst i => DecInst (g i oc)
| DecError _ m => @DecError inst m
| DecUndefined _ => @DecUndefined inst
| DecUnpredictable _ => @DecUnpredictable inst
end
| None => @DecUndefined inst
end.
End S.
Extraction decode_cond_mode.
(** inner match should not be factorized with a partial x->x (different type) *)
|
#include <bits/stdc++.h> using namespace std; int gcf(int A, int B) { if (A < B) return gcf(B, A); else if (B == 0) return A; else return gcf(B, A % B); } int main() { int n, m; cin >> m >> n; bool A[m], B[n]; memset(A, 0, sizeof(A)); memset(B, 0, sizeof(B)); int x, y; cin >> x; for (int i = 0; i < x; i++) { int temp; cin >> temp; A[temp] = 1; } cin >> y; for (int i = 0; i < y; i++) { int temp; cin >> temp; B[temp] = 1; } for (int i = 0; i < 5000000; i++) { if (A[i % m] || B[i % n]) A[i % m] = B[i % n] = 1; } for (int i = 0; i < m; i++) { if (!A[i]) { cout << No ; return 0; } } for (int i = 0; i < n; i++) { if (!B[i]) { cout << No ; return 0; } } cout << Yes ; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define pf printf #define PF(a) printf( %d n ,(a)) #define PF2(a,b) printf( %d %d n ,(a), (b)) #define PF3(a,b,c) printf( %d %d %d n ,(a), (b), (c)) #define PFL(a) printf( %lld n ,(a)) #define PFL2(a,b) printf( %lld %lld n ,(a), (b)) #define PFL3(a,b,c) printf( %lld %lld %lld n ,(a), (b), (c)) #define get(a) cin>>a #define sf scanf #define SF(a) scanf( %d ,&a) #define SF2(a,b) scanf( %d %d ,&a, &b) #define SF3(a,b,c) scanf( %d %d %d ,&a, &b, &c) #define SFL(a) scanf( %lld ,&a) #define SFL2(a,b) scanf( %lld %lld ,&a, &b) #define SFL3(a,b,c) scanf( %lld %lld %lld ,&a, &b, &c) #define gl(a) getline(cin,(a)) #define gc() getchar() #define pb push_back #define m_p make_pair #define pc() printf( Case %d: ,tt++) #define tc() cout<< Case <<tt++<< : #define dbg(x) cout << #x << -> << x << endl; #define SZ(a) (int)(a).size() #define all(a) a.begin(),a.end() #define FF first #define SS second #define MAX 2134567891 #define MOD 1000000007 #define MM 200005 #define PI 2*acos(0.0) #define cond(n,m) (xx>=0 && xx<(n) && yy>=0 && yy<(m)) #define mem(a) memset((a),0,sizeof (a)) #define SET(a) memset((a),-1,sizeof (a)) #define output freopen( output.txt , w ,stdout); #define input freopen( input.txt , r ,stdin); #define I_O ios_base::sync_with_stdio(0); cin.tie(0);cout.tie(0) #define rep(a) for(int i=0;i<(a);i++) #define FOR(a,b) for(int i=(a);i<(b);i++) #define REP(a) for(int j=0;j<(a);j++) #define rev(a) for(int i=(a);i>=0;i--) #define fr(i,n) for(i=0;i<n;i++) #define fr1(i,n,m) for(i=n;i<m;i++) mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; int dx8[] = {0, 0, 1, 1, 1, -1, -1, -1}; int dy8[] = {1, -1, -1, 0, 1, -1, 0, 1}; int kx8[] = {1, 1, 2, 2, -1, -1, -2, -2}; int ky8[] = {2, -2, 1, -1, 2, -2, 1, -1}; typedef long long ll; typedef unsigned long long llu; typedef priority_queue < int > PQ; typedef pair < ll , ll > pi; typedef pair < ll, pi > pii; typedef vector < int > vi; typedef vector < ll > vl; typedef vector < string > vs; /* //FUNCTION// ll bigmod(ll a, ll b, ll c) { if(b==0)return 1%c;ll x=bigmod(a,b/2,c);x=(x*x)%c; if(b%2==1)x=(x*a)%c;return x; } ll mod_inverse(ll a, ll mod){return bigmod(a,mod-2,mod);} ll poww(ll a, ll b) { if(b==0)return 1;ll x=poww(a,b/2);x=x*x;if(b%2==1)x=(x*a);return x; } ll LCM(ll a, ll b){ return a*b/ __gcd(a,b);} int pr = 100005; vi primelist; bool a[MM]; void seive( ) { int i,j,k=sqrt(pr); a[1]=1; primelist.pb(2); for(i=4;i<=pr;i+=2)a[i]=1; for(i=3;i<=k;i+=2)if(!a[i])for(j=i*i;j<=pr;j+=2*i)a[j]=1; for(i=3;i<=pr;i+=2)if(!a[i])primelist.pb(i); } int phi[MM]; void calculatePhi() { for (int i = 1; i < MM; i++) { phi[i] = i; } for (int p = 2; p < M; p++) { if (phi[p] == p) { // p is a prime for (int k = p; k < M; k += p) { phi[k] -= phi[k] / p; } } } } ll fact_divs( ll n, ll p) { ll cnt=0;while(p<=n){cnt += n/p;n /= p;}return cnt; } struct point{double x, y;}; double area( point A, point B, point C){ return 0.5*(A.x*(B.y-C.y) - A.y*(B.x-C.x) + B.x*C.y - C.x*B.y); } int Set(int N,int pos){return N=N | (1<<pos);} int reset(int N,int pos){return N= N & ~(1<<pos);} bool check(int N,int pos){return (bool)(N & (1<<pos));} //*/ int a[MM]; int main(){ I_O; int t, tt = 1; cin>>t; while(t--){ int n; cin>>n; int id = 0, mn = MAX; for(int i=1; i<=n; i++){ cin>>a[i]; if(a[i] < mn){ mn = a[i]; id = i; } } cout<<n-1<<endl; for(int i=id+1, cnt=1; i<=n; i++, cnt++){ cout<<id<< <<i<< <<a[id]<< <<a[id]+cnt<<endl; } for(int i=id-1, cnt=1; i >=1; i--, cnt++){ cout<<id<< <<i<< <<a[id]<< <<a[id]+cnt<<endl; } } return 0; } /* 2 5 9 6 3 11 15 3 7 5 13 */
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } int kolvo = 0; int kolvo1 = 0; for (int i = 0; i < n; i++) { if (a[i] == 5) { kolvo++; } if (a[i] == 0) { kolvo1++; } } sort(a.rbegin(), a.rend()); if ((kolvo / 9) > 0 and kolvo1 > 0) { for (int i = 0; i < (kolvo / 9) * 9; i++) { cout << a[i]; } sort(a.begin(), a.end()); for (int i = 0; i < kolvo1; i++) { cout << a[i]; } } else { if (kolvo1 > 0) { cout << 0; } else { cout << -1; } } return 0; }
|
module instr_mem ( input [31:0] address,
output [31:0] instruction );
reg [31:0] memory [249:0];
integer i;
initial
begin
for (i=0; i<250; i=i+1) memory[i] = 32'b0;
// Insert MIPS's assembly here start at memory[10] = ...
//memory[10] = 32'b001000_00000_01000_0000000000000010; //addi $t0, $0, 2
//memory[11] = 32'b101011_01000_01001_0000000000000000; //110100 sw
//memory[12] = 32'b100011_01000_01100_0000000000000000; // 111000 lw
memory[10] = 32'b001000_00000_01000_0000000000000010; //addi $t0, $0, 2
memory[11] = 32'b001000_00000_01001_0000000000000010; //addi $t1, $0, 2
memory[12] = 32'b001000_00000_01011_0000000000000010; //addi $t1, $0, 2
memory[13] = 32'b000011_00000000000000000000001000;
/*memory[13] = 32'b000100_01000_01001_0000000000000010; //branch
memory[14] = 32'b001000_00000_01010_0000000000000010; //addi $t2, $0, 2
memory[15] = 32'b001000_00000_01100_0000000000000001; //addi $t3, $0, 1
memory[16] = 32'b001000_00000_01101_0000000000000011; //addi $t4, $0, 3
memory[17] = 32'b001000_00000_01000_0000000000000010; //addi $t0, $0, 2
memory[18] = 32'b101011_01100_01000_0000011111010000; //sw $t4(rs),$t0(rt)
memory[19] = 32'b100011_01000_01100_0000011111010000; //lw $t0(rs) ,$t4(rt)*/
end
assign instruction = memory[address >> 2];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005, MAXT = 500, INF = 0x3f3f3f3f; int mx[MAXT], add[MAXT], sz[MAXT], num[MAXT][MAXT], A[MAXN]; int N, T = 314; void upd(int p) { if (add[p]) { for (int i = 0; i < sz[p]; ++i) num[p][i] += add[p]; add[p] = 0; } } void ins(int x, int k) { int p = x / T; x = x % T; for (int i = 0; i < p; ++i) add[i] += k, mx[i] += k; upd(p); for (int i = 0; i <= x; ++i) num[p][i] += k; mx[p] = -INF; for (int i = 0; i < sz[p]; ++i) mx[p] = max(mx[p], num[p][i]); } int query() { int p = (N - 1) / T; while (p >= 0 && mx[p] <= 0) p--; if (p < 0) return -1; upd(p); int x = sz[p] - 1; while (num[p][x] <= 0) x--; return A[p * T + x]; } int main() { scanf( %d , &N); int p = (N - 1) / T; for (int i = 0; i < p; ++i) sz[i] = T; sz[p] = (N - 1) % T + 1; for (int i = 0; i < N; ++i) { int a, b, c; scanf( %d%d , &a, &b); if (b) { scanf( %d , &c); A[a - 1] = c; ins(a - 1, 1); printf( %d n , query()); } else { ins(a - 1, -1); printf( %d n , query()); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class t> inline t read(t &x) { x = 0; char c = getchar(); bool f = 0; while (!isdigit(c)) f |= c == - , c = getchar(); while (isdigit(c)) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); if (f) x = -x; return x; } template <class t> inline void write(t x) { if (x < 0) { putchar( - ), write(-x); } else { if (x > 9) write(x / 10); putchar( 0 + x % 10); } } const int N = 1e5 + 5, M = 1e4 + 5, NM = N * 4 + M, TR = NM << 2; int n, m, pt[NM], pn; double p[TR], ans; struct tree { int x, h, l, r; } a[N]; struct mushroom { int x, v; } b[M]; void build(int x, int l, int r) { p[x] = 1; if (l == r) return; int mid = l + r >> 1; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); } void up(int x, int l, int r, int L, int R, double v) { if (L <= l && r <= R) { p[x] *= v; return; } int mid = l + r >> 1; if (L <= mid) up(x << 1, l, mid, L, R, v); if (R > mid) up(x << 1 | 1, mid + 1, r, L, R, v); } double que(int x, int l, int r, int pos) { if (l == r) return p[x]; int mid = l + r >> 1; if (pos <= mid) return p[x] * que(x << 1, l, mid, pos); return p[x] * que(x << 1 | 1, mid + 1, r, pos); } signed main() { read(n); read(m); for (int i = 1; i <= n; i++) { read(a[i].x); read(a[i].h); read(a[i].l); read(a[i].r); pt[++pn] = a[i].x - a[i].h; pt[++pn] = a[i].x - 1; pt[++pn] = a[i].x + 1; pt[++pn] = a[i].x + a[i].h; } for (int i = 1; i <= m; i++) { read(b[i].x); read(b[i].v); pt[++pn] = b[i].x; } sort(pt + 1, pt + 1 + pn); pn = unique(pt + 1, pt + 1 + pn) - pt - 1; build(1, 1, pn); for (int i = 1; i <= n; i++) { up(1, 1, pn, lower_bound(pt + 1, pt + 1 + pn, a[i].x - a[i].h) - pt, lower_bound(pt + 1, pt + 1 + pn, a[i].x - 1) - pt, 1.0 - 0.01 * a[i].l); up(1, 1, pn, lower_bound(pt + 1, pt + 1 + pn, a[i].x + 1) - pt, lower_bound(pt + 1, pt + 1 + pn, a[i].x + a[i].h) - pt, 1.0 - 0.01 * a[i].r); } for (int i = 1; i <= m; i++) ans += que(1, 1, pn, lower_bound(pt + 1, pt + 1 + pn, b[i].x) - pt) * b[i].v; printf( %.10lf , ans); }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int n, m; int volume[N]; int amount[N]; int parent[N]; int tofill[N]; int weight[N]; std::set<int> notFull; void reducePath(int index, int lead) { while (parent[index] != index) { int oldParent = parent[index]; parent[index] = lead; index = oldParent; } } int find(int index) { int lead = index; while (parent[lead] != lead) { lead = parent[lead]; } reducePath(index, lead); return lead; } bool merge(int l, int r) { int ll = find(l); int rl = find(r); if (ll == rl) { return false; } if (weight[ll] < weight[rl]) swap(ll, rl); parent[rl] = ll; weight[ll] += weight[rl]; if (tofill[ll] < tofill[rl]) tofill[ll] = tofill[rl]; return true; } void fill(int p, int x) { while (x > 0) { int lead = find(p); int f = tofill[lead]; int remainingVolume = volume[f] - amount[f]; int fillAmount = std::min(remainingVolume, x); amount[f] += fillAmount; x -= fillAmount; if (amount[f] == volume[f]) { if (f == n - 1) break; else ++f; merge(lead, f); } } } void fill2(int p, int x) { auto lb = notFull.lower_bound(p); while (x > 0 && lb != notFull.end()) { int remainingVolume = volume[*lb] - amount[*lb]; int fillAmount = std::min(remainingVolume, x); amount[*lb] += fillAmount; x -= fillAmount; if (amount[*lb] == volume[*lb]) lb = notFull.erase(lb); else lb++; } } void init() { for (int i = 0; i < n; ++i) { parent[i] = i; tofill[i] = i; weight[i] = 1; notFull.insert(i); } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 0; i < n; ++i) { cin >> volume[i]; } init(); cin >> m; for (int i = 0; i < m; ++i) { int q; cin >> q; if (q == 1) { int p, x; cin >> p >> x; fill2(--p, x); } else { int k; cin >> k; cout << amount[--k] << n ; } } return 0; }
|
`timescale 1ns/1ps
// This module is applicable to a X1 or X4 PCIe design.
// For independent channel design ( 2 X1 or multi protocol), instantiate 1 for
// each channel
module rx_reset_sm
(
input refclkdiv2,
input rst_n,
input [3:0] invValid,
input [3:0] rx_cdr_lol_ch_s,
input [3:0] rx_los_low_ch_s,
input tx_pll_lol_qd_s, //IF TX QUAD IS UNUSED, TIE THIS INPUT TO 0
output reg [3:0] rx_pcs_rst_ch_c, //RX Lane Reset
output reg pcie_ip_rst, //RX Lane Reset
output reg rx_serdes_rst_ch_c // QUAD Reset
);
parameter count_index = 18;
// States of LSM
localparam WAIT_FOR_PLOL = 0,
RX_SERDES_RESET = 1,
WAIT_FOR_TIMER1 = 2,
CHECK_LOL_LOS = 3,
WAIT_FOR_TIMER2 = 4,
NORMAL = 5;
localparam STATEWIDTH =3;
// Flop variables
reg [STATEWIDTH-1:0] cs /*synthesis syn_encoding="safe, sequential"*/;
// Combinational logic variables
reg [STATEWIDTH-1:0] ns; // next state of lsm
wire [3:0] emu_ElecIdle = rx_los_low_ch_s & invValid;
reg [3:0] emu_EIdl_m1;
reg [3:0] emu_EIdl_m2;
reg [3:0] emu_EIdl_m3;
reg [3:0] emu_EIedge;
always @(posedge refclkdiv2 or negedge rst_n) begin
if (rst_n == 1'b0) begin
emu_EIdl_m1 <= 4'hf;
emu_EIdl_m2 <= 4'hf;
emu_EIdl_m3 <= 4'hf;
end else begin
emu_EIdl_m1 <= emu_ElecIdle;
emu_EIdl_m2 <= emu_EIdl_m1;
emu_EIdl_m3 <= emu_EIdl_m2;
emu_EIedge <= ~emu_EIdl_m2 & emu_EIdl_m3;
end
end
reg tx_pll_lol_qd_m1;
reg tx_pll_lol_qd_s_int;
reg rx_lol_los_int;
reg [3:0] rx_pcs_rst_ch_c_int; // RX Lane Reset
reg rx_serdes_rst_ch_c_int; // QUAD Reset
reg rx_los_low_m1;
reg rx_los_low_int;
reg [3:0] rx_lol_m1;
reg [3:0] rx_lol_m2;
reg [3:0] rx_lol_del;
reg rx_lol_afe; // Any LOL falling edge cause a reset
always @(posedge refclkdiv2 or negedge rst_n) begin
if (rst_n == 1'b0) begin
rx_lol_m1 <= 4'hf;
rx_lol_m2 <= 4'hf;
rx_lol_del <= 4'hf;
rx_lol_afe <= 1'b0;
end else begin
rx_lol_m1 <= rx_cdr_lol_ch_s;
rx_lol_m2 <= rx_lol_m1;
rx_lol_del <= rx_lol_m2;
rx_lol_afe <= (~rx_lol_m2[3] & rx_lol_del[3]) |
(~rx_lol_m2[2] & rx_lol_del[2]) |
(~rx_lol_m2[1] & rx_lol_del[1]) |
(~rx_lol_m2[0] & rx_lol_del[0]) ;
end
end
//SEQUENTIAL
always @(posedge refclkdiv2 or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
cs <= WAIT_FOR_PLOL;
tx_pll_lol_qd_m1 <= 1;
tx_pll_lol_qd_s_int <= 1;
rx_pcs_rst_ch_c <= 4'hF;
rx_serdes_rst_ch_c <= 0;
rx_los_low_int <= 1;
end
else
begin
cs <= ns;
tx_pll_lol_qd_m1 <= tx_pll_lol_qd_s;
tx_pll_lol_qd_s_int <= tx_pll_lol_qd_m1;
rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
// rx_los_low_m1 <= | rx_los_low_ch_s;
// If there are signals on any channel then start reset state machine
// This takes care of X4, X1 Down grade or X1 Native
rx_los_low_m1 <= &emu_ElecIdle;
rx_los_low_int <= rx_los_low_m1;
end
end
reg reset_timer1, reset_timer2;
//TIMER1 = 3ns;
//Fastest REFLCK =312 MHZ, or 3 ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
// A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
localparam TIMER1WIDTH=2;
reg [TIMER1WIDTH-1:0] counter1;
reg TIMER1;
always @(posedge refclkdiv2 or posedge reset_timer1)
begin
if (reset_timer1)
begin
counter1 <= 0;
TIMER1 <= 0;
end
else
begin
if (counter1[1] == 1)
TIMER1 <=1;
else
begin
TIMER1 <=0;
counter1 <= counter1 + 1 ;
end
end
end
//TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
// An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
localparam TIMER2WIDTH=19;
reg [TIMER2WIDTH-1:0] counter2;
reg TIMER2;
always @(posedge refclkdiv2 or posedge reset_timer2)
begin
if (reset_timer2)
begin
counter2 <= 0;
TIMER2 <= 0;
end
else
begin
// `ifdef SIM //IF SIM parameter is set, define lower value
// //TO SAVE SIMULATION TIME
// if (counter2[4] == 1)
// `else
// if (counter2[18] == 1)
// `endif
if (counter2[count_index] == 1)
TIMER2 <=1;
else
begin
TIMER2 <=0;
counter2 <= counter2 + 1 ;
end
end
end
always @(*)
//always @(cs or tx_pll_lol_qd_s_int or TIMER1 or rx_lol_los_int or rx_lol_los_del or TIMER2)
begin : NEXT_STATE
reset_timer1 = 1;
reset_timer2 = 1;
case (cs)
WAIT_FOR_PLOL: begin
rx_pcs_rst_ch_c_int = 4'hF;
rx_serdes_rst_ch_c_int = 0;
pcie_ip_rst = 1;
if (tx_pll_lol_qd_s_int || rx_los_low_int) //Also make sure A Signal
ns = WAIT_FOR_PLOL; // is Present prior to moving to the next
else
ns = RX_SERDES_RESET;
end
RX_SERDES_RESET: begin
rx_pcs_rst_ch_c_int = 4'hF;
rx_serdes_rst_ch_c_int = 1;
pcie_ip_rst = 1;
ns = WAIT_FOR_TIMER1;
end
WAIT_FOR_TIMER1: begin
rx_pcs_rst_ch_c_int = 4'hF;
rx_serdes_rst_ch_c_int = 1;
pcie_ip_rst = 1;
reset_timer1 = 0;
if (TIMER1)
ns = CHECK_LOL_LOS;
else
ns = WAIT_FOR_TIMER1;
end
CHECK_LOL_LOS: begin
rx_pcs_rst_ch_c_int = 4'hF;
rx_serdes_rst_ch_c_int = 0;
pcie_ip_rst = 1;
ns = WAIT_FOR_TIMER2;
end
WAIT_FOR_TIMER2: begin
rx_pcs_rst_ch_c_int = emu_EIedge;
rx_serdes_rst_ch_c_int = 0;
reset_timer2 = 0;
pcie_ip_rst = 1;
if (TIMER2) begin
if (tx_pll_lol_qd_s_int || rx_lol_afe)
ns = WAIT_FOR_PLOL;
else
ns = NORMAL;
end else
ns = WAIT_FOR_TIMER2;
end
NORMAL: begin
rx_pcs_rst_ch_c_int = emu_EIedge;
rx_serdes_rst_ch_c_int = 0;
pcie_ip_rst = 0;
if (tx_pll_lol_qd_s_int || rx_lol_afe) begin
ns = WAIT_FOR_PLOL;
`ifdef SIM
$display ("rx_lol_los_int=1: %t",$time);
`endif
end else begin
ns = NORMAL;
`ifdef SIM
$display ("rx_lol_los_int=0: %t",$time);
`endif
end
end
// prevent lockup in undefined state
default: begin
rx_pcs_rst_ch_c_int = 4'hF;
rx_serdes_rst_ch_c_int = 0;
pcie_ip_rst = 1;
ns = WAIT_FOR_PLOL;
end
endcase // case
end //NEXT_STATE
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,sse4.1,sse4.2,popcnt,abm,mmx,avx,tune=native ) using namespace std; const int MOD = 1000000007; const int UNDEF = -1; const int INF = 1 << 30; template <typename T> inline bool chkmax(T &aa, T bb) { return aa < bb ? aa = bb, true : false; } template <typename T> inline bool chkmin(T &aa, T bb) { return aa > bb ? aa = bb, true : false; } int rint() { int x; scanf( %d , &x); return x; } long long rlong() { long long x; scanf( %lld , &x); return x; } const int mn = (5e5) + 4; long long c[mn]; map<long long, vector<pair<int, int> > > sig2e; map<int, vector<int> > h; set<int> seen; int cnt = 0; void dfs(int x) { seen.insert(x); for (auto &y : h[x]) { if (seen.find(y) == seen.end()) { --cnt; dfs(y); } } } int ptwo[mn]; int main() { int n = rint(), m = rint(), k = rint(); ptwo[0] = 1; for (int i = 1; i < mn; i++) { ptwo[i] = ptwo[i - 1] * 2; if (ptwo[i] >= MOD) ptwo[i] -= MOD; } for (int x = 1; x <= n; x++) c[x] = rlong(); for (int i = 0; i < m; i++) { int x = rint(), y = rint(); long long sig = c[x] ^ c[y]; sig2e[sig].push_back(make_pair(x, y)); } int rem = (ptwo[k] - (int)sig2e.size() + MOD) % MOD; int ans = (rem * (long long)ptwo[n]) % MOD; for (auto &sigve : sig2e) { auto &ve = sigve.second; h.clear(); seen.clear(); for (auto &e : ve) { int x = e.first, y = e.second; h[x].push_back(y); h[y].push_back(x); } cnt = n; for (auto &e : ve) { int x = e.first, y = e.second; if (seen.find(x) == seen.end()) dfs(x); if (seen.find(y) == seen.end()) dfs(y); } ans += ptwo[cnt]; if (ans >= MOD) ans -= MOD; } printf( %d n , ans); }
|
`timescale 1ns / 1ps
`include "constants.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Mahdi Enan
//
// Create Date: 15:37:20 01/22/2017
// Design Name:
// Module Name: Permute
// Project Name: spongent
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Permute(state_in, IV_in, INV_IV_in, state_out, IV_out, INV_IV_out, clk, rst, en, rdy);
input [263:0] state_in; // input of 33 iterations
input [ 15:0] IV_in;
input [ 15:0] INV_IV_in;
input rst;
input clk;
input en;
output reg[263:0] state_out; // output of 33 iterations
output reg[ 15:0] IV_out;
output reg[ 15:0] INV_IV_out;
output reg rdy;
reg [ 15:0] i;
reg [ 263:0] tmp_state;
reg [2048:0] sBoxLayer;
reg wr_en;
wire [ 15:0] lCounter_out, retnuoCl_out;
lCounter lCounter_instance(.lfsr(IV_in), .out(lCounter_out));
retnuoCl retnuoCl_instance(.lfsr(IV_in), .out(retnuoCl_out));
reg pLayer_enable;
reg [ 263:0] pLayer_state_in;
wire [ 263:0] pLayer_state_out;
wire pLayer_out_rdy;
pLayer pLayer_instance (.clk(clk),
.rst(rst),
.state_in(pLayer_state_in),
.state_out(pLayer_state_out),
.out_rdy(pLayer_out_rdy),
.en(pLayer_enable)
);
initial begin
`INIT_SBOX_LAYER;
end
integer j;
always @ (posedge clk or posedge rst) begin
if (rst) begin
state_out = 0;
tmp_state = 0;
pLayer_state_in = 0;
pLayer_enable = 0;
wr_en = 1;
rdy = 0;
end else if (en) begin
IV_out = 0;
INV_IV_out = 0;
state_out = 0;
tmp_state = state_in;
tmp_state[ 7:0] = tmp_state[ 7:0] ^ (IV_in & 16'hff);
tmp_state[15:8] = tmp_state[15:8] ^ ((IV_in >> 8) & 16'hff);
INV_IV_out = retnuoCl_out;
tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] = tmp_state[(`nSBox*8)-1:(`nSBox*8)-1-7] ^ (INV_IV_out >> 8) & 8'hff;
tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] = tmp_state[(`nSBox*8)-8:(`nSBox*8)-1-15] ^ INV_IV_out & 8'hff;
IV_out = lCounter_out;
for (j=0; j<`nSBox*8; j=j+8) begin
tmp_state[j+:8] = sBoxLayer[(tmp_state[j+:8]*8)+:8];
end
if (wr_en) begin
wr_en = 0;
pLayer_state_in = tmp_state;
pLayer_enable = 1;
end
if (pLayer_out_rdy) begin
state_out = pLayer_state_out;
rdy = 1;
end else begin
rdy = 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long add(long long a, long long b) { a += b; if (a >= 1000000007) a -= 1000000007; return a; } long long mul(long long a, long long b) { return ((a % 1000000007) * (b % 1000000007)) % 1000000007; } long long binary_expo(long long base, long long expo) { long long res = 1; while (expo) { if (expo % 2) { res = mul(res, base); expo /= 2; } base = mul(base, base); } return res; } vector<pair<long long, pair<long long, long long> > > v[1000002]; const long long N = 100002; long long Arr[N], dep[N]; multiset<long long> S1[N], S2[N]; long long n; long long BIT1[N], BIT2[N]; void update(long long BIT[], long long idx, long long val) { while (idx <= n) { BIT[idx] += val; idx += (idx & (-idx)); } } long long query(long long BIT[], long long idx) { long long sum = 0; while (idx > 0) { sum += BIT[idx]; idx -= (idx & (-idx)); } return sum; } void solve() { long long m, k; cin >> n >> m >> k; for (long long i = 1; i <= n; i++) { Arr[i] = 1e12; dep[i] = -1e12; } for (long long i = 0; i < m; i++) { long long d, f, t, c; cin >> d >> f >> t >> c; v[d].push_back({f, {t, c}}); if (t == 0) { Arr[f] = min(Arr[f], d); } else { dep[t] = max(dep[t], d); } } long long minn = 1e12; long long maxx = -1e12; for (long long i = 1; i <= n; i++) { if (Arr[i] == 1e12 or dep[i] == -1e12) { cout << -1 << endl; return; } maxx = max(maxx, Arr[i]); minn = min(minn, dep[i]); } long long ms = maxx + 1; long long me = minn - 1; if (me - ms + 1 < k) { cout << -1 << endl; return; } for (long long i = 1000000; i > (ms + k - 1); i--) { for (long long j = 0; j < v[i].size(); j++) { pair<long long, pair<long long, long long> > p = v[i][j]; if (p.first == 0) { long long val1 = 0; if (S1[p.second.first].size() != 0) { val1 = *(S1[p.second.first].begin()); } S1[p.second.first].insert(p.second.second); long long val = *(S1[p.second.first].begin()); update(BIT2, p.second.first, val - val1); } } } for (long long i = 1; i < ms; i++) { for (long long j = 0; j < v[i].size(); j++) { pair<long long, pair<long long, long long> > p = v[i][j]; if (p.second.first == 0) { long long val1 = 0; if (S2[p.first].size() != 0) { val1 = *(S2[p.first].begin()); } S2[p.first].insert(p.second.second); long long val = *(S2[p.first].begin()); update(BIT1, p.first, val - val1); } } } long long ans = query(BIT1, n) + query(BIT2, n); for (long long i = ms + k; i <= me; i++) { long long ar = i - k; long long de = i; for (long long j = 0; j < v[i].size(); j++) { pair<long long, pair<long long, long long> > p = v[i][j]; if (p.first == 0) { long long val1 = 0; if (S1[p.second.first].size() != 0) { val1 = *(S1[p.second.first].begin()); } S1[p.second.first].erase(S1[p.second.first].find(p.second.second)); long long val = *(S1[p.second.first].begin()); update(BIT2, p.second.first, val - val1); } } for (long long j = 0; j < v[ar].size(); j++) { pair<long long, pair<long long, long long> > p = v[ar][j]; if (p.second.first == 0) { long long val1 = 0; if (S2[p.first].size() != 0) { val1 = *(S2[p.first].begin()); } S2[p.first].insert(p.second.second); long long val = *(S2[p.first].begin()); update(BIT1, p.first, val - val1); } } ans = min(ans, query(BIT1, n) + query(BIT2, n)); } cout << ans << endl; } signed main() { long long t; ios_base::sync_with_stdio(false); t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); if (n == 2) { printf( -1 n ); return 0; } printf( 6 n10 n15 n ); for (int i = 4; i <= n; i++) { printf( 6 ); for (int zero = 1; zero <= i - 4 + 1; zero++) printf( 0 ); printf( n ); } return 0; }
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Compute
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
- (* i = 0 -- contradictory *)
intros c st st' H. inversion H.
- (* i = S i' *)
intros c st st' H.
destruct c;
simpl in H; inversion H; subst; clear H.
+ (* SKIP *) apply E_Skip.
+ (* ::= *) apply E_Ass. reflexivity.
+ (* ;; *)
destruct (ceval_step st c1 i') eqn:Heqr1.
* (* Evaluation of r1 terminates normally *)
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
* (* Otherwise -- contradiction *)
inversion H1.
+ (* IFB *)
destruct (beval st b) eqn:Heqr.
* (* r = true *)
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
* (* r = false *)
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
+ (* WHILE *) destruct (beval st b) eqn :Heqr.
* (* r = true *)
destruct (ceval_step st c i') eqn:Heqr1.
{ (* r1 = Some s *)
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption. }
{ (* r1 = None *) inversion H1. }
* (* r = false *)
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
- (* i1 = 0 *)
simpl in Hceval. inversion Hceval.
- (* i1 = S i1' *)
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
destruct c.
+ (* SKIP *)
simpl in Hceval. inversion Hceval.
reflexivity.
+ (* ::= *)
simpl in Hceval. inversion Hceval.
reflexivity.
+ (* ;; *)
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
* (* st1'o = Some *)
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
* (* st1'o = None *)
inversion Hceval.
+ (* IFB *)
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
+ (* WHILE *)
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
* (* st1'o = Some *)
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
* (* i1'o = None *)
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
induction Hce.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
(** $Date$ *)
|
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