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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_1r1w_rf16x160.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_1r1w_rf16x160
// Description: 1r1w regfile
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_1r1w_rf16x160 (/*AUTOARG*/
// Outputs
so_w, so_r, dout,
// Inputs
wr_en, wr_clk, wr_adr, word_wen, si_w, si_r, sehold, se,
rst_tri_en, reset_l, read_en, rd_clk, rd_adr, din, byte_wen,
testmux_sel
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [19:0] byte_wen; // To bw_r_rf16x160 of bw_r_rf16x160.v
input [159:0] din; // To bw_r_rf16x160 of bw_r_rf16x160.v
input [3:0] rd_adr; // To bw_r_rf16x160 of bw_r_rf16x160.v
input rd_clk; // To bw_r_rf16x160 of bw_r_rf16x160.v
input read_en; // To bw_r_rf16x160 of bw_r_rf16x160.v
input reset_l; // To bw_r_rf16x160 of bw_r_rf16x160.v
input rst_tri_en; // To bw_r_rf16x160 of bw_r_rf16x160.v
input se; // To bw_r_rf16x160 of bw_r_rf16x160.v
input sehold; // To bw_r_rf16x160 of bw_r_rf16x160.v
input si_r; // To bw_r_rf16x160 of bw_r_rf16x160.v
input si_w; // To bw_r_rf16x160 of bw_r_rf16x160.v
input [3:0] word_wen; // To bw_r_rf16x160 of bw_r_rf16x160.v
input [3:0] wr_adr; // To bw_r_rf16x160 of bw_r_rf16x160.v
input wr_clk; // To bw_r_rf16x160 of bw_r_rf16x160.v
input wr_en; // To bw_r_rf16x160 of bw_r_rf16x160.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output so_r; // From bw_r_rf16x160 of bw_r_rf16x160.v
output so_w; // From bw_r_rf16x160 of bw_r_rf16x160.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
input testmux_sel;
output [159:0] dout;
wire [159:0] dout_array;
wire [159:0] dout_scan;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
bw_r_rf16x160 bw_r_rf16x160 (.dout (dout_array[159:0]),
/*AUTOINST*/
// Outputs
.so_w (so_w),
.so_r (so_r),
// Inputs
.din (din[159:0]),
.rd_adr (rd_adr[3:0]),
.wr_adr (wr_adr[3:0]),
.read_en(read_en),
.wr_en (wr_en),
.rst_tri_en(rst_tri_en),
.word_wen(word_wen[3:0]),
.byte_wen(byte_wen[19:0]),
.rd_clk (rd_clk),
.wr_clk (wr_clk),
.se (se),
.si_r (si_r),
.si_w (si_w),
.reset_l(reset_l),
.sehold (sehold));
// testmux for DFT
assign dout = testmux_sel ? dout_scan : dout_array;
dff_ns #(160) dout_scan_ff (.din(dout_array),
.clk(rd_clk),
.q(dout_scan));
endmodule // iobdg_1r1w_rf16x160
// Local Variables:
// verilog-library-directories:("." "../../../srams/rtl")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, n, m; cin >> a >> b >> n >> m; if (max((3 * a) / 10, a - (a / 250) * n) > max((3 * b) / 10, b - (b / 250) * m)) cout << Misha ; if (max((3 * a) / 10, a - (a / 250) * n) < max((3 * b) / 10, b - (b / 250) * m)) cout << Vasya ; if (max((3 * a) / 10, a - (a / 250) * n) == max((3 * b) / 10, b - (b / 250) * m)) cout << Tie ; }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Tawas Arithmetic Unit:
//
// Perform arithmetic on registers.
//
module tawas_au
(
input clk,
input rst,
input [31:0] reg0,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] reg3,
input [31:0] reg4,
input [31:0] reg5,
input [31:0] reg6,
input [31:0] reg7,
input [4:0] thread_decode,
output [31:0] thread_mask,
input rf_imm_en,
input [2:0] rf_imm_reg,
input [31:0] rf_imm,
input au_op_en,
input [14:0] au_op,
output wb_au_en,
output [2:0] wb_au_reg,
output [31:0] wb_au_data,
output wb_au_flags_en,
output [7:0] wb_au_flags
);
parameter RTL_VERSION = 32'hFFFFFFFF;
//
// AU input registers
//
reg [32:0] reg_a;
reg [32:0] reg_b;
always @ (posedge clk)
if (rf_imm_en)
begin
reg_a <= {rf_imm[31], rf_imm};
reg_b <= 33'd0;
end
else if (au_op_en)
begin
case (au_op[2:0])
3'd0: reg_a <= {1'b0, reg0};
3'd1: reg_a <= {1'b0, reg1};
3'd2: reg_a <= {1'b0, reg2};
3'd3: reg_a <= {1'b0, reg3};
3'd4: reg_a <= {1'b0, reg4};
3'd5: reg_a <= {1'b0, reg5};
3'd6: reg_a <= {1'b0, reg6};
default: reg_a <= {1'b0, reg7};
endcase
case (au_op[5:3])
3'd0: reg_b <= {1'b0, reg0};
3'd1: reg_b <= {1'b0, reg1};
3'd2: reg_b <= {1'b0, reg2};
3'd3: reg_b <= {1'b0, reg3};
3'd4: reg_b <= {1'b0, reg4};
3'd5: reg_b <= {1'b0, reg5};
3'd6: reg_b <= {1'b0, reg6};
default: reg_b <= {1'b0, reg7};
endcase
end
//
// Pipeline commands
//
reg rf_imm_en_d1;
reg [2:0] rf_imm_reg_d1;
reg [14:0] au_op_d1;
reg [4:0] csr_thread_id;
always @ (posedge clk)
begin
rf_imm_en_d1 <= rf_imm_en;
rf_imm_reg_d1 <= rf_imm_reg;
au_op_d1 <= au_op;
csr_thread_id <= thread_decode;
end
//
// Shifters
//
wire [4:0] sh_bits = (au_op_d1[11]) ? au_op_d1[7:3] : reg_b[4:0];
wire [31:0] sh_lsl = (reg_a[31:0] << sh_bits);
wire [31:0] sh_lsr = (reg_a[31:0] >> sh_bits);
wire [31:0] sh_asr = (reg_a[31:0] >>> sh_bits);
//
// Perform operation (step 1)
//
reg [2:0] wbreg_d2;
reg [32:0] au_result_d2;
reg [31:0] csr_thread_mask;
reg [31:0] csr_ticks;
reg [31:0] csr_scratch;
assign thread_mask = csr_thread_mask;
always @ (posedge clk or posedge rst)
if (rst) csr_ticks <= 32'd0;
else csr_ticks <= csr_ticks + 32'd1;
always @ (posedge clk or posedge rst)
if (rst)
begin
wbreg_d2 <= 3'd0;
au_result_d2 <= 33'd0;
csr_thread_mask <= 32'd1;
csr_scratch <= 32'd0;
end
else if (rf_imm_en_d1)
begin
wbreg_d2 <= rf_imm_reg_d1;
au_result_d2 <= reg_a;
end
else if (au_op_d1[14:13] == 2'b00)
begin
wbreg_d2 <= au_op_d1[8:6];
case (au_op_d1[12:9])
4'h0: au_result_d2 <= reg_a | reg_b;
4'h1: au_result_d2 <= reg_a & reg_b;
4'h2: au_result_d2 <= reg_a ^ reg_b;
4'h3: au_result_d2 <= reg_a + reg_b;
4'h4: au_result_d2 <= reg_a - reg_b;
default: au_result_d2 <= 33'd0;
endcase
end
else if (au_op_d1[14:11] == 4'b0100)
begin
wbreg_d2 <= au_op_d1[2:0];
case (au_op_d1[10:6])
5'h00: au_result_d2 <= ~reg_b;
5'h01: au_result_d2 <= (~reg_b) + 33'd1;
5'h02: au_result_d2 <= {{25{reg_b[7]}}, reg_b[7:0]};
5'h03: au_result_d2 <= {{17{reg_b[15]}}, reg_b[15:0]};
5'h04: au_result_d2 <= (|reg_b[31:5]) ? 33'd0 : {sh_lsl[31], sh_lsl};
5'h05: au_result_d2 <= (|reg_b[31:5]) ? 33'd0 : {sh_lsr[31], sh_lsr};
5'h06: au_result_d2 <= (|reg_b[31:5]) ? {33{reg_a[31]}}
: {sh_lsr[31], sh_asr};
5'h1B:
case (au_op_d1[5:3])
3'd0: au_result_d2 <= {1'b0, RTL_VERSION};
3'd1: au_result_d2 <= {28'd0, csr_thread_id};
3'd2: au_result_d2 <= {1'b0, csr_thread_mask};
3'd3: au_result_d2 <= {1'b0, csr_ticks};
3'd7: au_result_d2 <= {1'b0, csr_scratch};
default: au_result_d2 <= 33'd0;
endcase
// NO STORE 1C-1F ...
5'h1D: au_result_d2 <= reg_a & reg_b;
5'h1E: au_result_d2 <= reg_a - reg_b;
5'h1F:
begin
au_result_d2 <= 33'd0;
case (au_op_d1[5:3])
3'd2: csr_thread_mask <= reg_a[31:0];
3'd7: csr_scratch <= reg_a[31:0];
default: ;
endcase
end
default: au_result_d2 <= 33'd0;
endcase
end
else if (au_op_d1[14:11] == 4'b0101)
begin
wbreg_d2 <= au_op_d1[2:0];
case (au_op_d1[10:8])
3'h0: au_result_d2 <= {32'd0, reg_a[au_op_d1[7:3]]};
3'h1: au_result_d2 <= (reg_a & ~(33'd1 << au_op_d1[7:3]));
3'h2: au_result_d2 <= (reg_a | (33'd1 << au_op_d1[7:3]));
3'h3: au_result_d2 <= (reg_a ^ (33'd1 << au_op_d1[7:3]));
3'h4: au_result_d2 <= {sh_lsl[31], sh_lsl};
3'h5: au_result_d2 <= {sh_lsr[31], sh_lsr};
3'h6: au_result_d2 <= {sh_asr[31], sh_asr};
default: au_result_d2 <= 33'd0;
endcase
end
else if (au_op_d1[14:12] == 3'b011)
begin
wbreg_d2 <= au_op_d1[2:0];
au_result_d2 <= reg_a - {{24{au_op_d1[11]}}, au_op_d1[11:3]};
end
else if (au_op_d1[14:13] == 2'b10)
begin
wbreg_d2 <= au_op_d1[2:0];
au_result_d2 <= reg_a + {{23{au_op_d1[12]}}, au_op_d1[12:3]};
end
else if (au_op_d1[14:13] == 2'b11)
begin
wbreg_d2 <= au_op_d1[2:0];
au_result_d2 <= {{23{au_op_d1[12]}}, au_op_d1[12:3]};
end
//
// Perform operation (step 2) - nothing to do
//
reg [32:0] au_result_d3;
reg [2:0] wbreg_d3;
always @ (posedge clk)
begin
wbreg_d3 <= wbreg_d2;
au_result_d3 <= au_result_d2;
end
//
// Store Result
//
reg wb_en_d1;
reg wb_en_d2;
reg wb_en_d3;
wire no_store_op = (au_op[14:8] == 7'b0100111) ||
(au_op[14:12] == 3'b011) ||
(au_op_d1[14:8] == 7'b0101000);
always @ (posedge clk or posedge rst)
if (rst)
begin
wb_en_d1 <= 1'b0;
wb_en_d2 <= 1'b0;
wb_en_d3 <= 1'b0;
end
else
begin
wb_en_d1 <= rf_imm_en || (au_op_en && !no_store_op);
wb_en_d2 <= wb_en_d1;
wb_en_d3 <= wb_en_d2;
end
assign wb_au_en = wb_en_d3;
assign wb_au_reg = wbreg_d3;
assign wb_au_data = au_result_d3[31:0];
//
// Store flags
//
wire au_flag_zero = (au_result_d3 == 33'd0);
wire au_flag_neg = au_result_d3[31];
wire au_flag_ovfl = au_result_d3[32];
assign wb_au_flags_en = wb_en_d3;
assign wb_au_flags = {5'd0, au_flag_ovfl, au_flag_neg, au_flag_zero};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int T = 31; const int mod = 1000000007; const long long oo = 1LL << 60; long long N; int K; long long B[T][T]; long long power[70]; long long dp[70][T][T]; bool bio[70]; long long rot[T][T][T]; long long mult(long long a, long long b) { if (a == 0) return 0; if (b >= oo / a + 1) return oo; return a * b; } void mult(long long A[T][T], long long B[T][T]) { static long long C[T][T]; for (int i = (0); i < (T); ++i) for (int j = (0); j < (T); ++j) C[i][j] = 0; for (int i = (0); i < (T); ++i) for (int j = (0); j < (T); ++j) for (int k = (0); k < (T); ++k) C[i][j] = (C[i][j] + A[i][k] * B[k][j]) % mod; for (int i = (0); i < (T); ++i) for (int j = (0); j < (T); ++j) A[i][j] = C[i][j]; } void rec(long long prefix, int n, long long A[T][T]) { long long lo = mult(prefix, power[n]); long long hi = lo + power[n] - 1; if (lo >= N) return; long long z = prefix % K; mult(A, rot[z]); if (n == 0) { mult(A, B); } else { bool memo = hi < N; auto AA = memo ? dp[n] : A; if (!bio[n] && memo) for (int i = (0); i < (T); ++i) AA[i][i] = 1; if (!bio[n] || !memo) for (int i = (0); i < (K); ++i) rec(prefix * K + i, n - 1, AA); if (memo) bio[n] = true, mult(A, AA); } mult(A, rot[(K - z) % K]); } int main() { scanf( %lld%d , &N, &K); for (int i = (0); i < (K); ++i) B[i][i] = 1; for (int i = (1); i < (K); ++i) B[i][0] = 1; B[K][0] = 1; B[K][K] = 1; for (int x = (0); x < (K); ++x) for (int i = (0); i < (K); ++i) rot[x][i][(i + x) % K] = 1; for (int x = (0); x < (K); ++x) for (int i = (K); i < (T); ++i) rot[x][i][i] = 1; static long long A[T][T]; A[0][K] = 1; power[0] = 1; for (int i = (1); i < (70); ++i) power[i] = mult(power[i - 1], K); rec(0, 69, A); long long ans = 1; for (int i = (0); i < (K); ++i) ans = (ans + A[0][i]) % mod; printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> void r1(T &x) { x = 0; char c(getchar()); int f(1); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); x *= f; } const int maxn = 100000 + 5; const int maxm = maxn << 1; typedef int room[maxn]; int n, m, d; int dis[maxn], f[maxn][2]; int head[maxn], cnt; struct Edge { int to, next; } edg[maxn << 1]; void add(int u, int v) { edg[++cnt] = (Edge){v, head[u]}, head[u] = cnt; } int vis[maxn]; void dfs(int p, int fa) { if (vis[p]) f[p][0] = 0; for (int i = head[p]; i; i = edg[i].next) { int to = edg[i].to; if (to == fa) continue; dfs(to, p); if (f[to][0] + 1 > f[p][0]) { f[p][1] = f[p][0], f[p][0] = f[to][0] + 1; } else f[p][1] = max(f[p][1], f[to][0] + 1); } } void dfs1(int p, int fa) { for (int i = head[p]; i; i = edg[i].next) { int to = edg[i].to; if (to == fa) continue; if (f[p][0] == f[to][0] + 1) { dis[to] = max(f[p][1] + 1, dis[p] + 1); } else dis[to] = max(dis[p] + 1, f[p][0] + 1); dfs1(to, p); } } signed main() { int i, j; memset(f, -0x3f, sizeof(f)), memset(dis, -0x3f, sizeof(dis)); r1(n), r1(m), r1(d); for (i = 1; i <= m; ++i) { int x; r1(x); vis[x] = 1; } for (i = 1; i < n; ++i) { int u, v; r1(u), r1(v); add(u, v), add(v, u); } dfs(1, 0), dfs1(1, 0); int ans((bool)(f[1][1] <= d && f[1][0] <= d)); for (i = 2; i <= n; ++i) if (dis[i] <= d && f[i][0] <= d) { ++ans; } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int s[n]; int f[10] = {0}; for (int i = 0; i < n; i++) { cin >> s[i]; } int tmp; for (int j = 0; j < m; j++) { cin >> tmp; f[tmp] = 1; } int emp = 1; for (int i = 0; i < n; i++) { if (f[s[i]] == 1) { emp = 0; cout << s[i] << ; } } if (emp == 1) cout << n ; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_1_V
`define SKY130_FD_SC_LP__DFSBP_1_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_1_V
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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int flag = 0; int count = 0; if (isupper(s[0])) { flag = 1; count = 1; } for (int i = 1; i < s.length(); i++) { if (isupper(s[i])) count++; } if (count == s.length()) { for (int i = 0; i < s.length(); i++) { s[i] = tolower(s[i]); } } else if (count == s.length() - 1 && flag == 0) { s[0] = toupper(s[0]); for (int i = 1; i < s.length(); i++) { s[i] = tolower(s[i]); } } cout << s; }
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// -- (c) Copyright 2011-2016 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXIS Broadcaster
// Generic single-channel AXIS to multiple channel AXIS.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module top_design_1_axis_broadcaster_0_0 #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "rtl",
parameter integer C_NUM_MI_SLOTS = 2,
parameter integer C_S_AXIS_TDATA_WIDTH = 8,
parameter integer C_M_AXIS_TDATA_WIDTH = 8,
parameter integer C_AXIS_TID_WIDTH = 1,
parameter integer C_AXIS_TDEST_WIDTH = 1,
parameter integer C_S_AXIS_TUSER_WIDTH = 1,
parameter integer C_M_AXIS_TUSER_WIDTH = 1,
parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire aclk,
input wire aresetn,
input wire aclken,
// Slave side
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
input wire s_axis_tlast,
input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input wire [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// Master side
output wire [C_NUM_MI_SLOTS-1:0] m_axis_tvalid,
input wire [C_NUM_MI_SLOTS-1:0] m_axis_tready,
output wire [C_NUM_MI_SLOTS*C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire [(C_NUM_MI_SLOTS*C_M_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tstrb,
output wire [(C_NUM_MI_SLOTS*C_M_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep,
output wire [C_NUM_MI_SLOTS-1:0] m_axis_tlast,
output wire [(C_NUM_MI_SLOTS*C_AXIS_TID_WIDTH)-1:0] m_axis_tid,
output wire [(C_NUM_MI_SLOTS*C_AXIS_TDEST_WIDTH)-1:0] m_axis_tdest,
output wire [(C_NUM_MI_SLOTS*C_M_AXIS_TUSER_WIDTH)-1:0] m_axis_tuser
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TPAYLOAD_WIDTH = f_payload_width(C_S_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH,
C_AXIS_TDEST_WIDTH, C_S_AXIS_TUSER_WIDTH,
C_AXIS_SIGNAL_SET);
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TDATA_WIDTH)-1:0] m_axis_tdata_i;
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep_i;
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tstrb_i;
wire [(C_NUM_MI_SLOTS*C_S_AXIS_TUSER_WIDTH)-1:0] m_axis_tuser_i;
axis_broadcaster_v1_1_8_core #(
.C_FAMILY (C_FAMILY),
.C_NUM_MI_SLOTS ( C_NUM_MI_SLOTS ),
.C_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ),
.C_AXIS_TID_WIDTH ( C_AXIS_TID_WIDTH ),
.C_AXIS_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ),
.C_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ),
.C_AXIS_SIGNAL_SET ( C_AXIS_SIGNAL_SET )
)
broadcaster_core
(
.aclk (aclk),
.aresetn (aresetn),
.aclken (aclken),
.s_axis_tvalid (s_axis_tvalid),
.s_axis_tready (s_axis_tready),
.s_axis_tdata (s_axis_tdata),
.s_axis_tstrb (s_axis_tstrb),
.s_axis_tkeep (s_axis_tkeep),
.s_axis_tlast (s_axis_tlast),
.s_axis_tid (s_axis_tid),
.s_axis_tdest (s_axis_tdest),
.s_axis_tuser (s_axis_tuser),
.m_axis_tvalid (m_axis_tvalid),
.m_axis_tready (m_axis_tready),
.m_axis_tdata (m_axis_tdata_i),
.m_axis_tstrb (m_axis_tstrb_i),
.m_axis_tkeep (m_axis_tkeep_i),
.m_axis_tlast (m_axis_tlast),
.m_axis_tid (m_axis_tid),
.m_axis_tdest (m_axis_tdest),
.m_axis_tuser (m_axis_tuser_i)
);
tdata_design_1_axis_broadcaster_0_0 #(
.C_S_AXIS_TDATA_WIDTH ( C_NUM_MI_SLOTS * C_S_AXIS_TDATA_WIDTH ),
.C_M_AXIS_TDATA_WIDTH ( C_NUM_MI_SLOTS * C_M_AXIS_TDATA_WIDTH )
)
tdata (
.tdata (m_axis_tdata_i),
.tdata_out (m_axis_tdata )
);
assign m_axis_tstrb = (C_S_AXIS_TDATA_WIDTH == C_M_AXIS_TDATA_WIDTH) ? m_axis_tstrb_i : {(C_NUM_MI_SLOTS*(C_M_AXIS_TDATA_WIDTH/8)){1'b0}};
assign m_axis_tkeep = (C_S_AXIS_TDATA_WIDTH == C_M_AXIS_TDATA_WIDTH) ? m_axis_tkeep_i : {(C_NUM_MI_SLOTS*(C_M_AXIS_TDATA_WIDTH/8)){1'b0}};
tuser_design_1_axis_broadcaster_0_0 #(
.C_S_AXIS_TUSER_WIDTH ( C_NUM_MI_SLOTS * C_S_AXIS_TUSER_WIDTH ),
.C_M_AXIS_TUSER_WIDTH ( C_NUM_MI_SLOTS * C_M_AXIS_TUSER_WIDTH )
)
tuser (
.tuser (m_axis_tuser_i),
.tuser_out (m_axis_tuser )
);
endmodule // axis_broadcaster_top
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_FUNCTIONAL_PP_V
|
/**
\file "shoelace.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: shoelace.v,v 1.3 2010/04/06 00:08:37 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`define inv_delay 0.010
`include "clkgen.v"
/* the humble inverter */
module inverter (in, out);
parameter DELAY=`inv_delay;
input in;
output out;
reg __o;
wire out = __o;
always @(in)
begin
#DELAY __o <= ~in;
end
endmodule
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
/* our top-level */
module TOP;
wire in, in1, in2, in3, in4;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
/**
assign in1 = ~out0;
assign in2 = ~out1;
assign in3 = ~out2;
assign in4 = ~out3;
**/
inverter q0(out0, in1);
inverter q1(out1, in2);
inverter q2(out2, in3);
inverter q3(out3, in4);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.in1", "in1");
$to_prsim("TOP.in2", "in2");
$to_prsim("TOP.in3", "in3");
$to_prsim("TOP.in4", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; long long l, val[205], cst[205]; char s[205]; long long ch[205][26], fail[205], cnt = 1; void Insert(char *s, long long w) { long long len = strlen(s), r = 0; for (long long i = 0; i < len; i++) { long long val = s[i] - a ; if (!ch[r][val]) ch[r][val] = cnt++; r = ch[r][val]; } val[r] += w; } long long Q[205], L, R; void build(long long r) { Q[L = 0] = r, R = 1; long long p, c; for (; L < R;) { r = Q[L++]; for (long long i = 0; i < 26; i++) if (c = ch[r][i]) { Q[R++] = c; for (p = fail[r]; p != 0 && ch[p][i] == 0; p = fail[p]) ; long long tmp = ch[p][i]; if (tmp && tmp != c) fail[c] = tmp; else fail[c] = 0; val[c] += val[fail[c]]; } else { for (p = fail[r]; p != 0 && ch[p][i] == 0; p = fail[p]) ; long long tmp = ch[p][i]; if (tmp) ch[r][i] = tmp; else ch[r][i] = 0; } } } long long dp[205][205], dp2[205][205], dp3[205][205], A[205][205], B[205][205]; void solve(long long a[205][205], long long b[205][205], long long c[205][205]) { memcpy(A, a, sizeof A), memcpy(B, b, sizeof B); for (long long k = 0; k < cnt; k++) for (long long i = 0; i < cnt; i++) for (long long j = 0; j < cnt; j++) if (A[i][k] != -0x3f3f3f3f3f3f3f3fll && B[k][j] != -0x3f3f3f3f3f3f3f3fll) c[i][j] = max(c[i][j], A[i][k] + B[k][j]); } int main() { scanf( %lld%lld , &n, &l); for (long long i = 1; i <= n; i++) scanf( %lld , &cst[i]); fail[0] = -1; for (long long i = 1; i <= n; i++) { scanf( %s , s); Insert(s, cst[i]); } build(0); for (long long i = 0; i < cnt; i++) for (long long j = 0; j < cnt; j++) dp[i][j] = dp2[i][j] = -0x3f3f3f3f3f3f3f3fll; for (long long i = 0; i < cnt; i++) dp[i][i] = dp2[i][i] = 0; for (long long i = 0; i < cnt; i++) for (long long j = 0; j < 26; j++) dp[i][ch[i][j]] = val[ch[i][j]]; for (; l; l >>= 1, solve(dp, dp, dp)) if (l & 1) solve(dp, dp2, dp2); printf( %lld n , *max_element(dp2[0], dp2[0] + cnt + 1)); }
|
// File: SeqROMEx_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Jun 27 01:09:28 2018
`timescale 1ns/10ps
module SeqROMEx_TBV (
);
// Verilog Only Testbench for `SeqROMEx`
reg [3:0] dout = 0;
reg clk = 0;
wire rst;
reg [2:0] SeqROMEx0_0_1_2_3_Count = 0;
assign rst = 1'd0;
always @(posedge clk) begin: SEQROMEX_TBV_SEQROMEX0_0_1_2_3_COUNTER
if (rst) begin
SeqROMEx0_0_1_2_3_Count <= 0;
end
else if ((SeqROMEx0_0_1_2_3_Count == 3)) begin
SeqROMEx0_0_1_2_3_Count <= 0;
end
else begin
SeqROMEx0_0_1_2_3_Count <= (SeqROMEx0_0_1_2_3_Count + 1);
end
end
always @(posedge clk) begin: SEQROMEX_TBV_SEQROMEX0_0_1_2_3_MEMORY
case (SeqROMEx0_0_1_2_3_Count)
'h0: begin
dout <= 3;
end
'h1: begin
dout <= 2;
end
'h2: begin
dout <= 1;
end
'h3: begin
dout <= 0;
end
endcase
end
initial begin: SEQROMEX_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: SEQROMEX_TBV_STIMULES
integer i;
for (i=0; i<(5 + 1); i=i+1) begin
@(posedge clk);
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
end
$finish;
end
always @(posedge clk) begin: SEQROMEX_TBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write(" ");
$write("%h", dout);
$write("\n");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int c[n + 1], e[n - 1][2]; for (int i = 0; i < n - 1; ++i) { cin >> e[i][0] >> e[i][1]; } for (int i = 1; i <= n; ++i) { cin >> c[i]; } vector<int> e1; vector<int> e2; for (int i = 0; i < n - 1; ++i) { if (c[e[i][1]] != c[e[i][0]]) { e1.push_back(e[i][1]); e2.push_back(e[i][0]); } } bool k = true; int v = 1; if (n > 2 && e1.size() > 1) { if (e1[0] == e1[1] || e1[0] == e2[1]) { v = e1[0]; } else if (e2[0] == e1[1] || e2[0] == e2[1]) { v = e2[0]; } else { k = false; } for (int i = 1; i < e1.size(); ++i) { if (e1[i] != v && e2[i] != v) { k = false; break; } } } if (e1.size() == 1) v = e1[0]; if (k || n < 3) cout << YES << n << v; else cout << NO ; return 0; }
|
`timescale 1 ns / 1 ps
`include "pmod_io_switch_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module pmod_io_switch_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
`define WIDTH_P ? // unused for now...
module test_bsg;
import bsg_tag_pkg::bsg_tag_s;
// Enable VPD dump file
//
initial
begin
$vcdpluson;
$vcdplusmemon;
end
logic TCK,TDI,TMS;
localparam bsg_tag_els_lp = 4;
wire [bsg_tag_els_lp-1:0] bsg_recv_clocks;
genvar i;
for (i = 0; i < bsg_tag_els_lp; i=i+1)
begin: rof
bsg_nonsynth_clock_gen #(i+2) recv_clock(bsg_recv_clocks[i]);
end
// Config net configuration clock. We run it continuously
// but this is not necessary.
bsg_nonsynth_clock_gen #(100) cfg_clk_gen (TCK);
bsg_tag_s [bsg_tag_els_lp-1:0] clients_lo;
logic [bsg_tag_els_lp-1:0] clients_reset;
wire [bsg_tag_els_lp-1:0] clients_new;
wire [bsg_tag_els_lp-1:0][bsg_tag_els_lp*8+5-1:0] clients_data;
localparam payload_bits_lp = 7;
localparam max_payload_lp = (1 << payload_bits_lp)-1;
`declare_bsg_tag_header_s(bsg_tag_els_lp,payload_bits_lp)
// one master tag to connect to the clients
bsg_tag_master #(.els_p(bsg_tag_els_lp), .lg_width_p(payload_bits_lp)) btm
(.clk_i (TCK)
,.data_i (TDI)
,.en_i (TMS)
,.clients_r_o(clients_lo)
);
// stamp out a bunch of client tags
for (i = 0; i < bsg_tag_els_lp; i=i+1)
begin: rof2
bsg_tag_client #(.width_p(5+i*8)
,.default_p(i)
) btc
(.bsg_tag_i (clients_lo [i])
,.recv_clk_i (bsg_recv_clocks [i])
,.recv_reset_i (clients_reset [i])
,.recv_new_r_o (clients_new [i])
,.recv_data_r_o(clients_data [i][0+:5+i*8])
);
always @(clients_data[i])
begin
$display("## client %d data = %b new = %b",i,clients_data[i],clients_new[i]);
end
end
bsg_tag_header_s send_me;
wire [5+3*8-1:0] val = 29'b0_1111_1001_0110_0011_1100_1010_0101;
initial
begin
$display("## sim start");
send_me.nodeID = 3;
send_me.data_not_reset = 0;
send_me.len = max_payload_lp;
@(negedge TCK);
TDI = 1'b0;
TMS = 1'b1;
@(negedge TCK);
clients_reset[0] = 1;
// clear reset counter going
@(negedge TCK);
TDI = 1'b1;
clients_reset[0] = 0;
// start reset counter going
@(negedge TCK);
TDI = 1'b0;
// trigger bsg_tag_master reset
for (integer i = 0; i < `bsg_tag_reset_len(bsg_tag_els_lp,payload_bits_lp); i++)
@(posedge TCK);
// packet bit
@(negedge TCK);
TDI = 1'b1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
send_me.data_not_reset = 1;
send_me.len = 29;
// transmit reset payload
for (integer i = 0; i < max_payload_lp; i=i+1)
begin
@(negedge TCK);
TDI = 1'b1;
end
// packet bit
@(negedge TCK);
TDI = 1'b1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
// transmit payload
for (integer i = 0; i < 29; i=i+1)
begin
@(negedge TCK);
TDI = val[i];
end
// packet bit
@(negedge TCK);
TDI = 1'b1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
// transmit payload
for (integer i = 0; i < 29; i=i+1)
begin
@(negedge TCK);
TDI = val[i];
end
// packet bit
@(negedge TCK);
TDI = 1'b1;
send_me.nodeID = 1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
// transmit payload
for (integer i = 0; i < 29; i=i+1)
begin
@(negedge TCK);
TDI = val[i];
end
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
$finish;
end
endmodule
|
#include <bits/stdc++.h> int main(void) { int a[5]; int Min; while (scanf( %d%d%d%d%d , a, a + 1, a + 2, a + 3, a + 4) != EOF) { Min = a[0]; if (a[1] < Min) Min = a[1]; if (a[2] / 2 < Min) Min = a[2] / 2; if (a[3] / 7 < Min) Min = a[3] / 7; if (a[4] / 4 < Min) Min = a[4] / 4; printf( %d n , Min); } return EXIT_SUCCESS; }
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_pio_1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 2: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_SYMBOL_V
`define SKY130_FD_SC_LS__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_SYMBOL_V
|
module octal();
reg [5:0] var1;
reg [4:0] var2;
initial begin
var1 = 6'o00; $displayo($signed(var1));
var1 = 6'o01; $displayo($signed(var1));
var1 = 6'o02; $displayo($signed(var1));
var1 = 6'o03; $displayo($signed(var1));
var1 = 6'o04; $displayo($signed(var1));
var1 = 6'o05; $displayo($signed(var1));
var1 = 6'o06; $displayo($signed(var1));
var1 = 6'o07; $displayo($signed(var1));
var1 = 6'o10; $displayo($signed(var1));
var1 = 6'o20; $displayo($signed(var1));
var1 = 6'o30; $displayo($signed(var1));
var1 = 6'o40; $displayo($signed(var1));
var1 = 6'o50; $displayo($signed(var1));
var1 = 6'o60; $displayo($signed(var1));
var1 = 6'o70; $displayo($signed(var1));
var1 = 6'o17; $displayo($signed(var1));
var1 = 6'o26; $displayo($signed(var1));
var1 = 6'o35; $displayo($signed(var1));
var1 = 6'o44; $displayo($signed(var1));
var1 = 6'o53; $displayo($signed(var1));
var1 = 6'o62; $displayo($signed(var1));
var1 = 6'o71; $displayo($signed(var1));
$display("");
var2 = 6'o00; $displayo($signed(var2));
var2 = 6'o01; $displayo($signed(var2));
var2 = 6'o02; $displayo($signed(var2));
var2 = 6'o03; $displayo($signed(var2));
var2 = 6'o04; $displayo($signed(var2));
var2 = 6'o05; $displayo($signed(var2));
var2 = 6'o06; $displayo($signed(var2));
var2 = 6'o07; $displayo($signed(var2));
var2 = 6'o10; $displayo($signed(var2));
var2 = 6'o20; $displayo($signed(var2));
var2 = 6'o30; $displayo($signed(var2));
var2 = 6'o17; $displayo($signed(var2));
var2 = 6'o26; $displayo($signed(var2));
var2 = 6'o35; $displayo($signed(var2));
end
endmodule
|
//hardware top level module
module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData,
input [ 7:0 ] exData
);
//metastability input filters
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_metafilter #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_metafilter #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_metafilter #(.SIZE(5)) f2(clkIn, regAddr, addr );
//cores
//clock devider
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData ),
.exData ( exData )
);
endmodule
//metastability input filter module
module sm_metafilter
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
);
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule
//tunable clock devider
module sm_clk_divider
#(
parameter shift = 16
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = cntr[shift + devide];
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_dwidth_converter:1.1
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_axis_dwidth_converter_0_0 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input [63 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output [255 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output [31 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output m_axis_tlast;
axis_dwidth_converter_v1_1_axis_dwidth_converter #(
.C_FAMILY("zynq"),
.C_S_AXIS_TDATA_WIDTH(64),
.C_M_AXIS_TDATA_WIDTH(256),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_S_AXIS_TUSER_WIDTH(1),
.C_M_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00010011)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(8'HFF),
.s_axis_tkeep(8'HFF),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_NIOS_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ADC.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module ADC (
address,
clock,
q);
input [10:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ADC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ADC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { double n, a, d; cin >> n >> a >> d; vector<int> t; vector<int> v; double prev = 0; int bit = 1; for (int i = 0; i < n; i++) { double t1, v1; cin >> t1 >> v1; double t2 = 0, t3 = 0, tot = 0; double dis = 0; t2 = (double)(v1) / double(a); dis = a * (t2) * (t2); dis = (float)dis / (float)2; if (dis >= d) { double velo = 2 * a * d; velo = sqrt(velo); t2 = velo / a; tot = t2 + (double)t1; } else { dis = d - dis; t3 = (double)dis / (double)v1; tot = (double)t2 + t3 + (double)t1; } if (tot > prev || bit == 1) { cout << setprecision(12) << tot << endl; prev = tot; bit = 0; } else { cout << setprecision(12) << prev << endl; bit = 0; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_4_V
`define SKY130_FD_SC_MS__A2BB2O_4_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_4_V
|
#include <bits/stdc++.h> using namespace std; int n; char s[105]; string S; multiset<string> st; vector<string> v; inline bool cmp(string a, string b) { return a.length() < b.length(); } int cnt[26]; char ans[105]; int f[105][26]; int main() { scanf( %d , &n); if (n <= 3) { if (n == 1) { printf( ? 1 1 n ), fflush(stdout); scanf( %s , s); printf( ! %s n , s); return 0; } printf( ? 2 %d n , n), fflush(stdout); for (int i = 1; i <= n * (n - 1) / 2; i++) { scanf( %s , s); S = s; sort(S.begin(), S.end()); st.insert(S); } printf( ? 1 %d n , n), fflush(stdout); for (int i = 1; i <= n * (n + 1) / 2; i++) { scanf( %s , s); S = s; sort(S.begin(), S.end()); if (st.find(S) == st.end()) v.push_back(S); else st.erase(st.find(S)); } sort(v.begin(), v.end(), cmp); printf( ! ); for (int i = 0; i < n; i++) { if (i == 0) { printf( %c , v[i][0]); continue; } for (int j = 0; j < i + 1; j++) cnt[v[i][j] - a ]++; for (int j = 0; j < i; j++) cnt[v[i - 1][j] - a ]--; for (int j = 0; j < 26; j++) { if (cnt[j]) { cnt[j] = 0, printf( %c , j + a ); break; } } } puts( ); return 0; } int m = (n + 1) / 2; printf( ? 2 %d n , m), fflush(stdout); for (int i = 1; i <= m * (m - 1) / 2; i++) { scanf( %s , s); S = s; sort(S.begin(), S.end()); st.insert(S); } printf( ? 1 %d n , m), fflush(stdout); for (int i = 1; i <= m * (m + 1) / 2; i++) { scanf( %s , s); S = s; sort(S.begin(), S.end()); if (st.find(S) == st.end()) v.push_back(S); else st.erase(st.find(S)); } sort(v.begin(), v.end(), cmp); for (int i = 0; i < m; i++) { if (i == 0) { ans[i + 1] = v[i][0]; continue; } for (int j = 0; j < i + 1; j++) cnt[v[i][j] - a ]++; for (int j = 0; j < i; j++) cnt[v[i - 1][j] - a ]--; for (int j = 0; j < 26; j++) { if (cnt[j]) { cnt[j] = 0, ans[i + 1] = j + a ; break; } } } printf( ? 1 %d n , n), fflush(stdout); for (int i = 1; i <= n * (n + 1) / 2; i++) { scanf( %s , s); int len = strlen(s); for (int j = 0; j < len; j++) { f[len][s[j] - a ]++; } } for (int i = m; i; i--) { for (int j = 0; j < 26; j++) { int x = f[i][j] - f[i - 1][j]; for (int k = i; k < n + 1 - i; k++) x -= ans[k] == j + a ; if (x) { ans[n + 1 - i] = j + a ; break; } } } printf( ! ); for (int i = 1; i <= n; i++) printf( %c , ans[i]); puts( ); }
|
/*
Servo Controller test bench
Author: Nathan Larson
Date: 10/20/2016
*/
`timescale 1 ns/ 1 ps
module ServoController_vlg_tst();
// test vector input registers
reg clk;
reg enable;
reg [7:0] pulse_in;
// wires
wire PWM_out;
pwm_generator #(.PWM_DEPTH(8)) i1 // pwm0 is your instance name
(//ports
.pwm( PWM_out ), // PWM output signal
.duty_cycle( pulse_in ), // PWM duty cycle (vector)
.rst_n( enable ), // Active-low reset
.clk( clk ) // Clock signal
);
initial
begin
// code that executes only once
// insert code here --> begin
$display("Running testbench");
enable = 0;
clk = 0;
pulse_in = 8'b00001111;
#10
enable = 1;
#20000;
pulse_in = 8'b00111111;
#20000;
pulse_in = 8'b11111000;
#20000;
// --> end
end
always #10 clk = ~clk;
// optional sensitivity list
// @(event1 or event2 or .... eventn)
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:26:07 09/22/2014
// Design Name:
// Module Name: filter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//sram0から32bのデータを読み込んできて，8bに分けてfilter_unitに与え
//結果の8bを32bに集めて，sram1に書き込む
module filter #(
parameter ADDRESS_WIDTH = 32,
parameter SRAMDATA_WIDTH = 32,
parameter TAG_WIDTH = 2
) (
output reg request0, request1,
output reg command_entry0, command_entry1,
output reg write_enable1,
output [ADDRESS_WIDTH - 1: 0] address0, address1,
output reg [TAG_WIDTH - 1: 0] tag0,
output reg [SRAMDATA_WIDTH - 1: 0] data_out1,
output reg is_end,
//debug用レジスタuser_reg(60~63)に対応
output reg [31:0] debug_signal0,
output reg [31:0] debug_signal1,
output reg [31:0] debug_signal2,
output reg [31:0] debug_signal3,
input valid0, valid1,
input [SRAMDATA_WIDTH - 1: 0] query0,
input [TAG_WIDTH - 1: 0] qtag0,
input ready0, ready1,
input [31: 0] image_size,
input [9: 0] image_width,
input user_flag,
input [9: 0] pos_x,
input [9: 0] pos_y,
input refresh,
input reset,
input clock
);
//! Constants
parameter INVALID_TAG = 2'd0;
parameter DATA_TAG0 = 2'd1;
parameter DATA_TAG1 = 2'd2;
parameter DATA_END_TAG = 2'd3;
//! Implement
wire [TAG_WIDTH-1:0] is_tag_in;
wire [TAG_WIDTH-1:0] is_tag_out;
wire [7:0] pixel_in;
wire [7:0] pixel_out;
wire [8+TAG_WIDTH-1:0] data_in;
wire [8+TAG_WIDTH-1:0] data_out;
reg [1:0] count0;
reg [1:0] count1;
reg [9:0] width_count;
reg [31:0] system_count;
reg [ADDRESS_WIDTH:0] ptr0;
reg [ADDRESS_WIDTH:0] ptr1;
reg [TAG_WIDTH-1:0] tag_in;
reg [TAG_WIDTH-1:0] tag_out;
reg start;
reg [SRAMDATA_WIDTH-1:0] word_in;
assign is_tag_in = (valid0 && is_end==1'b0)? qtag0 : INVALID_TAG;
assign pixel_in= word_in[0+:8];
assign data_in[8+:TAG_WIDTH] = tag_in;
assign data_in[0+:8] = pixel_in;
assign pixel_out = data_out[0+:8];
assign is_tag_out = data_out[8+:TAG_WIDTH];
assign address0 = (ptr0>>2);
assign address1 = (ptr1>>2);
always @(posedge clock) begin
debug_signal0 <= (reset) ? 32'h0: pos_x;
debug_signal1 <= (reset) ? 32'h0: pos_y;
debug_signal2 <= (reset) ? 32'h0: 32'h0;
debug_signal3 <= (reset) ? 32'h0: 32'h0;
start <=
(reset|refresh)? 1'b1: (
(is_tag_in==DATA_TAG0||is_tag_in==DATA_TAG1)? 1'b0 : (
start));
system_count <=
(reset|refresh)? 32'h0: (
(system_count == (image_size<<2))? (image_size<<2): system_count + 32'h1);
tag_in <=
(reset|refresh)? INVALID_TAG:is_tag_in;
tag_out <=
(reset|refresh)? INVALID_TAG:is_tag_out;
request0 <=
(reset)? 1'b0: (
(refresh)? 1'b1: (
(is_end)? 1'b0: (
request0)));
request1 <=
(reset)? 1'b0: (
(refresh)? 1'b1: (
(is_end)? 1'b0: (
request1)));
command_entry0 <=
(reset | refresh)? 0: (
ready0);
command_entry1 <=
(reset | refresh| is_end)? 0: (
(ready1&(count1==2'b10)&(start==1'b0))? 1 : (
0));
write_enable1 <=
(reset | refresh | is_end)? 0: (
ready1);
ptr0 <=
(reset|refresh)? 32'h0: (
(ptr0 == image_size)? image_size: (
(ready0)? ptr0 + 1: (
ptr0)));
width_count <=
(reset|refresh)? 10'b0 : (
(width_count==(image_width-10'h1))? 10'b0 :(
(ready0)? width_count+10'b01:width_count));
ptr1 <=
(reset|refresh|start)? 32'h0: (
((ptr1 == image_size))? image_size: (
(ready1 && (tag_out==DATA_TAG0||tag_out==DATA_TAG1))? ptr1 + 1: (
ptr1)));
tag0 <=
(reset | refresh| is_end | (!ready0) )? INVALID_TAG: (
(ptr0 == image_size)? DATA_END_TAG:(
(width_count==(image_width-10'h1))? DATA_TAG1: DATA_TAG0));
count0 <=
(reset|refresh)? 2'b00 : (
(ready0 &(tag_in==DATA_TAG0||tag_in==DATA_TAG1)&(start==1'b0))? count0+2'b01: (
count0));
count1 <=
(reset|refresh)? 2'b00 : (
(ready1 & (tag_out==DATA_TAG0||tag_out==DATA_TAG1))? count1+2'b01: (
count1));
word_in <=
(is_end)? 32'h0:(
(reset|refresh|start)? query0 : (
(count0==2'b11)? query0:(word_in >> 8)));
data_out1[23: 0]<= (data_out1[31:8]);
data_out1[31:24]<=pixel_out;
is_end <=
(reset|refresh)? 0: (
(ptr1 == (image_size) || system_count == (image_size<<2) )? 1: (
is_end));
end
//Ope_Width must be odd
filter_unit #(
.TAG_WIDTH(TAG_WIDTH),
.INVALID_TAG(INVALID_TAG),
.DATA_TAG0(DATA_TAG0),
.DATA_TAG1(DATA_TAG1),
.DATA_END_TAG(DATA_END_TAG),
.OPE_WIDTH(3)
)fil_uni(
.data_in(data_in),
.image_width(image_width),
.clk(clock),
.rst(reset),
.refresh(refresh),
.data_out(data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << (n / 2) + n; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const long long inf = 2e9 + 10; template <typename T1, typename T2> static void relax(T1 &x, T2 y) { if (x > y) x = y; } template <typename T1, typename T2> static void gain(T1 &x, T2 y) { if (x < y) x = y; } long long powmod(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline void add(int &x, int y) { x += y; if (x >= mod) x -= mod; } inline void sub(int &x, int y) { x -= y; if (x < 0) x += mod; } const int maxl = 2e3 + 3; int m, d; string a, b; int dp[maxl][maxl][2]; int solve(string s) { int n = (int)s.length(); for (int(i) = 0; (i) < (int)(n + 1); ++(i)) for (int(j) = 0; (j) < (int)(m); ++(j)) for (int(k) = 0; (k) < (int)(2); ++(k)) dp[i][j][k] = 0; dp[0][0][1] = 1; for (int(i) = 0; (i) < (int)(n); ++(i)) for (int(j) = 0; (j) < (int)(m); ++(j)) for (int(k) = 0; (k) < (int)(2); ++(k)) for (int dgt = 0; dgt <= (k ? int(s[i] - 0 ) : 9); ++dgt) { if ((i & 1) && dgt != d) continue; if (!(i & 1) && dgt == d) continue; int ni = i + 1; int nj = ((j * 10 + dgt) % m); int nk = k && (dgt == int(s[i] - 0 )); add(dp[ni][nj][nk], dp[i][j][k]); } int ans = 0; for (int(k) = 0; (k) < (int)(2); ++(k)) add(ans, dp[n][0][k]); return ans; } bool ok(string s) { int n = (int)s.length(); int rem = 0; for (int(i) = 0; (i) < (int)(n); ++(i)) { int dgt = int(s[i] - 0 ); if ((i & 1) && dgt != d) return false; if (!(i & 1) && dgt == d) return false; rem = (rem * 10 + dgt) % m; } return !rem; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> m >> d; cin >> a; cin >> b; int ans = 0; add(ans, solve(b)); sub(ans, solve(a)); add(ans, ok(a)); cout << ans << n ; return 0; }
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
`include "config.vh"
/* Chien search, determines roots of a polynomial defined over a finite field */
module bch_chien_reg #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter REG = 1,
parameter SKIP = 0,
parameter STRIDE = 1
) (
input clk,
input start,
input [`BCH_M(P)-1:0] in,
output reg [`BCH_M(P)-1:0] out = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
wire [M-1:0] mul_out;
wire [M-1:0] mul_out_start;
if (!SKIP)
assign mul_out_start = in;
else begin
/* Initialize with coefficients of the error location polynomial */
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const2 #(M, lpow(M, REG * SKIP)) u_mult_start(
.standard_in(in),
.standard_out(mul_out_start)
);
else
parallel_standard_multiplier #(M) u_mult_start(
.standard_in1(in),
.standard_in2(lpow(M, REG * SKIP)),
.standard_out(mul_out_start)
);
end
/* Multiply by alpha^P */
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const1 #(M, lpow(M, REG * STRIDE)) u_mult(
.standard_in(out),
.standard_out(mul_out)
);
else
parallel_standard_multiplier #(M) u_mult(
.standard_in1(lpow(M, REG * STRIDE)),
.standard_in2(out),
.standard_out(mul_out)
);
always @(posedge clk)
out <= #TCQ start ? mul_out_start : mul_out;
endmodule
module bch_chien_expand #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter REG = 1,
parameter SKIP = 1
) (
input [`BCH_M(P)-1:0] in,
output [`BCH_M(P)-1:0] out
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
parallel_standard_multiplier_const1 #(M, lpow(M, REG * SKIP)) u_mult(
.standard_in(in),
.standard_out(out)
);
endmodule
/*
* Each register is loaded with the associated syndrome
* and multiplied by alpha^i each cycle.
*/
module bch_chien #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
/*
* For multi-bit output, Only implement every Nth register. Use async
* logic to fill in the remaining values.
*/
parameter REG_RATIO = BITS > 8 ? 8 : BITS
) (
input clk,
input start,
input [`BCH_SIGMA_SZ(P)-1:0] sigma,
output first, /* First valid output data */
output [`BCH_CHIEN_SZ(P)*BITS-1:0] chien
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
localparam SKIP = `BCH_K(P) - `BCH_DATA_BITS(P);
if (REG_RATIO > BITS)
chien_reg_ratio_must_be_less_than_or_equal_to_bits u_crrmbltoeqb();
genvar i, b;
generate
for (b = 0; b < BITS; b = b + 1) begin : BIT
for (i = 0; i <= T; i = i + 1) begin : REG
if (!(b % REG_RATIO)) begin : ORIG
bch_chien_reg #(M, i + 1, SKIP + b - BITS + 1 + `BCH_N(P), BITS) u_chien_reg(
.clk(clk),
.start(start),
.in(sigma[i*M+:M]),
.out(chien[((BITS-b-1)*(T+1)+i)*M+:M])
);
end else begin : EXPAND
bch_chien_expand #(M, i + 1, b % REG_RATIO) u_chien_expand(
.in(chien[((BITS-b+(b%REG_RATIO)-1)*(T+1)+i)*M+:M]),
.out(chien[((BITS-b-1)*(T+1)+i)*M+:M])
);
end
end
end
endgenerate
pipeline #(2) u_first_pipeline (
.clk(clk),
.i(start),
.o(first)
);
endmodule
module bch_chien_counter #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1
) (
input clk,
input first, /* First valid output data */
output last, /* Last valid output cycle */
output valid /* Outputting data */
);
`include "bch.vh"
localparam TCQ = 1;
localparam CYCLES = (`BCH_DATA_BITS(P) + BITS - 1) / BITS;
localparam M = `BCH_M(P);
if (CYCLES == 1) begin
assign last = first;
assign valid = first;
end else begin
reg _valid = 0;
reg _last = 0;
wire penult;
if (CYCLES == 2)
assign penult = first;
else if (CYCLES == 3)
assign penult = valid && !last;
else begin
wire [M-1:0] count;
lfsr_counter #(M) u_counter(
.clk(clk),
.reset(first),
.ce(valid),
.count(count)
);
assign penult = count == lfsr_count(M, CYCLES - 3);
end
always @(posedge clk) begin
if (first)
_valid <= #TCQ 1;
else if (last)
_valid <= #TCQ 0;
_last <= #TCQ penult;
end
assign last = _last;
assign valid = _valid;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10, M = (1 << 18); int n, a[N], fa[N], cnt; long long ans; pair<int, int> mx[M][2], cur[M]; int getfa(int x) { return fa[x] == x ? x : fa[x] = getfa(fa[x]); } bool merge(int x, int y) { x = getfa(x), y = getfa(y); if (x == y) return 0; fa[x] = y; return 1; } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]), fa[i] = i; ans -= a[i]; } cnt = n + 1; while (cnt > 1) { for (int i = 0; i <= M - 1; i++) for (int j = 0; j <= 1; j++) mx[i][j] = make_pair(-1, -1); for (int i = 0; i <= n; i++) { pair<int, int> t = make_pair(a[i], getfa(i)); if (mx[a[i]][0] < t) { if (mx[a[i]][0].second != t.second) mx[a[i]][1] = mx[a[i]][0]; mx[a[i]][0] = t; } else if (mx[a[i]][1] < t) { if (mx[a[i]][0].second != t.second) mx[a[i]][1] = t; } } for (int i = 0; i <= M - 1; i++) { for (int j = 0; j <= 18; j++) { if (i & (1 << j)) { for (int k = 0; k <= 1; k++) { if (mx[i][0] < mx[i ^ (1 << j)][k]) { if (mx[i][0].second != mx[i ^ (1 << j)][k].second) mx[i][1] = mx[i][0]; mx[i][0] = mx[i ^ (1 << j)][k]; } else if (mx[i][1] < mx[i ^ (1 << j)][k]) { if (mx[i][0].second != mx[i ^ (1 << j)][k].second) mx[i][1] = mx[i ^ (1 << j)][k]; } } } } } for (int i = 0; i <= n; i++) cur[i] = make_pair(-1, -1); for (int i = 0; i <= n; i++) { int f = getfa(i); int t = ((M - 1) ^ a[i]); if (mx[t][0].second != -1 && mx[t][0].second != f) { cur[f] = max(cur[f], make_pair(mx[t][0].first + a[i], mx[t][0].second)); } else if (mx[t][1].second != -1 && mx[t][1].second != f) { cur[f] = max(cur[f], make_pair(mx[t][1].first + a[i], mx[t][1].second)); } } for (int i = 0; i <= n; i++) { if (fa[i] == i && merge(i, cur[i].second)) { cnt--, ans += cur[i].first; } } } printf( %lld n , ans); return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_256_139.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "139"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "139"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "139"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 139 0 INPUT NODEFVAL "data[138..0]"
// Retrieval info: USED_PORT: q 0 0 139 0 OUTPUT NODEFVAL "q[138..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 139 0 data 0 0 139 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 139 0 @q 0 0 139 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_wave*.jpg FALSE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:47 09/23/2013
// Design Name:
// Module Name: Comparador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comparador(clock, reset, write_value, read_value,
read_value_reg_en, led_success, led_fail);
input clock, reset, read_value_reg_en;
input [3:0] write_value, read_value;
output led_success, led_fail;
//Variable que guarda el valor del valor leido
reg [3:0] read_value_reg;
assign led_success = (write_value == read_value_reg);
assign led_fail = ~led_success;
//Guarda el valor leido en un registro con el enable
always @( posedge clock or posedge reset)
begin
if(reset)
begin
read_value_reg <= 4'b0;
end
else if (read_value_reg_en)
begin
read_value_reg <= read_value;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Q { int l; int r; int num; Q(int _l, int _r, int _num) : l(_l), r(_r), num(_num) {} }; int cnt[100100]; int res[100100]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } vector<int> comp = a; sort(comp.begin(), comp.end()); comp.resize(unique(comp.begin(), comp.end()) - comp.begin()); for (int i = 0; i < n; i++) { a[i] = lower_bound(comp.begin(), comp.end(), a[i]) - comp.begin(); } int K = sqrt(n); int B = n / K + 1; vector<vector<Q>> blocks(B); for (int i = 0; i < m; i++) { int l, r; cin >> l >> r; l--; r--; blocks[l / K].emplace_back(l, r, i); } for (int b = 0; b < B; b++) { sort(blocks[b].begin(), blocks[b].end(), [&](Q x, Q y) { return x.r < y.r; }); } for (int b = 0; b < B; b++) { if (blocks[b].empty()) continue; memset(cnt, 0, sizeof(cnt)); int ans = 0; for (int i = blocks[b][0].l; i <= blocks[b][0].r; i++) { if (cnt[a[i]] == comp[a[i]]) { ans--; } cnt[a[i]]++; if (cnt[a[i]] == comp[a[i]]) { ans++; } } int pl = blocks[b][0].l; int pr = blocks[b][0].r; res[blocks[b][0].num] = ans; for (int q = 1; q < (int)blocks[b].size(); q++) { for (int i = pr + 1; i <= blocks[b][q].r; i++) { if (cnt[a[i]] == comp[a[i]]) { ans--; } cnt[a[i]]++; if (cnt[a[i]] == comp[a[i]]) { ans++; } } pr = blocks[b][q].r; for (int i = blocks[b][q].l; i < pl; i++) { if (cnt[a[i]] == comp[a[i]]) { ans--; } cnt[a[i]]++; if (cnt[a[i]] == comp[a[i]]) { ans++; } } for (int i = pl; i < blocks[b][q].l; i++) { if (cnt[a[i]] == comp[a[i]]) { ans--; } cnt[a[i]]--; if (cnt[a[i]] == comp[a[i]]) { ans++; } } pl = blocks[b][q].l; res[blocks[b][q].num] = ans; } } for (int i = 0; i < m; i++) { cout << res[i] << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, q; scanf( %d %d , &n, &q); string s; cin >> s; int size = s.size(); int cnt = 0; for (int i = 1; i < size; i++) { if (s[i] == . && s[i] == s[i - 1]) cnt++; } while (q--) { int n1; char x; scanf( %d %c , &n1, &x); n1--; if (isalpha(x) == isalpha(s[n1])) ; else if (x == . && s[n1] != . ) { if (n1 < n - 1) if (s[n1 + 1] == . ) cnt++; if (n1 > 0) if (s[n1 - 1] == . ) cnt++; } else { if (n1 < n - 1) if (s[n1 + 1] == . ) cnt--; if (n1 > 0) if (s[n1 - 1] == . ) cnt--; } s[n1] = x; printf( %d n , cnt); } return 0; }
|
/**************************************************************\
*
* WS2812 LED controll module
*
* Parameters:
* CYCLES_SHORT clk cycles for the 400 ns duration
* CYCLES_LONG clk cycles for the 800 ns duration
* CYCLES_RET clk cycles for the wait time after
* clocking the bits out
*
* inputs:
* clk clock signal
* resetn reset signal (low active)
* bitstream_available in idle state trigger clocking
* out the bitstream supplied
* bitstream the bitstream to be clocked out
*
* outputs:
* bitstream_read bitstream has been read and may be updated
* ws2811_data the actual output to control the ws2811 LEDs
* debug_info
*
\**************************************************************/
module ws2812b_out_module (
input clk,
input resetn,
input bitstream_available,
input [23:0] bitstream,
output reg bitstream_read,
output reg ws2812b_data,
output reg [3:0] debug_info
);
parameter CYCLES_SHORT = 3; // ~0,44 us @ 9 MHz
parameter CYCLES_LONG = 5; // ~0,66 us @ 9 MHz
parameter CYCLES_RET = 450; // 50,0 us @ 9 MHz
localparam CYCLES_WIDTH = $clog2(CYCLES_RET > CYCLES_LONG ? CYCLES_RET
: CYCLES_LONG);
// keep an eye on the length of bitnum
reg [4:0] bitnum = 0; // 0 .. 23
reg [CYCLES_WIDTH-1:0] counter = 0; // 0 .. CYCLES_RET
reg [23:0] bitstream_int; // internal copy of the txed LED data
reg [0:0] idle = 0;
always @(posedge clk) begin
if (!resetn) begin
// reset state
counter <= 0;
bitstream_read <= 0;
bitnum <= 0;
end else begin
bitstream_read <= 0; // default value
if (counter != 0) begin
// wait state: consume the desired time
counter <= counter - 1;
end else begin
if (!bitnum && !ws2812b_data) begin
if (bitstream_available) begin
// communicate to "caller"
bitstream_read <= 1; // state bitstream to be read for this cycle
bitstream_int <= bitstream; // get internal copy of bitstream
// start output
ws2812b_data <= 1;
bitnum <= 24;
counter <= bitstream[23] ? CYCLES_LONG : CYCLES_SHORT;
idle <= 0;
end else begin
// no new bitstream available -> trigger output of ws2812b LEDs
ws2812b_data <= 0;
counter <= CYCLES_RET; // cheaper logic
// counter <= idle ? 0 : CYCLES_RET; // immidiate reaction to bitstream available
idle <= 1;
end
end else if (bitnum) begin
// output the remainder of bitstream
if (!ws2812b_data) begin
ws2812b_data <= 1;
counter <= bitstream_int[23] ? CYCLES_LONG : CYCLES_SHORT;
end else begin
ws2812b_data <= 0;
counter <= (bitstream_int[23]) ? CYCLES_SHORT : CYCLES_LONG;
bitstream_int <= {bitstream_int[22:0], bitstream_int[23]};
bitnum <= bitnum - 1;
end
end
end
end
end
// assign debug_info = {bitstream_read, bitstream_available, resetn, clk};
assign debug_info = {ws2812b_data, bitstream_read, bitstream_available, clk};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char ar[1002][1002]; int n, m, i, j, count, ar1[1002]; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) { scanf( %s , ar[i]); } for (i = 0; i < m; i++) { ar1[i] = 1; } for (i = 1; i < n; i++) { for (j = 0; j < m; j++) { if (ar1[j] == 1) { if (ar[i][j] < ar[i - 1][j]) { ar1[j] = 0; i = 0; break; } if (ar[i][j] > ar[i - 1][j]) { break; } } } } count = 0; for (i = 0; i < m; i++) { count += 1 - ar1[i]; } printf( %d n , count); return 0; }
|
#include <bits/stdc++.h> int A[50], B[50]; int main() { int N, M, i, j, Max, now, Cnt; while (scanf( %d , &N) != EOF) { for (i = 0; i < N; ++i) { scanf( %d , &A[i]); } scanf( %d , &M); for (i = 0; i < M; ++i) { scanf( %d , &B[i]); } for (Max = i = 0; i < N; ++i) { for (j = 0; j < M; ++j) { now = B[j] / A[i]; if (now * A[i] == B[j] && Max < now) { Max = now; } } } for (Cnt = i = 0; i < N; ++i) { for (j = 0; j < M; ++j) { now = B[j] / A[i]; if (now * A[i] == B[j] && Max == now) { ++Cnt; } } } printf( %d n , Cnt); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; bool flag[maxn]; int phi[maxn]; vector<int> prime; vector<int> fin[6][maxn]; int a[10][10], num; void get_prime_phi() { phi[1] = 1; for (int i = 2; i < 1e5; i++) { if (!flag[i]) { prime.push_back(i); phi[i] = i - 1; } int top = prime.size(); for (int j = 0; j < top && i * prime[j] < 1e5; j++) { flag[i * prime[j]] = 1; if (i % prime[j]) phi[i * prime[j]] = phi[i] * (prime[j] - 1); else { phi[i * prime[j]] = phi[i] * prime[j]; break; } } } } void init() { int si = prime.size(); for (int i = 0; i < si; i++) { int x = prime[i]; for (int j = 1; j <= 5; j++) { fin[j][x / 10].push_back(prime[i]); x /= 10; } } } int dfs(int x) { int ans = 0; int tem = 0, tt = num - x; for (int i = 0; i < x; i++) tem = tem * 10 + a[x][i]; int si = fin[tt][tem].size(); if (x == num - 1) return si; for (int i = 0; i < si; i++) { int xx = fin[tt][tem][i]; for (int j = num - 1; j >= x; j--) { a[x][j] = xx % 10; xx /= 10; } for (int j = x + 1; j < num; j++) a[j][x] = a[x][j]; ans += dfs(x + 1); } return ans; } int main() { get_prime_phi(); init(); int cas, n; cin >> cas; while (cas--) { memset(a, 0, sizeof(a)); scanf( %d , &n); int x = n; num = 0; while (x) { num++; x /= 10; } x = n; for (int i = 0; i < num; i++) { a[0][num - 1 - i] = a[num - 1 - i][0] = x % 10; x /= 10; } printf( %d n , dfs(1)); } }
|
#include <bits/stdc++.h> using namespace std; inline long long rd() { register long long x = 0; register bool f = 0; register char c = getchar(); while (!isdigit(c)) { if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) { x = x * 10 + (c ^ 48); c = getchar(); } return f ? -x : x; } int n, a[200010], bit[31]; inline int insert(int x) { for (register int i = 30; ~i; --i) { if (x & (1 << i)) { if (!bit[i]) { bit[i] = x; return 1; } x ^= bit[i]; } } return 0; } int main() { n = rd(); for (register int i = 1; i <= n; ++i) a[i] = rd() ^ a[i - 1]; if (!a[n]) { puts( -1 ); return 0; } int ans = insert(a[n]); for (register int i = n - 1; i; --i) ans += insert(a[i]); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); if (n == 1) { cout << 0 << endl; return 0; } int a[n + 2], cnt = n - 1; for (int i = 2; i <= n; i++) { a[i] = i; } for (int i = 2; i < n; i++) { for (int j = i + 1; j <= n; j++) { if (a[j] == 0) continue; if (i * j <= n && j % i != 0) { a[i * j] = 0; cnt--; } } } cnt = 0; for (int i = 2; i <= n; i++) { if (a[i] != 0) { cnt++; } } cout << cnt << endl; for (int i = 2; i <= n; i++) { if (a[i] != 0) { cout << a[i] << ; } } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int now[15][3], ans[15][3], nA, nB, nC, minN = 12, cnt, t[13]; void dfs(int a, int b, int c, int num, int jw, int cou, bool ifA, bool ifB) { if (!a && !b && !c && !jw) { minN = num; cnt = cou; memcpy(ans, now, sizeof(now)); return; } if (a % 10 + b % 10 - c % 10 + jw == 0 && c) dfs(a / 10, b / 10, c / 10, num, 0, cou + 1, a ? 0 : 1, b ? 0 : 1); else if (a % 10 + b % 10 - c % 10 + jw == 10 && c) dfs(a / 10, b / 10, c / 10, num, 1, cou + 1, a ? 0 : 1, b ? 0 : 1); else { if (minN - ++num <= 0) return; now[num][2] = ++cou; if (!ifA && c) { now[num][0] = 1; now[num][1] = (c % 10 - b % 10 - jw + 10) % 10; bool f = ifB; if (!b) ifB = 1; dfs(a, b / 10, c / 10, num, (now[num][1] + b % 10 + jw - c % 10) / 10, cou, ifA, ifB); ifB = f; } if (!ifB && c) { now[num][0] = 2; now[num][1] = (c % 10 - a % 10 + 10 - jw) % 10; bool f = ifA; if (a == 0) ifA = 1; dfs(a / 10, b, c / 10, num, (now[num][1] + a % 10 + jw - c % 10) / 10, cou, ifA, ifB); ifA = f; } now[num][0] = 3; now[num][1] = (a % 10 + b % 10 + jw) % 10; if (!a) ifA = 1; if (!b) ifB = 1; dfs(a / 10, b / 10, c, num, (a % 10 + b % 10 + jw - now[num][1]) / 10, cou, ifA, ifB); } } int main() { int a, b, c; bool f; scanf( %d+%d=%d , &a, &b, &c); dfs(a, b, c, 0, 0, 0, 0, 0); int p = 1; while (p <= minN && ans[p][0] - 1) p++; for (int i = 1; i <= cnt; i++) if (p <= minN && ans[p][2] == i) { t[i] = ans[p++][1]; while (p <= minN && ans[p][0] - 1) p++; } else { t[i] = a % 10; a /= 10; } f = 0; for (int i = cnt; i; i--) if (f || t[i]) { putchar(t[i] + 0 ); f = 1; } putchar( + ); p = 1; while (p <= minN && ans[p][0] - 2) p++; for (int i = 1; i <= cnt; i++) if (p <= minN && ans[p][2] == i) { t[i] = ans[p++][1]; while (p <= minN && ans[p][0] - 2) p++; } else { t[i] = b % 10; b /= 10; } f = 0; for (int i = cnt; i; i--) if (f || t[i]) { putchar(t[i] + 0 ); f = 1; } putchar( = ); p = 1; while (p <= minN && ans[p][0] - 3) p++; for (int i = 1; i <= cnt; i++) if (p <= minN && ans[p][2] == i) { t[i] = ans[p][1]; p++; while (p <= minN && ans[p][0] - 3) p++; } else { t[i] = c % 10; c /= 10; } f = 0; for (int i = cnt; i; i--) if (f || t[i]) { putchar(t[i] + 0 ); f = 1; } return 0; }
|
module top_string(char, clk, new, btn1, string, completeOut, changeOut);
input [6:0] char;
input clk, new, btn1;
output [76:0] string;
output completeOut, changeOut;
wire complete, change;
wire wCenter, wCene, wCvirgul, wCdelete, wCnum, wDelete, wAdd, wCcounter, wAddEnhe, wLoad, wEnter, wVirgul, wchangeVirgul;
wire [6:0] wMuxOut;
wire [3:0] wCounter;
control control1 (.clk(clk), .cEnter(wCenter), .cEne(wCene), .cDelete(wCdelete), .cCounter(wCcounter), .new(new), .reset(btn1), .cNum(wCnum), .complete(complete), .enter(wEnter), .delete(wDelete), .add(wAdd), .load(wLoad), .addEnhe(wAddEnhe), .change(change), .virgul(wVirgul), .changeVirgul(wchangeVirgul));
charComp charComp1 (.enter(wEnter), .char(char), .cEnter(wCenter), .cEne(wCene), .cVirgul(wCvirgul), .cDelete(wCdelete), .cNum(wCnum));
countComp countComp1 (.counter(wCounter), .cCounter(wCcounter));
counter counter1 (.delete(wDelete), .add(wAdd), .clk(clk), .counter(wCounter), .load(wLoad));
mux mux1 (.char(char), .addEnhe(wAddEnhe), .muxOut(wMuxOut));
shiftString shiftString1 (.load(wLoad), .add(wAdd), .clk(clk), .delete(wDelete), .muxOut(wMuxOut), .string(string));
memory memory1 (.cEnter(wCenter), .cVirgul(wCvirgul), .clk(clk), .enter(wEnter), .virgul(wVirgul), .load(wLoad), .changeVirgul(wchangeVirgul), .addEnhe(wAddEnhe));
adapter adapter1 (.change(change), .complete(complete), .clk(clk), .changeOut(changeOut), .completeOut(completeOut));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_PP_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* added stress test by Zeus Gomez Marmolejo <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
//`define ENABLE_VCD
//`define TEST_SOMETRANSFERS
//`define TEST_RANDOMTRANSFERS
module tb_hpdmc;
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire [1:0] sdram_dqm;
wire [11:0] sdram_adr;
wire [1:0] sdram_ba;
wire [15:0] sdram_dq;
// Module instances
mt48lc16m16a2 #(
.addr_bits (12),
.data_bits (16),
.col_bits (8),
//.mem_sizes ()
.mem_sizes (256)
) m (
.Dq (sdram_dq),
.Addr (sdram_adr),
.Ba (sdram_ba),
.Clk (clk),
.Cke (sdram_cke),
.Cs_n (sdram_cs_n),
.Ras_n (sdram_ras_n),
.Cas_n (sdram_cas_n),
.We_n (sdram_we_n),
.Dqm (sdram_dqm)
);
reg rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [22:0] fml_adr;
reg fml_stb;
reg fml_we;
wire fml_ack;
reg [1:0] fml_sel;
reg [15:0] fml_di;
wire [15:0] fml_do;
hpdmc dut(
.sys_clk(clk),
.sys_rst(rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dqm(sdram_dqm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
for(i=0;i<n;i=i+1)
waitclock;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
real reads;
real read_clocks;
task readburst;
input [31:0] address;
integer i;
begin
$display("READ [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b0;
i = 0;
while(~fml_ack) begin
i = i+1;
waitclock;
end
$display("%t: Memory Read : %x=%x acked in %d clocks", $time, address, fml_do, i);
fml_stb = 1'b0;
reads = reads + 1;
read_clocks = read_clocks + i;
for(i=0;i<3;i=i+1) begin
waitclock;
$display("%t: (R burst continuing) %x", $time, fml_do);
end
waitclock;
end
endtask
real writes;
real write_clocks;
task writeburst;
input [31:0] address;
integer i;
begin
$display("WRITE [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b1;
fml_sel = 8'hff;
fml_di = {$random, $random};
i = 0;
while(~fml_ack) begin
i = i+1;
waitclock;
end
$display("%t: Memory Write : %x=%x acked in %d clocks", $time, address, fml_di, i);
fml_stb = 1'b0;
writes = writes + 1;
write_clocks = write_clocks + i;
for(i=0;i<3;i=i+1) begin
waitclock;
fml_di = {$random, $random};
$display("%t: (W burst continuing) %x", $time, fml_di);
end
waitclock;
end
endtask
reg [5:0] i;
always
begin
i = 6'd0;
while (1'b1) begin
waitclock;
#1;
if (fml_ack) begin
i = i + 6'd1;
fml_adr = {17'h0, i};
end
end
end
always @(posedge clk)
fml_di <= $random;
task interleave;
input [31:0] iterations;
integer j;
begin
fml_stb = 1'b1;
for(j = 0; j<iterations; j=j+1)
begin
$display ("iteration %d of %d", j, iterations);
// write
fml_we = 1'b1;
waitclock;
while(~fml_ack) begin
waitclock;
end
// read
fml_we = 1'b0;
waitclock;
while(~fml_ack) begin
waitclock;
end
// write
fml_we = 1'b1;
waitclock;
while(~fml_ack) begin
waitclock;
end
// write
fml_we = 1'b1;
waitclock;
while(~fml_ack) begin
waitclock;
end
// read
fml_we = 1'b0;
waitclock;
while(~fml_ack) begin
waitclock;
end
// read
fml_we = 1'b0;
waitclock;
while(~fml_ack) begin
waitclock;
end
end
fml_stb = 1'b0;
waitclock;
end
endtask
integer n, addr;
always begin
`ifdef ENABLE_VCD
$dumpfile("hpdmc.vcd");
`endif
/* Reset / Initialize our logic */
rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_adr = 26'd0;
fml_di = 64'd0;
fml_sel = 8'd0;
fml_stb = 1'b0;
fml_we = 1'b0;
waitclock;
rst = 1'b0;
waitclock;
/* SDRAM initialization sequence. */
/* The controller already comes up in Bypass mode with CKE disabled. */
/* Wait 200us */
#200000;
/* Bring CKE high */
csrwrite(32'h00, 32'h07);
/* Precharge All:
* CS=1
* WE=1
* CAS=0
* RAS=1
* A=A10
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Auto Refresh
* CS=1
* WE=0
* CAS=1
* RAS=1
* A=Don't Care
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Auto Refresh */
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Load Mode Register, DLL enabled */
csrwrite(32'h04, 32'b00__000000_010_0_011__1111);
waitnclock(200);
/* SDRAM initialization completed */
`ifdef ENABLE_VCD
/* Now, we want to know what the controller will send to the SDRAM chips */
$dumpvars(0, dut);
`endif
/* Bring up the controller ! */
csrwrite(32'h00, 32'h04);
waitnclock(8);
`ifdef TEST_SOMETRANSFERS
/*
* Try some transfers.
*/
writeburst(32'h00);
writeburst(32'h20);
//writeburst(32'h40);
readburst(32'h00);
readburst(32'h20);
/*readburst(32'h40);
writeburst(32'h40);
readburst(32'h40);*/
`endif
fml_sel = 2'b11;
interleave(5);
`ifdef TEST_RANDOMTRANSFERS
writes = 0;
write_clocks = 0;
reads = 0;
read_clocks = 0;
for(n=0;n<500;n=n+1) begin
addr = $random;
if($random > 32'h80000000) begin
writeburst(addr);
//writeburst(addr+32'h20);
//writeburst(addr+32'h40);
end else begin
readburst(addr);
//readburst(addr+32'h20);
//readburst(addr+32'h40);
end
end
$display("");
$display("=======================================================");
$display(" Tested: %.0f reads, %.0f writes ", reads, writes);
$display("=======================================================");
$display(" Average read latency: %f cycles", read_clocks/reads);
$display(" Average write latency: %f cycles", write_clocks/writes);
$display("=======================================================");
$display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100);
$display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100);
$display("=======================================================");
`endif
// $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); printf( %d n , n / 2 - (n % 2 ? 0 : 1)); return 0; }
|
#include <bits/stdc++.h> using namespace std; auto SEED = chrono::steady_clock::now().time_since_epoch().count(); mt19937 rng(SEED); int main() { int n, k; cin >> n >> k; int dist[n][n]; for (int i = (0); i < (n); i++) { for (int j = (0); j < (n); j++) { cin >> dist[i][j]; } } int t = 0; int color[n]; long long int ans = 1ll << 60; while (t < 5000) { for (int i = (0); i < (n); i++) { int tt = uniform_int_distribution<int>(1, n)(rng); color[i] = tt & 1; } long long int dp[n][k]; for (int j = (0); j < (k + 1); j++) { for (int i = (0); i < (n); i++) { if (j) { dp[i][j] = 1ll << 60; for (int l = (0); l < (n); l++) { if (color[i] + color[l] == 1) { dp[i][j] = min(dp[i][j], dp[l][j - 1] + dist[l][i]); } } } else { if (i) dp[i][j] = 1ll << 60; else dp[i][j] = 0; } } } ans = min(ans, dp[0][k]); t++; } cout << ans << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_delay_cntrl #(
// parameters
parameter DISABLE = 0,
parameter INIT_DELAY = 0,
parameter DATA_WIDTH = 8,
parameter BASE_ADDRESS = 6'h02) (
// delay interface
input delay_clk,
output delay_rst,
input delay_locked,
// io interface
output [(DATA_WIDTH-1):0] up_dld,
output [((DATA_WIDTH*5)-1):0] up_dwdata,
input [((DATA_WIDTH*5)-1):0] up_drdata,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
generate
if (DISABLE == 1) begin
assign up_wack = 1'd0;
assign up_rack = 1'd0;
assign up_rdata = 32'd0;
assign up_dld = 'd0;
assign up_dwdata = 'd0;
assign delay_rst = 1'd0;
end else begin
// internal registers
reg up_preset = 'd0;
reg up_wack_int = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
reg up_dlocked_m1 = 'd0;
reg up_dlocked_m2 = 'd0;
reg up_dlocked_m3 = 'd0;
reg up_dlocked = 'd0;
reg [(DATA_WIDTH-1):0] up_dld_int = 'd0;
reg [((DATA_WIDTH*5)-1):0] up_dwdata_int = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 4:0] up_rdata_s;
wire [(DATA_WIDTH-1):0] up_drdata4_s;
wire [(DATA_WIDTH-1):0] up_drdata3_s;
wire [(DATA_WIDTH-1):0] up_drdata2_s;
wire [(DATA_WIDTH-1):0] up_drdata1_s;
wire [(DATA_WIDTH-1):0] up_drdata0_s;
wire [(DATA_WIDTH-1):0] up_dld_s;
wire [((DATA_WIDTH*5)-1):0] up_dwdata_s;
wire [(DATA_WIDTH-1):0] up_dinit_s;
wire [((DATA_WIDTH*5)-1):0] up_dinitdata_s;
wire delay_rst_s;
// variables
genvar n;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0;
assign up_rdata_s[4] = | up_drdata4_s;
assign up_rdata_s[3] = | up_drdata3_s;
assign up_rdata_s[2] = | up_drdata2_s;
assign up_rdata_s[1] = | up_drdata1_s;
assign up_rdata_s[0] = | up_drdata0_s;
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_drd
assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
end
// processor interface
assign up_wack = up_wack_int;
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_preset <= 1'd1;
up_wack_int <= 'd0;
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
up_dlocked_m1 <= 'd0;
up_dlocked_m2 <= 'd0;
up_dlocked_m3 <= 'd0;
up_dlocked <= 'd0;
end else begin
up_preset <= 1'd0;
up_wack_int <= up_wreq_s;
up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
if (up_dlocked == 1'b0) begin
up_rdata_int <= 32'hffffffff;
end else begin
up_rdata_int <= {27'd0, up_rdata_s};
end
end else begin
up_rdata_int <= 32'd0;
end
up_dlocked_m1 <= delay_locked;
up_dlocked_m2 <= up_dlocked_m1;
up_dlocked_m3 <= up_dlocked_m2;
up_dlocked <= up_dlocked_m3;
end
end
// init delay values (after delay locked)
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dinit
assign up_dinit_s[n] = up_dlocked_m2 & ~up_dlocked_m3;
assign up_dinitdata_s[((n*5)+4):(n*5)] = INIT_DELAY;
end
// write does not hold- read back what goes into effect.
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ?
up_wdata[4:0] : up_dwdata_int[((n*5)+4):(n*5)];
end
assign up_dld = up_dld_int;
assign up_dwdata = up_dwdata_int;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_dld_int <= 'd0;
up_dwdata_int <= 'd0;
end else begin
up_dld_int <= up_dld_s | up_dinit_s;
if ((up_dlocked_m2 == 1'b1) && (up_dlocked_m3 == 1'b0)) begin
up_dwdata_int <= up_dinitdata_s;
end else if (up_wreq_s == 1'b1) begin
up_dwdata_int <= up_dwdata_s;
end
end
end
// resets
assign delay_rst = delay_rst_s;
ad_rst i_delay_rst_reg (
.rst_async (up_preset),
.clk (delay_clk),
.rstn (),
.rst (delay_rst_s));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 22 02:25:26 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/quadencoder/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.v
// Design : dcfifo_32in_32out_16kb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_16kb(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[1:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [1:0]wr_data_count;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module blk_mem_gen_arb (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [15 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [15 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [11 : 0] doutb;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("blk_mem_gen_arb.mif"),
.C_INIT_FILE("blk_mem_gen_arb.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(65536),
.C_READ_DEPTH_A(65536),
.C_ADDRA_WIDTH(16),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(65536),
.C_READ_DEPTH_B(65536),
.C_ADDRB_WIDTH(16),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("22"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 18.3292 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(12'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int a[25], b[25]; int dp[1 << 24]; int main() { int n, k; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); scanf( %d , &k); for (int i = 1; i <= k; i++) scanf( %d , &b[i]); dp[0] = 1; for (int i = 1; i < (1 << n); i++) { int sum = 0, ans = 0; for (int j = 0; j < n; j++) { if ((i >> j) & 1) { sum += a[j]; ans = (ans + dp[i ^ (1 << j)]) % mod; if (sum > 1e9) sum = 1e9 + 1; } } bool ok = 1; for (int j = 1; j <= k; j++) { if (sum == b[j]) ok = 0; } if (!ok) continue; dp[i] = (dp[i] + ans) % mod; } printf( %d n , dp[(1 << n) - 1]); }
|
#include <bits/stdc++.h> using namespace std; string s; int main() { getline(cin, s); int n, flag = 0; n = s.length(); for (int i = n; i >= 0; i--) { if ((s[i] >= a && s[i] <= z ) || (s[i] >= A && s[i] <= Z )) { if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u || s[i] == y || s[i] == A || s[i] == E || s[i] == I || s[i] == O || s[i] == U || s[i] == Y ) { flag = 1; } break; } } if (flag) { cout << YES n ; } else { cout << NO n ; } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_avm_to_ic #(
parameter integer DATA_W = 256,
parameter integer WRITEDATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter ADDR_SHIFT=1 // shift the address?
)
(
// AVM interface
input logic avm_read,
input logic avm_write,
input logic [WRITEDATA_W-1:0] avm_writedata,
input logic [BURSTCOUNT_W-1:0] avm_burstcount,
input logic [ADDRESS_W-1:0] avm_address,
input logic [BYTEENA_W-1:0] avm_byteenable,
output logic avm_waitrequest,
output logic avm_readdatavalid,
output logic [WRITEDATA_W-1:0] avm_readdata,
output logic avm_writeack, // not a true Avalon signal
// IC interface
output logic ic_arb_request,
output logic ic_arb_read,
output logic ic_arb_write,
output logic [WRITEDATA_W-1:0] ic_arb_writedata,
output logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
output logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
output logic [BYTEENA_W-1:0] ic_arb_byteenable,
output logic [ID_W-1:0] ic_arb_id,
input logic ic_arb_stall,
input logic ic_wrp_ack,
input logic ic_rrp_datavalid,
input logic [WRITEDATA_W-1:0] ic_rrp_data
);
// The logic for ic_arb_request (below) makes a MAJOR ASSUMPTION:
// avm_write will never be deasserted in the MIDDLE of a write burst
// (read bursts are fine since they are single cycle requests)
//
// For proper burst functionality, ic_arb_request must remain asserted
// for the ENTIRE duration of a burst request, otherwise the burst may be
// interrupted and lead to all sorts of chaos. At this time, LSUs do not
// deassert avm_write in the middle of a write burst, so this assumption
// is valid.
//
// If there comes a time when this assumption is no longer valid,
// logic needs to be added to detect when a burst begins/ends.
assign ic_arb_request = avm_read | avm_write;
assign ic_arb_read = avm_read;
assign ic_arb_write = avm_write;
assign ic_arb_writedata = avm_writedata;
assign ic_arb_burstcount = avm_burstcount;
generate
if(ADDR_SHIFT==1)
begin
assign ic_arb_address = avm_address[ADDRESS_W-1:$clog2(DATA_W / 8)];
end
else
begin
assign ic_arb_address = avm_address[ADDRESS_W-$clog2(DATA_W / 8)-1:0];
end
endgenerate
assign ic_arb_byteenable = avm_byteenable;
assign avm_waitrequest = ic_arb_stall;
assign avm_readdatavalid = ic_rrp_datavalid;
assign avm_readdata = ic_rrp_data;
assign avm_writeack = ic_wrp_ack;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void print(T a) { for (auto i = a.begin(); i != a.end(); i++) cout << *i << ; cout << endl; } bool isVowel(char c) { if (c == a || c == e || c == i || c == o || c == u ) return true; return false; } void sync() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } vector<long long int> G[1000000]; map<long long int, bool> ck; bool dfs(long long int a, long long int b) { if (a == b) return true; ck[a] = true; for (long long int j : G[a]) { if (ck[j] == true) continue; bool d = dfs(j, b); if (d == true) return true; } return false; } int main() { sync(); long long int t; cin >> t; long long int j = 0; vector<pair<long long int, long long int> > edges; for (long long int testcase = 1; testcase <= t; testcase++) { long long int a, b, c; cin >> a >> b >> c; if (a == 2) { b--, c--; ck.clear(); bool d = dfs(b, c); if (d == true) cout << YES << endl; else cout << NO << endl; } else { edges.push_back({b, c}); if (j == 0) { } else { for (long long int i = 0; i < j; i++) { long long int x1 = edges[i].first; long long int y1 = edges[i].second; if ((x1 > b && x1 < c) || (y1 > b && y1 < c)) { G[i].push_back(j); } if ((b > x1 && b < y1) || (c > x1 && c < y1)) { G[j].push_back(i); } } } j++; } } }
|
`timescale 1ns/10ps
module soc_system_pll_stream(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("65.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("130.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct segtree { vector<vector<int>> t; vector<int> d; int h, n, sz; inline void build_node(const int& x) { for (int j = 0; j < 26; ++j) { t[x][j] = t[x << 1][j] + t[x << 1 | 1][j]; } } inline void build(int x) { for (x /= 2; x > 0; x /= 2) { build_node(x); } } segtree(const string& s) { sz = s.size(); h = sizeof(int) * 8 - __builtin_clz(sz); n = 1 << h; d = vector<int>(n << 1, 0); t = vector<vector<int>>(n << 1, vector<int>(26, 0)); for (int i = 0; i < sz; ++i) { ++t[i + n][s[i] - a ]; } for (int i = n - 1; i > 0; --i) { build_node(i); } } void apply(int x, int v) { if (x < n) { d[x] = v; } } void fill_nodes(const vector<int>& ind, vector<int> char_count, int dir) { for (const int& x : ind) { for (int i = 0; i < 26; ++i) { t[x][i] = 0; } } int ch_type = (dir == 1 ? 0 : 25); for (int i = (dir == 1 ? 0 : 0); i < ind.size(); ++i) { int x = ind[i]; int my_sz = 1 << (h - (sizeof(int) * 8 - __builtin_clz(x)) + 1); int have = 0; for (; have < my_sz; (dir == 1 ? ++ch_type : --ch_type)) { int take = min(my_sz - have, char_count[ch_type]); t[x][ch_type] += take; char_count[ch_type] -= take; have += take; if (have == my_sz) break; } } } void sort_nodes(const vector<int>& ind, int dir) { vector<int> char_count(26, 0); for (const int& x : ind) { for (int i = 0; i < 26; ++i) { char_count[i] += t[x][i]; } } fill_nodes(ind, char_count, dir); } void push_node(int x) { if (d[x] != 0) { fill_nodes(vector<int>({x << 1, x << 1 | 1}), t[x], d[x]); apply(x << 1, d[x]); apply(x << 1 | 1, d[x]); d[x] = 0; } } void push(int x) { for (int s = h; s > 0; --s) { int i = x >> s; if (d[i] != 0) { push_node(i); } } } void set(int l, int r, int dir) { int l0 = l + n; int r0 = r + n; push(l0); push(r0 - 1); vector<int> front, back; for (l += n, r += n; l < r; l /= 2, r /= 2) { if (l % 2) { front.push_back(l); apply(l, dir); ++l; } if (r % 2) { --r; back.push_back(r); apply(r, dir); } } reverse(back.begin(), back.end()); front.insert(front.end(), back.begin(), back.end()); sort_nodes(front, dir); push(l0); push(r0 - 1); build(l0); build(r0 - 1); } string to_string() { for (int i = 1; i < n; ++i) { push_node(i); } static char cstr[100010]; for (int i = 0; i < sz; ++i) { for (int j = 0; j < 26; ++j) { if (t[i + n][j] != 0) { cstr[i] = j + a ; } } } cstr[sz] = 0; return string(cstr); } }; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int N, Q; cin >> N >> Q; string s; cin >> s; segtree st(s); for (int qq = 0; qq < Q; ++qq) { int i, j, k; cin >> i >> j >> k; st.set(i - 1, j, (k == 1 ? 1 : -1)); } cout << st.to_string() << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_TB_V
`define SKY130_FD_SC_LS__DECAP_TB_V
/**
* decap: Decoupling capacitance filler.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__decap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_TB_V
|
#include <bits/stdc++.h> using namespace std; long long N, M, x, y, K, ml, T, ans; long long f[1000000], s[1000000]; const long long md = 1e9 + 7; const long long MAXN = 1e5 + 2; string in; int main() { cin >> N >> K; f[0] = 1; for (int i = 1; i <= MAXN; i++) { f[i] = f[i - 1]; if (i >= K) f[i] = (f[i] % md + f[i - K] % md) % md; } s[0] = 0; for (int i = 1; i <= MAXN; i++) s[i] = (s[i - 1] % md + f[i] % md) % md; for (int i = 0; i < N; i++) { cin >> x >> y; ans = (s[y] - s[x - 1] + md) % md; cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int64_t MOD = 1e9 + 7; void add(int64_t& a, int64_t b) { a = (a + b) % MOD; } int nth_bit(int64_t num, int n) { return (num >> n) & 1; } const int SZ = 14 * 16; void matmul(int64_t A[SZ][SZ], int64_t B[SZ][SZ]) { int64_t ret[SZ][SZ] = {0}; for (int i = 0; i < SZ; i++) for (int j = 0; j < SZ; j++) for (int k = 0; k < SZ; k++) add(ret[i][j], A[i][k] * B[k][j]); for (int i = 0; i < SZ; i++) for (int j = 0; j < SZ; j++) A[i][j] = ret[i][j]; } int main() { int N, K, M; cin >> N >> K >> M; static int64_t A[SZ][SZ]; for (int j = 0; j <= K; j++) for (int bits = 0; bits < 16; bits++) { int pos = 1; for (int k = 0; k < M; k++) if (nth_bit(bits, k)) pos++; add(A[(j + 1) * 16 + (bits << 1) % 16 + 1][j * 16 + bits], pos); add(A[j * 16 + (bits << 1) % 16][j * 16 + bits], 1); } static int64_t B[SZ][SZ]; for (int i = 0; i < SZ; i++) B[i][i] = 1; while (N > 0) { if (N % 2) matmul(B, A); matmul(A, A); N /= 2; } int64_t ans = 0; for (int bits = 0; bits < 16; bits++) add(ans, B[K * 16 + bits][0]); cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_BEHAVIORAL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_BEHAVIORAL_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="adder,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=150,HLS_SYN_LUT=264}" *)
module adder (
s_axi_AXI_CTRL_AWVALID,
s_axi_AXI_CTRL_AWREADY,
s_axi_AXI_CTRL_AWADDR,
s_axi_AXI_CTRL_WVALID,
s_axi_AXI_CTRL_WREADY,
s_axi_AXI_CTRL_WDATA,
s_axi_AXI_CTRL_WSTRB,
s_axi_AXI_CTRL_ARVALID,
s_axi_AXI_CTRL_ARREADY,
s_axi_AXI_CTRL_ARADDR,
s_axi_AXI_CTRL_RVALID,
s_axi_AXI_CTRL_RREADY,
s_axi_AXI_CTRL_RDATA,
s_axi_AXI_CTRL_RRESP,
s_axi_AXI_CTRL_BVALID,
s_axi_AXI_CTRL_BREADY,
s_axi_AXI_CTRL_BRESP,
ap_clk,
ap_rst_n,
interrupt
);
parameter ap_const_logic_1 = 1'b1;
parameter C_S_AXI_AXI_CTRL_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_AXI_CTRL_ADDR_WIDTH = 6;
parameter C_DATA_WIDTH = 32;
parameter ap_const_logic_0 = 1'b0;
parameter ap_true = 1'b1;
parameter C_S_AXI_AXI_CTRL_WSTRB_WIDTH = (C_S_AXI_AXI_CTRL_DATA_WIDTH / ap_const_int64_8);
parameter C_WSTRB_WIDTH = (C_DATA_WIDTH / ap_const_int64_8);
input s_axi_AXI_CTRL_AWVALID;
output s_axi_AXI_CTRL_AWREADY;
input [C_S_AXI_AXI_CTRL_ADDR_WIDTH - 1 : 0] s_axi_AXI_CTRL_AWADDR;
input s_axi_AXI_CTRL_WVALID;
output s_axi_AXI_CTRL_WREADY;
input [C_S_AXI_AXI_CTRL_DATA_WIDTH - 1 : 0] s_axi_AXI_CTRL_WDATA;
input [C_S_AXI_AXI_CTRL_WSTRB_WIDTH - 1 : 0] s_axi_AXI_CTRL_WSTRB;
input s_axi_AXI_CTRL_ARVALID;
output s_axi_AXI_CTRL_ARREADY;
input [C_S_AXI_AXI_CTRL_ADDR_WIDTH - 1 : 0] s_axi_AXI_CTRL_ARADDR;
output s_axi_AXI_CTRL_RVALID;
input s_axi_AXI_CTRL_RREADY;
output [C_S_AXI_AXI_CTRL_DATA_WIDTH - 1 : 0] s_axi_AXI_CTRL_RDATA;
output [1:0] s_axi_AXI_CTRL_RRESP;
output s_axi_AXI_CTRL_BVALID;
input s_axi_AXI_CTRL_BREADY;
output [1:0] s_axi_AXI_CTRL_BRESP;
input ap_clk;
input ap_rst_n;
output interrupt;
wire ap_start;
wire ap_done;
wire ap_idle;
wire ap_ready;
wire [31:0] a;
wire [31:0] b;
wire [31:0] c;
reg c_ap_vld;
reg ap_rst_n_inv;
wire adder_AXI_CTRL_s_axi_U_ap_dummy_ce;
adder_AXI_CTRL_s_axi #(
.C_ADDR_WIDTH( C_S_AXI_AXI_CTRL_ADDR_WIDTH ),
.C_DATA_WIDTH( C_S_AXI_AXI_CTRL_DATA_WIDTH ))
adder_AXI_CTRL_s_axi_U(
.AWVALID( s_axi_AXI_CTRL_AWVALID ),
.AWREADY( s_axi_AXI_CTRL_AWREADY ),
.AWADDR( s_axi_AXI_CTRL_AWADDR ),
.WVALID( s_axi_AXI_CTRL_WVALID ),
.WREADY( s_axi_AXI_CTRL_WREADY ),
.WDATA( s_axi_AXI_CTRL_WDATA ),
.WSTRB( s_axi_AXI_CTRL_WSTRB ),
.ARVALID( s_axi_AXI_CTRL_ARVALID ),
.ARREADY( s_axi_AXI_CTRL_ARREADY ),
.ARADDR( s_axi_AXI_CTRL_ARADDR ),
.RVALID( s_axi_AXI_CTRL_RVALID ),
.RREADY( s_axi_AXI_CTRL_RREADY ),
.RDATA( s_axi_AXI_CTRL_RDATA ),
.RRESP( s_axi_AXI_CTRL_RRESP ),
.BVALID( s_axi_AXI_CTRL_BVALID ),
.BREADY( s_axi_AXI_CTRL_BREADY ),
.BRESP( s_axi_AXI_CTRL_BRESP ),
.ACLK( ap_clk ),
.ARESET( ap_rst_n_inv ),
.ACLK_EN( adder_AXI_CTRL_s_axi_U_ap_dummy_ce ),
.ap_start( ap_start ),
.interrupt( interrupt ),
.ap_ready( ap_ready ),
.ap_done( ap_done ),
.ap_idle( ap_idle ),
.a( a ),
.b( b ),
.c( c ),
.c_ap_vld( c_ap_vld )
);
/// c_ap_vld assign process. ///
always @ (ap_start)
begin
if (~(ap_start == ap_const_logic_0)) begin
c_ap_vld = ap_const_logic_1;
end else begin
c_ap_vld = ap_const_logic_0;
end
end
assign adder_AXI_CTRL_s_axi_U_ap_dummy_ce = ap_const_logic_1;
assign ap_done = ap_start;
assign ap_idle = ap_const_logic_1;
assign ap_ready = ap_start;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
assign c = (b + a);
endmodule //adder
|
#include <bits/stdc++.h> using namespace std; using lld = signed long long int; lld solve() { lld n, m, k; cin >> n >> m >> k; lld x = n / k; if (m <= x) return m; if (m <= x + (k - 1)) return x - 1; return x - ceil((m - x) / (k - 1.0)); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { cout << solve() << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string colours; cin >> n >> colours; string collec[] = { RGB , RBG , BRG , BGR , GRB , GBR }; int index; int max = INT_MAX; for (int i = 0; i < 6; i++) { int count = 0; for (int j = 0; j < n; j++) { if (colours[j] != collec[i][j % 3]) count++; } if (count < max) { max = count; index = i; } } cout << max << endl; for (int i = 0; i < n; i++) cout << collec[index][i % 3]; }
|
//TODO: make memory do... something... when given an address not in range 0x80020000 -> (0x80020000 + Memory Size)
module mips_memory2 (clk, addr, din, dout, pc, access_size, rw, busy, enable);
parameter MEMSIZE = 1024;
parameter START_ADDR = 32'h8002_0000;
// input
input clk;
input [31:0] addr;
input [31:0] din;
input [2:0] access_size;
input rw; //1 is write, 0 is read
input enable;
// output
output reg busy;
output reg [31:0] dout;
output reg [31:0] pc;
// memory
reg [7:0] mem[0:MEMSIZE];
// local
reg [31:0] reg_cur_addr = 'hffff; // current address
reg [5:0] reg_counter = 0; // number of cycles remaining
reg reg_rw = 0; // rw status
reg [31:0] reg_din = 'hffff; // prev datain
wire wire_busy; // can read new data
wire wire_output; // can access mem
// comb
assign wire_busy = (reg_counter > 1);
assign wire_output = (reg_counter != 0);
// proc
always @(posedge clk)
begin
// update current address
if (wire_busy == 'b1)
begin
reg_cur_addr <= reg_cur_addr + 4;
end
else if (enable == 'b1) // + check address
begin
reg_cur_addr <= addr - START_ADDR;
end
else
begin
reg_cur_addr <= reg_cur_addr; // no change
end
// update counter/rw
if (wire_busy == 'b0 && enable == 'b1)
begin
case (access_size)
3'b000 : reg_counter <= 'd1; // word
3'b001 : reg_counter <= 'd4; // 4 words
3'b010 : reg_counter <= 'd8; // 8 words
3'b011 : reg_counter <= 'd16; // 16 words
3'b100 : reg_counter <= 'd1; // byte
3'b101 : reg_counter <= 'd1; // half word
default : reg_counter <= 'd0;
endcase
reg_rw <= rw;
end
else
begin
reg_counter <= reg_counter == 0 ? 0 : reg_counter - 1;
reg_rw <= reg_rw;
end
// read
if (wire_output == 'b1 && reg_rw == 'b0)
begin
if (access_size == 3'b100)
begin
dout[31:24] <= 0;
dout[23:16] <= 0;
dout[15:8] <= 0;
dout[7:0] <= mem[reg_cur_addr]; // LSB
end
else if (access_size == 3'b101)
begin
dout[31:24] <= 0;
dout[23:16] <= 0;
dout[15:8] <= mem[reg_cur_addr];
dout[7:0] <= mem[reg_cur_addr+1]; // LSB
end
else
begin
dout[31:24] <= mem[reg_cur_addr]; // MSB
dout[23:16] <= mem[reg_cur_addr+1];
dout[15:8] <= mem[reg_cur_addr+2];
dout[7:0] <= mem[reg_cur_addr+3]; // LSB
end
pc <= reg_cur_addr + START_ADDR;
end
else
begin
dout[31:0] <= 'bx;
end
// write
if (wire_output == 'b1 && reg_rw == 'b1)
begin
if (access_size == 3'b100)
begin
mem[reg_cur_addr] <= reg_din[7:0];
end
else if (access_size == 3'b101)
begin
mem[reg_cur_addr] <= reg_din[15:8]; // MSB
mem[reg_cur_addr+1] <= reg_din[7:0];
end
else
begin
mem[reg_cur_addr] <= reg_din[31:24]; // MSB
mem[reg_cur_addr+1] <= reg_din[23:16];
mem[reg_cur_addr+2] <= reg_din[15:8];
mem[reg_cur_addr+3] <= reg_din[7:0]; // LSB
end
end
busy <= wire_busy;
reg_din <= din;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_FUNCTIONAL_V
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/26/07 - Add else to handle x case for o_out (CR 424214).
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 03/19/09 - CR 511590 - Added Z condition handling
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 10/14/09 - CR 535630 - Added DIFF_TERM attribute.
// 05/12/10 - CR 559468 - Added DRC warnings for LVDS_25 bus architectures.
// 12/01/10 - CR 584500 - added attribute SLEW
// 08/08/11 - CR 616816 - ncsim compile error during XIL_TIMING
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/28/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS (O, IO, IOB, I, T);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
localparam MODULE_NAME = "IOBUFDS";
output O;
inout IO, IOB;
input I, T;
wire i_in, io_in, iob_in, t_in;
reg o_out, io_out, iob_out;
reg O_int;
reg DQS_BIAS_BINARY = 1'b0;
wire t_or_gts;
tri0 GTS = glbl.GTS;
assign i_in = I;
assign t_in = T;
assign io_in = IO;
assign iob_in = IOB;
assign t_or_gts = GTS || t_in;
assign IO = t_or_gts ? 1'bz : i_in;
assign IOB = t_or_gts ? 1'bz : ~i_in;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin
$display("DRC Warning : The IOSTANDARD attribute on %s instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", MODULE_NAME, IOSTANDARD);
end
end
always @(io_in or iob_in or DQS_BIAS_BINARY) begin
if (io_in == 1'b1 && iob_in == 1'b0)
o_out <= 1'b1;
else if (io_in == 1'b0 && iob_in == 1'b1)
o_out <= 1'b0;
else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((io_in === 1'bx) || (iob_in == 1'bx))
o_out <= 1'bx;
end
// assign O = (t_in === 1'b0) ? 1'b1 : ((t_in === 1'b1) ? o_out : 1'bx));
assign O = o_out;
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
(T => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; vector<int> cost[4]; vector<vector<int> > G; void solve() { long long n, p, w, d; cin >> n >> p >> w >> d; for (long long y = 0; y < w; y++) { if (p < y * d) continue; long long wx = p - y * d; if (wx % w) continue; long long x = wx / w; if (x + y > n) continue; cout << x << << y << << (n - x - y); return; } cout << -1; } int main() { ios_base::sync_with_stdio(false); int T; solve(); return 0; }
|
`timescale 1ns / 1ps
module Board232 (
input mclk,
input [3:0] btn,
input [7:0] sw,
output [7:0] led,
output reg [6:0] seg,
output reg [3:0] an,
output dp,
output [2:1] OutBlue,
output [2:0] OutGreen,
output [2:0] OutRed,
output HS,
output VS
);
assign dp = 1'b1;
//assign led[7:2]=0;
initial begin
seg[6:0] = 7'b0111111;
an[3:0] = 4'b0000; // 7 segmentte hangi yerler yanacak
end
// YOU SHOULD CHANGE THESE
parameter INT4 = 8'b00000000;
parameter INT3 = 8'b01100110;
parameter INT2= 8'b01100110;
// adjust board clock
reg [26:0] mclk_counter;
initial mclk_counter<= 0;
always @(posedge mclk) mclk_counter = mclk_counter+1;
// select clock : 26->slower | 24->faster
reg clk;
initial clk = 1'b0;
always@(btn[3] or mclk_counter[25] or btn[0])
begin
if(btn[3])
clk = mclk_counter[25];
else
clk = btn[0];
end
reg tmp_digit;
wire READY;
wire [7:0] STREAM;
VBEncoder ins (clk,
INT4,INT3,INT2,sw[7:0],
btn[1],
READY,
led[7:0]
);
always @(mclk_counter[18:17])
begin
case (mclk_counter[18:17])
2'b00:
begin
an = 4'b1110;
tmp_digit = READY;
end
default:
begin
an = 4'b1111;
end
endcase
case (tmp_digit)
4'd0: seg <= ~7'h3F;
4'd1: seg <= ~7'h06;
4'd2: seg <= ~7'h5B;
4'd3: seg <= ~7'h4F;
4'd4: seg <= ~7'h66;
4'd5: seg <= ~7'h6D;
4'd6: seg <= ~7'h7D;
4'd7: seg <= ~7'h07;
4'd8: seg <= ~7'h7F;
4'd9: seg <= ~7'h6F;
4'd10: seg <= ~7'h77;
4'd11: seg <= ~7'h7C;
4'd12: seg <= ~7'h39;
4'd13: seg <= ~7'h5E;
4'd14: seg <= ~7'h79;
4'd15: seg <= ~7'h71;
default: seg <= ~7'b0000000;
endcase
end
// VGA
assign OutBlue = 0;
assign OutGreen = 0;
assign OutRed = 0;
assign HS = 0;
assign VS = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int ask(string s) { cout << ? << s << endl; fflush(stdout); int x; cin >> x; return x; } int main() { int n; scanf( %d , &n); string s(n, 0 ); int c = ask(s); s[0] = 1 ; int a0; int d = ask(s); int pos1 = -1, pos0 = -1; int zo = 0; if (d < c) { pos1 = 0; zo = 1; } else { pos0 = 0; } if (zo == 1) { a0 = ask(string(n, 1 )); } else { a0 = c; } int le(0), ri(n - 2); while (le != ri) { string s; int mid((le + ri + 1) / 2); for (int i(0); i <= mid; i++) s.push_back( 1 ^ zo); for (int i(mid + 1); i < n; i++) s.push_back( 0 ^ zo); if (ask(s) == a0 + mid + 1) { le = mid; } else { ri = mid - 1; } } if (pos1 == -1) pos1 = le + 1; else pos0 = le + 1; printf( ! %d %d n , 1 + pos0, 1 + pos1); fflush(stdout); }
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long ans = 1; while (b > 0) { if (b & 1) { ans = (ans * a); } a = (a * a); b >>= 1; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a, b, i, l = 0, u; cin >> a >> b; if (a > b) { cout << -1 ; return 0; } if (a == 0 && b == 0) { cout << 0 ; return 0; } if (a == 0 && b % 2 == 0) { cout << 2 n << b / 2 << << b / 2; return 0; } if (a == b) { cout << 1 << n << a; return 0; } if (a % 2 != 0 && b % 2 != 0) { long long d = b - a; if (d == 0) { cout << 1 n << 1; return 0; } if ((a & (d / 2)) == 0) { cout << 2 << n ; cout << a + d / 2 << ; cout << d / 2; return 0; } cout << 3 << n ; cout << a << ; cout << d / 2 << << d / 2; return 0; } if (a % 2 == 0 && b % 2 == 0) { long long d = a; vector<int> v; while (d > 0) { v.push_back(d & 1); d = d >> 1; } while (v.size() <= 60) { v.push_back(0); } for (i = 60; i >= 0; i--) { if (v[i] == 0) { u = power(2, i); if (a + l + 2 * u == b) break; if (a + l + 2 * u < b) { l = l + 2 * u; } } } if (((a + l / 2 + u) ^ (l / 2 + u)) != a) { long long d = b - a; cout << 3 << n ; cout << a << ; cout << d / 2 << << d / 2; return 0; } cout << 2 n ; cout << a + l / 2 + u << << l / 2 + u << n ; return 0; } cout << -1 ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:31:59 04/23/2016
// Design Name:
// Module Name: cuckooRinging
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cuckooRinging(
output buzzer,
input isSameTime,
input clk,
input yoodRong,
input onOffAlarm
);
assign ringAble = isSameTime & (!onOffAlarm);
reg ringIng;
always @(posedge ringAble, negedge yoodRong) begin
if(ringAble) ringIng <= 1;
else ringIng <= 0;
if(!yoodRong) ringIng <= 0;
end
reg [12:0] soundFile = 13'b0000010111111;
wire sound = soundFile[0];
always @(posedge clk) begin
soundFile <= {soundFile[11:0],soundFile[12]};
end
assign buzzer = sound&ringIng;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; map<int, int> m; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; m[a[i]] = i; } long long int b[n]; map<int, int> freq; for (int i = 0; i < n; i++) { cin >> b[i]; int shift = m[b[i]] - i; if (m[b[i]] - i < 0) shift = (n - i + m[b[i]]); freq[shift]++; } int ans = 0; for (auto i : freq) { ans = max(ans, i.second); } cout << ans << n ; cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << n ; return 0; }
|
`timescale 1ns / 1ps
/*
-- Module Name: output_block
-- Description: Bloque de salida de la interfaz de red. Se encarga de la
interaccion entre el elemento de procesamiento y el
router.
Este modulo toma el resultado del elemento de
procesamiento y lo empaquete en flits para su transporte
a travez de la red.
-- Dependencies: -- system.vh
-- output_control_unit.v
-- Parameters: -- CHANNEL_WIDTH: Numero de lineas de comunicacion
entre la interfaz de red y el
router.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 18 de Junio 2015: Creacion
*/
`include "system.vh"
module output_block
(
input wire clk,
input wire reset,
// -- inputs from pn ----------------------------------------- >>>>>
input wire done_strobe_din,
input wire [(2* `CHANNEL_WIDTH)-1:0] ciphertext_din,
input wire [`CHANNEL_WIDTH-1:0] shifted_header_din,
// -- to input block ----------------------------------------- >>>>>
output wire zero_credits_dout,
// -- output port -------------------------------------------- >>>>>
input wire credit_in_din,
output reg [`CHANNEL_WIDTH-1:0] output_channel_dout
);
/*
-- Instancia: output_control_unit
-- Descripcion: Unidad de control para el bloque de salida de la
interfaz de red. Este bloque se encarga de organizar la
salida de flits en direccion del router de la red.
El control de creditos se encuentra implementado dentro
de este modulo.
*/
wire [2:0] output_selector;
output_control_unit output_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.done_strobe_din (done_strobe_din),
// -- outputs -------------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
.output_selector_dout (output_selector)
);
/*
-- Registro
-- Descripcion: Registro de captura del resultado del elemento de
procesamiento. Este registro proporciona el dato
procesado para ser liberado a la red.
Solo se captura el texto cifrado, la llave de encriptado
se desecha.
*/
reg [(2* `CHANNEL_WIDTH)-1:0] ciphertext_reg;
always @(posedge clk)
if (done_strobe_din)
ciphertext_reg <= ciphertext_din;
/*
-- Multiplexor
-- Descripcion: Multiplexor para la seleccion del flit que saldra
a la red durante el siguiente ciclo de reloj.
Los datos de entrada para el multiplexor son los
registros de resultado del PE y la flit de cabecera
modificado.
Los dos ultimos dos flits del paquete son cargados
con las constantes 'NUL1' y 'NUL2' por razones de
trazabilidad de errores.
Si no existe transito de flits el multiplexor mantiene
el canal en un valor de 0.
*/
always @(*)
begin
output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
case (output_selector)
3'b101: output_channel_dout = shifted_header_din;
3'b100: output_channel_dout = ciphertext_reg[`CHANNEL_WIDTH-1:0];
3'b011: output_channel_dout = ciphertext_reg[(2 * `CHANNEL_WIDTH)-1:`CHANNEL_WIDTH];
3'b010: output_channel_dout = "NUL1";
3'b001: output_channel_dout = "NUL2";
3'b000: output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
endcase
end
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
output_block bloque_de_salida
(
.clk (clk),
.reset (reset),
// -- inputs from PE ----------------------------------------- >>>>>
.done_strobe_din (done_strobe_din),
.ciphertext_din (ciphertext_din),
.shifted_header_din (shifted_header_din),
// -- to input block ----------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
// -- output port -------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.output_channel_dout (output_channel_dout)
);
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_PP_SYMBOL_V
`define SKY130_FD_SC_MS__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_PP_SYMBOL_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_fifo_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast);
// dump file
$dumpfile("test_axis_frame_fifo_64.lxt");
$dumpvars(0, test_axis_frame_fifo_64);
end
axis_frame_fifo_64 #(
.ADDR_WIDTH(6),
.DATA_WIDTH(64),
.DROP_WHEN_FULL(0)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_TB_V
`define SKY130_FD_SC_HD__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_TB_V
|
module jump_addr(
input [25:0] inst,
input [3:0] pc_4,
output[31:0] j_addr);
buf (j_addr[0 ] ,inst[0 ]);
buf (j_addr[1 ] ,inst[1 ]);
buf (j_addr[2 ] ,inst[2 ]);
buf (j_addr[3 ] ,inst[3 ]);
buf (j_addr[4 ] ,inst[4 ]);
buf (j_addr[5 ] ,inst[5 ]);
buf (j_addr[6 ] ,inst[6 ]);
buf (j_addr[7 ] ,inst[7 ]);
buf (j_addr[8 ] ,inst[8 ]);
buf (j_addr[9 ] ,inst[9 ]);
buf (j_addr[10] ,inst[10]);
buf (j_addr[11] ,inst[11]);
buf (j_addr[12] ,inst[12]);
buf (j_addr[13] ,inst[13]);
buf (j_addr[14] ,inst[14]);
buf (j_addr[15] ,inst[15]);
buf (j_addr[16] ,inst[16]);
buf (j_addr[17] ,inst[17]);
buf (j_addr[18] ,inst[18]);
buf (j_addr[19] ,inst[19]);
buf (j_addr[20] ,inst[20]);
buf (j_addr[21] ,inst[21]);
buf (j_addr[22] ,inst[22]);
buf (j_addr[23] ,inst[23]);
buf (j_addr[24] ,inst[24]);
buf (j_addr[25] ,inst[25]);
buf (j_addr[26] ,1'b0 );
buf (j_addr[27] ,1'b0 );
buf (j_addr[28] ,pc_4[0 ]);
buf (j_addr[29] ,pc_4[1 ]);
buf (j_addr[30] ,pc_4[2 ]);
buf (j_addr[31] ,pc_4[3 ]);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool h[1000009]; int main() { int n, m, k, tmp, tmp1, pos = 1; cin >> n >> m >> k; for (int i = 0; i < m; ++i) { cin >> tmp; h[tmp] = true; } if (h[1]) { cout << pos << endl; return 0; } for (int i = 0; i < k; ++i) { cin >> tmp >> tmp1; if (pos == tmp || tmp1 == pos) { pos = (tmp == pos) ? tmp1 : tmp; if (h[pos]) break; } } cout << pos << endl; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_frame_p,
adc_frame_n,
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
delay_clk,
dma_dbg_data,
dma_dbg_trigger,
adc_dbg_data,
adc_dbg_trigger,
adc_clk,
adc_mon_valid,
adc_mon_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_frame_p;
input adc_frame_n;
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
input delay_clk;
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_clk;
output adc_mon_valid;
output [143:0] adc_mon_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_adc_8c i_adc_8c (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_frame_p (adc_frame_p),
.adc_frame_n (adc_frame_n),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.delay_clk (delay_clk),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger),
.adc_clk (adc_clk),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, arr[26]; string s; memset(&arr, -1, sizeof(arr)); cin >> s; int l = s.length(); if (l < 26) { cout << -1; return 0; } i = 0; j = 0; while (j < l) { if (j - i == 26) break; if (s[j] == ? ) j++; else if (arr[s[j] - A ] != -1) { int temp = i; i = arr[s[j] - A ] + 1; for (; temp < i; temp++) if (s[temp] != ? ) arr[s[temp] - A ] = -1; } else if (s[j] != ? && arr[s[j] - A ] == -1) { arr[s[j] - A ] = j; j++; } } if (j - i == 26) { int temp = i, temp2; for (temp2 = 0; temp2 < 26; temp2++) { if (arr[temp2] == -1) { while (s[temp] != ? && temp < j) temp++; s[temp] = A + temp2; } } while (i--) { if (s[i] == ? ) s[i] = s[i + 26]; } while (j < l) { if (s[j] == ? ) s[j] = s[j - 26]; j++; } cout << s; } else cout << -1; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool solve() { int n; bool ret = false; int m = 0; scanf( %d , &n); int a; scanf( %d , &a); while ((a & 1) == 0) a >>= 1; while (a % 3 == 0) a /= 3; m = a; for (int i = 1; i < n; i++) { int a; scanf( %d , &a); while ((a & 1) == 0) a >>= 1; while (a % 3 == 0) a /= 3; if (m != a) return false; } return true; } int main() { if (solve()) puts( Yes ); else puts( No ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int n, arr[N], arr2[N], seg[4 * N], lazy[4 * N]; inline void fix(int s, int e, int idx) { seg[idx] += lazy[idx]; if (s != e) { lazy[(idx << 1)] += lazy[idx]; lazy[(idx << 1) + 1] += lazy[idx]; } lazy[idx] = 0; } int build(int s, int e, int idx) { if (s == e) return seg[idx] = arr2[s]; return seg[idx] = max(build(s, ((s + e) >> 1), (idx << 1)), build(((s + e) >> 1) + 1, e, (idx << 1) + 1)); } int l, r, val; inline int update(int s, int e, int idx) { fix(s, e, idx); if (s > r || e < l) return seg[idx]; if (s >= l && e <= r) { lazy[idx] += val; fix(s, e, idx); return seg[idx]; } return seg[idx] = max(update(s, ((s + e) >> 1), (idx << 1)), update(((s + e) >> 1) + 1, e, (idx << 1) + 1)); } int s, e, idx, mid; inline int Lower_bound(int val) { s = 0, e = n, idx = 1; while (true) { fix(s, e, idx); if (s == e) return s; mid = ((s + e) >> 1); fix(s, mid, (idx << 1)); fix(mid + 1, e, (idx << 1) + 1); if (seg[(idx << 1)] >= val) { idx = (idx << 1); e = mid; } else { idx = (idx << 1) + 1; s = mid + 1; } } assert(false); } int Idx; inline int get() { s = 0, e = n, idx = 1; while (true) { fix(s, e, idx); if (s == e) return seg[idx]; mid = ((s + e) >> 1); if (Idx <= mid) { idx = (idx << 1); e = mid; } else { idx = (idx << 1) + 1; s = mid + 1; } } assert(false); } int tmp1, tmp2, tmp3, tmp4, tmp5; int tmp7 = 0, tmp8 = 0; void check2(int cur) { for (int i = 1; i <= 4 * (n + 1); i++) seg[i] = lazy[i] = 0; arr[n] = cur; for (int i = 0; i <= n; i++) { arr2[i] = arr[i]; } sort(arr2, arr2 + n + 1); build(0, n, 1); tmp7 = 0; for (int i = n; i >= 0; i--) { Idx = i; tmp1 = get(); if (tmp1 <= 0) { tmp7 -= tmp1; continue; } if (i - tmp1 < 0) { l = 0, r = i - 1, val = -1; update(0, n, 1); tmp7 -= (i - tmp1); continue; } Idx = i - tmp1; tmp2 = get(); tmp3 = Lower_bound(tmp2); Idx = i - 1; tmp4 = get(); if (tmp2 == tmp4) { l = tmp3; r = tmp3 + tmp1 - 1; val = -1; update(0, n, 1); } else { tmp5 = Lower_bound(tmp2 + 1); l = tmp5; r = i - 1; val = -1; update(0, n, 1); l = tmp3; r = l + (tmp5 - (i - tmp1)) - 1; val - 1; update(0, n, 1); } } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); } check2(0); tmp8 = tmp7; check2(n); tmp7 = n - tmp7; if (tmp7 < tmp8) { puts( -1 ); return 0; } for (int i = tmp8; i <= tmp7; i += 2) { printf( %d , i); } puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
|
/* Verilog model created from schematic section3_schematic.sch -- May 07, 2014 14:52 */
module section3_schematic( A, B, C, D, LED, SegA, SegB, SegC, SegD, SegE, SegF,
SegG );
input A;
input B;
input C;
input D;
output LED;
output SegA;
output SegB;
output SegC;
output SegD;
output SegE;
output SegF;
output SegG;
wire N_44;
wire N_45;
wire N_46;
wire N_42;
wire N_43;
wire N_35;
wire N_39;
wire N_28;
wire N_29;
wire N_30;
wire N_16;
wire N_17;
wire N_18;
wire N_19;
wire N_20;
wire N_21;
wire N_22;
wire N_23;
wire N_24;
wire N_25;
wire N_26;
wire N_1;
wire N_2;
wire N_3;
wire N_8;
wire N_9;
wire N_10;
wire N_11;
wire N_12;
wire N_13;
wire N_14;
wire N_15;
AND2 I23 ( .A(N_45), .B(N_35), .Z(N_21) );
OR3 I36 ( .A(N_29), .B(N_30), .C(N_28), .Z(SegG) );
OR3 I24 ( .A(N_22), .B(N_20), .C(N_21), .Z(SegE) );
OR3 I18 ( .A(N_3), .B(N_1), .C(N_2), .Z(SegC) );
AND3 I33 ( .A(N_45), .B(N_42), .C(N_44), .Z(N_28) );
AND3 I25 ( .A(N_45), .B(N_42), .C(N_46), .Z(N_18) );
AND3 I26 ( .A(N_45), .B(N_46), .C(N_35), .Z(N_17) );
AND3 I27 ( .A(N_45), .B(N_42), .C(N_35), .Z(N_16) );
AND3 I28 ( .A(N_42), .B(N_44), .C(N_35), .Z(N_20) );
AND3 I29 ( .A(N_45), .B(N_43), .C(N_44), .Z(N_22) );
AND3 I19 ( .A(N_43), .B(N_46), .C(N_35), .Z(N_25) );
AND3 I5 ( .A(N_43), .B(N_46), .C(LED), .Z(N_10) );
AND3 I4 ( .A(N_39), .B(N_43), .C(LED), .Z(N_11) );
AND3 I3 ( .A(N_39), .B(N_46), .C(N_35), .Z(N_15) );
AND3 I2 ( .A(N_39), .B(N_43), .C(LED), .Z(N_1) );
AND3 I1 ( .A(N_39), .B(N_43), .C(N_46), .Z(N_2) );
OR4 I30 ( .A(N_19), .B(N_16), .C(N_17), .D(N_18), .Z(SegF) );
OR4 I31 ( .A(N_26), .B(N_23), .C(N_24), .D(N_25), .Z(SegD) );
OR4 I7 ( .A(N_12), .B(N_8), .C(N_9), .D(N_13), .Z(SegA) );
OR4 I6 ( .A(N_14), .B(N_10), .C(N_11), .D(N_15), .Z(SegB) );
AND4 I35 ( .A(N_45), .B(N_43), .C(N_46), .D(N_35), .Z(N_29) );
AND4 I34 ( .A(N_39), .B(N_43), .C(N_44), .D(LED), .Z(N_30) );
AND4 I32 ( .A(N_39), .B(N_43), .C(N_44), .D(N_35), .Z(N_19) );
AND4 I22 ( .A(N_45), .B(N_43), .C(N_44), .D(LED), .Z(N_26) );
AND4 I20 ( .A(N_39), .B(N_42), .C(N_46), .D(LED), .Z(N_24) );
AND4 I21 ( .A(N_45), .B(N_42), .C(N_44), .D(N_35), .Z(N_23) );
AND4 I13 ( .A(N_45), .B(N_42), .C(N_44), .D(N_35), .Z(N_12) );
AND4 I12 ( .A(N_45), .B(N_43), .C(N_44), .D(LED), .Z(N_8) );
AND4 I11 ( .A(N_39), .B(N_43), .C(N_44), .D(N_35), .Z(N_9) );
AND4 I10 ( .A(N_39), .B(N_42), .C(N_46), .D(N_35), .Z(N_13) );
AND4 I9 ( .A(N_45), .B(N_43), .C(N_44), .D(N_35), .Z(N_14) );
AND4 I8 ( .A(N_45), .B(N_42), .C(N_46), .D(LED), .Z(N_3) );
INV I15 ( .A(N_46), .Z(N_44) );
INV I16 ( .A(N_43), .Z(N_42) );
INV I37 ( .A(D), .Z(N_35) );
INV I38 ( .A(C), .Z(N_46) );
INV I39 ( .A(B), .Z(N_43) );
INV I40 ( .A(A), .Z(N_39) );
INV I17 ( .A(N_39), .Z(N_45) );
INV I14 ( .A(N_35), .Z(LED) );
endmodule // section3_schematic
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#include <bits/stdc++.h> using namespace std; template <typename T> bool chmax(T& a, const T& b) { return a < b ? (a = b, true) : false; } template <typename T> bool chmin(T& a, const T& b) { return b < a ? (a = b, true) : false; } int N; string S; int main() { cin >> S; N = S.size(); for (int i = (1); i < (N); i++) { if (S[i] == S[i - 1]) { cout << Impossible << endl; return 0; } } char twice; for (char c = A ; c <= Z ; c++) { if (count((S).begin(), (S).end(), c) == 2) { twice = c; break; } } int x = S.find(twice), y = S.find(twice, x + 1); string a = S.substr(0, x), b = S.substr(x + 1, y - x - 1), c = S.substr(y + 1); string t = b + c + a; vector<string> ans(2, string(13, . )); ans[0][12 - b.size() / 2] = twice; int idx = 0; bool flag = false; while (true) { for (int i = 0; i < 13; i++) { if (ans[0][i] == twice && flag == false) { flag = true; } else if (ans[0][i] == twice && flag == true) { cout << ans[0] << endl; cout << ans[1] << endl; return 0; } else if (flag && idx < t.size()) { ans[0][i] = t[idx++]; } } for (int i = 12; i >= 0; i--) { if (flag && idx < t.size()) { ans[1][i] = t[idx++]; } } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; while (cin >> a >> b >> c) { if (b == a / 2 && c == a / 2) cout << NO << endl; else if (b == a / 2 && c == a / 2 + 1) cout << NO << endl; else if (b == a / 2 + 1 && c == a / 2 + 1) cout << NO << endl; else if (b == a / 2 + 1 && c == a / 2) cout << NO << endl; else cout << YES << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n, q; cin >> n >> q; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } long long x = 0, y = 0; for (long long i = 0; i < n; i++) { y = max(y, x + a[i]); x = max(x, y - a[i]); } cout << max(x, y) << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; long double n, l, k, v1, v2; int main() { cout << fixed << setprecision(10); cin >> n >> l >> v1 >> v2 >> k; if (v2 <= v1) { cout << l / (v1 * 1.0) << endl; return 0; } if (n <= k) { cout << l / (v2 * 1.0) << endl; return 0; } int T = ceil(n / (k * 1.0)); long double K = ((T - 1) * (1 + (v2 - v1) / ((v2 + v1) * 1.0))) * v1; K += v2; K = l / K; long double ans = K * (T + (T - 1) * (v2 - v1) / (v2 + v1)); cout << ans << endl; }
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`timescale 1ns / 1ps
`define SIMULATION
module peripheral_audio_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
reg micData;
peripheral_audio uut (.clk(clk) , .rst(reset) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out),.micData(micData) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
reg d;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
#4 reset=0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
//d_in = 16'h0001; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
addr = 16'h0002;
cs=1; rd=1; wr=0;
for(i=0; i<40000; i=i+1) begin
@ (posedge clk);
end
//d_in = 16'h0002; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_audio_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200000) $finish;
end
endmodule
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#include <bits/stdc++.h> using namespace std; void sf(int &x) { scanf( %d , &x); } void sf(long long &x) { scanf( %lld , &x); } void sf(float &x) { scanf( %f , &x); } void sf(double &x) { scanf( %lf , &x); } void sf(int &x, int &y) { scanf( %d%d , &x, &y); } void sf(long long &x, long long &y) { scanf( %lld%lld , &x, &y); } void sf(float &x, float &y) { scanf( %f%f , &x, &y); } void sf(double &x, double &y) { scanf( %lf%lf , &x, &y); } void sf(double &x, double &y, double &z) { scanf( %lf%lf%lf , &x, &y, &z); } void sf(int &x, int &y, int &z) { scanf( %d%d%d , &x, &y, &z); } void sf(long long &x, long long &y, long long &z) { scanf( %lld%lld%lld , &x, &y, &z); } void sf(float &x, float &y, float &z) { scanf( %u%u%u , &x, &y, &z); } void sf(char &x) { x = getchar(); } void sf(char *s) { scanf( %s , s); } void sf(string &s) { cin >> s; } void sf(string &s, string &ss) { cin >> s >> ss; } void pf(int x) { printf( %d n , x); } void pf(int x, int y) { printf( %d %d n , x, y); } void pf(long long x) { printf( %lld n , x); } void pf(long long x, long long y) { printf( %lld %lld n , x, y); } void pf(float x) { printf( %u n , x); } void pf(unsigned long long x) { printf( %llu n , x); } void pf(double x) { printf( %.6lf n , x); } void pf(double x, double y) { printf( %.5lf %.5lf n , x, y); } void pf(char x) { printf( %c n , x); } void pf(char *x) { printf( %s n , x); } void pf(string x) { cout << x; puts( ); } void pf(int x, int y, int z) { printf( %d %d %d n , x, y, z); } template <class T> T bigmod(T b, T p, T m) { if (p == 0) return 1 % m; T x = b; T ans = 1; while (p) { if (p & 1) ans = (ans * x) % m; p >>= 1; x = (x * x) % m; } return ans; } template <class T> T gcd(T x, T y) { if (y == 0) return x; return gcd(y, x % y); } template <typename T> T POW(T b, T p) { if (p == 1) return b; if (p % 2 == 0) { T s = POW(b, p / 2); return s * s; } return b * POW(b, p - 1); } template <typename T> T modinv(T num, T m) { return bigmod(num, m - 2, m); } template <typename T> long long triangle(T a, T b, T c) { return (c.x - a.x) * (b.y - a.y) - (b.x - a.x) * (c.y - a.y); } int a, b, c, l[1009]; string s[1009]; int main() { while (getline(cin, s[a])) { l[a] = s[a].size(); b = max(b, l[a]); a++; } for (int i = 0; i < b + 2; i++) cout << * ; puts( ); c = 0; for (int i = 0; i < a; i++) { cout << * ; int kk = b - l[i]; if (kk & 1) { if (c == 0) { int k = kk / 2; int j = kk - k; for (int m = 0; m < k; m++) cout << ; cout << s[i]; for (int m = 0; m < j; m++) cout << ; cout << * ; } else { int k = kk / 2; int j = kk - k; for (int m = 0; m < j; m++) cout << ; cout << s[i]; for (int m = 0; m < k; m++) cout << ; cout << * ; } } else { int k = kk / 2; int j = kk - k; for (int m = 0; m < j; m++) cout << ; cout << s[i]; for (int m = 0; m < k; m++) cout << ; cout << * ; } puts( ); if (kk & 1) { if (c == 0) c = 1; else c = 0; } } for (int i = 0; i < b + 2; i++) cout << * ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int i, j, k; int ag[101], a[101][101]; int g = 0, dr[101], dl[101]; for (i = 1; i <= n; i++) { scanf( %d , &ag[i]); g += ag[i]; dl[i] = 1; dr[i] = ag[i]; for (j = 1; j <= ag[i]; j++) scanf( %d , &a[i][j]); } int m[10001], mg = 0; int s1 = 0, s2 = 0; for (i = 1; i <= n; i++) { if (ag[i] % 2 == 1) { m[mg] = a[i][(ag[i] + 1) / 2]; mg++; } for (j = 1; j <= ag[i]; j++) { if (j <= ag[i] / 2) s1 += a[i][j]; if (j > (ag[i] + 1) / 2) s2 += a[i][j]; } } sort(m, m + mg); for (i = mg - 1; i >= 0; i--) { if ((mg - i) % 2 == 1) s1 += m[i]; else s2 += m[i]; } printf( %d %d , s1, s2); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, c, d; cin >> a >> b >> c >> d; cout << b << << c << << c << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long> primer; long long mul(long long x, long long y, long long mod) { long long s = 0; for (; y; y /= 2, x = (x + x) % mod) if (y & 1) s = (s + x) % mod; return s; } long long gcd(long long x, long long y) { return y ? gcd(y, x % y) : x; } long long power(long long x, long long y, long long mo) { long long s = 1; for (; y; y /= 2, x = mul(x, x, mo)) if (y & 1) s = mul(s, x, mo); return s; } bool isPrime(long long x) { if (x == 2) return 1; for (int T = 10; T; T--) { long long a = rand() % (x - 2) + 2; if (power(a, x - 1, x) != 1) return 0; int p = x - 1; for (; p % 2 == 0;) { p /= 2; long long v = power(a, p, x); if (mul(v, v, x) == 1 && v != 1 && v != x - 1) return 0; } } return 1; } long long pollard(long long n, int c) { long long i = 0, k = 2, x = rand() % (n - 1) + 1, y = x; for (;;) { x = (mul(x, x, n) + c) % n; long long g = gcd((y - x + n) % n, n); if (g != 1 && g != n) return g; if (x == y) return n; if ((++i) == k) y = x, k <<= 1; } } void getPrimes(long long n, vector<long long> &p) { if (n == 1) return; if (isPrime(n)) { p.push_back(n); return; } long long d = n; for (int i = 2; d == n; i++) d = pollard(n, i); getPrimes(d, p); getPrimes(n / d, p); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline void moreprime() { int start = primer.back() + 1; if (primer.size() % 10000 == 0) cout << primer.size() << << primer.back() << endl; while (true) { for (unsigned int i = 0; i < primer.size(); i++) { if (start % primer[i] == 0) break; if (primer[i] * primer[i] > start) { primer.push_back(start); return; } } start++; } } vector<long long> defactor(long long a) { vector<long long> result; getPrimes(a, result); sort(result.begin(), result.end()); vector<long long> rs; if (result.size() > 0) rs.push_back(result[0]); for (int i = 1; i < result.size(); i++) { if (result[i] != result[i - 1]) rs.push_back(result[i]); } return rs; } int getbit(long long a, const vector<long long> &factors) { int bit = 0; for (unsigned int i = 0; i < factors.size(); i++) { if (a % factors[i] == 0) { a /= factors[i]; bit |= 1 << i; } } return bit; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); int n; long long x, y; primer.push_back(2); cin >> n >> x >> y; if (y % x != 0) { printf( 0 ); return 0; } vector<long long> factors = defactor(y / x); vector<long long> a(40000, 0), b(40000, 0); int maxa = 0, maxb = 0; int v; long long num; for (int i = 0; i < n; i++) { cin >> num; if (num % x == 0) { v = getbit(num / x, factors); a[v]++; maxa = max(maxa, v); } if (y % num == 0) { v = getbit(y / num * gcd(y / num, num) / gcd(y / num, x), factors); b[v]++; maxb = max(maxb, v); } } long long count = 0; for (int i = 0; i <= maxa; i++) { if (a[i]) { for (int j = 0; j <= maxb; j++) { if (b[j]) { if (!(i & j)) count += a[i] * b[j]; } } } } cout << count << endl; }
|
/**
\file "unstable-dequeue.v"
Bug-fix test case to show that next_event_time() returns
only the next non-killed event time.
copy-modified from "inverters.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: unstable-dequeue.v,v 1.1 2010/06/14 00:22:35 fang Exp $
*/
`timescale 1ps/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg in0;
wire in1;
reg out0, out1;
wire dummy;
clk_gen #(.HALF_PERIOD(4)) clk(in1);
// prsim stuff
initial
begin
// @haco@ inverters-separate.haco-c
$prsim("inverters-separate.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("unstable warn");
$prsim_cmd("unstable-dequeue");
$prsim_cmd("watchall");
$to_prsim("TOP.in0", "in0");
$to_prsim("TOP.in1", "in1");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
#100 in0 = 1'b0;
#100 in0 = 1'b1;
#100 in0 = 1'b0;
$prsim_cmd("queue");
// deliberate instability to trigger bug
#5 in0 = 1'b1;
$prsim_cmd("queue");
#5 in0 = 1'b0;
$prsim_cmd("queue");
#90 in0 = 1'b1;
#100 $finish;
end
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in0)
begin
$display("at time %7.3f, observed in0 %b", $realtime,in0);
end
always @(out0)
begin
$display("at time %7.3f, observed out0 = %b", $realtime,out0);
end
endmodule
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