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#include <bits/stdc++.h> using namespace std; long long x; int n, d; struct cmp { bool operator()(pair<int, int> x, pair<int, int> y) { return x.first > y.first; } }; set<pair<int, int>, cmp> que; set<pair<int, int>, cmp>::iterator it; vector<int> num; int a[100005], c[100005]; bool b[100005]; long long next() { x = (x * 37 + 10007) % 1000000007; return x; } void initAB() { for (int i = 0; i < n; i++) a[i] = i + 1; for (int i = 0; i < n; i++) swap(a[i], a[next() % (i + 1)]); for (int i = 0; i < n; i++) { if (i < d) b[i] = 1; else b[i] = 0; } for (int i = 0; i < n; i++) swap(b[i], b[next() % (i + 1)]); } int main() { scanf( %d%d%I64d , &n, &d, &x); initAB(); if (d < 1000) { for (int i = 0; i < n; i++) { if (b[i]) num.push_back(i); for (int j = 0; j < num.size(); j++) c[i] = max(c[i], a[i - num[j]]); } } else { for (int i = 0; i < n; i++) { que.insert(make_pair(a[i], i)); for (it = que.begin(); it != que.end(); it++) { if (b[i - it->second]) { c[i] = it->first; break; } } } } for (int i = 0; i < n; i++) cout << c[i] << endl; return 0; }
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_iface_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS)
)
(
input logic [ADDRESS_W-1:0] address,
output logic [NUM_BANKS-1:0] bank_sel_1hot, // one-hot
output logic [$clog2(NUM_BANKS)-1:0] bank_sel_fe, // full encoded
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] bank_address
);
integer i;
// To support NUM_BANKS=1 we need a wider address
logic [ADDRESS_W:0] wider_address;
assign wider_address = {1'b0,address};
always@*
begin
for (i=0; i<NUM_BANKS; i=i+1)
bank_sel_1hot[i] = (wider_address[BANK_SEL_BIT+$clog2(NUM_BANKS)-1 : BANK_SEL_BIT] == i);
end
always@*
begin
bank_sel_fe = (wider_address>>BANK_SEL_BIT) & ~({64{1'b1}}<<$clog2(NUM_BANKS));
end
assign bank_address = ((address>>(BANK_SEL_BIT+$clog2(NUM_BANKS)))<<(BANK_SEL_BIT)) |
// Take address[BANKS_SEL_BIT-1:0] in a manner that allows BANK_SEL_BIT=0
((~({ADDRESS_W{1'b1}}<<BANK_SEL_BIT)) & address);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DFRTN_FUNCTIONAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dfrtn (
VPWR ,
VGND ,
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , D, intclk, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_TB_V
`define SKY130_FD_SC_HD__AND3B_TB_V
/**
* and3b: 3-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_hd__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_TB_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int N = 1e6 + 5; int n, m, k; bool vis[N]; int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; int h; for (int i = 1; i <= m; i++) { cin >> h; vis[h] = 1; } bool fg = 0; int bone = 1; if (vis[bone]) fg = 1; for (int i = 1; i <= k; i++) { int u, v; cin >> u >> v; if ((u == bone || v == bone) && !fg) { bone = (bone == u) ? v : u; if (vis[bone]) fg = 1; } } cout << bone << endl; return 0; }
|
module wb_stream_writer_ctrl
#(parameter WB_AW = 32,
parameter WB_DW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 0)
(//Stream data output
input wb_clk_i,
input wb_rst_i,
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output reg [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//FIFO interface
output [WB_DW-1:0] fifo_d,
output fifo_wr,
input [FIFO_AW:0] fifo_cnt,
//Configuration interface
output reg busy,
input enable,
output reg [WB_DW-1:0] tx_cnt,
input [WB_AW-1:0] start_adr,
input [WB_AW-1:0] buf_size,
input [WB_AW-1:0] burst_size);
wire active;
wire timeout = 1'b0;
reg last_adr;
reg [$clog2(MAX_BURST_LEN-1):0] burst_cnt;
//FSM states
localparam S_IDLE = 0;
localparam S_ACTIVE = 1;
reg [1:0] state;
wire burst_end = (burst_cnt == burst_size-1);
wire fifo_ready = (fifo_cnt+burst_size <= 2**FIFO_AW);
always @(active or burst_end) begin
wbm_cti_o = !active ? 3'b000 :
burst_end ? 3'b111 :
3'b010; //LINEAR_BURST;
end
assign active = (state == S_ACTIVE);
assign fifo_d = wbm_dat_i;
assign fifo_wr = wbm_ack_i;
assign wbm_sel_o = 4'hf;
assign wbm_we_o = 1'b0;
assign wbm_cyc_o = active;
assign wbm_stb_o = active;
assign wbm_bte_o = 2'b00;
assign wbm_dat_o = {WB_DW{1'b0}};
assign wbm_adr_o = start_adr + tx_cnt*4;
always @(posedge wb_clk_i) begin
//Address generation
last_adr = (tx_cnt == buf_size[WB_AW-1:2]-1);
if (wbm_ack_i)
if (last_adr)
tx_cnt <= 0;
else
tx_cnt <= tx_cnt+1;
//Burst counter
if(!active)
burst_cnt <= 0;
else
if(wbm_ack_i)
burst_cnt <= burst_cnt + 1;
//FSM
case (state)
S_IDLE : begin
if (busy & fifo_ready)
state <= S_ACTIVE;
if (enable)
busy <= 1'b1;
end
S_ACTIVE : begin
if (burst_end & wbm_ack_i) begin
state <= S_IDLE;
if (last_adr)
busy <= 1'b0;
end
end
default : begin
state <= S_IDLE;
end
endcase // case (state)
if(wb_rst_i) begin
state <= S_IDLE;
tx_cnt <= 0;
busy <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char aa[100100]; int a[550][550]; int main() { int x, y, x0, y0; cin >> x >> y >> x0 >> y0; for (int i = 1; i <= x; i++) for (int j = 1; j <= y; j++) a[i][i] = 0; a[x0][y0] = 1; int sum = 1; scanf( %s , aa); int len = strlen(aa); cout << 1 ; for (int i = 0; i < len - 1; i++) { if (aa[i] == U ) { x0--; if (x0 < 1) x0++; if (a[x0][y0] == 1) cout << 0 ; else { cout << 1 ; sum++; a[x0][y0] = 1; } } if (aa[i] == D ) { x0++; if (x0 > x) x0--; if (a[x0][y0] == 1) cout << 0 ; else { cout << 1 ; sum++; a[x0][y0] = 1; } } if (aa[i] == L ) { y0--; if (y0 < 1) y0++; if (a[x0][y0] == 1) cout << 0 ; else { cout << 1 ; sum++; a[x0][y0] = 1; } } if (aa[i] == R ) { y0++; if (y0 > y) y0--; if (a[x0][y0] == 1) cout << 0 ; else { cout << 1 ; sum++; a[x0][y0] = 1; } } } cout << x * y - sum << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int a, b, h, w, ans = INT_MAX, f[int(1e5 + 10)]; bool cmp(int x, int y) { return x > y; } void get_answ(long long x, long long y, int d, bool flag) { if (x >= a && y >= b) { ans = min(ans, d - 1); return; } if (d == n + 1) return; if ((!flag || f[d] != f[d - 1]) && x < a) get_answ(1ll * x * f[d], y, d + 1, 0); if (y < b) get_answ(x, 1ll * y * f[d], d + 1, 1); } int main() { scanf( %d%d%d%d%d , &a, &b, &h, &w, &n); for (int i = 1; i <= n; i++) scanf( %d , f + i); sort(f + 1, f + n + 1, cmp); get_answ(h, w, 1, 0); get_answ(w, h, 1, 0); if (ans != INT_MAX) printf( %d , ans); else printf( -1 ); }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 50, M = 1e4 + 2, OO = 0x3f3f3f3f; int n, m, A[N], rem; int main() { scanf( %d %d , &n, &m); rem = m; for (int i = 0; i < n; ++i) { scanf( %d , A + i); int ans = 0; if (A[i] >= rem) ans = 1, A[i] -= rem, rem = m; ans += A[i] / m; rem -= A[i] % m; printf( %d n , ans); } return 0; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_egmreset (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_data #(
parameter NUM_OF_BITS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_BITS-1:0] in_data,
input out_clk,
output reg [NUM_OF_BITS-1:0] out_data
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
reg [NUM_OF_BITS-1:0] cdc_hold;
sync_bits i_sync_out (
.in(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out(out_toggle)
);
sync_bits i_sync_in (
.in(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out(in_toggle)
);
wire in_load = in_toggle == in_toggle_d1;
wire out_load = out_toggle ^ out_toggle_d1;
always @(posedge in_clk) begin
if (in_load == 1'b1) begin
cdc_hold <= in_data;
in_toggle_d1 <= ~in_toggle_d1;
end
end
always @(posedge out_clk) begin
if (out_load == 1'b1) begin
out_data <= cdc_hold;
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_data <= in_data;
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int s[4]; int main() { long long int x, y; while (scanf( %I64d%I64d , &x, &y) == 2) { s[0] = y; s[1] = y; s[2] = y; sort(s, s + 3); long long int cnt = 0; while (1) { if (s[0] == x && s[1] == x && s[2] == x) { break; } if (s[1] + s[2] - 1 > x) { s[0] = x; } else { s[0] = s[1] + s[2] - 1; } cnt++; sort(s, s + 3); } printf( %I64d n , cnt); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int s, tens, sum = 0; cin >> s; for (; s > 0;) { tens = s / 10; s -= tens * 10; s += tens; sum += tens * 10; if (s >= 10 && s <= 18) { s -= 10; s++; sum += 10; if (s) { sum += s; s = 0; } } else if (s <= 9) { sum += s; s = 0; } } cout << sum << endl; } return 0; }
|
module Data_Memory
(
clk_i,
rst_i,
addr_i,
data_i,
enable_i,
write_i,
ack_o,
data_o
);
// Interface
input clk_i;
input rst_i;
input [31:0] addr_i;
input [255:0] data_i;
input enable_i;
input write_i;
output ack_o;
output [255:0] data_o;
// Memory
reg [255:0] memory [0:511]; //16KB
reg [3:0] count;
reg ack;
reg ok;
reg [255:0] data;
wire [26:0] addr;
parameter STATE_IDLE = 3'h0,
STATE_WAIT = 3'h1,
STATE_ACK = 3'h2,
STATE_FINISH = 3'h3;
reg [1:0] state;
assign ack_o = ack;
assign addr = addr_i>>5;
assign data_o = data;
//Controller
always@(posedge clk_i or negedge rst_i) begin
if(~rst_i) begin
count <= 4'b0;
ok <= 1'b0;
ack <= 1'b0;
state <= STATE_IDLE;
end
else begin
case(state)
STATE_IDLE: begin
if(enable_i) begin
count <= count + 1;
state <= STATE_WAIT;
end
else begin
state <= STATE_IDLE;
end
end
STATE_WAIT: begin
if(count == 4'd6) begin
ok <= 1'b1;
state <= STATE_ACK;
end
else begin
count <= count + 1;
state <= STATE_WAIT;
end
end
STATE_ACK: begin
count <= 4'b0;
ok <= 1'b0;
ack <= 1'b1;
state <= STATE_FINISH;
end
STATE_FINISH: begin
ack <= 1'b0;
state <= STATE_IDLE;
end
endcase
end
end
// Read Data
always@(posedge clk_i) begin
if(ok && !write_i) begin
data = memory[addr];
end
end
// Write Data
always@(posedge clk_i) begin
if(ok && write_i) begin
memory[addr] <= data_i;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void maximize(int &a, int b) { a = max(a, b); } int absolut(int x) { if (x < 0) return -x; return x; } const int tope = 1 << 19; const int first = 1 << 18; struct elem { int ls, lH, lh, lb; int rs, rH, rh, rb; int sol; }; elem v[tope]; void recompute(int pos) { elem &e = v[pos]; elem &e0 = v[2 * pos]; elem &e1 = v[2 * pos + 1]; e.ls = e0.ls + e1.ls; e.lH = max(e0.lH, e0.ls + e1.lH); e.lh = min(e0.lh, e0.ls + e1.lh); e.lb = max(e0.lb, -e0.ls + e1.lb); if (e0.lh < e0.ls + e1.lH) maximize(e.lb, -2 * e0.lh + e0.ls + e1.lH); e.rs = e0.rs + e1.rs; e.rH = max(e1.rH, e0.rH + e1.rs); e.rh = min(e1.rh, e0.rh + e1.rs); e.rb = max(e1.rb, e0.rb - e1.rs); if (e1.rh < e0.rH + e1.rs) maximize(e.rb, -2 * e1.rh + e1.rs + e0.rH); e.sol = max(max(e0.sol, e1.sol), max(e0.rb + e1.lH, e0.rH + e1.lb)); } void insert(int pos, int val) { pos += first; elem &e = v[pos]; e.ls = val; e.lH = max(0, val); e.lh = min(0, val); e.lb = absolut(val); val *= -1; e.rs = val; e.rH = max(0, val); e.rh = min(0, val); e.rb = absolut(val); e.sol = absolut(val); while (pos > 1) { pos /= 2; recompute(pos); } } int n, cases; string s; void insert(int pos) { insert(pos, s[pos] == ( ? 1 : -1); } int main() { cin >> n >> cases >> s; s = + s; for (int i = 1; i < int(s.size()); i++) insert(i); cout << v[1].sol << endl; for (int cas = 0; cas < cases; cas++) { int pos0, pos1; cin >> pos0 >> pos1; swap(s[pos0], s[pos1]); insert(pos0); insert(pos1); cout << v[1].sol << endl; } }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's reg2mem aligner ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Aligns register data to memory alignment. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_reg2mem.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// Internal regs and wires
//
reg [7:0] memdata_hh;
reg [7:0] memdata_hl;
reg [7:0] memdata_lh;
reg [7:0] memdata_ll;
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(regdata)
memdata_ll = regdata[7:0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
m3 m3_inst (.clk(clk));
defparam m3_inst.FROMDEFP = 19;
defparam m3_inst.P2 = 2;
//defparam m3_inst.P3 = PAR;
defparam m3_inst.P3 = 3;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter UNCH = 99;
parameter P1 = 10;
parameter P2 = 20;
parameter P3 = 30;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
if (FROMDEFP !== 19) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, ch; while (!isdigit(ch = getchar())) ; while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return x; } template <typename T> inline T gcd(T a, T b) { return !b ? a : gcd(b, a % b); } struct Node { int len, pos, id; }; struct prime { int p, c; }; const int MAXN = 100000; vector<Node> a[MAXN + 1]; vector<prime> d[41]; int pri[45][10]; long long pw[45][10]; int main() { int n = read(), m = read(); for (int i = 1; i <= n; i++) { int len = read(); for (int j = 0; j < len; j++) { int x = read(); a[x].push_back((Node){len, j, i}); } } for (int i = 2; i <= 40; i++) { int tmp = i; for (int j = 2; j <= i; j++) { if (tmp % j) continue; int c = 0; while (tmp % j == 0) tmp /= j, ++c; d[i].push_back((prime){j, c}); } long long mul = 1; for (int j = 0; j < 10; j++) pw[i][j] = mul, mul *= i; } for (int i = 1; i <= m; i++) { int si = a[i].size(), res = 1, l = 0; if (!si) { puts( 0 ); continue; } long long lcm = a[i][0].len, pos = a[i][0].pos, las = a[i][0].id; int s = d[lcm].size(); for (int j = 0; j < s; j++) { prime z = d[lcm][j]; pri[z.p][z.c]++; } for (int r = 1; r < si; r++) { Node x = a[i][r], y = a[i][l]; if (x.id != las + 1) { l = r, lcm = x.len, pos = x.pos; memset(pri, 0, sizeof(pri)); } else { long long g = gcd(lcm, (long long)x.len); while (l < r && abs(pos - x.pos) % g) { s = d[y.len].size(); for (int j = 0; j < s; j++) { prime z = d[y.len][j]; pri[z.p][z.c]--; if (!pri[z.p][z.c]) { int flag = 0; for (int k = z.c + 1; k < 10; k++) flag |= pri[z.p][k]; if (!flag) { lcm /= pw[z.p][z.c]; for (int k = z.c; k >= 1; k--) if (pri[z.p][k]) { lcm *= pw[z.p][k]; break; } } } } g = gcd(lcm, (long long)x.len); y = a[i][++l]; pos %= lcm; } long long tpos = x.pos; while (pos != tpos) { if (pos < tpos) pos += (tpos - pos + lcm - 1) / lcm * lcm; else tpos += (pos - tpos + x.len - 1) / x.len * x.len; } lcm = lcm / g * x.len; } las = x.id; s = d[x.len].size(); for (int j = 0; j < s; j++) { prime z = d[x.len][j]; pri[z.p][z.c]++; } res = max(res, r - l + 1); } printf( %d n , res); memset(pri, 0, sizeof(pri)); } return 0; }
|
//--------------------------------------------------------------------------------
// filter.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Fast 32 channel digital noise filter using a single LUT function for each
// individual channel. It will filter out all pulses that only appear for half
// a clock cycle. This way a pulse has to be at least 5-10ns long to be accepted
// as valid. This is sufficient for sample rates up to 100MHz.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module filter (clock, indata, indata180, outdata);
input clock;
input [31:0] indata;
input [31:0] indata180;
output [31:0] outdata;
reg [31:0] dly_indata, next_dly_indata;
reg [31:0] dly_indata180, next_dly_indata180;
reg [31:0] outdata, next_outdata;
always @(posedge clock)
begin
outdata = next_outdata;
dly_indata = next_dly_indata;
dly_indata180 = next_dly_indata180;
end
always @*
begin
#1;
next_outdata = (outdata | dly_indata | indata) & dly_indata180;
next_dly_indata = indata;
next_dly_indata180 = indata180;
end
endmodule
|
#include <bits/stdc++.h> int main() { static long long N, K, b[1000000] = {}, n, i, t; for (scanf( %lld%lld , &N, &K), n = N, i = 900000; n; n /= 2, i++) n & 1 && (b[i]++, K--); if (K < 0) puts( No ); else { for (i = 999999; K >= b[i]; i--) if (b[i]) while (b[i]) b[i - 1] += 2, b[i]--, K--; for (i = 0; !b[i]; i++) ; for (; K;) b[i] ? (b[i]--, b[i - 1] += 2, K--, i--) : i--; for (puts( Yes ), t = 0, i = 999999; i >= 0; i--) while (b[i]) printf( %lld , i - 900000), b[i]--, t++; } }
|
#include <bits/stdc++.h> using namespace std; const int oo = 3e5 + 7; unordered_map<int, vector<int>> values[2]; int t, n, q, a[oo], p[oo]; vector<int> ans; int psum(int l, int r) { return p[r] - (l ? p[l - 1] : 0); } int first(vector<int>& list, int val) { int l = 0, r = list.size(); while (l < r) { int s = (l + r) / 2; if (list[s] >= val) r = s; else l = s + 1; } if (l == list.size()) return n * 2; return list[l]; } void problem(int l, int r) { int sum = psum(l, r); if (sum == 0) return; if (sum % 2 == 0) { ans.push_back(r); problem(l, r - 1); return; } int pl = p[l] - a[l]; int vals[2] = {pl + (sum + 1) / 2 - 1, pl + (sum - 1) / 2 + 1}; for (int i = 0; i < 2; i++) { int pans = first(values[i][vals[i]], l); if (pans <= r) { ans.push_back(pans); return; } } throw 69; } void solve() { cin >> n >> q; string ss; cin >> ss; for (int i = 0; i < n; i++) a[i] = (ss[i] == + ? 1 : -1) * (i % 2 == 0 ? -1 : 1); p[0] = a[0]; for (int i = 1; i < n; i++) p[i] = p[i - 1] + a[i]; for (int i = 0; i < n; i++) values[(a[i] + 1) / 2][p[i]].push_back(i); while (q--) { int l, r; cin >> l >> r; l--, r--; problem(l, r); cout << ans.size() << endl; for (int e : ans) cout << e + 1 << ; cout << endl; ans.clear(); } values[0].clear(); values[1].clear(); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) solve(); }
|
// nios_dut_mm_interconnect_0_avalon_st_adapter_004.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_004 #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_004_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
`include "bch_defs.vh"
module xilinx_noinv #(
parameter T = 3,
parameter DATA_BITS = 5
) (
input clk_in,
input in,
output reg out = 0
);
`include "bch_params.vh"
localparam P = bch_params(DATA_BITS, T);
localparam IN = `BCH_SYNDROMES_SZ(P) + 2;
localparam OUT = `BCH_SIGMA_SZ(P) + `BCH_ERR_SZ(P) + 2;
wire start;
wire [`BCH_SYNDROMES_SZ(P)-1:0] syndromes;
wire ack_done;
wire done;
wire ready;
wire [`BCH_SIGMA_SZ(P)-1:0] sigma;
wire [`BCH_ERR_SZ(P)-1:0] err_count;
(* KEEP = "TRUE" *)
reg [IN-1:0] all;
(* KEEP = "TRUE" *)
reg [OUT-1:0] out_all;
(* KEEP = "TRUE" *)
reg in1, in2, out1;
wire out2;
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
assign start = all[0];
assign ack_done = all[1];
assign syndromes = all >> 2;
assign out2 = out_all[0];
always @(posedge clk) begin
in1 <= in;
in2 <= in1;
out <= out1;
out1 <= out2;
all <= (all << 1) | in2;
if (done)
out_all <= {done, ready, sigma, err_count};
else
out_all <= out_all >> 1;
end
bch_sigma_bma_noinv #(P) u_bma (
.clk(clk),
.start(start),
.ready(ready),
.syndromes(syndromes),
.sigma(sigma),
.done(done),
.ack_done(ack_done),
.err_count(err_count)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long M = 100100 * 5; const long long N = 50005; long long m, b, k; map<long long, long long> fre; int v1[M], mmax; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> m; for (int i = 0; i < m; i++) { cin >> b; fre[b]++; } for (int i = 0; i < N; i++) { if (fre[i]) v1[k] = i, k++, fre[i]--, mmax = max(mmax, i); } for (int i = mmax - 1; i >= 0; i--) { if (fre[i]) v1[k] = i, k++; } cout << k << endl; for (int i = 0; i < k; i++) cout << v1[i] << ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; const int inf = 1e9; const long long inff = 1e18; const long long mod = 1e9 + 7; int a[maxn]; vector<int> v[maxn]; vector<int> tmp; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); int _1 = 0, _2 = 0; int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = n; i >= 1; i--) { if (a[i] == 1) { v[_1 + 1].push_back(i); _1++; } else if (a[i] == 2) { _2++; if (_2 > _1) return cout << -1 << endl, 0; v[_2].push_back(i); } else if (a[i] == 3) { if (_2 > 0) { v[1].push_back(i); } else { v[1].push_back(i); _2++; if (_2 > _1) return cout << -1 << endl, 0; } } } int cntt = 1; vector<pair<int, int> > ans; for (int i = 1; i <= n; i++) { reverse((v[i]).begin(), (v[i]).end()); for (int j = 0; j < ((int)(v[i]).size()); j++) { if (a[v[i][j]] >= 2) { ans.push_back({cntt, v[i][j]}); ans.push_back({cntt, v[i][j + 1]}); cntt++; } else { if (((int)(v[i]).size()) == 1 || a[v[i][j - 1]] == 3) { ans.push_back({cntt, v[i][j]}); cntt++; } } } } cout << ((int)(ans).size()) << endl; for (pair<int, int> i : ans) cout << i.first << << i.second << endl; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_RAMB18E1
#(
.LOC("RAMB18_X2Y120"),
.DOA_REG(1'b1),
.DOB_REG(1'b0),
.INIT_A(18'b001000001000010101),
.INIT_B(18'b001111100001101011),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b1),
.IS_RSTRAMB_INVERTED(1'b1),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b1),
.RDADDRCHANGEA("FALSE"),
.RDADDRCHANGEB("FALSE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(1),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SRVAL_A(18'b110111110110100101),
.SRVAL_B(18'b000001011100001111),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 24]),
.dout(dout[ 0 +: 8])
);
endmodule
// ---------------------------------------------------------------------
module my_RAMB18E1 (input clk, input [23:0] din, output [7:0] dout);
parameter LOC = "";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RDADDRCHANGEA = "FALSE";
parameter RDADDRCHANGEB = "FALSE";
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
(* LOC=LOC *)
RAMB18E2 #(
.INITP_00(256'b0),
.INITP_01(256'b0),
.INITP_02(256'b0),
.INITP_03(256'b0),
.INITP_04(256'b0),
.INITP_05(256'b0),
.INITP_06(256'b0),
.INITP_07(256'b0),
.INIT_00(256'b0),
.INIT_01(256'b0),
.INIT_02(256'b0),
.INIT_03(256'b0),
.INIT_04(256'b0),
.INIT_05(256'b0),
.INIT_06(256'b0),
.INIT_07(256'b0),
.INIT_08(256'b0),
.INIT_09(256'b0),
.INIT_0A(256'b0),
.INIT_0B(256'b0),
.INIT_0C(256'b0),
.INIT_0D(256'b0),
.INIT_0E(256'b0),
.INIT_0F(256'b0),
.INIT_10(256'b0),
.INIT_11(256'b0),
.INIT_12(256'b0),
.INIT_13(256'b0),
.INIT_14(256'b0),
.INIT_15(256'b0),
.INIT_16(256'b0),
.INIT_17(256'b0),
.INIT_18(256'b0),
.INIT_19(256'b0),
.INIT_1A(256'b0),
.INIT_1B(256'b0),
.INIT_1C(256'b0),
.INIT_1D(256'b0),
.INIT_1E(256'b0),
.INIT_1F(256'b0),
.INIT_20(256'b0),
.INIT_21(256'b0),
.INIT_22(256'b0),
.INIT_23(256'b0),
.INIT_24(256'b0),
.INIT_25(256'b0),
.INIT_26(256'b0),
.INIT_27(256'b0),
.INIT_28(256'b0),
.INIT_29(256'b0),
.INIT_2A(256'b0),
.INIT_2B(256'b0),
.INIT_2C(256'b0),
.INIT_2D(256'b0),
.INIT_2E(256'b0),
.INIT_2F(256'b0),
.INIT_30(256'b0),
.INIT_31(256'b0),
.INIT_32(256'b0),
.INIT_33(256'b0),
.INIT_34(256'b0),
.INIT_35(256'b0),
.INIT_36(256'b0),
.INIT_37(256'b0),
.INIT_38(256'b0),
.INIT_39(256'b0),
.INIT_3A(256'b0),
.INIT_3B(256'b0),
.INIT_3C(256'b0),
.INIT_3D(256'b0),
.INIT_3E(256'b0),
.INIT_3F(256'b0),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RDADDRCHANGEA(RDADDRCHANGEA),
.RDADDRCHANGEB(RDADDRCHANGEB),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B)
) ram (
// Port A Address/Control Signals inputs: Port A address and control signals
.ADDRARDADDR(din[0]), // 14-bit input: A/Read port address
.ADDRENA(din[1]), // 1-bit input: Active-High A/Read port address enable
.CLKARDCLK(din[2]), // 1-bit input: A/Read port clock
.ENARDEN(din[3]), // 1-bit input: Port A enable/Read enable
.REGCEAREGCE(din[4]), // 1-bit input: Port A register enable/Register enable
.RSTRAMARSTRAM(din[5]), // 1-bit input: Port A set/reset
.RSTREGARSTREG(din[6]), // 1-bit input: Port A register set/reset
.WEA(1'b0), // 2-bit input: Port A write enable
// Port A Data inputs: Port A data
.DINADIN(din[7]), // 16-bit input: Port A data/LSB data
.DINPADINP(din[8]), // 2-bit input: Port A parity/LSB parity
// Port B Address/Control Signals inputs: Port B address and control signals
.ADDRBWRADDR(din[9]), // 14-bit input: B/Write port address
.ADDRENB(din[10]), // 1-bit input: Active-High B/Write port address enable
.CLKBWRCLK(din[11]), // 1-bit input: B/Write port clock
.ENBWREN(din[12]), // 1-bit input: Port B enable/Write enable
.REGCEB(din[13]), // 1-bit input: Port B register enable
.RSTRAMB(din[14]), // 1-bit input: Port B set/reset
.RSTREGB(din[15]), // 1-bit input: Port B register set/reset
.SLEEP(din[16]), // 1-bit input: Sleep Mode
.WEBWE(din[17]), // 4-bit input: Port B write enable/Write enable
// Port B Data inputs: Port B data
.DINBDIN(din[18]), // 16-bit input: Port B data/MSB data
.DINPBDINP(din[19]), // 2-bit input: Port B parity/MSB parity
// Port A Data outputs: Port A data
.DOUTADOUT(dout[0]), // 16-bit output: Port A data/LSB data
.DOUTPADOUTP(dout[1]), // 2-bit output: Port A parity/LSB parity
// Port B Data outputs: Port B data
.DOUTBDOUT(dout[2]), // 16-bit output: Port B data/MSB data
.DOUTPBDOUTP(dout[3])); // 2-bit output: Port B parity/MSB parity
endmodule
|
#include <bits/stdc++.h> using namespace std; int k; bool primes[200000][100]; int okay[5000000]; int okayN; int nLeft[1000]; bool isPrime[1000]; bool used[5000000]; vector<int> ans; bool compare(int a, int b) { if (nLeft[a] > nLeft[b]) return 1; if (nLeft[a] < nLeft[b]) return 0; return (a < b); } int main() { scanf( %d , &k); okayN = 1; okay[0] = 1; isPrime[1] = 0; for (int p = 2; true; ++p) { bool prime = 1; for (int i = 2; i * i <= p; ++i) { if (p % i == 0) prime = 0; } if (!prime) { isPrime[p] = 0; continue; } isPrime[p] = 1; for (int i = okayN - 1; i >= 0; --i) { int j = okay[i] * p; while (j <= 2 * k * k) { for (int m = 2; m < p; ++m) primes[okayN][m] = primes[i][m]; primes[okayN][p] = 1; okay[okayN++] = j; j *= p; } } for (int i = 2; i <= p; ++i) nLeft[i] = (k + 1) / 2; int need[1000]; int needN = 0; for (int i = 2; i <= p; ++i) if (isPrime[i]) need[needN++] = i; for (int i = 0; i < okayN; ++i) used[i] = 0; bool ok = 1; bool anybad = 0; ans.clear(); while (ans.size() < k) { int best = 0; for (int i = 1; i < okayN; ++i) { if (used[i]) continue; for (int j = 0; j < needN; ++j) { if (primes[i][need[j]] && !primes[best][need[j]]) { best = i; break; } if (!primes[i][need[j]] && primes[best][need[j]]) { break; } } } ans.push_back(okay[best]); if (used[best]) { ok = 0; break; } used[best] = 1; anybad = 0; for (int j = 0; j < needN; ++j) { if (nLeft[need[j]]) anybad = 1; if (primes[best][need[j]] && nLeft[need[j]]) --nLeft[need[j]]; } sort(need, need + needN, compare); } if (ok && !anybad) { for (int i = 0; i < ans.size(); ++i) printf( %d , ans[i]); return 0; } } return 0; }
|
// Implements GPIO pins from the PS/EMIO
// Works with 7010 (24 pins) or 7020 (48 pins) and
// either single-ended or differential IO
module parallella_gpio_emio
(/*AUTOARG*/
// Outputs
PS_GPIO_I,
// Inouts
GPIO_P, GPIO_N,
// Inputs
PS_GPIO_O, PS_GPIO_T
);
parameter NUM_GPIO_PAIRS = 24; // 12 or 24
parameter DIFF_GPIO = 0; // 0 or 1
parameter NUM_PS_SIGS = 64;
inout [NUM_GPIO_PAIRS-1:0] GPIO_P;
inout [NUM_GPIO_PAIRS-1:0] GPIO_N;
output [NUM_PS_SIGS-1:0] PS_GPIO_I;
input [NUM_PS_SIGS-1:0] PS_GPIO_O;
input [NUM_PS_SIGS-1:0] PS_GPIO_T;
genvar m;
generate
if( DIFF_GPIO == 1 ) begin: GPIO_DIFF
IOBUFDS
#(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("LVDS_25"),
.SLEW("FAST")
)
GPIOBUF_DS [NUM_GPIO_PAIRS-1:0]
(
.O(PS_GPIO_I), // Buffer output
.IO(GPIO_P), // Diff_p inout (connect directly to top-level port)
.IOB(GPIO_N), // Diff_n inout (connect directly to top-level port)
.I(PS_GPIO_O), // Buffer input
.T(PS_GPIO_T) // 3-state enable input, high=input, low=output
);
end else begin: GPIO_SE // single-ended
wire [NUM_GPIO_PAIRS-1:0] gpio_i_n, gpio_i_p;
wire [NUM_GPIO_PAIRS-1:0] gpio_o_n, gpio_o_p;
wire [NUM_GPIO_PAIRS-1:0] gpio_t_n, gpio_t_p;
// Map P/N pins to single-ended signals
for(m=0; m<NUM_GPIO_PAIRS; m=m+2) begin : assign_se_sigs
assign PS_GPIO_I[2*m] = gpio_i_n[m];
assign PS_GPIO_I[2*m+1] = gpio_i_n[m+1];
assign PS_GPIO_I[2*m+2] = gpio_i_p[m];
assign PS_GPIO_I[2*m+3] = gpio_i_p[m+1];
assign gpio_o_n[m] = PS_GPIO_O[2*m];
assign gpio_o_n[m+1] = PS_GPIO_O[2*m+1];
assign gpio_o_p[m] = PS_GPIO_O[2*m+2];
assign gpio_o_p[m+1] = PS_GPIO_O[2*m+3];
assign gpio_t_n[m] = PS_GPIO_T[2*m];
assign gpio_t_n[m+1] = PS_GPIO_T[2*m+1];
assign gpio_t_p[m] = PS_GPIO_T[2*m+2];
assign gpio_t_p[m+1] = PS_GPIO_T[2*m+3];
end // block: assign_se_sigs
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
GPIOBUF_SE_N [NUM_GPIO_PAIRS-1:0]
(
.O(gpio_i_n), // Buffer output
.IO(GPIO_N), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_n), // Buffer input
.T(gpio_t_n) // 3-state enable input, high=input, low=output
);
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
GPIOBUF_SE_P [NUM_GPIO_PAIRS-1:0]
(
.O(gpio_i_p), // Buffer output
.IO(GPIO_P), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_p), // Buffer input
.T(gpio_t_p) // 3-state enable input, high=input, low=output
);
end // block: GPIO_SE
endgenerate
// Tie unused PS signals back to themselves
genvar n;
generate for(n=NUM_GPIO_PAIRS*2; n<48; n=n+1) begin : unused_ps_sigs
assign PS_GPIO_I[n]
= PS_GPIO_O[n] &
~PS_GPIO_T[n];
end
endgenerate
endmodule // parallella_gpio_emio
/*
File: parallella_gpio_emio.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2014 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hd__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_1_V
`define SKY130_FD_SC_HD__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; cout << max(abs(y2 - y1), abs(x2 - x1)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int a[1010]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } sort(a, a + n); if (a[0] == 1) { printf( -1 n ); } else { printf( 1 n ); } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long rowNum[] = {-1, 0, 0, 1}; long long colNum[] = {0, -1, 1, 0}; int main() { int n, d, h; cin >> n >> d >> h; if (d > n - 1 || d < h || d > 2 * h || (n > 2 && h < 2 && d == h)) { cout << -1 n ; return 0; } int prev = 0; for (long long i = 1; i < h + 1; i++) { cout << prev + 1 << << i + 1 << endl; prev = i; } if (d == h) { for (long long i = h + 1; i < n; i++) { cout << 2 << i + 1 << endl; } return 0; } prev = 0; for (long long i = h + 1; i < d + 1; i++) { cout << prev + 1 << << i + 1 << endl; prev = i; } for (long long i = d + 1; i < n; i++) { cout << 1 << i + 1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long dp = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n, a; cin >> n >> a; vector<int> vec(n); int cnt = 0; for (int i = 0; i < n; i++) { cin >> vec[i]; if (vec[i]) cnt++; } for (int i = 0; i < a; i++) { if (vec[a - 1 - i] + vec[a - 1 + i] == 1) cnt--; if (i >= n - a) break; } cout << cnt << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_TB_V
`define SKY130_FD_SC_HVL__AND2_TB_V
/**
* and2: 2-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__and2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_TB_V
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: shifter.v (tranlate from shifter.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from shifter.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Shifter Unit
// AUTHOR: Steve Rhoads ()
// Matthias Gruenewald
// DATE CREATED: 2/2/01
// FILENAME: shifter.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software \'as is\' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements the 32-bit shifter unit.
//-------------------------------------------------------------------
module shifter (value, shift_amount, shift_func, c_shift);
input [31:0] value;
input [ 4:0] shift_amount;
input [ 1:0] shift_func;
output [31:0] c_shift;
// type shift_function_type is (
// shift_nothing, shift_left_unsigned,
// shift_right_signed, shift_right_unsigned);
wire [31: 0] shift1L ;
wire [31: 0] shift2L ;
wire [31: 0] shift4L ;
wire [31: 0] shift8L ;
wire [31: 0] shift16L;
wire [31: 0] shift1R ;
wire [31: 0] shift2R ;
wire [31: 0] shift4R ;
wire [31: 0] shift8R ;
wire [31: 0] shift16R;
wire [31:16] fills ;
assign fills = (shift_func == `shift_right_signed &
value[31]) ? 16'b1111111111111111 : 16'b0000000000000000;
assign shift1L = (shift_amount[0]) ? {value [30:0], 1'b0} :value;
assign shift2L = (shift_amount[1]) ? {shift1L[29:0], 2'b0} :shift1L;
assign shift4L = (shift_amount[2]) ? {shift2L[27:0], 4'b0} :shift2L;
assign shift8L = (shift_amount[3]) ? {shift4L[23:0], 8'b0} :shift4L;
assign shift16L = (shift_amount[4]) ? {shift8L[15:0], 16'b0} :shift8L;
assign shift1R = (shift_amount[0]) ? {fills[31], value[31:1]}:value;
assign shift2R = (shift_amount[1]) ? {fills[31:30],shift1R[31: 2]}: shift1R;
assign shift4R = (shift_amount[2]) ? {fills[31:28],shift2R[31: 4]}: shift2R;
assign shift8R = (shift_amount[3]) ? {fills[31:24],shift4R[31: 8]}: shift4R;
assign shift16R = (shift_amount[4]) ? {fills[31:16],shift8R[31:16]}: shift8R;
`ifdef shifter_type_GENERIC
reg [31:0] c_shift;
/*
assign c_shift = (shift_func == `shift_left_unsigned) ? shift16L :
(shift_func == `shift_right_unsigned |
shift_func == `shift_right_signed) ? shift16R : `ZERO ;
*/
always @(shift_func or shift16L or shift16R) begin
case(shift_func) // synopsys parallel_case
`shift_left_unsigned : c_shift = shift16L;
`shift_right_unsigned,
`shift_right_signed : c_shift = shift16R;
default : c_shift = `ZERO;
endcase
end
`endif
`ifdef shifter_type_TRISTATE
wire [31:0] c_shift;
assign c_shift = (shift_func == `shift_left_unsigned) ? shift16L:{32{1'bz}};
assign c_shift = (shift_func == `shift_right_unsigned |
shift_func == `shift_right_signed) ? shift16R:{32{1'bz}};
assign c_shift = (shift_func == `shift_nothing) ? `ZERO : {32{1'bz}} ;
`endif
endmodule
|
module taxicab_distance #(parameter N = 32)(
input [N-1:0] x1, y1, x2, y2,
output [N+1:0] dist
);
wire signed [N:0] dist_x12, dist_x21, dist_xabs, dist_y12, dist_y21, dist_yabs;
/*SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .S(dist_x12[N-1:0]), .CO(dist_x12[N]));
SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .S(dist_x21[N-1:0]), .CO(dist_x21[N]));*/
SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .D(dist_x12));
SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .D(dist_x21));
MUX #(.N(N+1)) abs_x (.A(dist_x12), .B(dist_x21), .S(dist_x12[N]), .O(dist_xabs));
/*SUB_1 #(.N(N)) diff_y12 (.A(y1), .B(y2), .S(dist_y12[N-1:0]), .CO(dist_y12[N]));
SUB_1 #(.N(N)) diff_y21 (.A(y2), .B(y1), .S(dist_y21[N-1:0]), .CO(dist_y21[N]));*/
SUB_1 #(.N(N)) diff_y12 (.A(y1), .B(y2), .D(dist_y12));
SUB_1 #(.N(N)) diff_y21 (.A(y2), .B(y1), .D(dist_y21));
MUX #(.N(N+1)) abs_y (.A(dist_y12), .B(dist_y21), .S(dist_y12[N]), .O(dist_yabs));
ADD #(.N(N+1))t_d (.A(dist_xabs), .B(dist_yabs), .CI(1'b0), .S(dist[N:0]), .CO(dist[N+1]));
endmodule
module SUB_1 #(parameter N = 32)(
input [N-1:0] A, B,
output [N:0] D
);
wire CO;
assign D[N] = ~CO;
ADD
#(
.N(N)
)
ADD_
(
.A(A),
.B(~B),
.CI(1'b1),
.S(D[N-1:0]),
.CO(CO)
);
endmodule
|
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Top level control.
//
// Revision Information:
// Date Description
//
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
//
// *********************************************************************/
// ------------------------------------------------------
// AS:
// - remove auto fill and auto empty ports/ function
// - remove frame count and associated signals
// - remove tx_fifo_
// ------------------------------------------------------
module spi_control # (
// AS: added parameters
parameter CFG_FRAME_SIZE = 4
)( input pclk,
input presetn,
input psel,
input penable,
input pwrite,
input [6:0] paddr,
input [CFG_FRAME_SIZE-1:0] wr_data_in,
//input [15:0] cfg_framecnt,
//input auto_fill,
//input auto_empty,
input cfg_master,
//input rx_fifo_first, // not really needed anymore
input rx_fifo_empty,
// -----------------------
// AS: added tx_fifo_empty
// -----------------------
input tx_fifo_empty,
//input clear_frame_count,
//input fill_okay,
output [CFG_FRAME_SIZE-1:0] tx_fifo_data,
output tx_fifo_write,
output tx_fifo_last,
output rx_fifo_read
);
//######################################################################################################
reg tx_fifo_write_sig;
reg rx_fifo_read_sig;
//reg [15:0] txrx_frame_count_d; //frame count
//reg [15:0] txrx_frame_count_q;
reg tx_last_frame_sig;
//reg auto_write;
//reg auto_read;
// Output assignments.
// AS: modified tx_fifo_last to be dependent on tx_fifo_empty (undone)
assign tx_fifo_last = tx_last_frame_sig;
//assign tx_fifo_last = tx_last_frame_sig && tx_fifo_empty;
assign tx_fifo_data = wr_data_in;
assign tx_fifo_write = tx_fifo_write_sig;
assign rx_fifo_read = rx_fifo_read_sig;
// AS: removed counter
//always @(posedge pclk or negedge presetn)
// begin
// if (~presetn)
// begin
// txrx_frame_count_q <= 16'h0001;
// end
// else
// begin
// txrx_frame_count_q <= txrx_frame_count_d;
// end
// end
// Note combinational generation of FIFO read and write signals
always @(*)
begin
//defaults
rx_fifo_read_sig = 1'b0; //default no read on rx fifo
tx_fifo_write_sig = 1'b0; //default no write on tx fifo
tx_last_frame_sig = 1'b0; //default not last frame
//txrx_frame_count_d = txrx_frame_count_q;
if (penable && psel)
begin
case (paddr) //synthesis parallel_case
6'h0C: //write to transmit fifo
begin
if (pwrite)
begin
tx_fifo_write_sig = 1'b1; //write to the fifo
//txrx_frame_count_d = txrx_frame_count_q + 1'b1;
// *************************************************************
// AS: what to do here? not sure how tx_last_frame_sig should be
// be assigned
// *************************************************************
//if (txrx_frame_count_q == cfg_framecnt)
// begin
// tx_last_frame_sig = 1'b1;
// txrx_frame_count_d = 16'h0001;
// end
// Solution: created Aliased TX DATA register to indicate last frame
end
end
6'h08: //read from receive fifo
begin
if (~pwrite)
begin
rx_fifo_read_sig = 1'b1;
end
end
6'h28: // aliased transmit data, sets last frame bit
begin
tx_fifo_write_sig = 1'b1; //write to the fifo
tx_last_frame_sig = 1'b1; //last frame
end
default:
begin
end
endcase
end
//if (auto_write)
// begin
// tx_fifo_write_sig = 1'b1; //write to the fifo
// txrx_frame_count_d = txrx_frame_count_q + 1'b1;
// if (txrx_frame_count_q == cfg_framecnt)
// begin
// tx_last_frame_sig = 1'b1;
// txrx_frame_count_d = 16'h0001;
// end
// end
//
//if (auto_read)
// begin
// rx_fifo_read_sig = 1'b1;
// end
//
//if (clear_frame_count) txrx_frame_count_d = 16'h0001;
end
//----------------------------------------------------------------------------------
// AS: removed auto write and auto read features
//always@(posedge pclk or negedge presetn)
//begin
// if (!presetn)
// begin
// auto_write <= 1'b0;
// auto_read <= 1'b0;
// end
// else
// begin
// auto_write <= 1'b0;
// auto_read <= 1'b0;
//
// if ((auto_fill) & !auto_write & (fill_okay)) // if room in FIFOs write data
// begin
// auto_write <= 1'b1;
// end
//
// //on master empty until all frames done
// if (cfg_master && auto_empty && !auto_read && !rx_fifo_empty)
// begin
// auto_read <= 1'b1;
// end
//
// //On slave empty until start of next packet
// if (!cfg_master && auto_empty && !auto_read && !rx_fifo_first && !rx_fifo_empty)
// begin
// auto_read <= 1'b1;
// end
//
// end
//end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, q, a[501][501], x, y, s, ans; vector<int> v; int main() { ios::sync_with_stdio(false); cin >> n >> m >> q; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j]; for (int p = 1; p <= q; p++) { cin >> x >> y; if (a[x][y] == 1) a[x][y] = 0; else a[x][y] = 1; for (int i = 1; i <= n; i++) { s = 0; for (int j = 1; j <= m; j++) { if (a[i][j] == 1) s++; else s = 0; ans = max(ans, s); } } v.push_back(ans); ans = 0; } for (int i = 0; i < v.size(); i++) cout << v[i] << endl; }
|
#include <bits/stdc++.h> using namespace std; double dp[110][110][110] = {0}; double c[110][110] = {0}; int a[110], n, m; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) scanf( %d , &a[i]); for (int i = 0; i <= n + m; ++i) c[i][0] = 1; for (int i = 1; i <= n + m; ++i) for (int j = 1; j <= i; ++j) c[i][j] = c[i - 1][j - 1] + c[i - 1][j]; for (int i = 0; i <= m; ++i) dp[i][0][0] = 1; for (int i = 1; i <= m; ++i) for (int j = 1; j <= n; ++j) for (int k = 0; k <= j; ++k) { int l = max(a[i] * (k - 1) + 1, 0), r = a[i] * k; for (int w = 0; w <= k; ++w) for (int p = l; p <= min(r, j); ++p) dp[i][j][k] += dp[i - 1][j - p][w] * c[n - j + p][p]; for (int p = 0; p <= min(l - 1, j); ++p) dp[i][j][k] += dp[i - 1][j - p][k] * c[n - j + p][p]; } double ans = 0; for (int i = 1; i <= n; ++i) ans += dp[m][n][i] * i; for (int i = 1; i <= n; ++i) ans /= (double)m; printf( %.10lf , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_BLACKBOX_V
`define SKY130_FD_SC_HD__A211O_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211o (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_BLACKBOX_V
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test triggers constant propagation through AND gates.
*/
module main;
wire a = 1'b0;
wire b = 1'b1;
wire c = 1'b1;
wire d = 1'bx;
wire out0, out1, out2, out3;
and (out0, a, b); // Should be 0
and (out1, b, c); // Should be 1
and (out2, a, d); // Should be 0 because of a
and (out3, b, d); // Should be x
initial begin
#0 if (out0 !== 1'b0) begin
$display("FAILED -- out0 = %b", out0);
$finish;
end
if (out1 !== 1'b1) begin
$display("FAILED -- out1 = %b", out1);
$finish;
end
if (out2 !== 1'b0) begin
$display("FAILED -- out2 = %b", out2);
$finish;
end
if (out3 !== 1'bx) begin
$display("FAILED -- outx = %b", out3);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; struct node { int l, r; } ar[300000]; bool compare(node a, node b) { if (a.r != b.r) return a.r < b.r; else return a.l < b.l; } vector<pair<int, int> > vectl, vectn, temp; int main() { int n, i, m, flag = 0; scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { scanf( %d%d , &ar[i].l, &ar[i].r); } sort(ar, ar + m, compare); int col = -1; for (int j = 0; j < m; j++) { if (ar[j].r != col) { ar[i].l = n + 1; ar[i].r = ar[j].r; col = ar[j].r; i++; } } m = i; sort(ar, ar + m, compare); int row = ar[0].l, lastrow = 1, lastcol = ar[0].r; i = 0; col = ar[i].r; while (ar[i].r == col) { if (ar[i].l > lastrow) vectl.push_back(make_pair(lastrow, ar[i].l - 1)); lastrow = ar[i].l + 1; i++; if (col == 1) { while (ar[i].r == 1) i++; break; } } col = ar[i].r; while (i < m) { if (ar[i].r > lastcol + 1) { int st = vectl[0].first; lastrow = 1; while (ar[i].r == col) { if (ar[i].l > lastrow && ar[i].l > st) { vectn.push_back(make_pair(lastrow, ar[i].l - 1)); } lastrow = ar[i].l + 1; i++; if (i >= m) break; } } else { int j = 0; lastrow = 1; while (ar[i].r == col) { while (j < vectl.size() && vectl[j].second < lastrow) j++; if (j == vectl.size()) { while (i < m && ar[i].r == col) i++; break; } lastrow = max(vectl[j].first, lastrow); if (ar[i].l > lastrow) { vectn.push_back(make_pair(lastrow, ar[i].l - 1)); } lastrow = ar[i].l + 1; i++; if (i >= m) break; } } if (i >= m) { vectl = vectn; lastcol = ar[i - 1].r; if (vectl.size() == 0) { flag = 1; } break; } lastcol = col; col = ar[i].r; vectl = vectn; vectn.clear(); if (vectl.size() == 0) { flag = 1; break; } } if (flag == 1) printf( -1 n ); else if (lastcol != n) printf( %d n , n + n - 2); else if (vectl[vectl.size() - 1].second == n) printf( %d n , n + n - 2); else printf( -1 n ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkinv (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const long long int maxn = 1e5 + 6; const long long int MOD = 1e9 + 7; vector<int> prim(1000005, 1); int fact[maxn]; long long int binomialCoeff(long long int n, long long int k) { long long int res = 1; if (k > n - k) k = n - k; for (long long int i = 0; i < k; ++i) { res *= (n - i); res /= (i + 1); } return res; } bool isVowel(char ch) { if (ch == a || ch == i || ch == e || ch == u || ch == o ) { return true; } return false; } long long int power(long long int x, long long int i, long long int mod) { long long int ans = 1; while (i > 0) { if (i & 1) ans = (ans * x) % mod; i >>= 1; x = (x * x) % mod; } return ans; } long long int modInverse(long long int x, long long int mod) { return power(x, mod - 2, mod); } int nCr(int n, int r) { if (n < r) { return 0; } return (((fact[n] * modInverse(fact[n - r], MOD)) % MOD) * modInverse(fact[r], MOD)) % MOD; } long long int power(int x, unsigned int y) { long long int temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp; else return x * temp * temp; } void erath(int n) { prim[1] = 0; prim[0] = 0; prim[2] = 1; for (int i = 2; i * i <= n; i++) { if (prim[i]) { for (int j = i * i; j <= n; j += i) { prim[j] = 0; } } } } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int lcm(long long int a, long long int b) { return (a / gcd(a, b)) * b; } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int n, m, k; int getmid(int l, int r) { return (l + (r - l) / 2); } struct segtree { int siz; vector<pair<long long int, long long int> > sums; void init(int n) { siz = 1; while (siz < n) siz *= 2; sums.assign(2 * siz, {LONG_MAX, 0}); } void set(int i, int v, int cur, int l, int r) { if (r - l == 1) { sums[cur].first = v; sums[cur].second = 1; return; } int m = getmid(l, r); if (i < m) { set(i, v, 2 * cur + 1, l, m); } else set(i, v, 2 * cur + 2, m, r); sums[cur].first = min(sums[2 * cur + 1].first, sums[2 * cur + 2].first); if (sums[2 * cur + 1].first == sums[cur].first && sums[2 * cur + 2].first == sums[cur].first) { sums[cur].second = sums[cur * 2 + 1].second + sums[cur * 2 + 2].second; } else if (sums[2 * cur + 1].first == sums[cur].first) { sums[cur].second = sums[cur * 2 + 1].second; } else { sums[cur].second = sums[cur * 2 + 2].second; } } void set(int i, int v) { set(i, v, 0, 0, siz); } pair<long long int, long long int> sum(int l, int r, int cur, int lx, int rx) { if (lx >= r || l >= rx) return {LONG_MAX, 0}; if (lx >= l && rx <= r) return {sums[cur].first, sums[cur].second}; int mid = getmid(lx, rx); pair<long long int, long long int> s1 = sum(l, r, 2 * cur + 1, lx, mid), s2 = sum(l, r, 2 * cur + 2, mid, rx); if (s1.first < s2.first) { return s1; } else if (s1.first > s2.first) return s2; else return {s1.first, s1.second + s2.second}; } pair<long long int, long long int> sum(int l, int r) { return sum(l, r, 0, 0, siz); } }; int nCrModp(int n, int r, int p) { if (r > n - r) r = n - r; int C[r + 1]; memset(C, 0, sizeof(C)); C[0] = 1; for (int i = 1; i <= n; i++) { for (int j = min(i, r); j > 0; j--) C[j] = (C[j] + C[j - 1]) % p; } return C[r]; } void ans(int top) { cin >> n >> k; long long int h[n], mx = INT_MIN, mn = INT_MAX; vector<long long int> fin(200002, 0); for (int i = 0; i < n; i++) { cin >> h[i]; if (h[i] > 0) fin[1] += 1; if (h[i] > 0) fin[h[i] + 1] -= 1; mx = max(mx, h[i]); mn = min(mn, h[i]); } for (int i = 1; i < mx + 1; i++) { fin[i] += fin[i - 1]; } int i = mx, ans = 0; while (i > mn) { int j = i, sum = 0; while (sum + fin[j] <= k) { sum += fin[j]; j--; } i = j; ans++; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1, co = 1; while (t--) { ans(co); co++; } return 0; }
|
module t;
/*fifo_s AUTO_TEMPLATE (
.ignored_signal (1'b1),
.out_signal (NC),
.out_bus (out_bus[]),
);
*/
fifo_s data_fifo (
//fifo_s data_fifo (
// Inputs
.clk (fifo_clk),
/*AUTOINST*/
// Outputs
.out_bus (out_bus[31:0]), // Templated
.out_signal (NC), // Templated
// Inputs
.ignored_signal (1'b1), // Templated
.reset (reset));
/*fifo_s AUTO_TEMPLATE (
.ignored_signal (1'b1),
.out_signal (NC),
.out_bus (out_bus[]),
);
*/
//fifo_s data_fifo (
fifo_s data_fifo (
// Inputs
.clk (fifo_clk),
/*AUTOINST*/
// Outputs
.out_bus (out_bus[31:0]), // Templated
.out_signal (NC), // Templated
// Inputs
.ignored_signal (1'b1), // Templated
.reset (reset));
endmodule
module fifo_s;
input ignored_signal;
input reset;
output [31:0] out_bus;
output out_signal;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, t = 0, min, d = 0; cin >> n >> m; int a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> a[i][j]; } vector<vector<int>> b(2, vector<int>(m, -1)); vector<vector<int>> c(n, vector<int>(2, -1)); for (int i = 0; i < m; i++) { min = -1; for (int j = 0; j < n; j++) { if (a[j][i] == 1 && min == -1) { b[0][i] = j; min = 0; } if (a[j][i] == 1) b[1][i] = j; } } for (int i = 0; i < n; i++) { min = -1; for (int j = 0; j < m; j++) { if (a[i][j] == 1 && min == -1) { c[i][0] = j; min = 0; } if (a[i][j] == 1) c[i][1] = j; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == 0) { if (b[0][j] < i && b[0][j] != -1) d++; if (b[1][j] > i && b[1][j] != -1) d++; if (c[i][0] < j && c[i][0] != -1) d++; if (c[i][1] > j && c[i][1] != -1) d++; } } } cout << d; }
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps
// ============================================================
// File Name: Line_Buffer.v
// Megafunction Name(s):
// altshift_taps
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Line_Buffer (
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x);
input clken;
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [11:0] taps0x;
output [11:0] taps1x;
wire [23:0] sub_wire0;
wire [11:0] sub_wire3;
wire [23:12] sub_wire1 = sub_wire0[23:12];
wire [11:0] sub_wire2 = sub_wire0[11:0];
wire [11:0] taps1x = sub_wire1[23:12];
wire [11:0] taps0x = sub_wire2[11:0];
wire [11:0] shiftout = sub_wire3[11:0];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire3));
defparam
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 2,
altshift_taps_component.tap_distance = 1280,
altshift_taps_component.width = 12;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// clocker module for simulation
module clocker(
input wire clk1,
input wire clk2,
input wire clksel,
input wire divsel,
output wire clkout
);
/*
êàê áëÿòü òóò ïåðåêëþ÷èòü êëîêè?
ñíà÷àëà clksel ðåñèíõðèì ïî âûõîäíîìó êëîêó, êàê ïðîéä¸ò -
âûõîäíîé êëîê âûêëþ÷èëè
ïîòîì ïî íîâîìó âõîäíîìó êëîêó óæå ïðîðåñèíõðåííîå ïðîãîíÿåì
åùå ðàç ðåñèíõðÿ - è êàê ïðîøëî, âêëþ÷àåì âûõîä îïÿòü
*/
/*
* âûøå íàïèñàíà õóåòà!11
*/
wire midck,ck;
reg cksel,midsel;
reg ckon;
reg divby2,idiv;
initial
begin
ckon = 1'b1;
cksel = 1'b0;
midsel = 1'b0;
end
assign midck = midsel ? clk2 : clk1;
always
begin
@(negedge ck);
if( cksel!=clksel )
begin
ckon <= 1'b0;
midsel <= clksel;
repeat(2) @(negedge midck);
ckon <= 1'b1;
cksel <= midsel;
end
end
assign ck = ckon ? (cksel ? clk2 : clk1) : 1'b0;
initial
begin
divby2 = 1'b0;
idiv=1'b0;
end
always @(posedge ck)
divby2 <= ~divby2;
always @(posedge divby2)
idiv <= divsel;
assign clkout = idiv ? divby2 : ck;
endmodule
|
/*
* NAME
* ----
*
* bar_leds-test.v - test module for 'bar_leds.v'
*
* INTRODUCTION
* ------------
*
* TODO
*
* AUTHOR
* ------
*
* Jeremiah Mahler <>
*
*/
`include "bar_leds.v"
module test;
wire ce;
wire [8:1] data;
wire rw;
wire [8:1] leds;
bar_leds bar_leds1(ce, data, rw, leds);
// registers for assigning to wires
reg cer;
assign ce = cer;
reg rwr;
assign rw = rwr;
reg [8:1] datar;
assign data = datar;
reg read_data;
initial begin
$dumpfile("output.vcd");
$dumpvars(0,test);
parameter READ = 1'b1;
parameter WRITE = 1'b0;
parameter ENABLE = 1'b1;
parameter DISABLE = 1'b0;
// initialize
#1;
ce = DISABLE;
//datar = 8'h00;
datar = 8'bz;
rwr = 1;
// ### WRITE ###
// IMPORTANT - Nothing else should be driving the bus or else
// bad things could happen.
#1 datar = 8'h4f; // start driving the outputs
#1 rwr = WRITE;
#1 ce = ENABLE; // enable, triggers a write
// value should have been written
#1 ce = DISABLE;
datar = 8'hz; // stop driving the outputs
// ### READ ###
#1 rwr = READ;
#1 ce = ENABLE;
// data should be ready
#1 read_data = datar;
#1 ce = DISABLE;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; string s; int f(int id) { string t; for (int j = id; j < s.size(); j++) { t.push_back(s[j]); } t.push_back( # ); for (int j = 0; j < id; j++) { t.push_back(s[j]); } int mx = 0; vector<int> z(t.size() + 1); for (int i = 1, l = 0, r = 0; i < t.size(); i++) { if (i <= r) { z[i] = min(r - i + 1, z[i - l]); } while (i + z[i] < t.size() && t[z[i]] == t[i + z[i]]) { z[i]++; } if (i + z[i] - 1 > r) { l = i, r = i + z[i] - 1; } } for (int i = t.find( # ) + 1; i < t.size(); i++) { mx = max(mx, z[i]); } return mx; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n, a, b; cin >> n >> a >> b >> s; vector<int> maxLen(n); for (int i = 1; i < n; i++) { maxLen[i] = f(i); } vector<int> dp(n); dp[0] = a; for (int i = 1; i < n; i++) { dp[i] = dp[i - 1] + a; int min = 1e9; for (int j = 1; j <= i; j++) { int len = maxLen[j]; if (i <= j + len - 1 && dp[i] > dp[j - 1] + b) { dp[i] = dp[j - 1] + b; } } } cout << dp.back(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, count = 1, ans = 0; string input; cin >> input; for (i = 1; i < input.length(); i++) { if (input[i] != input[i - 1]) { ans += (count / 5) + (count % 5 > 0); count = 0; } count++; } ans += (count / 5) + (count % 5 > 0); cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_TB_V
`define SKY130_FD_SC_HVL__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_TB_V
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_128x16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dpram_32_128x16 (
byteena_a,
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [3:0] byteena_a;
input [31:0] data;
input [1:0] rdaddress;
input rdclock;
input [3:0] wraddress;
input wrclock;
input wren;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "128"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL rdaddress[1..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_b 0 0 128 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns/1ns
module foc_cmd
(input c,
input udp_cmd_dv,
input [31:0] udp_target_reg,
input [31:0] udp_damping_reg,
input udp_foc_active_reg,
input [31:0] temperature,
input [31:0] temperature_limit,
input ignore_temperature,
input overtemp_rst,
input [7:0] submsg_rxd,
input submsg_rxdv,
input submsg_rxlast,
output [31:0] foc_target,
output [31:0] foc_damping,
output [31:0] control_id,
output foc_active,
output float);
wire [7:0] foc_cmd_rx_control_mode;
wire [31:0] foc_cmd_rx_control_id;
wire [31:0] foc_cmd_rx_target;
wire [31:0] foc_cmd_rx_damping; // = 32'hbf80_0000;
wire foc_cmd_rx_rx;
foc_cmd_rx foc_cmd_rx_inst
(.c(c),
.submsg_rxd(submsg_rxd), .submsg_rxdv(submsg_rxdv),
.submsg_rxlast(submsg_rxlast),
.control_mode(foc_cmd_rx_control_mode),
.control_id(control_id),
.target(foc_cmd_rx_target),
.damping(foc_cmd_rx_damping),
.cmd_rx(foc_cmd_rx_rx));
wire last_cmd_from_foc_cmd;
r last_cmd_from_foc_cmd_r
(.c(c), .d(1'b1), .q(last_cmd_from_foc_cmd),
.rst(udp_cmd_dv), .en(foc_cmd_rx_rx));
wire udp_cmd_dv_d1, udp_cmd_dv_d2;
d1 udp_cmd_dv_d1_r(.c(c), .d(udp_cmd_dv), .q(udp_cmd_dv_d1));
d1 udp_cmd_dv_d2_r(.c(c), .d(udp_cmd_dv_d1), .q(udp_cmd_dv_d2));
localparam [31:0] HARD_OVERTEMP_LIMIT = 32'h42d2_0000; // 105.0 celsius
wire hard_overtemp;
fp_compare hard_overtemp_compare_r
(.clock(c), .ageb(hard_overtemp),
.dataa(temperature),
.datab(HARD_OVERTEMP_LIMIT));
wire soft_overtemp_ageb;
wire soft_overtemp = soft_overtemp_ageb & |temperature_limit;
fp_compare soft_overtemp_compare_r
(.clock(c), .ageb(soft_overtemp_ageb),
.dataa(temperature),
.datab(temperature_limit));
wire [23:0] overtemp_cnt;
r #(24) overtemp_cnt_r
(.c(c), .rst(ignore_temperature), .en(1'b1),
.d((hard_overtemp | soft_overtemp) ? overtemp_cnt + 1'b1 :
(|overtemp_cnt ? overtemp_cnt - 1'b1 : overtemp_cnt)),
.q(overtemp_cnt));
`ifdef SIM
localparam TARGET_TIMEOUT = 24'd100_000; // 1 ms
localparam ZERO_TIMEOUT = 24'd001_000;
localparam OVERTEMP_TIMEOUT = 24'd000_100;
`else
localparam TARGET_TIMEOUT = 24'd10_000_000; // 100ms timeout
localparam ZERO_TIMEOUT = 24'd10_000_000; // command zero amps for 100ms
localparam OVERTEMP_TIMEOUT = 24'd01_000_000; // 10ms overtemp timeout
`endif
localparam ST_IDLE = 4'd0;
localparam ST_RUNNING = 4'd1;
localparam ST_DRIVE_ZERO = 4'd2;
localparam ST_OVERTEMP = 4'd3;
localparam SW=4, CW=4;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire state_cnt_rst = ctrl[0];
wire [17:0] state_cnt;
r #(18) state_cnt_r
(.c(c), .rst(state_cnt_rst), .en(1'b1), .d(state_cnt+1'b1), .q(state_cnt));
always @* begin
case (state)
ST_IDLE:
if (udp_cmd_dv_d2 | foc_cmd_rx_rx) ctrl = { ST_RUNNING , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_RUNNING:
if (overtemp_cnt > OVERTEMP_TIMEOUT) ctrl = { ST_DRIVE_ZERO, 4'b0010 };
else if (timeout) ctrl = { ST_DRIVE_ZERO, 4'b0001 };
else ctrl = { ST_RUNNING , 4'b0000 };
ST_DRIVE_ZERO:
if ((udp_cmd_dv_d2 | foc_cmd_rx_rx) &
~overtemp_latch) ctrl = { ST_RUNNING , 4'b0000 };
else if (state_cnt == ZERO_TIMEOUT)
if (overtemp_latch) ctrl = { ST_OVERTEMP , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_DRIVE_ZERO, 4'b0000 };
ST_OVERTEMP:
if (~overtemp_latch) ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_OVERTEMP , 4'b0000 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
wire overtemp_latch;
r overtemp_latch_r
(.c(c), .rst(overtemp_rst), .en(ctrl[1]), .d(1'b1), .q(overtemp_latch));
wire [23:0] timeout_cnt;
r #(24) timeout_cnt_r
(.c(c), .rst(udp_cmd_dv | foc_cmd_rx_rx), .en(1'b1),
.d(timeout_cnt+1'b1), .q(timeout_cnt));
wire timeout = timeout_cnt == TARGET_TIMEOUT;
wire [31:0] next_foc_target;
d1 #(32) next_foc_target_r
(.c(c), .d(last_cmd_from_foc_cmd ? foc_cmd_rx_target : udp_target_reg),
.q(next_foc_target));
wire [31:0] next_foc_damping;
d1 #(32) next_foc_damping_r
(.c(c), .d(last_cmd_from_foc_cmd ? foc_cmd_rx_damping : udp_damping_reg),
.q(next_foc_damping));
r #(32) foc_target_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(state == ST_RUNNING ? next_foc_target : 32'h0), .q(foc_target));
r #(32) foc_damping_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(state == ST_RUNNING ? next_foc_damping : 32'h0), .q(foc_damping));
//assign foc_damping = foc_cmd_rx_damping;
assign float = state == ST_IDLE | state == ST_OVERTEMP;
assign foc_active = udp_foc_active_reg &
(state == ST_RUNNING |
state == ST_DRIVE_ZERO);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_2_V
`define SKY130_FD_SC_LP__O2111AI_2_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111ai_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; int a[7]; for (int i = 0; i < 6; i++) { a[i] = s[i] - 0 ; } int ans = 3; for (int i = 0; i <= 9; i++) { for (int j = 0; j <= 9; j++) { for (int k = 0; k <= 9; k++) { for (int x = 0; x <= 9; x++) { for (int y = 0; y <= 9; y++) { for (int z = 0; z <= 9; z++) { if (i + j + k == x + y + z) { int res = 0; if (i != a[0]) res++; if (j != a[1]) res++; if (k != a[2]) res++; if (x != a[3]) res++; if (y != a[4]) res++; if (z != a[5]) res++; ans = min(ans, res); } } } } } } } for (int i = 0; i <= 9; i++) { for (int j = 0; j <= 9; j++) { for (int k = 0; k <= 9; k++) { if (i + j + k == a[3] + a[4] + a[5]) { int res = 0; if (i != a[0]) res++; if (j != a[1]) res++; if (k != a[2]) res++; ans = min(ans, res); } } } } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; using ii = pair<ll, ll>; using vi = vector<int>; using vii = vector<ii>; using graph = vector<vii>; const int INF = 0x3f3f3f3f; const ll INFL = 0x3f3f3f3f3f3f3f3f; const int MAXN = 2123; const ll mod = 998244353; int seen[MAXN], color[MAXN]; string s; graph g; bool dfs(int u) { seen[u] = 1; int v, type; for (auto k : g[u]) { tie(v, type) = k; if (!seen[v]) { if (color[v] == -1) color[v] = color[u] ^ type; if (dfs(v)) return 1; } if (color[v] ^ color[u] != type) return 1; } return 0; } void build(int n) { for (int i = 0; i < n; ++i) { seen[i] = 0; color[i] = -1; } color[0] = 0; color[1] = 1; } ll bxp(int xp) { ll ans = 1, base = 2; while (xp > 0) { if (xp & 1) ans = ans * base % mod; base = base * base % mod; xp >>= 1; } return ans; } int main() { int n, m; cin >> s; n = s.size(); ll ans = 0; for (int k = n - 1; k > 0; --k) { g.assign(2 + n + k + 1, vii()); for (int i = 2 + n, j = 2 + n + k - 1; i < j; ++i, --j) { g[i].emplace_back(j, 0); g[j].emplace_back(i, 0); } for (int i = 2, j = 2 + n - 1; i < j; ++i, --j) { g[i].emplace_back(j, 0); g[j].emplace_back(i, 0); } for (int i = 0, j = 0; i < n; ++i) { if (s[i] == ? ) { if (i >= n - k) ++j; continue; } if (i < n - k) { g[i + 2].emplace_back(s[i] - 0 , 0); g[s[i] - 0 ].emplace_back(i + 2, 0); } else { g[i + 2].emplace_back(j + 2 + n, s[i] - 0 ); g[j + 2 + n].emplace_back(i + 2, s[i] - 0 ); ++j; } } build(2 + n + k); g[1].emplace_back(0, 1); g[0].emplace_back(1, 1); g[n + 2].emplace_back(1, 0); g[1].emplace_back(n + 2, 0); if (dfs(0)) { continue; } int cnt = 0; bool skip = 0; for (int i = 2; i < 2 + n + k && !skip; ++i) { if (!seen[i]) { color[i] = 0; if (dfs(i)) { skip = 1; } ++cnt; } } if (skip) continue; ans += bxp(cnt); if (ans >= mod) ans -= mod; } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 6e3 + 5; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; int main() { int t, n, k; char x; cin >> t; while (t--) { cin >> n >> k; for (int i = 0; i < n % k; i++) { cout << a ; } for (int i = 0; i < k; i++) { x = a + i; for (int j = 0; j < n / k; j++) { cout << x; } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> istream& operator>>(istream& is, vector<T>& a) { for (T& ai : a) is >> ai; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T> const& a) { os << [ ; for (const T& ai : a) os << ai << ; return os << ] ; } template <typename T1, typename T2> istream& operator>>(istream& is, pair<T1, T2>& a) { return is >> a.first >> a.second; } template <typename T1, typename T2> ostream& operator<<(ostream& os, pair<T1, T2> const& a) { return os << ( << a.first << , << a.second << ) ; } int f() { int n; cin >> n; vector<int> a(n); cin >> a; vector<int> val(a); sort((val).begin(), (val).end()); int m = unique((val).begin(), (val).end()) - val.begin(); val.resize(m); map<int, int> idx; for (int i = 0; i < m; ++i) idx[val[i]] = i; vector<vector<int> > tiers(m); for (int i = 0; i < n; ++i) tiers[idx[a[i]]].push_back(i); int i = 0, j = 1, r = 0; while (i < m) { while (j < m && tiers[j - 1].back() < tiers[j].front()) ++j; int s = 0, lb = tiers[i].front(), ub = tiers[j - 1].back(); for (int k = i; k < j; ++k) s += tiers[k].size(); if (i - 1 >= 0) { for (int x : tiers[i - 1]) { if (x < lb) ++s; } } if (j < m) { for (int x : tiers[j]) { if (x > ub) ++s; } } r = max(r, s); i = j++; } for (int i = 0; i < m - 1; ++i) { int j = 0, jz = tiers[i + 1].size(); int s = jz; for (int lhs : tiers[i]) { ++s; while (j < jz && tiers[i + 1][j] <= lhs) { ++j; --s; } r = max(r, s); } } return n - r; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) cout << f() << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int d[6][3] = {{1, 0, 0}, {-1, 0, 0}, {0, 1, 0}, {0, -1, 0}, {0, 0, 1}, {0, 0, -1}}; int main() { int k, n, m, sn, sm, ans = 0; cin >> k >> n >> m; string plate[k][n]; bool visited[k][n][m]; for (int i = 0; i < k; i++) for (int j = 0; j < n; j++) { for (int N = 0; N < m; N++) visited[i][j][N] = false; cin >> plate[i][j]; } queue<vector<int> > q; cin >> sn >> sm; vector<int> init; for (int i = 0; i < 3; i++) init.push_back(0); int arr[3] = {0, sn - 1, sm - 1}; for (int i = 0; i < 3; i++) init[i] = arr[i]; q.push(init); while (!q.empty()) { vector<int> A = q.front(); visited[A[0]][A[1]][A[2]] = true; ans++; q.pop(); for (int i = 0; i < 6; i++) { vector<int> B(A); for (int j = 0; j < 3; j++) B[j] += d[i][j]; if (B[0] >= 0 && B[0] < k && B[1] >= 0 && B[1] < n && B[2] >= 0 && B[2] < m && plate[B[0]][B[1]][B[2]] == . && !visited[B[0]][B[1]][B[2]]) { q.push(B); visited[B[0]][B[1]][B[2]] = true; } } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
`define SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_4_V
`define SKY130_FD_SC_MS__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_4_V
|
#include <bits/stdc++.h> using namespace std; int block[101]; int nuclea[101]; int inst[101][101]; int main() { ios_base::sync_with_stdio(0); int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> inst[j][i]; } } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { if (nuclea[j] == 0) block[inst[i][j]]++; } block[0] = 0; for (int j = 0; j < n; j++) { if (block[inst[i][j]] > 1 && nuclea[j] == 0) { nuclea[j] = i + 1; } } for (int i = 1; i < 101; i++) { if (block[i] < 2) block[i] = 0; } } for (int i = 0; i < n; i++) cout << nuclea[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int tc; cin >> tc; while (tc-- > 0) { int arr[7]; for (int i = 0; i < 7; i++) { cin >> arr[i]; } cout << arr[0] << << arr[1] << << arr[6] - arr[0] - arr[1] << endl; } }
|
#include <bits/stdc++.h> const long long inf = 1ll << 60; const long long maxn = 30010; using namespace std; struct lsg { long long x, y; } a[maxn], b[maxn]; signed n, q, ffa[maxn], ffb[maxn], ban[maxn], x, y; long long f[maxn], w1[maxn], w2[maxn], w3[maxn]; bool pd(lsg a, lsg b) { return a.x < b.x; } inline void doit(long long i) { w1[i] = w2[i] = w3[i] = -inf; if (i >= 1 && ban[i] != i) w1[i] = a[i].x * b[i].x; if (i >= 2 && ban[i] != i - 1 && ban[i - 1] != i) w2[i] = a[i].x * b[i - 1].x + a[i - 1].x * b[i].x; if (i >= 3) { if (ban[i] != i - 2 && ban[i - 1] != i && ban[i - 2] != i - 1) w3[i] = a[i].x * b[i - 2].x + a[i - 1].x * b[i].x + a[i - 2].x * b[i - 1].x; if (ban[i] != i - 1 && ban[i - 1] != i - 2 && ban[i - 2] != i) w3[i] = max(w3[i], a[i].x * b[i - 1].x + a[i - 1].x * b[i - 2].x + a[i - 2].x * b[i].x); } } inline signed read() { char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); signed k = 1, kk = 0; if (c == - ) k = -1; else kk = c - 0 ; c = getchar(); while (c >= 0 && c <= 9 ) kk = kk * 10 + c - 0 , c = getchar(); return k * kk; } inline long long max(long long x, long long y) { return x > y ? x : y; } inline long long min(long long x, long long y) { return x < y ? x : y; } signed main() { n = read(); q = read(); for (signed i = 1; i <= n; i++) a[i].x = read(), a[i].y = i; for (signed i = 1; i <= n; i++) b[i].x = read(), b[i].y = i; sort(a + 1, a + 1 + n, pd), sort(b + 1, b + 1 + n, pd); for (signed i = 1; i <= n; i++) ffa[a[i].y] = i, ffb[b[i].y] = i; for (signed i = 1; i <= n; i++) ban[i] = ffb[a[i].y]; for (signed i = 1; i <= n; i++) doit(i); for (signed j = 1; j <= q; j++) { x = ffa[read()], y = ffa[read()], swap(ban[x], ban[y]); for (signed i = max(1, x - 5); i <= min(n, x + 5); i++) doit(i); for (signed i = max(1, y - 5); i <= min(n, y + 5); i++) doit(i); f[0] = 0; for (signed i = 1; i <= n; i++) { if (i >= 1) f[i] = f[i - 1] + w1[i]; if (i >= 2) f[i] = max(f[i], f[i - 2] + w2[i]); if (i >= 3) f[i] = max(f[i], f[i - 3] + w3[i]); } cout << f[n] << endl; } }
|
/* Concrete parameterizations of tapped FIFO for testing.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "tapped_fifo.v"
module tapped_fifo_test1(
input clk,
input rst,
input wire inp,
output wire [9:0] taps,
output wire outp
);
tapped_fifo #(.WIDTH(1), .DEPTH(10)) f_1_10(clk, rst, inp, taps, outp);
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace myrand { mt19937 mt(chrono::system_clock::now().time_since_epoch() / chrono::microseconds(1)); long long Int(long long l, long long r) { return uniform_int_distribution<long long>(l, r)(mt); } } // namespace myrand using namespace myrand; auto ss = chrono::system_clock::now(); double remain_time() { auto en = chrono::system_clock::now(); return (chrono::duration_cast<chrono::nanoseconds>(en - ss).count() * 1e-9); } long long cnt; long long dp[3001][3001]; const long long mod = 998244353; void solve(string s, string t) { int n = s.size(); int m = t.size(); for (int i = 0; i <= n; i++) dp[i][i] = 1; for (int len = 1; len <= n; len++) for (int i = 0; i + len <= n; i++) { int j = i + len; if (i >= m || s[len - 1] == t[i]) dp[i][j] += dp[i + 1][j]; if (j > m || s[len - 1] == t[j - 1]) dp[i][j] += dp[i][j - 1]; dp[i][j] %= mod; } for (int j = m; j <= n; j++) cnt = (cnt + dp[0][j]) % mod; cout << cnt; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s, t; cin >> s; cin >> t; solve(s, t); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct M { int t, x[4]; M(int s, int a, int b, int c, int d = 0) { t = s; x[0] = a; x[1] = b; x[2] = c; x[3] = d; } void p() { printf( %d , t); for (int i = 0; i < (int)(t); ++i) printf( %d , x[i]); printf( n ); } }; vector<M> an; int main() { int n; scanf( %d , &n); while (n > 4) { int a = n, b = n - 1; an.push_back(M(3, 1, a, b)); an.push_back(M(3, 1, a, b)); for (int i = 3; i < (int)(b); ++i) an.push_back(M(4, i - 1, a, i, b)); an.push_back(M(4, b - 1, a, 2, b)); n -= 2; } if (n == 4) { an.push_back(M(4, 1, 2, 3, 4)); an.push_back(M(4, 1, 3, 4, 2)); an.push_back(M(4, 1, 4, 2, 3)); } else { an.push_back(M(3, 1, 2, 3)); an.push_back(M(3, 1, 2, 3)); } printf( %d n , (int)an.size()); for (int i = 0; i < (int)(an.size()); ++i) an[i].p(); }
|
#include <bits/stdc++.h> using namespace std; long long gcd(int a, int b) { if (!b) return a; return gcd(b, a % b); } bool isprime(long long n) { if (n == 2) { return true; } if (n % 2 == 0) { return false; } for (long long i = 3; i <= sqrt(n); i += 2) { if (n % i == 0) { return false; } } return true; } long long a[1005][2]; int main() { long long n, m; cin >> n >> m; long long flag[m]; memset(flag, 0, sizeof(flag)); for (int(i) = (0); (i) < (m); (i)++) { long long k; cin >> k; map<int, int> m; for (int(j) = (0); (j) < (k); (j)++) { long long x; cin >> x; m[x]++; if (m.find(-x) != m.end()) flag[i] = 1; } } for (int(i) = (0); (i) < (m); (i)++) { if (flag[i] == 0) { cout << YES ; return 0; } } cout << NO ; }
|
#include <bits/stdc++.h> const int N = 100010; const int inf = 0x3f3f3f3f; using namespace std; int a[N], b[N], c[N], d[N]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < m; i++) scanf( %d%d%d , a + i, b + i, c + i); long long ret = 0; for (int i = 0; i < k; i++) { scanf( %d , d + i); for (int j = 0; j < m; j++) { if (a[j] <= d[i] && d[i] <= b[j]) ret += c[j] + d[i] - a[j]; } } cout << ret << endl; return 0; }
|
module lsu
(/*AUTOARG*/
// Outputs
issue_ready,
vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en,
mem_gm_or_lds, tracemon_gm_or_lds,
vgpr_dest_wr_en,
mem_rd_en, mem_wr_en,
sgpr_dest_wr_en,
exec_rd_wfid,
mem_tag_req,
sgpr_source1_addr, sgpr_source2_addr, sgpr_dest_addr,
vgpr_source1_addr, vgpr_source2_addr, vgpr_dest_addr,
vgpr_dest_wr_mask, mem_wr_mask,
sgpr_dest_data,
mem_addr,
vgpr_dest_data, mem_wr_data, rfa_dest_wr_req,
lsu_done, lsu_done_wfid,
sgpr_instr_done, sgpr_instr_done_wfid,
vgpr_instr_done, vgpr_instr_done_wfid,
tracemon_retire_pc, tracemon_mem_addr, tracemon_idle,
// Inputs
clk, rst, issue_lsu_select, mem_ack, issue_wfid, mem_tag_resp,
issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg, issue_mem_sgpr, issue_imm_value0, issue_lds_base,
issue_imm_value1, issue_opcode, sgpr_source2_data,
exec_rd_m0_value, issue_instr_pc, exec_exec_value,
sgpr_source1_data, vgpr_source2_data, vgpr_source1_data,
mem_rd_data, lsu_stall
);
parameter MEMORY_BUS_WIDTH = 32;
parameter MEM_SLOTS = 1;
input clk;
input rst;
input issue_lsu_select, mem_ack;
input [5:0] issue_wfid;
input [6:0] mem_tag_resp;
input [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg, issue_mem_sgpr;
input [15:0] issue_imm_value0, issue_lds_base;
input [31:0] issue_imm_value1, issue_opcode, sgpr_source2_data, exec_rd_m0_value,
issue_instr_pc;
input [63:0] exec_exec_value;
input [127:0] sgpr_source1_data;
input [2047:0] vgpr_source1_data;
input [2047:0] vgpr_source2_data;
input [MEMORY_BUS_WIDTH-1:0] mem_rd_data;
input lsu_stall;
output issue_ready, vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en, mem_gm_or_lds,
tracemon_gm_or_lds;
output vgpr_dest_wr_en, mem_rd_en, mem_wr_en;
output [3:0] sgpr_dest_wr_en;
output [5:0] exec_rd_wfid;
output [6:0] mem_tag_req;
output [8:0] sgpr_source1_addr, sgpr_source2_addr, sgpr_dest_addr;
output [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_dest_addr;
output [63:0] vgpr_dest_wr_mask, mem_wr_mask;
output [127:0] sgpr_dest_data;
output [31:0] mem_addr;
output [2047:0] vgpr_dest_data;
output [MEMORY_BUS_WIDTH-1:0] mem_wr_data;
output rfa_dest_wr_req;
output lsu_done;
output sgpr_instr_done;
output vgpr_instr_done;
output [5:0] lsu_done_wfid;
output [5:0] sgpr_instr_done_wfid;
output [5:0] vgpr_instr_done_wfid;
output [31:0] tracemon_retire_pc;
output [2047:0] tracemon_mem_addr;
output tracemon_idle;
assign exec_rd_wfid = issue_wfid;
reg [31:0] issue_opcode_flopped;
reg [15:0] issue_lds_base_flopped;
reg [15:0] issue_imm_value0_flopped;
wire [2047:0] calc_mem_addr;
wire gm_or_lds;
wire decoded_sgpr_source1_rd_en;
wire decoded_sgpr_source2_rd_en;
wire [8:0] decoded_sgpr_source1_addr;
wire [8:0] decoded_sgpr_source2_addr;
//wire decoded_vgpr_source1_rd_en;
wire decoded_vgpr_source2_rd_en;
wire [9:0] decoded_vgpr_source1_addr;
wire [9:0] decoded_vgpr_source2_addr;
wire [5:0] mem_op_cnt;
wire mem_op_rd;
wire mem_op_wr;
wire mem_gpr;
wire [3:0] sgpr_wr_mask;
wire [1:0] gpr_op_depth;
always@(posedge clk) begin
if(rst) begin
issue_opcode_flopped <= 32'd0;
issue_lds_base_flopped <= 16'd0;
issue_imm_value0_flopped <= 16'd0;
end
else begin
issue_opcode_flopped <= issue_opcode;
issue_lds_base_flopped <= issue_lds_base;
issue_imm_value0_flopped <= issue_imm_value0;
end
end
// The decoder requires two cycles to receive the entire opcode. On the second
// cycle it generates register read operations for getting addres values from
// the GPRs.
lsu_opcode_decoder lsu_opcode_decoder0(
.lsu_selected(issue_lsu_select),
.lsu_opcode(issue_opcode),
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3),
.issue_mem_sgpr(issue_mem_sgpr),
//.issue_dest_reg(issue_dest_reg_flopped),
.sgpr_source1_rd_en(decoded_sgpr_source1_rd_en),
.sgpr_source2_rd_en(decoded_sgpr_source2_rd_en),
.sgpr_source1_addr(decoded_sgpr_source1_addr),
.sgpr_source2_addr(decoded_sgpr_source2_addr),
.vgpr_source2_rd_en(decoded_vgpr_source2_rd_en),
.vgpr_source1_addr(decoded_vgpr_source1_addr),
.vgpr_source2_addr(decoded_vgpr_source2_addr),
// Signals to indicate a new memory request
.mem_op_cnt(mem_op_cnt),
.mem_op_rd(mem_op_rd),
.mem_op_wr(mem_op_wr),
.mem_gpr(mem_gpr),
.sgpr_wr_mask(sgpr_wr_mask),
.gpr_op_depth(gpr_op_depth)
);
lsu_op_manager lsu_op_manager0(
.lsu_wfid(issue_wfid),
.instr_pc(issue_instr_pc),
// Signals to indicate a new memory request
.mem_op_cnt(mem_op_cnt),
.mem_op_rd(mem_op_rd),
.mem_op_wr(mem_op_wr),
.mem_gpr(mem_gpr),
.gm_or_lds(gm_or_lds),
.sgpr_wr_mask(sgpr_wr_mask),
.gpr_op_depth(gpr_op_depth),
.exec_mask(exec_exec_value),
.mem_in_addr(calc_mem_addr),
.mem_ack(mem_ack),
.mem_rd_data(mem_rd_data),
.vgpr_source1_data(vgpr_source1_data),
.free_mem_slots(1'b0),
.decoded_sgpr_source1_rd_en(decoded_sgpr_source1_rd_en),
.decoded_sgpr_source2_rd_en(decoded_sgpr_source2_rd_en),
.decoded_sgpr_source1_addr(decoded_sgpr_source1_addr),
.decoded_sgpr_source2_addr(decoded_sgpr_source2_addr),
//decoded_vgpr_source1_rd_en,
.decoded_vgpr_source2_rd_en(decoded_vgpr_source2_rd_en),
.decoded_vgpr_source1_addr(decoded_vgpr_source1_addr),
.decoded_vgpr_source2_addr(decoded_vgpr_source2_addr),
.decoded_dest_addr(issue_dest_reg),
.sgpr_dest_data(sgpr_dest_data),
.sgpr_dest_wr_en(sgpr_dest_wr_en),
.sgpr_dest_addr(sgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_dest_wr_en(vgpr_dest_wr_en),
.vgpr_wr_mask(vgpr_dest_wr_mask),
.vgpr_dest_addr(vgpr_dest_addr),
.lsu_rdy(issue_ready),
.lsu_done(lsu_done),
.sgpr_instr_done(sgpr_instr_done),
.vgpr_instr_done(vgpr_instr_done),
.lsu_done_wfid(lsu_done_wfid),
.sgpr_instr_done_wfid(sgpr_instr_done_wfid),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.retire_pc(tracemon_retire_pc),
.retire_gm_or_lds(tracemon_gm_or_lds),
.tracemon_mem_addr(tracemon_mem_addr),
.mem_rd_en(mem_rd_en),
.mem_wr_en(mem_wr_en),
.mem_out_addr(mem_addr),
.mem_wr_data(mem_wr_data),
.mem_tag_req(mem_tag_req),
.mem_gm_or_lds(mem_gm_or_lds),
.sgpr_source1_rd_en(sgpr_source1_rd_en),
.sgpr_source2_rd_en(sgpr_source2_rd_en),
.sgpr_source1_addr(sgpr_source1_addr),
.sgpr_source2_addr(sgpr_source2_addr),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.clk(clk),
.rst(rst)
);
// Because the register read operations for the address values will take one
// cycle to complete the opcode needs to be flopped so that the opcode being
// used by the address calculator is properly aligned.
lsu_addr_calculator addr_calc(
.in_vector_source_b(vgpr_source2_data),
.in_scalar_source_a(sgpr_source1_data),
.in_scalar_source_b(sgpr_source2_data),
.in_opcode(issue_opcode_flopped),
.in_lds_base(issue_lds_base_flopped),
.in_imm_value0(issue_imm_value0_flopped),
.out_ld_st_addr(calc_mem_addr),
.out_gm_or_lds(gm_or_lds)
);
assign rfa_dest_wr_req = (|sgpr_dest_wr_en) | vgpr_dest_wr_en;
// Something of a hack, at this point it's not actually needed
assign mem_wr_mask = vgpr_dest_wr_mask;
assign tracemon_idle = issue_ready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, ans, notOK; map<int, int> M; int main() { cin >> n; for (int i = 0, x; i < n; i++) cin >> x, M[x]++; for (map<int, int>::iterator it = M.begin(); it != M.end(); it++) { if (it->first) { if (it->second == 2) ans++; else if (it->second > 2) notOK = 1; } } cout << (notOK ? -1 : ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long a, b, c, count = 0; scanf( %lld %lld , &a, &b); while (a--) { scanf( %lld , &c); if (c <= b) count++; else count += 2; } printf( %lld , count); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_BEHAVIORAL_PP_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int n, m; cin >> n >> m; cin >> s; for (int i = 0; i < m; i++) { int l, r; char c1, c2; scanf( %d %d %c %c , &l, &r, &c1, &c2); for (int j = l - 1; j < r; j++) { if (s[j] == c1) { s[j] = c2; } } } cout << s << endl; cin >> n; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> v; int main() { v.push_back(0); for (int i = 0; i < int(30); i++) v.push_back(1 << i); while (1) { int hi, lo; int test; string s; cin >> s; if (s == mistake || s == end ) return 0; bool found = 0; for (int i = 0; i < int(30); i++) { cout << ? << v[i] << << v[i + 1] << endl; fflush(stdout); char c; cin >> c; if (c == e ) return 0; if (c == x ) { found = 1; lo = v[i] + 1; hi = v[i + 1]; test = v[i]; break; } } if (!found) { lo = v[v.size() - 1] + 1; hi = 1000000000; test = v[v.size() - 1]; } while (hi - lo > 1) { int mid = (lo + hi) / 2; cout << ? << test << << mid << endl; fflush(stdout); char c; cin >> c; if (c == e ) return 0; if (c == x ) hi = mid; else lo = mid + 1; } cout << ? << test << << lo << endl; fflush(stdout); char c; cin >> c; if (c == e ) return 0; if (c == x ) cout << ! << lo << endl; else cout << ! << hi << endl; } }
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// axis to vector
// A generic module to unmerge all axis 'data' signals from payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_1_0_util_vector2axis
//
//--------------------------------------------------------------------------
`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_util_vector2axis #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// outputs
input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
// inputs
output wire [C_TDATA_WIDTH-1:0] TDATA,
output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
output wire TLAST,
output wire [C_TID_WIDTH-1:0] TID,
output wire [C_TDEST_WIDTH-1:0] TDEST,
output wire [C_TUSER_WIDTH-1:0] TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ;
end
else begin : no_gen_tdata
assign TDATA = {C_TDATA_WIDTH{1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
end
else begin : no_gen_tstrb
assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
end
else begin : no_gen_tkeep
assign TKEEP = {(C_TDATA_WIDTH/8){1'b1}};
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ;
end
else begin : no_gen_tlast
assign TLAST = 1'b0;
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ;
end
else begin : no_gen_tid
assign TID = {C_TID_WIDTH{1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ;
end
else begin : no_gen_tdest
assign TDEST = {C_TDEST_WIDTH{1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ;
end
else begin : no_gen_tuser
assign TUSER = {C_TUSER_WIDTH{1'b0}};
end
endgenerate
endmodule
`default_nettype wire
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYMETAL6S4S_PP_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); inline long long int rand(long long int x, long long int y) { ++y; return (rng() % (y - x)) + x; } string to_string(char c) { string second(1, c); return second; } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void degug_out() { cerr << endl; } template <typename Head, typename... Tail> void degug_out(Head H, Tail... T) { cerr << << to_string(H); degug_out(T...); } long long int n, fac[(300006)], dp[(300006)]; const long long int MOD = 998244353; vector<long long int> v[(300006)]; void fact() { fac[0] = fac[1] = 1; for (long long int i = 2; i <= n; ++i) { fac[i] = (i * fac[i - 1]) % MOD; } return; } void dfs(long long int x, long long int p) { long long int ans = 1; long long int child = 1; for (auto i : v[x]) if (i != p) { child++; dfs(i, x); ans *= dp[i]; ans %= MOD; } ans *= fac[child - 1]; ans %= MOD; if (x != 1) ans *= child; ans %= MOD; return void(dp[x] = ans); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; fact(); for (long long int i = 0; i < (long long int)n - 1; ++i) { long long int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } dfs(1, 1); cout << (dp[1] * n) % MOD; }
|
// This is the Avalon slave for the motor controller
// Registers 0-5 store the direction and on/off switch for each motor
// Registers 8-13 store the respective duty cycle
// The output should be fed to GPIO pins in the SOPC configuration
`include "defines.v"
module slave_controller(input clk, input reset, input chipselect, input write, input [3:0]addr, input [31:0] writedata, output [23:0] GPIO_out);
reg [11:0] in = 12'd0;
reg [6*`PERIOD_LENGTH-1:0] duty_cycle = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (chipselect & write)
casex (addr)
4'b0000:
in[1:0] <= writedata[1:0];
4'b0001:
in[3:2] <= writedata[1:0];
4'b0010:
in[5:4] <= writedata[1:0];
4'b0011:
in[7:6] <= writedata[1:0];
4'b0100:
in[9:8] <= writedata[1:0];
4'b0101:
in[11:10] <= writedata[1:0];
4'b1000:
duty_cycle[`PERIOD_LENGTH-1:0] <= writedata[`PERIOD_LENGTH-1:0];
4'b1001:
duty_cycle[2*`PERIOD_LENGTH-1:`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1010:
duty_cycle[3*`PERIOD_LENGTH-1:2*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1011:
duty_cycle[4*`PERIOD_LENGTH-1:3*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1100:
duty_cycle[5*`PERIOD_LENGTH-1:4*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1101:
duty_cycle[6*`PERIOD_LENGTH-1:5*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1110:
period <= writedata[15:0];
default:
; // do nothing
endcase
generate
genvar i;
for (i=0; i<6; i=i+1)
begin : motor_control_loop
motor_controller mc(clk, in[i*2 + 1], in[i*2], period, duty_cycle[(i+1)*`PERIOD_LENGTH-1:i*`PERIOD_LENGTH], GPIO_out[i*4+3:i*4]);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_M_V
`define SKY130_FD_SC_LP__O22AI_M_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_m (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_m (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_M_V
|
#include <bits/stdc++.h> using namespace std; int ans; char s[100]; int main() { cin >> s; for (int i = 0; i < strlen(s); i++) if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u || s[i] == 1 || s[i] == 3 || s[i] == 5 || s[i] == 7 || s[i] == 9 ) ans++; cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int o, O, f, z, i, d; string t, s[6] = { lios , liala , etr , etra , initis , inites }; int V[ zz ]; int main() { while (cin >> t) { for (i = O = 0; i < 6; i++) if ((d = t.size() - s[i].size()) < 0 ? 0 : t.substr(d) == s[i]) { if (z && V[z - 1] > i) break; O = 1; V[z++] = i; f += i / 2 == 1; o += i % 2; } if (!O) { cout << NO n ; return 0; } } cout << (z != 1 && (o % z || f != 1) ? NO n : YES n ); }
|
// Basic Components; muxes, flip-flops, etc.
//
// Author: Ivan Castellanos
// email:
// VLSI Computer Architecture Research Group,
// Oklahoma Stata University
//Reduced Full Adder Cell (for CLA, 8 gates instead of 9)
module rfa (sum, g, p, a, b, cin);
output sum;
output g;
output p;
input a;
input b;
input cin;
xor x1(sum, a, b, cin);
and a1(g, a, b);
or o1(p, a, b);
endmodule
//17-bit Register with reset
module dffr_17 (q, d, clk, reset);
output [16:0] q;
input [16:0] d;
input clk, reset;
reg [16:0] q;
always @ (posedge clk or negedge reset)
if (reset == 0)
q <= 0;
else
q <= d;
endmodule
//Basic adders for Multiplier
module FA (Sum, Cout, A, B, Cin);
input A;
input B;
input Cin;
output Sum;
output Cout;
wire w1;
wire w2;
wire w3;
wire w4;
xor x1(w1, A, B);
xor x2(Sum, w1, Cin);
nand n1(w2, A, B);
nand n2(w3, A, Cin);
nand n3(w4, B, Cin);
nand n4(Cout, w2, w3, w4);
endmodule // FA
module MFA (Sum, Cout, A, B, Sin, Cin);
input A;
input B;
input Sin;
input Cin;
output Sum;
output Cout;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
and a1(w0, A, B);
xor x1(w1, w0, Sin);
xor x2(Sum, w1, Cin);
nand n1(w2, w0, Sin);
nand n2(w3, w0, Cin);
nand n3(w4, Sin, Cin);
nand n4(Cout, w2, w3, w4);
endmodule // MFA
module NMFA (Sum, Cout, A, B, Sin, Cin);
input A;
input B;
input Sin;
input Cin;
output Sum;
output Cout;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
nand n0(w0, A, B);
xor x1(w1, w0, Sin);
xor x2(Sum, w1, Cin);
nand n1(w2, w0, Sin);
nand n2(w3, w0, Cin);
nand n3(w4, Sin, Cin);
nand n4(Cout, w2, w3, w4);
endmodule // NMFA
module MHA (Sum, Cout, A, B, Sin);
input A;
input B;
input Sin;
output Sum;
output Cout;
wire w1;
and a0(w1, A, B);
xor x1(Sum, w1, Sin);
and a1(Cout, w1, Sin);
endmodule // MHA
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; void __print(long long int x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename Th, typename V> void __print(const pair<Th, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename Th> void __print(const Th &x) { long long int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename Th, typename... V> void _print(Th t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void binary_rock() { long long int v, c, n, m; cin >> v >> c >> n >> m; if (v + c < n + m) { cout << No << endl; return; } long long int mini = min(v, c); if (mini >= m) { cout << Yes << endl; return; } if (v >= c) { long long int req = (v - c); if (n < req) { cout << No << endl; return; } n -= req; v -= req; if (n >= m) { cout << Yes << endl; return; } m -= n; v -= n; c -= n; n -= n; if (m > v) { cout << No << endl; return; } else { cout << Yes << endl; return; } return; } else { long long int req = (c - v); if (n < req) { cout << No << endl; } else { n -= req; c -= req; if (n >= m) { cout << Yes << endl; return; } m -= n; v -= n; c -= n; n -= n; if (m > v) { cout << No << endl; return; } else { cout << Yes << endl; return; } cout << Yes << endl; } return; } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); clock_t t1 = clock(); long long int t = 1; cin >> t; while (t--) { binary_rock(); } clock_t t2 = clock(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long in() { int32_t x; scanf( %d , &x); return x; } inline long long lin() { long long x; scanf( %lld , &x); return x; } inline void read(long long *a, long long n) { for (long long i = 0; i < n; i++) a[i] = in(); } inline void readL(long long *a, long long n) { for (long long i = 0; i < n; i++) a[i] = lin(); } const long long maxn = 100 + 10; const long long mod = 1e9 + 7; const long long MAX_VAL = 1e18 + 10; const long long MAGIC = 350; long long n, m; vector<pair<long long, long long> > g[maxn]; long long dp[maxn][maxn][27]; long long ret[maxn][maxn]; inline long long dfs(long long a, long long b, long long pre) { if (pre >= 26) return 1; if (dp[a][b][pre] + 1) return dp[a][b][pre]; for (auto u : g[a]) { if (u.second >= pre) { long long getRes = dfs(b, u.first, u.second); if (getRes == 1) return dp[a][b][pre] = 0; } } return dp[a][b][pre] = 1; } int32_t main() { n = in(), m = in(); memset(dp, -1, sizeof dp); for (long long i = 0; i < m; i++) { long long v = in() - 1, u = in() - 1; char ch; do { ch = getchar(); } while (!isalpha(ch)); g[v].push_back({u, ch - a }); } for (long long a = 0; a < n; a++, cout << n ) { for (long long b = 0; b < n; b++) { ret[a][b] = dfs(a, b, 0); if (ret[a][b] == 0) cout << A ; else cout << B ; } } }
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Simple send-only UART
module uart(
input wire clock, // main clock
output reg txd = 1'b1,
input wire [23:0] tx_data,
output reg tx_empty = 1'b1, // '1' when tx_data can take a new byte
input wire transmit // pulse '1' when tx_data is valid
);
// clock divider to get baud rate. 82M / 115.2k = 712, giving 115.169 kb/s
parameter divide_count = 712;
// clock divider, assuming divide_count <= 1023
reg [9:0] divider = 0;
// shift register -- (start bit + 8 data bits + 1 stop bit) x 3 bytes
reg [29:0] shifter;
// how many bits to shift -- counts down from 30
reg [4:0] shift_count = 0;
always @(posedge clock) begin
// trying making this synchronous to debug missing transfers
// that could possibly be to do with the fifo in elk_interface...
// previously this was:
// assign tx_empty = (shift_count == 0) ? 1'b1 : 1'b0;
tx_empty = (shift_count == 0) ? 1'b1 : 1'b0;
// note that we can get slightly lower latency by setting this inside the loop that
// decrements shift_count, but that only happens on divider expiry and this happens
// every clock, so having it out here only slows it down 12 ns!
// accept a new byte to send
if (tx_empty == 1'b1 && transmit == 1'b1) begin
$display("accept new byte from tx_data");
// shifter <= {tx_data, 1'b0}; // 8-bit
shifter <= {1'b1, tx_data[23:16], 1'b0, 1'b1, tx_data[15:8], 1'b0, 1'b1, tx_data[7:0], 1'b0}; // 24-bit
shift_count <= 31;
tx_empty <= 1'b0;
end
// divider divides clock down to the serial bit rate (x 4 for reception?)
if (divider == divide_count) begin
divider <= 1;
// transmit a bit on divider expiry
if (shift_count != 0) begin
txd <= shifter[0];
// shift right
shifter <= {1'b1, shifter[29:1]};
shift_count <= shift_count - 5'd1;
end
end else begin
divider <= divider + 10'd1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(NULL); ios_base::sync_with_stdio(false); int N; vector<int> V; cin >> N; int X; for (int i = 0; i < N; i++) { cin >> X; V.push_back(X); } int ans = 100100, t = 0; for (int i = 1; i <= 100; i++) { int cost = 0; for (int j = 0; j < N; j++) { if (abs(V[j] - i) > 1) { cost += min(abs(V[j] - (i + 1)), abs(V[j] - (i - 1))); } } if (cost < ans) { ans = cost; t = i; } } cout << t << << ans << endl; return 0; }
|
//////////////////////////////////////////////////////////////////
// //
// Generic Library SRAM with single write enable //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Configurable depth and width. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module generic_sram_line_en
#(
parameter DATA_WIDTH = 128,
parameter ADDRESS_WIDTH = 7,
parameter INITIALIZE_TO_ZERO = 0
)
(
input i_clk,
input [DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
output reg [DATA_WIDTH-1:0] o_read_data
);
reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];
generate
if ( INITIALIZE_TO_ZERO ) begin : init0
integer i;
initial
begin
for (i=0;i<2**ADDRESS_WIDTH;i=i+1)
mem[i] <= 'd0;
end
end
endgenerate
always @(posedge i_clk)
begin
// read
o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
// write
if (i_write_enable)
mem[i_address] <= i_write_data;
end
endmodule
|
// file: system_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "system_clk_wiz_1_0,clk_wiz_v5_3_3_0,{component_name=system_clk_wiz_1_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module system_clk_wiz_1_0
(
// Clock out ports
output clk_out1,
// Status and control signals
output locked,
// Clock in ports
input clk_in1
);
system_clk_wiz_1_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Latch_Index_Pulse.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Latch_Index_Pulse
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Latch_Index_Pulse
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Latch_Index_Pulse
(
CLK_IN,
reset,
enb,
In1,
Out1
);
input CLK_IN;
input reset;
input enb;
input In1;
output Out1;
wire Constant1_out1;
wire Switch_out1;
reg Delay_out1;
// <S7>/Constant1
assign Constant1_out1 = 1'b1;
// <S7>/Delay
always @(posedge CLK_IN)
begin : Delay_process
if (reset == 1'b1) begin
Delay_out1 <= 1'b0;
end
else if (enb) begin
Delay_out1 <= Switch_out1;
end
end
// <S7>/Switch
assign Switch_out1 = (Delay_out1 == 1'b0 ? In1 :
Constant1_out1);
assign Out1 = Switch_out1;
endmodule // Latch_Index_Pulse
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m4_n12.v ** //
// ** Project : ISAAC Newton / SMAP ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : February 17, 2009 ** //
// ** Description : Polyphase Decimation, 4 parallel inputs ** //
// ** M = 4, L = 12 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : FIR0.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : February 9, 2009 ** //
// ** FileName : ** //
// ** Notes : Initial Release for SMAP demo ** //
// ** ** //
// ** File : firdecim_m4_n12.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : February , 2009 ** //
// ** FileName : ** //
// ** Notes : Change from 16 taps to 12 taps ** //
// ** ** //
// ******************************************************************************* //
`timescale 1ns/100ps
module firdecim_m4_n12(/*AUTOARG*/
// Outputs
dsp_out, outValid,
// Inputs
dsp_in0, dsp_in1, dsp_in2, dsp_in3, ein, new_e, clk, rst, inValid
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter OWIDTH = 16;
parameter IWIDTH = 8;
parameter ACCUMWIDTH = 24;
parameter CNTWIDTH = 2; // DECIMATION FACTOR
// DATA TYPE - INPUTS AND OUTPUTS
output signed [(OWIDTH-1):0] dsp_out;
output outValid;
input signed [(IWIDTH-1):0] dsp_in0; // 2-bit integer
input signed [(IWIDTH-1):0] dsp_in1;
input signed [(IWIDTH-1):0] dsp_in2;
input signed [(IWIDTH-1):0] dsp_in3;
input signed [(OWIDTH-1):0] ein;
input new_e;
input clk;
input rst;
input inValid;
// DATA TYPE - REGISTERS
reg signed [15:0] eff0; // 2-bit integer
reg signed [15:0] eff1;
reg signed [15:0] eff2;
reg signed [15:0] eff3;
reg signed [15:0] eff4;
reg signed [15:0] eff5;
reg signed [15:0] eff6;
reg signed [15:0] eff7;
reg signed [15:0] eff8;
reg signed [15:0] eff9;
reg signed [15:0] effA;
reg signed [15:0] effB;
reg signed [(ACCUMWIDTH-1):0] mul00; // 4-bit integer
reg signed [(ACCUMWIDTH-1):0] mul01;
reg signed [(ACCUMWIDTH-1):0] mul02;
reg signed [(ACCUMWIDTH-1):0] mul03;
reg signed [(ACCUMWIDTH-1):0] mul10;
reg signed [(ACCUMWIDTH-1):0] mul11;
reg signed [(ACCUMWIDTH-1):0] mul12;
reg signed [(ACCUMWIDTH-1):0] mul13;
reg signed [(ACCUMWIDTH-1):0] mul20;
reg signed [(ACCUMWIDTH-1):0] mul21;
reg signed [(ACCUMWIDTH-1):0] mul22;
reg signed [(ACCUMWIDTH-1):0] mul23;
reg signed [(ACCUMWIDTH-1):0] acc0; // 4-bit integer
reg signed [(ACCUMWIDTH-1):0] acc1;
reg signed [(ACCUMWIDTH-1):0] acc2;
reg inValid_z;
reg [(CNTWIDTH-1):0] cnt;
reg outValid;
reg signed [(OWIDTH-1):0] dsp_out; // 2-bit integer
// DATA TYPE - WIRES
wire signed [(ACCUMWIDTH-1):0] result; // 2-bit integer
//**************************************************************************//
//* Coefficient Rotation *//
//**************************************************************************//
always @ (posedge clk or posedge rst)
if (rst)
begin
eff0[15:0] <= 16'd0;//eff0[15:0];
eff1[15:0] <= 16'd0;//eff1[15:0];
eff2[15:0] <= 16'd0;//eff2[15:0];
eff3[15:0] <= 16'd0;//eff3[15:0];
eff4[15:0] <= 16'd0;//eff4[15:0];
eff5[15:0] <= 16'd0;//eff5[15:0];
eff6[15:0] <= 16'd0;//eff6[15:0];
eff7[15:0] <= 16'd0;//eff7[15:0];
eff8[15:0] <= 16'd0;//eff8[15:0];
eff9[15:0] <= 16'd0;//eff9[15:0];
effA[15:0] <= 16'd0;//effA[15:0];
effB[15:0] <= 16'd0;//effB[15:0];
end
else if (new_e)
begin
eff0[15:0] <= ein[15:0];
eff1[15:0] <= eff0[15:0];
eff2[15:0] <= eff1[15:0];
eff3[15:0] <= eff2[15:0];
eff4[15:0] <= eff3[15:0];
eff5[15:0] <= eff4[15:0];
eff6[15:0] <= eff5[15:0];
eff7[15:0] <= eff6[15:0];
eff8[15:0] <= eff7[15:0];
eff9[15:0] <= eff8[15:0];
effA[15:0] <= eff9[15:0];
effB[15:0] <= effA[15:0];
end
else if (inValid)
begin
eff0[15:0] <= eff4[15:0];
eff1[15:0] <= eff5[15:0];
eff2[15:0] <= eff6[15:0];
eff3[15:0] <= eff7[15:0];
eff4[15:0] <= eff8[15:0];
eff5[15:0] <= eff9[15:0];
eff6[15:0] <= effA[15:0];
eff7[15:0] <= effB[15:0];
eff8[15:0] <= eff0[15:0];
eff9[15:0] <= eff1[15:0];
effA[15:0] <= eff2[15:0];
effB[15:0] <= eff3[15:0];
end
//****************************************************************************//
//* Counter *//
//****************************************************************************//
always @ (posedge clk or posedge rst)
if (rst)
begin
cnt[(CNTWIDTH-1):0] <= {(CNTWIDTH){1'b0}};
end
else
begin
cnt[(CNTWIDTH-1):0] <= (cnt == 2) ?
0 :
cnt[(CNTWIDTH-1):0] + inValid;
end
//****************************************************************************//
//* Multiplier - Accumulator *//
//****************************************************************************//
always @ (posedge clk or posedge rst)
if (rst)
begin
mul00[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul01[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul02[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul03[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul10[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul11[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul12[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul13[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul20[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul21[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul22[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
mul23[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
end
else if (inValid)
begin
mul00[(ACCUMWIDTH-1):0] <= dsp_in0 * eff0;
mul01[(ACCUMWIDTH-1):0] <= dsp_in1 * eff1;
mul02[(ACCUMWIDTH-1):0] <= dsp_in2 * eff2;
mul03[(ACCUMWIDTH-1):0] <= dsp_in3 * eff3;
mul10[(ACCUMWIDTH-1):0] <= dsp_in0 * eff8;
mul11[(ACCUMWIDTH-1):0] <= dsp_in1 * eff9;
mul12[(ACCUMWIDTH-1):0] <= dsp_in2 * effA;
mul13[(ACCUMWIDTH-1):0] <= dsp_in3 * effB;
mul20[(ACCUMWIDTH-1):0] <= dsp_in0 * eff4;
mul21[(ACCUMWIDTH-1):0] <= dsp_in1 * eff5;
mul22[(ACCUMWIDTH-1):0] <= dsp_in2 * eff6;
mul23[(ACCUMWIDTH-1):0] <= dsp_in3 * eff7;
end
always @ (posedge clk or posedge rst)
if (rst)
begin
acc0[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
acc1[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
acc2[(ACCUMWIDTH-1):0] <= {(ACCUMWIDTH){1'b0}};
end
else if (inValid_z)
begin
acc0[(ACCUMWIDTH-1):0] <= mul00 + mul01 + mul02 + mul03 +
({(ACCUMWIDTH){cnt[(CNTWIDTH-1):0]==(2)|
cnt[(CNTWIDTH-1):0]==(0)} }
& acc0[(ACCUMWIDTH-1):0] );
acc1[(ACCUMWIDTH-1):0] <= mul10 + mul11 + mul12 + mul13 +
({(ACCUMWIDTH){cnt[(CNTWIDTH-1):0]==(1)|
cnt[(CNTWIDTH-1):0]==(0)} }
& acc1[(ACCUMWIDTH-1):0] );
acc2[(ACCUMWIDTH-1):0] <= mul20 + mul21 + mul22 + mul23 +
({(ACCUMWIDTH){cnt[(CNTWIDTH-1):0]==(1)|
cnt[(CNTWIDTH-1):0]==(2)} }
& acc2[(ACCUMWIDTH-1):0] );
end
//****************************************************************************//
//* Output Buffers *//
//****************************************************************************//
assign result[(ACCUMWIDTH-1):0] = ({(ACCUMWIDTH){cnt==1}} & acc0[(ACCUMWIDTH-1):0]) |
({(ACCUMWIDTH){cnt==2}} & acc1[(ACCUMWIDTH-1):0]) |
({(ACCUMWIDTH){cnt==0}} & acc2[(ACCUMWIDTH-1):0]) ;
always @ (posedge clk or posedge rst)
if (rst)
begin
inValid_z <= 0;
outValid <= 0;
dsp_out[(OWIDTH-1):0]<= {(OWIDTH){1'b0}};
end
else
begin
inValid_z <= inValid;
outValid <= inValid_z;
dsp_out[(OWIDTH-1):0]<= inValid_z ?
result[(ACCUMWIDTH-3):(ACCUMWIDTH-OWIDTH-2)] :
dsp_out[(OWIDTH-1):0];
end
endmodule // firdecim_m4_n12
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_1_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_1_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv3sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv3sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_1_V
|
#include <bits/stdc++.h> using namespace std; ; const long long maxn = 1e5 + 7; const long double pi = 3.14159265358979323846; struct pirog { long long r; long long h; long long i; }; long long V[4 * maxn]; pirog A[maxn]; vector<pirog> C; void update(long long v, long long tl, long long tr, long long i, long long color) { if (tl == tr) { V[v] = color; return; } long long tm = (tl + tr) / 2; if (tm >= i) { update(2 * v, tl, tm, i, color); } else { update(2 * v + 1, tm + 1, tr, i, color); } V[v] = max(V[2 * v], V[2 * v + 1]); } long long mx(long long v, long long tl, long long tr, long long l, long long r) { if (tl > r || l > tr) { return 0; } if (tl == l && tr == r) { return V[v]; } long long tm = (tl + tr) / 2; return max(mx(2 * v, tl, tm, l, min(tm, r)), mx(2 * v + 1, tm + 1, tr, max(l, tm + 1), r)); } bool cmp(pirog a, pirog b) { return a.h * a.r * a.r < b.h * b.r * b.r; } long long X[maxn]; int main() { long long q, w, e, k, n; cin >> n; cout << fixed << setprecision(10); for (q = 0; q < n; q++) { cin >> A[q].r >> A[q].h; A[q].i = q; C.push_back(A[q]); } sort(C.begin(), C.end(), cmp); long long l = 0; for (q = 0; q < n; q++) { long long x = mx(1, 0, n - 1, 0, C[q].i) + C[q].h * C[q].r * C[q].r; X[q] = x; if (C[q].r * C[q].r * C[q].h == C[q + 1].r * C[q + 1].r * C[q + 1].h) { continue; } for (w = l; w <= q; w++) { update(1, 0, n - 1, C[w].i, X[w]); } l = q + 1; } cout << mx(1, 0, n - 1, 0, n - 1) * pi; return 0; }
|
#include <bits/stdc++.h> int main() { int n; std::cin >> n; std::vector<int> a(n); std::vector<int> mn(n); for (int i = 0; i < n; ++i) { std::cin >> a[i]; } mn[n - 1] = a[n - 1]; for (int i = n - 2; i >= 0; --i) { if (a[i] < mn[i + 1]) { mn[i] = a[i]; } else { mn[i] = mn[i + 1]; } } for (int i = 0; i < n; ++i) { int left = i; int right = n - 1; int val = a[i]; while (left != right) { int mid = (left + right + 1) / 2; if (mn[mid] < val) { left = mid; } else { right = mid - 1; } } std::cout << right - i - 1 << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_TB_V
`define SKY130_FD_SC_HS__FAH_TB_V
/**
* fah: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fah.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 CI = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 CI = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 CI = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 CI = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__fah dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_TB_V
|
#include <bits/stdc++.h> using namespace std; long long int n, m; long long int power(long long int a, long long int b) { if (b == 0) return 1; long long int sr = power(a, b >> 1); long long int r = sr * sr; if (b & 1) r = a * r; return r; } void solve() { long long int z = power(2, 0); cin >> n; vector<long long int> v(n); long long int ans = 0; long long int p = 1; for (long long int i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); long long int count = 0; for (long long int i = 0; i < n; i++) { if (v[i] >= z) { ans += (count * (count - 1) / 2); while (v[i] >= z) { z = power(2, p); p++; } count = 0; } count++; } ans += (count * (count - 1) / 2); cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int x; cin >> x; for (long long int i = 1; i <= x; i++) solve(); return 0; }
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