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module MUX8_1(Sel,S0,S1,S2,S3,S4,S5,S6,S7,out);
input [2:0] Sel;
input [7:0] S0,S1,S2,S3,S4,S5,S6,S7;
output [7:0]out;
assign out = (Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module MUX4_1(Sel,S0,S1,S2,S3,out);
input [1:0] Sel;
input [7:0] S0,S1,S2,S3;
output [7:0]out;
assign out = (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module Memory_ShiftOutput(
input [31:0] Mem_data_out,
input [1:0] Mem_addr_in,
input [31:26] IR,
output [31:0] Mem_data_shift
);
wire [2:0] MEM_data_shift_ctr;
wire [31:0]Mem_d_l,Mem_d_r;
assign MEM_data_shift_ctr[2] = (IR[31])&(!IR[30])&(!IR[29])&(((!IR[28])&(IR[27])) | ((IR[27])&(!IR[26])) );
assign MEM_data_shift_ctr[1] = (IR[31])&(!IR[30])&(!IR[29])&(((!IR[27])&(IR[26])) | ((IR[28])&(IR[27])&(!IR[26])));
assign MEM_data_shift_ctr[0] = (IR[31])&(!IR[30])&(!IR[29])&(((IR[28])&(!IR[27])) | ((!IR[28])&(IR[27])&(!IR[26])));
MUX4_1 mux4_1_10(Mem_addr_in[1:0],Mem_data_out[31:24],Mem_data_out[23:16],Mem_data_out[15:8],Mem_data_out[7:0],Mem_d_l[31:24]);
MUX4_1 mux4_1_11(Mem_addr_in[1:0],Mem_data_out[23:16],Mem_data_out[15:8],Mem_data_out[7:0],8'b0,Mem_d_l[23:16]);
MUX4_1 mux4_1_12(Mem_addr_in[1:0],Mem_data_out[15:8],Mem_data_out[7:0],8'b0,8'b0,Mem_d_l[15:8]);
MUX4_1 mux4_1_13(Mem_addr_in[1:0],Mem_data_out[7:0],8'b0,8'b0,8'b0,Mem_d_l[7:0]);
MUX4_1 mux4_1_14(Mem_addr_in[1:0],8'b0,8'b0,8'b0,Mem_data_out[31:24],Mem_d_r[31:24]);
MUX4_1 mux4_1_15(Mem_addr_in[1:0],8'b0,8'b0,Mem_data_out[31:24],Mem_data_out[23:16],Mem_d_r[23:16]);
MUX4_1 mux4_1_16(Mem_addr_in[1:0],8'b0,Mem_data_out[31:24],Mem_data_out[23:16],Mem_data_out[15:8],Mem_d_r[15:8]);
MUX4_1 mux4_1_17(Mem_addr_in[1:0],Mem_data_out[31:24],Mem_data_out[23:16],Mem_data_out[15:8],Mem_data_out[7:0],Mem_d_r[7:0]);
MUX8_1 mux8_1_10(MEM_data_shift_ctr[2:0],{8{Mem_d_l[31]}},8'b0,{8{Mem_d_l[31]}},8'b0,Mem_d_l[31:24],Mem_d_l[31:24],Mem_d_r[31:24],8'b0,Mem_data_shift[31:24]);
MUX8_1 mux8_1_11(MEM_data_shift_ctr[2:0],{8{Mem_d_l[31]}},8'b0,{8{Mem_d_l[31]}},8'b0,Mem_d_l[23:16],Mem_d_l[23:16],Mem_d_r[23:16],8'b0,Mem_data_shift[23:16]);
MUX8_1 mux8_1_12(MEM_data_shift_ctr[2:0],{8{Mem_d_l[31]}},8'b0,Mem_d_l[31:24],Mem_d_l[31:24],Mem_d_l[15:8],Mem_d_l[15:8],Mem_d_r[15:8],8'b0,Mem_data_shift[15:8]);
MUX8_1 mux8_1_13(MEM_data_shift_ctr[2:0],Mem_d_l[31:24],Mem_d_l[31:24],Mem_d_l[23:16],Mem_d_l[23:16],Mem_d_l[7:0],Mem_d_l[7:0],Mem_d_r[7:0],8'b0,Mem_data_shift[7:0]);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int ans = 6; for (int i = 4; i <= n; i++) { ans += (i - 1) * i; } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5, MX = 2e5, MN = 0; struct node; extern node* empty; struct node { int mx; node *LF, *RT; node() : mx(0), LF(this), RT(this) {} node(int val, node* lf = empty, node* rt = empty) : mx(val), LF(lf), RT(rt) {} }; node* empty = new node(); node* insert(int val, int ind, node* cur, int ns = 0, int ne = MX) { if (ind > ne or ind < ns) return cur; if (ns == ne) return new node(val); int mid = ns + (ne - ns) / 2; node* lf = insert(val, ind, cur->LF, ns, mid); node* rt = insert(val, ind, cur->RT, mid + 1, ne); return new node(max(lf->mx, rt->mx), lf, rt); } int getMax(int qe, node* cur, int ns = 0, int ne = MX) { if (qe < 0) return 0; if (ns > qe) return 0; if (ne <= qe) return cur->mx; int mid = ns + (ne - ns) / 2; return max(getMax(qe, cur->LF, ns, mid), getMax(qe, cur->RT, mid + 1, ne)); } node* roots[N]; int main() { int n, m; scanf( %d%d , &n, &m); for (long long i = 1; i <= n; i++) { roots[i] = empty; } for (long long i = 0; i < m; i++) { int a, b, w; scanf( %d%d%d , &a, &b, &w); roots[b] = insert(getMax(w - 1, roots[a]) + 1, w, roots[b]); } int ans = 0; for (long long i = 1; i <= n; i++) { ans = max(ans, getMax(MX, roots[i])); } printf( %d n , ans); return 0; }
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module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[7];
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int ans[] = {0, 1, 0, 18, 0, 1800, 0, 670320, 0, 734832000, 0, 890786230, 0, 695720788, 0, 150347555, 0}; int n; cin >> n; cout << ans[n] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[200007], b[200007]; bool check[200007]; int main() { string s; getline(cin, s); int res = 0; for (auto i = (0); i <= ((int)s.size() - 1); ++i) { int tmp = s[i]; int ans = 0; for (auto i = (1); i <= (8); ++i) { ans = 2 * ans + tmp % 2; tmp /= 2; } printf( %d n , (res - ans + 256) % 256); res = ans; } return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) using namespace std; string s; const int maxn = (int)1e5 + 1; const int maxlog = 19; struct vt { int w[26]; vector<int> lnk[26]; vector<int> rlnk[26]; string s; vt() {} vt(string s) : s(s) {} int get_cnt(int l, int r) { int ans = 0; for (int i = 0; i < 26; i++) { if (lnk[i][r] >= l || i == s[r] - a ) { ans++; } } return ans - 1; } vector<long long> sum[1][26]; vector<pair<int, int> > tab[1][26]; void build() { memset(w, -1, sizeof w); for (int i = 0; i < 26; i++) { lnk[i].resize(s.size()); rlnk[i].resize(s.size()); for (int j = 0; j < 1; j++) { sum[j][i].resize(s.size()); tab[j][i].resize(s.size()); } } for (int i = 0; i < (int)s.size(); i++) { for (int j = 0; j < 26; j++) { lnk[j][i] = w[j]; } w[s[i] - a ] = i; } for (int j = 0; j < 26; j++) { w[j] = (int)s.size() - 1; } for (int i = (int)s.size() - 1; i >= 0; i--) { for (int j = 0; j < 26; j++) { rlnk[j][i] = w[j]; } w[s[i] - a ] = i; } for (int i = 0; i < (int)s.size(); i++) { vector<int> g; for (int j = 0; j < 26; j++) { if (j != s[i] - a ) { g.push_back(lnk[j][i]); } else { g.push_back(i); } } sort(g.rbegin(), g.rend()); int rm = i; for (int j = 0; j < (int)g.size(); j++) { if (g[j] == -1) { tab[0][j][i] = tab[0][j - 1][i]; sum[0][j][i] = sum[0][j - 1][i]; continue; } rm = max(rm, rlnk[s[g[j]] - a ][g[j]]); int lm = g[j]; int cnt = get_cnt(lm, rm); tab[0][j][i] = make_pair(cnt, rm); sum[0][j][i] = rm; } } } vector<long long> sums[maxlog]; vector<int> tot[maxlog]; vector<int> tabs[maxlog]; void build(int k) { for (int i = 0; i < maxlog; i++) { sums[i].assign(s.size(), 0); tabs[i].assign(s.size(), -1); tot[i].assign(s.size(), 0); } for (int i = 0; i < (int)s.size(); i++) { if (tab[0][k][i].first == k) { sums[0][i] = tab[0][k][i].second; tabs[0][i] = tab[0][k][i].second; tot[0][i] = 1; } else { sums[0][i] = 0; tabs[0][i] = i; tot[0][i] = 0; } } for (int it = 1; it < maxlog; it++) { for (int i = 0; i < (int)s.size(); i++) { tabs[it][i] = tabs[it - 1][tabs[it - 1][i]]; sums[it][i] = sums[it - 1][i] + sums[it - 1][tabs[it - 1][i]]; tot[it][i] = tot[it - 1][i] + tot[it - 1][tabs[it - 1][i]]; } } } }; long long stup(int pos) { int lm = pos; int rm = pos; int n = (int)s.size(); long long ans = 0; while (rm - lm + 1 != n) { ans += n - 1 - (rm - lm); int mask = 0; for (int i = lm; i <= rm; i++) { mask |= (1 << (s[i] - a )); } int l = lm; while (lm > 0 && mask != 0) { lm--; int c = s[lm] - a ; if ((mask >> c) & 1) { mask ^= (1 << c); } } mask = 0; for (int i = l; i <= rm; i++) { mask |= (1 << (s[i] - a )); } while (rm < n - 1 && mask != 0) { rm++; int c = s[rm] - a ; if ((mask >> c) & 1) { mask ^= (1 << c); } } } return ans; } int main() { cin >> s; for (int i = 0; i < (int)1e4; i++) { } vt dpr = vt(s); dpr.build(); reverse(s.begin(), s.end()); vt dpl = vt(s); dpl.build(); reverse(s.begin(), s.end()); long long ans = 0; long long pre = 0; int n = (int)s.size(); vector<pair<int, int> > cur; for (int i = 0; i < (int)s.size(); i++) { cur.push_back(make_pair(n - 1 - i, i)); ans += n - 1; } for (int j = 0; j < 26; j++) { dpr.build(j); dpl.build(j); for (int i = 0; i < (int)s.size(); i++) { int lm = cur[i].first; int rm = cur[i].second; int cnt = dpr.get_cnt(n - 1 - lm, rm); if (cnt == j) { for (int it = maxlog - 1; it >= 0; it--) { if (dpr.tot[it][rm] == (1 << it) && dpl.tot[it][lm] == (1 << it)) { ans -= dpr.sums[it][rm]; rm = dpr.tabs[it][rm]; ans -= dpl.sums[it][lm]; ans += 2ll * (n - 1) * (1 << it); lm = dpl.tabs[it][lm]; } } rm = dpr.tab[0][cnt][rm].second; lm = dpl.tab[0][cnt][lm].second; ans -= rm + lm; ans += 2 * (n - 1); cur[i].first = lm; cur[i].second = rm; } } } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; int n; struct node { int cnt; node* bit[3]; node() { bit[0] = bit[1] = NULL; cnt = 0; } }; node* root; void Insertt(int x) { node* cur = root; for (int i = 28; i >= 0; --i) { if (cur->bit[(x >> i) & 1] == NULL) cur->bit[(x >> i) & 1] = new node(); cur = cur->bit[(x >> i) & 1]; ++(cur->cnt); } } void Erasee(int x) { node* cur = root; for (int i = 28; i >= 0; --i) { --(cur->bit[(x >> i) & 1]->cnt); if (cur->bit[(x >> i) & 1]->cnt == 0) { cur->bit[(x >> i) & 1] = NULL; return; } else cur = cur->bit[(x >> i) & 1]; } } int Query(int p, int l) { int res = 0; node* cur = root; for (int i = 28; i >= 0; --i) { if (((l >> i) & 1) == 0) { if (cur->bit[(p >> i) & 1] != NULL) cur = cur->bit[(p >> i) & 1]; else return res; } else { if (cur->bit[(p >> i) & 1] != NULL) res += cur->bit[(p >> i) & 1]->cnt; if (cur->bit[(1 ^ ((p >> i) & 1))] != NULL) cur = cur->bit[(1 ^ ((p >> i) & 1))]; else return res; } } return res; } int main() { scanf( %d , &n); root = new node(); for (int i = 1; i <= n; ++i) { int type, p, l; scanf( %d%d , &type, &p); if (type == 1) Insertt(p); if (type == 2) Erasee(p); if (type == 3) { scanf( %d , &l); printf( %d n , Query(p, l)); } } return 0; }
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#include<bits/stdc++.h> typedef long long ll; using namespace std; const int MAXN = 5005; int tag[MAXN],s[MAXN]; ll dp[MAXN]; int main(){ ios::sync_with_stdio(false); int t;cin>>t; while(t--){ int n;cin>>n; for(int i=1;i<=n;i++){ cin>>tag[i]; } for(int i=1;i<=n;i++){ cin>>s[i]; dp[i]=0; } for(int i=2;i<=n;i++){ for(int j=i-1;j>=1;j--){ if(tag[i]==tag[j]) continue; ll di=dp[i],dj=dp[j],add=abs(s[i]-s[j]); dp[i]=max(dp[i],dj+add); dp[j]=max(dp[j],di+add); } } ll ans=0; for(int i=1;i<=n;i++){ ans=max(ans,dp[i]); } cout<<ans<< n ; } return 0; }
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/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_pulse.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU noise channel.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_pulse
#(
parameter [0:0] CHANNEL = 1'b0 // Pulse channel 0 or 1
)
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] pulse_out, // pulse channel output
output wire active_out // pulse channel active (length counter > 0)
);
//
// Envelope
//
wire envelope_generator_wr;
wire envelope_generator_restart;
wire [3:0] envelope_generator_out;
apu_envelope_generator envelope_generator(
.clk_in(clk_in),
.rst_in(rst_in),
.eg_pulse_in(eg_pulse_in),
.env_in(d_in[5:0]),
.env_wr_in(envelope_generator_wr),
.env_restart(envelope_generator_restart),
.env_out(envelope_generator_out)
);
assign envelope_generator_wr = wr_in && (a_in == 2'b00);
assign envelope_generator_restart = wr_in && (a_in == 2'b11);
//
// Timer
//
reg [10:0] q_timer_period, d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(12)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in({ q_timer_period, 1'b0 }),
.pulse_out(timer_pulse)
);
//
// Sequencer
//
wire [3:0] sequencer_out;
reg [1:0] q_duty;
wire [1:0] d_duty;
reg [2:0] q_sequencer_cnt;
wire [2:0] d_sequencer_cnt;
wire seq_bit;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_duty <= 2'h0;
q_sequencer_cnt <= 3'h0;
end
else
begin
q_duty <= d_duty;
q_sequencer_cnt <= d_sequencer_cnt;
end
end
assign d_duty = (wr_in && (a_in == 2'b00)) ? d_in[7:6] : q_duty;
assign d_sequencer_cnt = (timer_pulse) ? q_sequencer_cnt - 3'h1 : q_sequencer_cnt;
assign seq_bit = (q_duty == 2'h0) ? &q_sequencer_cnt[2:0] :
(q_duty == 2'h1) ? &q_sequencer_cnt[2:1] :
(q_duty == 2'h2) ? q_sequencer_cnt[2] : ~&q_sequencer_cnt[2:1];
assign sequencer_out = (seq_bit) ? envelope_generator_out : 4'h0;
//
// Sweep
//
reg q_sweep_reload;
wire d_sweep_reload;
reg [7:0] q_sweep_reg;
wire [7:0] d_sweep_reg;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_sweep_reg <= 8'h00;
q_sweep_reload <= 1'b0;
end
else
begin
q_sweep_reg <= d_sweep_reg;
q_sweep_reload <= d_sweep_reload;
end
end
assign d_sweep_reg = (wr_in && (a_in == 2'b01)) ? d_in : q_sweep_reg;
assign d_sweep_reload = (wr_in && (a_in == 2'b01)) ? 1'b1 :
(lc_pulse_in) ? 1'b0 : q_sweep_reload;
wire sweep_divider_reload;
wire sweep_divider_pulse;
reg sweep_silence;
reg [11:0] sweep_target_period;
apu_div #(.PERIOD_BITS(3)) sweep_divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(lc_pulse_in),
.reload_in(sweep_divider_reload),
.period_in(q_sweep_reg[6:4]),
.pulse_out(sweep_divider_pulse)
);
assign sweep_divider_reload = lc_pulse_in & q_sweep_reload;
always @*
begin
sweep_target_period =
(!q_sweep_reg[3]) ? q_timer_period + (q_timer_period >> q_sweep_reg[2:0]) :
q_timer_period + ~(q_timer_period >> q_sweep_reg[2:0]) + CHANNEL;
sweep_silence = (q_timer_period[10:3] == 8'h00) || sweep_target_period[11];
if (wr_in && (a_in == 2'b10))
d_timer_period = { q_timer_period[10:8], d_in };
else if (wr_in && (a_in == 2'b11))
d_timer_period = { d_in[2:0], q_timer_period[7:0] };
else if (sweep_divider_pulse && q_sweep_reg[7] && !sweep_silence && (q_sweep_reg[2:0] != 3'h0))
d_timer_period = sweep_target_period[10:0];
else
d_timer_period = q_timer_period;
end
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_length_counter_halt <= 1'b0;
end
else
begin
q_length_counter_halt <= d_length_counter_halt;
end
end
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[5] : q_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign length_counter_wr = wr_in && (a_in == 2'b11);
assign pulse_out = (length_counter_en && !sweep_silence) ? sequencer_out : 4'h0;
assign active_out = length_counter_en;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > adj(500005); int visited[500005]; int counter; void dfs(int node, int color) { counter++; visited[node] = color; for (int i = 0; i < adj[node].size(); ++i) { if (visited[adj[node][i]] == 0) dfs(adj[node][i], color); } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int test = 1; while (test--) { int n, val; cin >> n; vector<int> arr; for (int i = 0; i < n; ++i) { cin >> val; arr.push_back(val); } string s; cin >> s; vector<pair<int, int> > v; int flag = 0, start = -1, ender = -1; for (int i = 0; i < s.size(); ++i) { if (flag == 0 && s[i] == 0 ) continue; if (flag == 0 && s[i] == 1 ) { start = i; flag = 1; continue; } if (flag == 1 && s[i] == 0 ) { ender = i; v.push_back({start, ender}); start = -1; ender = -1; flag = 0; continue; } if (flag == 1 && s[i] == 1 ) continue; } if (flag == 1) v.push_back({start, n - 1}); vector<pair<int, int> >::iterator it; for (it = v.begin(); it != v.end(); ++it) { sort(arr.begin() + it->first, arr.begin() + it->second + 1); } flag = 0; for (int i = 1; i < n; ++i) { if (arr[i] <= arr[i - 1]) { flag = 1; break; } } if (flag == 1) cout << NO ; else cout << YES ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j, k = -1, c, d; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= m; i++) { scanf( %d %d , &c, &d); if (k == -1 || (d - c + 1) < k) { k = d - c + 1; } } printf( %d n , k); c = 0; for (i = 1; i <= n; i++) { printf( %d , c); c = (c + 1) % k; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3B_2_V
`define SKY130_FD_SC_MS__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3B_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, v, a, b, x; cin >> n >> v; int mp[3002] = {0}; for (int i = 0; i < n; i++) { cin >> a >> b; mp[a] += b; } int prev = 0, ans = 0; for (int i = 1; i <= 3001; i++) { int now = mp[i]; if (now + prev <= v) { ans += (now + prev); prev = 0; } else { ans += v; prev = now - max(v - prev, 0); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; const int inf = 1e7; int tree[4 * N + 100], ans[2 * N + 100]; vector<int> R[N + 100], C[N + 100]; vector<pair<pair<int, int>, pair<int, int> > > qr[N + 100], qc[N + 100]; void update(int v, int tl, int tr, int idx, int val) { if (tl == tr) { tree[v] = val; } else { int tm = (tl + tr) / 2; if (idx <= tm) { update(v * 2, tl, tm, idx, val); } else { update(v * 2 + 1, tm + 1, tr, idx, val); } tree[v] = min(tree[v * 2], tree[v * 2 + 1]); } } int getMin(int v, int tl, int tr, int l, int r) { if (l > r) { return inf; } if (l == tl && r == tr) { return tree[v]; } int tm = (tl + tr) / 2; return min(getMin(v * 2, tl, tm, l, min(r, tm)), getMin(v * 2 + 1, tm + 1, tr, max(tm + 1, l), r)); } int main() { int n, m, k, q; scanf( %d%d%d%d , &n, &m, &k, &q); for (int i = 1; i <= k; i++) { int x, y; scanf( %d%d , &x, &y); R[y].push_back(x); C[x].push_back(y); } for (int i = 1; i <= q; i++) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); qc[x2].push_back(make_pair(make_pair(y1, y2), make_pair(x1, i))); qr[y2].push_back(make_pair(make_pair(x1, x2), make_pair(y1, i))); } memset(tree, 0, sizeof tree); for (int i = 1; i <= n; i++) { for (auto it : C[i]) { update(1, 1, m, it, i); } for (auto it : qc[i]) { int mn = getMin(1, 1, m, it.first.first, it.first.second); if (mn >= it.second.first) { ans[it.second.second] = 1; } } } memset(tree, 0, sizeof tree); for (int i = 1; i <= m; i++) { for (auto it : R[i]) { update(1, 1, n, it, i); } for (auto it : qr[i]) { int mn = getMin(1, 1, n, it.first.first, it.first.second); if (mn >= it.second.first) { ans[it.second.second] = 1; } } } for (int i = 1; i <= q; i++) { if (ans[i]) { printf( YES n ); } else { printf( NO n ); } } }
|
module ERROR_OUTPUT_LOGIC #(
parameter [7:0] DATA_WIDTH = 1,
parameter [7:0] ADDR_WIDTH = 6
) (
input rst,
input clk,
input loop_complete,
input error_detected,
input [7:0] error_state,
input [ADDR_WIDTH-1:0] error_address,
input [DATA_WIDTH-1:0] expected_data,
input [DATA_WIDTH-1:0] actual_data,
// Output to UART
input tx_data_accepted,
output reg tx_data_ready,
output reg [7:0] tx_data
);
reg reg_error_detected;
reg [7:0] reg_error_state;
reg [ADDR_WIDTH-1:0] reg_error_address;
reg [DATA_WIDTH-1:0] reg_expected_data;
reg [DATA_WIDTH-1:0] reg_actual_data;
reg [7:0] error_count;
reg [7:0] output_shift;
wire [7:0] next_output_shift = output_shift + 8;
wire count_shift_done = next_output_shift >= 8'd16;
wire address_shift_done = next_output_shift >= ADDR_WIDTH;
wire data_shift_done = next_output_shift >= DATA_WIDTH;
reg loop_ready;
reg [7:0] latched_error_count;
reg [7:0] errors;
reg [10:0] state;
reg [15:0] loop_count;
reg [15:0] latched_loop_count;
localparam START = (1 << 0),
ERROR_COUNT_HEADER = (1 << 1),
ERROR_COUNT_COUNT = (1 << 2),
CR = (1 << 3),
LF = (1 << 4),
ERROR_HEADER = (1 << 5),
ERROR_STATE = (1 << 6),
ERROR_ADDRESS = (1 << 7),
ERROR_EXPECTED_DATA = (1 << 8),
ERROR_ACTUAL_DATA = (1 << 9),
LOOP_COUNT = (1 << 10);
initial begin
tx_data_ready <= 1'b0;
tx_data <= 8'b0;
state <= START;
reg_error_detected <= 1'b0;
end
always @(posedge clk) begin
if(rst) begin
state <= START;
error_count <= 0;
reg_error_detected <= 0;
tx_data_ready <= 0;
tx_data <= 8'b0;
loop_count <= 0;
loop_ready <= 0;
end else begin
if(error_detected) begin
if(error_count < 255) begin
error_count <= error_count + 1;
end
if(!reg_error_detected) begin
reg_error_detected <= 1;
reg_error_state <= error_state;
reg_error_address <= error_address;
reg_expected_data <= expected_data;
reg_actual_data <= actual_data;
end
end
if(tx_data_accepted) begin
tx_data_ready <= 0;
end
if(loop_complete) begin
loop_count <= loop_count + 1;
if(!loop_ready) begin
loop_ready <= 1;
latched_error_count <= error_count;
latched_loop_count <= loop_count;
error_count <= 0;
end
end
case(state)
START: begin
if(reg_error_detected) begin
state <= ERROR_HEADER;
end else if(loop_ready) begin
state <= ERROR_COUNT_HEADER;
end
end
ERROR_COUNT_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "L";
tx_data_ready <= 1;
state <= ERROR_COUNT_COUNT;
end
end
ERROR_COUNT_COUNT: begin
if(!tx_data_ready) begin
tx_data <= latched_error_count;
tx_data_ready <= 1;
output_shift <= 0;
state <= LOOP_COUNT;
end
end
LOOP_COUNT: begin
if(!tx_data_ready) begin
tx_data <= (latched_loop_count >> output_shift);
tx_data_ready <= 1;
if(count_shift_done) begin
output_shift <= 0;
loop_ready <= 0;
state <= CR;
end else begin
output_shift <= next_output_shift;
end
end
end
CR: begin
if(!tx_data_ready) begin
tx_data <= 8'h0D; // "\r"
tx_data_ready <= 1;
state <= LF;
end
end
LF: begin
if(!tx_data_ready) begin
tx_data <= 8'h0A; // "\n"
tx_data_ready <= 1;
state <= START;
end
end
ERROR_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "E";
tx_data_ready <= 1;
state <= ERROR_STATE;
end
end
ERROR_STATE: begin
if(!tx_data_ready) begin
tx_data <= reg_error_state;
tx_data_ready <= 1;
output_shift <= 0;
state <= ERROR_ADDRESS;
end
end
ERROR_ADDRESS: begin
if(!tx_data_ready) begin
tx_data <= (reg_error_address >> output_shift);
tx_data_ready <= 1;
if(address_shift_done) begin
output_shift <= 0;
state <= ERROR_EXPECTED_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_EXPECTED_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_expected_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
output_shift <= 0;
state <= ERROR_ACTUAL_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_ACTUAL_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_actual_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
state <= CR;
reg_error_detected <= 0;
end else begin
output_shift <= output_shift + 8;
end
end
end
default: begin
state <= START;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005, M = 500005; vector<int> gr[N], path, odd; pair<int, int> ed[M]; bool us[M]; void GetEulerCircuit(int u) { while (true) { while (!gr[u].empty() && us[gr[u].back()]) { gr[u].pop_back(); } if (gr[u].empty()) { break; } us[gr[u].back()] = true; int v = u ^ ed[gr[u].back()].first ^ ed[gr[u].back()].second; gr[u].pop_back(); GetEulerCircuit(v); } path.push_back(u); } int main() { ios_base::sync_with_stdio(false); cout.tie(0); int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int u, v; scanf( %d %d , &u, &v); ed[i] = make_pair(u, v); gr[u].push_back(i); gr[v].push_back(i); } for (int u = 1; u <= n; u++) { if (gr[u].size() % 2) { odd.push_back(u); } } for (int i = 0; i < odd.size(); i += 2) { int u = odd[i], v = odd[i + 1]; ed[m] = make_pair(u, v); gr[u].push_back(m); gr[v].push_back(m); m++; } if (m % 2) { ed[m] = make_pair(1, 1); gr[1].push_back(m); gr[1].push_back(m); m++; } GetEulerCircuit(1); for (int i = 0; i < m; i++) { int u = path[i], v = path[i + 1]; if (i % 2) { swap(u, v); } ed[i] = make_pair(u, v); } printf( %d n , m); for (int i = 0; i < m; i++) { int u = ed[i].first, v = ed[i].second; printf( %d %d n , u, v); } }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long fastexp(long long b, long long exp) { if (exp == 0) return 1; long long temp = fastexp(b, exp / 2); temp = (temp * temp) % 998244353; if (exp % 2 == 1) temp *= b; return temp % 998244353; } long long fact[100001], inv[100001]; void precompute() { fact[0] = 1; inv[0] = 1; for (int i = 1; i <= 100000; i++) { fact[i] = (fact[i - 1] * i) % 998244353; inv[i] = fastexp(fact[i], 998244353 - 2); } } long long choose(int n, int k) { if (n < 0 || k < 0 || k > n) return 0; long long ans = (fact[n] * inv[k]) % 998244353; ans = (ans * inv[n - k]) % 998244353; return ans; } bool row[3605], col[3605]; int H, W, N; long long dp1[3605][3605], dp2[3605][3605]; int emptyH, emptyW; int main() { ios_base::sync_with_stdio(0); cin.tie(0); precompute(); cin >> H >> W >> N; for (int i = 0; i < N; i++) { int r1, c1, r2, c2; cin >> r1 >> c1 >> r2 >> c2; row[r1] = true; row[r2] = true; col[c1] = true; col[c2] = true; } for (int i = 1; i <= H; i++) if (!row[i]) emptyH++; for (int i = 1; i <= W; i++) if (!col[i]) emptyW++; dp1[0][0] = true; for (int i = 1; i <= H; i++) { for (int j = 0; j <= i; j++) { if (row[i] || row[i - 1]) dp1[i][j] = dp1[i - 1][j]; else { dp1[i][j] = dp1[i - 1][j]; if (i - 2 >= 0 && j - 1 >= 0) dp1[i][j] += dp1[i - 2][j - 1]; dp1[i][j] %= 998244353; } } } dp2[0][0] = true; for (int i = 1; i <= W; i++) { for (int j = 0; j <= i; j++) { if (col[i] || col[i - 1]) dp2[i][j] = dp2[i - 1][j]; else { dp2[i][j] = dp2[i - 1][j]; if (i - 2 >= 0 && j - 1 >= 0) dp2[i][j] += dp2[i - 2][j - 1]; dp2[i][j] %= 998244353; } } } long long ans = 0; for (int i = 0; i <= H; i++) { for (int j = 0; j <= W; j++) { long long R = dp1[H][j] * choose(emptyH - 2 * j, i); R %= 998244353; long long C = dp2[W][i] * choose(emptyW - 2 * i, j); C %= 998244353; long long F = (fact[i] * fact[j]) % 998244353; ans += ((R * C) % 998244353 * F) % 998244353; ans %= 998244353; } } cout << ans << endl; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: exam.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module exam (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/exam.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/exam.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/exam.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; if (k == 2) puts( 1 1 ); if (k == 3) puts( 1 0 1 ); if (k == 4) puts( 0 0 1 1 ); if (k == 5) puts( 1 1 1 0 1 ); if (k == 6) puts( 1 0 0 1 1 1 ); if (k == 7) puts( 1 1 1 0 1 1 1 ); if (k == 8) puts( 1 0 0 0 1 1 0 1 ); if (k == 9) puts( 1 0 1 1 0 1 1 0 1 ); if (k == 10) puts( 0 0 0 0 0 0 1 0 0 1 ); if (k == 11) puts( 0 0 1 1 0 1 0 1 1 0 1 ); if (k == 12) puts( 0 1 0 0 0 1 0 1 1 1 0 1 ); if (k == 13) puts( 1 1 1 1 0 0 0 0 1 1 0 1 1 ); if (k == 14) puts( 0 1 1 1 1 0 0 0 0 0 1 1 1 1 ); if (k == 15) puts( 1 1 1 1 0 1 0 1 1 0 1 1 0 0 1 ); if (k == 16) puts( 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 ); if (k == 17) puts( 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 1 ); if (k == 18) puts( 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 1 ); if (k == 19) puts( 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 1 ); if (k == 20) puts( 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 ); if (k == 21) puts( 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 ); if (k == 22) puts( 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 ); if (k == 23) puts( 1 1 1 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 1 1 ); if (k == 24) puts( 1 1 1 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 ); if (k == 25) puts( 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 ); if (k == 26) puts( 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 0 1 ); if (k == 27) puts( 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 1 1 ); if (k == 28) puts( 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 ); if (k == 29) puts( 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 ); if (k == 30) puts( 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 ); if (k == 31) puts( 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 ); if (k == 32) puts( 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 0 0 0 1 1 0 1 0 1 ); if (k == 33) puts( 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 ); if (k == 34) puts( 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 ); if (k == 35) puts( 0 0 1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 ); if (k == 36) puts( 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 ); if (k == 37) puts( 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 ); if (k == 38) puts( 1 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 ); if (k == 39) puts( 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 1 ); if (k == 40) puts( 1 0 1 1 0 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 ); if (k == 41) puts( 1 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 ); if (k == 42) puts( 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 0 1 0 0 1 ); if (k == 43) puts( 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 1 ); if (k == 44) puts( 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 0 1 ); if (k == 45) puts( 0 0 1 0 1 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 ); if (k == 46) puts( 1 1 0 1 0 1 1 0 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 1 1 ); if (k == 47) puts( 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 1 ); if (k == 48) puts( 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 1 ); if (k == 49) puts( 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 ); if (k == 50) puts( 1 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 ); for (int i = 1; i <= k; ++i) printf((i > 1) ? 1 : 1 ); puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_SYMBOL_V
`define SKY130_FD_SC_HS__DLXTN_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:45 02/20/2015
// Design Name:
// Module Name: Fetch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Fetch_Crude(
input [98:0] InstructionPacket,
input clock,
input stall,
output reg [31:0] x_input = 32'h00000000,
output reg [31:0] y_input = 32'h00000000,
output reg [31:0] z_input = 32'h00000000,
output reg [1:0] mode,
output reg operation,
output reg load = 1'b0
);
wire [3:0] Opcode;
wire [31:0] x_processor;
wire [31:0] y_processor;
wire [31:0] z_processor;
assign Opcode = InstructionPacket[98:96];
assign x_processor = InstructionPacket[31:0];
assign y_processor = InstructionPacket[63:32];
assign z_processor = InstructionPacket[95:64];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // This requires pre processing. x = (a+1)/4 and y = (a-1)/4
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10;
parameter vectoring = 1'b0,
rotation = 1'b1;
parameter circular = 2'b01,
linear = 2'b00,
hyperbolic = 2'b11;
always @ (posedge clock)
begin
if (stall == 1'b0) begin
case(Opcode)
sin_cos:
begin
mode <= circular;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
sinh_cosh:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
arctan:
begin
mode <= circular;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
arctanh:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
exp:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h3F800000;
z_input <= z_processor;
load <= 1'b1;
end
sqr_root:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= Register_File[x_address];
y_input <= Register_File[y_address];
z_input <= 32'h00000000;
load <= 1'b1;
end
division:
begin
mode <= linear;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
hypotenuse:
begin
mode <= circular;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
endcase
end
else begin
load <= 1'b0;
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:09:46 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a,
bram_wrdata_a, bram_rddata_a, bram_rst_b, bram_clk_b, bram_en_b, bram_we_b, bram_addr_b,
bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [11:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, cnt11 = 0, cnt10 = 0, cnt01 = 0; string s, t; cin >> n >> s >> t; for (int i = 0; i < 2 * n; ++i) { if (s[i] == 1 && t[i] == 1 ) ++cnt11; else if (s[i] == 1 ) ++cnt10; else if (t[i] == 1 ) ++cnt01; } if (cnt11 & 1) { if (cnt10 >= cnt01) puts( First ); else if (cnt10 + 1 == cnt01 || cnt10 + 2 == cnt01) puts( Draw ); else puts( Second ); } else { if (cnt10 == cnt01 || cnt10 + 1 == cnt01) puts( Draw ); else if (cnt01 < cnt10) puts( First ); else puts( Second ); } return 0; }
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:48 EST 2017
//
// Method conflict info:
// Method: select
// Conflict-free: select
// Sequenced before: next
//
// Method: next
// Sequenced after: select
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// select O 5
// CLK I 1 clock
// RST_N I 1 reset
// select_requests I 5
// EN_next I 1
//
// Combinational paths from inputs to outputs:
// select_requests -> select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkInputArbiter(CLK,
RST_N,
select_requests,
select,
EN_next);
input CLK;
input RST_N;
// value method select
input [4 : 0] select_requests;
output [4 : 0] select;
// action method next
input EN_next;
// signals for module outputs
wire [4 : 0] select;
// register arb_token
reg [4 : 0] arb_token;
wire [4 : 0] arb_token$D_IN;
wire arb_token$EN;
// remaining internal signals
wire [1 : 0] ab__h1657,
ab__h1672,
ab__h1687,
ab__h1702,
ab__h1717,
ab__h3098,
ab__h3545,
ab__h3938,
ab__h4282,
ab__h4577;
wire NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
ab_BIT_0___h2269,
ab_BIT_0___h2376,
ab_BIT_0___h2483,
ab_BIT_0___h2590,
ab_BIT_0___h3169,
ab_BIT_0___h3305,
ab_BIT_0___h3698,
ab_BIT_0___h4042,
ab_BIT_0___h4337,
arb_token_BIT_0___h2267,
arb_token_BIT_1___h2374,
arb_token_BIT_2___h2481,
arb_token_BIT_3___h2588,
arb_token_BIT_4___h2695;
// value method select
assign select =
{ ab__h1657[1] || ab__h3098[1],
!ab__h1657[1] && !ab__h3098[1] &&
(ab__h1672[1] || ab__h3545[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h1657[1] && !ab__h3098[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// register arb_token
assign arb_token$D_IN = { arb_token[0], arb_token[4:1] } ;
assign arb_token$EN = EN_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h1717));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h2269),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h1702));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h2376),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h1687));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h2483),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h1672));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h2590),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h1657));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h3169),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h4577));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h4337),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h4282));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h4042),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h3938));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h3698),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h3545));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h3305),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h3098));
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
(ab__h1687[1] || ab__h3938[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h1687[1] && !ab__h3938[1] && !ab__h1702[1] &&
!ab__h4282[1] &&
(ab__h1717[1] || ab__h4577[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h1672[1] && !ab__h3545[1] && !ab__h1687[1] &&
!ab__h3938[1] &&
(ab__h1702[1] || ab__h4282[1]) ;
assign ab_BIT_0___h2269 = ab__h1717[0] ;
assign ab_BIT_0___h2376 = ab__h1702[0] ;
assign ab_BIT_0___h2483 = ab__h1687[0] ;
assign ab_BIT_0___h2590 = ab__h1672[0] ;
assign ab_BIT_0___h3169 = ab__h1657[0] ;
assign ab_BIT_0___h3305 = ab__h3545[0] ;
assign ab_BIT_0___h3698 = ab__h3938[0] ;
assign ab_BIT_0___h4042 = ab__h4282[0] ;
assign ab_BIT_0___h4337 = ab__h4577[0] ;
assign arb_token_BIT_0___h2267 = arb_token[0] ;
assign arb_token_BIT_1___h2374 = arb_token[1] ;
assign arb_token_BIT_2___h2481 = arb_token[2] ;
assign arb_token_BIT_3___h2588 = arb_token[3] ;
assign arb_token_BIT_4___h2695 = arb_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
arb_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
end
else
begin
if (arb_token$EN) arb_token <= `BSV_ASSIGNMENT_DELAY arb_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
arb_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkInputArbiter
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000005; const int MD = 1000 * 1000 * 1000 + 7; vector<int> g[maxn]; long long dp[maxn][2], mult[maxn][2], ans, cnt[maxn]; bool visited[maxn]; int binPow(int a, int b) { if (!b) return 1; if (b & 1) { return (1LL * binPow(a, b - 1) * a) % MD; } else { int half = binPow(a, b / 2); return (1LL * half * half) % MD; } } long long inv(int a) { return binPow(a, MD - 2); } void dfs(int v) { cnt[v] = 1; visited[v] = true; mult[v][0] = mult[v][1] = 1; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (visited[to]) continue; dfs(to); cnt[v] += cnt[to]; mult[v][0] *= dp[to][0]; mult[v][0] %= MD; mult[v][1] *= dp[to][1]; mult[v][1] %= MD; } if (cnt[v] == 1) { dp[v][0] = dp[v][1] = 1; } else { dp[v][0] = (mult[v][0] + mult[v][1]) % MD; dp[v][1] = (mult[v][0] + mult[v][1]) % MD; } } void set_root(int v, int to) { cnt[v] -= cnt[to]; cnt[to] += cnt[v]; mult[v][0] *= inv(dp[to][0]); mult[v][0] %= MD; mult[v][1] *= inv(dp[to][1]); mult[v][1] %= MD; if (cnt[v] > 1) { dp[v][0] = (mult[v][0] + mult[v][1]) % MD; dp[v][1] = (mult[v][0] + mult[v][1]) % MD; } else { dp[v][0] = dp[v][1] = 1; } mult[to][0] *= dp[v][0]; mult[to][0] %= MD; mult[to][1] *= dp[v][1]; mult[to][1] %= MD; dp[to][0] = (mult[to][0] + mult[to][1]) % MD; dp[to][1] = (mult[to][0] + mult[to][1]) % MD; } void calc(int v, int parent) { ans += dp[v][0]; if (ans >= MD) ans -= MD; for (auto to : g[v]) { if (to == parent) continue; set_root(v, to); calc(to, v); set_root(to, v); } } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } ans = 0; memset(visited, false, sizeof(visited)); dfs(1); calc(1, 0); cout << ans << endl; return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "NIOS_Sys_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_FUNCTIONAL_PP_V
|
//########################################################################
//# ELINK TX CONFIGURATION REGISTER FILE
//########################################################################
`include "elink_regmap.vh"
module etx_cfg (/*AUTOARG*/
// Outputs
cfg_mmu_access, etx_cfg_access, etx_cfg_packet, tx_enable,
mmu_enable, gpio_enable, remap_enable, burst_enable, gpio_data,
ctrlmode, ctrlmode_bypass,
// Inputs
nreset, clk, cfg_access, etx_access, etx_packet, etx_wait,
tx_status
);
//##################################################################
//# INTERFACE
//##################################################################
//parameters
parameter AW = 32;
parameter PW = 2*AW+40;
parameter RFAW = 6;
parameter VERSION = 16'h0000;
parameter ID = 999;
//reset+clk
input nreset; // sync reset
input clk; // slow clock
//packet input
input cfg_access; // register access
input etx_access; // for transaction counter
input [PW-1:0] etx_packet; // for transaction sampler
input etx_wait; // wait signal
output cfg_mmu_access; // mmu access
//packet output (for RX)
output etx_cfg_access; // access for rx (write or rdata forward)
output [PW-1:0] etx_cfg_packet; // packet
//tx (static configs)
output tx_enable; // enable signal for TX
output mmu_enable; // enables MMU on transmit path
output gpio_enable; // forces TX output pins to constants
output remap_enable; // enable address remapping
output burst_enable; // enables bursting
output [8:0] gpio_data; // data for elink outputs (static)
output [3:0] ctrlmode; // value for emesh ctrlmode tag
output ctrlmode_bypass; // selects ctrlmode
input [15:0] tx_status; // tx status signals
//##################################################################
//# BODY
//##################################################################
//registers/wires
reg [15:0] tx_version_reg;
reg [15:0] tx_cfg_reg;
reg [8:0] tx_gpio_reg;
reg [15:0] tx_status_reg;
reg [31:0] tx_monitor_reg;
reg [31:0] tx_packet_reg;
reg [31:0] cfg_dout;
reg ecfg_access;
reg [1:0] datamode_out;
reg [4:0] ctrlmode_out;
reg write_out;
reg [AW-1:0] dstaddr_out;
reg [AW-1:0] srcaddr_out;
reg [AW-1:0] data_out;
reg read_sel;
reg etx_cfg_access;
wire [15:0] tx_status_sync;
wire [31:0] data_mux;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//###########################
//# DECODE LOGIC
//###########################
packet2emesh #(.AW(AW))
p2e (.packet_in (etx_packet[PW-1:0]),
/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]));
//read/write decode
assign tx_match = cfg_access &
(dstaddr_in[19:16] ==`EGROUP_MMR) &
(dstaddr_in[10:8] ==`EGROUP_TX);
//MMU access
assign cfg_mmu_access = cfg_access &
(dstaddr_in[19:16] ==`EGROUP_MMU) &
~dstaddr_in[15];
assign ecfg_read = tx_match & ~write_in;
assign ecfg_write = tx_match & write_in;
//Config write enables
assign tx_version_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`E_VERSION);
assign tx_cfg_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_CFG);
assign tx_status_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_STATUS);
assign tx_gpio_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_GPIO);
assign tx_monitor_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_MONITOR);
//###########################
//# TX CONFIG
//###########################
always @ (posedge clk)
if(!nreset)
tx_cfg_reg[15:0] <= 'b0;
else if (tx_cfg_write)
tx_cfg_reg[15:0] <= data_in[15:0];
assign tx_enable = 1'b1;//TODO: fix! ecfg_tx_config_reg[0];
assign mmu_enable = tx_cfg_reg[1];
assign remap_enable = (tx_cfg_reg[3:2]==2'b01);
assign ctrlmode[3:0] = tx_cfg_reg[7:4];
assign ctrlmode_bypass = tx_cfg_reg[9];
assign burst_enable = tx_cfg_reg[10];
assign gpio_enable = (tx_cfg_reg[12:11]==2'b01);
//###########################
//# STATUS REGISTER
//###########################
//Synchronize to make easy regular
oh_dsync isync[15:0] (.dout (tx_status_sync[15:0]),
.clk (clk),
.nreset (1'b1),
.din (tx_status[15:0]));
always @ (posedge clk)
if (tx_status_write)
tx_status_reg[15:0] <= data_in[15:0];
else
tx_status_reg[15:0]<= tx_status_reg[15:0] | {tx_status_sync[15:0]};
//###########################
//# GPIO DATA
//###########################
always @ (posedge clk)
if (tx_gpio_write)
tx_gpio_reg[8:0] <= data_in[8:0];
assign gpio_data[8:0] = tx_gpio_reg[8:0];
//###########################
//# VERSION
//###########################
always @ (posedge clk)
if(!nreset)
tx_version_reg[15:0] <= VERSION;
else if (tx_version_write)
tx_version_reg[15:0] <= data_in[15:0];
//###########################
//# MONITOR
//###########################
always @ (posedge clk)
if (tx_monitor_write)
tx_monitor_reg[31:0] <= data_in[31:0];
else
tx_monitor_reg[31:0] <= tx_monitor_reg[31:0] + (etx_access & ~etx_wait);
//###########################
//# PACKET (FOR DEBUG)
//###########################
always @ (posedge clk)
if(etx_access)
tx_packet_reg[31:0] <= etx_packet[39:8];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(dstaddr_in[RFAW+1:2])
`E_VERSION: cfg_dout[31:0] <= {16'b0, tx_version_reg[15:0]};
`ETX_CFG: cfg_dout[31:0] <= {16'b0, tx_cfg_reg[15:0]};
`ETX_GPIO: cfg_dout[31:0] <= {23'b0, tx_gpio_reg[8:0]};
`ETX_STATUS: cfg_dout[31:0] <= {16'b0, tx_status_reg[15:0]};
`ETX_MONITOR: cfg_dout[31:0] <= {tx_monitor_reg[31:0]};
`ETX_PACKET: cfg_dout[31:0] <= {tx_packet_reg[31:0]};
default: cfg_dout[31:0] <= 32'd0;
endcase // case (dstaddr_in[RFAW+1:2])
else
cfg_dout[31:0] <= 32'd0;
//###########################
//# FORWARD PACKET TO RX
//###########################
//pipeline
always @ (posedge clk)
if(~etx_wait)
begin
etx_cfg_access <= cfg_access;
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[4:0] <= {1'b0,ctrlmode_in[3:0]};
write_out <= ecfg_read | write_in;
dstaddr_out[31:0] <= ecfg_read ? srcaddr_in[31:0] : dstaddr_in[31:0];
data_out[31:0] <= data_in[31:0];
srcaddr_out[31:0] <= srcaddr_in[31:0];
read_sel <= ecfg_read;
end
assign data_mux[31:0] = read_sel ? cfg_dout[31:0] :
data_out[31:0];
//Create packet
emesh2packet #(.AW(AW))
e2p (.packet_out (etx_cfg_packet[PW-1:0]),
.data_out (data_mux[AW-1:0]),
/*AUTOINST*/
// Inputs
.write_out (write_out),
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
endmodule // ecfg_tx
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
#include<bits/stdc++.h> using namespace std; /* User Template @Shaurya Gautam CP.cpp */ /*****************************************/ #define ll long long #define vb vector<bool> #define vi vector<int> #define vl vector<long> #define vll vector<long long> #define vpii vector<pair<int, int>> #define vc vector<char> #define pii pair<int, int> #define mp make_pair #define F(i,L,R) for (int i = L; i < R; i++) #define FE(i,L,R) for (int i = L; i <= R; i++) #define FR(i,L,R) for (int i = L; i > R; i--) #define FRE(i,L,R) for (int i = L; i >= R; i--) #define pb push_back #define ppb pop_back #define endl n class my_compare{ public: bool operator()(pii &p1, pii &p2){ return p1.second < p2.second; } }; /*************************************************/ void solve(){ int n; cin >> n; vi arr(n + 1); FE(i, 1, n){ cin >> arr[i]; } int ans{0}; FE(i, 1, n){ if(arr[i] > 2*i - 1) continue; int j = (arr[i] > i) ? 1 : (i/arr[i]) + 1; while(j*arr[i] <= 2*i - 1){ if(arr[j*arr[i] - i] == j) ans++; j++; } } cout << ans << endl; } int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); bool test_case{1}, fileop{0}; if(fileop){ freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); } int t; if(test_case){ cin >> t; F(i, 0, t){ solve(); } } else solve(); } /* Some Learnings- -Don t focus on ratings or standings -See problem from new perspective and forget current thoughts -Accuracy is important, be sure that you think right -Speed builds up once accuracy does... solve as many questions as possible -Editorial is last resort... don t jump to it -BE CONSISTENT -My two brothers - Hard Work and Perseverance -Never leave a contest, no matter how tough it might be */
|
#include <bits/stdc++.h> using namespace std; int const nmax = 100000; int const domain = 1000000; struct Person { int x; int v; bool operator<(Person other) const { return (x < other.x); } }; int n, nl, nr; int s; Person pl[1 + nmax], pr[1 + nmax]; bitset<1 + domain> okl, okr; double timetodest(int distp, int vp, int distray) { double timep = 1.0L * distp / vp; double timehit = 1.0L * (distray - distp) / (s - vp); if (timep <= timehit) return timep; else { double disthit = distp - timehit * vp; return timehit + (disthit / (vp + s)); } } void checktime(double target, Person *p, int np, bitset<1 + domain> *ok) { for (int i = 1; i <= np; i++) { if (p[i].x <= p[i].v * target) { for (int j = 1; j < domain; j++) (*ok)[j] = 1; return; } } int i = 1; for (int j = 1; j < domain; j++) { bool flag = false; while (flag == false && i <= np && p[i].x <= j) { if (timetodest(p[i].x, p[i].v, j) <= target) flag = true; else i++; } (*ok)[j] = flag; } } int main() { cin >> n >> s; for (int i = 0; i < n; i++) { int x, v, dir; cin >> x >> v >> dir; if (dir == 1) { nl++; pl[nl] = {x, v}; } else { nr++; pr[nr] = {domain - x, v}; } } sort(pl + 1, pl + nl + 1); sort(pr + 1, pr + nr + 1); double t1 = 0, t2 = domain, tmid; double deltat = 1; double stop = 0.0000000001L; while (stop < deltat) { tmid = (t1 + t2) / 2; deltat = (tmid - t1) / 2; checktime(tmid, pl, nl, &okl); checktime(tmid, pr, nr, &okr); int flag = 0, j = 1; while (flag == 0 && j < domain) { if (okl[j] == 1 && okr[domain - j] == 1) flag = 1; j++; } if (flag == 1) t2 = tmid; else t1 = tmid; } cout << fixed << setprecision(12) << tmid << n ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 17:41:40 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_color_test_0_0 -prefix
// system_vga_color_test_0_0_ system_vga_color_test_0_0_stub.v
// Design : system_vga_color_test_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_color_test,Vivado 2016.4" *)
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output [5:0] data_out
);
wire [5:0] data_out;
wire builder_pll_fb;
wire fdce_0_out, fdce_1_out;
wire main_locked;
FDCE FDCE_0 (
.D (data_in),
.C (clk),
.CE (1'b1),
.CLR(1'b0),
.Q (fdce_0_out)
);
FDCE FDCE_1 (
.D (fdce_0_out),
.C (clk),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[0])
);
PLLE2_ADV #(
.CLKFBOUT_MULT(4'd12),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(9.99999),
.CLKOUT0_DIVIDE(4'd12),
.CLKOUT0_PHASE(90.0),
.CLKOUT1_DIVIDE(3'd6),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(2'd3),
.CLKOUT2_PHASE(90.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout_x1),
.CLKOUT1(main_clkout_x2),
.CLKOUT2(main_clkout_x4),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH90 (
.D (data_in),
.C (main_clkout_x1),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[1])
);
FDCE FDCE_PLLx4_PH0_0 (
.D (data_in),
.C (main_clkout_x2),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[2])
);
FDCE FDCE_PLLx4_PH0_1 (
.D (data_in),
.C (main_clkout_x2),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[3])
);
FDCE FDCE_PLLx4_PH0_2 (
.D (data_in),
.C (main_clkout_x2),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[4])
);
FDCE FDCE_PLLx2_PH90_0 (
.D (data_in),
.C (main_clkout_x4),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out[5])
);
endmodule
|
`timescale 1ns / 1ps
module test;
reg rst, clk;
wire wr_n, cen_fm, cen_fm2;
wire a0;
wire [7:0] din, dout;
initial begin
rst = 1'b0;
#300 rst=1'b1;
#3000 rst=1'b0;
end
initial begin
clk = 1'b0;
forever #10.417 clk=~clk; // 48MHz
end
jtframe_cen3p57 u_cen(
.clk ( clk ), // 48 MHz
.cen_3p57 ( cen_fm ),
.cen_1p78 ( cen_fm2 )
);
wire signed [15:0] left;
wire signed [15:0] right;
wire sample, ct1, ct2, irq_n;
jt51 uut(
.rst ( rst ), // reset
.clk ( clk ), // main clock
.cen ( cen_fm ), // clock enable
.cen_p1 ( cen_fm2 ), // clock enable at half the speed
.cs_n ( 1'b0 ), // chip select
.wr_n ( wr_n ), // write
.a0 ( a0 ),
.din ( din ), // data in
.dout ( dout ), // data out
// peripheral control
.ct1 ( ct1 ),
.ct2 ( ct2 ),
.irq_n ( irq_n ), // I do not synchronize this signal
// Low resolution output (same as real chip)
.sample ( sample ), // marks new output sample
.left ( left ),
.right ( right ),
// Full resolution output
.xleft ( ),
.xright ( ),
// unsigned outputs for sigma delta converters, full resolution
.dacleft ( ),
.dacright ( )
);
time_commands u_cmd(
.rst ( rst ),
.clk ( clk ),
.wr_n ( wr_n ),
.a0 ( a0 ),
.din ( din )
);
`ifdef DUMP
initial begin
`ifdef NCVERILOG
$shm_open("test.shm");
//$shm_probe(test,"AS");
$shm_probe(test.uut.u_mmr,"AS");
$shm_probe(test.uut.u_timers,"AS");
`else
$dumpfile("test.lxt");
//$dumpvars(0,test);
$dumpvars(1,test);
$dumpvars(1,test.uut);
$dumpvars(0,test.u_cmd);
$dumpvars(0,test.uut.u_mmr);
$dumpvars(0,test.uut.u_timers);
$dumpon;
`endif
end
`endif
endmodule
//////////////////////////////////////////////////////////7
// Possible stimulus controllers
/////////////////////////////////////////////
// Read a file with the following format
// clock ticks,a0 value, din value
//
// This file is dumped by JT51 during regular simulation
// The tick values are offset so there is no need for
// a long wait of the first tick count as the file is likely
// to start off with a very large value
module time_commands(
input rst,
input clk,
output reg wr_n,
output reg a0,
output reg [7:0] din
);
integer next_tick, next_a0, next_din;
integer ticks;
integer file, check;
initial begin
file=$fopen("test_cmd.txt","r");
if( file==0 ) begin
$display("Cannot open test_cmd.txt");
$finish;
end
next_tick=-1;
//check=$fscanf(file,"%d,%d,%x"\n, next_tick, next_a0, next_din );
//ticks = next_tick-10;
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
if( next_tick==-1) check <=$fscanf(file,"%d,%d,%x\n", next_tick, next_a0, next_din );
ticks <= next_tick-10;
end else begin
ticks <= ticks+1;
wr_n <= 1'b1;
if( ticks==next_tick ) begin
din <= next_din;
a0 <= next_a0;
wr_n <= 1'b0;
check=$fscanf(file,"%d,%d,%x\n", next_tick, next_a0, next_din );
if($feof(file)) begin
#100 $finish;
end
end
end
end
endmodule
/////////////////////////////////////////////
// Read hex file with commands
module hex_commands(
input rst,
input clk,
output reg wr_n,
output a0,
output reg [7:0] din
);
// simulation control
reg [7:0] cmd[0:4096];
integer cnt, waitcnt;
assign a0 = ~cnt[0];
wire busy = dout[7];
initial begin
$readmemh( "cmd.hex", cmd);
end
always @(posedge clk, posedge rst) begin
if( rst ) begin
din <= 8'd0;
wr_n <= 1'b1;
cnt <= 0;
waitcnt <= 0;
end else begin
wr_n <= 1'b1;
if(!busy ) begin
waitcnt <= waitcnt-1;
if(waitcnt==0) begin
$display("%d, %h, %d", a0, cmd[cnt], waitcnt);
if( cnt[0]==1'b0 && (cmd[cnt]==0 || cmd[cnt]==1) ) begin
if( cmd[cnt]==0) begin
$finish;
end else begin
cnt<=cnt+4; // wait
waitcnt<={cmd[cnt+1],~11'h0};
end
end
else begin
din <= cmd[cnt];
cnt <= cnt+1;
wr_n <= 1'b0;
waitcnt <= 1;
end
end
end
end
end
endmodule
module jtframe_cen3p57(
input clk, // 48 MHz
output reg cen_3p57,
output reg cen_1p78
);
wire [10:0] step=11'd105;
wire [10:0] lim =11'd1408;
wire [10:0] absmax = lim+step;
reg [10:0] cencnt=11'd0;
reg [10:0] next;
reg [10:0] next2;
always @(*) begin
next = cencnt+11'd105;
next2 = next-lim;
end
reg alt=1'b0;
always @(posedge clk) begin
cen_3p57 <= 1'b0;
cen_1p78 <= 1'b0;
if( cencnt >= absmax ) begin
// something went wrong: restart
cencnt <= 11'd0;
alt <= 1'b0;
end else
if( next >= lim ) begin
cencnt <= next2;
cen_3p57 <= 1'b1;
alt <= ~alt;
if( alt ) cen_1p78 <= 1'b1;
end else begin
cencnt <= next;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int lins, cols; cin >> lins >> cols; for (int i(0); i < lins; i++) { if (i % 2 == 0) { for (int j(0); j < cols; j++) { cout << # ; } cout << endl; } else if ((i + 1) % 4 == 0) { cout << # ; for (int j(0); j < cols - 1; j++) { cout << . ; } cout << endl; } else { for (int j(0); j < cols - 1; j++) { cout << . ; } cout << # ; cout << endl; } } return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module niosII_system_sram_0 (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
readdata,
readdatavalid,
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// Bi-Directional
inout [15: 0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [17: 0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & (read | write));
SRAM_UB_N <= ~(byteenable[1] & (read | write));
SRAM_CE_N <= ~(read | write);
SRAM_OE_N <= ~read;
SRAM_WE_N <= ~write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign SRAM_DQ = (is_write) ? writedata_reg : 16'hzzzz;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[81][81][81][81]; vector<pair<int, int>> graph[81]; int solve(int v, int l, int r, int k) { if (k == 0) return 0; if (dp[v][l][r][k] != -1) return dp[v][l][r][k]; int &ret = dp[v][l][r][k]; ret = 1000000; for (auto e : graph[v]) { int w = e.second; int u = e.first; if (u < r && u > v) { ret = min(ret, solve(u, v, r, k - 1) + w); } if (u > l && u < v) { ret = min(ret, solve(u, l, v, k - 1) + w); } } return ret; } int main() { int n, k; scanf( %d %d , &n, &k); int m; scanf( %d , &m); for (int i = 0; i < m; i++) { int a, b, c; scanf( %d %d %d , &a, &b, &c); graph[a].push_back({b, c}); } int ans = 1000000; memset(dp, -1, sizeof dp); for (int i = 1; i <= n; i++) { ans = min(ans, solve(i, 0, n + 1, k - 1)); } printf( %d n , ans >= 1000000 ? -1 : ans); return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:05:03 06/28/2015
// Design Name:
// Module Name: nmievents
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module nmievents (
input wire clk,
input wire rst_n,
//------------------------------
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
//------------------------------
input wire [4:0] userevents,
//------------------------------
input wire [15:0] a,
input wire m1_n,
input wire mreq_n,
input wire rd_n,
output wire [7:0] dout,
output wire oe_n,
output reg nmiout_n,
output reg page_configrom_active
);
parameter NMIEVENT = 8'h08;
parameter IDLE = 1'd0,
ABOUT_TO_EXIT = 1'd1;
initial page_configrom_active = 1'b0;
initial nmiout_n = 1'b1;
reg state = IDLE;
reg [7:0] nmieventreg = 8'h00;
assign dout = nmieventreg;
assign oe_n = ~(zxuno_addr == NMIEVENT && zxuno_regrd == 1'b1);
always @(posedge clk) begin
if (rst_n == 1'b0) begin
nmieventreg <= 8'h00;
page_configrom_active <= 1'b0;
state <= IDLE;
end
else begin
if (userevents != 5'b00000 && page_configrom_active == 1'b0) begin
nmieventreg <= {3'b000, userevents};
nmiout_n <= 1'b0;
page_configrom_active <= 1'b1;
state <= IDLE;
end
if (mreq_n == 1'b0 && m1_n == 1'b0 && a == 16'h0066 && page_configrom_active == 1'b1) // ya estamos en NMI
nmiout_n <= 1'b1; // asi que desactivo la señal
case (state)
IDLE:
begin
if (mreq_n == 1'b0 && m1_n == 1'b0 && rd_n == 1'b0 && a==16'h006A && page_configrom_active == 1'b1)
state <= ABOUT_TO_EXIT;
end
ABOUT_TO_EXIT:
begin
if (m1_n == 1'b1) begin
page_configrom_active <= 1'b0;
nmieventreg <= 8'h00;
state <= IDLE;
end
end
default: state <= IDLE;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int size = 1000007; const long long modulo = 1000000007; const long long INF = 1e9; const double EPS = 1e-10; int main() { cin.sync_with_stdio(0); int n, m, k; cin >> n >> m >> k; int ans = 0; for (int i = 0; i < n; i++) { int a; cin >> a; if (a == 1) { if (m > 0) --m; else ++ans; } else { if (k > 0) --k; else if (m > 0) --m; else ++ans; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int z[2 * 1000 * 1000 + 10]; char s[2 * 1000 * 1000 + 10]; bool T[2 * 1000 * 1000 + 10]; int cnt[2 * 1000 * 1000 + 10]; int main() { int K, L; scanf( %d%d , &L, &K); scanf( %s , &s); for (int i = 1, l = 0, r = 0; i < L; ++i) { if (i <= r) z[i] = min(r - i + 1, z[i - l]); while (i + z[i] < L && s[z[i]] == s[i + z[i]]) ++z[i]; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; } int k, m; for (int i = 1; i < L; i++) { k = z[i] / i + 1; m = z[i] % (i); if (k == K) { T[i * K - 1] = true; cnt[i * K - 1] = max(cnt[i * K - 1], m); } if (k > K) { T[i * K - 1] = true; cnt[i * K - 1] = max(cnt[i * K - 1], i); } if (k >= K + 1) T[i * (K + 1) - 1] = true; } for (int i = 0; i < L; i++) { if (K == 1) T[i] = true; if (cnt[i]) { T[i + 1] = true; cnt[i + 1] = max(cnt[i + 1], cnt[i] - 1); } printf( %d , T[i]); } printf( n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A31O_FUNCTIONAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using uiII = unsigned int long long; using II = int long long; using namespace std; const II N = 0x3f3f3f3f3f3f3f; int main() { vector<pair<II, II>> v; vector<pair<II, II>>::iterator it; v.reserve(1000000); II t, n, l, r, i(0); for (cin >> t; i < t; i++) { cin >> n; v.push_back(make_pair(1, n)); bool x[2000][2000]{false}; for (II i = 0; i < n; i++) { cin >> l >> r; x[l][r] = true; } bool f = false; for (II i = 0; i < v.size(); i++) { for (II j = v[i].first; j <= v[i].second; j++) { if (v[i].first == v[i].second) { cout << v[i].first << << v[i].second << << v[i].first << endl; } if (j - v[i].first == 0) { if (v[i].second - v[i].first >= 2) { if (x[j + 1][v[i].second] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(j + 1, v[i].second)); } continue; } if (v[i].second - v[i].first == 1) { if (x[v[i].second][v[i].second] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(v[i].second, v[i].second)); } continue; } } if (j - v[i].second == 0) { if (j - v[i].first >= 2) { if (x[v[i].first][v[i].second - 1] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(v[i].first, v[i].second - 1)); } continue; } if (j - v[i].first == 1) { if (x[v[i].first][v[i].first] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(v[i].first, v[i].first)); } continue; } } if (j != v[i].first && j != v[i].second) { if (j - v[i].first == 1) { if (x[v[i].first][v[i].first] == true) { if (x[j + 1][v[i].second] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(v[i].first, v[i].first)); v.push_back(make_pair(j + 1, v[i].second)); break; } } continue; } if (v[i].second - j == 1) { if (x[v[i].first][j - 1] == true) { if (x[v[i].second][v[i].second] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(v[i].second, v[i].second)); v.push_back(make_pair(v[i].first, j - 1)); break; } } continue; } else { if (x[v[i].first][j - 1] == true) { if (x[j + 1][v[i].second] == true) { cout << v[i].first << << v[i].second << << j << endl; v.push_back(make_pair(v[i].first, j - 1)); v.push_back(make_pair(j + 1, v[i].second)); break; } } continue; } } } } v.clear(); } }
|
#include <bits/stdc++.h> using namespace std; long long dx[] = {1, 0, -1, 0}; long long dy[] = {0, 1, 0, -1}; long long gcd(long long x, long long y) { if (y == 0) return x; else return gcd(y, x % y); } long long expo(long long n, long long m, long long p) { long long r = 1; n = n % p; while (m > 0) { if (m % 2) r = (r * n) % p; n = (n * n) % p; m = m / 2; } return r % p; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; map<double, long long> p; vector<string> v(n); for (long long j = 0; j < n; j++) { string s; cin >> s; v[j] = s; long long a = 0, b = 0, c = 0; long long i = 1; while (s[i] != + ) { a = a * 10 + s[i] - 0 ; i++; } i++; while (s[i] != ) ) { b = b * 10 + s[i] - 0 ; i++; } i++; i++; while (i != s.size()) { c = c * 10 + s[i] - 0 ; i++; } double aa = (a * 1.0 + b) / c; p[aa]++; } for (long long j = 0; j < n; j++) { string s = v[j]; long long a = 0, b = 0, c = 0; long long i = 1; while (s[i] != + ) { a = a * 10 + s[i] - 0 ; i++; } i++; while (s[i] != ) ) { b = b * 10 + s[i] - 0 ; i++; } i++; i++; while (i != s.size()) { c = c * 10 + s[i] - 0 ; i++; } double aa = (a * 1.0 + b) / c; cout << p[aa] << ; } cout << n ; }
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`timescale 1ns / 1ps
module forwarding_unit (
input ex_mem_reg_write,
input mem_wb_reg_write,
input [4:0] ex_mem_dst_reg,
input [4:0] mem_wb_dst_reg,
input [4:0] id_ex_rs,
input [4:0] id_ex_rt,
input [4:0] if_id_rs,
input [4:0] if_id_rt,
output [1:0] if_rs_forward_control,
output [1:0] id_rt_forward_control,
output [1:0] ex_rs_forward_control,
output [1:0] ex_rt_forward_control );
//tmp signals
wire [3:0] id_fwd_ctrl, ex_fwd_ctrl;
// encoding for muxes control signals
// general for both forwarding muxes
// 2'b01 - from EX_MEM pipe reg
// 2'b10 - from MEM_WB pipe reg
// 2'b00 - no forwarding
assign if_rs_forward_control = id_fwd_ctrl[0] ? 2'b01 : id_fwd_ctrl[2] ? 2'b10 : 2'b00;
assign id_rt_forward_control = id_fwd_ctrl[1] ? 2'b01 : id_fwd_ctrl[3] ? 2'b10 : 2'b00;
assign ex_rs_forward_control = ex_fwd_ctrl[0] ? 2'b01 : ex_fwd_ctrl[2] ? 2'b10 : 2'b00;
assign ex_rt_forward_control = ex_fwd_ctrl[1] ? 2'b01 : ex_fwd_ctrl[3] ? 2'b10 : 2'b00;
base_forwarding_unit ex_forwarding_inst(
.ex_mem_reg_write(ex_mem_reg_write),
.mem_wb_reg_write(mem_wb_reg_write),
.ex_mem_dst_reg(ex_mem_dst_reg),
.mem_wb_dst_reg(mem_wb_dst_reg),
.rs(id_ex_rs),
.rt(id_ex_rt),
.forward_control(ex_fwd_ctrl));
base_forwarding_unit id_forwarding_inst(
.ex_mem_reg_write(ex_mem_reg_write),
.mem_wb_reg_write(mem_wb_reg_write),
.ex_mem_dst_reg(ex_mem_dst_reg),
.mem_wb_dst_reg(mem_wb_dst_reg),
.rs(if_id_rs),
.rt(if_id_rt),
.forward_control(id_fwd_ctrl));
endmodule
/* Generic base logic module to implement forwarding
*
* Description of forward_control signal:
* 0000 - no forwarding
* 0001 - forwarding value from EX_MEM for replace rs value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rs]
* 0010 - forwarding value from EX_MEM for replace rt value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rt]
* 0100 - forwarding value from WB for replace rs value on destination stage.
* WB[Value] -> PIPE_STAGE[rs]
* 1000 - forwarding value from WB for replace rt value on destination stage.
* WB[Value] -> PIPE_STAGE[rt]
* 0011 - forwarding value from EX_MEM for replace rs and rt value on destination stage
* EX_MEM[Value] -> PIPE_STAGE[rs]; EX_MEM[Value] -> PIPE_STAGE[rt]
* 1100 - forwarding value from WB for replace Rs and Rt value on destination stage
* WB[Value] -> PIPE_STAGE[rs]; WB[Value] -> PIPE_STAGE[rt]
* 0110 - forwarding value from EX_MEM for replace rt value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rt]
* forwarding value from WB for replace rs value on destination stage.
* WB[Value] -> PIPE_STAGE[rs]
* 1001 - forwarding value from EX_MEM for replace rs value on destination stage.
* EX_MEM[Value] -> PIPE_STAGE[rs]
* forwarding value from WB for replace rt value on destination stage.
* WB[Value] -> PIPE_STAGE[rt]
*/
module base_forwarding_unit ( input ex_mem_reg_write,
input mem_wb_reg_write,
input [4:0] ex_mem_dst_reg,
input [4:0] mem_wb_dst_reg,
input [4:0] rs,
input [4:0] rt,
output reg [3:0] forward_control);
//service signals
reg ex_mem_dst_reg_is_not_zero;
reg mem_wb_dst_reg_is_not_zero;
always @* begin
ex_mem_dst_reg_is_not_zero = |ex_mem_dst_reg;
mem_wb_dst_reg_is_not_zero = |mem_wb_dst_reg;
forward_control = 4'h0;
if (ex_mem_reg_write & ex_mem_dst_reg_is_not_zero) begin
if (ex_mem_dst_reg == rs)
forward_control[0] = 1'b1;
else
forward_control[0] = 1'b0;
if (ex_mem_dst_reg == rt)
forward_control[1] = 1'b1;
else
forward_control[1] = 1'b0;
end
else
forward_control[1:0] = 2'b00;
if (mem_wb_reg_write & mem_wb_dst_reg_is_not_zero) begin
if ((mem_wb_dst_reg == rs) & (ex_mem_dst_reg != rs))
forward_control[2] = 1'b1;
else
forward_control[2] = 1'b0;
if ((mem_wb_dst_reg == rt) & (ex_mem_dst_reg != rt))
forward_control[3] = 1'b1;
else
forward_control[3] = 1'b0;
end
else
forward_control[3:2] = 2'b00;
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_1_V
`define SKY130_FD_SC_HD__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_1_V
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#include <bits/stdc++.h> using namespace std; int main() { int num; int a = 0; int b = 0; int n; cin >> n; int sol[n]; for (a = 0; a < n; a++) { cin >> num; sol[num - 1] = (a + 1); } for (b = 0; b < n; b++) { cout << sol[b] << ; } return 0; }
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Coprocessor 0. Exceptions and Interrupts Unit.
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Coprocessor 0 EIU */
module uparc_coproc0_eiu(
clk,
nrst,
/* External interrupt */
i_intr,
/* CU signals */
i_exec_stall,
i_mem_stall,
i_fetch_stall,
o_wait_stall,
i_jump_valid,
/* COP0 signals */
i_cop0_ivtbase,
i_cop0_ie,
i_cop0_intr_wait,
/* Exception signals */
o_except_start,
o_except_dly_slt,
o_except_valid,
o_except_haddr,
/* Error signals from stages */
i_bus_error_p0,
i_addr_error_p0,
i_decode_error_p1,
i_overfl_error_p2,
i_addr_error_p2,
i_syscall_trap_p2,
i_break_trap_p2,
i_bus_error_p3,
i_addr_error_p3,
/* Result nullify signals */
o_nullify_fetch,
o_nullify_decode,
o_nullify_execute,
o_nullify_mem,
o_nullify_wb
);
/* Exceptions */
localparam [2:0] EX_NONE = 3'b000;
localparam [2:0] EX_BUSERR = 3'b001;
localparam [2:0] EX_OVERFL = 3'b010;
localparam [2:0] EX_ADDRERR = 3'b011;
localparam [2:0] EX_RESVDI = 3'b100;
localparam [2:0] EX_BREAK = 3'b101;
localparam [2:0] EX_SYSCALL = 3'b110;
localparam [2:0] EX_HWINTR = 3'b111;
/* Inputs */
input wire clk;
input wire nrst;
/* External interrupt */
input wire i_intr;
/* CU signals */
input wire i_exec_stall;
input wire i_mem_stall;
input wire i_fetch_stall;
output wire o_wait_stall;
input wire i_jump_valid;
/* COP0 signals */
input wire [`UPARC_ADDR_WIDTH-11:0] i_cop0_ivtbase;
input wire i_cop0_ie;
input wire i_cop0_intr_wait;
/* Exception signals */
output wire o_except_start;
output wire o_except_dly_slt;
output reg o_except_valid;
output reg [`UPARC_ADDR_WIDTH-1:0] o_except_haddr;
/* Error signals from stages */
input wire i_bus_error_p0;
input wire i_addr_error_p0;
input wire i_decode_error_p1;
input wire i_overfl_error_p2;
input wire i_addr_error_p2;
input wire i_syscall_trap_p2;
input wire i_break_trap_p2;
input wire i_bus_error_p3;
input wire i_addr_error_p3;
/* Result nullify signals */
output wire o_nullify_fetch;
output wire o_nullify_decode;
output wire o_nullify_execute;
output wire o_nullify_mem;
output wire o_nullify_wb;
wire core_stall = i_exec_stall || i_mem_stall || i_fetch_stall || o_wait_stall;
assign o_nullify_fetch = ex_state_p0 || ex_state_p1 || ex_state_p2 || ex_state_p3;
assign o_nullify_decode = ex_state_p0 || ex_state_p1 || ex_state_p2 || ex_state_p3;
assign o_nullify_execute = ex_state_p1 || ex_state_p2 || ex_state_p3;
assign o_nullify_mem = ex_state_p2 || ex_state_p3;
assign o_nullify_wb = ex_state_p3;
assign o_except_start = ex_state_p3;
assign o_except_dly_slt = dly_p3;
/* External interrupt registered flag */
wire intr_reg = intr_reg_p3 | intr_reg_p4;
/* Exception state at stages */
wire ex_state_p0 = i_bus_error_p0 || i_addr_error_p0;
wire ex_state_p1 = |ex_p1 || i_decode_error_p1;
wire ex_state_p2 = |ex_p2 || i_overfl_error_p2 || i_addr_error_p2 ||
i_syscall_trap_p2 || i_break_trap_p2 ||
(intr_valid && !bubble_p2 && !intr_reg);
wire ex_state_p3 = |ex_p3 || i_bus_error_p3 || i_addr_error_p3;
/******************************* DECODE STAGE *********************************/
reg [2:0] ex_p1;
reg bubble_p1;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
ex_p1 <= EX_NONE;
bubble_p1 <= 1'b0;
end
else if(!core_stall)
begin
if(i_bus_error_p0)
ex_p1 <= EX_BUSERR;
else if(i_addr_error_p0)
ex_p1 <= EX_ADDRERR;
else
ex_p1 <= EX_NONE;
/* Mark bubble instructions (nullified instructions) */
bubble_p1 <= (o_nullify_fetch || i_jump_valid || o_except_valid) ? 1'b1 : 1'b0;
end
end
/****************************** EXECUTE STAGE *********************************/
reg [2:0] ex_p2;
reg dly_p2;
reg bubble_p2;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
ex_p2 <= EX_NONE;
dly_p2 <= 1'b0;
bubble_p2 <= 1'b0;
end
else if(!core_stall)
begin
if(i_decode_error_p1)
ex_p2 <= EX_RESVDI;
else
ex_p2 <= ex_p1;
dly_p2 <= i_jump_valid;
bubble_p2 <= bubble_p1;
end
end
/******************************* MEMORY STAGE *********************************/
reg [2:0] ex_p3;
reg dly_p3;
reg intr_reg_p3;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
ex_p3 <= EX_NONE;
dly_p3 <= 1'b0;
intr_reg_p3 <= 1'b0;
end
else if(!core_stall)
begin
if(intr_valid && !bubble_p2 && !intr_reg)
begin
ex_p3 <= EX_HWINTR;
intr_reg_p3 <= 1'b1;
end
else if(i_overfl_error_p2)
ex_p3 <= EX_OVERFL;
else if(i_addr_error_p2)
ex_p3 <= EX_ADDRERR;
else if(i_syscall_trap_p2)
ex_p3 <= EX_SYSCALL;
else if(i_break_trap_p2)
ex_p3 <= EX_BREAK;
else
begin
ex_p3 <= ex_p2;
intr_reg_p3 <= 1'b0;
end
dly_p3 <= dly_p2;
end
end
/***************************** WRITEBACK STAGE ********************************/
reg intr_reg_p4;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_except_valid <= 1'b0;
o_except_haddr <= {(`UPARC_ADDR_WIDTH){1'b0}};
intr_reg_p4 <= 1'b0;
end
else if(!core_stall)
begin
intr_reg_p4 <= intr_reg_p3;
if(i_bus_error_p3)
begin
o_except_valid <= 1'b1;
o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_BUSERR };
end
else if(i_addr_error_p3)
begin
o_except_valid <= 1'b1;
o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_ADDRERR };
end
else if(|ex_p3)
begin
o_except_valid <= 1'b1;
case(ex_p3)
EX_BUSERR: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_BUSERR };
EX_OVERFL: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_OVERFL };
EX_ADDRERR: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_ADDRERR };
EX_RESVDI: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_RESVDI };
EX_BREAK: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_BREAK };
EX_SYSCALL: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_SYSCALL };
EX_HWINTR: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_HWINTR };
default: o_except_haddr <= { i_cop0_ivtbase, `UPARC_EXVECT_RESET };
endcase
end
else
begin
o_except_valid <= 1'b0;
end
end
end
/************************* EXTERNAL INTERRUPT CAPTURE *************************/
reg intr_valid;
reg intr_latch;
/* Interrupt wait stall condition */
assign o_wait_stall = i_cop0_intr_wait && !intr_latch && !intr_valid && !intr_reg;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
intr_valid <= 1'b0;
intr_latch <= 1'b0;
end
else if(!core_stall)
begin
intr_valid <= (intr_latch | ((i_intr && i_cop0_ie && !intr_valid) ? 1'b1 : 1'b0)) &
~intr_reg;
intr_latch <= 1'b0;
end
else
intr_latch <= intr_latch | ((i_intr && i_cop0_ie && !intr_valid) ? 1'b1 : 1'b0);
end
endmodule /* uparc_coproc0_eiu */
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#include <bits/stdc++.h> using namespace std; int n, l[200000 + 5], r[200000 + 5]; int p[200000 + 5], q[200000 + 5], sum; long long add(long long a, long long b) { return (a + b) % 1000000007; } long long mul(long long a, long long b) { return 1LL * a * b % 1000000007; } long long dec(long long a, long long b) { return (a - b + 1000000007) % 1000000007; } int fst_pow(int a, int b) { int res = 1; while (b) { if (b & 1) res = mul(res, a); a = mul(a, a); b >>= 1; } return res; } int val(int i) { int ans = 1; ans = dec(ans, p[i]), ans = dec(ans, p[i + 1]); int L = max(l[i - 1], max(l[i], l[i + 1])), R = min(r[i - 1], min(r[i], r[i + 1])); if (L < R) ans = add(ans, mul(R - L, fst_pow(mul(mul(r[i] - l[i], r[i - 1] - l[i - 1]), r[i + 1] - l[i + 1]), 1000000007 - 2))); return ans; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &l[i]); for (int i = 1; i <= n; i++) { scanf( %d , &r[i]); r[i]++; } int sum = 0; for (int i = 1; i <= n; i++) { int L = max(l[i], l[i - 1]), R = min(r[i], r[i - 1]); if (L < R) p[i] = mul(R - L, fst_pow(mul(r[i] - l[i], r[i - 1] - l[i - 1]), 1000000007 - 2)); q[i] = dec(1, p[i]); sum = add(sum, q[i]); } int ans = 0; for (int i = 1; i <= n; i++) { ans = add(ans, q[i]); int ps = dec(sum, q[i]); if (i > 2) ans = add(ans, val(i - 1)), ps = dec(ps, q[i - 1]); if (i < n) ans = add(ans, val(i)), ps = dec(ps, q[i + 1]); ans = add(ans, mul(q[i], ps)); } printf( %d , ans); }
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#include <bits/stdc++.h> using namespace std; struct my { int num; int dmg; } dmg[10010]; int mx, reg, rg[10010], n; int flag[10010]; vector<pair<int, int> > v; bool operator<(my a, my b) { if (a.dmg > b.dmg) return 1; return 0; } int main() { cin >> n >> mx >> reg; for (int i = 0; i < n; i++) { cin >> rg[i] >> dmg[i].dmg; dmg[i].num = i; } int time = 0, inds, kols = 0, fl = 0; int total_dmg = 0, cur = mx; sort(dmg, dmg + n); while (1) { cur += (reg - total_dmg); if (cur > mx) cur = mx; if (cur <= 0) { cout << YES n ; cout << time << << kols << n ; for (int i = 0; i < (int)v.size(); i++) cout << v[i].first << << v[i].second << n ; return 0; } inds = -1; for (int i = 0; i < n; i++) { if (!flag[i]) { if (cur * 100 <= rg[dmg[i].num] * mx) { inds = i; break; } } } if (inds != -1) { total_dmg += dmg[inds].dmg; flag[inds] = 1; kols++; v.push_back(make_pair(time, dmg[inds].num + 1)); } else { if (reg >= total_dmg) { cout << NO n ; return 0; } } time++; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, k, s, bigx[11], bigy[11], smlx[11], smly[11]; int main() { scanf( %d%d%d%d , &n, &m, &k, &s); for (int i = 1; i <= k; i++) bigx[i] = bigy[i] = -2020, smlx[i] = smly[i] = 2 * 2020; for (int i = 0; i < (n); i++) for (int j = 0; j < (m); j++) { int t; scanf( %d , &t); bigx[t] = max(bigx[t], i + j); bigy[t] = max(bigy[t], i - j); smlx[t] = min(smlx[t], i + j); smly[t] = min(smly[t], i - j); } int a, b, ans = -1; scanf( %d , &a); for (int i = 1; i < s; i++) { scanf( %d , &b); ans = max(ans, max(abs(bigx[a] - smlx[b]), abs(bigx[b] - smlx[a]))); ans = max(ans, max(abs(bigy[a] - smly[b]), abs(bigy[b] - smly[a]))); a = b; } printf( %d n , ans); return 0; }
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#include <cassert> #include <climits> #include <cstdio> #include <cstdlib> #include <cstring> #include <cmath> #include <cctype> #include <vector> #include <string> #include <queue> #include <deque> #include <stack> #include <set> #include <map> #include <utility> #include <algorithm> #include <iostream> #include <sstream> #include <numeric> using namespace std; #define SIZE(x) int((x).size()) #define REP(i,c) for(auto &i : c) #define pb push_back #define eb emplace_back typedef long long i64; typedef unsigned long long u64; const double EPS = 1e-12; const int INF = 999999999; typedef vector<int> VI; typedef vector<string> VS; typedef pair<int,int> PII; typedef vector<PII> VPII; const int MAXN=1500; int n,m; int a[MAXN][MAXN]; int f[MAXN][MAXN]; VPII row[MAXN]; // colors in a[i][j .. n] VPII col[2][MAXN]; // colors in a[i..n][j] // colors in square (i,j) ... (i+f[i]][j]-1, j+f[i][j-1]), order max(x-i,y-i) VPII sq[2][MAXN]; int cur; bool seen[MAXN*MAXN+1]; struct Fenwick { int n; VI f; Fenwick(int n) : n(n) { f=VI(n+1,0); } inline int LowBit(int x) { return x&(-x); } void Update(int i,int x) { while(i>0) { f[i]+=x; i-=LowBit(i); } } int Get(int i) { int r=0; while(i<=n) { r+=f[i]; i+=LowBit(i); } return r; } }; void Dbg(const VPII& v) { REP(p,v) printf( (%d %d) ,p.first,p.second);printf( n ); } void Bf() { for(int i=0;i<n;i++) { for(int j=0;j<n;j++) { int k; set<int> s; for(k=1;;k++) { if(i+k>n || j+k>n) break; for(int x=i;x<i+k;x++) for(int y=j;y<j+k;y++) s.insert(a[x][y]); if(SIZE(s)>m) break; } k--; if(k!=f[i][j]) printf( Wrong %d %d: %d %d n ,i,j,k,f[i][j]); } } } void Solve() { scanf( %d%d ,&n,&m); for(int i=0;i<n;i++) for(int j=0;j<n;j++) { scanf( %d ,&a[i][j]); } cur=0; for(int i=n-1;i>=0;i--) { int pre=cur; cur=cur^1; for(int j=n-1;j>=0;j--) { row[j]={{0,a[i][j]}}; col[cur][j]={{0,a[i][j]}}; sq[cur][j]={{0,a[i][j]}}; if(i==n-1 || j==n-1) { f[i][j]=1; continue; } REP(p,row[j+1]) { if(p.second==a[i][j]) continue; row[j].eb(p.first+1,p.second); if(SIZE(row[j])>m) break; } // printf( Row %d %d n ,i,j);Dbg(row[j]); REP(p,col[pre][j]) { if(p.second==a[i][j]) continue; col[cur][j].eb(p.first+1,p.second); if(SIZE(col[cur][j])>m) break; } // printf( Col %d %d n ,i,j);Dbg(col[cur][j]); seen[a[i][j]]=1; VI ps={0,0,0}; vector<const VPII*> vs={&row[j+1],&col[pre][j],&sq[pre][j+1]}; while(SIZE(sq[cur][j])<=m) { int md=INF; int mi=-1; for(int i=0;i<3;i++) { const VPII& v=*vs[i]; if(ps[i]==SIZE(v)) continue; if(v[ps[i]].first<md) { md=v[ps[i]].first; mi=i; } } if(mi<0) break; const PII &u=(*vs[mi])[ps[mi]++]; if(!seen[u.second]) { seen[u.second]=1; sq[cur][j].eb(u.first+1,u.second); } } REP(p,sq[cur][j]) seen[p.second]=0; // printf( Sq %d %d n ,i,j);Dbg(sq[cur][j]); f[i][j]=min(n-i,n-j); if(SIZE(sq[cur][j])>m) f[i][j]=min(f[i][j],sq[cur][j][m].first); // printf( %d %d: %d n ,i,j,f[i][j]); } } // Bf(); Fenwick ans(n); for(int i=0;i<n;i++) for(int j=0;j<n;j++) ans.Update(f[i][j],1); for(int i=1;i<=n;i++) printf( %d n ,ans.Get(i)); } int main() { Solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; queue<int> fila; struct G { double d; int m, p, r; } g[250002]; bool mk[250002]; int a2[9000000]; bool cmp2(int a, int b) { return g[a].d < g[b].d; } int pos = 0; int ind = 0; struct T { int m; int* e; void pdt(int a, int* b) { m = a, e = b; } } mas[2 * 250002]; bool cmp(T a, T b) { return a.m < b.m; } int ls[4 * 250002]; int s[4 * 250002][2]; int r[4 * 250002]; int build(int a, int b, int f) { int p = ind++; ls[p] = pos; r[p] = b; int i = ls[f]; for (int i = ls[f]; a2[i] >= 0; i++) { if (g[a2[i]].m >= a && g[a2[i]].m <= b) a2[pos] = a2[i], pos++; } a2[pos] = -1; pos++; if (a != b) s[p][0] = build(a, (a + b) / 2, p), s[p][1] = build(((a + b) / 2) + 1, b, p); else s[p][0] = s[p][1] = -1; return p; } void get(int p, int power, int ray) { if (r[p] <= power) { for (int i = ls[p]; a2[i] >= 0; i++) { if (g[a2[i]].d <= ray + 1e-2) { if (!mk[a2[i]]) fila.push(a2[i]), mk[a2[i]] = true; ls[p] = i + 1; } else break; } } else { get(s[p][0], power, ray); if (power > r[s[p][0]]) get(s[p][1], power, ray); } } int main() { double x0, y0; int pp, rr, n; scanf( %lf %lf %d %d %d , &x0, &y0, &pp, &rr, &n); int tot = 0; mas[tot++].pdt(pp, &pp); double x, y; for (int i = 0; i < n; i++) { scanf( %lf %lf %d %d %d , &x, &y, &g[i].m, &g[i].p, &g[i].r); x -= x0; y -= y0; g[i].d = sqrt(x * x + y * y); mk[i] = false; a2[i] = i; mas[tot++].pdt(g[i].m, &g[i].m), mas[tot++].pdt(g[i].p, &g[i].p); } a2[n] = -1; sort(mas, mas + tot, cmp); int v = 1; int tmp = mas[0].m; *mas[0].e = v; for (int i = 1; i < tot; i++) { if (mas[i].m != tmp) v++; tmp = mas[i].m; *mas[i].e = v; } sort(a2, a2 + n, cmp2); r[0] = v; ls[0] = 0; ind = 1; pos = n + 1; if (n >= 2) s[0][0] = build(1, v / 2, 0), s[0][1] = build((v / 2) + 1, v, 0); get(0, pp, rr); int resp = 0; while (fila.size()) { resp++; int u = fila.front(); fila.pop(); get(0, g[u].p, g[u].r); } printf( %d n , resp); return 0; }
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#include <bits/stdc++.h> using namespace std; char st[8][20] = { err , monday , tuesday , wednesday , thursday , friday , saturday , sunday }; int main() { char s1[20], s2[20]; scanf( %s %s , s1, s2); int t1 = 0, t2 = 0; for (int i = 1; i <= 7; i++) if (strcmp(s1, st[i]) == 0) { t1 = i; break; } for (int i = 1; i <= 7; i++) if (strcmp(s2, st[i]) == 0) { t2 = i; break; } bool flag = false; if (t1 == t2) flag = true; int tmp = t1 + 2; if (tmp > 7) tmp -= 7; if (tmp == t2) flag = true; tmp = t1 + 3; if (tmp > 7) tmp -= 7; if (tmp == t2) flag = true; puts(flag ? YES : NO ); return 0; }
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`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date: 03:54:40 13/25/2015
// Design Name: SAM Coupé clone
// Module Name: samcoupe
// Project Name: SAM Coupé clone
// Target Devices: Spartan 6
// Tool versions: ISE 12.4
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module samcoupe (
input wire clk24,
input wire clk12,
input wire clk6,
input wire clk8,
input wire master_reset_n,
// Video output
output wire [1:0] r,
output wire [1:0] g,
output wire [1:0] b,
output wire bright,
output wire hsync_pal,
output wire vsync_pal,
// Audio output
input wire ear,
output wire audio_out_left,
output wire audio_out_right,
// PS/2 keyoard interface
inout wire clkps2,
inout wire dataps2,
// SRAM interface
output wire [18:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n
);
// ROM memory
wire [14:0] romaddr;
wire [7:0] data_from_rom;
// RAM memory
wire [18:0] vramaddr, cpuramaddr;
wire [7:0] data_from_ram;
wire [7:0] data_to_asic;
wire ram_we_n;
wire asic_is_using_ram;
// Keyboard
wire [8:0] kbrows;
wire [7:0] kbcolumns;
wire kb_nmi_n;
wire kb_rst_n;
wire kb_mrst_n;
wire rdmsel;
assign kbrows = {rdmsel, cpuaddr[15:8]};
// CPU signals
wire mreq_n, iorq_n, rd_n, wr_n, int_n, wait_n, rfsh_n;
wire [15:0] cpuaddr;
wire [7:0] data_from_cpu;
wire [7:0] data_to_cpu;
// ASIC signals
wire [7:0] data_from_asic;
wire asic_oe_n;
wire rom_oe_n;
// ROM signals
assign romaddr = {cpuaddr[15], cpuaddr[13:0]};
// RAM signals
wire ram_oe_n;
// Audio signals
wire mic, beep;
wire [7:0] saa_out_l, saa_out_r;
// MUX from memory/devices to Z80 data bus
assign data_to_cpu = (rom_oe_n == 1'b0)? data_from_rom :
(ram_oe_n == 1'b0)? data_from_ram :
(asic_oe_n == 1'b0)? data_from_asic :
8'hFF;
tv80a el_z80 (
.m1_n(),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rfsh_n(rfsh_n),
.halt_n(),
.busak_n(),
.A(cpuaddr),
.dout(data_from_cpu),
.reset_n(kb_rst_n & master_reset_n),
.clk(clk6),
.wait_n(wait_n),
.int_n(int_n),
.nmi_n(kb_nmi_n),
.busrq_n(1'b1),
.di(data_to_cpu)
);
asic la_ula_del_sam (
.clk(clk12),
.rst_n(kb_rst_n & master_reset_n),
// CPU interface
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.cpuaddr(cpuaddr),
.data_from_cpu(data_from_cpu),
.data_to_cpu(data_from_asic),
.data_enable_n(asic_oe_n),
.wait_n(wait_n),
// RAM/ROM interface
.vramaddr(vramaddr),
.cpuramaddr(cpuramaddr),
.data_from_ram(data_to_asic),
.ramwr_n(ram_we_n),
.romcs_n(rom_oe_n),
.ramcs_n(ram_oe_n),
.asic_is_using_ram(asic_is_using_ram),
// audio I/O
.ear(ear),
.mic(mic),
.beep(beep),
// keyboard I/O
.keyboard(kbcolumns),
.rdmsel(rdmsel),
// disk I/O
.disc1_n(),
.disc2_n(),
// video output
.r(r),
.g(g),
.b(b),
.bright(bright),
.hsync_pal(hsync_pal),
.vsync_pal(vsync_pal),
.int_n(int_n)
);
rom rom_32k (
.clk(clk24),
.a(romaddr),
.dout(data_from_rom)
);
ram_dual_port_turnos ram_512k (
.clk(1'b0 /*clk24*/),
.whichturn(asic_is_using_ram),
.vramaddr(vramaddr),
.cpuramaddr(cpuramaddr),
.cpu_we_n(ram_we_n),
.data_from_cpu(data_from_cpu),
.data_to_asic(data_to_asic),
.data_to_cpu(data_from_ram),
// Actual interface with SRAM
.sram_a(sram_addr),
.sram_we_n(sram_we_n),
.sram_d(sram_data)
);
// ram_dual_port ram_512k (
// .clk(clk24),
// .whichturn(asic_is_using_ram),
// .vramaddr(vramaddr),
// .cpuramaddr(cpuramaddr),
// .mreq_n(ram_oe_n),
// .rd_n(rd_n),
// .wr_n(ram_we_n),
// .rfsh_n(rfsh_n),
// .data_from_cpu(data_from_cpu),
// .data_to_asic(data_to_asic),
// .data_to_cpu(data_from_ram),
// // Actual interface with SRAM
// .sram_a(sram_addr),
// .sram_we_n(sram_we_n),
// .sram_d(sram_data)
// );
ps2_keyb el_teclado (
.clk(clk6),
.clkps2(clkps2),
.dataps2(dataps2),
//---------------------------------
.rows(kbrows),
.cols(kbcolumns),
.rst_out_n(kb_rst_n),
.nmi_out_n(kb_nmi_n),
.mrst_out_n(kb_mrst_n),
.user_toggles(),
//---------------------------------
.zxuno_addr(8'h00),
.zxuno_regrd(1'b0),
.zxuno_regwr(1'b0),
.regaddr_changed(1'b0),
.din(data_from_cpu),
.keymap_dout(),
.oe_n_keymap(),
.scancode_dout(),
.oe_n_scancode(),
.kbstatus_dout(),
.oe_n_kbstatus()
);
saa1099 el_saa (
.clk(clk8), // 8 MHz
.rst_n(kb_rst_n),
.cs_n(~(cpuaddr[7:0] == 8'hFF && iorq_n == 1'b0)),
.a0(cpuaddr[8]), // 0=data, 1=address
.wr_n(wr_n),
.din(data_from_cpu),
.out_l(saa_out_l),
.out_r(saa_out_r)
);
mixer sam_audio_mixer (
.clk(clk8),
.rst_n(kb_rst_n),
.ear(ear),
.mic(mic),
.spk(beep),
.saa_left(saa_out_l),
.saa_right(saa_out_r),
.audio_left(audio_out_left),
.audio_right(audio_out_right)
);
multiboot back_to_bios (
.clk_icap(clk24), // WARNING: this clock must not be greater than 20MHz (50ns period)
.mrst_n(kb_mrst_n)
);
endmodule
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#include <bits/stdc++.h> using namespace std; struct ball { float coord; int mass; float vel; short num; }; bool sort_num(ball a, ball b) { return a.num < b.num; } bool sort_coord(ball a, ball b) { return a.coord < b.coord; } void collide(ball &a, ball &b) { float temp = a.vel; a.vel = ((a.mass - b.mass) * a.vel + 2 * b.vel * b.mass) / (b.mass + a.mass); b.vel = ((b.mass - a.mass) * b.vel + 2 * temp * a.mass) / (b.mass + a.mass); } void iter(vector<ball> &balls, int size, float &cur_time, int time) { float col_t = 9999.9; int col_c = -1; float temp; for (int i = 0; i < size - 1; i++) { temp = (balls[i + 1].coord - balls[i].coord) / (balls[i].vel - balls[i + 1].vel); if (temp > 0.0000001 && temp < col_t) { col_t = temp; col_c = i; } } if (cur_time + col_t > time || col_c == -1) { col_t = time - cur_time; for (int i = 0; i < size; i++) balls[i].coord += balls[i].vel * col_t; cur_time += col_t; return; } for (int i = 0; i < size; i++) { balls[i].coord += balls[i].vel * col_t; } for (int i = 0; i < size - 1; i++) { if (fabs(balls[i].coord - balls[i + 1].coord) < 0.0000001) { collide(balls[i], balls[i + 1]); i++; } } cur_time += col_t; } int main() { int n, t; float cur_t = 0.0; cin >> n >> t; vector<ball> balls(n); for (int i = 0; i < n; i++) { cin >> balls[i].coord >> balls[i].vel >> balls[i].mass; balls[i].num = i; } sort(balls.begin(), balls.end(), sort_coord); while (cur_t < t) { iter(balls, n, cur_t, t); } sort(balls.begin(), balls.end(), sort_num); for (int i = 0; i < n; i++) cout << balls[i].coord << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, V = 1e5; inline int read() { register int x = 0, f = 0; register char c = getchar(); while (c < 0 || c > 9 ) f |= c == - , c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); return f ? -x : x; } int n, tot, top; struct point { int x, y; } p[N * 10], s[N * 10]; point operator-(const point &A, const point &B) { return (point){A.x - B.x, A.y - B.y}; } inline void add(int x, int y) { p[++tot].x = x; p[tot].y = y; } inline double accross(point A, point B) { return (double)A.x * B.y - (double)A.y * B.x; } inline double dis(point A, point B) { return (double)(A.x - B.x) * (A.x - B.x) + (double)(A.y - B.y) * (A.y - B.y); } inline bool cmp1(const point &A, const point &B) { return A.x == B.x ? A.y < B.y : A.x < B.x; } inline bool cmp2(const point &A, const point &B) { return A.x == B.x && A.y == B.y; } inline bool cmp3(const point &A, const point &B) { double res = accross(A - p[1], B - p[1]); if (res > 0) return true; else if (res == 0 && dis(A, p[1]) < dis(B, p[1])) return true; return false; } void Get_TB() { for (int i = 2; i <= tot; ++i) if (p[1].y > p[i].y || (p[1].y == p[i].y && p[1].x > p[i].x)) swap(p[i], p[1]); sort(p + 2, p + tot + 1, cmp3); s[1] = p[1]; s[2] = p[2]; top = 2; for (int i = 3; i <= tot; ++i) { while (top > 1 && accross(p[i] - s[top - 1], s[top] - s[top - 1]) >= 0) top--; s[++top] = p[i]; } return; } inline double len(point &A) { return sqrt((double)A.x * A.x + (double)A.y * A.y); } double calc(point A, point B, point C) { point x = A - B, y = C - B, z = C - A; double res = len(x) * len(y) * len(z) / (accross(y, x) * 2); return res; } int main() { n = read(); for (int i = 1; i <= n; ++i) { int x = read(), y = read(), v = read(); if (x < v) add(0, min(V, y + v - x)), add(0, max(0, y - v + x)); else add(x - v, y); if (y < v) add(max(0, x - v + y), 0), add(min(V, x + v - y), 0); else add(x, y - v); if (x + v > V) add(V, min(V, y + x + v - V)), add(V, max(0, y - x - v + V)); else add(x + v, y); if (y + v > V) add(min(V, x + y + v - V), V), add(max(0, x - y - v + V), V); else add(x, y + v); } sort(p + 1, p + 1 + tot, cmp1); tot = unique(p + 1, p + 1 + tot, cmp2) - p - 1; Get_TB(); int id = 0; double ans = -1e9, tmp; s[0] = s[top]; s[top + 1] = s[1]; for (int i = 1; i <= top; ++i) { point a = s[i - 1], b = s[i], c = s[i + 1]; if ((tmp = calc(a, b, c)) > ans) ans = tmp, id = i; } cout << s[id - 1].x << << s[id - 1].y << n ; cout << s[id].x << << s[id].y << n ; cout << s[id + 1].x << << s[id + 1].y << n ; return 0; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_array02.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_array02(/*AUTOARG*/
// Outputs
pcx_scache2_data_px_l, pcx_scache0_data_px_l, scan_out,
// Inputs
spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa,
spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa,
spc1_pcx_data_pa, spc0_pcx_data_pa, shiftenable, rclk,
arbpc2_pcxdp_shift_px, arbpc2_pcxdp_qsel1_pa,
arbpc2_pcxdp_qsel0_pa, arbpc2_pcxdp_q0_hold_pa,
arbpc2_pcxdp_grant_pa, arbpc0_pcxdp_shift_px,
arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa,
arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa, scan_in
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l;// From pcx_dp0 of pcx_dp0.v
output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l;// From pcx_dp2 of pcx_dp2.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] arbpc0_pcxdp_grant_pa; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_q0_hold_pa;// To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_qsel0_pa; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_qsel1_pa; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_shift_px; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc2_pcxdp_grant_pa; // To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_q0_hold_pa;// To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_qsel0_pa; // To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_qsel1_pa; // To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_shift_px; // To pcx_dp2 of pcx_dp2.v
input rclk; // To pcx_dp0 of pcx_dp0.v, ...
input shiftenable; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc0_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc1_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc2_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc3_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc4_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc5_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc6_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc7_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
input scan_in;
output scan_out;
/*
pcx_dp0 AUTO_TEMPLATE(
.scan_out (),
.scan_in ());
*/
pcx_dp0 pcx_dp0(/*AUTOINST*/
// Outputs
.scan_out (), // Templated
.pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),
// Inputs
.arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
.arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7:0]),
.arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
.arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7:0]),
.arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
.rclk (rclk),
.scan_in (), // Templated
.shiftenable (shiftenable),
.spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));
/*
pcx_dp2 AUTO_TEMPLATE(
.scan_out (),
.scan_in ());
*/
pcx_dp2 pcx_dp2(/*AUTOINST*/
// Outputs
.scan_out (), // Templated
.pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),
// Inputs
.arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
.arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7:0]),
.arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
.arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7:0]),
.arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
.rclk (rclk),
.scan_in (), // Templated
.shiftenable (shiftenable),
.spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));
endmodule // pcx_dp_array02
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`timescale 1ns / 1ps
`include "riffa.vh"
module pcie_data_sender #(parameter C_PCI_DATA_WIDTH = 128, INPUT_DATA_WIDTH = 8, NUM_PES = 8) (
input clk,
input rst,
//Collector Interface
output coll_ready,
input coll_data_valid,
input[INPUT_DATA_WIDTH - 1:0] coll_data,
//RIFFA TX Interface
output CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output[`SIG_CHNL_LENGTH_W - 1:0] CHNL_TX_LEN,
output[30:0] CHNL_TX_OFF,
output[C_PCI_DATA_WIDTH - 1:0] CHNL_TX_DATA,
output reg CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
input[`SIG_CHNL_LENGTH_W - 1:0] dna_len,
output idle,
input en
);
localparam DATA_PER_TX = C_PCI_DATA_WIDTH/INPUT_DATA_WIDTH; //number of data chunks that can fit with in C_PCI_DATA_WIDTH
parameter IT_BITS = $clog2(DATA_PER_TX);
reg state = STATE_IDLE;
localparam STATE_IDLE = 1'b0;
localparam STATE_SENDING = 1'b1;
reg[`SIG_CHNL_LENGTH_W - 1:0] dna_len_r, send_len;
reg tx_issued;
//state transition logic
always@(posedge clk) begin
if(rst) begin
state <= STATE_IDLE;
dna_len_r <= 0;
send_len <= 0;
end
else begin
case(state)
STATE_IDLE: begin
if(en) begin
dna_len_r <= (dna_len - NUM_PES)*NUM_PES >> 7 /*to 128-bit chunks*/ ; // excluding reference dna reads
send_len <= (dna_len - NUM_PES)*NUM_PES >> 5/*to 32-bit words*/; // excluding reference dna reads
state <= STATE_SENDING;
end
end //STATE_IDLE
STATE_SENDING: begin
if(tx_issued) begin
dna_len_r <= dna_len_r - 1;
if(dna_len_r == 1) begin
state <= STATE_IDLE;
end
end
end //STATE_SENDING
endcase
end
end
assign idle = (state == STATE_IDLE);
//Register Input Data
reg[INPUT_DATA_WIDTH - 1:0] data_r;
reg data_valid_r;
wire fetch_input = coll_ready;
always@(posedge clk) begin
if(rst) begin
data_r <= 0;
data_valid_r <= 0;
end
else begin
if(fetch_input) begin
data_r <= coll_data;
data_valid_r <= coll_data_valid;
end
end
end
//Put data chuck in tx buffer
reg[IT_BITS - 1:0] iter = 0;
reg[C_PCI_DATA_WIDTH - 1:0] tx_buffer;
reg tx_buffer_valid = 0;
always@(posedge clk) begin
if(rst) begin
tx_buffer <= 0;
tx_buffer_valid <= 0;
end
else begin
if(data_valid_r && coll_ready) begin
tx_buffer[iter*INPUT_DATA_WIDTH +:INPUT_DATA_WIDTH] <= data_r;
iter <= iter + 1'b1;
tx_buffer_valid <= &iter;
end
else if(tx_issued) begin
tx_buffer_valid <= 1'b0;
end
end
end
//TODO: consider adding one more register stage for better timing
//Send tx buffer to RIFFA
assign CHNL_TX_LEN = send_len; //C_PCI_DATA_WIDTH/32;
assign CHNL_TX_LAST = 1'b1; //(dna_len_r == 1);
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = tx_buffer;
assign CHNL_TX = (state == STATE_SENDING);
always@* begin
tx_issued = 1'b0;
CHNL_TX_DATA_VALID = 1'b0;
if(state == STATE_SENDING) begin
if(tx_buffer_valid) begin
CHNL_TX_DATA_VALID = 1'b1;
if(CHNL_TX_DATA_REN) begin
tx_issued = 1'b1;
end
end //tx_buffer_valid
end
end
assign coll_ready = ~tx_buffer_valid || (tx_buffer_valid && tx_issued);
endmodule
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#include <bits/stdc++.h> using namespace std; bool issquare(int n) { int sq = sqrt(n); if (sq * sq == n) { return true; } else { return false; } } int main() { long long int n; cin >> n; long long int ans = n; int f = 1; while (n != 1 and f == 1) { int sqr = ceil(sqrt((n * 1.0))); f = 0; for (int i = 2; i <= sqr; i++) { if (n % i == 0) { n = n / i; ans += n; f = 1; break; } } } if (n != 1) ans += 1; cout << ans << endl; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__OR4B_FUNCTIONAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; const int OO = (int)1e9 + 1; const int MAX = 1e5 + 1; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, x, arr[3] = {}; cin >> n; for (int i = 0; i < n; i++) { cin >> x; arr[x]++; } if (!arr[1]) cout << 0 << endl; else if (arr[1] > arr[2]) cout << arr[2] + (arr[1] - arr[2]) / 3 << endl; else if (arr[2] >= arr[1]) cout << arr[1] << endl; }
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#include <bits/stdc++.h> using namespace std; int N, M, K; int Ar[110][110]; int Temp[110][110]; int Dn[110]; int Res = -1; int f() { int rev = 0; for (int i = 1, a, b; i <= N; i++) { a = 0; b = 0; for (int j = 1; j <= M; j++) { a += (Ar[i][j] == Dn[j]); b += (Ar[i][j] != Dn[j]); } rev += min(a, b); } return rev; } int main() { scanf( %d%d%d , &N, &M, &K); for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) scanf( %d , &Temp[i][j]); if (N < M) { for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) Ar[j][i] = Temp[i][j]; int temp = N; N = M; M = temp; } else for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) Ar[i][j] = Temp[i][j]; if (N <= K) { for (int i = 0, mi = (1 << M); i < mi; i++) { for (int j = 1; j <= M; j++) Dn[j] = (i & (1 << (j - 1))) != 0; int temp = f(); if (temp <= K && (Res == -1 || temp < Res)) Res = temp; } } else { for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) Dn[j] = Ar[i][j]; int temp = f(); if (temp <= K && (Res == -1 || temp < Res)) Res = temp; } } printf( %d n , Res); return 0; }
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// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_never_unknown_async (reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NEVER_UNKNOWN_ASYNC";
`include "std_ovl_reset.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_never_unknown_async_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_never_unknown_async_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_never_unknown_async_psl_logic.v"
`else
`endmodule // ovl_never_unknown_async
`endif
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#include <bits/stdc++.h> using namespace std; const double long EPS = 1e-7; vector<vector<long long>> precost(long long n, vector<long long> &p, vector<long long> &id) { vector<vector<long long>> res(n, vector<long long>(n)); for (int i = 0; i < n; i++) { vector<long long> deg(p.size()); for (int j = 1; j < p.size(); j++) { deg[p[j]]++; } long long val = 0; for (int j = i; j < n; j++) { long long cur = id[j]; while (cur != 0 && deg[cur] == 0) { val++; deg[p[cur]]--; cur = p[cur]; } res[i][j] = val; } } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<vector<long long>> adj(2); vector<vector<long long>> id(2, vector<long long>(n)); for (int i = 0; i < 2; i++) { long long a; cin >> a; adj[i].resize(a); for (int j = 1; j <= a - 1; j++) { cin >> adj[i][j]; adj[i][j]--; } for (int j = 0; j < n; j++) { cin >> id[i][j]; id[i][j]--; } } vector<vector<vector<long long>>> cost(2); for (int i = 0; i < 2; i++) { cost[i] = precost(n, adj[i], id[i]); } vector<long long> dp(n + 1); for (int i = 0; i < n; i++) { for (int j = i + 1; j <= n; j++) { dp[j] = max(dp[j], dp[i] + max(cost[0][i][j - 1], cost[1][i][j - 1])); } } cout << dp[n]; return 0; }
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/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_top (
input wire clk_50,
input wire reset_n,
output wire [9:0] dbg_phy_num_valid_blocks,
output wire dbg_phy_rebuilt_badblock,
output wire dbg_phy_remapped_runtime,
output wire err_phy_out_of_extras,
// slave wishbone interface (from SDHC)
input wire wbs_clk_i,
input wire [31:0] wbs_adr_i,
output wire [31:0] wbs_dat_o,
input wire [31:0] wbs_dat_i,
input wire [3:0] wbs_sel_i,
input wire wbs_cyc_i,
input wire wbs_stb_i,
input wire wbs_we_i,
output wire wbs_ack_o,
// master wishbone interface (to NANDC)
output wire wbm_clk_o,
output wire [2:0] wbm_cti_o, // type - cycle type identifier
output wire [1:0] wbm_bte_o, // exten - burst type extension
output wire [31:0] wbm_adr_o,
input wire [31:0] wbm_dat_i,
output wire [31:0] wbm_dat_o,
output wire [3:0] wbm_sel_o,
output wire wbm_cyc_o,
output wire wbm_stb_o,
output wire wbm_we_o,
input wire wbm_ack_i
);
wire reset_s;
synch_3 a(reset_n, reset_s, clk_50);
wire physical_init_done;
wire op_page_do;
wire [2:0] op_page_cmd;
wire [15:0] op_page_num;
wire [15:0] op_page_bram;
wire [41:0] op_page_spare_wr;
wire [41:0] op_page_spare_rd;
wire op_page_status;
wire op_page_ack;
wire op_page_done;
wire logical_init_done;
wire wb_read;
wire wb_write;
wire [9:0] wb_block;
wire wb_ack;
wire wb_done;
wire bram_wbs_clk;
wire [15:0] bram_wbs_addr;
wire bram_wbs_wren;
wire [31:0] bram_wbs_data;
wire [31:0] bram_wbs_q;
wire bram_physical_req;
wire bram_physical_ack;
wire [15:0] bram_physical_addr;
wire bram_physical_wren;
wire [31:0] bram_physical_data;
wire [31:0] bram_physical_q;
ftl_wbs ifw (
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
// slave wishbone interface (from SDHC)
.wbs_clk_i ( wbs_clk_i ),
.wbs_adr_i ( wbs_adr_i ),
.wbs_dat_o ( wbs_dat_o ),
.wbs_dat_i ( wbs_dat_i ),
.wbs_sel_i ( wbs_sel_i ),
.wbs_cyc_i ( wbs_cyc_i ),
.wbs_stb_i ( wbs_stb_i ),
.wbs_we_i ( wbs_we_i ),
.wbs_ack_o ( wbs_ack_o ),
// port to cached block ram
.bram_wbs_clk ( bram_wbs_clk ),
.bram_wbs_addr ( bram_wbs_addr ),
.bram_wbs_wren ( bram_wbs_wren ),
.bram_wbs_data ( bram_wbs_data ),
.bram_wbs_q ( bram_wbs_q ),
.logical_init_done ( logical_init_done ),
.wb_read ( wb_read ),
.wb_write ( wb_write ),
.wb_block ( wb_block ),
.wb_ack ( wb_ack ),
.wb_done ( wb_done )
);
ftl_logical ilog (
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
.physical_init_done ( physical_init_done ),
.init_done ( logical_init_done ),
.wb_read ( wb_read ),
.wb_write ( wb_write ),
.wb_block ( wb_block ),
.wb_ack ( wb_ack ),
.wb_done ( wb_done ),
.op_page_do ( op_page_do ),
.op_page_cmd ( op_page_cmd ),
.op_page_num ( op_page_num ),
.op_page_bram ( op_page_bram ),
.op_page_spare_wr ( op_page_spare_wr ),
.op_page_spare_rd ( op_page_spare_rd ),
.op_page_status ( op_page_status ),
.op_page_ack ( op_page_ack ),
.op_page_done ( op_page_done )
);
ftl_buf ibuf (
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
.bram_wbs_clk ( bram_wbs_clk ),
.bram_wbs_addr ( bram_wbs_addr ),
.bram_wbs_wren ( bram_wbs_wren ),
.bram_wbs_data ( bram_wbs_data ),
.bram_wbs_q ( bram_wbs_q ),
.bram_physical_addr ( bram_physical_addr ),
.bram_physical_wren ( bram_physical_wren ),
.bram_physical_data ( bram_physical_data ),
.bram_physical_q ( bram_physical_q )
);
ftl_physical iphy(
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
.init_done ( physical_init_done ),
.dbg_num_valid_blocks ( dbg_phy_num_valid_blocks ),
.dbg_rebuilt_badblock ( dbg_phy_rebuilt_badblock ),
.dbg_remapped_runtime ( dbg_phy_remapped_runtime ),
.err_out_of_extras ( err_phy_out_of_extras ),
.bram_page_addr ( bram_physical_addr ),
.bram_page_wren ( bram_physical_wren ),
.bram_page_data ( bram_physical_data ),
.bram_page_q ( bram_physical_q ),
.op_page_do ( op_page_do ),
.op_page_cmd ( op_page_cmd ),
.op_page_num ( op_page_num ),
.op_page_bram ( op_page_bram ),
.op_page_spare_wr ( op_page_spare_wr ),
.op_page_spare_rd ( op_page_spare_rd ),
.op_page_status ( op_page_status ),
.op_page_ack ( op_page_ack ),
.op_page_done ( op_page_done ),
.wbm_clk_o ( wbm_clk_o ),
.wbm_cti_o ( wbm_cti_o ),
.wbm_bte_o ( wbm_bte_o ),
.wbm_adr_o ( wbm_adr_o ),
.wbm_dat_i ( wbm_dat_i ),
.wbm_dat_o ( wbm_dat_o ),
.wbm_sel_o ( wbm_sel_o ),
.wbm_cyc_o ( wbm_cyc_o ),
.wbm_stb_o ( wbm_stb_o ),
.wbm_we_o ( wbm_we_o ),
.wbm_ack_i ( wbm_ack_i )
);
/*
(* mark_debug = "true" *) reg wb_read_reg;
(* mark_debug = "true" *) reg wb_write_reg;
(* mark_debug = "true" *) reg [9:0] wb_block_reg;
(* mark_debug = "true" *) reg wb_ack_reg;
(* mark_debug = "true" *) reg wb_done_reg;
(* mark_debug = "true" *) reg logical_init_done_reg;
(* mark_debug = "true" *) reg physical_init_done_reg;
always @(posedge clk_50) begin
wb_read_reg <= wb_read;
wb_write_reg <= wb_write;
wb_block_reg <= wb_block;
wb_ack_reg <= wb_ack;
wb_done_reg <= wb_done;
logical_init_done_reg <= logical_init_done;
physical_init_done_reg <= physical_init_done;
end
ila_0 ila_0 (
.clk(clk_50),
.probe0({
physical_init_done_reg,
logical_init_done_reg,
wb_done_reg,
wb_ack_reg,
wb_block_reg,
wb_write_reg,
wb_read_reg
})
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int SIZE = 2e6 + 10; int a[SIZE]; int num[SIZE], nxt[SIZE]; int main() { int n, q; scanf( %d%d , &n, &q); long long sum = 0; for (int i = 0; i < (n); ++i) { scanf( %d , &(a[i])); sum += a[i]; a[i + n] = a[i]; } for (int tt = 1; tt <= q; tt++) { long long b; scanf( %I64d , &b); if (b >= sum) { puts( 1 ); continue; } { int rr = -1; long long now = 0; for (int i = 0; i < (n); ++i) { while (now + a[rr + 1] <= b) now += a[++rr]; nxt[i] = rr + 1; nxt[i + n] = rr + 1 + n; num[i] = 1; now -= a[i]; } } int an = n; for (int i = n - 1; i >= 0; i--) { if (nxt[i] < n) { num[i] += num[nxt[i]]; nxt[i] = nxt[nxt[i]]; } if (nxt[i] >= i + n) an = min(an, num[i]); } printf( %d n , an); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios ::sync_with_stdio(0); cin.tie(0); long long n; int k; cin >> n >> k; long long num = 0; long long idx = 1; long long todie = n; for (int i = 0; i < k; ++i) { long long x; cin >> x; if (n % x < todie) { todie = n % x; idx = i + 1; num = n / x; } } cout << idx << << num; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// cpu_behavioral.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: cpu_behavioral.v,v $
// Revision 1.2 2010-01-08 01:41:08 Nathan
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan
// Original from OpenCores
//
// Revision 1.4 2004/03/28 20:27:40 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004/01/22 11:07:28 mohor
// test stall_test added.
//
// Revision 1.2 2004/01/17 18:01:31 mohor
// New version.
//
// Revision 1.1 2004/01/17 17:01:25 mohor
// Almost finished.
//
//
//
//
//
`include "timescale.v"
module cpu_behavioral
(
// CPU signals
cpu_rst_i,
cpu_clk_o,
cpu_addr_i,
cpu_data_o,
cpu_data_i,
cpu_bp_o,
cpu_stall_i,
cpu_stb_i,
cpu_we_i,
cpu_ack_o,
cpu_rst_o
);
// CPU signals
input cpu_rst_i;
output cpu_clk_o;
input [31:0] cpu_addr_i;
output [31:0] cpu_data_o;
input [31:0] cpu_data_i;
output cpu_bp_o;
input cpu_stall_i;
input cpu_stb_i;
input cpu_we_i;
output cpu_ack_o;
output cpu_rst_o;
reg cpu_clk_o;
reg [31:0] cpu_data_o;
reg cpu_bp_o;
reg cpu_ack_o;
reg cpu_ack_q;
wire cpu_ack;
initial
begin
cpu_clk_o = 1'b0;
forever #5 cpu_clk_o = ~cpu_clk_o;
end
initial
begin
cpu_bp_o = 1'b0;
end
assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
if (cpu_rst_i)
begin
cpu_ack_o <= #1 1'b0;
cpu_ack_q <= #1 1'b0;
end
else
begin
cpu_ack_o <= #1 cpu_ack;
cpu_ack_q <= #1 cpu_ack_o;
end
end
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
if (cpu_rst_i)
cpu_data_o <= #1 32'h12345678;
else if (cpu_ack_o && (!cpu_ack_q))
cpu_data_o <= #1 cpu_data_o + 32'h11111111;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1003, INF = 0x3f3f3f3f; long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a; a = a * a; b >>= 1; } return ans; } int n, m, k; int a[N][N]; int ans = 0; void dfs(int first, int second, int xx, int yy) { if (first == n + 1) { ans = yy; return; } if (a[first][second] == 1) { a[first][second] = 2; dfs(first, second + 1, first, second); } else if (a[first][second] == 2) { dfs(first + 1, second, first, second); } else { a[first][second] = 2; dfs(first, second - 1, first, second); } } int main() { ios::sync_with_stdio; cin.tie(0); cout.tie(0); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } for (int i = 1; i <= k; i++) { int first; cin >> first; ans = 0; dfs(1, first, 0, 0); cout << ans << ; } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long Hash(char* s, int sz) { const int p = 31; long long hash = 0, p_pow = 1; for (size_t i = 0; i < sz; ++i) { hash += (s[i] - a + 1) * p_pow; p_pow *= p; } return hash; } int gcd(int a, int b) { while (b) { a %= b; swap(a, b); } return a; } vector<int> fac; void Factor(int N) { int n = N; for (int i = 2; i * i <= N; i++) { if (n % i == 0) { fac.push_back(i); n /= i; i--; } } if (n > 1) fac.push_back(n); sort(fac.begin(), fac.end()); fac.push_back(1); } int main() { int n; scanf( %d , &n); fac.clear(); Factor(n); int qur = 1; long long ans = 0; int k = 0; while (fac.size() != k) { ans += n / qur; qur *= fac[k]; k++; } printf( %I64d , ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:13:35 03/31/2015
// Design Name:
// Module Name: zlozony
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module zlozony(
input clk,
input ce,
input [17:0] a,
input [7:0] b,
input [11:0] c,
input [7:0] d,
input [13:0] e,
input [18:0] f,
output [36:0] y
);
wire [18:0] sum_ab;
wire [11:0] c_del;
wire [14:0] sum_de;
wire [14:0] sum_de_del;
wire [19:0] sum_ef;
wire [30:0] mul_abc;
wire [34:0] mul_def;
sum_18_13 summer_ab (
.a(a), // input [17 : 0] a
.b({b, 5'd0}), // input [12 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(sum_ab) // output [18 : 0] s
);
delay_line #(
.DELAY(3),
.WIDTH(12)
) delay_c (
.clk(clk),
.ce(ce),
.in(c),
.out(c_del),
.rst(1'b0)
);
sum_11_14 summer_de (
.a({d, 3'd0}), // input [10 : 0] a
.b(e), // input [13 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(sum_de) // output [14 : 0] s
);
delay_line #(
.DELAY(1),
.WIDTH(15)
) delay_sum_de (
.clk(clk),
.ce(ce),
.in(sum_de),
.out(sum_de_del),
.rst(1'b0)
);
sum_18_19 summer_ef (
.a({e, 4'd0}), // input [17 : 0] a
.b(f), // input [18 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(sum_ef) // output [19 : 0] s
);
mul_19_12 multiplier_abc (
.clk(clk), // input clk
.ce(ce), // input ce
.a(sum_ab), // input [18 : 0] a
.b(c_del), // input [11 : 0] b
.p(mul_abc) // output [30 : 0] p
);
mul_15_20 multiplier_def (
.clk(clk), // input clk
.ce(ce), // input ce
.a(sum_de_del), // input [14 : 0] a
.b(sum_ef), // input [19 : 0] b
.p(mul_def) // output [34 : 0] p
);
sum_31_36 sum_abcdef (
.a(mul_abc), // input [30 : 0] a
.b({mul_def, 1'b0}), // input [35 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(y) // output [36 : 0] s
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int r[105]; int i; double pi = acos(-1.0); for (i = 0; i < n; i++) { cin >> r[i]; } sort(r, r + n); int s = 0; for (i = 0; i < n; i++) { s = r[i] * r[i] - s; } printf( %.6lf n , s * pi); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> T my_pow(T n, T p) { if (p == 0) return 1; T x = my_pow(n, p / 2); x = (x * x); if (p & 1) x = (x * n); return x; } template <class T> T big_mod(T n, T p, T m) { if (p == 0) return (T)1; T x = big_mod(n, p / 2, m); x = (x * x) % m; if (p & 1) x = (x * n) % m; return x; } template <class T> inline T Mod(T n, T m) { return (n % m + m) % m; } template <class T> T extract(string s, T ret) { stringstream ss(s); ss >> ret; return ret; } template <class T> string itos(T n) { ostringstream ost; ost << n; ost.flush(); return ost.str(); } long long stoi(string s) { long long r = 0; istringstream sin(s); sin >> r; return r; } double toDouble(string s) { double r = 0; istringstream sin(s); sin >> r; return r; } long long ar[2000005], ar1[200005]; long long a = 0, b = 0, c = 0, r = 0, rr = 0, res = 0, n, m; string s, ss; long long fun(long long val) { r = 0; for (__typeof(n) i = 0; i < (n); i++) { if (val < ar[i]) return false; r += (val - ar[i]); } if (r >= val) return true; else return false; } int main() { cin >> n; for (__typeof(n) i = 0; i < (n); i++) { cin >> ar[i]; } long long lo = 0, hi = 10000000000ll; while (hi - lo > 1) { long long mid = (lo + hi) >> 1; if (fun(mid)) hi = mid; else lo = mid; } cout << hi; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a; stack<int> q; vector<int> d; void insert(int x) { if (q.empty()) { q.push(x); return; } if (q.top() != x) { q.push(x); return; } q.pop(); insert(x + 1); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a), insert(a); while (!q.empty()) d.push_back(q.top()), q.pop(); int k = d.size(); printf( %d n , k); for (int i = k - 1; i >= 0; i--) printf( %d%c , d[i], i ? : n ); return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Serial Output Controller ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_soc.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_soc.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_soc(clk, wclk, rst,
ps_ce, resume, suspended,
sync, out_le, in_valid, ld, valid
);
input clk, wclk, rst;
input ps_ce;
input resume;
output suspended;
output sync;
output [5:0] out_le;
output [2:0] in_valid;
output ld;
output valid;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] cnt;
reg sync_beat;
reg sync_resume;
reg [5:0] out_le;
reg ld;
reg valid;
reg [2:0] in_valid;
reg bit_clk_capture;
reg bit_clk_capture_r;
//reg bit_clk_r;
//reg bit_clk_r1;
reg bit_clk_e;
reg suspended;
wire to;
reg [5:0] to_cnt;
reg [3:0] res_cnt;
wire resume_done;
assign sync = sync_beat | sync_resume;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 8'hff;
else
if(suspended) cnt <= #1 8'hff;
else cnt <= #1 cnt + 8'h1;
always @(posedge clk)
ld <= #1 (cnt == 8'h00);
always @(posedge clk)
sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
always @(posedge clk)
valid <= #1 (cnt > 8'h39);
always @(posedge clk)
out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
always @(posedge clk)
out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
always @(posedge clk)
out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
always @(posedge clk)
out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
always @(posedge clk)
out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
always @(posedge clk)
out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
always @(posedge clk)
in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
always @(posedge clk)
in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
always @(posedge clk)
in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
always @(clk or bit_clk_e)
if(clk) bit_clk_capture <= #1 1'b1;
else
if(bit_clk_e) bit_clk_capture <= #1 1'b0;
//always @(posedge wclk)
// bit_clk_r <= #1 clk;
//
//always @(posedge wclk)
// bit_clk_r1 <= #1 bit_clk_r;
//
//always @(posedge wclk)
// bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
always @(posedge wclk)
bit_clk_capture_r <= #1 bit_clk_capture;
always @(posedge wclk)
bit_clk_e <= #1 bit_clk_capture_r;
always @(posedge wclk)
suspended <= #1 to;
assign to = (to_cnt == `AC97_SUSP_DET);
always @(posedge wclk or negedge rst)
if(!rst) to_cnt <= #1 6'h0;
else
if(bit_clk_e) to_cnt <= #1 6'h0;
else
if(!to) to_cnt <= #1 to_cnt + 6'h1;
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
always @(posedge wclk or negedge rst)
if(!rst) sync_resume <= #1 1'b0;
else
if(resume_done) sync_resume <= #1 1'b0;
else
if(suspended & resume) sync_resume <= #1 1'b1;
assign resume_done = (res_cnt == `AC97_RES_SIG);
always @(posedge wclk)
if(!sync_resume) res_cnt <= #1 4'h0;
else
if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, V, A[64], B[64]; bool canCook(double x) { double tot = 0.0; for (int i = 0; i < n; i++) if (A[i] * x > B[i]) return 0; else tot += A[i] * x; return tot <= V; } double totalAmount(double x) { double tot = 0.0; for (int i = 0; i < n; i++) tot += A[i] * x; return tot; } int main() { scanf( %d%d , &n, &V); for (int i = 0; i < n; i++) scanf( %d , &A[i]); for (int i = 0; i < n; i++) scanf( %d , &B[i]); double lo = 0.0, hi = double(2 * V), mid; while (abs(hi - lo) >= 1e-6) { mid = (hi + lo) / 2; if (canCook(mid)) lo = mid; else hi = mid; } printf( %.6f n , totalAmount(lo)); }
|
#include <bits/stdc++.h> using namespace std; template <class P, class Q> inline bool mmin(P &a, Q b) { if (a > b) { a = b; return true; } return false; } template <class P, class Q> inline bool mmax(P &a, Q b) { if (a < b) { a = b; return true; } return false; } const int MAXn = 400 + 5, INF = 1000; int n; vector<pair<int, int> > adj[MAXn]; vector<int> son[MAXn]; int par[MAXn], siz[MAXn]; int dp[MAXn][MAXn]; int cur[MAXn][MAXn], upd[MAXn][MAXn]; bool mark[MAXn]; int nxt[MAXn]; inline void calcDP(int x) { int m = ((int)son[x].size()); cur[m][0] = 0; for (int j = 1; j < siz[x]; ++j) cur[m][j] = INF; int s = 0; for (int i = m - 1; i >= 0; --i) { s += siz[son[x][i]]; for (int j = 0; j <= s; ++j) { cur[i][j] = INF; for (int k = 0; k <= j && k <= siz[son[x][i]]; ++k) if (j - k <= s - siz[son[x][i]] && mmin(cur[i][j], cur[i + 1][j - k] + dp[son[x][i]][k])) upd[i][j] = k; } } } void DFS(int x) { siz[x] = 1; for (int i = 0; i < ((int)adj[x].size()); ++i) { int y = adj[x][i].first; if (y != par[x]) { son[x].push_back(y); par[y] = x; DFS(y); siz[x] += siz[y]; } } calcDP(x); dp[x][0] = 1; for (int j = 1; j <= siz[x]; ++j) dp[x][j] = cur[0][j - 1]; } void DFS2(int x, int k) { if (!k) return; mark[x] = 1; if (k == 1) return; calcDP(x); int y = k - 1; for (int i = 0; i < ((int)son[x].size()); ++i) { nxt[son[x][i]] = upd[i][y]; y -= upd[i][y]; } y = k - 1; for (int i = 0; i < ((int)son[x].size()); ++i) { DFS2(son[x][i], nxt[son[x][i]]); y -= nxt[son[x][i]]; } } int main() { ios_base::sync_with_stdio(false); int k; cin >> n >> k; for (int i = 0; i < n - 1; ++i) { int x, y; cin >> x >> y; --x; --y; adj[x].push_back(pair<int, int>(y, i + 1)); adj[y].push_back(pair<int, int>(x, i + 1)); } fill(dp[0], dp[n], INF); DFS(0); int mn = dp[0][k], ind = 0; for (int i = 1; i < n; ++i) if (mmin(mn, dp[i][k] + 1)) ind = i; DFS2(ind, k); vector<int> v; for (int i = 0; i < n; ++i) for (int j = 0; j < ((int)adj[i].size()); ++j) if (adj[i][j].first > i && (mark[i] ^ mark[adj[i][j].first])) v.push_back(adj[i][j].second); cout << ((int)v.size()) << endl; for (int i = 0; i < ((int)v.size()); ++i) cout << v[i] << ; cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A211O_BEHAVIORAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_BEHAVIORAL_PP_V
|
/*
* Copyright (c) 2013, Stefan Kristiansson <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module avalon_to_wb_bridge #(
parameter DW = 32, // Data width
parameter AW = 32 // Address width
)(
input clk,
input rst,
// Avalon Master input
input [AW-1:0] avm_address_i,
input [DW/8-1:0] avm_byteenable_i,
input avm_read_i,
output [DW-1:0] avm_readdata_o,
input [7:0] avm_burstcount_i,
input avm_write_i,
input [DW-1:0] avm_writedata_i,
output avm_waitrequest_o,
output avm_readdatavalid_o,
// Wishbone Master Output
output [AW-1:0] wbm_adr_o,
output [DW-1:0] wbm_dat_o,
output [DW/8-1:0] wbm_sel_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
input wbm_rty_i
);
reg read_access;
always @(posedge clk)
if (rst)
read_access <= 0;
else if (wbm_ack_i | wbm_err_i)
read_access <= 0;
else if (avm_read_i)
read_access <= 1;
reg readdatavalid;
reg [DW-1:0] readdata;
always @(posedge clk) begin
readdatavalid <= (wbm_ack_i | wbm_err_i) & read_access;
readdata <= wbm_dat_i;
end
assign wbm_adr_o = avm_address_i;
assign wbm_dat_o = avm_writedata_i;
assign wbm_sel_o = avm_byteenable_i;
assign wbm_we_o = avm_write_i;
assign wbm_cyc_o = read_access | avm_write_i;
assign wbm_stb_o = read_access | avm_write_i;
assign wbm_cti_o = 3'b111; // TODO: support burst accesses
assign wbm_bte_o = 2'b00;
assign avm_waitrequest_o = !(wbm_ack_i | wbm_err_i);
assign avm_readdatavalid_o = readdatavalid;
assign avm_readdata_o = readdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long(n), (k); scanf( %lld%lld , &(n), &(k)); ; long long n2 = n; vector<long long> vec; while (n) { vec.push_back(n); if (n - 1 > 0) vec.push_back(n - 1); if (n - 2 > 0) vec.push_back(n - 2); if (n - 3 > 0) vec.push_back(n - 3); n /= 2; } long long maxi = 1; auto allok = [&](long long v) { long long mi = v, ma = (v % 2) ? v : v + 1; long long c = ma - mi + 1; while (ma <= n2) { mi *= 2; ma = 2 * ma + 1; if (mi < n2) c += min(ma, n2) - mi + 1; } return c >= k; }; for (auto i : vec) { if (allok(i)) maxi = max(maxi, i); } printf( %lld n , maxi); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int logb(int base, int x) { return (log(x) / log(base)); } int occurs(vector<long long> v, int n) { auto it = lower_bound(((v)).begin(), ((v)).end(), (n)); auto it1 = upper_bound(((v)).begin(), ((v)).end(), (n)); int x = it1 - it; return x; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long powm(int a, int b) { long long res = 1; while (b) { if (b & 1) res = (res * 1LL * a) % mod; b >>= 1; a = (a * 1LL * a) % mod; } return res; } long long nCr(long long n, long long k) { int fact[n]; long long res = (fact[n] * powm(fact[k], mod - 2)) % mod; return (res * powm(fact[n - k], mod - 2)) % mod; } const int N = 1e5 + 5, inf = 1e9; vector<int> g[N]; int n, m, d; int mxin[N], mxout[N], marked[N]; void dfs_down(int v, int p) { mxin[v] = -inf; if (marked[v]) mxin[v] = 0; for (auto u : g[v]) { if (u == p) continue; dfs_down(u, v); mxin[v] = max(mxin[v], mxin[u] + 1); } } void dfs_up(int v, int p) { int max1 = -1 * inf, max2 = -1 * inf; for (auto u : g[v]) { if (u == p) continue; if (mxin[u] >= max1) max2 = max1, max1 = mxin[u]; else if (mxin[u] > max2) max2 = mxin[u]; } for (auto u : g[v]) { if (u == p) continue; int used = (mxin[u] == max1) ? max2 : max1; mxout[u] = max(1 + mxout[v], 2 + used); if (mxout[u] < 0 && marked[u]) mxout[u] = 0; dfs_up(u, v); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> d; int x, y; for (int(i) = 0; (i) < (m); ++(i)) { cin >> x; marked[x] = 1; } for (int(i) = 0; (i) < (n - 1); ++(i)) { cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs_down(1, 0); mxout[1] = (marked[1] ? 0 : -inf); dfs_up(1, 0); int ans = 0; for (int i = 1; i <= n; i++) ans += (mxin[i] <= d && mxout[i] <= d); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int R, C; cin >> R >> C; char m[R][C]; for (int i = 0; i < R; i++) for (int j = 0; j < C; j++) cin >> m[i][j]; for (int i = 0; i < R; i++) for (int j = 0; j < C; j++) { if (m[i][j] == S ) { if (i > 0) if (m[i - 1][j] == W ) { cout << No n ; return 0; } if (i < R - 1) if (m[i + 1][j] == W ) { cout << No n ; return 0; } if (j > 0) if (m[i][j - 1] == W ) { cout << No n ; return 0; } if (j < C - 1) if (m[i][j + 1] == W ) { cout << No n ; return 0; } } } cout << Yes n ; for (int i = 0; i < R; i++) for (int j = 0; j < C; j++) if (m[i][j] == . ) m[i][j] = D ; for (int i = 0; i < R; i++) { for (int j = 0; j < C; j++) { cout << m[i][j]; } cout << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_PP_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM with byte enables
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
// DATA = 0; // While this line is better coding sytle, it leads to incorrect synthsis for some tools
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif // !`ifdef __ICARUS__
always @(posedge CLK) begin
if (EN) begin
if (|WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule // BRAM1BE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:32:42 03/12/2013
// Design Name:
// Module Name: butterfly_unit_radix4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module butterfly_unit_radix4(
input clk,
input[15:0] cos0,
input[15:0] sin0,
input[15:0] cos1,
input[15:0] sin1,
input[15:0] cos2,
input[15:0] sin2,
input[15:0] x1_re,
input[15:0] x1_im,
input[15:0] x2_re,
input[15:0] x2_im,
input[15:0] x3_re,
input[15:0] x3_im,
input[15:0] x4_re,
input[15:0] x4_im,
output[15:0] p1_re,
output[15:0] p1_im,
output[15:0] p2_re,
output[15:0] p2_im,
output[15:0] p3_re,
output[15:0] p3_im,
output[15:0] p4_re,
output[15:0] p4_im
);
/**³Ë·¨Êä³ö**/
wire[15:0] X2_re;
wire[15:0] X2_im;
wire[15:0] X3_re;
wire[15:0] X3_im;
wire[15:0] X4_re;
wire[15:0] X4_im;
/**end**/
reg[15:0] X1_re_reg0 = 16'd0;
reg[15:0] X1_re_reg1 = 16'd0;
reg[15:0] X1_re_reg2 = 16'd0;
reg[15:0] X1_re_reg3 = 16'd0;
reg[15:0] X1_re_reg4 = 16'd0;
reg[15:0] X1_re_reg5 = 16'd0;
reg[15:0] X1_im_reg0 = 16'd0;
reg[15:0] X1_im_reg1 = 16'd0;
reg[15:0] X1_im_reg2 = 16'd0;
reg[15:0] X1_im_reg3 = 16'd0;
reg[15:0] X1_im_reg4 = 16'd0;
reg[15:0] X1_im_reg5 = 16'd0;
always @(posedge clk)
begin
X1_re_reg0 <= x1_re;
X1_im_reg0 <= x1_im;
X1_re_reg1 <= X1_re_reg0;
X1_im_reg1 <= X1_im_reg0;
X1_re_reg2 <= X1_re_reg1;
X1_im_reg2 <= X1_im_reg1;
X1_re_reg3 <= X1_re_reg2;
X1_im_reg3 <= X1_im_reg2;
X1_re_reg4 <= X1_re_reg3;
X1_im_reg4 <= X1_im_reg3;
X1_re_reg5 <= X1_re_reg4;
X1_im_reg5 <= X1_im_reg4;
end
complex_mul inst0_complex_mul(
.clk(clk),
.ar(cos0),
.ai(sin0),
.br(x2_re),
.bi(x2_im),
.pr(X2_re),
.pi(X2_im)
);
complex_mul inst1_complex_mul(
.clk(clk),
.ar(cos1),
.ai(sin1),
.br(x3_re),
.bi(x3_im),
.pr(X3_re),
.pi(X3_im)
);
complex_mul inst2_complex_mul(
.clk(clk),
.ar(cos2),
.ai(sin2),
.br(x4_re),
.bi(x4_im),
.pr(X4_re),
.pi(X4_im)
);
complex_add_radix_4 inst_complex_add_radix_4(
.clk(clk),
.x1_re(X1_re_reg5),
.x1_im(X1_im_reg5),
.x2_re(X2_re),
.x2_im(X2_im),
.x3_re(X3_re),
.x3_im(X3_im),
.x4_re(X4_re),
.x4_im(X4_im),
.re_0(p1_re),
.im_0(p1_im),
.re_1(p2_re),
.im_1(p2_im),
.re_2(p3_re),
.im_2(p3_im),
.re_3(p4_re),
.im_3(p4_im)
);
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007-2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
`timescale 1ns/10ps
`include "../../soclib/pipeconnect.h"
module main(input wire CLK_48_MHZ,
// Table 1
//output wire BURST_MODE,
input wire CHRG_N,
input wire LBO_N,
// Table 2
output wire ENABLE_12V,
// Table 3
//output wire ADC_SPI_DIN,
input wire ADC_SPI_DOUT,
//output wire ADC_SPI_CLK,
//output wire ADC_SPI_CS_N,
// Table 4
//output wire MISO, // XXX IS THE DIRECTION CORRECT?
input wire MOSI,
input wire SPI_CLK,
// Table 5
//output wire AUDIO_SPI_DATA,
//output wire AUDIO_SPI_EN,
//output wire AUDIO_SPI_CLK,
//output wire AUDIO_I2C_DATA,
//output wire AUDIO_I2C_WS,
//output wire AUDIO_I2C_CLK,
//output wire AUDIO_CLK,
// Table 6
//output wire [16:0] FLASH_A,
//inout wire [15:0] FLASH_D,
input wire FLASH_WAIT,
//output wire FLASH_ADV_N,
//output wire FLASH_CLK,
//output wire FLASH_RST_N,
//output wire FLASH_OE_N,
//output wire FLASH_CE_N,
//output wire FLASH_WP_N,
//output wire FLASH_WE_N, // XXX ?
// Table 7
input wire SD_CARD_SPI_MISO, // SD_D[0]
//output wire SD_CARD_SPI_MOSI,
////output wire ADC_SPI_CLK,
//output wire SD_SCARD_SPI_CS_N,
// Table 8
input wire SD_PROTECT_N,
input wire SD_DETECT_N,
input wire SD_D2,
input wire SD_D1,
// Table 9
//output wire HSEN,
// Table 10
inout wire [ 7:0] DISPLAY_D,
//output wire DISPLAY_ERD_N,
//output wire DISPLAY_RW_N,
//output wire DISPLAY_DC_N,
//output wire DISPLAY_BSI,
//output wire DISPLAY_RES_N,
//output wire DISPLAY_CS_N,
// Table 11
input wire [ 5:0] USER_PB, // {ENTER,ESC,DOWN,UP,RIGHT,LEFT}
input wire BUTTON_INT_N,
// Table 12
output wire [ 3:0] USER_LED,
// Table 13
inout wire [12:1] USER_IO,
// The MT45W4MW16BCGB PSRAM
output wire RAM_CLK,
output wire RAM_CE_N,
output wire RAM_WE_N,
output wire RAM_OE_N,
output wire RAM_ADV_N,
output wire [22:1] RAM_A,
inout wire [15:0] RAM_D,
output wire RAM_CRE,
output wire RAM_LB_N,
output wire RAM_UB_N,
input wire RAM_WAIT
);
parameter FREQ = 48_000_000; // match clock frequency
parameter BPS = 115_200; // Serial speed
wire clock, clock_locked;
// Actually, just a 1-1 clock filter at this point
assign clock = CLK_48_MHZ;
assign clock_locked = 1;
assign USER_LED = rst_counter[25:22];
reg [26:0] rst_counter = 0;
always @(posedge clock)
if (~USER_PB[0] | ~clock_locked)
rst_counter <= 'd48_000_000;
else if (~rst_counter[26])
rst_counter <= rst_counter - 1;
wire rst = ~rst_counter[26];
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire ttyb_txd;
assign USER_IO[11] = 1'bz; // Input
assign USER_IO[12] = ttyb_txd;
wire ttyb_rxd = USER_IO[11];
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
yari yari_inst(
.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
/*
reg state_read = 0;
reg [ 4:0] a = 2;
reg [ 4:0] my_address;
reg [31:0] my_writedata;
reg my_read = 0;
reg my_write = 0;
assign mem_address = my_address;
assign mem_read = my_read;
assign mem_write = my_write;
assign mem_writedata = my_writedata;
assign mem_writedatamask = 'hF;
assign mem_id = mem_address;
always @(posedge clock)
if (!rst & !mem_waitrequest) begin
my_read <= 0;
my_write <= 0;
state_read <= !state_read;
if (state_read) begin
my_address <= a - 1'd3;
my_read <= 1;
end else begin
a <= a + 1'd1;
my_address <= a;
my_writedata <= (a << 16) + (a << 2);
my_write <= 1;
end
end
*/
assign RAM_CLK = 0;
assign RAM_CRE = 0;
assign RAM_ADV_N = 0;
sram16_ctrl sram16_ctrl_inst
(.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(RAM_A[22:1])
,.sram_d(RAM_D)
,.sram_cs_n(RAM_CS_N)
,.sram_be_n({RAM_UB_N,RAM_LB_N})
,.sram_oe_n(RAM_OE_N)
,.sram_we_n(RAM_WE_N)
);
rs232out rs232out_inst
(.clock(clock),
.serial_out(ttyb_txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clock),
.serial_in(ttyb_rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clock),
.rst(rst),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
endmodule
|
`timescale 1ns / 1ps
module clock_get_all(input clk_origin, //需输入50MHz时钟，
input clkcnt_reset, //异步复位，低有效用于仿真
output out_clk_1khz, //对输入50k分频后输出时钟
output out_clk_100hz); //对输入时钟500k分频后输出
wire clk_1ms; //千分之一秒
wire clk_1cs; //百分之一秒
assign out_clk_1khz = clk_1ms;
assign out_clk_100hz = clk_1cs;
clock_div_50k instan_div_50k (.clk(clk_origin),
.clkcnt_reset(clkcnt_reset),
.div_50k(clk_1ms)); //得毫秒时钟
clock_div_500k instan_div_500k(.clk(clk_origin),
.clkcnt_reset(clkcnt_reset),
.div_500k(clk_1cs)); //得百分之一秒时钟
endmodule
//50k分频器，异步复位低有效
module clock_div_50k(clk, clkcnt_reset, div_50k);
input clk;
input clkcnt_reset;
output div_50k;
reg div_50k;
reg [19:0] cnt;
always @(negedge clkcnt_reset or posedge clk)begin
if(~clkcnt_reset) cnt <= 0;
else if (cnt >= 50000) begin
div_50k <= 0;
cnt <= 0; end
else if (cnt < 25000) begin
div_50k <= 0;
cnt <= cnt + 1; end
else if ((cnt >= 25000) && (cnt < 50000)) begin
div_50k <= 1;
cnt <= cnt + 1; end
end // always
endmodule
//500k分频器，异步复位低电平有效
module clock_div_500k(clk, clkcnt_reset, div_500k);
input clk;
input clkcnt_reset;
output div_500k;
reg div_500k;
reg [19:0] cnt;
always @(negedge clkcnt_reset or posedge clk)begin
if(~clkcnt_reset) cnt <= 0;
else if (cnt >= 500000) begin
div_500k <= 0;
cnt <= 0; end
else if (cnt < 250000) begin
div_500k <= 0;
cnt <= cnt + 1; end
else if ((cnt >= 250000) && (cnt < 500000)) begin
div_500k <= 1;
cnt <= cnt + 1; end
end // always
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i, x, sum = 0; long long int c[100009]; scanf( %lld %lld , &n, &x); for (i = 0; i < n; i++) { scanf( %lld , &c[i]); } sort(c, c + n); for (i = 0; i < n; i++) { sum = sum + c[i] * x; x--; if (x == 0) x++; } printf( %lld n , sum); }
|
//library ieee;
//use ieee.std_logic_1164.all;
//use ieee.std_logic_unsigned.all;
//-----------------------------------------------------
// Design Name : ram_dp_sr_sw
// File Name : ram_dp_sr_sw.v
// Function : Synchronous read write RAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
`timescale 1ns/1ps
module blk_mem #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 4
)(
input clka,
input wea,
input [ADDRESS_WIDTH - 1 :0] addra,
input [DATA_WIDTH - 1:0] dina,
input clkb,
input [ADDRESS_WIDTH - 1:0] addrb,
output [DATA_WIDTH - 1:0] doutb
);
//Parameters
//Registers/Wires
reg [DATA_WIDTH - 1:0] mem [0:2 ** ADDRESS_WIDTH];
reg [DATA_WIDTH - 1:0] dout;
//Submodules
//Asynchronous Logic
assign doutb = dout;
//Synchronous Logic
//write only on the A side
`ifdef SIMULATION
//Only initialize in simulation... somthing gets fucked when you try and do it on an FPGA
integer i;
initial begin
i = 0;
for (i = 0; i < (2 ** ADDRESS_WIDTH); i = i + 1) begin
mem[i] <= 0;
end
end
`endif
always @ (posedge clka)
begin
if ( wea ) begin
mem[addra] <= dina;
end
end
//read only on the b side
always @ (posedge clkb)
begin
dout <= mem[addrb];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2013; char p[1 << 20], s[205]; int k, n, m; int main() { gets(p); gets(s); cin >> k; n = strlen(p); m = strlen(s); string minLex; for (int i = 1; i <= k + 1; ++i) minLex += 1 ; int rboud = min(m, k), cntIn = n / k, R = n % k; for (int d = 1; d <= rboud && cntIn * d <= m; ++d) { string cans; for (int i = 1; i <= k; ++i) cans += 0 ; { int r = d - 1, i = min(n - 1, k - 1); for (; i >= 0 && r >= 0; --i) { int l1 = m / d + (r < m % d); int l2 = cntIn + (i < R); if (l1 != l2) continue; bool diff = false; for (int e = 0; e < l1 && !diff; ++e) diff = s[r + e * d] != p[i + e * k]; if (diff) continue; cans[i] = 1 ; --r; } if (r == -1) minLex = min(minLex, cans); } } if (minLex.size() > k) cout << 0; else cout << minLex; return 0; }
|
#include <bits/stdc++.h> using namespace std; signed long long n, m, answer; signed long long calc(signed long long n, signed long long m) { signed long long answer; if (m - n >= 1) { answer = n; } else { answer = m + (signed long long)ceil((sqrt(1.0L + 8.0L * (n - m)) - 1.0L) / 2.0L); } return answer; } int main() { cin >> n >> m; cout << calc(n, m); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
end
endmodule
|
module top(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
localparam NUM_FF = 4;
localparam FF_TYPE = "FDRE";
assign tx = rx;
// Generate some signals for the CE and reset lines.
wire ce = sw[14];
wire reset = sw[15];
wire [(4*NUM_FF)-1:0] Q;
wire [(4*NUM_FF)-1:0] D;
reg rst = 1;
always @(posedge clk) begin
rst <= 0;
end
assign led[0] = Q[0];
assign led[1] = Q[1];
assign led[2] = Q[2];
assign led[3] = Q[3];
assign led[4] = Q[4];
assign led[5] = Q[4*(NUM_FF-1)+0];
assign led[6] = Q[4*(NUM_FF-1)+1];
assign led[7] = Q[4*(NUM_FF-1)+2];
assign led[8] = Q[4*(NUM_FF-1)+3];
assign led[9] = ^Q;
assign led[10] = |Q;
assign led[11] = &Q;
assign led[12] = ^sw;
assign led[13] = |sw;
assign led[14] = &sw;
assign led[15] = sw[15];
genvar i;
// 4 FF's of each SR/CE varient to check packing behavior.
generate for(i = 0; i < NUM_FF; i=i+1) begin:ff
assign D[4*i+0] = sw[(4*i+0) % 14];
assign D[4*i+1] = sw[(4*i+1) % 14];
assign D[4*i+2] = sw[(4*i+2) % 14];
assign D[4*i+3] = sw[(4*i+3) % 14];
// Tie SR to GND and CE to VCC
(* keep *) FF #(
.INIT(1'b0),
.FF_TYPE(FF_TYPE)
) vcc_gnd (
.Q(Q[4*i+0]),
.C(clk),
.D(D[4*i+0]),
.CE(1'b1),
.SR(1'b0)
);
// Tie SR to GND and CE to signal
(* keep *) FF #(
.INIT(1'b0),
.FF_TYPE(FF_TYPE)
) s_gnd (
.Q(Q[4*i+1]),
.C(clk),
.D(D[4*i+1]),
.CE(ce),
.SR(1'b0)
);
// Tie SR to signal and CE to signal
(* keep *) FF #(
.INIT(1'b0),
.FF_TYPE(FF_TYPE)
) s_s (
.Q(Q[4*i+2]),
.C(clk),
.D(D[4*i+2]),
.CE(ce),
.SR(reset)
);
// Tie SR to signal and CE to VCC
(* keep *) FF #(
.INIT(0),
.FF_TYPE(FF_TYPE)
) vcc_s (
.Q(Q[4*i+3]),
.C(clk),
.D(D[4*i+3]),
.CE(1'b1),
.SR(reset)
);
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 503; int m, n, vis[N][N]; vector<int> adj[N * N]; void init() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int id(int x, int y) { return (x - 1) * n + y; } struct ds { char c; int x, y; }; vector<ds> V; void print(int u, int cc, int type = -1) { int x = (u - 1) / n + 1, y = u - (x - 1) * n; if (adj[u].size() == 0 && !type) { V.push_back((ds){ R , x, y}); return; } V.push_back((ds){ B , x, y}); for (int v : adj[u]) print(v, cc, 0); if (!type) V.push_back((ds){ D , x, y}), V.push_back((ds){ R , x, y}); } int cc = 0; queue<pair<int, int> > Q; int hang[4] = {0, 0, 1, -1}; int cot[4] = {1, -1, 0, 0}; void build(int orgx, int orgy, int cc) { vis[orgx][orgy] = cc; Q.push({orgx, orgy}); while (Q.size()) { int x = Q.front().first, y = Q.front().second; Q.pop(); for (int t = 0; t <= (int)3; ++t) { int nx = x + hang[t], ny = y + cot[t]; if (nx < 1 || nx > m || ny < 1 || ny > n || vis[nx][ny]) continue; adj[id(x, y)].push_back(id(nx, ny)); vis[nx][ny] = cc; Q.push({nx, ny}); } } print(id(orgx, orgy), cc); } void solve() { cin >> m >> n; for (int i = 1; i <= (int)m; ++i) for (int j = 1; j <= (int)n; ++j) { char c; cin >> c; if (c == # ) vis[i][j] = -1; } for (int i = 1; i <= (int)m; ++i) for (int j = 1; j <= (int)n; ++j) if (!vis[i][j]) build(i, j, ++cc); cout << V.size() << n ; for (ds it : V) cout << it.c << << it.x << << it.y << n ; } int main() { init(); solve(); }
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#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 10; long long n, m; long long res[N], sum[N], a[N]; long long len; struct Node { int x, p, id; } Q[N]; inline long long read() { long long x = 0, f = 0; char ch; while (((ch = getchar()) < 0 || ch > 9 ) && (ch != - )) ; while (!isdigit(ch)) f |= ch == - , ch = getchar(); while (isdigit(ch)) x = x * 10 + (ch ^ 48), ch = getchar(); return f ? -x : x; } inline bool cmp(Node a, Node b) { return a.p != b.p ? a.p < b.p : a.x > b.x; } signed main() { n = read(); len = sqrt(n); for (long long i = 1; i <= n; i++) a[i] = read(); m = read(); for (int i = 1; i <= m; i++) { long long x, p; x = read(), p = read(); Q[i].x = x, Q[i].p = p; Q[i].id = i; } sort(Q + 1, Q + m + 1, cmp); int last = n; for (int i = 1; i <= m; i++) { long long ans = 0; if (Q[i].p >= len) { for (int j = Q[i].x; j <= n; j += Q[i].p) { ans += a[j]; } } else { int p = Q[i].p, x = Q[i].x; if (Q[i].p != Q[i - 1].p) last = n; for (int j = last; j >= x; j--) { sum[j] = a[j]; if (j + p <= n) sum[j] += sum[j + p]; } last = x - 1; ans = sum[x]; } res[Q[i].id] = ans; } for (int i = 1; i <= m; i++) printf( %lld n , res[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long P = 998244353LL; const int N_MAX = 1e5 + 15; int A[N_MAX]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> A[i]; long long ans = 0LL; bool rem = 1; long long q = 1LL; while (rem) { long long t = 0LL; for (int i = 0; i < n; i++) { t += (1LL * (A[i] % 10)); A[i] /= 10; if (A[i] == 0) rem = 0; } t *= q; t %= P; q *= 100LL; q %= P; ans += t; ans %= P; } ans *= 11LL; ans %= P; ans *= n; ans %= P; cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int d1[5], c1[5], d2[5], c2[5]; int min2[5], min1[5]; int main() { int n; cin >> n; for (int i = 1; i <= 4; i++) { cin >> c1[i] >> d1[i] >> c2[i] >> d2[i]; min1[i] = min(c1[i], d1[i]); min2[i] = min(c2[i], d2[i]); } int tmp = 1e9; int it; for (int i = 1; i <= 4; i++) if (min1[i] + min2[i] < tmp) { tmp = min1[i] + min2[i]; it = i; } if (tmp > n) cout << -1; else cout << it << << min1[it] << << n - min1[it]; return 0; }
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