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#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e5 + 1, maxs = 21; int n, m, q, stot, etot, que[maxn], rnk[maxn]; long long bit[maxn], ans[maxn]; struct Point { int x, y; void read() { scanf( %d%d , &x, &y); } bool operator<(Point const &t) const { return x < t.x || (x == t.x && y < t.y); } Point operator-(Point const &t) const { return (Point){x - t.x, y - t.y}; } Point operator+(Point const &t) const { return (Point){x + t.x, y + t.y}; } Point operator*(int const &t) const { return (Point){x * t, y * t}; } long long det(Point const &t) const { return (long long)x * t.y - (long long)y * t.x; } } stk[maxs], vec; pair<Point, int> a[maxn], b[maxn]; Point p[maxn << 1 | 1]; struct Event { int typ, idx; long long dis; bool operator<(Event const &t) const { return dis < t.dis || (dis == t.dis && typ < t.typ); } } eve[maxn << 2 | 1]; int main() { scanf( %d%d%d , &m, &n, &q); stk[stot++] = (Point){0, 0}; while (m--) { vec.read(); for (int i = 0; i < stot; ++i) { stk[stot + i] = stk[i] + vec; stk[i] = stk[i] - vec; } sort(stk, stk + stot + stot); int sz = 0; for (int i = 0; i < stot + stot; ++i) { for (; sz > 1 && (stk[sz - 1] - stk[sz - 2]).det(stk[i] - stk[sz - 2]) <= 0; --sz) ; stk[sz++] = stk[i]; } stot = sz; } stot -= stot > 1 && !(stk[stot - 1] - stk[stot - 2]).x; for (int i = 0; i < n; ++i) { a[i].first.read(); scanf( %d , &a[i].second); que[i] = a[i].first.x; } sort(que, que + n); m = unique(que, que + n) - que; for (int i = 0; i < n; ++i) rnk[i] = lower_bound(que, que + m, a[i].first.x) - que + 1; for (int i = 0; i < q; ++i) { b[i].first.read(); scanf( %d , &b[i].second); } for (int i = 0; i + 1 < stot; ++i) { vec = stk[i + 1] - stk[i]; etot = 0; for (int j = 0; j < n; ++j) eve[etot++] = (Event){0, j, vec.det(a[j].first)}; for (int j = 0; j < q; ++j) { p[j << 1] = b[j].first + stk[i] * b[j].second; eve[etot++] = (Event){-1, j << 1, vec.det(p[j << 1])}; p[j << 1 | 1] = b[j].first - stk[i + 1] * b[j].second; eve[etot++] = (Event){1, j << 1 | 1, vec.det(p[j << 1 | 1])}; } sort(eve, eve + etot); memset(bit + 1, 0, m * sizeof(long long)); auto bit_upd = [&](int x, int v) { for (; x <= m; x += x & -x) bit[x] += v; }; auto bit_sum = [&](int x) { long long ret = 0; for (; x > 0; x -= x & -x) ret += bit[x]; return ret; }; for (int j = 0; j < etot; ++j) { int idx = eve[j].idx; if (!eve[j].typ) { bit_upd(rnk[idx], a[idx].second); } else { Point lft = p[idx], rht = lft + vec * b[idx >> 1].second; lft.x += eve[j].typ < 0 && i > 0 || eve[j].typ > 0 && i + 2 < stot; int L = lower_bound(que, que + m, lft.x) - que + 1; int R = upper_bound(que, que + m, rht.x) - que; long long las = ans[idx >> 1]; ans[idx >> 1] += eve[j].typ * (bit_sum(R) - bit_sum(L - 1)); las = ans[idx >> 1] - las; } } } for (int i = 0; i < q; ++i) printf( %lld n , ans[i]); return 0; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stratix_pmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module stratix_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.byteena_aclr_a = "NONE",
altsyncram_component.byte_size = 8,
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.wrcontrol_aclr_a = "NONE";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: BYTEENA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix_pmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, l, k, ultim; map<int, int> cnt; int main() { cin >> n >> k; for (int i = 0; i <= 63; i++) if ((n >> i) & 1) cnt[i]++, l++; if (l > k) { cout << No ; return 0; } for (int i = 63; i >= -63; i--) { if (l + cnt[i] <= k) l += cnt[i], cnt[i - 1] += cnt[i] * 2, cnt[i] = 0; else break; } multiset<int> ms; multiset<int>::iterator it; for (int i = 63; i >= -63; i--) for (int j = 0; j < cnt[i]; j++) ms.insert(i); while (ms.size() < k) { it = ms.begin(); int u = *it; ms.erase(it); ms.insert(u - 1); ms.insert(u - 1); } cout << Yes n ; for (auto it = ms.rbegin(); it != ms.rend(); it++) { cout << *it << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int x, i; int a[100]; while (cin >> x && x) { if (x == 1) { cout << x << endl; } else { cout << x << ; for (i = 1; i < x; i++) cout << i << ; cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long power(long long base, long long e) { long long answer = 1; while (e) { if (e % 2 == 1) { answer *= base; } base *= base; e /= 2; } return answer; } int main() { long long i, n, m, k, j; cin >> n >> m; string s[n]; for (i = 0; i < n; i++) { cin >> s[i]; } long long a[m]; for (i = 0; i < m; i++) { cin >> a[i]; } long long sum = 0; for (i = 0; i < m; i++) { long long f[5] = {0}; for (j = 0; j < n; j++) { f[s[j][i] - A ]++; } long long max = f[0]; for (j = 1; j < 5; j++) { if (max <= f[j]) max = f[j]; } sum += (max * a[i]); } cout << sum; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_1_V
`define SKY130_FD_SC_MS__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_TB_V
`define SKY130_FD_SC_HS__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hs__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31A_1_V
`define SKY130_FD_SC_HS__O31A_1_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31a_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_2_V
`define SKY130_FD_SC_LS__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_2_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 1e3 + 10; long long dis[N][N][4]; int dx[] = {0, 0, -1, 1}; int dy[] = {1, -1, 0, 0}; char c[N][N]; queue<pair<int, int>> q[4]; int n, m; long long check(int o) { long long d[4] = {0, INF * INF, INF * INF, INF * INF}; while (!q[o].empty()) { int x, y; tie(x, y) = q[o].front(); q[o].pop(); if (isdigit(c[x][y])) { long long &oo = d[c[x][y] - 0 ]; oo = min(oo, dis[x][y][o]); } for (int i = 0; i < 4; i++) { int tx = x + dx[i]; int ty = y + dy[i]; if (tx < 0 || tx >= n) continue; if (ty < 0 || ty >= m) continue; if (c[tx][ty] == # ) continue; if (dis[tx][ty][o] > dis[x][y][o] + 1) { dis[tx][ty][o] = dis[x][y][o] + 1; q[o].push({tx, ty}); } } } return min(INF, d[1] + d[2] + d[3] - 2); } int main() { cin >> n >> m; memset((dis), (0x1f), sizeof(dis)); for (int i = 0; i < n; i++) { cin >> c[i]; for (int j = 0; j < m; j++) { if (isdigit(c[i][j])) { q[c[i][j] - 0 ].push({i, j}); dis[i][j][c[i][j] - 0 ] = 0; } } } long long ans = min(check(1), min(check(2), check(3))); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (c[i][j] != . ) continue; ans = min(ans, dis[i][j][1] + dis[i][j][2] + dis[i][j][3] - 2); } } if (ans >= INF) ans = -1; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, ans = 1e9 + 1; string s; cin >> n >> s; vector<double> x(n); for (int i = 0; i < n; i++) { cin >> x[i]; } for (int i = 0; i < n; i++) { if (i < n + 1 && s[i] == R && s[i + 1] == L && (x[i + 1] - x[i]) / 2 < ans) { ans = (x[i + 1] - x[i]) / 2; } } if (ans == 1e9 + 1) { cout << -1; } else { cout << ans; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_2_V
`define SKY130_FD_SC_LP__DFXTP_2_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_2 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_2 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int test = 1; for (int loop = 0; loop < test; loop++) { long long int num, val; cin >> num >> val; vector<long long int> arr; long long int temp; for (int i = 0; i < num; i++) { cin >> temp; arr.push_back(temp); } long long int count = 0; for (int i = 0; i < num; i++) { for (int j = 0; j < num; j++) { if (abs(arr[i] - arr[j]) <= val && i != j) count++; } } cout << count << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, m, n, k, a[1100], b[1100][10], count = 0; cin >> n >> m >> k; for (i = 0; i <= m; i++) a[i] = 10000000; for (i = 1; i <= n; i++) { for (j = 0; j < 2; j++) cin >> b[i][j]; if (a[b[i][0]] > b[i][1]) a[b[i][0]] = b[i][1]; } for (i = 1; i <= m; i++) count += a[i]; if (count > k) cout << k << endl; else cout << count << endl; return 0; }
|
module decode(inst,
opndC, opndA, opndB,
arithmetic, slowArithmetic, logic, memory,
reg_bank_control, control, arith_cntl,
control_mask
);
// The instruction to be decoded
input [15:0] inst;
// The respective operands
output [3:0] opndC, opndA, opndB;
output [4:0] reg_bank_control;// Control signals for register_bank
output [2:0] control; // tells the 2op, logic inst what to do
output [2:0] arith_cntl;
// Tells which Functional Blocks to power on for this cycle
output reg arithmetic; // includes all add, sub, shift
output reg slowArithmetic; // includes signed/unsigned multiply, divide
output reg logic; // includes all or, and, xnor, not
output reg memory; // includes all memory operations
// tells which FFs to pass their values
output [2:0] control_mask;
// The operand decode is just an assignment
assign opndC = inst[11:08];
assign opndA = inst[07:04];
assign opndB = inst[03:00];
// top_op is a boolean that tells if the decoded instruction is
// one of the "top_op" instructions that are declared by inst[14:12]
// bot_op is a boolean that tells if the decoded instruction is
// one of the "bot_op" instructions that are declared by inst[3:1]
// A RSVD instruction will return false for both of these
wire top_op = (inst[14:12] != 3'b000);
wire bot_op = (inst[03:01] != 3'b000); // will also be true if op is a top_op
assign reg_bank_control[4] = (inst[14:13] == 2'b01);
assign reg_bank_control[3] = (inst[14:12] == 3'b001);
assign reg_bank_control[2] = (~top_op & (inst[3:1] == 3'b100));
assign reg_bank_control[1] = (~top_op & (inst[3:0] == 4'b1110));
assign reg_bank_control[0] = top_op | bot_op;
assign control = inst[2:0];
assign arith_cntl = (top_op) ? inst[14:12] : {2'b11, inst[0]};
wire [3:0] cmd_top = inst[14:12];
wire [3:0] cmd_bot = inst[3:1];
always @ (*) begin
if(top_op) begin
loadHex = (cmd_top[2:0] == 3'b001);
arithmetic = (cmd_top[2] ^ cmd_top[1]);
slowArithmetic = 1'b0;
logic = 1'b0;
memory = (cmd_top[2:1] == 2'b11);
move = 1'b0;
end else if(bot_op) begin
loadHex = 1'b0;
arithmetic = (cmd_bot[2:0] == 3'b001);
slowArithmetic = (cmd_bot[2:1] == 3'b01);
logic = ((cmd_bot[2] == 1'b1) & ~move); // #TODO might be incorrect
memory = 1'b0;s
move = (cmd_bot[1:0] == 2'b00);
end else begin
// This means that it is a RSVD operation
loadHex = 1'b0;
arithmetic = 1'b0;
slowArithmetic = 1'b0;
logic = 1'b0;
memory = 1'b0;
move = 1'b0;
end
end
assign control_mask = {logic, logic&slowArithmetic&memory, logic&slowArithmetic&move};
// #TODO This will need to be completely rewritten
// #TODO include r14 == 0 control conditional signal, do nothing if i15 == 1 & cntl_conditional == 0
endmodule
|
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
task registerTask;
input [17:0] signals;
//6 7 8 12 14 16
fork
//#2 set the alu signals
#2 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = {signals[17],1'b0,signals[15],1'b0,signals[13],1'b0,signals[11:9],1'b0,1'b0,1'b0,signals[5:0]};
//#4 set the register signals
#4 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
//#6 let data be saved
#6 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
join
endtask
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00000; end
else
State <= NextState;
always @ (State, MFC)
case (State)
5'b00000 : if(Reset) NextState = 5'b00000; else NextState = 5'b00001;
5'b00001 : NextState = 5'b00010;
5'b00010 : NextState = 5'b00011;
5'b00011 : NextState = 5'b00100;
5'b00100 : NextState = 5'b00101;
5'b00101 : NextState = 5'b00110;
5'b00110 : NextState = 5'b00111;
5'b00111 : NextState = 5'b01000;
5'b01000 : NextState = 5'b01001;
5'b01001 : NextState = 5'b01010;
5'b01010 : NextState = 5'b01011;
5'b01011 : NextState = 5'b01100;
5'b01100 : NextState = 5'b01101;
5'b01101 : NextState = 5'b01110;
5'b01110 : NextState = 5'b01111;
5'b01111 : NextState = 5'b10000;
5'b10000 : NextState = 5'b10001;
5'b10001 : NextState = 5'b00000;
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin opcode = 0; ALUSTORE = 1 ; end
5'b00001 : begin opcode = 1; ALUSTORE = 1 ; end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin opcode = 2; ALUSTORE = 1 ; end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin opcode = 3; ALUSTORE = 1 ; end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin opcode = 4; ALUSTORE = 1 ; end // transfer data to IR
5'b00101 : begin opcode = 5; ALUSTORE = 1 ; end // Check status codes
5'b00110 : begin opcode = 6; ALUSTORE = 1 ; end // Decode instruction type and set out signals
5'b00111 : begin opcode = 7; ALUSTORE = 1 ; end
5'b01000 : begin opcode = 8; ALUSTORE = 1 ; end
5'b01001 : begin opcode = 9; ALUSTORE = 1 ; end
5'b01010 : begin opcode = 10; ALUSTORE = 1 ; end
5'b01011 : begin opcode = 11; ALUSTORE = 1 ; end
5'b01100 : begin opcode = 12; ALUSTORE = 1 ; end
5'b01101 : begin opcode = 13; ALUSTORE = 1 ; end
5'b01110 : begin opcode = 14; ALUSTORE = 1 ; end
5'b01111 : begin opcode = 15; ALUSTORE = 1 ; end
5'b10000 : begin opcode = 16; ALUSTORE = 1 ; end
5'b10001 : begin opcode = 17; ALUSTORE = 1 ; end
/*branch and load_store instruction*/
default : begin end
endcase
endmodule
|
#include <bits/stdc++.h> int main() { int i, j, l = 0, a, A[6], n[6], m = 0; for (i = 0; i < 6; i++) { scanf( %d , &a); for (j = 0; j < l; j++) { if (A[j] == a) break; } if (j == l) { n[l] = 1; A[l++] = a; } else n[j]++; } for (i = 0; i < l; i++) { if (n[i] > m) m = n[i]; } if (l == 1 || (l == 2 && m == 4)) printf( Elephant ); else if ((l == 2 && m == 5) || (l == 3 && m == 4)) printf( Bear ); else printf( Alien ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long x, y; cin >> x >> y; cout << (x + x % 2) * (y + y % 2) * (x / 2) / 2 * (y / 2) / 2; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_1_V
`define SKY130_FD_SC_MS__O32A_1_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32a_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_2_V
`define SKY130_FD_SC_LS__DLRTP_2_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_2_V
|
// --------------------------------------------------------------------
// ng_SEQ.v - Sequence generator module
//
// Sequence generator module contains the stage registers and branch
// registers that (along with the time pulse generator) control
// execution of the microinstruction sequence.
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_SEQ(
input CLK2, // Clock Pulse 2
input [ 5:0] SELECT, // Select Input
input [100:0] CP, // Control Pulse
input [ 15:0] WRITE_BUS, // Control Pulse
output reg SNI, // SELECT NEXT INST 1=select next instruction (SNI register)
output reg STB_0,STB_1, // STAGE REG where STB_1 is MSB, STB_0 is LSB
output reg BR1,BR2, // BRANCH REG 1 where BR1 is MSB, BR2 is LSB
output reg [ 3:0] SQ, // INST REG where SQ_3 is MSB, SQ_0 is LSB
output LOOP6 // LOOPCNTR EQ 6 0=LOOPCNTR is holding the number 6.
);
// --------------------------------------------------------------------
// General Control Signals
// --------------------------------------------------------------------
wire GENRST = CP[`CPX(`GENRST)]; // General reset signal
wire WSQ = CP[`CPX(`WSQ) ]; // Write SQ
wire NISQ = CP[`CPX(`NISQ) ]; // New instruction to the SQ register
wire CLISQ = CP[`CPX(`CLISQ) ]; // Clear SNI
wire ST1 = CP[`CPX(`ST1) ]; // Stage 1
wire ST2 = CP[`CPX(`ST2) ]; // Stage 2
wire TRSM = CP[`CPX(`TRSM) ]; // Test for resume
wire CLSTA = CP[`CPX(`CLSTA) ]; // Clear state counter A (STA)
wire WSTB = CP[`CPX(`WSTB) ]; // Write stage counter B (STB)
wire CLSTB = CP[`CPX(`CLSTB) ]; // Clear state counter B
wire SETSTB = CP[`CPX(`SETSTB)]; // Set the ST1 bit of STB
wire TSGN = CP[`CPX(`TSGN) ]; // Test sign
wire TSGN2 = CP[`CPX(`TSGN2) ]; // Test sign 2
wire TOV = CP[`CPX(`TOV) ]; // Test for overflow
wire TMZ = CP[`CPX(`TMZ) ]; // Test for minus zero
wire CTR = CP[`CPX(`CTR) ]; // Loop counter
wire CLCTR = CP[`CPX(`CLCTR) ]; // Clear loop counter
wire EQU_25 = SELECT[`SLX(`EQU_25)]; // Equal to Octal 25 signal
// --------------------------------------------------------------------
// Select Next instruction Logic
// --------------------------------------------------------------------
reg SNI1; // Instantiate internal SNI register
always@(posedge CLK2)
if(!GENRST) SNI1 <= 1'b0; // Reset condition, clear register
else if(!CLISQ) SNI1 <= 1'b0; // Signal to clear register
else if(!NISQ) SNI1 <= 1'b1; // Signal to set register
always@(negedge CLK2) SNI <= SNI1; // Transfer to outputs on negative edge
// --------------------------------------------------------------------
// Branch Register Logic
// --------------------------------------------------------------------
wire SQ_MZ = &WRITE_BUS; // All 1's is minus zero in 1's compliment
wire OVER = WRITE_BUS[14]; // bit 14 set is overflow condition
wire SIGN = WRITE_BUS[15]; // bit 15 set is negative number
reg [1:0] BR; // instantiate internal Branch register
wire SQ_BR1J = !(!(!TSGN & SIGN) & !(!TOV & SIGN & !OVER));
wire SQ_BR1K = !(!(!TSGN & !SIGN) & !(!TOV & !SIGN) & !(!TOV & OVER));
always@(posedge CLK2)
if(!GENRST) BR[0] <= 1'b0;
else BR[0] <= ~BR[0] & SQ_BR1J | BR[0] & ~SQ_BR1K;
always@(negedge CLK2) BR1 <= BR[0]; // Transfer to outputs on negative edge
wire SQ_BR2J = !(!(!TSGN2 & SIGN) & !(!TOV & !SIGN & OVER) & !(!TMZ & SQ_MZ));
wire SQ_BR2K = !(!(!TSGN2 & !SIGN) & !(!TOV & SIGN) & !(!TOV & !OVER) & !(!TMZ & !SQ_MZ));
always@(posedge CLK2)
if(!GENRST) BR[1] <= 1'b0;
else BR[1] <= ~BR[1] & SQ_BR2J | BR[1] & ~SQ_BR2K;
always@(negedge CLK2) BR2 <= BR[1]; // Transfer to outputs on negative edge
// --------------------------------------------------------------------
// Stage Register Logic
// --------------------------------------------------------------------
reg [1:0] STA; // instantiate stage A internal register
wire SET2 = !ST2 | (!TRSM & !EQU_25); // Conditions to set bit 1
always@(posedge CLK2) begin // Stage Register A behavior
if(!GENRST) STA <= 2'b00; // clear the register
else if(!CLSTA) STA <= 2'b00; // clear the register
else begin
if(!ST1) STA[0] <= 1'b1; // set bit 0
if(SET2) STA[1] <= 1'b1; // set bit 1
end
end
reg [1:0] STA_Q; // instantiate stage A output register
always@(negedge CLK2) STA_Q <= STA; // Transfer to outputs on negative edge
reg [1:0] STB; // instantiate stage B internal register
always@(posedge CLK2) begin // Stage Register B behavior
if(!GENRST) STB <= 2'b00; // clear the register
else if(!CLSTB) STB <= 2'b00; // clear the register
else if(!SETSTB) STB <= 2'b01; // set bit 0 and clear bit 1
else if(!WSTB) STB <= STA_Q; // Transfer stA to stB
end
always@(negedge CLK2) STB_0 <= STB[0]; // Transfer to outputs on negative edge
always@(negedge CLK2) STB_1 <= STB[1]; // Transfer to outputs on negative edge
// --------------------------------------------------------------------
// Seqence Counter Output Register
// --------------------------------------------------------------------
always @(posedge CLK2)
if(!GENRST) SQ <= 4'h0;
else if(!WSQ) SQ <= WRITE_BUS[15:12];
// --------------------------------------------------------------------
// Seqence Counter Logic, used to count to 6
// --------------------------------------------------------------------
reg [3:0] seq_cntr; // Counter register
always @(posedge CLK2)
if(!GENRST) seq_cntr <= 4'h0; // Clear register on reset
else if(!CLCTR) seq_cntr <= 4'h0; // Request load 0
else if(!CTR) seq_cntr <= seq_cntr + 4'd1; // Increment counter
assign LOOP6 = !(seq_cntr == 3'd6); // Loop on 6
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O32A_FUNCTIONAL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o32a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 or0_out ;
wire B1 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; inline long long int gcd(long long int ga, long long int gb) { if (!gb) return ga; return gcd(gb, ga % gb); } inline long long int lcm(long long int a, long long int b, long long int c) { long long int ans = a * b / gcd(a, b); return ans * c / gcd(ans, c); } int main() { long long int n; scanf( %lld , &n); if (n == 1) printf( 1 ); else if (n == 2) printf( 2 ); else if (n & 1) printf( %lld , n * (n - 1) * (n - 2)); else { long long int ans(1); for (int i = 1; i <= n; ++i) ans = max(ans, lcm(n, n - 1, i)); printf( %lld , max(ans, max((n - 1) * (n - 2) * (n - 3), n * (n - 1) * (n - 2) / 2))); } return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous <= in assignment.
//
module main;
reg globvar;
reg [3:0] var1;
reg error;
wire var2 = (var1 <= 4'h02);
initial
begin
error = 0;
var1 = 4'h0 ;
#1 ;
if(var2 !== 1'b1)
begin
$display("FAILED continuous <= logical op (1)");
error = 1;
end
#1 ;
var1 = 4'h2;
#1 ;
if(var2 !== 1'b1)
begin
$display("FAILED continuos <= logical op (2)");
error = 1;
end
#1 ;
var1 = 4'h4;
#1 ;
if(var2 !== 1'b0)
begin
$display("FAILED continuos <= logical op (3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
module ddr3_init_sm (rst, clk, init_done, init_start);
input wire rst;
input wire clk;
input wire init_done;
output reg init_start;
reg [7:0] init_dly_cnt;
parameter IDLE = 3'b000,
START_CNT = 3'b001,
WAITFOR_CNT = 3'b010,
INIT_DDR = 3'b011,
INIT_DONE = 3'b100;
reg [2:0] state, next;
always @(posedge clk or posedge rst)
if (rst) state <= IDLE;
else state <= next;
always @(state or init_done or init_dly_cnt) begin
next = 'bx;
case (state)
IDLE : next = START_CNT;
START_CNT : next = WAITFOR_CNT;
WAITFOR_CNT : if (init_dly_cnt == 8'h3c) next = INIT_DDR;
else next = WAITFOR_CNT;
INIT_DDR : if (init_done) next = INIT_DONE;
else next = INIT_DDR;
INIT_DONE : next = INIT_DONE;
endcase
end
always @(posedge clk or posedge rst)
if (rst) begin
init_start <= 1'b0;
end
else begin
init_start <= 1'b0;
case (next)
INIT_DDR: init_start <= 1'b1;
endcase
end
always @(posedge clk or posedge rst)
begin
if (rst) begin
init_dly_cnt <= 8'h00;
end else begin
init_dly_cnt <= init_dly_cnt + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double dist(double x1, double y1, double x2, double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } int main() { double r, x1, y1, x2, y2; cin >> r >> x1 >> y1 >> x2 >> y2; if (dist(x1, y1, x2, y2) >= r) { printf( %.12f %.12f %.12f n , x1, y1, r); } else if (x1 == x2 && y1 == y2) { double r1 = r / 2.0; double x3 = x1 - r1; double y3 = y1; printf( %.12f %.12f %.12f n , x3, y3, r1); } else { double r1 = (dist(x1, y1, x2, y2) + r) / 2.0; double d1 = dist(x1, y1, x2, y2); double d2 = r1 - d1; double alpha1 = d1 / (d1 + d2); double alpha2 = d2 / (d1 + d2); double x3 = (x1 - alpha2 * x2) / alpha1; double y3 = (y1 - alpha2 * y2) / alpha1; printf( %.12f %.12f %.12f n , x3, y3, r1); } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Analog Auxiliary SYSMON Input Output Buffer
// /___/ /\ Filename : IOBUF_ANALOG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_ANALOG #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer DRIVE = 12,
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter SLEW = "SLOW"
)(
output O,
inout IO,
input I,
input T
);
// define constants
localparam MODULE_NAME = "IOBUF_ANALOG";
// Parameter encodings and registers
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
localparam SLEW_FAST = 1;
localparam SLEW_SLOW = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IOBUF_ANALOG_dr.v"
`else
localparam [4:0] DRIVE_REG = DRIVE;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
localparam [32:1] SLEW_REG = SLEW;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire I_in;
wire T_in;
assign I_in = (I === 1'bz) || I; // rv 1
assign T_in = (T === 1'bz) || T; // rv 1
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DRIVE_REG < 2) || (DRIVE_REG > 24))) begin
$display("Error: [Unisim %s-101] DRIVE attribute is set to %d. Legal values for this attribute are 2 to 24. Instance: %m", MODULE_NAME, DRIVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SLEW_REG != "SLOW") &&
(SLEW_REG != "FAST"))) begin
$display("Error: [Unisim %s-109] SLEW attribute is set to %s. Legal values for this attribute are SLOW or FAST. Instance: %m", MODULE_NAME, SLEW_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign O = IO;
assign IO = ~T_in ? I_in : 1'bz;
specify
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int maxt = 1000000, maxn = maxt + 7; int h[7][7]; char s[5][maxn]; void output(int n) { for (int i = 1; i <= 4; i++) { for (int j = 1; j <= n; j++) printf( %c , s[i][j]); puts( ); } } bool DoIt_2(int I, int n, int tot) { for (int i = 1; i <= n; i++) if (s[2][i] != s[I][i]) tot--; if (tot < 0) return false; if (tot == 0) return true; if (tot % 2 == 1) return false; vector<int> A, B; A.clear(), B.clear(); for (int i = 1; i <= n; i++) if (s[2][i] == s[I][i]) { if (s[2][i] == a ) A.push_back(i); if (s[2][i] == b ) B.push_back(i); } for (int i = 0; i < min(A.size(), B.size()); i++) { int x = A[i], y = B[i]; tot -= 2; swap(s[I][x], s[I][y]); if (tot == 0) return true; } return false; } bool DoIt_3(int I, int n, int tot) { for (int i = 1; i <= n; i++) if (s[3][i] != s[I][i]) tot--; if (tot < 0) return false; if (tot == 0) return true; if (tot % 2 == 1) return false; vector<int> AA, AB, BA, BB; AA.clear(), AB.clear(), BA.clear(), BB.clear(); for (int i = 1; i <= n; i++) if (s[3][i] == s[I][i]) { if (s[2][i] == a && s[3][i] == a ) AA.push_back(i); if (s[2][i] == a && s[3][i] == b ) AB.push_back(i); if (s[2][i] == b && s[3][i] == a ) BA.push_back(i); if (s[2][i] == b && s[3][i] == b ) BB.push_back(i); } for (int i = 0; i < min(AA.size(), AB.size()); i++) { int x = AA[i], y = AB[i]; tot -= 2; swap(s[I][x], s[I][y]); if (tot == 0) return true; } for (int i = 0; i < min(BA.size(), BB.size()); i++) { int x = BA[i], y = BB[i]; tot -= 2; swap(s[I][x], s[I][y]); if (tot == 0) return true; } return false; } bool check(int n) { for (int i = 1; i <= 4; i++) for (int j = 1; j <= n; j++) s[i][j] = a ; for (int i = 2; i <= 4; i++) for (int j = 1; j <= h[1][i]; j++) s[i][j] = b ; for (int i = 3; i <= 4; i++) if (!DoIt_2(i, n, h[2][i])) return false; if (!DoIt_3(4, n, h[3][4])) return false; return true; } int main() { for (int i = 1; i <= 4; i++) for (int j = i + 1; j <= 4; j++) scanf( %d , &h[i][j]); int head = 1, tail = maxt; while (head <= tail) { int mid = (head + tail) / 2; if (check(mid)) tail = mid - 1; else head = mid + 1; } int n = tail + 1; if (n > maxt) { puts( -1 ); return 0; } printf( %d n , n); check(n); output(n); }
|
#include <bits/stdc++.h> const double eps = (1e-9); using namespace std; int dcmp(long double a, long double b) { return fabsl(a - b) <= eps ? 0 : (a > b) ? 1 : -1; } int getBit(int num, int idx) { return ((num >> idx) & 1) == 1; } int setBit1(int num, int idx) { return num | (1 << idx); } long long setBit0(long long num, int idx) { return num & ~(1ll << idx); } long long flipBit(int num, int idx) { return num ^ (1 << idx); } void FS() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int countNumBit1(int mask) { int ret = 0; while (mask) { mask &= (mask - 1); ++ret; } return ret; } const int N = 100009; int arr[N]; int main() { int n; cin >> n; int mx = -1; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] > mx) { mx = arr[i]; } } int mxlen = 1; int cnt = 0, str = -1, en = 0; for (int i = 0; i < n; i++) { if (arr[i] == mx) { if (str == -1) str = i; en = i; } else { if (str != -1) mxlen = max(mxlen, en - str + 1); str = -1; } } if (str != -1) mxlen = max(mxlen, en - str + 1); cout << mxlen << endl; }
|
#include <bits/stdc++.h> using namespace std; string s, t, x; vector<int> lcp; vector<bool> match; constexpr int mxn = int(2e5) + 10; int dp[mxn][3]; int pref[mxn]; const int mod = 1e9 + 7; int ans(int start) { if (dp[start][2] != -1) return dp[start][2]; if (start >= x.size()) return dp[start][0] = dp[start][1] = dp[start][2] = 0; if (match[start]) { dp[start][0] = dp[start][1] = 0; int st = start + t.size() - 1; int end = x.size() - 1; int cnt = end - st + 1; ans(st + 1); dp[start][0] += cnt; dp[start][0] %= mod; dp[start][0] += pref[st + 1]; dp[start][0] %= mod; dp[start][1] += ans(start + 1); dp[start][1] %= mod; dp[start][2] = (dp[start][0] + dp[start][1]) % mod; pref[start] = pref[start + 1] + dp[start][2]; pref[start] %= mod; return dp[start][2]; } int curr = start; while (curr < x.size() and not match[curr]) { curr++; } ans(curr); for (int i = curr - 1; i >= start; i--) { dp[i][0] = dp[curr][0]; dp[i][1] = dp[i + 1][2]; dp[i][2] = dp[i][0] + dp[i][1]; dp[i][2] %= mod; pref[i] = pref[i + 1] + dp[i][2]; pref[i] %= mod; } return dp[start][2]; } void solve() { cin >> s >> t; x = t + # + s; lcp = vector<int>(x.size()); match = vector<bool>(x.size()); lcp[0] = 0; for (int i = 1; i < x.size(); i++) { int j = lcp[i - 1]; while (j > 0 and x[j] != x[i]) j = lcp[j - 1]; if (x[j] == x[i]) j++; lcp[i] = j; if (lcp[i] == t.size()) { match[i - t.size() + 1] = true; } } cout << ans(t.size() + 1); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); memset(dp, -1, sizeof(dp)); memset(pref, 0, sizeof(pref)); solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, mid, rt, res, a[200010], f[200010], sz[200010]; vector<int> e[200010]; void dfs(int u, int fa) { f[u] = sz[u] = 1; int m1 = 0, m2 = 0; for (auto v : e[u]) { if (v == fa) continue; dfs(v, u); sz[u] += sz[v]; if (f[v] == sz[v]) f[u] += f[v]; else { if (f[v] > m1) swap(f[v], m1); if (f[v] > m2) swap(f[v], m2); } } f[u] = a[u] < mid ? 0 : f[u] + m1; res = max(res, f[u] + m2); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); e[u].push_back(v); e[v].push_back(u); } rt = min_element(a + 1, a + 1 + n) - a; int l = 0, r = 1000010, ans; while (l <= r) { mid = (l + r) >> 1; res = 0; dfs(rt, 0); if (res >= m) l = mid + 1, ans = mid; else r = mid - 1; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int tc = 0; long long a, b, c, d; inline long long sum(long long i) { return -a * i + b * (d - 1) * i + i * (i - 1) / 2 * b * d; } inline long long calc(long long i) { if (i < 0) return 0; long long ans = 0; if (i < (c + 1) / d) { ans = min(ans, sum(i) - a + i * b); } else { i = (c + 1) / d; ans = min(ans, sum(i) - a + (i - 1) * b + (c + 1 % d > 0) * b); ans = min(ans, sum(i)); ans = min(ans, -a); } return ans; } inline void solve() { ++tc; scanf( %lld%lld%lld%lld , &a, &b, &c, &d); if (c < d) { if (b * c >= a) printf( %lld n , a); else puts( -1 ); } else { long long i = floor(-(-a + b * (d - 1) + b - 1.0 * b * d / 2) / (b * d)); i = max(i, 0ll); long long dmg = (-a + b * (d - 1) + b * d * ((c + 1) / d - 1) + ((c + 1) % d) * b); long long ans = 0; if (dmg < 0) { puts( -1 ); } else { ans = min(ans, calc(i - 1)); ans = min(ans, calc(i)); ans = min(ans, calc(i + 1)); ans = min(ans, calc(i + 2)); printf( %lld n , -ans); } } return; } int main() { int T; for (scanf( %d , &T); T--; solve()) ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned int n, m, l; cin >> n >> m >> l; int s = 0; while (l--) { s += 2 * (n + m - 2); n -= 4; m -= 4; } cout << s; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file instrmem.v when simulating
// the core, instrmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module instrmem(
clka,
addra,
douta
);
input clka;
input [9 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("instrmem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int k, rt, i, j; char a[] = { a , e , i , o , u }; cin >> k; rt = (int)sqrt(k); for (; k % rt != 0; rt--) ; if (rt > 4) { for (i = 0; i != k / rt; i++) { for (j = 0; j != rt; j++) { cout << a[(i + j) % 5]; } } } else cout << -1 ; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:52:19 03/03/2014
// Design Name:
// Module Name: flash_spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module flash_and_sd (
input wire clk, //
input wire [15:0] a, //
input wire iorq_n, // Señales de control de E/S estándar
input wire rd_n, // para manejar los puertos ZXMMC y DIVMMC
input wire wr_n, //
input wire [7:0] addr, // numero de registro almacenado en puerto ZXUNOADDR. Este módulo atiende a $02 y $03
input wire ior, // lectura a un registro ZXUNO
input wire iow, // escritura a un registro ZXUNO
input wire [7:0] din, // del bus de datos de salida de la CPU
output wire [7:0] dout, // al bus de datos de entrada de la CPU
output wire oe_n, // el dato en dout es válido
output wire wait_n, // pausa para la CPU. Mejora estabilidad
input wire in_boot_mode,// Esta interfaz sólo es válida en modo boot
output wire flash_cs_n, //
output wire flash_clk, // Interface SPI con la Flash
output wire flash_di, //
input wire flash_do, //
input wire disable_spisd,
output wire sd_cs_n, //
output wire sd_clk, // Interface SPI con la SD/MMC
output wire sd_mosi, // (de momento, solo puertos ZXMMC)
input wire sd_miso //
);
wire sclk,miso,mosi;
parameter
CSPIN = 8'h03, // bit 0: estado/control de la señal FLASH_CS
SPIPORT = 8'h02, // registro de lectura/escritura SPI
SDCS = 8'h1F, //
SDSPI = 8'h3F, // Puertos de la ZXMMC
DIVCS = 8'he7, //
DIVSPI = 8'heb; // Puertos del DIVMMC
reg flashpincs = 1'b1;
assign flash_cs_n = flashpincs;
reg sdpincs = 1'b1;
assign sd_cs_n = sdpincs;
assign flash_clk = sclk;
assign flash_di = mosi;
assign sd_clk = sclk;
assign sd_mosi = mosi;
assign miso = (sd_cs_n == 1'b0)? sd_miso : flash_do;
// Control del pin CS de la flash y de la SD
always @(posedge clk) begin
if (addr == CSPIN && iow && in_boot_mode) begin
flashpincs <= din[0];
sdpincs <= 1'b1; // si accedemos a la flash para cambiar su estado CS, automaticamente deshabilitamos la SD
end
else if (!disable_spisd && !iorq_n && (a[7:0]==SDCS || a[7:0]==DIVCS) && !wr_n) begin
sdpincs <= din[0];
flashpincs <= 1'b1; // y lo mismo hacemos si es la SD a la que estamos accediendo
end
end
// Control del modulo SPI
reg enviar_dato;
reg recibir_dato;
always @* begin
if ((addr==SPIPORT && ior && in_boot_mode) || (!disable_spisd && !iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !rd_n))
recibir_dato = 1'b1;
else
recibir_dato = 1'b0;
if ((addr==SPIPORT && iow && in_boot_mode) || (!disable_spisd && !iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !wr_n))
enviar_dato = 1'b1;
else
enviar_dato = 1'b0;
end
// Instanciación del modulo SPI
spi mi_spi (
.clk(clk),
.enviar_dato(enviar_dato),
.recibir_dato(recibir_dato),
.din(din),
.dout(dout),
.oe_n(oe_n),
.wait_n(wait_n),
.spi_clk(sclk),
.spi_di(mosi),
.spi_do(miso)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O211A_PP_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int h1, t1, h2, t2, ansh, anst; scanf( %2d:%2d , &h1, &t1); scanf( %2d:%2d , &h2, &t2); if (t1 < t2) { h1--, t1 += 60; } anst = t1 - t2; ansh = h1 - h2; if (ansh < 0) ansh += 24; printf( %02d:%02d n , ansh, anst); return 0; }
|
//
// Copyright 2014-2015 Ettus Research LLC
//
module noc_block_synthese #(
parameter NOC_ID = 64'h11F5_0000_0000_0000,
parameter STR_SINK_FIFOSIZE = 11)
(
input bus_clk, input bus_rst,
input ce_clk, input ce_rst,
input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
output [63:0] debug,
output [31:0] t_loop_data_out
);
////////////////////////////////////////////////////////////
//
// RFNoC Shell
//
////////////////////////////////////////////////////////////
wire [31:0] set_data;
wire [7:0] set_addr;
wire set_stb;
wire [63:0] cmdout_tdata, ackin_tdata;
wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready;
wire [63:0] str_sink_tdata, str_src_tdata;
wire str_sink_tlast, str_sink_tvalid, str_sink_tready, str_src_tlast, str_src_tvalid, str_src_tready;
wire clear_tx_seqnum;
noc_shell #(
.NOC_ID(NOC_ID),
.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE))
inst_noc_shell (
.bus_clk(bus_clk), .bus_rst(bus_rst),
.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
// Computer Engine Clock Domain
.clk(ce_clk), .reset(ce_rst),
// Control Sink
.set_data(set_data), .set_addr(set_addr), .set_stb(set_stb), .rb_data(64'd0),
// Control Source
.cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
.ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready),
// Stream Sink
.str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready),
// Stream Source
.str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready),
.clear_tx_seqnum(clear_tx_seqnum),
.debug(debug));
////////////////////////////////////////////////////////////
//
// AXI Wrapper
// Convert RFNoC Shell interface into AXI stream interface
//
////////////////////////////////////////////////////////////
wire [31:0] m_axis_data_tdata;
wire m_axis_data_tlast;
wire m_axis_data_tvalid;
wire m_axis_data_tready;
wire [31:0] s_axis_data_tdata;
wire s_axis_data_tlast;
wire s_axis_data_tvalid;
wire s_axis_data_tready;
localparam AXI_WRAPPER_BASE = 128;
localparam SR_NEXT_DST = AXI_WRAPPER_BASE;
// Set next destination in chain
wire [15:0] next_dst;
setting_reg #(
.my_addr(SR_NEXT_DST), .width(16))
sr_next_dst(
.clk(ce_clk), .rst(ce_rst),
.strobe(set_stb), .addr(set_addr), .in(set_data), .out(next_dst), .changed());
axi_wrapper
inst_axi_wrapper (
.clk(ce_clk), .reset(ce_rst),
.clear_tx_seqnum(clear_tx_seqnum),
.next_dst(next_dst),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.i_tdata(str_sink_tdata), .i_tlast(str_sink_tlast), .i_tvalid(str_sink_tvalid), .i_tready(str_sink_tready),
.o_tdata(str_src_tdata), .o_tlast(str_src_tlast), .o_tvalid(str_src_tvalid), .o_tready(str_src_tready),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.m_axis_config_tdata(),
.m_axis_config_tlast(),
.m_axis_config_tvalid(),
.m_axis_config_tready());
////////////////////////////////////////////////////////////
//
// User code
//
////////////////////////////////////////////////////////////
// Control Source Unused
assign cmdout_tdata = 64'd0;
assign cmdout_tlast = 1'b0;
assign cmdout_tvalid = 1'b0;
assign ackin_tready = 1'b1;
synthese sysgen_dut (
.clk(ce_clk),
.reset_in(ce_rst),
//
.set_addr_in(set_addr),
.set_data_in(set_data),
.set_stb_in(set_stb),
//
.ready_in(m_axis_data_tready),
.last_in(m_axis_data_tlast),
.valid_in(m_axis_data_tvalid),
.data_in(m_axis_data_tdata),
//
.ready_out(s_axis_data_tready),
.valid_out(s_axis_data_tvalid),
.last_out(s_axis_data_tlast),
.data_out(s_axis_data_tdata)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500010; struct E { int u, v, w, I; } e[N]; int n, m, F[N], T[N], q, k, a[N], A[N], V, d, L[N], C[N]; vector<int> G[N]; bool M(E a, E b) { return a.w < b.w; } int P(int x) { return x == A[x] ? x : A[x] = P(A[x]); } void D(int b, int x) { if (L[x] == b) return; L[x] = b; V++; d += G[x].size(); for (int J = 0; J < G[x].size(); J++) D(b, G[x][J]); } bool K(int b, int x) { V = d = 0; D(b, x); return d == 2 * (V - 1); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &e[i].u, &e[i].v, &e[i].w); e[i].I = i; F[i] = e[i].u; T[i] = e[i].v; } for (int i = 1; i <= n; i++) A[i] = i; sort(e + 1, e + m + 1, M); for (int i = 1; i <= m; i++) { int o = i; while (e[o].w == e[i].w && o <= m) { int u = P(e[o].u), v = P(e[o].v); F[e[o].I] = u; T[e[o].I] = v; C[e[o].I] = u != v; o++; } for (; i < o; i++) A[P(e[i].u)] = P(e[i].v); i--; } scanf( %d , &q); for (int c = 1; c <= q; c++) { scanf( %d , &k); bool Y = 1; for (int i = 1; i <= k; i++) { scanf( %d , &a[i]); if (!C[a[i]]) Y = 0; G[F[a[i]]].clear(); G[T[a[i]]].clear(); } for (int i = 1; i <= k; i++) G[F[a[i]]].push_back(T[a[i]]), G[T[a[i]]].push_back(F[a[i]]); for (int i = 1; i <= k; i++) { int x = F[a[i]], y = T[a[i]]; if (L[x] != c) Y &= K(c, x); if (L[y] != c) Y &= K(c, y); } puts(Y ? YES : NO ); } return 0; }
|
#include <bits/stdc++.h> int Pos(int a) { if (a < 0) { return 0; } return a; } int main() { int n = 0, p1 = 0, t1 = 0, p2 = 0, t2 = 0, p3 = 0; int energy = 0; std::vector<int> timeDatal; std::vector<int> timeDatar; std::cin >> n >> p1 >> p2 >> p3 >> t1 >> t2; for (int i = 0; i < n; i++) { int input; std::cin >> input; timeDatal.push_back(input); std::cin >> input; timeDatar.push_back(input); energy += p1 * (timeDatar[i] - timeDatal[i]); if (i != 0) { int delta = timeDatal[i] - timeDatar[i - 1]; if (delta - t1 >= 0) { energy += t1 * p1; } else if (delta >= 0) { energy += delta * p1; } delta -= t1; if (delta - t2 >= 0) { energy += t2 * p2; } else if (delta >= 0) { energy += delta * p2; } delta -= t2; if (delta > 0) { energy += p3 * delta; } } } std::cout << energy; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dds data to samples conversion
module cf_ddsv (
// vdma interface
vdma_clk,
vdma_fs,
vdma_valid,
vdma_data,
vdma_ready,
vdma_ovf,
vdma_unf,
// dac interface
dac_div3_clk,
dds_master_enable,
// I data (0 is transmitted first)
dds_data_00,
dds_data_01,
dds_data_02,
// Q data (0 is transmitted first)
dds_data_10,
dds_data_11,
dds_data_12,
// 2's compl (0x0) or offset-bin (0x1)
dds_format_n,
// interpolation controls
up_intp_enable,
up_intp_scale_a,
up_intp_scale_b,
up_vdma_fscnt,
// debug data (chipscope)
vdma_dbg_data,
vdma_dbg_trigger,
// debug data (chipscope)
dac_dbg_data,
dac_dbg_trigger);
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_ovf;
output vdma_unf;
// dac interface
input dac_div3_clk;
input dds_master_enable;
// I data (0 is transmitted first)
output [15:0] dds_data_00;
output [15:0] dds_data_01;
output [15:0] dds_data_02;
// Q data (0 is transmitted first)
output [15:0] dds_data_10;
output [15:0] dds_data_11;
output [15:0] dds_data_12;
// 2's compl (0x0) or offset-bin (0x1)
input dds_format_n;
// interpolation controls
input up_intp_enable;
input [15:0] up_intp_scale_a;
input [15:0] up_intp_scale_b;
input [15:0] up_vdma_fscnt;
// debug data (chipscope)
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
// debug data (chipscope)
output [195:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
wire dds_rd_s;
wire [95:0] dds_rdata_s;
// interpolator
cf_ddsv_intp i_ddsv_intp (
.dac_div3_clk (dac_div3_clk),
.dds_rd (dds_rd_s),
.dds_rdata (dds_rdata_s),
.dds_data_00 (dds_data_00),
.dds_data_01 (dds_data_01),
.dds_data_02 (dds_data_02),
.dds_data_10 (dds_data_10),
.dds_data_11 (dds_data_11),
.dds_data_12 (dds_data_12),
.dds_format_n (dds_format_n),
.up_intp_enable (up_intp_enable),
.up_intp_scale_a (up_intp_scale_a),
.up_intp_scale_b (up_intp_scale_b),
.dac_dbg_data (dac_dbg_data),
.dac_dbg_trigger (dac_dbg_trigger));
// vdma read interface
cf_ddsv_vdma i_ddsv_vdma (
.vdma_clk (vdma_clk),
.vdma_fs (vdma_fs),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf),
.vdma_unf (vdma_unf),
.dac_div3_clk (dac_div3_clk),
.dds_master_enable (dds_master_enable),
.dds_rd (dds_rd_s),
.dds_rdata (dds_rdata_s),
.up_vdma_fscnt (up_vdma_fscnt),
.vdma_dbg_data (vdma_dbg_data),
.vdma_dbg_trigger (vdma_dbg_trigger),
.dac_dbg_data (),
.dac_dbg_trigger ());
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10, OO = 0x3f3f3f3f; int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; int tc, n, m; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> tc; while (tc--) { cin >> n >> m; cin >> s; vector<long long> freq(n + 1, 0); vector<int> indx(m); for (int i = 0; i < int(m); i++) { cin >> indx[i]; freq[0]++; freq[indx[i]]--; } freq[0]++; for (int i = int(1); i <= int(n - 1); i++) freq[i] += freq[i - 1]; vector<long long> karakter(26, 0); for (int i = 0; i < int(n); i++) karakter[s[i] - a ] += freq[i]; for (int i = 0; i < int(26); i++) cout << karakter[i] << ; cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e6 + 3; const int INFI = 1e9 * 2; const long long LINFI = 1e17; const double pi = acos(-1.0); const int N = 111; const int M = 11; const int move[8][2] = {1, 0, -1, 0, 0, 1, 0, -1, 1, 1, 1, -1, -1, 1, -1, -1}; double mabs(double x) { return x > 0 ? x : -x; } int main() { int n; while (scanf( %d , &n) != EOF) { if (n == 1) printf( a na nb nb n ); else { if (n & 1) { n--; for (int i = 0; i < n; i++) putchar((i & 2) ? a : b ); puts( c ); for (int i = 0; i < n; i++) putchar((i & 2) ? d : e ); puts( c ); putchar( f ); for (int i = 0; i < n; i++) putchar((i & 2) ? g : h ); printf( n ); putchar( f ); for (int i = 0; i < n; i++) putchar((i & 2) ? i : j ); printf( n ); } else { for (int i = 0; i < n; i++) putchar((i & 2) ? a : b ); printf( n ); for (int i = 0; i < n; i++) putchar((i & 2) ? c : d ); printf( n ); n -= 2; putchar( e ); for (int i = 0; i < n; i++) putchar((i & 2) ? f : g ); puts( h ); putchar( e ); for (int i = 0; i < n; i++) putchar((i & 2) ? i : j ); puts( h ); } } } return 0; }
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#include <bits/stdc++.h> using namespace std; template <class t> t mag(t a) { return a > 0 ? a : -a; } template <class T, class U> T cdiv(T num, U den) { return (num / den) + ((num % den) > 0); } std::ifstream term( /dev/tty ); std::string tempstring; using ll = int_fast64_t; using ii = pair<int, int>; using vi = vector<int>; using vl = vector<ll>; using vii = vector<ii>; const int &sij = 400010; const ll &mod = 998244353ll; int n; ll add(ll a, ll b) { return (a + b) % mod; } int esc(int tcase) { cin >> n; vi vec(n); for (auto &e : vec) cin >> e; vl dp0(201), sdp0(201), dp1(201), sdp1(201); for (int i = 1; i <= 200; i++) { if (vec.back() == -1 or i == vec.back()) dp0[i] = 1; } partial_sum(dp0.begin(), dp0.end(), sdp0.begin(), add); partial_sum(dp1.begin(), dp1.end(), sdp1.begin(), add); ; auto get0 = [&](int l, int r) -> ll { if (r < l) return 0; return (sdp0[r] - sdp0[l - 1] + mod) % mod; }; auto get1 = [&](int l, int r) -> ll { if (r < l) return 0; return (sdp1[r] - sdp1[l - 1] + mod) % mod; }; for (auto i = n - 2; i >= 0; i--) { vl ndp0(201), ndp1(201); for (int x = 1; x <= 200; x++) { if (vec[i] == -1 or x == vec[i]) { ndp0[x] = (get0(1, x - 1) + get1(1, x - 1)) % mod; ndp1[x] = (get1(x + 1, 200) + get1(x, x) + get0(x, x)) % mod; } } partial_sum(ndp0.begin(), ndp0.end(), sdp0.begin(), add); partial_sum(ndp1.begin(), ndp1.end(), sdp1.begin(), add); ; ; ; } cout << get1(1, 200) << n ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tc = 1; for (int i = 1; i <= tc; i++) esc(i); }
|
#include <bits/stdc++.h> const int maxN = 1000005, p = 998244353; int n, ans, fac[maxN], inv[maxN]; inline int power(int x, long long y) { int res = 1; for (; y; y >>= 1, x = (long long)x * x % p) { if (y & 1) { res = (long long)res * x % p; } } return res; } inline int binomial(int x, int y) { return (long long)fac[x] * inv[y] % p * inv[x - y] % p; } inline long long sign(int x) { return x & 1 ? -1 : 1; } int main() { scanf( %d , &n); for (int i = fac[0] = 1; i <= n; i++) { fac[i] = (long long)fac[i - 1] * i % p; } inv[n] = power(fac[n], p - 2); for (int i = n; i; i--) { inv[i - 1] = (long long)inv[i] * i % p; } for (int i = 1; i <= n; i++) { ans = (ans + sign(i) * binomial(n, i) * power(3, (long long)n * (n - i) + i) * 2) % p; } for (int i = 0; i < n; i++) { ans = (ans + sign(n - i) * binomial(n, i) * (power(power(3, i) - 1, n) - power(3, (long long)n * i)) * 3) % p; } printf( %d n , (p - ans) % p); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a; string b; cin >> a >> b; while (a++) { int i = a; string comp = ; while (i > 0) { int c = i % 10; if (c == 4 || c == 7) { comp = to_string(c) + comp; } i /= 10; } if (comp == b) { cout << a; return 0; } } }
|
#include <bits/stdc++.h> int main() { using namespace std; int c, m, i; cin >> c >> m; int a = 0; for (i = 1; i <= 9; i++) { if (i * c % 10 == 0) { cout << i; break; } if (c == m) { cout << i; break; } if (i * c % 10 == m) { cout << i; break; } } }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int N = 300001; int dp[82][82][82][82], n, k, m, u, v, c; vector<pair<int, int> > g[83]; int calc(int idx, int l, int r, int rem) { if (rem == 0) return 0; if (l > r) return 1e9; int &ret = dp[idx][l][r][rem]; if (ret != -1) return ret; ret = 1e9; for (int i = 0; i < g[idx].size(); ++i) { int v = g[idx][i].first; int cost = g[idx][i].second; if (v < l) continue; if (v > r) continue; ret = min(ret, cost + calc(v, v + 1, r, rem - 1)); ret = min(ret, cost + calc(v, l, v - 1, rem - 1)); } return ret; } int main() { memset(dp, -1, sizeof dp); scanf( %d%d , &n, &k); scanf( %d , &m); for (int i = 0; i < m; ++i) { scanf( %d%d%d , &u, &v, &c); if (u == v) continue; g[u].push_back(make_pair(v, c)); } int ret = 1e9; for (int i = 1; i <= n; ++i) { ret = min(ret, calc(i, i + 1, n, k - 1)); ret = min(ret, calc(i, 1, i - 1, k - 1)); } if (ret == 1e9) ret = -1; printf( %d n , ret); return 0; }
|
`timescale 1ns / 1ps
//*************************************************************************
// > ÎļþÃû: data_mem.v
// > ÃèÊö £ºÒì²½Êý¾Ý´æ´¢Æ÷Ä£¿é£¬²ÉÓüĴæÆ÷´î½¨¶ø³É£¬ÀàËƼĴæÆ÷¶Ñ
// > ͬ²½Ð´£¬Òì²½¶Á
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module data_ram(
input clk, // ʱÖÓ
input [3:0] wen, // ×Ö½ÚдʹÄÜ
input [4:0] addr, // µØÖ·
input [31:0] wdata, // дÊý¾Ý
output reg [31:0] rdata, // ¶ÁÊý¾Ý
//µ÷ÊԶ˿ڣ¬ÓÃÓÚ¶Á³öÊý¾ÝÏÔʾ
input [4 :0] test_addr,
output reg [31:0] test_data
);
reg [31:0] DM[31:0]; //Êý¾Ý´æ´¢Æ÷£¬×Ö½ÚµØÖ·7'b000_0000~7'b111_1111
//дÊý¾Ý
always @(posedge clk) // µ±Ð´¿ØÖÆÐźÅΪ1£¬Êý¾ÝдÈëÄÚ´æ
begin
if (wen[3])
begin
DM[addr][31:24] <= wdata[31:24];
end
end
always @(posedge clk)
begin
if (wen[2])
begin
DM[addr][23:16] <= wdata[23:16];
end
end
always @(posedge clk)
begin
if (wen[1])
begin
DM[addr][15: 8] <= wdata[15: 8];
end
end
always @(posedge clk)
begin
if (wen[0])
begin
DM[addr][7 : 0] <= wdata[7 : 0];
end
end
//¶ÁÊý¾Ý,È¡4×Ö½Ú
always @(*)
begin
case (addr)
5'd0 : rdata <= DM[0 ];
5'd1 : rdata <= DM[1 ];
5'd2 : rdata <= DM[2 ];
5'd3 : rdata <= DM[3 ];
5'd4 : rdata <= DM[4 ];
5'd5 : rdata <= DM[5 ];
5'd6 : rdata <= DM[6 ];
5'd7 : rdata <= DM[7 ];
5'd8 : rdata <= DM[8 ];
5'd9 : rdata <= DM[9 ];
5'd10: rdata <= DM[10];
5'd11: rdata <= DM[11];
5'd12: rdata <= DM[12];
5'd13: rdata <= DM[13];
5'd14: rdata <= DM[14];
5'd15: rdata <= DM[15];
5'd16: rdata <= DM[16];
5'd17: rdata <= DM[17];
5'd18: rdata <= DM[18];
5'd19: rdata <= DM[19];
5'd20: rdata <= DM[20];
5'd21: rdata <= DM[21];
5'd22: rdata <= DM[22];
5'd23: rdata <= DM[23];
5'd24: rdata <= DM[24];
5'd25: rdata <= DM[25];
5'd26: rdata <= DM[26];
5'd27: rdata <= DM[27];
5'd28: rdata <= DM[28];
5'd29: rdata <= DM[29];
5'd30: rdata <= DM[30];
5'd31: rdata <= DM[31];
endcase
end
//µ÷ÊԶ˿ڣ¬¶Á³öÌض¨ÄÚ´æµÄÊý¾Ý
always @(*)
begin
case (test_addr)
5'd0 : test_data <= DM[0 ];
5'd1 : test_data <= DM[1 ];
5'd2 : test_data <= DM[2 ];
5'd3 : test_data <= DM[3 ];
5'd4 : test_data <= DM[4 ];
5'd5 : test_data <= DM[5 ];
5'd6 : test_data <= DM[6 ];
5'd7 : test_data <= DM[7 ];
5'd8 : test_data <= DM[8 ];
5'd9 : test_data <= DM[9 ];
5'd10: test_data <= DM[10];
5'd11: test_data <= DM[11];
5'd12: test_data <= DM[12];
5'd13: test_data <= DM[13];
5'd14: test_data <= DM[14];
5'd15: test_data <= DM[15];
5'd16: test_data <= DM[16];
5'd17: test_data <= DM[17];
5'd18: test_data <= DM[18];
5'd19: test_data <= DM[19];
5'd20: test_data <= DM[20];
5'd21: test_data <= DM[21];
5'd22: test_data <= DM[22];
5'd23: test_data <= DM[23];
5'd24: test_data <= DM[24];
5'd25: test_data <= DM[25];
5'd26: test_data <= DM[26];
5'd27: test_data <= DM[27];
5'd28: test_data <= DM[28];
5'd29: test_data <= DM[29];
5'd30: test_data <= DM[30];
5'd31: test_data <= DM[31];
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_1_V
`define SKY130_FD_SC_LP__DFRTN_1_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_1_V
|
/*
* Single channel counter of 8254 timer simplified for Zet SoC
* Copyright (c) 2010 YS <>
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* This module uses:
* - Modes (binary) 2 and 3 only
* Assumptions:
* 1. clkt is asynchronous simple wire (1.193182 MHz by default)
* 2. gate is synchronous (comes from Wishbone controlled register)
* 3. clkrw read/write clock (derived from Wishbone clock) is running
* always and it has much higher frequency than clkt
*/
module timer_counter(
input [1:0] cntnum, // Counter Number constant 0/1/2
input [5:0] cw0, // Initial Control Word constant
input [15:0] cr0, // Initial Constant Register constant
input clkrw, // Read/Write System Clock
input rst, // Reset
input wrc, // Write Command 1 clock pulse
input wrd, // Write Data 1 clock pulse
input rdd, // Read Data full cycle strobe
input [7:0] data_i, // Input Data
output reg [7:0] data_o, // Output Data
input clkt, // Timer Clock (asynchronous to clkrw)
input gate, // Timer Gate (synchronous to clkrw)
output out // Timer Out (synchronous to clkrw)
);
localparam
DATL = 2'd0,
DATH = 2'd1,
STAT = 2'd2;
reg [15:0] rCounter; // Timer Counter
reg [15:0] rConstant; // Constant Register
reg [5:0] rControl; // Control Word Register
reg [15:0] rLatchD; // Output Data Latch
reg [7:0] rLatchS; // Output State Latch
reg bOut;
reg bFn;
reg clcd, clcs; // Latch Data and Latch State command pulses
reg fWroteLow;
reg fWroteHigh;
reg fCount;
reg bCurrentClk;
reg bFilterClk1;
reg bFilterClk2;
reg fLatchData;
reg fLatchStat;
reg rdd1;
reg [1:0] outmux;
reg fToggleHigh;
wire fReadEnd;
wire [2:0] rbc_cnt_mask = data_i[3:1];
wire fMode3 = (rControl[2:1] == 2'b11);
wire fRWLow = rControl[4];
wire fRWHigh = rControl[5];
assign out = bOut;
// Write to Control Word Register
always @(posedge clkrw)
begin
if (rst)
begin
rControl <= cw0;
clcd <= 1'b0;
clcs <= 1'b0;
end
else
begin
if (wrc && data_i[7:6] == cntnum)
begin
if (data_i[5:4] == 2'b00)
clcd <= 1'b1; // CLC
else
rControl <= data_i[5:0]; // WRC
end
else if (wrc && data_i[7:6] == 2'b11 && rbc_cnt_mask[cntnum])
begin
clcd <= ~data_i[5]; // RBC
clcs <= ~data_i[4];
end
if (clcd)
clcd <= 1'b0; // 1 clock pulse clcd
if (clcs)
clcs <= 1'b0; // 1 clock pulse clcs
end
end
// Write to Constant Register
always @(posedge clkrw)
begin
if (rst)
begin
rConstant <= cr0;
fWroteLow <= 1'b0;
fWroteHigh <= 1'b0;
end
else
begin
if (fWroteHigh || wrc)
begin
fWroteLow <= 1'b0;
fWroteHigh <= 1'b0;
end
if (wrd) // need 1 clock pulse wrd!!!
begin
if (!fWroteLow)
begin
if (fRWLow)
rConstant[7:0] <= data_i[7:0];
fWroteLow <= 1'b1;
if (!fRWHigh)
begin
rConstant[15:8] <= 8'b00000000;
fWroteHigh <= 1'b1;
end
end
if (!fWroteHigh && (fWroteLow || !fRWLow))
begin
if (fRWHigh)
rConstant[15:8] <= data_i[7:0];
fWroteHigh <= 1'b1;
if (!fRWLow)
begin
rConstant[7:0] <= 8'b00000000;
fWroteLow <= 1'b1;
end
end
end // if (wrd)
end
end
// Synchronizing Count Clock with Wishbone Clock
always @(posedge clkrw)
begin
if (rst)
begin
fCount <= 1'b0;
bCurrentClk <= 1'b0;
bFilterClk1 <= 1'b0;
bFilterClk2 <= 1'b0;
end
else
begin
bFilterClk1 <= clkt;
bFilterClk2 <= bFilterClk1;
if ((bFilterClk1 == bFilterClk2) && (bCurrentClk != bFilterClk2))
begin
bCurrentClk <= bFilterClk2;
if (bCurrentClk == 1'b1) // falling edge of clkt
fCount <= 1'b1;
end
if (fCount)
fCount <= 1'b0; // 1 clock pulse fCount
end
end
// Timer Counter in mode 2 or mode 3
always @(posedge clkrw)
begin
if (rst)
begin
bOut <= 1'b1;
rCounter <= cr0 & ((cw0[2:1] == 2'b11) ? 16'hFFFE : 16'hFFFF); // (mode==3) ? :
bFn <= 1'b0;
end
else
begin
if (fWroteHigh)
begin
rCounter <= rConstant & ((fMode3) ? 16'hFFFE : 16'hFFFF);
bOut <= 1'b1;
end
else if (fCount && gate) // tclk_i && gate_i
begin
if ((fMode3) ? (bOut == 1'b0 && rCounter == 16'h0002) : (bOut == 1'b0))
begin
rCounter <= rConstant & ((fMode3) ? 16'hFFFE : 16'hFFFF);
bOut <= 1'b1;
end
else if (fMode3 && bOut == 1'b1 && rCounter == ((rConstant[0]) ? 16'h0000 : 16'h0002))
begin
rCounter <= rConstant & 16'hFFFE;
bOut <= 1'b0;
end
else if (!fMode3 && rCounter == 16'h0002)
bOut <= 1'b0;
else
rCounter <= rCounter - ((fMode3) ? 16'h0002 : 16'h0001);
end
end
end
// Output Latch Control
always @(posedge clkrw)
begin
if (rst)
begin
fLatchData <= 1'b0;
fLatchStat <= 1'b0;
rLatchD <= 16'b0;
rLatchS <= 8'b0;
end
else
begin
if (!fLatchData)
rLatchD <= rCounter;
if (!fLatchStat)
rLatchS <= {bOut, bFn, rControl};
if (clcd)
fLatchData <= 1'b1;
if (clcs)
fLatchStat <= 1'b1;
if (fReadEnd)
begin
if (fLatchStat)
fLatchStat <= 1'b0;
else if (fLatchData)
fLatchData <= 1'b0;
end
end
end
// Output Mux
always @(outmux or rLatchS or rLatchD)
begin
case (outmux)
STAT: data_o = rLatchS;
DATH: data_o = rLatchD[15:8];
DATL: data_o = rLatchD[7:0];
endcase
end
assign fReadEnd = !rdd && rdd1; // 1 clock pulse after read
// Read Data/State
always @(posedge clkrw)
begin
if (rst)
begin
rdd1 <= 1'b0;
outmux <= DATL;
fToggleHigh <= 1'b0;
end
else
begin
// Helper for fReadEnd
rdd1 <= rdd;
// Output Mux Control
if (fLatchStat)
outmux <= STAT;
else if ((fRWHigh && !fRWLow) || (fRWHigh && fToggleHigh))
outmux <= DATH;
else
outmux <= DATL;
if (wrc)
fToggleHigh <= 1'b0;
else if (fReadEnd && !fLatchStat)
fToggleHigh <= !fToggleHigh;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, a, b; vector<long long> v; long long rec(long long l, long long r) { long long i = lower_bound(v.begin(), v.end(), l) - v.begin(); long long j = upper_bound(v.begin(), v.end(), r) - v.begin(); j--; long long na = j - i + 1; long long val1 = b * (r - l + 1) * na; if (na == 0) return a; if (l == r) { if (na == 0) return a; else return val1; } long long mid = (r + l) / 2; long long val2 = rec(l, mid) + rec(mid + 1, r); long long ans = min(val1, val2); return ans; } int main() { cin >> n >> k >> a >> b; long long x; for (long long i = 0; i < k; i++) { cin >> x; v.push_back(x); } sort(v.begin(), v.end()); long long l = 1, r = pow(2, n); long long ans = rec(l, r); cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxsize = 100005; const int inf = 1061109567; vector<int> edge[maxsize]; vector<pair<int, int> > base[maxsize]; int nnext[maxsize]; int n; int deepth[maxsize]; int siz[maxsize]; int last = 0; int ans[10 * maxsize]; int cnt = 0; void dfs1(int u) { if (edge[u].size() == 0) { deepth[u] = 1; return; } int maxi = 0; for (auto v : edge[u]) { siz[v] = siz[u] + 1; dfs1(v); maxi = max(deepth[v], maxi); base[u].push_back({deepth[v], v}); } deepth[u] = maxi + 1; sort(base[u].begin(), base[u].end()); return; } void dfs2(int u) { for (auto v : base[u]) { nnext[last] = v.second; last = v.second; printf( %d , v.second); dfs2(v.second); } return; } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int u; scanf( %d , &u); edge[u].push_back(i + 1); } dfs1(0); printf( 0 ); dfs2(0); puts( ); int gg = 0; while (nnext[gg]) { int r = siz[gg] - siz[nnext[gg]] + 1; for (int i = 0; i < r; i++) ans[cnt++] = nnext[gg]; gg = nnext[gg]; } printf( %d n , cnt); for (int i = 0; i < cnt; i++) printf( %d , ans[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int l, n, a[55], b[55], c[55], d[55]; int main() { cin >> n >> l; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 1; i < n; i++) c[i] = a[i] - a[i - 1]; c[0] = a[0] + l - a[n - 1]; for (int i = 1; i < n; i++) d[i] = b[i] - b[i - 1]; d[0] = b[0] + l - b[n - 1]; for (int i = 0; i < n; i++) { bool f = 1; for (int j = i; j < n; j++) { if (c[j - i] != d[j]) f = 0; } for (int j = 0; j < i; j++) { if (c[j + n - i] != d[j]) f = 0; } if (f) { cout << YES n ; return 0; } } cout << NO n ; }
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#include <bits/stdc++.h> const int Mod = 1001943197; const int Base = 34300; const int MN = 100005, MQ = 100005, S = 500, MS = S + 5; char s[MN], t[MN]; int N, lt, Lim, per[MN]; int pBase[MN]; int Hs[MN], Ht[MN]; inline int Hmerge(int h1, int h2, int l2) { return (int)(((long long)h1 * pBase[l2] + h2) % Mod); } inline int gHash(int *H, int lb, int rb) { return (int)(((long long)H[lb - 1] * (Mod - pBase[rb - lb + 1]) + H[rb]) % Mod); } inline bool smallerThan(int pos1, int pos2) { if (pos1 == pos2) return false; bool rev = false; if (pos1 > pos2) std::swap(pos1, pos2), rev = true; int lb = 0, rb = lt + (pos2 - pos1), ans = -1; while (lb <= rb) { int mid = (lb + rb) / 2; int hs1 = mid <= lt ? gHash(Ht, 1, mid) : Hmerge(Ht[lt], gHash(Hs, pos1 + 1, pos1 + (mid - lt)), mid - lt); int hs2 = mid <= pos2 - pos1 ? gHash(Hs, pos1 + 1, pos1 + mid) : Hmerge(gHash(Hs, pos1 + 1, pos2), gHash(Ht, 1, mid - (pos2 - pos1)), mid - (pos2 - pos1)); if (hs1 == hs2) ans = mid, lb = mid + 1; else rb = mid - 1; } if (ans == lt + (pos2 - pos1)) return rev ? pos2 < pos1 : pos1 < pos2; char ch1 = ans < lt ? t[ans + 1] : s[pos1 + ans - lt + 1]; char ch2 = ans < pos2 - pos1 ? s[pos1 + ans + 1] : t[ans - (pos2 - pos1) + 1]; if (rev) std::swap(ch1, ch2); return ch1 < ch2; } int iper[MN], id[MN]; int ST[17][MN]; inline int gMin(int x, int y) { return iper[x] < iper[y] ? x : y; } inline int RMQ(int l, int r) { int j = 31 - __builtin_clz(r - l + 1); return gMin(ST[j][l + (1 << j) - 1], ST[j][r]); } int Q, ql[MQ], qr[MQ], qk[MQ], qx[MQ], qy[MQ], Ans[MQ]; std::vector<int> V[MS]; int main() { scanf( %s%s%d , s + 1, t + 1, &Q); N = (int)(strlen(s + 1)), lt = (int)(strlen(t + 1)); for (int i = 1; i <= N; ++i) Hs[i] = (int)(((long long)Hs[i - 1] * Base + (s[i] - a + 1)) % Mod); for (int i = 1; i <= lt; ++i) Ht[i] = (int)(((long long)Ht[i - 1] * Base + (t[i] - a + 1)) % Mod); Lim = std::max(N, lt), pBase[0] = 1; for (int i = 1; i <= Lim; ++i) pBase[i] = (int)((long long)pBase[i - 1] * Base % Mod); for (int i = 1; i <= N + 1; ++i) per[i] = i - 1; std::sort(per + 1, per + N + 2, smallerThan); for (int i = 1; i <= N + 1; ++i) iper[per[i]] = i; for (int i = 0; i <= N; ++i) ST[0][i] = i; for (int j = 0; 2 << j <= N + 1; ++j) for (int i = (2 << j) - 1; i <= N; ++i) ST[j + 1][i] = gMin(ST[j][i - (1 << j)], ST[j][i]); for (int i = 1; i <= Q; ++i) { scanf( %d%d%d%d%d , &ql[i], &qr[i], &qk[i], &qx[i], &qy[i]); if (qk[i] > S) { int lim = N / qk[i], ans = -1; for (int j = 0; j <= lim; ++j) { int l = j * qk[i] + qx[i]; int r = j * qk[i] + qy[i]; l = std::max(l, ql[i]); r = std::min(r, qr[i]); if (l <= r) { int res = RMQ(l, r); if (ans == -1) ans = res; else ans = gMin(ans, res); } } Ans[i] = ans; } else V[qk[i]].push_back(i); } for (int k = 1; k <= S; ++k) { int tot = 0, mxlen = N / k + 1; for (int j = 0; j < k; ++j) for (int i = j; i <= N; i += k) ST[0][++tot] = i, id[i] = tot; for (int j = 0; 2 << j <= mxlen; ++j) for (int i = 2 << j; i <= tot; ++i) ST[j + 1][i] = gMin(ST[j][i - (1 << j)], ST[j][i]); for (int i : V[k]) { int ans = -1; for (int j = qx[i]; j <= qy[i]; ++j) { int l = id[j] + (ql[i] - j + k - 1) / k; int r = id[j] + (qr[i] - j + k) / k - 1; if (l <= r) { int res = RMQ(l, r); if (ans == -1) ans = res; else ans = gMin(ans, res); } } Ans[i] = ans; } } for (int i = 1; i <= Q; ++i) printf( %d%c , Ans[i], n [i == Q]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/13/2016 05:51:29 PM
// Design Name:
// Module Name: Testbench_Barrel_Shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EWR=5;
parameter SWR=26;
//inputs
reg clk;
reg rst;
reg load_i;
reg [EWR-1:0] Shift_Value_i;
reg [SWR-1:0] Shift_Data_i;
reg Left_Right_i;
reg Bit_Shift_i;
///////////////////OUTPUT//////////////////////////7
wire [SWR-1:0] N_mant_o;
Mux_Array_DW #(
.SWR(SWR),
.EWR(EWR)
) inst_Mux_Array (
.clk(clk),
.rst(rst),
.load_i(load_i),
.Data_i (Shift_Data_i),
.FSM_left_right_i (Left_Right_i),
.Shift_Value_i (Shift_Value_i),
.bit_shift_i (Bit_Shift_i),
.Data_o (N_mant_o)
);
integer Contador_shiftvalue = 0;
always begin
#(8*PERIOD/2) Contador_shiftvalue = Contador_shiftvalue + 1;
Shift_Value_i = Contador_shiftvalue;
Left_Right_i = ~Left_Right_i;
#(8*PERIOD/2);
end
always @ (N_mant_o )
begin
$monitor($time,"REA Salida = %b Entrada = %b Numero de Corrimiento: %d",N_mant_o,Shift_Data_i, Shift_Value_i);
$display($time,"TEO Salida = %b Entrada = %b Numero de Corrimiento: %d",(Shift_Data_i>>Shift_Value_i),Shift_Data_i,Shift_Value_i);
end
initial begin
// Initialize Input
rst = 1;
clk = 0;
load_i = 0;
Shift_Value_i = 0;
Shift_Data_i = $random;
Left_Right_i = 0;
Bit_Shift_i = 0;
#40 rst = 0;
load_i = 1;
end
initial begin
#(PERIOD * 1024);
$finish;
end
initial begin
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 105; const long long INF = (long long)0x7fffffffffff; long long dp[maxn][maxn][maxn], wi[maxn], c[maxn]; long long min(long long a, long long b) { return a > b ? b : a; } int main() { int n, m, k, temp, flag = 1, ans1 = 0; cin >> n >> m >> k; for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { for (int l = 0; l <= n; l++) { dp[i][j][l] = INF; } } } for (int i = 1; i <= n; i++) { cin >> c[i]; } for (int i = 1; i <= m; i++) cin >> wi[i]; if (c[1] == 0) for (int i = 1; i <= m; i++) dp[1][i][1] = wi[i]; else dp[1][c[1]][1] = 0; for (int i = 2; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> wi[j]; for (int l = 1; l <= i; l++) { if (c[i] == 0) { for (int p = 1; p <= m; p++) { if (p == j) { dp[i][j][l] = min(dp[i][j][l], dp[i - 1][j][l] + wi[j]); } else { dp[i][j][l] = min(dp[i][j][l], dp[i - 1][p][l - 1] + wi[j]); } } } else { for (int p = 1; p <= m; p++) { if (p == c[i]) { dp[i][c[i]][l] = min(dp[i][c[i]][l], dp[i - 1][c[i]][l]); } else { dp[i][c[i]][l] = min(dp[i][c[i]][l], dp[i - 1][p][l - 1]); } } } } } } long long ans = INF; for (int i = 1; i <= m; i++) ans = min(ans, dp[n][i][k]); if (ans >= INF) cout << -1 << endl; else cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const int M = 1000000000; const int INF = 1e18; int a[N], b[N], s1[N], s2[N]; int n, m, k, d, top1, top2, ansr, ansl, sum[N], pos[N], t[N], mn[N]; map<int, int> mp; void reset(int x) { mn[x] = INF; for (int i = (x - 1) * m + 1; i <= min(n, x * m); i++) mn[x] = min(mn[x], t[i] + sum[x]); } inline void add(int l, int r, int c) { for (int i = l; i <= min(r, pos[l] * m); i++) t[i] += c; reset(pos[l]); if (pos[l] != pos[r]) { for (int i = (pos[r] - 1) * m + 1; i <= min(n, r); i++) t[i] += c; reset(pos[r]); } for (int i = pos[l] + 1; i <= pos[r] - 1; i++) sum[i] += c, mn[i] += c; } inline int query(int l, int r, int c) { for (int i = r; i >= max((pos[r] - 1) * m + 1, l); i--) if (t[i] + sum[pos[i]] <= c) { return i; } for (int i = pos[r] - 1; i >= pos[l] + 1; i--) if (mn[i] <= c) for (int j = i * m; j >= (i - 1) * m + 1; j--) if (t[j] + sum[pos[j]] <= c) { return j; } if (pos[l] != pos[r]) { for (int i = pos[l] * m; i >= l; i--) { if (t[i] + sum[pos[i]] <= c) return i; } } } inline void sol(int L, int R) { if (L == R) return; mp.clear(); int r = R + 1; top1 = top2 = 0; s1[top1] = s2[top2] = R + 1; for (int i = 0; i <= pos[n]; i++) sum[i] = 0; for (int i = R; i >= L; i--) { if (mp.count(a[i])) r = min(r, mp[a[i]]); while (top1 && a[i] > a[s1[top1]]) { add(s1[top1], s1[top1 - 1] - 1, -a[s1[top1]]); top1--; } s1[++top1] = i; add(s1[top1], s1[top1 - 1] - 1, a[s1[top1]]); while (top2 && a[i] < a[s2[top2]]) { add(s2[top2], s2[top2 - 1] - 1, a[s2[top2]]); top2--; } s2[++top2] = i; add(s2[top2], s2[top2 - 1] - 1, -a[s2[top2]]); int rr = query(i, r - 1, k - i); if (rr - i > ansr - ansl || (rr - i == ansr - ansl && i < ansl)) ansl = i, ansr = rr; mp[a[i]] = i; } return; } int main() { scanf( %d%d%d , &n, &k, &d); if (d == 0) { for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int ansl = 1; int ansr = 1; int lst = 1; for (int i = 2; i <= n; i++) { if (a[i] != a[lst]) { if (i - 1 - lst > ansr - ansl) { ansl = lst; ansr = i - 1; } lst = i; } } printf( %d %d n , ansl, ansr); return 0; } ansl = n + 1; ansr = 0; m = sqrt(n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = (a[i] += M) % d; a[i] = (a[i]) / d + 1; pos[i] = (i - 1) / m + 1; t[i] = -i; } for (int i = 1, j; i <= n; i = j) { for (j = i + 1; j <= n; j++) { if (b[i] != b[j]) break; } sol(i, j - 1); } printf( %d %d n , ansl, ansr); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2005; char mp[N][N]; int deg[N][N]; int cnt[2], n, m; int dx[] = {0, 0, 1, -1}, dy[] = {1, -1, 0, 0}; string str = ><v^ , tmp = <>^v ; bool check(int x, int y) { return x >= 1 && x <= n && y >= 1 && y <= m; } int main() { ios ::sync_with_stdio(0); cin >> n >> m; for (int i = (int)(1); i <= (int)(n); ++i) { cin >> (mp[i] + 1); } for (int i = (int)(1); i <= (int)(n); ++i) { for (int j = (int)(1); j <= (int)(m); ++j) { if (mp[i][j] == . ) { if ((i + j) & 1) { cnt[1]++; } else cnt[0]++; } } } if (cnt[0] != cnt[1]) { cout << Not unique << endl; return 0; } else { queue<int> q; for (int i = (int)(1); i <= (int)(n); ++i) { for (int j = (int)(1); j <= (int)(m); ++j) { if (mp[i][j] == . ) { for (int k = 0; k < (int)(4); ++k) { int x = i + dx[k]; int y = j + dy[k]; if (check(x, y) && mp[x][y] == . ) { deg[i][j]++; } } if (deg[i][j] == 1) { q.push(i); q.push(j); } } } } while (q.size()) { int x = q.front(); q.pop(); int y = q.front(); q.pop(); for (int k = 0; k < (int)(4); ++k) { int tx = x + dx[k]; int ty = y + dy[k]; if (check(tx, ty) && mp[tx][ty] == . && deg[tx][ty] > 0) { mp[x][y] = tmp[k]; mp[tx][ty] = str[k]; deg[tx][ty] = 0; deg[x][y] = 0; for (int t = 0; t < (int)(4); ++t) { int ax = tx + dx[t]; int ay = ty + dy[t]; if (check(ax, ay) && mp[ax][ay] == . && deg[ax][ay] > 0) { deg[ax][ay]--; if (deg[ax][ay] == 1) { q.push(ax); q.push(ay); } } } break; } } } for (int i = (int)(1); i <= (int)(n); ++i) { for (int j = (int)(1); j <= (int)(m); ++j) { if (deg[i][j] > 0 || mp[i][j] == . ) { cout << Not unique << endl; return 0; } } } for (int i = (int)(1); i <= (int)(n); ++i) { cout << mp[i] + 1 << endl; } } return 0; }
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//This module maps physical 512KB blocks of every memory chip to different memory ranges in Amiga
module minimig_bankmapper
(
input chip0, // chip ram select: 1st 512 KB block
input chip1, // chip ram select: 2nd 512 KB block
input chip2, // chip ram select: 3rd 512 KB block
input chip3, // chip ram select: 4th 512 KB block
input slow0, // slow ram select: 1st 512 KB block
input slow1, // slow ram select: 2nd 512 KB block
input slow2, // slow ram select: 3rd 512 KB block
input kick, // Kickstart ROM address range select
input kick1mb, // 1MB Kickstart 'upper' half
input cart, // Action Reply memory range select
input aron, // Action Reply enable
input ecs, // ECS chipset enable
input [3:0] memory_config,// memory configuration
output reg [7:0] bank // bank select
);
always @(*)
begin
case ({aron,memory_config})
5'b0_0000 : bank = { kick, kick1mb, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, chip3 | chip2 | chip1 | chip0 }; // 0.5M CHIP
5'b0_0001 : bank = { kick, kick1mb, 1'b0, 1'b0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP
5'b0_0010 : bank = { kick, kick1mb, 1'b0, 1'b0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP
5'b0_0011 : bank = { kick, kick1mb, 1'b0, 1'b0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP
5'b0_0100 : bank = { kick, kick1mb, 1'b0, slow0, 1'b0, 1'b0, 1'b0, chip0 | (chip1 & !ecs) | chip2 | (chip3 & !ecs) }; // 0.5M CHIP + 0.5MB SLOW
5'b0_0101 : bank = { kick, kick1mb, 1'b0, slow0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP + 0.5MB SLOW
5'b0_0110 : bank = { kick, kick1mb, 1'b0, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 0.5MB SLOW
5'b0_0111 : bank = { kick, kick1mb, 1'b0, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 0.5MB SLOW
5'b0_1000 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, 1'b0, chip3 | chip2 | chip1 | chip0 }; // 0.5M CHIP + 1.0MB SLOW
5'b0_1001 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP + 1.0MB SLOW
5'b0_1010 : bank = { kick, kick1mb, slow1, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.0MB SLOW
5'b0_1011 : bank = { kick, kick1mb, slow1, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.0MB SLOW
5'b0_1100 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, 1'b0, chip3 | chip2 | chip1 | chip0 }; // 0.5M CHIP + 1.5MB SLOW
5'b0_1101 : bank = { kick, kick1mb, slow1, slow0, 1'b0, 1'b0, chip3 | chip1, chip2 | chip0 }; // 1.0M CHIP + 1.5MB SLOW
5'b0_1110 : bank = { kick, kick1mb, slow1, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.5MB SLOW
5'b0_1111 : bank = { kick, kick1mb, slow1, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.5MB SLOW
5'b1_0000 : bank = { kick, kick1mb, cart, 1'b0, 1'b0, 1'b0, 1'b0, chip0 | chip1 | chip2 | chip3 }; // 0.5M CHIP
5'b1_0001 : bank = { kick, kick1mb, cart, 1'b0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP
5'b1_0010 : bank = { kick, kick1mb, cart, 1'b0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP
5'b1_0011 : bank = { kick, kick1mb, cart, 1'b0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP
5'b1_0100 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, 1'b0, chip0 | (chip1 & !ecs) | chip2 | (chip3 & !ecs) }; // 0.5M CHIP + 0.5MB SLOW
5'b1_0101 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP + 0.5MB SLOW
5'b1_0110 : bank = { kick, kick1mb, cart, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 0.5MB SLOW
5'b1_0111 : bank = { kick, kick1mb, cart, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 0.5MB SLOW
5'b1_1000 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, 1'b0, chip0 | chip1 | chip2 | chip3 }; // 0.5M CHIP + 1.0MB SLOW
5'b1_1001 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP + 1.0MB SLOW
5'b1_1010 : bank = { kick, kick1mb, cart, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.0MB SLOW
5'b1_1011 : bank = { kick, kick1mb, cart, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.0MB SLOW
5'b1_1100 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, 1'b0, chip0 | chip1 | chip2 | chip3 }; // 0.5M CHIP + 1.5MB SLOW
5'b1_1101 : bank = { kick, kick1mb, cart, slow0, 1'b0, 1'b0, chip1 | chip3, chip0 | chip2 }; // 1.0M CHIP + 1.5MB SLOW
5'b1_1110 : bank = { kick, kick1mb, cart, slow0, 1'b0, chip2, chip1, chip0 }; // 1.5M CHIP + 1.5MB SLOW
5'b1_1111 : bank = { kick, kick1mb, cart, slow0, chip3, chip2, chip1, chip0 }; // 2.0M CHIP + 1.5MB SLOW
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Filename: wbpriarbiter.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This is a priority bus arbiter. It allows two separate wishbone
// masters to connect to the same bus, while also guaranteeing
// that one master can have the bus with no delay any time the
// other master is not using the bus. The goal is to eliminate
// the combinatorial logic required in the other wishbone
// arbiter, while still guarateeing access time for the priority
// channel.
//
// The core logic works like this:
//
// 1. When no one requests the bus, 'A' is granted the bus and
// guaranteed that any access will go right through.
// 2. If 'B' requests the bus (asserts cyc), and the bus is idle,
// then 'B' will be granted the bus.
// 3. Bus grants last as long as the 'cyc' line is high.
// 4. Once 'cyc' is dropped, the bus returns to 'A' as the owner.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module wbpriarbiter(i_clk,
// Bus A
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
// Bus B
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
// Both buses
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
parameter DW=32, AW=32;
//
input wire i_clk;
// Bus A
input wire i_a_cyc, i_a_stb, i_a_we;
input wire [(AW-1):0] i_a_adr;
input wire [(DW-1):0] i_a_dat;
input wire [(DW/8-1):0] i_a_sel;
output wire o_a_ack, o_a_stall, o_a_err;
// Bus B
input wire i_b_cyc, i_b_stb, i_b_we;
input wire [(AW-1):0] i_b_adr;
input wire [(DW-1):0] i_b_dat;
input wire [(DW/8-1):0] i_b_sel;
output wire o_b_ack, o_b_stall, o_b_err;
//
output wire o_cyc, o_stb, o_we;
output wire [(AW-1):0] o_adr;
output wire [(DW-1):0] o_dat;
output wire [(DW/8-1):0] o_sel;
input wire i_ack, i_stall, i_err;
// Go high immediately (new cycle) if ...
// Previous cycle was low and *someone* is requesting a bus cycle
// Go low immadiately if ...
// We were just high and the owner no longer wants the bus
// WISHBONE Spec recommends no logic between a FF and the o_cyc
// This violates that spec. (Rec 3.15, p35)
reg r_a_owner;
assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc;
initial r_a_owner = 1'b1;
always @(posedge i_clk)
if (!i_b_cyc)
r_a_owner <= 1'b1;
// Allow B to set its CYC line w/o activating this interface
else if ((i_b_cyc)&&(i_b_stb)&&(!i_a_cyc))
r_a_owner <= 1'b0;
// Realistically, if neither master owns the bus, the output is a
// don't care. Thus we trigger off whether or not 'A' owns the bus.
// If 'B' owns it all we care is that 'A' does not. Likewise, if
// neither owns the bus than the values on the various lines are
// irrelevant.
assign o_we = (r_a_owner) ? i_a_we : i_b_we;
`ifdef ZERO_ON_IDLE
//
// ZERO_ON_IDLE will use up more logic and may even slow down the master
// clock if set. However, it may also reduce the power used by the
// FPGA by preventing things from toggling when the bus isn't in use.
// The option is here because it also makes it a lot easier to look
// for when things happen on the bus via VERILATOR when timing and
// logic counts don't matter.
//
assign o_stb = (o_cyc)? ((r_a_owner) ? i_a_stb : i_b_stb):0;
assign o_adr = (o_stb)? ((r_a_owner) ? i_a_adr : i_b_adr):0;
assign o_dat = (o_stb)? ((r_a_owner) ? i_a_dat : i_b_dat):0;
assign o_sel = (o_stb)? ((r_a_owner) ? i_a_sel : i_b_sel):0;
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0;
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
`else
assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb;
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
// We cannot allow the return acknowledgement to ever go high if
// the master in question does not own the bus. Hence we force it
// low if the particular master doesn't own the bus.
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0;
// Stall must be asserted on the same cycle the input master asserts
// the bus, if the bus isn't granted to him.
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
//
//
assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (!r_a_owner) ? i_err : 1'b0;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; struct segment_tree { long long a[1 << 20][5]; int sz[1 << 20]; int N; void initi(int x) { N = 1; while (N < x) N <<= 1; } void pushup(int x) { int pos = x + N - 1; while (x > 0) { x = (x - 1) >> 1; sz[x] = sz[(x << 1) + 1] + sz[(x << 1) + 2]; for (int i = 0; i < 5; i++) a[x][i] = 0; for (int i = 0; i < 5; i++) { a[x][i] += a[(x << 1) + 1][i]; a[x][(i + sz[(x << 1) + 1]) % 5] += a[(x << 1) + 2][i]; } } } void ins(int x, int y) { int pos = x + N - 1; sz[pos]++; a[pos][0] = y; pushup(pos); } void del(int x) { int pos = x + N - 1; sz[pos]--; a[pos][0] = 0; pushup(pos); } } tr; int n; int s[100010]; vector<int> v; vector<int> vc; map<int, int> mp; int l; int main() { cin >> n; for (int i = 0; i < n; i++) { string t; int x; cin >> t; if (t == add ) { cin >> x; v.push_back(x); vc.push_back(x); } else if (t == del ) { cin >> x; v.push_back(-x); } else { v.push_back(0); } } sort(vc.begin(), vc.end()); tr.initi((int)vc.size()); for (int i = 0; i < vc.size(); i++) { mp[vc[i]] = i; } for (int i = 0; i < v.size(); i++) { if (!v[i]) { printf( %lld n , tr.a[0][2]); } else if (v[i] < 0) { tr.del(mp[-v[i]]); } else { tr.ins(mp[v[i]], v[i]); } } return 0; }
|
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "zynq_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,da_axi4_cnt=1}" *)
module zynq_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire VCC_1;
wire [14:0]processing_system7_1_ddr_ADDR;
wire [2:0]processing_system7_1_ddr_BA;
wire processing_system7_1_ddr_CAS_N;
wire processing_system7_1_ddr_CKE;
wire processing_system7_1_ddr_CK_N;
wire processing_system7_1_ddr_CK_P;
wire processing_system7_1_ddr_CS_N;
wire [3:0]processing_system7_1_ddr_DM;
wire [31:0]processing_system7_1_ddr_DQ;
wire [3:0]processing_system7_1_ddr_DQS_N;
wire [3:0]processing_system7_1_ddr_DQS_P;
wire processing_system7_1_ddr_ODT;
wire processing_system7_1_ddr_RAS_N;
wire processing_system7_1_ddr_RESET_N;
wire processing_system7_1_ddr_WE_N;
wire processing_system7_1_fclk_clk0;
wire processing_system7_1_fclk_reset0_n;
wire processing_system7_1_fixed_io_DDR_VRN;
wire processing_system7_1_fixed_io_DDR_VRP;
wire [53:0]processing_system7_1_fixed_io_MIO;
wire processing_system7_1_fixed_io_PS_CLK;
wire processing_system7_1_fixed_io_PS_PORB;
wire processing_system7_1_fixed_io_PS_SRSTB;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
zynq_1_proc_sys_reset_1_0 proc_sys_reset_1
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_1_fclk_reset0_n),
.mb_debug_sys_rst(GND_1),
.slowest_sync_clk(processing_system7_1_fclk_clk0));
zynq_1_processing_system7_1_0 processing_system7_1
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_1_fclk_clk0),
.FCLK_RESET0_N(processing_system7_1_fclk_reset0_n),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_1_fclk_clk0),
.M_AXI_GP0_ARREADY(GND_1),
.M_AXI_GP0_AWREADY(GND_1),
.M_AXI_GP0_BID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.M_AXI_GP0_BRESP({GND_1,GND_1}),
.M_AXI_GP0_BVALID(GND_1),
.M_AXI_GP0_RDATA({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.M_AXI_GP0_RID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.M_AXI_GP0_RLAST(GND_1),
.M_AXI_GP0_RRESP({GND_1,GND_1}),
.M_AXI_GP0_RVALID(GND_1),
.M_AXI_GP0_WREADY(GND_1),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.TTC0_CLK0_IN(processing_system7_1_fclk_clk0),
.TTC0_CLK1_IN(processing_system7_1_fclk_clk0),
.TTC0_CLK2_IN(processing_system7_1_fclk_clk0));
endmodule
|
// Test implicit casts during procedural continuous (reg) assignments.
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
real dst_r;
bit unsigned [3:0] dst_u2s;
bit signed [3:0] dst_s2s;
bit unsigned [11:0] dst_u2l;
bit signed [11:0] dst_s2l;
logic unsigned [3:0] dst_u4s;
logic signed [3:0] dst_s4s;
logic unsigned [11:0] dst_u4l;
logic signed [11:0] dst_s4l;
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8'bx0z00111;
src_sx = 8'bx0z00111;
$display("cast to real");
assign dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
assign dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
assign dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
assign dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
assign dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
assign dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
assign dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
$display("cast to small unsigned bit");
assign dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
assign dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
assign dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
assign dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
assign dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
assign dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
assign dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
$display("cast to small signed bit");
assign dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
assign dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
assign dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
assign dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
assign dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
assign dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
assign dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
$display("cast to large unsigned bit");
assign dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
assign dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
assign dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
assign dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
assign dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
assign dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
assign dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
$display("cast to large signed bit");
assign dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
assign dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
assign dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
assign dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
assign dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
assign dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
assign dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
$display("cast to small unsigned logic");
assign dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
assign dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
assign dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
assign dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
assign dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
assign dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
assign dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
$display("cast to small signed logic");
assign dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
assign dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
assign dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
assign dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
assign dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
assign dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
assign dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
$display("cast to large unsigned logic");
assign dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
assign dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
assign dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
assign dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
assign dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
assign dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
assign dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
assign dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
assign dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
assign dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
assign dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
assign dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
assign dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
assign dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 10, M = 26; template <typename T = int> inline T read() { T x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f |= ch == - , ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f ? -x : x; } char s[N]; int a[N], pre[N][26], suf[N][26], f[N][26], g[N], dp[27]; inline int mex(int a) { int res = 0; while (a >> res & 1) ++res; return res; } inline int solve(int l, int r, int c) { if (l > r) return 0; if (dp[c] != -1) return dp[c]; int sta = 0; for (int i = 0; i < 26; ++i) { int L = suf[l][i], R = pre[r][i]; if (R < L) continue; sta |= 1 << (f[L - 1][c] ^ g[R] ^ g[L] ^ solve(R + 1, r, i)); } return dp[c] = mex(sta); } inline int Solve(int l, int r, int c) { if (l > r) return 0; if (dp[c] != -1) return dp[c]; int sta = 0; for (int i = 0; i < 26; ++i) { int L = suf[l][i], R = pre[r][i]; if (R < L) continue; sta |= 1 << (Solve(l, L - 1, i) ^ g[R] ^ g[L] ^ f[r][i]); } return dp[c] = mex(sta); } int main() { scanf( %s , s + 1); int n = strlen(s + 1); for (int i = 1; i <= n; ++i) a[i] = s[i] - a ; for (int i = 0; i < 26; ++i) suf[n + 1][i] = n + 1; for (int i = 1; i <= n; ++i) memcpy(pre[i], pre[i - 1], sizeof(pre[i])), pre[i][a[i]] = i; for (int i = n; i >= 1; --i) memcpy(suf[i], suf[i + 1], sizeof(suf[i])), suf[i][a[i]] = i; for (int i = 1; i <= n; ++i) { memset(dp, -1, sizeof(dp)), g[i] = g[pre[i - 1][a[i]]] ^ f[i - 1][a[i]]; for (int c = 0; c < 26; ++c) f[i][c] = solve(pre[i][c] + 1, i, c); } for (int q = read(); q; --q) { int l = read(), r = read(); memset(dp, -1, sizeof(dp)); puts(Solve(l, r, 26) ? Alice : Bob ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1e6; namespace IO { const int MAXSIZE = 1 << 20; char buf[MAXSIZE], *p1, *p2; inline int gc() { return (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, MAXSIZE, stdin), p1 == p2) ? EOF : *p1++); } inline int rd() { int x = 0, f = 1; char c = gc(); while (!isdigit(c)) { if (c == - ) f = -1; c = gc(); } while (isdigit(c)) x = x * 10 + (c ^ 48), c = gc(); return x * f; } inline char getc() { char c = gc(); while (!isgraph(c)) { c = gc(); } return c; } char pbuf[MAXSIZE], *pp = pbuf; inline void push(const char &c) { if (pp - pbuf == MAXSIZE) fwrite(pbuf, 1, MAXSIZE, stdout), pp = pbuf; *pp++ = c; } inline void flush() { fwrite(pbuf, 1, pp - pbuf, stdout), pp = pbuf; } inline void write(int x) { static int sta[35]; int top = 0; do { sta[top++] = x % 10, x /= 10; } while (x); while (top) push(sta[--top] + 0 ); } } // namespace IO int main() { int n, m; n = IO::rd(); m = IO::rd(); vector<char> a(n * m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) a[((i)*m + (j))] = IO::getc(); vector<int> dp(n * m, INF); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (a[((i)*m + (j))] != X ) dp[((i)*m + (j))] = 0; else { if (i && j) dp[((i)*m + (j))] = min(dp[((i - 1) * m + (j - 1))], min(dp[((i - 1) * m + (j))], dp[((i)*m + (j - 1))])) + 1; else dp[((i)*m + (j))] = 1; } } int l = 0, r = min(n, m); auto dp2 = dp; while (l < r) { int mid = (l + r + 1) / 2; int ok = 1; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (dp[((i)*m + (j))] < mid) dp[((i)*m + (j))] = 0; } for (int i = n - 1; i >= 0; i--) for (int j = m - 1; j >= 0; j--) { if (i != n - 1) dp[((i)*m + (j))] = max(dp[((i)*m + (j))], dp[((i + 1) * m + (j))] - 1); if (j != m - 1) dp[((i)*m + (j))] = max(dp[((i)*m + (j))], dp[((i)*m + (j + 1))] - 1); if (i != n - 1 && j != m - 1) dp[((i)*m + (j))] = max(dp[((i)*m + (j))], dp[((i + 1) * m + (j + 1))] - 1); if (dp[((i)*m + (j))] == 0 && a[((i)*m + (j))] == X ) { ok = 0; goto zml; } } zml: if (ok) { l = mid; } else { r = mid - 1; } dp = dp2; } int ans = l; IO::write((ans - 1) / 2); int a1 = (ans - 1) / 2; int a2 = ans / 2; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { a[((i)*m + (j))] = . ; if (dp[((i)*m + (j))] >= ans) { a[((i - a1) * m + (j - a1))] = X ; a[((i - a1) * m + (j - a2))] = X ; a[((i - a2) * m + (j - a1))] = X ; a[((i - a2) * m + (j - a2))] = X ; } } IO::push( n ); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) IO::push(a[((i)*m + (j))]); IO::push( n ); } IO::flush(); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int l, r, k; cin >> l >> r >> k; if (k == 1 || l == r || (r - l == 1 && l % 2 && (l ^ r) >= l)) { cout << l << n1 n << l << endl; return 0; } long long int num = 1, ind; for (int i = 0;; i++) { if (num > l) { ind = i; break; } num *= 2; } if (num + num / 2 <= r && k >= 3) { cout << 0 n3 n << num - 1 << << num + num / 2 << << num + num / 2 - 1 << endl; return 0; } if (r - l == 1) { cout << (l ^ (l + 1)) << n2 n << l << << l + 1 << endl; return 0; } if (l % 2) l++; if (l + 3 <= r && k >= 4) { cout << 0 n4 n << l << << l + 1 << << l + 2 << << l + 3 << endl; } else { cout << 1 n2 n << l << << l + 1 << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { struct node* left; struct node* right; int vl; node() { vl = 0; left = NULL; right = NULL; } }; int a[300005]; int ans = 0; void query(node* n, int v, int i, int j) { if (n == NULL || j == 0) return; int no = (1 << (j - 1)); node* l2 = n->left; node* r2 = n->right; int l1 = 0, r1 = 0; if (l2 != NULL) l1 = l2->vl; if (r2 != NULL) r1 = r2->vl; j--; if ((v & (1 << j)) == 0) { if (l1 == no) { ans += (1 << (j)); query(n->right, v, i / 2, j); return; } query(n->left, v, i / 2, j); return; } if (r1 == no) { ans += (1 << (j)); query(n->left, v, i / 2, j); return; } query(n->right, v, i / 2, j); return; } void insert(node* n, int val, int i, int j) { if (j == 0) return; j--; if ((val & (1 << j)) == 0) { if (n->left == NULL) { node* cur = new node(); n->left = cur; } insert(n->left, val, i / 2, j); return; } if (n->right == NULL) { node* cur = new node(); n->right = cur; } insert(n->right, val, i / 2, j); return; } int dfs(node* n) { if (n->left == NULL && n->right == NULL) { n->vl = 1; return 1; } int w = 0; int u = 0; if (n->left != NULL) { w += dfs(n->left); u++; } if (n->right != NULL) { w += dfs(n->right); u++; } n->vl = w; return w; } int main() { int n, m; cin >> n >> m; node* h = new node(); node* w1 = h; for (int i = 1; i <= n; i++) { cin >> a[i]; h = w1; insert(h, a[i], (1 << 20) - 1, 19); } int x = 0; h = w1; dfs(h); for (int i = 1; i <= m; i++) { int x1; cin >> x1; x = x ^ x1; ans = 0; h = w1; query(h, x, (1 << 20) - 1, 19); cout << ans << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_HS__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_2_1_inv/sky130_fd_sc_hs__u_mux_2_1_inv.v"
`celldefine
module sky130_fd_sc_hs__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
// Local signals
wire u_mux_2_1_inv0_out_Y;
wire u_vpwr_vgnd0_out_Y ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1_inv u_mux_2_1_inv0 (u_mux_2_1_inv0_out_Y, A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y , u_mux_2_1_inv0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_BEHAVIORAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:28:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.v
// Design : system_vga_pll_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_pll_0_0,vga_pll,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_pll,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_pll_0_0
(clk_100,
clk_50,
clk_25,
clk_12_5,
clk_6_25);
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
wire clk_100;
wire clk_12_5;
wire clk_25;
wire clk_50;
wire clk_6_25;
system_vga_pll_0_0_vga_pll U0
(.clk_100(clk_100),
.clk_12_5(clk_12_5),
.clk_25(clk_25),
.clk_50(clk_50),
.clk_6_25(clk_6_25));
endmodule
(* ORIG_REF_NAME = "vga_pll" *)
module system_vga_pll_0_0_vga_pll
(clk_50,
clk_25,
clk_12_5,
clk_6_25,
clk_100);
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
input clk_100;
wire clk_100;
wire clk_12_5;
wire clk_12_5_s_i_1_n_0;
wire clk_25;
wire clk_25_s_i_1_n_0;
wire clk_50;
wire clk_6_25;
wire clk_6_25_s_i_1_n_0;
wire p_0_in;
LUT1 #(
.INIT(2'h1))
clk_12_5_s_i_1
(.I0(clk_12_5),
.O(clk_12_5_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_12_5_s_reg
(.C(clk_25),
.CE(1'b1),
.D(clk_12_5_s_i_1_n_0),
.Q(clk_12_5),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_25_s_i_1
(.I0(clk_25),
.O(clk_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_25_s_reg
(.C(clk_50),
.CE(1'b1),
.D(clk_25_s_i_1_n_0),
.Q(clk_25),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_50_s_i_1
(.I0(clk_50),
.O(p_0_in));
FDRE #(
.INIT(1'b0))
clk_50_s_reg
(.C(clk_100),
.CE(1'b1),
.D(p_0_in),
.Q(clk_50),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_6_25_s_i_1
(.I0(clk_6_25),
.O(clk_6_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_6_25_s_reg
(.C(clk_6_25),
.CE(1'b1),
.D(clk_6_25_s_i_1_n_0),
.Q(clk_6_25),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; double power(float x, int y) { float temp; if (y == 0) return 1; temp = power(x, y / 2); if (y % 2 == 0) return temp * temp; else { if (y > 0) return x * temp * temp; else return (temp * temp) / x; } } bool isPrime(int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } void solve() { long long int n; cin >> n; vector<long long int> a(n); for (long long int i = 0; i < n; i++) cin >> a[i]; ; long long int ans = a[0]; long long int t = a[0]; for (long long int i = 1; i < n; i++) { t += a[i]; ans = min(ans, t); } cout << abs(ans) << endl; } int main() { long long int t; cin >> t; while (t--) solve(); }
|
//--------------------------------------------------------------------------------
//
// sram_interface.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// Writes data to SRAM incrementally, fully filling a 32bit word before
// moving onto the next one. On reads, pulls data back out in reverse
// order (to maintain SUMP client compatability). But really, backwards?!!?
//
//--------------------------------------------------------------------------------
//
`define BRAM_MAX_ADDRESS 6*1024-1 // 6K x 36
`define BRAM_MAXINDEX 12 // 12:0 = 8K
`define BRAM_MAXDATA 35
`timescale 1ns/100ps
module sram_interface #(
// memory parameters
parameter MSZ = 6*1024, // size (6K x 36bit)
//parameter MAW = $clog2(MSZ), // address width (13bit => 8K)
parameter MAW = 13, // address width (13bit => 8K)
parameter MDW = 32 // data width
)(
// system signals
input wire clk,
input wire rst,
// configuration/control signals
input wire wrFlags,
input wire [3:0] config_data,
// write interface
input wire write,
input wire lastwrite,
input wire [MDW-1:0] wrdata,
// read interface
input wire rd_ready,
output reg rd_valid,
output reg [3:0] rd_keep,
output wire [MDW-1:0] rd_data
);
//
// Registers...
//
reg init, next_init;
reg [1:0] mode, next_mode;
reg [3:0] validmask, next_validmask;
reg [3:0] clkenb, next_clkenb;
reg [MAW-1:0] address, next_address;
reg [3:0] next_rd_keep;
wire maxaddr = &address[MAW-1-2:0] & address[MAW-1]; // detect 0x17FF
wire addrzero = ~|address;
//
// Control logic...
//
initial
begin
init = 1'b0;
mode = 2'b00;
validmask = 4'hF;
clkenb = 4'b1111;
address = 0;
rd_keep = 4'b0000;
rd_valid = 1'b0;
end
always @ (posedge clk)
begin
init <= next_init;
mode <= next_mode;
validmask <= next_validmask;
clkenb <= next_clkenb;
address <= next_address;
rd_keep <= next_rd_keep;
rd_valid <=|next_rd_keep;
end
always @*
begin
next_init = 1'b0;
next_mode = mode;
next_validmask = validmask;
next_clkenb = clkenb;
next_address = address;
next_rd_keep = clkenb & validmask;
//
// Setup architecture of RAM based on which groups are enabled/disabled.
// If any one group is selected, 24k samples are possible.
// If any two groups are selected, 12k samples are possible.
// If three or four groups are selected, only 6k samples are possible.
//
if (wrFlags)
begin
next_init = 1'b1;
next_mode = 0; // 32 bit wide, 6k deep + 24 bit wide, 6k deep
case (config_data)
4'b1100, 4'b0011, 4'b0110, 4'b1001, 4'b1010, 4'b0101 : next_mode = 2'b10; // 16 bit wide, 12k deep
4'b1110, 4'b1101, 4'b1011, 4'b0111 : next_mode = 2'b01; // 8 bit wide, 24k deep
endcase
// The clkenb register normally indicates which bytes are valid during a read.
// However in 24-bit mode, all 32-bits of BRAM are being used. Thus we need to
// tweak things a bit. Since data is aligned (see data_align.v), all we need
// do is ignore the MSB here...
next_validmask = 4'hF;
case (config_data)
4'b0001, 4'b0010, 4'b0100, 4'b1000 : next_validmask = 4'h7;
endcase
end
//
// Handle writes & reads. Fill a given line of RAM completely before
// moving onward.
//
// This differs from the original SUMP storage which wrapped around
// before changing clock enables. Client sees no difference. However,
// it'll eventally allow easier streaming of data to the client...
//
casex ({write && !lastwrite, rd_ready})
2'b1x : // inc clkenb/address on all but last write (to avoid first read being bogus)...
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[2:0],clkenb[3]}; // 8 bit
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]}; // 16 bit
endcase
if (clkenb[3]) next_address = (maxaddr) ? 0 : address+1'b1;
end
2'bx1 :
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = {clkenb[0],clkenb[3:1]}; // 8 bit
2'b1x : next_clkenb = {clkenb[1:0],clkenb[3:2]}; // 16 bit
endcase
if (clkenb[0]) next_address = (addrzero) ? MSZ-1 : address-1'b1;
end
endcase
//
// Reset clock enables & ram address...
//
if (init)
begin
next_clkenb = 4'b1111;
casex (mode[1:0])
2'bx1 : next_clkenb = 4'b0001; // 1 byte writes
2'b1x : next_clkenb = 4'b0011; // 2 byte writes
endcase
next_address = 0;
end
end
//
// Prepare RAM input data. Present write data to all four lanes of RAM.
//
reg [MDW-1:0] ram_datain;
always @*
begin
ram_datain = wrdata;
casex (mode[1:0])
2'bx1 : ram_datain[31:0] = {wrdata[7:0],wrdata[7:0],wrdata[7:0],wrdata[7:0]}; // 8 bit memory
2'b1x : ram_datain[31:0] = {wrdata[15:0],wrdata[15:0]}; // 16 bit memory
endcase
end
//
// Instantiate RAM's (each BRAM6kx9bit in turn instantiates three 2kx9's block RAM's)...
//
`ifdef XC3S250E
genvar i;
generate
for (i=0; i<4; i=i+1) begin : mem
// byte wide memory array
reg [8-1:0] mem1 [0:2048-1];
reg [8-1:0] mem0 [0:4096-1];
reg [8-1:0] rd_data1;
reg [8-1:0] rd_data0;
reg adr_reg;
// write access
always @ (posedge clk) if (write & clkenb[i] & address[12]) mem1 [address[10:0]] <= ram_datain[i*8+:8];
always @ (posedge clk) if (write & clkenb[i] & ~address[12]) mem0 [address[10:0]] <= ram_datain[i*8+:8];
// read access
always @ (posedge clk) rd_data1 <= mem1 [address[10:0]];
always @ (posedge clk) rd_data0 <= mem0 [address[11:0]];
// multiplexer
always @ (posedge clk) adr_reg <= address[12];
assign rd_data [i*8+:8] = adr_reg ? rd_data1 : rd_data0;
end
endgenerate
`else
genvar i;
generate
for (i=0; i<4; i=i+1) begin : mem
// byte wide memory array
reg [8-1:0] mem [0:MSZ-1];
reg [8-1:0] mem_rdt;
// write access
always @ (posedge clk)
if (write & clkenb[i]) mem [address] <= ram_datain[i*8+:8];
// read access
always @ (posedge clk)
mem_rdt <= mem [address];
assign rd_data [i*8+:8] = mem_rdt;
end
endgenerate
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPADV2_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPADV2_PP_SYMBOL_V
/**
* top_power_hvc_wpadv2: A power pad with an ESD high-voltage clamp.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpadv2 (
//# {{data|Data Signals}}
inout P_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout VSWITCH ,
inout DRN_HVC ,
inout OGC_HVC ,
inout P_CORE ,
inout SRC_BDY_HVC,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPADV2_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_SYMBOL_V
`define SKY130_FD_SC_LP__OR2B_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_SYMBOL_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_rtc(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [31:0] io_regs_s_write_bits,
output [31:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [31:0] io_regs_cmp_0_write_bits,
output [31:0] io_regs_cmp_0_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0
);
wire [3:0] T_134;
reg [3:0] scale;
reg [31:0] GEN_7;
wire [3:0] GEN_0;
reg [31:0] cmp_0;
reg [31:0] GEN_8;
wire [31:0] GEN_1;
wire T_141;
wire AsyncResetRegVec_1_clock;
wire AsyncResetRegVec_1_reset;
wire AsyncResetRegVec_1_io_d;
wire AsyncResetRegVec_1_io_q;
wire AsyncResetRegVec_1_io_en;
wire countAlways;
reg [5:0] T_145;
reg [31:0] GEN_10;
wire [5:0] GEN_9;
wire [6:0] T_146;
reg [41:0] T_148;
reg [63:0] GEN_11;
wire T_149;
wire [42:0] T_151;
wire [42:0] GEN_2;
wire [47:0] T_152;
wire [15:0] T_155;
wire [47:0] T_156;
wire [41:0] T_157;
wire [47:0] GEN_3;
wire [42:0] GEN_4;
wire [31:0] T_160;
wire [63:0] T_161;
wire [57:0] T_162;
wire [63:0] GEN_5;
wire [57:0] GEN_6;
wire [47:0] T_163;
wire [31:0] s;
wire elapsed_0;
reg ip;
reg [31:0] GEN_12;
wire [8:0] T_191;
wire [11:0] T_194;
wire [3:0] T_196;
wire [4:0] T_198;
wire [12:0] T_199;
wire [16:0] T_200;
wire [28:0] T_201;
wire T_207_0;
sirv_AsyncResetRegVec AsyncResetRegVec_1 (
.clock(AsyncResetRegVec_1_clock),
.reset(AsyncResetRegVec_1_reset),
.io_d(AsyncResetRegVec_1_io_d),
.io_q(AsyncResetRegVec_1_io_q),
.io_en(AsyncResetRegVec_1_io_en)
);
assign io_regs_cfg_read = {{3'd0}, T_201};
assign io_regs_countLo_read = T_152[31:0];
assign io_regs_countHi_read = {{16'd0}, T_155};
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_207_0;
assign T_134 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_134 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign T_141 = io_regs_cfg_write_bits[12];
assign AsyncResetRegVec_1_clock = clock;
assign AsyncResetRegVec_1_reset = reset;
assign AsyncResetRegVec_1_io_d = T_141;
assign AsyncResetRegVec_1_io_en = io_regs_cfg_write_valid;
assign countAlways = AsyncResetRegVec_1_io_q;
assign GEN_9 = {{5'd0}, countAlways};
assign T_146 = T_145 + GEN_9;
assign T_149 = T_146[6];
assign T_151 = T_148 + 42'h1;
assign GEN_2 = T_149 ? T_151 : {{1'd0}, T_148};
assign T_152 = {T_148,T_145};
assign T_155 = T_152[47:32];
assign T_156 = {T_155,io_regs_countLo_write_bits};
assign T_157 = T_156[47:6];
assign GEN_3 = io_regs_countLo_write_valid ? T_156 : {{41'd0}, T_146};
assign GEN_4 = io_regs_countLo_write_valid ? {{1'd0}, T_157} : GEN_2;
assign T_160 = T_152[31:0];
assign T_161 = {io_regs_countHi_write_bits,T_160};
assign T_162 = T_161[63:6];
assign GEN_5 = io_regs_countHi_write_valid ? T_161 : {{16'd0}, GEN_3};
assign GEN_6 = io_regs_countHi_write_valid ? T_162 : {{15'd0}, GEN_4};
assign T_163 = T_152 >> scale;
assign s = T_163[31:0];
assign elapsed_0 = s >= cmp_0;
assign T_191 = {5'h0,scale};
assign T_194 = {3'h0,T_191};
assign T_196 = {3'h0,countAlways};
assign T_198 = {ip,4'h0};
assign T_199 = {T_198,8'h0};
assign T_200 = {T_199,T_196};
assign T_201 = {T_200,T_194};
assign T_207_0 = ip;
always @(posedge clock or posedge reset) begin
if(reset) begin
scale <= 4'b0;
cmp_0 <= 32'hFFFF_FFFF;
T_145 <= 6'b0;
T_148 <= 42'b0;
ip <= 1'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_134;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
T_145 <= GEN_5[5:0];
T_148 <= GEN_6[41:0];
ip <= elapsed_0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const long double PI = 3.141592653589793238462643383279502884197; long long fac[1] = {1}, inv[1] = {1}; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long mp(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret = ret * a % MOD; a = a * a % MOD; b >>= 1; } return ret; } long long cmb(long long r, long long c) { return fac[r] * inv[c] % MOD * inv[r - c] % MOD; } int n[3]; int vec[3][200]; long long dp[201][201][201]; long long go(int a, int b, int c) { if (dp[a][b][c] != -1) return dp[a][b][c]; long long mav = 0; int nn[3] = {a, b, c}; for (int i = 0; i < 3; i++) { int flag = 0; for (int j = 0; j < 3; j++) { if (i == j) continue; if (nn[j] == n[j]) flag = 1; } if (flag) continue; if (i == 0) mav = max(mav, go(a, b + 1, c + 1) + vec[1][b] * vec[2][c]); if (i == 1) mav = max(mav, go(a + 1, b, c + 1) + vec[0][a] * vec[2][c]); if (i == 2) mav = max(mav, go(a + 1, b + 1, c) + vec[0][a] * vec[1][b]); } return dp[a][b][c] = mav; } int main() { memset(dp, -1, sizeof(dp)); scanf( %d %d %d , &n[0], &n[1], &n[2]); for (int i = 0; i < 3; i++) { for (int j = 0; j < n[i]; j++) scanf( %d , &vec[i][j]); sort(vec[i], vec[i] + n[i], greater<long long>()); } long long ans = go(0, 0, 0); printf( %lld , ans); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:58:00 10/31/2016
// Module Name: I_EXECUTE_tb
// Project Name: MIPS
// Description: Testing the MIPS EX_MEM register implementation.
//
// Dependencies: I_EXECUTE.v
//
////////////////////////////////////////////////////////////////////////////////
module EX_MEM_tb;
// Inputs.
reg clk;
reg [1:0] ctlwb_out;
reg [2:0] ctlm_out;
reg [31:0] adder_out;
reg aluzero;
reg [31:0] aluout;
reg [31:0] readdat2;
reg [4:0] muxout;
// Outputs.
wire [1:0] wb_ctlout;
wire [2:0] m_ctlout;
wire [31:0] add_result;
wire zero;
wire [31:0] alu_result;
wire [31:0] rdata2out;
wire [4:0] five_bit_muxout;
// Instantiate the module.
EX_MEM ex_mem(.clk(clk), .ctlwb_out(ctlwb_out), .ctlm_out(ctlm_out),
.adder_out(adder_out), .aluzero(aluzero), .aluout(aluout),
.readdat2(readdat2), .muxout(muxout), .wb_ctlout(wb_ctlout),
.m_ctlout(m_ctlout), .add_result(add_result), .zero(zero),
.alu_result(alu_result), .rdata2out(rdata2out),
.five_bit_muxout(five_bit_muxout));
initial begin
// Initialize inputs.
clk = 0;
ctlwb_out = 0;
ctlm_out = 0;
adder_out = 0;
aluzero = 0;
aluout = 0;
readdat2 = 0;
muxout = 0;
// Wait 100 ns for global reset to finish.
#100;
$monitor("ctlwb_out = %b, ctlm_out = %b, adder_out = %b, ",
ctlwb_out, ctlm_out, adder_out,
"aluzero = %b, aluout = %b, readdat2 = %b, muxout = %b",
aluzero, aluout, readdat2, muxout);
ctlwb_out = 2'b01;
ctlm_out = 3'b101;
adder_out = 32'h00FF1133;
aluzero = 0;
aluout = 32'h00FFFFFF;
readdat2 = 32'h005100C3;
muxout = 4'b0101;
#20;
ctlwb_out = 2'b10;
ctlm_out = 3'b001;
adder_out = 32'h00FF1100;
aluzero = 0;
aluout = 32'h00FFFF23;
readdat2 = 32'h00F3DD10;
muxout = 4'b0011;
#20;
$finish;
end
always @ *
begin
#10 clk = ~clk;
end
endmodule
|
//deps: core.v, sdram_controller3.v, IS42S16160.v
`timescale 1ns/1ps
module top_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [12:0] DRAM_ADDR; // From controller of sdram_controller3.v
wire [1:0] DRAM_BA; // From controller of sdram_controller3.v
wire DRAM_CAS_N; // From controller of sdram_controller3.v
wire DRAM_CKE; // From controller of sdram_controller3.v
wire DRAM_CLK; // From controller of sdram_controller3.v
wire DRAM_CS_N; // From controller of sdram_controller3.v
wire [15:0] DRAM_DQ; // To/From controller of sdram_controller3.v
wire [1:0] DRAM_DQM; // From controller of sdram_controller3.v
wire DRAM_RAS_N; // From controller of sdram_controller3.v
wire DRAM_WE_N; // From controller of sdram_controller3.v
wire [16-1:0] Dq; // To/From memory of IS42S16160.v
wire [7:0] LED; // From core of core.v
wire [31:0] data_out; // From controller of sdram_controller3.v
wire data_valid; // From controller of sdram_controller3.v
wire [23:0] dram_addr; // From core of core.v
wire [31:0] dram_data_out; // From core of core.v
wire dram_req_read; // From core of core.v
wire dram_req_write; // From core of core.v
wire snd_out; // From core of core.v
wire [3:0] snd_signals; // From core of core.v
wire tx; // From core of core.v
wire write_complete; // From controller of sdram_controller3.v
wire [31:0] dram_data_in; // To core of core.v
wire dram_data_valid; // To core of core.v
wire dram_write_complete; // To core of core.v
wire req_read; // To controller of sdram_controller3.v
wire req_write; // To controller of sdram_controller3.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [13-1:0] Addr; // To memory of IS42S16160.v
reg [1:0] Ba; // To memory of IS42S16160.v
reg CLOCK_100; // To controller of sdram_controller3.v
reg CLOCK_100_del_3ns; // To controller of sdram_controller3.v
reg CLOCK_50; // To controller of sdram_controller3.v
reg Cas_n; // To memory of IS42S16160.v
reg Cke; // To memory of IS42S16160.v
reg Clk; // To memory of IS42S16160.v
reg Cs_n; // To memory of IS42S16160.v
reg [1:0] Dqm; // To memory of IS42S16160.v
reg Ras_n; // To memory of IS42S16160.v
reg We_n; // To memory of IS42S16160.v
reg [23:0] address; // To controller of sdram_controller3.v
reg clk; // To core of core.v
reg [31:0] data_in; // To controller of sdram_controller3.v
reg rst; // To controller of sdram_controller3.v
reg rx; // To core of core.v
reg [3:0] switches; // To core of core.v
wire rst_n;
assign rst_n = ~rst;
always @* begin
clk <= CLOCK_50;
end
// End of automatics
core core(
// Outputs
.LED (LED[7:0]),
.tx (tx),
.snd_out (snd_out),
.snd_signals (snd_signals[3:0]),
.dram_data_out (dram_data_in[31:0]),
.dram_addr (dram_addr[23:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.rst_n (rst_n),
.rx (rx),
.switches (switches[3:0]),
.dram_data_in (dram_data_out[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete (dram_write_complete));
sdram_controller3 controller(
// Outputs
.data_out (dram_data_out[31:0]),
.data_valid (dram_data_valid),
.write_complete (dram_write_complete),
.DRAM_ADDR (DRAM_ADDR[12:0]),
.DRAM_BA (DRAM_BA[1:0]),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQM (DRAM_DQM[1:0]),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N),
// Inouts
.DRAM_DQ (DRAM_DQ[15:0]),
// Inputs
.CLOCK_50 (CLOCK_50),
.CLOCK_100 (CLOCK_100),
.CLOCK_100_del_3ns(CLOCK_100_del_3ns),
.rst (rst),
.address (dram_addr[23:0]),
.req_read (dram_req_read),
.req_write (dram_req_write),
.data_in (dram_data_in[31:0]));
IS42S16160 memory(
// Inouts
.Dq (DRAM_DQ[16-1:0]),
// Inputs
.Addr (DRAM_ADDR[13-1:0]),
.Ba (DRAM_BA[1:0]),
.Clk (DRAM_CLK),
.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),
.Dqm (DRAM_DQM[1:0]));
initial begin
CLOCK_50 = 0;
CLOCK_100 = 0;
rst = 1;
$dumpfile("dump.vcd");
$dumpvars;
#9000 $finish;
end // initial begin
initial begin
#60 rst = 0;
end
always #10 CLOCK_50 <= ~CLOCK_50;
always #5 begin
CLOCK_100 <= ~CLOCK_100;
end
always @(CLOCK_100) begin
#3
CLOCK_100_del_3ns <= CLOCK_100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v[20001]; struct triplet { int x, y, z, sum; }; int a, b, c; void init() { for (int i = 1; i <= 20000; ++i) { for (int j = i; j <= 20000; j += i) v[j].push_back(i); } } triplet calc(int n) { triplet res; int ans = 1000000; for (int fac : v[n]) { int idx = lower_bound(v[fac].begin(), v[fac].end(), a) - v[fac].begin(); int idx1 = upper_bound(v[fac].begin(), v[fac].end(), a) - v[fac].begin(); if (idx1 != 0) idx1--; if (abs(v[fac][idx1] - a) < abs(v[fac][idx] - a)) idx = idx1; int val = abs(v[fac][idx] - a) + abs(fac - b) + abs(n - c); if (val < ans) { ans = val; res.x = v[fac][idx]; res.y = fac; res.z = n; res.sum = ans; } } return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); init(); int tc; cin >> tc; while (tc--) { cin >> a >> b >> c; int ans = 1000000; triplet fin; for (int i = 1; i <= 20000; ++i) { triplet res = calc(i); if (res.sum < ans) { ans = res.sum; fin.x = res.x; fin.y = res.y; fin.z = res.z; fin.sum = res.sum; } } cout << ans << n ; cout << fin.x << << fin.y << << fin.z << n ; } return 0; }
|
#include <bits/stdc++.h> int dx[4] = {-1, 0, 1, 0}; int dy[4] = {0, -1, 0, 1}; int n; int map[2010][2010]; int vis[2010][2010]; int as, ac; int go(int x, int y) { vis[y][x] = 1; int r = 1; for (int i = 0; i < 4; ++i) { int nx = x + dx[i], ny = y + dy[i]; if (map[ny][nx] == 0 || vis[ny][nx] == 1) continue; r += go(nx, ny); } return r; } int chk(int x, int y, int r) { int ok = 1; for (int i = y; i < y + r && ok == 1; ++i) for (int j = x; j < x + r && ok == 1; ++j) if (map[i][j] != 1) ok = 0; return ok == 1; } int main(void) { scanf( %d , &n); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) scanf( %d , &map[i][j]); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if (map[i][j] == 0 || vis[i][j] == 1) continue; int nd = go(j, i); int r = (int)sqrt(nd); if (nd != r * r) ++ac; else { if (chk(j, i, r) == 1) ++as; else ++ac; } } } printf( %d %d n , ac, as); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Iztok Jeras.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg alu_ltu, alu_lts;
logic [3:0] in_op1;
logic [3:0] in_op2;
reg aaa_ltu, aaa_lts;
always @(posedge clk) begin
in_op1 = 4'sb1110;
in_op2 = 4'b0010;
aaa_ltu = in_op1 < in_op2;
// bug999
aaa_lts = $signed(in_op1) < $signed(in_op2);
`checkh (aaa_ltu, 1'b0);
`checkh (aaa_lts, 1'b1);
end
generate if (1) begin
always @(posedge clk) begin
in_op1 = 4'sb1110;
in_op2 = 4'b0010;
alu_ltu = in_op1 < in_op2;
// bug999
alu_lts = $signed(in_op1) < $signed(in_op2);
`checkh (alu_ltu, 1'b0);
`checkh (alu_lts, 1'b1);
$write("*-* All Finished *-*\n");
$finish;
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double pi = 3.14159265358979323846; const long long mod = 1e9 + 7; const long long N = 5e5; const long long INF = 1e9 + 1; long long n, m, ans; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); std::cout.tie(0); cin >> n >> m; for (long long i = 1; i <= n; ++i) { long long a, b; cin >> a >> b; ans = max(ans, a + b); } cout << max(ans, m); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
* size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4_V
|
//==========================================================
// Copyright (c) 2014 by Cuong-TV
//==========================================================
// Project : Video and Image Processing Design Using FPGAs
// File name: CCD_Capture.v
// Author : Cuong-TV
// Email : -
//==========================================================
// Description
// Revision History :
// --------+----------------+-----------+--------------------------------+
// Ver | Author | Mod. Date | Changes Made: |
// --------+----------------+-----------+--------------------------------+
// V1.0 | Cuong-TV | 2014/11/1 | Initial Revision |
// --------+----------------+-----------+--------------------------------+
module CCD_Capture(
oYCbCr,
oDATA1,
oDATA2,
oDVAL,
oX_Cont,
oY_Cont,
oFrame_Cont,
// oPIXCLK,
iDATA,
iFVAL,
iLVAL,
iSTART,
iEND,
iCLK,
iRST );
output [15:0] oYCbCr;
reg [15:0] YCbCr;
reg [7:0] Cb;
reg [7:0] Cr;
assign oYCbCr = YCbCr;
input [7:0] iDATA;
input iFVAL;
input iLVAL;
input iSTART;
input iEND;
input iCLK;
input iRST;
output [7:0] oDATA1;
output [7:0] oDATA2;
//output oPIXCLK;
output [10:0] oX_Cont;
output [9:0] oY_Cont;
output [31:0] oFrame_Cont;
output oDVAL;
reg Pre_FVAL;
reg mCCD_FVAL;
reg mCCD_LVAL;
reg [7:0] mCCD_DATA1;
reg [7:0] mCCD_DATA2;
//reg PIXCLK;
reg [10:0] X_Cont;
reg [9:0] Y_Cont;
reg [31:0] Frame_Cont;
reg mSTART;
assign oX_Cont = X_Cont;
assign oY_Cont = Y_Cont;
assign oFrame_Cont = Frame_Cont;
assign oDATA1 = mCCD_DATA1;
assign oDATA2 = mCCD_DATA2;
//assign oPIXCLK = PIXCLK;
reg DVAL;
assign oDVAL = DVAL;
//assign oDVAL = mCCD_FVAL&mCCD_LVAL&X_Cont[0];
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mSTART <= 0;
else
begin
if(iSTART)
mSTART <= 1;
if(iEND)
mSTART <= 0;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Pre_FVAL <= 0;
mCCD_FVAL <= 0;
mCCD_LVAL <= 0;
X_Cont <= 0;
Y_Cont <= 0;
end
else
begin
Pre_FVAL <= iFVAL;
if({Pre_FVAL,iFVAL}==2'b01)
mCCD_FVAL <= 0;
else if(({Pre_FVAL,iFVAL}==2'b10)&& mSTART)
mCCD_FVAL <= 1;
///////////////////////////////////////
mCCD_LVAL <= iLVAL;
if(mCCD_FVAL && mCCD_LVAL)
begin
if(X_Cont<1279)
X_Cont <= X_Cont+1;
else
begin
X_Cont <= 0;
Y_Cont <= Y_Cont+1;
end
end
else
begin
X_Cont <= 0;
Y_Cont <= 0;
end
// check valid
///*
if(mCCD_FVAL && mCCD_LVAL && X_Cont[0])
DVAL <= 1'b1;
else
DVAL <= 1'b0;
//l*/
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
Frame_Cont <= 0;
else
begin
if( ({Pre_FVAL,iFVAL}==2'b10) && mSTART )
Frame_Cont <= Frame_Cont+1;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
mCCD_DATA1 <= 0;
mCCD_DATA2 <= 0;
YCbCr <= 0;
end
else if(iLVAL)
begin
if(!X_Cont[0])
mCCD_DATA1 <= iDATA;
else if(X_Cont[0])
mCCD_DATA2 <= iDATA;
case(X_Cont[1:0]) // Normal
0: Cb <= iDATA;
1: YCbCr <= {iDATA,Cb};
2: Cr <= iDATA;
3: YCbCr <= {iDATA,Cr};
endcase
end
else
begin
YCbCr <= 16'h0000;
mCCD_DATA1 <= 0;
mCCD_DATA2 <= 0;
end
end
/*
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
PIXCLK <= 1;
else
PIXCLK <= ~PIXCLK;
end
*/
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 1,
NUM_STAGE = 4,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_2_max_dsp_32 convolve_kernel_ap_fmul_2_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a, b, n, k, h; int main() { int arr[3]; cin >> arr[0] >> arr[1] >> arr[2]; int y = 1, b = 2, r = 3; while (y < arr[0] && b < arr[1] && r < arr[2]) { y++; r++; b++; } cout << y + b + r; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, flag = 1; char ch = getchar(); for (; ch > 9 || ch < 0 ; ch = getchar()) if (ch == - ) flag = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = (x << 3) + (x << 1) + ch - 0 ; return x * flag; } const int MAXN = 2e5 + 50, B = 317, INF = 998244353; int n, m, Ans[MAXN], rt, cnt = 0; int XX[MAXN], YY[MAXN], DY[MAXN], Cl = 0; struct Point { int x, y, id; } P[MAXN]; struct Ques { int X1, Y1, X2, Y2, id, h; } Q[MAXN]; struct Tree { int X, Y, Min, ls, rs, dat, fa; int mx[2], my[2]; void clean() { X = Y = ls = rs = mx[1] = my[1] = 0; mx[0] = my[0] = dat = Min = INF; } } T[MAXN]; int MIN(int a, int b) { return a < b ? a : b; } bool cmp3(Point a, Point b) { return a.y < b.y; } bool cmp2(Point a, Point b) { return a.x < b.x; } bool cmp(Ques a, Ques b) { return a.h < b.h; } void update(int cur) { T[cur].Min = MIN(T[T[cur].rs].Min, T[T[cur].ls].Min); T[cur].Min = MIN(T[cur].Min, T[cur].dat); T[cur].mx[0] = MIN(MIN(T[T[cur].rs].mx[0], T[T[cur].ls].mx[0]), T[cur].mx[0]); T[cur].my[0] = MIN(MIN(T[T[cur].rs].my[0], T[T[cur].ls].my[0]), T[cur].my[0]); T[cur].mx[1] = max(max(T[T[cur].rs].mx[1], T[T[cur].ls].mx[1]), T[cur].mx[1]); T[cur].my[1] = max(max(T[T[cur].rs].my[1], T[T[cur].ls].my[1]), T[cur].my[1]); } void build(int &cur, int L, int R, int D, int fa) { if (L > R) return; if (!cur) cur = ++cnt; int mid = (L + R) >> 1; T[cur].fa = fa; if (L == R) { int x = P[L].x, y = P[L].y; T[cur].mx[0] = T[cur].mx[1] = T[cur].X = x; T[cur].my[0] = T[cur].my[1] = T[cur].Y = y; T[cur].dat = T[cur].Min = P[L].id; DY[P[L].id] = cur; return; } if (D == 0) nth_element(P + L, P + mid, P + 1 + R, cmp2); else nth_element(P + L, P + mid, P + 1 + R, cmp3); T[cur].dat = P[mid].id, T[cur].X = P[mid].x, T[cur].Y = P[mid].y; T[cur].mx[0] = T[cur].mx[1] = T[cur].X; T[cur].my[0] = T[cur].my[1] = T[cur].Y; DY[P[mid].id] = cur; build(T[cur].ls, L, mid - 1, D ^ 1, cur); build(T[cur].rs, mid + 1, R, D ^ 1, cur); update(cur); return; } bool out(int x, int X1, int Y1, int X2, int Y2) { return (T[x].mx[0] > X2 || T[x].mx[1] < X1 || T[x].my[0] > Y2 || T[x].my[1] < Y1); } bool in(int x, int X1, int Y1, int X2, int Y2) { return (T[x].mx[0] >= X1 && T[x].mx[1] <= X2 && T[x].my[0] >= Y1 && T[x].my[1] <= Y2); } int query(int now, int X1, int Y1, int X2, int Y2) { int Min = INF; if (T[now].X >= X1 && T[now].Y >= Y1 && T[now].X <= X2 && T[now].Y <= Y2) Min = T[now].dat; if (out(now, X1, Y1, X2, Y2) || !now) return Min; if (in(now, X1, Y1, X2, Y2)) return min(T[now].Min, T[now].dat); if (T[now].ls) Min = MIN(Min, query(T[now].ls, X1, Y1, X2, Y2)); if (T[now].rs) Min = MIN(Min, query(T[now].rs, X1, Y1, X2, Y2)); return Min; } void Go(int x, int t) { if (!x) return; if (T[x].dat == t) T[x].dat = INF; update(x); Go(T[x].fa, t); return; } void clean() { for (int i = 1; i <= cnt; i++) T[i].clean(); cnt = 0; } int main() { n = read(); T[0].clean(); for (int i = 1; i <= n; i++) Ans[i] = -1; for (int i = 1; i <= n; i++) { Q[i].X1 = read(), Q[i].X2 = read(); Q[i].Y1 = read(), Q[i].Y2 = read(); Q[i].h = read(), Q[i].id = i; } rt = 0; m = read(); sort(Q + 1, Q + 1 + n, cmp); for (int i = 1; i <= m; i++) { XX[i] = P[i].x = read(), YY[i] = P[i].y = read(); P[i].id = i; } build(rt, 1, m, 0, 0); for (int i = 1; i <= n; i++) { int t = query(rt, Q[i].X1, Q[i].Y1, Q[i].X2, Q[i].Y2); if (t == 998244353 || !t) continue; Ans[t] = Q[i].id, Go(DY[t], t); } for (int i = 1; i <= m; i++) printf( %d n , max(Ans[i], 0)); return 0; }
|
module Memory_TestBench;
reg clk, cs, we;
reg [31:0] addr, data_i;
integer i;
parameter mem_size = 5;
DRAM #(.mem_size(mem_size), .delay(0)) mem_dut
(
.clk (clk),
.addr_i (addr),
.cs (cs),
.we (we),
.data_i (data_i),
.data_o (),
.ack ()
);
// The clock pulse.
initial begin
clk = 0;
forever #10
clk = ~clk;
end
// Reset the memory and control signals.
initial begin
for(i = 0; i < mem_size; i = i+1) begin
mem_dut.memory[i] = 32'b0;
end
i = 0;
cs = 0;
we = 0;
data_i = 32'bz;
end
// Stimulus
always @ (posedge clk) begin
if(i < 30) begin
if(i > 15)
addr = 32'h01;
end else if(i < 60) begin
if(i > 46) begin
cs = 0;
we = 0;
end else if(i > 45) begin
cs = 1;
we = 0;
end
end else if(i < 90) begin
if(i > 75)
data_i = 42;
end else if(i < 120) begin
if(i > 106) begin
cs = 0;
we = 0;
end else if(i > 105) begin
cs = 0;
we = 1;
end
end else if(i < 150) begin
if(i > 136) begin
cs = 0;
we = 0;
end else if(i > 135) begin
cs = 1;
we = 1;
end
end else if(i < 180) begin
cs = 0;
we = 0;
end else if(i < 210) begin
if(i > 196)
cs = 0;
else if(i > 195)
cs = 1;
end else if(i < 240) begin
cs = 0;
end else
$stop;
i = i+1;
end
endmodule
|
`include "senior_defines.vh"
module operand_select
#(parameter nat_w=`SENIOR_NATIVE_WIDTH,
parameter ctrl_w=`OPSEL_CTRL_WIDTH)
(
input wire [nat_w-1:0] imm_val_i,
input wire [nat_w-1:0] rf_a_i,
input wire [nat_w-1:0] rf_b_i,
input wire [ctrl_w-1:0] ctrl_i,
output reg [nat_w-1:0] op_a_o,
output reg [nat_w-1:0] op_b_o);
`include "std_messages.vh"
always@* begin
case(ctrl_i`OPSEL_OPA)
0: op_a_o = rf_a_i;
1: op_a_o = rf_b_i;
2: op_a_o = imm_val_i;
default: begin
op_a_o = rf_a_i;
if(defined_but_illegal(ctrl_i`OPSEL_OPA,2,"ctrl_i`OPSEL_OPA")) begin
$stop;
end
end
endcase // case(ctrl_i`OPSEL_OPA)
end
always@* begin
case(ctrl_i`OPSEL_OPB)
0: op_b_o = rf_b_i;
1: op_b_o = rf_a_i;
2: op_b_o = imm_val_i;
default: begin
op_b_o = rf_b_i;
if(defined_but_illegal(ctrl_i`OPSEL_OPB,2,"ctrl_i`OPSEL_OPB")) begin
$stop;
end
end
endcase // case(ctrl_i`OPSEL_OPB)
end
endmodule // operand_select
|
`define bsg_dff_en_macro(bits,womp) \
if (harden_p && width_p==bits && (strength_p==womp)) \
begin: macro \
bsg_rp_tsmc_250_EDFFX``womp``_b``bits dff(.i0(data_i) \
,.i1({ width_p { en_i } }) \
,.i2({ width_p {clock_i} }) \
,.o(data_o) \
); \
end
module bsg_dff_en #(width_p="inv"
, harden_p=1
, strength_p=1
)
(input clock_i
,input [width_p-1:0] data_i
,input en_i
,output [width_p-1:0] data_o
);
`bsg_dff_en_macro(40,1) else
`bsg_dff_en_macro(39,1) else
`bsg_dff_en_macro(38,1) else
`bsg_dff_en_macro(37,1) else
`bsg_dff_en_macro(36,1) else
`bsg_dff_en_macro(35,1) else
`bsg_dff_en_macro(34,1) else
`bsg_dff_en_macro(33,1) else
`bsg_dff_en_macro(32,1) else
`bsg_dff_en_macro(31,1) else
`bsg_dff_en_macro(30,1) else
`bsg_dff_en_macro(29,1) else
`bsg_dff_en_macro(28,1) else
`bsg_dff_en_macro(27,1) else
`bsg_dff_en_macro(26,1) else
`bsg_dff_en_macro(25,1) else
`bsg_dff_en_macro(24,1) else
`bsg_dff_en_macro(23,1) else
`bsg_dff_en_macro(22,1) else
`bsg_dff_en_macro(21,1) else
`bsg_dff_en_macro(20,1) else
`bsg_dff_en_macro(19,1) else
`bsg_dff_en_macro(18,1) else
`bsg_dff_en_macro(17,1) else
`bsg_dff_en_macro(16,1) else
`bsg_dff_en_macro(15,1) else
`bsg_dff_en_macro(14,1) else
`bsg_dff_en_macro(13,1) else
`bsg_dff_en_macro(12,1) else
`bsg_dff_en_macro(11,1) else
`bsg_dff_en_macro(10,1) else
`bsg_dff_en_macro(9,1) else
`bsg_dff_en_macro(8,1) else
`bsg_dff_en_macro(7,1) else
`bsg_dff_en_macro(6,1) else
`bsg_dff_en_macro(5,1) else
`bsg_dff_en_macro(4,1) else
`bsg_dff_en_macro(3,1) else
`bsg_dff_en_macro(2,1) else
`bsg_dff_en_macro(1,1) else
`bsg_dff_en_macro(40,2) else
`bsg_dff_en_macro(39,2) else
`bsg_dff_en_macro(38,2) else
`bsg_dff_en_macro(37,2) else
`bsg_dff_en_macro(36,2) else
`bsg_dff_en_macro(35,2) else
`bsg_dff_en_macro(34,2) else
`bsg_dff_en_macro(33,2) else
`bsg_dff_en_macro(32,2) else
`bsg_dff_en_macro(31,2) else
`bsg_dff_en_macro(30,2) else
`bsg_dff_en_macro(29,2) else
`bsg_dff_en_macro(28,2) else
`bsg_dff_en_macro(27,2) else
`bsg_dff_en_macro(26,2) else
`bsg_dff_en_macro(25,2) else
`bsg_dff_en_macro(24,2) else
`bsg_dff_en_macro(23,2) else
`bsg_dff_en_macro(22,2) else
`bsg_dff_en_macro(21,2) else
`bsg_dff_en_macro(20,2) else
`bsg_dff_en_macro(19,2) else
`bsg_dff_en_macro(18,2) else
`bsg_dff_en_macro(17,2) else
`bsg_dff_en_macro(16,2) else
`bsg_dff_en_macro(15,2) else
`bsg_dff_en_macro(14,2) else
`bsg_dff_en_macro(13,2) else
`bsg_dff_en_macro(12,2) else
`bsg_dff_en_macro(11,2) else
`bsg_dff_en_macro(10,2) else
`bsg_dff_en_macro(9,2) else
`bsg_dff_en_macro(8,2) else
`bsg_dff_en_macro(7,2) else
`bsg_dff_en_macro(6,2) else
`bsg_dff_en_macro(5,2) else
`bsg_dff_en_macro(4,2) else
`bsg_dff_en_macro(3,2) else
`bsg_dff_en_macro(2,2) else
`bsg_dff_en_macro(1,2) else
`bsg_dff_en_macro(40,4) else
`bsg_dff_en_macro(39,4) else
`bsg_dff_en_macro(38,4) else
`bsg_dff_en_macro(37,4) else
`bsg_dff_en_macro(36,4) else
`bsg_dff_en_macro(35,4) else
`bsg_dff_en_macro(34,4) else
`bsg_dff_en_macro(33,4) else
`bsg_dff_en_macro(32,4) else
`bsg_dff_en_macro(31,4) else
`bsg_dff_en_macro(30,4) else
`bsg_dff_en_macro(29,4) else
`bsg_dff_en_macro(28,4) else
`bsg_dff_en_macro(27,4) else
`bsg_dff_en_macro(26,4) else
`bsg_dff_en_macro(25,4) else
`bsg_dff_en_macro(24,4) else
`bsg_dff_en_macro(23,4) else
`bsg_dff_en_macro(22,4) else
`bsg_dff_en_macro(21,4) else
`bsg_dff_en_macro(20,4) else
`bsg_dff_en_macro(19,4) else
`bsg_dff_en_macro(18,4) else
`bsg_dff_en_macro(17,4) else
`bsg_dff_en_macro(16,4) else
`bsg_dff_en_macro(15,4) else
`bsg_dff_en_macro(14,4) else
`bsg_dff_en_macro(13,4) else
`bsg_dff_en_macro(12,4) else
`bsg_dff_en_macro(11,4) else
`bsg_dff_en_macro(10,4) else
`bsg_dff_en_macro(9,4) else
`bsg_dff_en_macro(8,4) else
`bsg_dff_en_macro(7,4) else
`bsg_dff_en_macro(6,4) else
`bsg_dff_en_macro(5,4) else
`bsg_dff_en_macro(4,4) else
`bsg_dff_en_macro(3,4) else
`bsg_dff_en_macro(2,4) else
`bsg_dff_en_macro(1,4) else
begin : notmacro
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clock_i)
if (en_i)
data_r <= data_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_en)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:30:50 05/08/2015
// Design Name:
// Module Name: hazard
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hazard(
// d
input [2:0] reg_read_adr1_d,
input [2:0] reg_read_adr2_d,
// e
input [2:0] reg_read_adr1_e,
input [2:0] reg_read_adr2_e,
input [2:0] reg_write_adr_e,
input mem_to_reg_e,
// m
input reg_write_m,
input [2:0] reg_write_adr_m,
// w
input reg_write_w,
input [2:0] reg_write_adr_w,
input PC_source,
// f
output reg stall_f,
//d
output reg stall_d,
output reg flush_d,
// e
output reg flush_e,
output reg [1:0] forward1_e,
output reg [1:0] forward2_e
);
always @(*) begin
// Forward
if ((reg_write_adr_m == reg_read_adr1_e) && reg_write_m)
forward1_e = 2'h1;
else if ((reg_write_adr_w == reg_read_adr1_e) && reg_write_w)
forward1_e = 2'h2;
else
forward1_e = 2'h0;
if ((reg_write_adr_m == reg_read_adr2_e) && reg_write_m)
forward2_e = 2'h1;
else if ((reg_write_adr_w == reg_read_adr2_e) && reg_write_w)
forward2_e = 2'h2;
else
forward2_e = 2'h0;
end
reg stallCompare;
// Stall
always @(*) begin
// LD stall
if ((reg_write_adr_e == reg_read_adr1_d) || (reg_write_adr_e == reg_read_adr2_d))
stallCompare <= 1;
else
stallCompare <= 0;
stall_f <= stallCompare && mem_to_reg_e;
stall_d <= stallCompare && mem_to_reg_e;
flush_e <= stallCompare && mem_to_reg_e;
// Branch stall
flush_d <= PC_source;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__HA_BEHAVIORAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <typename... T> void read(T &...args) { ((cin >> args), ...); } template <typename... T> void write(T... args) { ((cout << args << ), ...); cout << n ; } long long gcd(long long a, long long b) { if (b > a) { return gcd(b, a); } if (b == 0) { return a; } return gcd(b, a % b); } long long add(long long a, long long b) { a = a % 1000000007; b = b % 1000000007; return (((a + b) % 1000000007) + 1000000007) % 1000000007; } long long sub(long long a, long long b) { a = a % 1000000007; b = b % 1000000007; return (((a - b) % 1000000007) + 1000000007) % 1000000007; } long long mul(long long a, long long b) { a = a % 1000000007; b = b % 1000000007; return (((a * b) % 1000000007) + 1000000007) % 1000000007; } long long power(long long x, long long y) { long long res = 1; x = x % 1000000007; if (x == 0) return 0; while (y > 0) { if (y & 1) { res = (res * x) % 1000000007; } y = y >> 1; x = (x * x) % 1000000007; } return res; } long long find(vector<long long> &parent, long long x) { if (parent[x] != x) parent[x] = find(parent, parent[x]); return parent[x]; } void join(vector<long long> &parent, vector<long long> &rank, long long x, long long y) { long long xParent = find(parent, x); long long yParent = find(parent, y); if (xParent == yParent) return; if (rank[xParent] > rank[yParent]) { parent[yParent] = xParent; } else if (rank[xParent] < rank[yParent]) { parent[xParent] = yParent; } else { parent[xParent] = yParent; rank[yParent]++; } } void solve() { long long n, m, k; read(n, m, k); vector<vector<long long> > mat(n, vector<long long>(m, 0)); for (long long i = 0; i < n; i++) { string str; cin >> str; for (long long j = 0; j < m; j++) { if (str[j] == * ) mat[i][j] = 1; } } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (mat[i][j] == 0) continue; long long len = 0; while (j - len >= 0 && i - len >= 0 && j + len < m) { if (mat[i - len][j - len] == 0 || mat[i - len][j + len] == 0) break; len++; } len--; if (len >= k) { for (long long p = 0; p < len + 1; p++) { mat[i - p][j - p] = 2; mat[i - p][j + p] = 2; } } } } bool found = false; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (mat[i][j] == 1) found = true; } } if (found) write( NO ); else write( YES ); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long iter; cin >> iter; while (iter) { solve(); iter--; } }
|
#include <bits/stdc++.h> int main() { long int a, i, s; scanf( %ld , &a); s = a; if (a != 1) { for (i = 2;; i++) { s = s + 1 + i * (a - i); if ((a - i) == 0) { break; } } printf( %ld , s); } else { printf( 1 ); } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 09:37:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_stub.v
// Design : system_inverter_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_1_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
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