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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int v[26][N]; int main() { int n; cin >> n; string s; for (int i = 0; i < n; ++i) { cin >> s; for (int j = 0; j < s.size(); j++) if (s[j] != ? ) v[s[j] - a ][j]++; } string ans = ; int pos = 0; for (int i = 0; i < s.size(); ++i) { int may = 0; for (int j = 0; j < 26; j++) { if (may < v[j][i]) { may = v[j][i]; pos = j; } } int a1 = 0; bool flag = 0; char x = * ; for (int j = 0; j < 26; j++) { if (may == v[j][i] or (v[j][i] != may && v[j][i])) a1++, flag = 1; if (flag && !v[j][i]) { if (a1 <= 1) x = j; flag = 0; } } if (a1 == 1) ans += char(pos) + a ; else { if (may != 0) ans += ? ; else ans += char(x) + a ; } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 400000 + 10; const int M = 26; namespace Trie { int trie[N][M], cnt[N], size; void init() { size = 0; memset(trie[0], 0, sizeof(trie[0])); cnt[0] = 0; } void insert(char str[]) { int u = 0, v; for (int i = 0; str[i]; i++) { v = str[i] - a ; if (!trie[u][v]) { trie[u][v] = ++size; cnt[size] = 0; memset(trie[size], 0, sizeof(trie[size])); } u = trie[u][v]; } cnt[u]++; } } // namespace Trie namespace SAM { struct state { int len, link, siz; int next[M]; } st[N]; int sz, last; void init() { sz = 1, last = 0; st[0].len = 0; st[0].link = -1; } void add(int c) { int r = sz++; st[r].len = st[last].len + 1; st[r].siz = 1; int p = last; while (p != -1 && !st[p].next[c]) st[p].next[c] = r, p = st[p].link; if (p == -1) st[r].link = 0; else { int q = st[p].next[c]; if (st[q].len == st[p].len + 1) st[r].link = q; else { int qq = sz++; st[qq].link = st[q].link; memcpy(st[qq].next, st[q].next, sizeof(st[q].next)); st[qq].len = st[p].len + 1; st[qq].siz = 0; while (p != -1 && st[p].next[c] == q) st[p].next[c] = qq, p = st[p].link; st[q].link = st[r].link = qq; } } last = r; } int tp[N], tmp[N]; void get_topo() { memset(tmp, 0, sizeof(tmp)); for (int i = 0; i < sz; i++) tmp[st[i].len]++; for (int i = 1; i < sz; i++) tmp[i] += tmp[i - 1]; for (int i = 0; i < sz; i++) tp[--tmp[st[i].len]] = i; } void calc_siz() { get_topo(); for (int i = sz - 1; i > 0; i--) st[st[tp[i]].link].siz += st[tp[i]].siz; st[0].siz = 0; } } // namespace SAM long long dfs(int tu, int su) { long long ans = 1ll * Trie::cnt[tu] * SAM::st[su].siz; for (int i = 0; i < M; i++) { int tv = Trie::trie[tu][i]; int sv = SAM::st[su].next[i]; if (tv == 0 || sv == 0) continue; ans += dfs(tv, sv); } return ans; } int id[N]; void ddfs(int i) { if (id[i] == -1) return; for (int j = 0; j < M; j++) { int v = Trie::trie[i][j]; if (v) { id[v] = SAM::st[id[i]].next[j]; if (id[v] == 0) id[v]--; ddfs(v); } } } char s[N]; int main() { SAM::init(), Trie::init(); scanf( %s , s); for (int i = 0; s[i]; i++) SAM::add(s[i] - a ); SAM::calc_siz(); int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , s); Trie::insert(s); } ddfs(0); long long ans = 0; for (int i = 0; i <= Trie::size; i++) { if (id[i] <= 0) continue; if (Trie::cnt[i]) ans += 1ll * Trie::cnt[i] * dfs(0, id[i]); } printf( %lld n , ans); }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module fifo_xlnx_2Kx36_2clk(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
rd_data_count,
wr_data_count);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
output [11 : 0] rd_data_count;
output [11 : 0] wr_data_count;
// synthesis translate_off
FIFO_GENERATOR_V4_3 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(12),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(36),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(36),
.C_ENABLE_RLOCS(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("2kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(2047),
.C_PROG_FULL_THRESH_NEGATE_VAL(2046),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(12),
.C_RD_DEPTH(2048),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(11),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(12),
.C_WR_DEPTH(2048),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(11),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.UNDERFLOW(),
.WR_ACK(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box"
endmodule
|
module peripheral_ultrsnd (clk , reset , d_in , cs , addr , rd , wr, d_out, echo, done, trigger, [15:0]distance);
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
input echo;
output trigger
//------------------------------------ regs and wires-------------------------------
//selector mux_4 and write registers
reg [5:0] s;
//---mult_32 input registers--//
reg echo = 0;
reg trigger = 0;
//---mult_32 output Regs-----//
wire [15:0]distance;
wire done;
//------------------------------------ regs and wires-------------------------------
ultrasonido (.clk(clk),.reset(reset),.echo(echo),.trigger(trigger),.done(done),.distance(distance));
//----------------address_decoder-------------------//
always @(*) begin
case (addr)
4'h0:begin s = (cs && wr) ? 6'b000001 : 6'b000000; end //echo
4'h2:begin s = (cs && wr) ? 6'b000010 : 6'b000000; end //trigger
4'h4:begin s = (cs && wr) ? 6'b000100 : 6'b000000; end //distance
4'h6:begin s = (cs && rd) ? 6'b001000 : 6'b000000; end //done
default:begin s = 6'b000000 ; end
endcase
end
//------------------address_decoder-----------------//
//-----------------escritura de registros
always @(negedge clk) begin
echo = (s[0]) ? d_in : echo; //Write Registers
trigger = (s[1]) ? d_in[0] : trigger; //Write Registers
end
//-----------------escritura de registros
//----------------mux_4 : multiplexa salidas del periferico
always @(negedge clk) begin
case (s[5:3])
4'b1000: d_out[0] = done;
4'b0100: d_out = [15:0]distance;
default: d_out = 0 ;
endcase
end
//----------------mux_4
endmodule
|
#include <bits/stdc++.h> template <typename T> inline bool MIN(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool MAX(T &a, const T &b) { return a < b ? a = b, 1 : 0; } using namespace std; int n, m, K, p; int exgcd(int a, int b, int &x, int &y) { if (b == 0) { x = 1, y = 0; return a; } int res = exgcd(b, a % b, x, y); int t = x; x = y; y = t - a / b * y; return res; } int get_inv(int a) { int x, y; exgcd(a, 1000000007, x, y); return (x % 1000000007 + 1000000007) % 1000000007; } int P[100010], sum_P[100010]; int g[1510][1510], sum[1510][1510]; int main() { scanf( %d%d , &n, &m); int a, b; scanf( %d%d , &a, &b); p = (long long)a * get_inv(b) % 1000000007; scanf( %d , &K); int pow2 = 1; for (int i = 1; i <= K; ++i) pow2 = (long long)pow2 * (1 - p + 1000000007) % 1000000007; for (int i = 0, pow = 1, c = 1; i <= K; ++i) { if (i == K && p == 1) pow2 = 1; P[i] = (long long)c * pow % 1000000007 * pow2 % 1000000007; pow2 = (long long)pow2 * get_inv((1 - p + 1000000007) % 1000000007) % 1000000007; pow = (long long)pow * p % 1000000007; c = (long long)c * (K - i) % 1000000007 * get_inv(i + 1) % 1000000007; } sum_P[0] = P[0]; for (int i = 1; i <= m; ++i) sum_P[i] = (sum_P[i - 1] + P[i]) % 1000000007; g[0][m] = sum[0][m] = 1; for (int i = 1; i <= n; ++i) { int tmp = 0; for (int j = 1; j <= m; ++j) { tmp = (tmp + (long long)P[j - 1] * sum[i - 1][j - 1]) % 1000000007; g[i][j] = ((long long)sum_P[j - 1] * (sum[i - 1][m] - sum[i - 1][m - j] + 1000000007) - tmp + 1000000007) % 1000000007; g[i][j] = (long long)g[i][j] * P[m - j] % 1000000007; sum[i][j] = (sum[i][j - 1] + g[i][j]) % 1000000007; } } printf( %d n , sum[n][m]); return 0; }
|
//
// Copyright (c) 2012 Simon W. Moore
// Copyright (c) 2013 Jonathan Woodruff
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
module ISP1761_IF(
// SWM: clock and reset keep Qsys happy though they are not used
csi_clk,
csi_reset_n,
// host controller slave port
s_cs_n,
s_address,
s_write_n,
s_writedata,
s_read_n,
s_readdata,
s_hc_irq,
// device controller
s_dc_irq,
s_dc_readdata,
// exported to ISP1761 I/O pins
CS_N,
WR_N,
RD_N,
D,
A,
DC_IRQ,
HC_IRQ,
DC_DREQ,
HC_DREQ,
DC_DACK,
HC_DACK
);
input csi_clk;
input csi_reset_n;
// slave host controller
input s_cs_n;
input [15:0] s_address;
input s_write_n;
input [31:0] s_writedata;
input s_read_n;
output [31:0] s_readdata;
output s_hc_irq;
// dummy (don't support device controller)
output s_dc_irq;
output [31:0] s_dc_readdata;
// exported
output CS_N;
output WR_N;
output RD_N;
inout [31:0] D;
output [17:1] A;
input DC_IRQ;
input HC_IRQ;
input DC_DREQ;
input HC_DREQ;
output DC_DACK;
output HC_DACK;
assign CS_N = s_cs_n;
assign WR_N = s_write_n;
assign RD_N = s_read_n;
assign A = {s_address[15:0],1'b0};
assign s_hc_irq = HC_IRQ;
assign s_dc_irq = DC_IRQ;
assign D = (!s_cs_n & s_read_n) ? s_writedata : 32'hzzzzzzzz;
assign s_readdata = D;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3f; const int mod = 1000000007; const double eps = 1e-6; const double PI = acos(-1); int tar, n, tot, a[N], hs[N], cnt[N], mx[N], now[N]; vector<int> vc; bool check(int add) { vc.clear(); int c = tar; int p = mx[c]; while (c) { if (add > c) add = 0; while (!now[p] && p) p--; p = min(p, mx[c]); if (!p && !add) break; if (p && hs[p] >= add) { vc.push_back(p); int v = hs[p], num = min(now[p], c / v); now[p] -= num; c -= num * v; } else { c -= add; add = 0; } } for (auto& x : vc) now[x] = cnt[x]; return c; } int main() { scanf( %d%d , &tar, &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); hs[++tot] = a[i]; } sort(hs + 1, hs + tot + 1); tot = unique(hs + 1, hs + tot + 1) - hs - 1; for (int i = 1; i <= n; i++) cnt[lower_bound(hs + 1, hs + tot + 1, a[i]) - hs]++; for (int i = 1; i <= tot; i++) now[i] = cnt[i]; for (int i = 1; i <= tar; i++) mx[i] = upper_bound(hs + 1, hs + tot + 1, i) - hs - 1; for (int i = 1; i <= tar; i++) { if (check(i)) { printf( %d n , i); return 0; } } puts( Greed is good ); return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k; cin >> n >> k; map<char, long long> mp; for (long long i = 0; i < n; i++) { char x; cin >> x; mp[x]++; } vector<pair<long long, char>> v; for (auto it : mp) { pair<long long, char> p; p.first = it.second; p.second = it.first; v.push_back(p); } sort(v.begin(), v.end(), greater<pair<long long, char>>()); long long ans = 0; for (long long i = 0; i < v.size() && k > 0; i++) { long long x = min(k, v[i].first); ans += (x * x); k -= x; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) const long long INF = 0x3f3f3f3f3f3f3f3f; const long long llinf = (1LL << 62); const int inf = (1 << 30); const long long nmax = 5e5 + 50; const int mod = 1e9 + 7; using namespace std; int n, m, i, x, a[nmax], p[nmax], q, st[4 * nmax], ans[nmax], j; long long nr[nmax], k; vector<int> b[nmax]; vector<pair<int, int> > qr[nmax]; pair<int, int> pr; pair<int, int> fnd(long long y) { int l = 0, r = n, mid, rs = n, i; while (l <= r) { mid = (l + r) / 2; if (nr[mid] > y) rs = mid, r = mid - 1; else l = mid + 1; } for (i = max(rs - 1, 0); i <= min(rs + 1, n); i++) if (nr[i] >= y) break; rs = i; if (rs <= n) { if (rs) y -= nr[rs - 1]; return make_pair(rs, y); } else { y -= nr[n]; if (y % m == 0) return make_pair(m, -1); return make_pair(y % m, -1); } } void upd(int nod, int l, int r, int p) { if (l == r) { st[nod] = 1; return; } int mid = (l + r) / 2; if (p <= mid) upd(2 * nod, l, mid, p); else upd(2 * nod + 1, mid + 1, r, p); st[nod] = st[2 * nod] + st[2 * nod + 1]; } int qry(int nod, int l, int r, int z) { if (z > st[nod]) return -1; if (l == r) return l; int mid = (l + r) / 2; if (st[nod * 2] >= z) return qry(2 * nod, l, mid, z); return qry(2 * nod + 1, mid + 1, r, z - st[nod * 2]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n >> m >> q; for (i = 1; i <= n; i++) { cin >> x; a[x]++; } for (i = 1; i <= m; i++) { nr[a[i]]++; b[a[i]].push_back(i); } p[0] = b[0].size(); for (i = 1; i <= n; i++) p[i] = p[i - 1] + b[i].size(); for (i = 1; i <= n; i++) nr[i] += nr[i - 1]; for (i = 1; i <= n; i++) nr[i] += nr[i - 1]; for (i = 1; i <= q; i++) { cin >> k; k -= n; pr = fnd(k); if (pr.second == -1) ans[i] = pr.first; else qr[pr.first].push_back(make_pair(pr.second, i)); } for (i = 0; i <= n; i++) { for (j = 0; j < b[i].size(); j++) upd(1, 1, m, b[i][j]); for (j = 0; j < qr[i].size(); j++) ans[qr[i][j].second] = qry(1, 1, m, qr[i][j].first); } for (i = 1; i <= q; i++) cout << ans[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int a[200000 + 5]; vector<int> g[200000 + 5]; int cnt = 0; void dfs(int x, int fa) { cnt++; if (cnt > n) return; printf( %d , x); for (int i = 0; i < g[x].size(); i++) { int y = g[x][i]; if (y == fa) continue; dfs(y, x); } } int main() { scanf( %d , &n); int xx, yy; for (int i = 1; i <= n; i++) { int x, y; scanf( %d , &x), scanf( %d , &y); if (i == 1) xx = x, yy = y; g[y].push_back(x), g[x].push_back(y); } if (g[1][0] != xx && g[1][0] != yy) swap(g[1][0], g[1][1]); dfs(1, 0); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16000000 ) using namespace std; const int Maxn = 1000005; const int Maxm = 4194304; const int Inf = 1000000000; int n, c; pair<int, int> lef[Maxn], rig[Maxn]; int me[Maxn]; int res[Maxn], rlen; int st[Maxm]; void Insert(int v, int l, int r, int x, int val) { if (l == r) st[v] = val; else { int m = l + r >> 1; if (x <= m) Insert(2 * v, l, m, x, val); else Insert(2 * v + 1, m + 1, r, x, val); st[v] = max(st[2 * v], st[2 * v + 1]); } } int Get(int v, int l, int r, int a, int b) { if (l == a && r == b) return st[v]; else { int res = -Inf; int m = l + r >> 1; if (a <= m) res = max(res, Get(2 * v, l, m, a, min(m, b))); if (m + 1 <= b) res = max(res, Get(2 * v + 1, m + 1, r, max(m + 1, a), b)); return res; } } bool isNull(const pair<int, int> &p) { return p == pair<int, int>(Inf, -Inf); } void Print(int l, int r) { if (l > r) return; if (l == r) res[rlen++] = l; else { int from = l + 1; if (!isNull(lef[l])) { Print(l + 1, lef[l].second); from = lef[l].second + 1; } res[rlen++] = l; Print(from, r); } } int main() { scanf( %d %d , &n, &c); for (int i = 1; i <= n; i++) { lef[i] = pair<int, int>(Inf, -Inf); rig[i] = pair<int, int>(Inf, -Inf); } int a, b; char s[10]; while (c--) { scanf( %d %d %s , &a, &b, s); if (s[0] == L ) { lef[a].first = min(lef[a].first, b); lef[a].second = max(lef[a].second, b); } else { rig[a].first = min(rig[a].first, b); rig[a].second = max(rig[a].second, b); } } for (int i = n; i >= 1; i--) { if (isNull(lef[i]) && isNull(rig[i])) me[i] = i; else if (isNull(lef[i])) if (rig[i].first <= i) { printf( IMPOSSIBLE n ); return 0; } else me[i] = Get(1, 1, n, i + 1, rig[i].second); else if (isNull(rig[i])) if (lef[i].first <= i) { printf( IMPOSSIBLE n ); return 0; } else { lef[i].second = Get(1, 1, n, i + 1, lef[i].second); me[i] = lef[i].second; } else if (lef[i].first <= i) { printf( IMPOSSIBLE n ); return 0; } else { lef[i].second = Get(1, 1, n, i + 1, lef[i].second); if (lef[i].second >= rig[i].first) { printf( IMPOSSIBLE n ); return 0; } else me[i] = Get(1, 1, n, lef[i].second + 1, rig[i].second); } Insert(1, 1, n, i, me[i]); } Print(1, n); for (int i = 0; i < rlen; i++) printf( %d%c , res[i], i + 1 < rlen ? : n ); return 0; }
|
module dct_ctrl(
clk,
rst,
i_valid,
i_transize,
i_valid_4,
i_transize_1,
i_transize_2,
i_transize_3,
i_transize_4
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input i_valid;
input [1:0] i_transize;
output reg i_valid_4;
output reg [1:0] i_transize_1;
output reg [1:0] i_transize_2;
output reg [1:0] i_transize_3;
output reg [1:0] i_transize_4;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg i_valid_1;
reg i_valid_2;
reg i_valid_3;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
i_transize_1<=2'b00;
else
i_transize_1<=i_transize;
always@(posedge clk or negedge rst)
if(!rst)
i_transize_2<=2'b00;
else
i_transize_2<=i_transize_1;
always@(posedge clk or negedge rst)
if(!rst)
i_transize_3<=2'b00;
else
i_transize_3<=i_transize_2;
always@(posedge clk or negedge rst)
if(!rst)
i_transize_4<=2'b00;
else
i_transize_4<=i_transize_3;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_1<=1'b0;
else
i_valid_1<=i_valid;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_2<=1'b0;
else
i_valid_2<=i_valid_1;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_3<=1'b0;
else
i_valid_3<=i_valid_2;
always@(posedge clk or negedge rst)
if(!rst)
i_valid_4<=1'b0;
else
i_valid_4<=i_valid_3;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_ls__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__EDFXBP_FUNCTIONAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__MUX2I_FUNCTIONAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ms__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ms__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int hv[5]; map<string, int> dys; string dyi[5] = { S , M , L , XL , XXL }; int order[5][5] = {{0, 1, 2, 3, 4}, {1, 2, 0, 3, 4}, {2, 3, 1, 4, 0}, {3, 4, 2, 1, 0}, {4, 3, 2, 1, 0}}; int k; string sk; void init() { dys[ S ] = 0; dys[ M ] = 1; dys[ L ] = 2; dys[ XL ] = 3; dys[ XXL ] = 4; } int main() { init(); for (int i = 0; i < 5; i++) scanf( %d , hv + i); scanf( %d , &k); for (int i = 0; i < k; i++) { cin >> sk; int dyk = dys[sk]; for (int j = 0; j < 5; j++) if (hv[order[dyk][j]]) { hv[order[dyk][j]]--; cout << dyi[order[dyk][j]] << endl; break; } } return 0; }
|
//==================================================================================================
// Filename : subRecursiveKOA_1c.v
// Created On : 2016-10-27 23:29:04
// Last Modified : 2016-10-31 11:41:40
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module csubRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
// input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
localparam integer STOP_CONT = `STOP_CONT;
generate
//assign i = Stop_I;
if (SW <= STOP_CONT) begin : GENSTOP
cmult #(.SW(SW))
inst_cmult (
// .clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long vet[9], used[9], available[9]; int dp[100][32]; int dp2[100][32]; vector<int> itens, itens2; void comp() { for (int i = 1; i <= 8; i++) { long long j = 1; used[i] = min(used[i], (long long)32 / i); while (used[i]) { itens.push_back(min(used[i], j) * i); used[i] -= min(used[i], j); j <<= 1; } j = 1; available[i] = min(available[i], (long long)32 / i); while (available[i]) { itens2.push_back(min(available[i], j) * i); available[i] -= min(available[i], j); j <<= 1; } } dp[0][0] = dp2[0][0] = 1; for (int i = 0; i < itens.size(); i++) { for (int j = 0; j < 32; j++) { dp[i + 1][j] |= dp[i][j]; if (j >= itens[i]) dp[i + 1][j] |= dp[i][j - itens[i]]; } } for (int i = 0; i < itens2.size(); i++) { for (int j = 0; j < 32; j++) { dp2[i + 1][j] |= dp2[i][j]; if (j >= itens2[i]) dp2[i + 1][j] |= dp2[i][j - itens2[i]]; } } } int consegue(int x) { for (int i = 0; i < 32 - x; i++) if (dp2[itens2.size()][i] && dp[itens.size()][x + i]) return 1; return 0; } int main() { long long W, total = 0; scanf( %lld , &W); for (int i = 1; i <= 8; i++) { scanf( %lld , &vet[i]); total += i * vet[i]; } if (total <= W) printf( %lld n , total); else { for (int i = 1; i <= 8; i++) used[i] = vet[i]; for (int i = 8; i >= 1; i--) { if (total - i * used[i] >= W) { total -= i * used[i]; available[i] = used[i]; used[i] = 0; } else { long long d = (total - W) / i; total -= d * i; used[i] -= d; available[i] = d; } } comp(); for (long long z = W; z >= max(0LL, W - 8); z--) { int x = total - z; if (consegue(x)) { return !printf( %lld n , z); } } } return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 4'h0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 25,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 10,
parameter data_delay = 0,
parameter dqs_delay = 0,
parameter clock_delay = 0,
parameter addr_delay = 0
) (
input sys_clk,
input sys_clk_n,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Simple FML 4x64 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_eack,
output reg fml_ack,
input [3:0] fml_sel,
input [31:0] fml_di,
output [31:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output sdram_clk_p,
output sdram_clk_n,
output sdram_cke,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [12:0] sdram_adr,
output [1:0] sdram_ba,
output [1:0] sdram_dm,
inout [15:0] sdram_dq,
inout [1:0] sdram_dqs
);
/* Register all control signals. */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [12:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
reg sdram_cke_predelay;
reg sdram_cs_n_predelay;
reg sdram_we_n_predelay;
reg sdram_cas_n_predelay;
reg sdram_ras_n_predelay;
reg [12:0] sdram_adr_predelay;
reg [1:0] sdram_ba_predelay;
/* -----\/----- EXCLUDED -----\/-----
always @(posedge sys_clk) begin
sdram_cke_predelay <= sdram_cke_r;
sdram_cs_n_predelay <= sdram_cs_n_r;
sdram_we_n_predelay <= sdram_we_n_r;
sdram_cas_n_predelay <= sdram_cas_n_r;
sdram_ras_n_predelay <= sdram_ras_n_r;
sdram_ba_predelay <= sdram_ba_r;
sdram_adr_predelay <= sdram_adr_r;
end
-----/\----- EXCLUDED -----/\----- */
hpdmc_ofd
#(
.g_width(20),
.g_delay(addr_delay)
)
delay_ctrl
(
.clk_p_i(sys_clk),
.clk_n_i(sys_clk_n),
.in_i( {sdram_cke_r,
sdram_cs_n_r,
sdram_we_n_r,
sdram_cas_n_r,
sdram_ras_n_r,
sdram_ba_r,
sdram_adr_r } ),
.out_o( {sdram_cke,
sdram_cs_n,
sdram_we_n,
sdram_cas_n,
sdram_ras_n,
sdram_ba,
sdram_adr } )
);
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [12:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [12:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
wire idelay_rst;
wire idelay_ce;
wire idelay_inc;
wire idelay_cal;
hpdmc_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.idelay_cal(idelay_cal)
);
/* SDRAM management unit */
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
wire eack;
reg eack_d, eack_d1;
always@(posedge sys_clk)
begin
eack_d <= eack;
eack_d1 <= eack_d;
end
assign fml_eack = (fml_we ? eack : eack_d1 );
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(fml_stb),
.we(fml_we),
.address(fml_adr[sdram_depth-1:2]),
.ack(eack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Data path controller */
wire direction;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.direction(direction),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_ddrio #(
.data_delay(data_delay),
.dqs_delay(dqs_delay),
.clock_delay(clock_delay)
) drio (
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.direction(direction),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DM pins.
*/
.mo(~fml_sel),
.do(fml_di),
.di(fml_do),
.sdram_dm(sdram_dm),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.sdram_clk_p(sdram_clk_p),
.sdram_clk_n(sdram_clk_n),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.idelay_cal(idelay_cal)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 5; int di[] = {1, 1, -1, -1}; int dj[] = {1, -1, 1, -1}; long long n, k; long long solv() { long long st = 0, ed = k, ans; while (st <= ed) { long long x = (k * (k + 1)) / 2; long long mid = (st + ed) / 2; long long xx = k - mid; x -= ((xx * (xx + 1)) / 2) + mid - 1; if (x < n) st = mid + 1; else if (x >= n) ans = mid, ed = mid - 1; else return mid; } return ans; } int main() { cin >> n >> k; if ((k * (k + 1)) / 2 - k + 1 < n) return cout << -1, 0; cout << solv(); }
|
/*
* Copyright (c) 2003 Michael Ruff (mruff @ chiaro.com)
*
* This source code is free software; rou can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at rour option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: real3.v,v 1.1 2003/03/07 05:29:41 stevewilliams Exp $
*/
/*
* Verifies some real values to make sure the real->double conversion
* is properly handled and the values make it into vvp properly.
*
* http://babbage.cs.qc.edu/courses/cs341/IEEE-754.html
*
*/
module main;
real r;
reg errors;
initial begin
errors = 0;
r = 1.0;
if ($realtobits(r) != 64'h3FF0000000000000) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
r = 1.1;
if ($realtobits(r) != 64'h3FF199999999999a) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
r = 3.3;
if ($realtobits(r) != 64'h400A666666666666) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
r = 5.5;
if ($realtobits(r) != 64'h4016000000000000) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
r = 1.0000000000_0000000001;
if ($realtobits(r) != 64'h3FF0000000000000) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
r = 3.1415926535_8979323846;
if ($realtobits(r) != 64'h400921FB54442D18) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
r = 1234567890_1234567890.1;
if ($realtobits(r) != 64'h43E56A95319D63E1) begin
$display("%f != 'h%h", r, $realtobits(r));
$display("FAIL");
errors = 1;
end
if (errors === 0) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int kor = 1e7; int main() { long long n, rad, v; cin >> n >> rad >> v; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; long long d = r - l; int ma = 0; while (d < kor) { d *= 10; rad *= 10; ma++; } long long mnv = 0; long long mxv = d; while (mnv != mxv) { long long cv = (mnv + mxv) / 2; double cd = cv + rad * sin((double)cv / rad); if (cd < (d / 2)) { mnv = cv + 1; continue; } mxv = cv; } long long ev = mnv; mnv = 0; mxv = d; while (mnv != mxv) { long long cv = (mnv + mxv) / 2; double cd = cv - rad * sin((double)cv / rad); if (cd < (d / 2)) { mnv = cv + 1; continue; } mxv = cv; } long long bv = min(ev, mnv); bv *= 2; double t = (double)bv / v; while (ma > 0) { t /= 10; rad /= 10; ma--; } cout << setprecision(20) << t << endl; } cin >> n; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int mc = 0, i = 1, j = n; while (1) { cout << i << ; mc++; if (mc == n) break; cout << j << ; i++; j--; mc++; if (mc == n) break; } cout << endl; return 0; }
|
Require Import Fiat.Common Fiat.Computation Fiat.ADT Coq.Sets.Ensembles.
Generalizable All Variables.
Set Implicit Arguments.
Section MethodRefinement.
(** Old and new representations **)
Variables oldRep newRep : Type.
(** Abstraction Relation *)
Variable AbsR : oldRep -> newRep -> Prop.
Notation "ro ≃ rn" := (AbsR ro rn) (at level 70).
(** Refinement of a constructor: the computation produced by
a constructor [newConstructor] should be a refinement
of the computation produced by the old constructor [oldObserver] on
[d]. That is, the following diagram should commute:
<<
old constructor
Dom --------------> old rep
∥ |
∥ id AbsR |
∥ |
Dom --------------> new rep
new constructor
>>
*)
Fixpoint refineConstructor
{dom : list Type}
: constructorType oldRep dom
-> constructorType newRep dom
-> Prop :=
match dom return
constructorType oldRep dom
-> constructorType newRep dom
-> Prop
with
| nil => fun oldConstructor newConstructor =>
refine (r_o' <- oldConstructor;
{r_n | r_o' ≃ r_n})
(newConstructor)
| cons D dom' =>
fun oldConstructor newConstructor =>
forall d : D,
@refineConstructor dom' (oldConstructor d)
(newConstructor d)
end.
(* Variant for use in tactics. *)
Fixpoint refineConstructor_eq
{dom : list Type}
: constructorType oldRep dom
-> constructorType oldRep dom
-> Prop :=
match dom return
constructorType oldRep dom
-> constructorType oldRep dom
-> Prop
with
| nil => fun oldConstructor newConstructor =>
refine oldConstructor newConstructor
| cons D dom' =>
fun oldConstructor newConstructor =>
forall d : D,
@refineConstructor_eq dom' (oldConstructor d)
(newConstructor d)
end.
(** Refinement of a method : the values of the computation
produced by applying a new method [newMethod] to any new
state [r_n] related to an old state [r_o] by the abstraction
relation [AbsR] are related by [AbsR] to some value produced by
the corresponding old method on [r_o]. Related values
are taken to related values (with the new method potentially
producing more deterministic computations). That is, the
following diagram commutes:
<<
old method
old rep --------------> old rep
| |
AbsR | | AbsR
↓ ↓
new rep --------------> new rep
new method
>> *)
Fixpoint refineMethod'
{dom : list Type}
{cod : option Type}
: methodType' oldRep dom cod
-> methodType' newRep dom cod
-> Prop :=
match dom return
methodType' oldRep dom cod
-> methodType' newRep dom cod
-> Prop
with
| nil =>
match cod return
methodType' oldRep [] cod
-> methodType' newRep [] cod
-> Prop
with
| Some cod' =>
fun oldMethod newMethod =>
refine (r_o' <- oldMethod;
r_n' <- {r_n | fst r_o' ≃ r_n};
ret (r_n', snd r_o'))
newMethod
| _ =>
fun oldMethod newMethod =>
refine (r_o' <- oldMethod;
{r_n | r_o' ≃ r_n})
newMethod
end
| cons D dom' =>
fun oldMethod newMethod =>
forall d : D,
@refineMethod' dom' cod (oldMethod d)
(newMethod d)
end.
Definition refineMethod
{dom : list Type}
{cod : option Type}
(oldMethod : methodType oldRep dom cod)
(newMethod : methodType newRep dom cod)
:= forall r_o r_n,
r_o ≃ r_n ->
@refineMethod' dom cod (oldMethod r_o) (newMethod r_n).
Fixpoint refineMethod_eq'
{dom : list Type}
{cod : option Type}
: methodType' oldRep dom cod
-> methodType' oldRep dom cod
-> Prop :=
match dom return
methodType' oldRep dom cod
-> methodType' oldRep dom cod
-> Prop
with
| nil =>
match cod return
methodType' oldRep [] cod
-> methodType' oldRep [] cod
-> Prop
with
| Some cod' =>
fun oldMethod newMethod =>
refine oldMethod newMethod
| _ =>
fun oldMethod newMethod =>
refine oldMethod newMethod
end
| cons D dom' =>
fun oldMethod newMethod =>
forall d : D,
@refineMethod_eq' dom' cod (oldMethod d)
(newMethod d)
end.
Definition refineMethod_eq
{dom : list Type}
{cod : option Type}
(oldMethod : methodType oldRep dom cod)
(newMethod : methodType oldRep dom cod)
:= forall r_o,
@refineMethod_eq' dom cod (oldMethod r_o) (newMethod r_o).
End MethodRefinement.
Record refineADT {Sig} (A B : ADT Sig) :=
refinesADT {
AbsR : _;
ADTRefinementPreservesConstructors
: forall idx : ConstructorIndex Sig,
@refineConstructor
(Rep A) (Rep B) AbsR
(ConstructorDom Sig idx)
(Constructors A idx)
(Constructors B idx);
ADTRefinementPreservesMethods
: forall idx : MethodIndex Sig,
@refineMethod
(Rep A) (Rep B) AbsR
(fst (MethodDomCod Sig idx))
(snd (MethodDomCod Sig idx))
(Methods A idx)
(Methods B idx) }.
(** We should always just unfold [refineMethod] and [refineConstructor]
into [refine], so that we can rewrite with lemmas about [refine]. *)
Notation "ro ≃ rn" := (@AbsR _ _ _ _ ro rn) (at level 70).
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A2111O_PP_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_PP_BLACKBOX_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module sends and receives data to/from the DE2's audio and TV *
* peripherals' control registers. *
* *
******************************************************************************/
module altera_up_av_config_serial_bus_controller (
// Inputs
clk,
reset,
start_transfer,
data_in,
transfer_mask,
restart_counter,
restart_data_in,
restart_transfer_mask,
// Bidirectionals
serial_data,
// Outputs
serial_clk,
serial_en,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 26; // Datawidth
parameter CW = 4; // Counter's datawidth
parameter SCCW = 11; // Slow clock's counter's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input start_transfer;
input [DW: 0] data_in;
input [DW: 0] transfer_mask;
input [CW: 0] restart_counter;
input [DW: 0] restart_data_in;
input [DW: 0] restart_transfer_mask;
// Bidirectionals
inout serial_data; // I2C Data
// Outputs
output serial_clk; // I2C Clock
output reg serial_en;
output [DW: 0] data_out;
output reg transfer_complete;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States for finite state machines
localparam STATE_0_IDLE = 3'h0,
STATE_1_INITIALIZE = 3'h1,
STATE_2_RESTART_BIT = 3'h2,
STATE_3_START_BIT = 3'h3,
STATE_4_TRANSFER = 3'h4,
STATE_5_STOP_BIT = 3'h5;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire slow_clk;
wire toggle_data_in;
wire toggle_data_out;
// Internal Registers
reg [CW: 0] counter;
reg [DW: 0] shiftreg_data;
reg [DW: 0] shiftreg_mask;
reg new_data;
// State Machine Registers
reg [ 2: 0] ns_serial_protocol;
reg [ 2: 0] s_serial_protocol;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_serial_protocol <= STATE_0_IDLE;
else
s_serial_protocol <= ns_serial_protocol;
end
always @(*)
begin
// Defaults
ns_serial_protocol = STATE_0_IDLE;
case (s_serial_protocol)
STATE_0_IDLE:
begin
if (start_transfer & ~transfer_complete & toggle_data_in)
ns_serial_protocol = STATE_1_INITIALIZE;
else
ns_serial_protocol = STATE_0_IDLE;
end
STATE_1_INITIALIZE:
begin
ns_serial_protocol = STATE_3_START_BIT;
end
STATE_2_RESTART_BIT:
begin
if (toggle_data_in)
ns_serial_protocol = STATE_3_START_BIT;
else
ns_serial_protocol = STATE_2_RESTART_BIT;
end
STATE_3_START_BIT:
begin
if (toggle_data_out)
ns_serial_protocol = STATE_4_TRANSFER;
else
ns_serial_protocol = STATE_3_START_BIT;
end
STATE_4_TRANSFER:
begin
if (toggle_data_out & (counter == DW))
ns_serial_protocol = STATE_5_STOP_BIT;
else if (toggle_data_out & shiftreg_mask[DW] & shiftreg_data[DW])
ns_serial_protocol = STATE_2_RESTART_BIT;
else
ns_serial_protocol = STATE_4_TRANSFER;
end
STATE_5_STOP_BIT:
begin
if (toggle_data_in)
ns_serial_protocol = STATE_0_IDLE;
else
ns_serial_protocol = STATE_5_STOP_BIT;
end
default:
begin
ns_serial_protocol = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
serial_en <= 1'b1;
else if (toggle_data_out & (s_serial_protocol == STATE_3_START_BIT))
serial_en <= 1'b0;
else if (s_serial_protocol == STATE_5_STOP_BIT)
serial_en <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
transfer_complete <= 1'b0;
else if (s_serial_protocol == STATE_5_STOP_BIT)
transfer_complete <= 1'b1;
else if (~start_transfer)
transfer_complete <= 1'b0;
end
// Input Registers
always @(posedge clk)
begin
if (reset)
begin
counter <= 'h0;
shiftreg_data <= 'h0;
shiftreg_mask <= 'h0;
end
else if (s_serial_protocol == STATE_1_INITIALIZE)
begin
counter <= 'h0;
shiftreg_data <= data_in;
shiftreg_mask <= transfer_mask;
end
else if (toggle_data_in & (s_serial_protocol == STATE_2_RESTART_BIT))
begin
counter <= restart_counter;
shiftreg_data <= restart_data_in;
shiftreg_mask <= restart_transfer_mask;
end
else if (toggle_data_out & (s_serial_protocol == STATE_4_TRANSFER))
begin
counter <= counter + 'h1;
shiftreg_data <= {shiftreg_data[(DW - 1):0], new_data};
shiftreg_mask <= {shiftreg_mask[(DW - 1):0], 1'b0};
end
end
always @(posedge clk)
begin
if (reset)
new_data <= 1'b0;
else if (toggle_data_in & (s_serial_protocol == STATE_4_TRANSFER))
new_data <= serial_data;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign serial_clk = (s_serial_protocol == STATE_0_IDLE) ? 1'b1 : slow_clk;
assign serial_data = (s_serial_protocol == STATE_0_IDLE) ? 1'b1 :
(s_serial_protocol == STATE_2_RESTART_BIT) ? 1'b1 :
(s_serial_protocol == STATE_4_TRANSFER) ?
((shiftreg_mask[DW]) ? 1'bz :
shiftreg_data[DW]) :
1'b0;
assign data_out = shiftreg_data;
// Input Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_slow_clock_generator Serial_Config_Clock_Generator (
// Inputs
.clk (clk),
.reset (reset),
.enable_clk (1'b1),
// Bidirectionals
// Outputs
.new_clk (slow_clk),
.rising_edge (),
.falling_edge (),
.middle_of_high_level (toggle_data_in),
.middle_of_low_level (toggle_data_out)
);
defparam
Serial_Config_Clock_Generator.CB = SCCW;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* LocalLink to AXI4-Stream bridge
*/
module ll_axis_bridge #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* LocalLink input
*/
input wire [DATA_WIDTH-1:0] ll_data_in,
input wire ll_sof_in_n,
input wire ll_eof_in_n,
input wire ll_src_rdy_in_n,
output wire ll_dst_rdy_out_n,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] axis_tdata,
output wire axis_tvalid,
input wire axis_tready,
output wire axis_tlast
);
assign axis_tdata = ll_data_in;
assign axis_tvalid = ~ll_src_rdy_in_n;
assign axis_tlast = ~ll_eof_in_n;
assign ll_dst_rdy_out_n = ~axis_tready;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module memtest_prng64(
input clk,
input rst,
input ce,
output reg [63:0] rand
);
reg [30:0] state;
reg o;
integer i;
always @(posedge clk) begin
if(rst) begin
state = 31'd0;
rand = 64'd0;
end else if(ce) begin
for(i=0;i<64;i=i+1) begin
o = ~(state[30] ^ state[27]);
rand[i] = o;
state = {state[29:0], o};
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND3B_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_SYMBOL_V
|
#include <bits/stdc++.h> typedef struct { long long s, l, r, m; } value; long long maxll(long long a, long long b) { return a > b ? a : b; } void sum(value *v, value *l, value *r) { v->s = l->s + r->s; v->l = maxll(l->l, l->s + r->l); v->r = maxll(r->r, r->s + l->r); v->m = maxll(l->r + r->l, maxll(l->m, r->m)); } value t[4 * 150000]; long long a[150000]; void build(int i, int l, int r) { if (l == r) { t[i].s = a[l]; t[i].l = t[i].r = t[i].m = maxll(a[l], 0); } else { int m = (l + r) / 2; build(2 * i + 1, l, m); build(2 * i + 2, m + 1, r); sum(&t[i], &t[2 * i + 1], &t[2 * i + 2]); } } value get(int ll, int rr, int i, int l, int r) { if (rr < l || r < ll) { value v = {0, 0, 0, 0}; return v; } if (ll <= l && r <= rr) return t[i]; int m = (l + r) / 2; value lv, rv, av; lv = get(ll, rr, 2 * i + 1, l, m); rv = get(ll, rr, 2 * i + 2, m + 1, r); sum(&av, &lv, &rv); return av; } int main() { int n, m, c; scanf( %d%d%d , &n, &m, &c); int i, x[150000]; for (i = 0; i < n; i++) scanf( %d , &x[i]); int p[150000]; for (i = 0; i < n - 1; i++) scanf( %d , &p[i]); for (i = 0; i < n - 1; i++) a[i] = 1LL * (x[i + 1] - x[i]) * 50 - c * p[i]; build(0, 0, n - 2); long long s = 0; for (i = 0; i < m; i++) { int l, r; scanf( %d%d , &l, &r); l--; r--; r--; s += get(l, r, 0, 0, n - 2).m; } printf( %.2lf n , 1. * s / 100); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 2e9; const int mod = 1e9 + 7; const int N = 1234; int n, m; long long k; int a[N][N], h[N * N], p[N * N]; long long b[N][N]; bool used[N][N]; vector<pair<int, int> > go = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; bool check(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } int get(int x) { return x == p[x] ? x : p[x] = get(p[x]); } void unite(int x, int y) { x = get(x); y = get(y); if (x == y) return; p[x] = y; h[y] += h[x]; h[x] = 0; } long long qwe; void dfs(int i, int j) { k -= qwe; used[i][j] = true; b[i][j] = qwe; for (auto w : go) { int x = i + w.first, y = j + w.second; if (check(x, y) && !used[x][y] && k > 0ll && a[x][y] >= qwe) dfs(x, y); } } int main() { ios::sync_with_stdio(0); cin >> n >> m >> k; vector<pair<int, pair<int, int> > > v; v.reserve(n * m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; p[i * m + j] = i * m + j; h[i * m + j] = 1; v.push_back({a[i][j], {i, j}}); } } sort(v.rbegin(), v.rend()); for (int i = 0; i < n * m; i++) { int x = v[i].second.first, y = v[i].second.second, w = v[i].first; for (auto z : go) { int nx = x + z.first, ny = y + z.second; if (check(nx, ny) && a[nx][ny] >= w) { unite(x * m + y, nx * m + ny); } } int sz = h[get(x * m + y)]; if (k % (long long)w == 0ll && k / (long long)w <= (long long)sz) { qwe = w; dfs(x, y); cout << YES n ; for (int j = 0; j < n; j++) { for (int z = 0; z < m; z++) { cout << b[j][z] << ; } cout << n ; } return 0; } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, M; signed long long L[100020], R[100020], T[100020]; signed long long Q[100020]; vector<pair<signed long long, signed long long> > QP; signed long long PP[200200]; signed long long AS[200200], BS[200200], ret[200200]; vector<signed long long> S[200200], E[200200]; void solve() { int i, j, k, l, r, x, y; string s; cin >> N >> M; for (i = 0; i < M; i++) cin >> L[i] >> R[i] >> T[i]; for (i = 0; i < N; i++) cin >> Q[i], QP.push_back(make_pair(Q[i], i)); sort(QP.begin(), QP.end()); map<signed long long, signed long long> UM; UM[0] = 0; for (i = 0; i < M; i++) UM[L[i]] = UM[R[i]] = 1; i = 0; for (__typeof(UM.begin()) it = UM.begin(); it != UM.end(); it++) it->second = i++, PP[it->second] = it->first; for (i = 0; i < M; i++) S[UM[L[i]]].push_back(T[i]), E[UM[R[i]]].push_back(T[i]); map<signed long long, int> CS; for (i = 0; i < UM.size(); i++) { for (j = 0; j < E[i].size(); j++) if (--CS[E[i][j]] == 0) CS.erase(E[i][j]); for (j = 0; j < S[i].size(); j++) CS[S[i][j]]++; if (CS.size()) { signed long long ct = CS.begin()->first; x = lower_bound(QP.begin(), QP.end(), make_pair(ct - PP[i + 1], 0LL)) - QP.begin(); y = lower_bound(QP.begin(), QP.end(), make_pair(ct - PP[i], 0LL)) - QP.begin(); AS[x]++; AS[y]--; BS[x] -= ct - PP[i + 1], BS[y] += ct - PP[i]; } } signed long long aa = 0, bb = 0; for (i = 0; i < N; i++) aa += AS[i], bb += BS[i], ret[QP[i].second] = aa * QP[i].first + bb; for (i = 0; i < N; i++) cout << ret[i] << endl; } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false); for (i = 0; i < argc - 1; i++) s += argv[i + 1], s += n ; for (i = 0; i < s.size(); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { if (b) return GCD(b, a % b); return a; } bool u1[10]; bool u2[10]; int main() { long long n, m, v; vector<long long> a, b; ios_base::sync_with_stdio(0); cin >> n >> m; for (long long i = 0; i < n; i++) { cin >> v; a.push_back(v); u1[v] = true; } for (long long i = 0; i < m; i++) { cin >> v; b.push_back(v); u2[v] = true; } sort(a.begin(), a.end()); sort(b.begin(), b.end()); for (long long i = 1; i <= 9; i++) { if (u1[i] && u2[i]) { cout << i; return 0; } } if (a[0] < b[0]) { cout << a[0] << b[0]; } else cout << b[0] << a[0]; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int k1, k2, k3; cin >> k1 >> k2 >> k3; int n = k1 + k2 + k3; int maps[n]; for (int i = 0; i < n; i++) { int inp; cin >> inp; inp--; if (i < k1) maps[inp] = 0; else if (i < k1 + k2) maps[inp] = 1; else maps[inp] = 2; } int costsk1[n]; int costsk2[n]; int costsk3[n]; int profits[n]; int maxprofits[n]; for (int i = 0; i < n; i++) { costsk1[i] = (i == 0 ? 0 : costsk1[i - 1]) + (maps[i] == 0 ? 0 : 1); costsk2[i] = (i == 0 ? 0 : costsk2[i - 1]) + (maps[i] == 1 ? 0 : 1); costsk3[i] = (i == 0 ? 0 : costsk3[i - 1]) + (maps[i] == 2 ? 0 : 1); profits[i] = costsk2[i] - costsk1[i]; maxprofits[i] = max((i == 0 ? 0 : maxprofits[i - 1]), profits[i]); } int minn = costsk3[n - 1]; for (int i = 0; i < n; i++) { minn = min(minn, costsk2[i] - maxprofits[i] + costsk3[n - 1] - costsk3[i]); } cout << minn << endl; }
|
#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int n, k, sum = 0; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , a + i); sum += a[i]; } sort(a, a + n); int res = a[n - 1]; for (int t = n - k, i = n - k - 1; i >= 0; i--, t++) { if (res < a[i] + a[t]) { res = a[i] + a[t]; } } if (k == 1) printf( %d n , sum); else printf( %d n , res); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_2_V
`define SKY130_FD_SC_MS__A21BO_2_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:14:09 03/08/2014
// Design Name:
// Module Name: obc1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module obc1(
input clk,
input enable,
input [7:0] data_in,
output [7:0] data_out,
input [12:0] addr_in,
input reg_we_rising
);
reg [7:0] obc1_regs [7:0];
wire [6:0] oam_number = obc1_regs[6][6:0];
wire obc_bank = obc1_regs[5][0];
wire low_en = enable & ((addr_in & 13'h1a00) == 13'h1800);
wire high_en = enable & ((addr_in & 13'h1a00) == 13'h1a00);
wire reg_en = enable & ((addr_in & 13'h1ff8) == 13'h1ff0);
wire [2:0] obc_reg = addr_in[2:0];
wire oam_low_we = enable & (reg_we_rising) & (((addr_in & 13'h1ffc) == 13'h1ff0) | low_en);
wire oam_high_we = enable & (reg_we_rising) & (addr_in == 13'h1ff4);
wire snes_high_we = enable & (reg_we_rising) & high_en;
wire [9:0] oam_low_addr = (~reg_en) ? addr_in[9:0] : {~obc_bank, oam_number, addr_in[1:0]};
wire [7:0] oam_high_addr = (~reg_en) ? addr_in[5:0] : {~obc_bank, oam_number};
wire [7:0] low_douta;
wire [7:0] high_doutb;
`ifdef MK2
obc_lower oam_low (
.clka(clk), // input clka
.wea(oam_low_we), // input [0 : 0] wea
.addra(oam_low_addr), // input [9 : 0] addra
.dina(data_in), // input [7 : 0] dina
.douta(low_douta) // output [7 : 0] douta
);
obc_upper oam_high (
.clka(clk), // input clka
.wea(oam_high_we), // input [0 : 0] wea
.addra(oam_high_addr), // input [7 : 0] addra
.dina(data_in[1:0]), // input [1 : 0] dina
.douta(douta), // unused
.clkb(clk), // input clkb
.web(snes_high_we), // input [0 : 0] web
.addrb(addr_in[5:0]), // input [5 : 0] addrb
.dinb(data_in),
.doutb(high_doutb) // output [7 : 0] doutb
);
`endif
`ifdef MK3
obc_lower oam_low (
.clock(clk), // input clka
.wren(oam_low_we), // input [0 : 0] wea
.address(oam_low_addr), // input [9 : 0] addra
.data(data_in), // input [7 : 0] dina
.q(low_douta) // output [7 : 0] douta
);
obc_upper oam_high (
.clock(clk), // input clka
.wren_a(oam_high_we), // input [0 : 0] wea
.address_a(oam_high_addr), // input [7 : 0] addra
.data_a(data_in[1:0]), // input [1 : 0] dina
.q_a(douta), // unused
.wren_b(snes_high_we), // input [0 : 0] web
.address_b(addr_in[5:0]), // input [5 : 0] addrb
.data_b(data_in),
.q_b(high_doutb) // output [7 : 0] doutb
);
`endif
assign data_out = reg_en ? obc1_regs[addr_in[2:0]]
: low_en ? low_douta
: high_en ? high_doutb
: 8'h77;
always @(posedge clk) begin
if(reg_en & reg_we_rising) begin
obc1_regs[obc_reg] <= data_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double eps = (long double)1e-9; const long double PI = (long double)acos(-1.0); const int inf = 1e9 + 5; const long long linf = 1e18L + 5; const int mod = 1e9 + 7; void solve() { int n, q, r, c; cin >> n >> q; unordered_set<int> s[3]; set<pair<int, int> > p; pair<int, int> pr; for (int i = 0; i < q; ++i) { cin >> r >> c; if (s[r].count(c)) { s[r].erase(c); for (int j : {c - 1, c, c + 1}) { if (j < 1 || j > n) continue; if (r == 1) pr = {c, j}; else pr = {j, c}; auto it = p.find(pr); if (it != p.end()) p.erase(it); } } else { s[r].insert(c); for (int j : {c - 1, c, c + 1}) { if (j < 1 || j > n) continue; if (r == 1) pr = {c, j}; else pr = {j, c}; if (s[3 - r].count(j)) p.insert(pr); } } cout << ((int)(p).size() ? no : yes ) << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int test = 1; while (test--) { solve(); cout << n ; } return 0; }
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Instruction fetch unit
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* IFU */
module uparc_ifu(
clk,
nrst,
/* Internal signals */
addr,
instr_dat,
rd_cmd,
busy,
err_align,
err_bus,
/* I-Bus */
o_IAddr,
o_IRdC,
i_IData,
i_IRdy,
i_IErr
);
/* I-Bus FSM states */
localparam IDLE = 1'b0; /* Ready to accept response */
localparam WAIT = 1'b1; /* Wait for response */
/* Inputs */
input wire clk;
input wire nrst;
/* Internal CPU interface */
input wire [`UPARC_ADDR_WIDTH-1:0] addr;
output wire [`UPARC_INSTR_WIDTH-1:0] instr_dat;
input wire rd_cmd;
output wire busy;
output wire err_align;
output wire err_bus;
/* I-Bus interface */
output reg [`UPARC_ADDR_WIDTH-1:0] o_IAddr;
output reg o_IRdC;
input wire [`UPARC_INSTR_WIDTH-1:0] i_IData;
input wire i_IRdy;
input wire i_IErr;
/* Address alignment error */
assign err_align = (rd_cmd == 1'b1 && addr[1:0] != 2'b0);
/* Active IFU transfer */
wire active = (!err_align && !i_IErr && rd_cmd == 1'b1);
/* Busy IFU state */
assign busy = ((active || (state == WAIT)) && !i_IRdy);
assign err_bus = i_IErr; /* Bus error occurred */
/* Transfer start logic */
always @(*)
begin
o_IAddr = 32'b0;
o_IRdC = 1'b0;
/* Issue command to I-Bus if no error */
if(active)
begin
o_IAddr = addr;
o_IRdC = 1'b1;
end
end
reg [`UPARC_INSTR_WIDTH-1:0] lch_idata; /* Latched instruction data */
reg state; /* Instruction fetch FSM state */
/* I-Bus response wait FSM */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
state <= IDLE;
lch_idata <= {(`UPARC_INSTR_WIDTH){1'b0}};
end
else
begin
if(state == IDLE && (active && i_IRdy))
begin
lch_idata <= i_IData;
end
else if(state == IDLE && (active && !i_IRdy))
begin
state <= !i_IErr ? WAIT : IDLE;
end
else if(state == WAIT && i_IRdy)
begin
state <= IDLE;
lch_idata <= i_IData;
end
end
end
/* Output logic */
assign instr_dat = (active || state == WAIT) ? i_IData : lch_idata;
endmodule /* uparc_ifu */
|
#include <bits/stdc++.h> using namespace std; int N, K; int h[100005]; bool isok[100005]; int check(int L) { deque<int> A, B; int ret = 0; for (int i = 1; i <= N; ++i) { while (A.size() && A.front() + L <= i) A.pop_front(); while (B.size() && B.front() + L <= i) B.pop_front(); while (A.size() && h[A.back()] >= h[i]) A.pop_back(); while (B.size() && h[B.back()] <= h[i]) B.pop_back(); A.push_back(i); B.push_back(i); if (i >= L) ret += (isok[i - L + 1] = (h[B.front()] - h[A.front()] <= K)); } return ret; } int main() { while (scanf( %d %d , &N, &K) == 2) { for (int i = 1; i <= N; ++i) scanf( %d , h + i); int lo = 1, hi = N + 1, mid; while (lo + 1 < hi) { mid = lo + hi >> 1; if (check(mid)) lo = mid; else hi = mid; } int s = check(lo); printf( %d %d n , lo, s); for (int i = 1; i + lo - 1 <= N; ++i) if (isok[i]) printf( %d %d n , i, i + lo - 1); } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 9, B = 511; inline long long read() { long long res = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { res = (res << 3) + (res << 1) + ch - 0 ; ch = getchar(); } return res * f; } struct query { long long p, id; query(long long _p = 0, long long _id = 0) { p = _p, id = _id; } }; long long m, n, tri[N][27], fail[N], cnt = 1, siz[N], ind, dfn[N]; long long len[N], fa[N], ed[N], tr[N], ans[N], a[N]; char s[N]; vector<long long> G[N]; vector<query> L[N], R[N], ll[N], rr[N]; inline bool cmp(query a, query b) { return a.p > b.p; } inline void insert(long long x) { long long p = 1; for (long long i = 1; i <= len[x]; i++) { long long v = s[i] - a ; if (!tri[p][v]) tri[p][v] = ++cnt, fa[tri[p][v]] = p; p = tri[p][v]; } ed[x] = p; } inline void build_fail() { queue<long long> Q; for (long long i = 0; i < 26; i++) if (tri[1][i]) Q.push(tri[1][i]), fail[tri[1][i]] = 1; else tri[1][i] = 1; while (!Q.empty()) { long long u = Q.front(); Q.pop(); for (long long i = 0; i < 26; i++) if (tri[u][i]) Q.push(tri[u][i]), fail[tri[u][i]] = tri[fail[u]][i]; else tri[u][i] = tri[fail[u]][i]; } } void dfs(long long u) { for (auto v : G[u]) dfs(v), a[u] += a[v]; } void Dfs(long long u) { siz[u] = 1; dfn[u] = ++ind; for (auto v : G[u]) Dfs(v), siz[u] += siz[v]; } inline void add(long long x, long long c) { while (x <= ind) tr[x] += c, x += (x & -x); } inline long long ask(long long x) { long long res = 0; while (x) res += tr[x], x -= (x & -x); return res; } signed main() { n = read(), m = read(); for (long long i = 1; i <= n; i++) { scanf( %s , s + 1); len[i] = strlen(s + 1); insert(i); } build_fail(); for (long long i = 2; i <= cnt; i++) G[fail[i]].push_back(i); for (long long i = 1; i <= m; i++) { long long l, r, k; l = read(), r = read(), k = read(); if (len[k] > B) L[k].push_back(query(l, i)), R[k].push_back(query(r, i)); else ll[l].push_back(query(k, i)), rr[r].push_back(query(k, i)); } for (long long i = 1; i <= n; i++) if (L[i].size() || R[i].size()) { sort(L[i].begin(), L[i].end(), cmp); sort(R[i].begin(), R[i].end(), cmp); } for (long long i = 1; i <= n; i++) if (len[i] > B) { long long p = ed[i]; while (p != 1) a[p] = 1, p = fa[p]; dfs(1); for (long long j = 1, val = 0; j <= n; j++) { while (L[i].size() && L[i].back().p == j) ans[L[i].back().id] -= val, L[i].pop_back(); val += a[ed[j]]; while (R[i].size() && R[i].back().p == j) ans[R[i].back().id] += val, R[i].pop_back(); } memset(a, 0, sizeof a); } Dfs(1); for (long long i = 1; i <= n; i++) { for (auto j : ll[i]) { long long p = ed[j.p]; while (p != 1) ans[j.id] -= ask(dfn[p]), p = fa[p]; } add(dfn[ed[i]], 1), add(dfn[ed[i]] + siz[ed[i]], -1); for (auto j : rr[i]) { long long p = ed[j.p]; while (p != 1) ans[j.id] += ask(dfn[p]), p = fa[p]; } } for (long long i = 1; i <= m; i++) printf( %lld n , ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_BLACKBOX_V
`define SKY130_FD_SC_LP__O21A_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21a (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_BEHAVIORAL_PP_V
|
`define ADDER_WIDTH 016
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 20; int h[maxn], n, q, cnt; string s; struct Node { int ans, mx, mn, l, r, lazy; Node(int a = 0) { ans = mn = mx = l = r = lazy = a; } void update(Node a, Node b) { ans = max({a.ans, b.ans, a.l + b.mx, b.r + a.mx}); mx = max({a.mx, b.mx}); mn = min({a.mn, b.mn}); l = max({a.l, b.l, a.mx - 2 * b.mn}); r = max({a.r, b.r, b.mx - 2 * a.mn}); } } sg[4 * maxn]; void add(int qval, int id) { sg[id].l -= qval; sg[id].r -= qval; sg[id].mn += qval; sg[id].mx += qval; sg[id].lazy += qval; } void shift(int id) { add(sg[id].lazy, id * 2); add(sg[id].lazy, id * 2 + 1); sg[id].lazy = 0; } void update(int l, int r, int ql, int qr, int qval, int id) { if (l >= ql && r <= qr) add(qval, id); else if (l > qr || r < ql) return; else { int mid = (l + r) / 2; shift(id); update(l, mid, ql, qr, qval, id * 2); update(mid + 1, r, ql, qr, qval, id * 2 + 1); sg[id].update(sg[id * 2], sg[id * 2 + 1]); } } void build(int l, int r, int id) { if (l == r) { sg[id].mn = sg[id].mx = h[r]; sg[id].l = sg[id].r = -h[r]; } else { int mid = (l + r) / 2; build(l, mid, id * 2); build(mid + 1, r, id * 2 + 1); sg[id].update(sg[id * 2], sg[id * 2 + 1]); } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> q >> s; for (int i = 0; i < 2 * n - 2; i++) { if (s[i] == ( ) cnt++; else cnt--; h[i + 2] = cnt; } build(1, 2 * n - 1, 1); int a, b, tmp; cout << sg[1].ans << endl; while (q--) { cin >> a >> b; if (a > b) swap(a, b); tmp = 0; if (s[a - 1] == ( && s[b - 1] == ) ) tmp = -2; if (s[a - 1] == ) && s[b - 1] == ( ) tmp = 2; update(1, 2 * n - 1, a + 1, b, tmp, 1); cout << sg[1].ans << endl; swap(s[a - 1], s[b - 1]); } }
|
#include <bits/stdc++.h> using namespace std; int N, M; bitset<2020> mat[2020]; int main() { int T; scanf( %d , &T); while (T--) { scanf( %d%d , &N, &M); vector<pair<int, int> > E; int deg[2020] = {}; for (int i = 1; i <= M; i++) { int x, y; scanf( %d%d , &x, &y); deg[x]++; deg[y]++; E.push_back(pair<int, int>(x, y)); } int ok = 1; for (int i = 1; i <= N; i++) if (deg[i] & 1) ok = 0; if (ok) { puts( 1 ); for (int i = 1; i <= N; i++) printf( 1 ); puts( ); } else { for (int i = 1; i <= N; i++) mat[i].reset(); for (int i = 1; i <= N; i++) if (deg[i] & 1) mat[i][i] = 1; for (pair<int, int> e : E) { int x = e.first, y = e.second; mat[x][y] = !mat[x][y]; mat[y][x] = !mat[y][x]; } int V[2020] = {}; for (int i = 1; i <= N; i++) V[i] = (deg[i] & 1); int now = 1; int base[2020]; for (int i = 1; i <= N; i++) { int f = -1; for (int j = now; j <= N; j++) if (mat[j][i]) { f = j; break; } if (f == -1) continue; swap(mat[f], mat[now]); swap(V[f], V[now]); for (int j = now + 1; j <= N; j++) { if (mat[j][i]) { mat[j] ^= mat[now]; V[j] ^= V[now]; } } base[now] = i; ++now; } --now; int res[2020] = {}; for (int i = now; i; i--) { int p = base[i]; res[p] = V[i]; if (res[p]) { for (int j = 1; j < i; j++) if (mat[j][p]) V[j] ^= 1; } } puts( 2 ); for (int i = 1; i <= N; i++) printf( %d , res[i] + 1); puts( ); } } }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2 * 1000 * 100 + 100; const int maxS = 4 * maxN; vector<int> seg[maxS]; int f[maxS], toxor[maxS]; int n; inline vector<int> merge(vector<int> a, vector<int> b) { for (auto x : b) { for (auto y : a) if (x & (y & -y)) x ^= y; if (x) { for (auto& y : a) if (y & (x & -x)) y ^= x; a.push_back(x); } } return a; } inline void handle(int ind, int qv) { f[ind] ^= qv; toxor[ind] ^= qv; } inline void shift(int ind) { handle(ind * 2, toxor[ind]); handle(ind * 2 + 1, toxor[ind]); toxor[ind] = 0; } inline vector<int> val(int ind) { vector<int> tmp; tmp.push_back(f[ind]); return merge(seg[ind], tmp); } void add(int ql, int qr, int qv, int xl = 0, int xr = n, int ind = 1) { if (xr <= ql || qr <= xl) return; if (ql <= xl && xr <= qr) { handle(ind, qv); return; } int xm = (xl + xr) / 2; shift(ind); add(ql, qr, qv, xl, xm, ind * 2); add(ql, qr, qv, xm, xr, ind * 2 + 1); f[ind] = f[ind * 2]; vector<int> tmp; tmp.push_back(f[ind * 2 + 1] ^ f[ind * 2]); seg[ind] = merge(merge(seg[ind * 2], seg[ind * 2 + 1]), tmp); } vector<int> get(int ql, int qr, int xl = 0, int xr = n, int ind = 1) { if (xr <= ql || qr <= xl) return vector<int>(); if (ql <= xl && xr <= qr) return val(ind); int xm = (xl + xr) / 2; shift(ind); return merge(get(ql, qr, xl, xm, ind * 2), get(ql, qr, xm, xr, ind * 2 + 1)); } int main() { ios::sync_with_stdio(false); cin.tie(0); int q; cin >> n >> q; for (int i = 0; i < n; i++) { int x; cin >> x; add(i, i + 1, x); } for (int i = 0; i < q; i++) { int t; cin >> t; if (t == 1) { int l, r, k; cin >> l >> r >> k; add(l - 1, r, k); } else { int l, r; cin >> l >> r; cout << (1 << get(l - 1, r).size()) << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[100005], n, x, minn = 3; bool m1[100005], m2[100005]; int read() { int w = 0, f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { w = (w << 3) + (w << 1) + (c ^ 48); c = getchar(); } return w * f; } int main() { n = read(), x = read(); for (int i = 1; i <= n; i++) { a[i] = read(); } for (int i = 1; i <= n; i++) { if (m1[a[i]]) minn = min(0, minn); if (m2[a[i]]) minn = min(1, minn); if (m1[a[i] & x]) minn = min(1, minn); if (m2[a[i] & x]) minn = min(2, minn); m1[a[i]] = 1, m2[a[i] & x] = 1; } if (minn == 3) puts( -1 ); else printf( %d n , minn); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n1, n2; cin >> n1 >> n2; int k, m; cin >> k >> m; long long a[n1], b[n2]; for (int i = 0; i < n1; i++) cin >> a[i]; for (int i = 0; i < n2; i++) cin >> b[i]; int count = 0; for (int i = 0; i < n1; i++) { if (a[i] >= b[n2 - m]) break; count++; if (count >= k) break; } if (count >= k && n2 >= m) cout << YES n ; else cout << NO n ; }
|
/*
* From IEEE 1800-2012
*
* 5.8 Time literals
*
* Time is written in integer or fixed-point format, followed without a space by a
* time unit ( fs ps ns us ms s ).
* For example:
* 2.1ns
* 40ps
* The time literal is interpreted as a realtime value scaled to the current time
* unit and rounded to the current time precision.
*/
module same;
timeunit 1ps;
timeprecision 1ps;
function logic check_time;
realtime result;
check_time = 1'b1;
result = 1ns;
if (result != 1000.0) begin
$display("Failed-same: Expected 1ns to be rounded to 1000.0, got %f", result);
check_time = 1'b0;
end
result = 1ps;
if (result != 1.0) begin
$display("Failed-same: Expected 1ps to be rounded to 1.0, got %f", result);
check_time = 1'b0;
end
result = 0.5ps;
if (result != 1.0) begin
$display("Failed-same: Expected 0.5ps to be rounded to 1.0, got %f", result);
check_time = 1'b0;
end
result = 0.499ps;
if (result != 0.0) begin
$display("Failed-same: Expected 0.49ps to be rounded to 0.0, got %f", result);
check_time = 1'b0;
end
endfunction
endmodule
module max;
timeunit 100s;
timeprecision 1fs;
function logic check_time;
realtime result;
check_time = 1'b1;
result = 1s;
if (result != 1e-2) begin
$display("Failed-max: Expected 1s to be rounded to 1.0e-2, got %f", result);
check_time = 1'b0;
end
result = 0.5fs;
if (result != 1e-17) begin
$display("Failed-max: Expected 0.5fs to be rounded to 1.0e-17, got %f", result);
check_time = 1'b0;
end
result = 0.499fs;
if (result != 0.0) begin
$display("Failed-max: Expected 0.49fs to be rounded to 0.0, got %f", result);
check_time = 1'b0;
end
endfunction
endmodule
module top;
timeunit 1ns;
timeprecision 1ps;
realtime result;
logic passed;
initial begin
passed = 1'b1;
result = 1ns;
if (result != 1.0) begin
$display("Failed: Expected 1ns to be rounded to 1.0, got %f", result);
passed = 1'b0;
end
result = 1ps;
if (result != 0.001) begin
$display("Failed: Expected 1ps to be rounded to 0.001, got %f", result);
passed = 1'b0;
end
result = 1.23456789ps;
if (result != 0.001) begin
$display("Failed: Expected 1.23456789ps to be rounded to 0.001, got %f", result);
passed = 1'b0;
end
result = 0.5ps;
if (result != 0.001) begin
$display("Failed: Expected 0.5ps to be rounded to 0.001, got %f", result);
passed = 1'b0;
end
result = 0.499ps;
if (result != 0.0) begin
$display("Failed: Expected 0.49ps to be rounded to 0.0, got %f", result);
passed = 1'b0;
end
passed &= same.check_time();
passed &= max.check_time();
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const long long N = 2005; void init() {} long long n, m, k; long long dp[N][N]; void solve() { scanf( %lld%lld%lld , &n, &m, &k); dp[1][0] = m; for (long long i = 2; i <= n; i++) { for (long long j = 0; j < i; j++) { dp[i][j] = (dp[i][j] + dp[i - 1][j]) % MOD; if (j) dp[i][j] = (dp[i][j] + dp[i - 1][j - 1] * (m - 1) % MOD) % MOD; } } printf( %lld n , dp[n][k]); } signed main() { long long TTT = 1; while (TTT--) { init(); solve(); } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module usdrx1_spi (
spi_afe_csn,
spi_clk_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_afe_sdio,
spi_clk_sdio);
// 4 wire
input [ 3:0] spi_afe_csn;
input spi_clk_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_afe_sdio;
inout spi_clk_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire [ 1:0] spi_csn_3_s;
wire spi_csn_s;
wire spi_enable_s;
wire spi_afe_miso_s;
wire spi_clk_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_3_s[1] = & spi_afe_csn;
assign spi_csn_3_s[0] = spi_clk_csn;
assign spi_csn_s = & spi_csn_3_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_csn_3_s[1] == 1'b0)) ||
((spi_count == 6'd16) && (spi_csn_3_s[0] == 1'b0))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) |
(spi_clk_miso_s & ~spi_csn_3_s[0]));
// io buffers
assign spi_afe_miso_s = spi_afe_sdio;
assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
assign spi_clk_miso_s = spi_clk_sdio;
assign spi_clk_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:02:15 03/12/2015
// Design Name:
// Module Name: pal_generator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pal_sync_generator (
input wire clk,
input wire [1:0] mode, // 00: 48K, 01: 128K, 10: Pentagon, 11: Reserved
input wire rasterint_enable,
input wire vretraceint_disable,
input wire [8:0] raster_line,
output wire raster_int_in_progress,
input wire csync_option,
input wire [8:0] hinit48k,
input wire [8:0] vinit48k,
input wire [8:0] hinit128k,
input wire [8:0] vinit128k,
input wire [8:0] hinitpen,
input wire [8:0] vinitpen,
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
output wire [8:0] hcnt,
output wire [8:0] vcnt,
output reg [2:0] ro,
output reg [2:0] go,
output reg [2:0] bo,
output reg hsync,
output reg vsync,
output reg csync,
output wire int_n
);
reg [8:0] hc = 9'h000;
reg [8:0] vc = 9'h000;
reg [8:0] hc_sync = 9'd104;
reg [8:0] vc_sync = 9'd0;
reg [8:0] end_count_h = 9'd447;
reg [8:0] end_count_v = 9'd311;
reg [8:0] begin_hblank = 9'd320;
reg [8:0] end_hblank = 9'd415;
reg [8:0] begin_hsync = 9'd344;
reg [8:0] end_hsync = 9'd375;
reg [8:0] begin_vblank = 9'd248;
reg [8:0] end_vblank = 9'd255;
reg [8:0] begin_vsync = 9'd248;
reg [8:0] end_vsync = 9'd251;
reg [8:0] begin_vcint = 9'd248;
reg [8:0] end_vcint = 9'd248;
reg [8:0] begin_hcint = 9'd2;
reg [8:0] end_hcint = 9'd65;
//reg [1:0] old_mode = 2'b11;
assign hcnt = hc;
assign vcnt = vc;
always @(posedge clk) begin
if (hc_sync == end_count_h) begin
hc_sync <= 9'd0;
if (vc_sync == end_count_v) begin
vc_sync <= 9'd0;
end
else begin
vc_sync <= vc_sync + 9'd1;
end
end
else begin
hc_sync <= hc_sync + 9'd1;
end
if (hc == end_count_h) begin
hc <= 9'd0;
if (vc == end_count_v) begin
vc <= 9'd0;
case (mode)
2'b00: begin // timings for Sinclair 48K
end_count_h <= 9'd447;
end_count_v <= 9'd311;
hc_sync <= hinit48k;
vc_sync <= vinit48k;
begin_hblank <= 9'd320;
end_hblank <= 9'd415;
begin_hsync <= 9'd344;
end_hsync <= 9'd375;
begin_vblank <= 9'd248;
end_vblank <= 9'd255;
begin_vsync <= 9'd248;
end_vsync <= 9'd251;
begin_vcint <= 9'd248;
end_vcint <= 9'd248;
begin_hcint <= 9'd2;
end_hcint <= 9'd65;
end
2'b01: begin // timings for Sinclair 128K/+2 grey
end_count_h <= 9'd455;
end_count_v <= 9'd310;
hc_sync <= hinit128k;
vc_sync <= vinit128k;
begin_hblank <= 9'd320;
end_hblank <= 9'd415;
begin_hsync <= 9'd344;
end_hsync <= 9'd375;
begin_vblank <= 9'd248;
end_vblank <= 9'd255;
begin_vsync <= 9'd248;
end_vsync <= 9'd251;
begin_vcint <= 9'd248;
end_vcint <= 9'd248;
begin_hcint <= 9'd4;
end_hcint <= 9'd67;
end
2'b10,
2'b11: begin // timings for Pentagon 128
end_count_h <= 9'd447;
end_count_v <= 9'd319;
hc_sync <= hinitpen;
vc_sync <= vinitpen;
begin_hblank <= 9'd336; // 9'd328;
end_hblank <= 9'd399; // 9'd391;
begin_hsync <= 9'd336; // 9'd328;
end_hsync <= 9'd367; // 9'd359;
begin_vblank <= 9'd240;
end_vblank <= 9'd271; // 9'd255;
begin_vsync <= 9'd240;
end_vsync <= 9'd255; // 9'd243;
begin_vcint <= 9'd239;
end_vcint <= 9'd239;
begin_hcint <= 9'd323; // 9'd323;
end_hcint <= 9'd386; //9'd386;
end
endcase
end
else
vc <= vc + 9'd1;
end
else
hc <= hc + 9'd1;
end
// INT generation
reg vretrace_int_n, raster_int_n;
assign int_n = vretrace_int_n & raster_int_n;
assign raster_int_in_progress = ~raster_int_n;
always @* begin
vretrace_int_n = 1'b1;
if (vretraceint_disable == 1'b0 && (hc >= begin_hcint && vc == begin_vcint) && (hc <= end_hcint && vc == end_vcint))
vretrace_int_n = 1'b0;
raster_int_n = 1'b1;
if (rasterint_enable == 1'b1 && hc >= 256 && hc <= 319) begin
if (raster_line == 9'd0 && vc == end_count_v)
raster_int_n = 1'b0;
if (raster_line != 9'd0 && vc == (raster_line - 9'd1))
raster_int_n = 1'b0;
end
end
always @* begin
ro = ri;
go = gi;
bo = bi;
hsync = 1'b1;
vsync = 1'b1;
if ( (hc >= begin_hblank && hc <= end_hblank) || (vc >= begin_vblank && vc <= end_vblank) ) begin
ro = 3'b000;
go = 3'b000;
bo = 3'b000;
if (hc >= begin_hsync && hc <= end_hsync)
hsync = 1'b0;
if (vc >= begin_vsync && vc <= end_vsync)
vsync = 1'b0;
end
end
always @* begin
csync = 1'b1;
if (csync_option == 1'b1) begin
if (vc_sync < 9'd248 || vc_sync > 9'd255) begin
if (hc_sync >= 9'd0 && hc_sync <= 9'd27)
csync = 1'b0;
end
else if (vc_sync == 9'd248 || vc_sync == 9'd249 || vc_sync == 9'd250 || vc_sync == 9'd254 || vc_sync == 9'd255) begin
if ((hc_sync >= 9'd0 && hc_sync <= 9'd13) || (hc_sync >= 9'd224 && hc_sync <= 9'd237))
csync = 1'b0;
end
else if (vc_sync == 9'd251 || vc_sync == 9'd252) begin
if ((hc_sync >= 9'd0 && hc_sync <= 9'd210) || (hc_sync >= 9'd224 && hc_sync <= 9'd433))
csync = 1'b0;
end
else begin // linea 253
if ((hc_sync >= 9'd0 && hc_sync <= 9'd210) || (hc_sync >= 9'd224 && hc_sync <= 9'd237))
csync = 1'b0;
end
end
else begin
if ((hc_sync >= 9'd0 && hc_sync <= 9'd27) || (vc_sync >= 9'd248 && vc_sync <= 9'd251))
csync = 1'b0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__TAP_FUNCTIONAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tap (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int k, n, root, par[100005]; vector<int> v[100005]; bool vis[100005], fr; void findroot(int u, int l) { int i; if (v[u].size() == 1 && l == 2 * k) { fr = true; root = u; } for (i = 0; i < v[u].size(); i++) { if (fr) break; if (!vis[v[u][i]]) { vis[v[u][i]] = true; par[v[u][i]] = u; findroot(v[u][i], l + 1); } } } void dfs(int u, int l) { int i; if (v[u].size() == 1 && l != k) fr = true; if (u != root && l != k && v[u].size() < 4) fr = true; for (i = 0; i < v[u].size(); i++) { if (fr) break; if (!vis[v[u][i]]) { vis[v[u][i]] = true; dfs(v[u][i], l + 1); } } } int main() { int i, x, y, leaf, cnt = 0; cin >> n >> k; for (i = 0; i < n - 1; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } if (n == 1) { cout << No n ; return 0; } for (i = 1; i <= n; i++) if (v[i].size() == 1) { leaf = i; break; } memset(vis, false, sizeof(vis)); vis[leaf] = true; fr = false; findroot(leaf, 0); if (!fr) { cout << No n ; return 0; } while (cnt != k) { root = par[root]; cnt++; } if (v[root].size() < 3) { cout << No n ; return 0; } memset(vis, false, sizeof(vis)); vis[root] = true; fr = false; dfs(root, 0); if (fr) { cout << No n ; } else cout << Yes n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<long long> a(n); for (long long& v : a) cin >> v; vector<long long> p(n); for (long long& v : p) cin >> v; int m; cin >> m; vector<long long> b(m); for (long long& v : b) cin >> v; vector<long long> cost(m + 1); for (int i = 0; i < n; i++) { int j = lower_bound(b.begin(), b.end(), a[i]) - b.begin(); if (j == m) cost[m] += p[i]; else if (p[i] < 0) { cost[j] += p[i]; } } vector<long long> dp(m + 1, 1e18); dp[0] = 0; for (int i = 0; i < n; i++) { int j = lower_bound(b.begin(), b.end(), a[i]) - b.begin(); if (j == m) continue; if (b[j] == a[i]) { long long take_cost = 0; if (p[i] < 0) take_cost = -p[i]; dp[j + 1] = min(dp[j + 1], dp[j] + cost[j] + take_cost); } if (p[i] > 0) { cost[j] += p[i]; } } if (dp[m] > 1e17) { cout << NO << endl; return 0; } cout << YES << endl; cout << dp[m] + cost[m] << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; vector<vector<int> > v(N); int col[N]; int par[N]; int n; int in[N], out[N]; int timer; bool all_same[N]; bool can[N]; int euler[2 * N]; int tree[8 * N]; int answer = -1; void dfs(int node) { all_same[node] = true; can[node] = true; timer++; in[node] = timer; euler[timer] = col[node]; for (int to : v[node]) { if (to == par[node]) continue; par[to] = node; dfs(to); can[node] &= (all_same[to]); all_same[node] &= (all_same[to] and (col[node] == col[to])); } out[node] = timer; } void build(int id, int lo, int hi) { if (lo == hi) { tree[id] = euler[lo]; return; } int mid = (lo + hi) >> 1; build(2 * id, lo, mid); build(2 * id + 1, mid + 1, hi); if (tree[2 * id + 1] == tree[2 * id]) tree[id] = tree[2 * id]; } int query(int id, int lo, int hi, int l, int r) { if (r < l) return -2; if (l > hi or r < lo) return -2; if (l <= lo and r >= hi) { if (tree[id] == 0) return -1; return (tree[id]); } int mid = (lo + hi) >> 1; int tmp1 = query(2 * id, lo, mid, l, r); int tmp2 = query(2 * id + 1, mid + 1, hi, l, r); if (tmp1 == tmp2) { return tmp1; } if (tmp1 == -2) { return tmp2; } if (tmp2 == -2) { return tmp1; } return -1; } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d %d , &x, &y); v[x].emplace_back(y); v[y].emplace_back(x); } for (int i = 1; i <= n; i++) { scanf( %d , &col[i]); } dfs(1); build(1, 1, timer); for (int i = 1; i <= n; i++) { if (can[i]) { int node = i; int tmp1 = query(1, 1, timer, 1, in[node] - 1); int tmp2 = query(1, 1, timer, out[node] + 1, timer); if ((tmp1 == tmp2 and tmp1 != -1) or (tmp1 == -2 and tmp2 != -1) or (tmp1 != -1 and tmp2 == -2)) { puts( YES ); printf( %d n , i); return 0; } } } puts( NO ); }
|
module SuperAdder(a,b,cin,s,cout);
input wire [3:0]a;
input wire [3:0]b;
input wire cin;
output wire [3:0]s;
output wire cout;
wire [3:0]c;
wire [3:0]G;
wire [3:0]P;
assign G[3]=a[3]&&b[3];
assign G[2]=a[2]&&b[2];
assign G[1]=a[1]&&b[1];
assign G[0]=a[0]&&b[0];
assign P[3]=a[3]&&~b[3]||~a[3]&&b[3];
assign P[2]=a[2]&&~b[2]||~a[2]&&b[2];
assign P[1]=a[1]&&~b[1]||~a[1]&&b[1];
assign P[0]=a[0]&&~b[0]||~a[0]&&b[0];
wire [3:0]c3;
wire [2:0]c2;
wire [1:0]c1;
and(c3[0],P[3],P[2],P[1],P[0],cin);
and(c3[1],P[3],P[2],P[1],G[0]);
and(c3[2],P[3],P[2],G[1]);
and(c3[3],P[3],G[2]);
and(c2[0],P[2],P[1],P[0],cin);
and(c2[1],P[2],P[1],G[0]);
and(c2[2],P[2],G[1]);
and(c1[0],P[1],P[0],cin);
and(c1[1],P[1],G[0]);
and(c0,P[0],cin);
or(cout,c3[0],c3[1],c3[2],c3[3],G[3]);
or(c[2],c2[0],c2[1],c2[2],G[2]);
or(c[1],c1[0],c1[1],G[1]);
or(c[0],c0,G[0]);
assign s[0]=~a[0]&&(~b[0]&&cin||b[0]&&~cin)||a[0]&&(b[0]&&cin||~b[0]&&~cin);
assign s[1]=~a[1]&&(~b[1]&&c[0]||b[1]&&~c[0])||a[1]&&(b[1]&&c[0]||~b[1]&&~c[0]);
assign s[2]=~a[2]&&(~b[2]&&c[1]||b[2]&&~c[1])||a[2]&&(b[2]&&c[1]||~b[2]&&~c[1]);
assign s[3]=~a[3]&&(~b[3]&&c[2]||b[3]&&~c[2])||a[3]&&(b[3]&&c[2]||~b[3]&&~c[2]);
endmodule
|
#include <bits/stdc++.h> using namespace std; double pie = 3.14159265358979323846; bool isPowerOfTwo(long long int n) { if (n == 0) return false; return (ceill(log2l(n)) == floorl(log2l(n))); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int T, i, j, j1, k = 0, n, m, co = 0, check, mi, l, sum; long long int ans = 0; cin >> T; for (i = 0; i < T; i++) { string s, s1 = twone , s2 = two ; cin >> s; n = s.length(); set<long long int> second; for (j = 0; j < n - 4; j++) { co = 0; for (k = 0; k < 5; k++) { if (s[j + k] != s1[k]) { co = 1; break; } } if (co == 0) second.insert(j + 2); } for (j = 0; j < n - 2; j++) { co = 0; for (k = 0; k < 3; k++) { if (s[j + k] != s2[k]) { co = 1; break; } } if (co == 0 && second.find(j + 2) == second.end()) second.insert(j + 1); } s2 = one ; for (j = 0; j < n - 2; j++) { co = 0; for (k = 0; k < 3; k++) { if (s[j + k] != s2[k]) { co = 1; break; } } if (co == 0 && second.find(j) == second.end()) second.insert(j + 1); } cout << second.size() << endl; for (auto w : second) { cout << w + 1 << ; } cout << endl; } }
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#include <bits/stdc++.h> using namespace std; int bit[100005], n, dt; set<int> ms; vector<int> nums, ops; void add(int pos, int val) { while (pos <= (int)nums.size()) { bit[pos] += val; pos += (-pos) & pos; } } int sum(int pos) { int res = 0; while (pos > 0) { res += bit[pos]; pos -= (-pos) & pos; } return res; } struct range { int l, r, cnt, cov; long long sum[5]; range(int L, int R) { l = L; r = R; cov = 0; cnt = 0; memset(sum, 0, sizeof(sum)); } range() { l = r = cnt = cov = 0; memset(sum, 0, sizeof(sum)); } }; range operator+(range a, range b) { range c = a; c.r = b.r; c.cnt += b.cnt; int xb; for (xb = 0; xb < 5; xb++) c.sum[xb] += b.sum[(xb + 10 - b.cov + a.cov) % 5]; return c; } range operator-(range a, range b) { range c = a; c.r = b.r; c.cnt -= b.cnt; int xb; for (xb = 0; xb < 5; xb++) c.sum[xb] -= b.sum[(xb + 10 - b.cov + a.cov) % 5]; return c; } void proc(range &a, range b, int type) { int xb; if (type == 1) { a = a - b; a.cnt += b.cnt; for (xb = 0; xb < 5; xb++) a.sum[xb] += b.sum[(xb + 15 - b.cov + a.cov - 1) % 5]; } else { a = a - b; a.cnt += b.cnt; for (xb = 0; xb < 5; xb++) a.sum[xb] += b.sum[(xb + 15 - b.cov + a.cov + 1) % 5]; } } struct SegT { range tree[300005]; void init(int pos, int l, int r) { tree[pos].l = l; tree[pos].r = r; memset(tree[pos].sum, 0, sizeof(tree[pos].sum)); tree[pos].cnt = tree[pos].cov = 0; if (l != r) { int m = (l + r) / 2; init(pos * 2, l, m); init(pos * 2 + 1, m + 1, r); } } range query(int pos, int l, int r) { if (l <= tree[pos].l && r >= tree[pos].r) return tree[pos]; int m = (tree[pos].l + tree[pos].r) / 2; range ret = range(tree[pos].l, 0); if (l <= m) ret = ret + query(pos * 2, l, r); if (r > m) ret = ret + query(pos * 2 + 1, l, r); ret.cov += tree[pos].cov; ret.r = tree[pos].r; ret.cov %= 5; return ret; } void addcov(int pos, int l, int r, int v) { if (l <= tree[pos].l && r >= tree[pos].r) { tree[pos].cov += v; tree[pos].cov %= 5; return; } int m = (tree[pos].l + tree[pos].r) / 2; if (l <= m) addcov(pos * 2, l, r, v); if (r > m) addcov(pos * 2 + 1, l, r, v); } void edit(int pos, int d, int rst, int type, int cov) { tree[pos].cnt += type; if (d == tree[pos].r) { tree[pos].sum[(rst - cov - tree[pos].cov + 10) % 5] += type * nums[d]; if (tree[pos].l != tree[pos].r) edit(pos * 2 + 1, d, rst, type, (cov + tree[pos].cov) % 5); return; } range res = query(pos, d + 1, tree[pos].r); tree[pos].sum[(rst - cov - tree[pos].cov + 10) % 5] += type * nums[d]; proc(tree[pos], res, type); int m = (tree[pos].l + tree[pos].r) / 2; if (d <= m) { edit(pos * 2, d, rst, type, (cov + tree[pos].cov) % 5); addcov(pos * 2 + 1, m + 1, tree[pos].r, type); } else { edit(pos * 2 + 1, d, rst, type, (cov + tree[pos].cov) % 5); } } } T; int Bsearch(int key) { int left = 1, right = (int)nums.size(), mid; while (left < right) { mid = (left + right) / 2; if (nums[mid] < key) left = mid + 1; else right = mid; } return left; } char inp[100005][10]; int main() { ms.clear(); int xb, x2, op; scanf( %d , &n); if (n == 1) { scanf( %s , inp[0]); if (inp[0][0] == s ) printf( 0 ); return 0; } for (xb = 0; xb < n; xb++) { scanf( %s , inp[xb]); if (inp[xb][0] == a ) { scanf( %d , &op); ops.push_back(op); ms.insert(op); } else if (inp[xb][0] == d ) { scanf( %d , &op); ops.push_back(op); } else ops.push_back(-1); } set<int>::iterator it; nums.push_back(-1); for (it = ms.begin(); it != ms.end(); it++) { nums.push_back(*it); } T.init(1, 1, nums.size() - 1); for (xb = 0; xb < n; xb++) { if (inp[xb][0] == a ) { int d = Bsearch(ops[xb]), rst = sum(d - 1); add(d, 1); T.edit(1, d, rst, 1, 0); } else if (inp[xb][0] == d ) { int d = Bsearch(ops[xb]), rst = sum(d - 1); add(d, -1); T.edit(1, d, rst, -1, 0); } else { range res = T.query(1, 1, nums.size() - 1); printf( %I64d n , res.sum[(7 - res.cov) % 5]); } } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; char A[200]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> A[i]; for (int i = 1; i <= n; i++) { for (int j = 1; 4 * j <= n; j++) { if (A[i] == * ) if (A[i] == A[i + j]) if (A[i + j] == A[i + 2 * j]) if (A[i + 2 * j] == A[i + 3 * j]) if (A[i + 3 * j] == A[i + 4 * j]) { cout << yes ; return 0; } } } cout << no ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 2e9; long long sum(long long l, long long r) { return (l + r) * (r - l + 1) / 2; } int main() { long long n, H; cin >> n >> H; long long l = H, r = 2e9, ans = -1; while (l <= r) { long long mid = (l + r) >> 1; if (n >= sum(H, mid) + sum(1, mid) - mid) ans = mid, l = mid + 1; else r = mid - 1; } if (ans != -1) { cout << 2 * ans - H + ((n - sum(H, ans) - sum(1, ans) + ans) + ans - 1) / ans << endl; } else { l = 1, r = min(H, N); while (l <= r) { long long mid = (l + r) >> 1; if (n >= sum(1, mid)) ans = mid, l = mid + 1; else r = mid - 1; } cout << ans + (n - sum(1, ans) + ans - 1) / ans << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace rel_ops; using ll = int64_t; using Pii = pair<int, int>; using ull = uint64_t; using Vi = vector<int>; void run(); int main() { cin.sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(10); run(); return 0; } int uplg(int n) { return 32 - __builtin_clz(n); } int uplg(ll n) { return 64 - __builtin_clzll(n); } struct Vert { int ver{-1}; int defPar{-1}, par; bool defBlocked{1}, blocked; }; int hei, wid, nQuestions; vector<Vert> G; set<Pii> permEdges, tempEdges; int currentVer = 1; void update(int i) { if (G[i].ver != currentVer) { G[i].ver = currentVer; G[i].par = G[i].defPar; G[i].blocked = G[i].defBlocked; } } int find(int i) { update(i); if (G[i].par == -1) return i; return G[i].par = find(G[i].par); } int join(int i, int j) { i = find(i); j = find(j); if (i == j) return i; if (rand() % 2) swap(i, j); return G[i].par = j; } int ind(int first, int second) { return first * wid + second; } Vert& vert(int i) { update(i); return G[i]; } Vert& vert(int first, int second) { return vert(ind(first, second)); } void eachNeigh(int i, int j, function<void(int, int)> func) { for (int dx = (-1); dx < (2); dx++) for (int dy = (-1); dy < (2); dy++) if (dx != 0 || dy != 0) { int first = i + dx, second = j + dy; if (first >= 0 && second >= 0 && first < hei && second < wid) { func(first, second); } } } void addEdges(int i, int j) { assert(vert(i, j).blocked); eachNeigh(i, j, [&](int first, int second) { if (vert(first, second).blocked) return; eachNeigh(first, second, [&](int a, int b) { if (vert(a, b).blocked) { int p1 = find(ind(i, j)), p2 = find(ind(a, b)); tempEdges.insert({p1, p2}); tempEdges.insert({p2, p1}); } }); }); } void query() { int k; cin >> k; vector<Pii> toBlock(k); for (auto& p : (toBlock)) cin >> p.first >> p.second; Vi toCheck; currentVer++; tempEdges.clear(); for (auto& p : (toBlock)) { vert(p.first, p.second).blocked = 1; toCheck.push_back(find(ind(p.first, p.second))); eachNeigh(p.first, p.second, [&](int i, int j) { if (vert(i, j).blocked) { toCheck.push_back(find(ind(i, j))); join(ind(i, j), ind(p.first, p.second)); } }); addEdges(p.first, p.second); toCheck.push_back(find(ind(p.first, p.second))); eachNeigh(p.first, p.second, [&](int i, int j) { if (vert(i, j).blocked) { toCheck.push_back(find(ind(i, j))); } }); } int top = find(ind(0, 3)), bottom = find(ind(3, 0)); toCheck.push_back(top); toCheck.push_back(bottom); for (auto& i : (toCheck)) if (find(i) == top) { for (auto& j : (toCheck)) if (find(j) == bottom) { if (permEdges.count({i, j}) || tempEdges.count({i, j})) { cout << NO << endl; return; } } } cout << YES << endl; } void run() { cin >> hei >> wid >> nQuestions; hei += 2; wid += 2; G.resize(hei * wid); for (int i = (0); i < (3); i++) { vert(i, 0).defBlocked = vert(0, i).defBlocked = 0; vert(hei - i - 1, wid - 1).defBlocked = vert(hei - 1, wid - i - 1).defBlocked = 0; } for (int i = (1); i < (hei - 1); i++) { string tmp; cin >> tmp; for (int j = (1); j < (wid - 1); j++) vert(i, j).defBlocked = (tmp[j - 1] == # ); } for (int first = (0); first < (hei); first++) for (int second = (0); second < (wid); second++) { auto& cur = vert(first, second); if (!cur.defBlocked) continue; eachNeigh(first, second, [&](int i, int j) { if (vert(i, j).defBlocked) { join(ind(first, second), ind(i, j)); } }); } for (auto& v : (G)) v.defPar = v.par; currentVer++; for (int i = (0); i < (hei); i++) for (int j = (0); j < (wid); j++) { auto& cur = vert(i, j); if (cur.defBlocked) addEdges(i, j); } swap(tempEdges, permEdges); while (nQuestions--) query(); }
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//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: STAN_MEMC
// / / Filename: pipeline_inserter.v
// /___/ /\ Date Last Modified: $Date:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: Insert pipelines
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module pipeline_inserter(data_i, data_o, clk_i, en_i);
parameter DATA_WIDTH = 32;
parameter PIPE_STAGES = 1;
input [DATA_WIDTH-1:0] data_i;
output [DATA_WIDTH-1:0] data_o;
input clk_i;
input en_i;
genvar i;
integer j;
reg [DATA_WIDTH - 1:0] pipe_array [PIPE_STAGES+1:0];
//**********************************************************
//*
//* No Pipeline
//*
//***********************************************************/
generate
if(PIPE_STAGES == 0) begin: no_pipe
assign data_o = data_i;
end
endgenerate
//**********************************************************
//*
//* Add Pipeline
//*
//***********************************************************/
generate
if(PIPE_STAGES > 0) begin: add_pipe
initial begin
for(j = 0; j < PIPE_STAGES; j = j + 1)
pipe_array[j] <= 'b0;
end
assign data_o = pipe_array[PIPE_STAGES-1];
always @ (posedge clk_i) begin
if(en_i) begin
pipe_array[0] <= data_i;
end
end
for(i = 1; i < PIPE_STAGES; i = i + 1) begin : pipe
always @ (posedge clk_i) begin
if(en_i) begin
pipe_array[i] <= pipe_array[i-1];
end
end
end
end
endgenerate
endmodule // pipeline_inserter
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#include <bits/stdc++.h> using namespace std; int a[100005], b[100005], f[100005], cnt[100005], ans[100005]; int main() { int i, j, k, l, n, m; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> j; if (!cnt[j]) f[j] = i; cnt[j]++; } int flag = 1; l = 1; for (i = 1; i <= m; i++) { cin >> j; if (flag) if (!cnt[j]) flag = 0; else if (cnt[j] > 1) flag = 2; else ans[l++] = f[j]; } if (l == m + 1) { cout << Possible n ; for (i = 1; i <= m; i++) cout << ans[i] << ; cout << endl; } else if (!flag) cout << Impossible n ; else cout << Ambiguity n ; return 0; }
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#include <bits/stdc++.h> using namespace std; void calcula(long long int n, long long int m, long long int r[10000], long long int sumar[10000], long long int k, long long int p) { priority_queue<long long int> q; for (int i = 0; i < n; i++) q.push(r[i]); for (int paso = 1; paso <= k; paso++) { long long int x = q.top(); q.pop(); sumar[paso] = sumar[paso - 1] + x; q.push(x - m * p); } } long long int n, m, k, p; long long int c[10000], r[10000]; long long int sumac[2000000], sumar[2000000]; int main() { cin >> n >> m >> k >> p; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int a; cin >> a; r[i] += a; c[j] += a; } } calcula(n, m, r, sumar, k, p); calcula(m, n, c, sumac, k, p); long long int maximo = -1000000000000000000LL; for (long long int kc = 0; kc <= k; kc++) { long long int kr = k - kc; maximo = max(maximo, sumar[kr] + sumac[kc] - p * kc * kr); } cout << maximo << endl; }
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#include <bits/stdc++.h> using namespace std; const int MAX = (1 << 22) + 5; int n, m; bool is[MAX], seen[MAX]; int conj(int x) { int r = 0; for (int i = 0; i < n; ++i) if (!(x & (1 << i))) r += (1 << i); return r; } void dfs(int st, bool p = 0) { if (seen[st]) return; seen[st] = 1; if (is[st]) dfs(conj(st), 1); if (p) { for (int i = 0; i < n; ++i) if (st & (1 << i)) { dfs(st - (1 << i), 1); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n >> m; vector<int> st((1 << n) + 1, 0); vector<bool> lz((1 << n) + 1, 0); for (int i = 0; i < m; ++i) { int x; cin >> x; is[x] = 1; } int cnt = 0; for (int i = 0; i < (1 << n); ++i) { if (!seen[i] && is[i]) { dfs(i); ++cnt; } } cout << cnt << n ; return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 20:11:30
// Design Name:
// Module Name: _4bit_binary_multiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _4bit_binary_multiplier
#(parameter WIDTH = 4)
(
input start,
input clk,
input [WIDTH:0] multiplier_address,
input [WIDTH:0] multiplicand_address,
output [((WIDTH*2)-1):0] p,
output done
);
// default: 32 * 4 ROM
reg [(WIDTH-1):0] ROM [0: (2*(2**WIDTH)-1)];
// control unit signal
wire cnt_done, start_process, add, shift, count_up;
wire clk_process;
// adder variable
wire [(WIDTH-1):0] b, s;
wire cout;
// register variable
wire P_IN_out, P_H_shift_out, P_L_shift_out;
wire [(WIDTH-1):0] P_H_parallel_out, P_L_parallel_out, MUL_parallel_out;
// ROM data variable
wire [(WIDTH-1):0] multiplier, multiplicand;
assign b = MUL_parallel_out & {(WIDTH){P_L_parallel_out[0]}};
assign p = {P_H_parallel_out, P_L_parallel_out};
assign #7 clk_process = clk;
assign multiplier = ROM[multiplier_address];
assign multiplicand = ROM[multiplicand_address];
initial begin
$readmemb("/home/sabertazimi/gitrepo/hust-lab/verilog/lab5/ASM_4bit_binary_multiplier/ASM_4bit_binary_multiplier.srcs/sources_1/new/_4bit_binary_multiplier.dat", ROM, 0, 2*(2**WIDTH)-1);
end
binary_multiplier_control_unit UNIT (start, clk, cnt_done, P_L_parallel_out[0], start_process, add, shift, count_up, done);
shift_out_register #(1) P_IN (.start({1'b0, start_process}), .clk(clk_process), .load(~shift), .shift(shift), .D(cout), .shift_in(1'b0), .Q(), .shift_out(P_IN_out));
shift_out_register #(WIDTH) P_H (.start({{(WIDTH){1'b0}},start_process}), .clk(clk_process), .load(add), .shift(shift), .D(s), .shift_in(P_IN_out), .Q(P_H_parallel_out), .shift_out(P_H_shift_out));
shift_out_register #(WIDTH) P_L (.start({multiplier, start_process}), .clk(clk_process), .load(1'b0), .shift(shift), .D(multiplier), .shift_in(P_H_shift_out), .Q(P_L_parallel_out), .shift_out(P_L_shift_out));
parallel_out_register #(WIDTH) MUL (.start({multiplicand, start_process}), .clk(clk_process), .load(1'b0), .D(multiplicand), .Q(MUL_parallel_out));
full_adder #(WIDTH) ADDER (.start(start_process), .add(add), .a(P_H_parallel_out), .b(b), .s(s), .cout(cout));
down_counter #(WIDTH) COUNTER (.start(start), .clk(count_up), .cnt_done(cnt_done));
endmodule
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#include <bits/stdc++.h> const int maxn = 2e5 + 5; using namespace std; int rd() { int x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); return x * f; } int n, q, cnt, id, now; map<long long, int> mp; map<pair<int, int>, int> ans; vector<pair<int, int> > a[maxn]; vector<pair<int, int> >::iterator it; int gcd(int a, int b) { return (b == 0) ? a : gcd(b, a % b); } int get(long long x) { if (!mp.count(x)) mp[x] = ++id; return mp[x]; } pair<int, int> fac(int x, int y) { int z = gcd(x, y); return make_pair(x / z, y / z); } int main() { n = rd(); for (int i = 1, op, x, y; i <= n; i++) { op = rd(); x = rd(); y = rd(); long long r = 1ll * x * x + 1ll * y * y; if (op == 1) { ++cnt; now = get(r); for (int i = 0; i < ((int)a[now].size()); i++) ans[fac(a[now][i].first + x, a[now][i].second + y)] += 2; ans[fac(x, y)]++; a[now].push_back(make_pair(x, y)); } else if (op == 2) { --cnt; now = get(r); for (int i = 0; i < ((int)a[now].size()); i++) if (a[now][i] != make_pair(x, y)) ans[fac(a[now][i].first + x, a[now][i].second + y)] -= 2; ans[fac(x, y)]--; it = a[now].begin(); while (*it != make_pair(x, y)) ++it; a[now].erase(it); } else printf( %d n , cnt - ans[fac(x, y)]); } return 0; }
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module dyn_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKFX1_OUT,
CLKFX2_OUT,
CLKDV_OUT,
DCM_SP_LOCKED_OUT,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
input CLKIN_IN;
wire CLKIN_IBUFG_OUT;
wire CLK0_OUT;
output CLKFX1_OUT;
output CLKFX2_OUT;
output CLKDV_OUT;
output DCM_SP_LOCKED_OUT;
input dcm_progclk;
input dcm_progdata;
input dcm_progen;
input dcm_reset;
output dcm_progdone;
output dcm_locked;
output [2:1] dcm_status;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFX1_BUF;
wire CLKFX2_BUF;
wire CLKDV_BUF;
wire GND_BIT;
wire dcm_progclk_buf;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLKFX1_BUFG_INST (.I(CLKFX1_BUF),
.O(CLKFX1_OUT));
BUFG CLKFX2_BUFG_INST (.I(CLKFX2_BUF),
.O(CLKFX2_OUT));
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG DCMPROGCLK_BUFG_INST (.I(dcm_progclk),
.O(dcm_progclk_buf));
// 100 MHZ osc gives fixed 50MHz CLKFX1, 12.5MHZ CLKDV
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(8.0), .CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX1_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(DCM_SP_LOCKED_OUT),
.PSDONE(),
.STATUS());
DCM_CLKGEN #(
.CLKFX_DIVIDE(100), // 100Mhz osc so gives steps of 1MHz
.CLKFX_MULTIPLY(SPEED_MHZ),
.CLKFXDV_DIVIDE(2), // Unused
.CLKIN_PERIOD(10.0),
.CLKFX_MD_MAX(0.000),
.SPREAD_SPECTRUM("NONE"),
.STARTUP_WAIT("FALSE")
)
DCM_CLKGEN_INST (
.CLKIN(CLKIN_IBUFG),
.CLKFX(CLKFX2_BUF),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata),
.PROGEN(dcm_progen),
.PROGDONE(dcm_progdone),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(dcm_reset)
);
endmodule
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#include <bits/stdc++.h> int main() { int q; std::cin >> q; std::vector<int> V; for (int i = 0; i < q; ++i) { int n; std::cin >> n; std::vector<int> v1; std::vector<int> v2(n); for (int j = 0; j < n; ++j) { std::cin >> v2[j]; v1.push_back(j + 1); } for (int k = 0; k < v1.size(); ++k) { int count = 1; int num = k; while (v1[k] != v2[num]) { num = v2[num] - 1; ++count; } V.push_back(count); } V.push_back(0); } for (int i = 0; i < V.size(); ++i) { if (V[i] == 0) std::cout << n ; else { std::cout << V[i] << ; } } }
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#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; map<int, int> memo; int solve(int mask) { if (!mask) return 0; if (memo.find(mask) != memo.end()) return memo[mask]; map<int, bool> canreach; for (int i = 0; i < 32; i++) { int aux = ((1 << i) - 1) & mask; int ns = aux | ((mask - aux) >> (i + 1)); if (ns == mask) continue; canreach[solve(ns)] = true; } int mex = 0; for (int i = 0; i < 100; i++) if (!canreach[i]) { mex = i; break; } return memo[mask] = mex; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; map<int, int> mps; for (int j = 0; j < n; j++) { int val, aux; cin >> val; aux = val; for (int i = 2; i * i <= val; i++) { int cnt = 0; while (aux % i == 0) { aux /= i; cnt++; } if (cnt) mps[i] |= (1 << (cnt - 1)); } if (aux != 1) mps[aux] |= 1; } int grundy = 0; for (auto u : mps) grundy ^= solve(u.second); cout << (grundy ? Mojtaba : Arpa ) << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; m--; int cnt = 0; for (int i = 0; i < n; ++i) if (1) { bool ok = 0; for (int j = i + m; j >= 0 && j >= i - m; --j) if (j >= n) continue; else if (a[j] == 1) { cnt++; i = j + m; ok = 1; break; } if (!ok) return cout << -1, 0; } cout << cnt; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S18_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYGATE4S18_BLACKBOX_V
/**
* dlygate4s18: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlygate4s18 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S18_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; long long mo = 998244353; long long bin_fun(long long chto, long long vkak) { if (vkak == 0) return 1; if (vkak == 1) return chto; if (vkak % 2 == 0) return bin_fun(chto * chto % mo, vkak / 2); else return (bin_fun(chto * chto % mo, vkak / 2) * chto) % mo; } int main() { long long a, s, d, i, j, k; cin >> a; vector<long long> v1; for (i = 0; i < a * 2; i++) { cin >> s; v1.push_back(s); } sort(v1.begin(), v1.end()); long long sum = 0; for (i = 0; i < a; i++) sum = (sum + abs(v1[a * 2 - i - 1] - v1[i])) % mo; long long ch1 = 1, ch2 = 1; for (i = a + 1; i <= a * 2; i++) { ch1 = (ch1 * i) % mo; } for (i = 1; i <= a; i++) { long long t = bin_fun(i, mo - 2); ch2 = (ch2 * t) % mo; } long long otv = (ch1 * ch2) % mo; cout << (otv * sum) % mo; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_TB_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PR_PP_PG_N_TB_V
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; long long m_min = 1ll << 62; long long ans = 0; for (int i = 0; i < n; i++) { long long x; cin >> x; ans += x; if (x % 2 == 1) m_min = min(m_min, x); } if (ans % 2 == 1) ans -= m_min; cout << ans << n ; return 0; }
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module fifo_TB;
reg clk;
reg reset;
reg rd;
reg wr;
reg[7:0] dataint;
fifo uttf(.rd(rd),.wr(wr),.din(dataint),.clk(clk),.reset(reset));
always
begin
clk =1'b1;
#10;
clk=1'b0;
#10;
end
initial
begin
reset = 1'b1;
#4 reset = 1'b0;
end
initial
begin
wr = 1'b0;
#34300;
wr=1'b1;
#343000;
wr = 1'b0;
#343000;
/*wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;
#3430;
wr = 1'b1;
#3430;
wr=1'b0;*/
end
initial
begin
rd=1'b0;
#643000;
rd=1'b1;
#343000;
rd=1'b0;
#34300;
/*
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;
#3430;
rd=1'b1;
#3430;
rd=1'b0;*/
end
initial begin
#3430 dataint = 7'h1;
#3400 dataint = 7'h3;
#3400 dataint = 7'hA;
#3400 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3430 dataint = 7'h1;
#3400 dataint = 7'h3;
#3400 dataint = 7'hA;
#3400 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3430 dataint = 7'h1;
#3400 dataint = 7'h3;
#3400 dataint = 7'hA;
#3400 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3400 dataint = 7'hA;
#3400 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3430 dataint = 7'h05;
#3430 dataint = 7'h1;
#3400 dataint = 7'h3;
#3400 dataint = 7'hA;
#3400 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3400 dataint = 7'hA;
#3400 dataint = 7'h3;
#3430 dataint = 7'hA;
#3430 dataint = 7'h05;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
#3430 dataint = 1'b1;
#3430 dataint = 1'b0;
end
initial begin: TEST_CASE
$dumpfile("fifo_TB.vcd");
$dumpvars(-1, uttf);
#() $finish;
end
endmodule //
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#include <bits/stdc++.h> using namespace std; int main() { int n, m, s1 = 0, s2 = 0; cin >> n; vector<int> v1(n); for (int i = 0; i < n; i++) cin >> v1[i]; cin >> m; vector<int> v2(m); for (int i = 0; i < m; i++) cin >> v2[i]; sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); int res = 0; while (s1 < n && s2 < m) { if (abs(v1[s1] - v2[s2]) <= 1) { res++; s1++; s2++; } else if (v1[s1] > v2[s2]) s2++; else s1++; } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; string s; set<string> st; int main() { ios_base::sync_with_stdio(0); cin.tie(0); while (cin >> s) { st.clear(); for (int i = 0; i < s.size(); i++) { string s1 = ; for (int j = 0; j < s.size(); j++) s1 += s[(i + j) % s.size()]; st.insert(s1); } cout << st.size() << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> inline bool chkmin(T &a, T const &b) { return a > b ? a = b, 1 : 0; } template <class T> inline bool chkmax(T &a, T const &b) { return a < b ? a = b, 1 : 0; } const int M = 35; const int N = 205; const int Mod = 998244353; long long A[M], a[M][M * N]; vector<int> F[M][M * N]; int Sz[M], C[N][N], S[M * N], Inv[N]; int n; int calc(vector<int> &P, long long l, long long r) { int res = 0, x = 1, y = 1; l = l % Mod * 616898040 % Mod; r = r % Mod * 616898040 % Mod; for (int i = (0), i_end__ = (P.size()); i < i_end__; i++) { res = (res + (long long)(y - x) * P[i]) % Mod; x = ((long long)(x) * (l) % Mod), y = ((long long)(y) * (r) % Mod); } return res; } int main() { for (int i = (0), i_end__ = (N); i < i_end__; i++) { C[i][0] = 1; for (int j = (1), j_end__ = (i + 1); j < j_end__; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % Mod; } Inv[1] = 1; for (int i = (2), i_end__ = (N); i < i_end__; i++) Inv[i] = ((long long)(-Mod / i) * (Inv[Mod % i]) % Mod); scanf( %d , &n); for (int i = (0), i_end__ = (n); i < i_end__; i++) { double x; scanf( %lf , &x); A[i] = min(x, i + 1.0) * 1000000 + 0.5; } Sz[0] = 2; F[0][1].push_back(0), F[0][1].push_back(1); F[0][2].push_back(0); a[0][1] = A[0]; for (int i = (1), i_end__ = (n); i < i_end__; i++) { for (int j = (1), j_end__ = (Sz[i - 1]); j < j_end__; j++) S[j] = (S[j - 1] + calc(F[i - 1][j], a[i - 1][j - 1], a[i - 1][j])) % Mod; int pos = lower_bound(a[i - 1], a[i - 1] + Sz[i - 1], A[i]) - a[i - 1]; a[i - 1][pos] = A[i]; a[i - 1][pos + 1] = 0x3f3f3f3f3f3f3f3fLL; F[i][0].push_back(0), Sz[i] = 1; int l = 0, r = 1; long long lp = -1000000, rp = 0; while (r <= pos) { long long Next = min(a[i - 1][l] - lp, a[i - 1][r] - rp); a[i][Sz[i]] = rp + Next; vector<int> &poy = F[i][Sz[i]]; poy.resize(max(F[i - 1][r].size(), F[i - 1][l].size()) + 1); poy[1] = (calc(F[i - 1][l], 0, a[i - 1][l]) - calc(F[i - 1][r], 0, a[i - 1][r - 1])) % Mod; if (l < r) poy[1] = ((long long)poy[1] + S[r - 1] - S[l]) % Mod; for (int j = (0), j_end__ = (F[i - 1][r].size()); j < j_end__; j++) poy[j + 1] = (poy[j + 1] + F[i - 1][r][j]) % Mod; for (int j = (1), j_end__ = (F[i - 1][l].size()); j < j_end__; j++) for (int k = (0), k_end__ = (j + 1); k < k_end__; k++) poy[k + 1] = (poy[k + 1] + ((j - k) & 1 ? 1LL : -1LL) * C[j][k] * F[i - 1][l][j]) % Mod; for (int j = (1), j_end__ = (poy.size()); j < j_end__; j++) poy[j] = ((long long)(poy[j]) * (Inv[j]) % Mod); if ((lp += Next) == a[i - 1][l]) l++; if ((rp += Next) == a[i - 1][r]) r++; Sz[i]++; } F[i][Sz[i]].push_back(0); } int ans = 0; for (int j = (1), j_end__ = (Sz[n - 1]); j < j_end__; j++) (ans += calc(F[n - 1][j], a[n - 1][j - 1], a[n - 1][j])) %= Mod; printf( %d n , (ans + Mod) % Mod); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long inf = LLONG_MAX / 2; const long long MX = 1e5 + 10; int a[MX]; set<int> s; vector<int> v; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; for (long long(i) = (0); (i) <= (n - 1); ++(i)) { cin >> a[i]; s.insert(a[i]); } int num = 1; while (m >= num) { if (!s.count(num)) { m -= num; v.push_back(num); } num++; } cout << v.size() << endl; for (auto it : v) { cout << it << ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:16:05 04/24/2015
// Design Name:
// Module Name: StartCastle
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HallwayLeft(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
//Top wall with door
if(((CurrentY < 40) && (CurrentX < 260)) || ((CurrentY < 40) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end
//left wall
else if(CurrentX < 40)
mColor[7:0] <= wall;
//Bottom wall
else if(~(CurrentY < 440)) begin
mColor[7:0] <= wall;
//Floor area
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
/**
\file "channel-expect-fail.v"
Chain a source and sink in prsim to verilog.
$Id: $
*/
`timescale 1ns/1ps
`include "standard.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg l0, l1, re;
wire le, r0, r1;
DELAY #(0.01) d0(l0, r0);
DELAY #(0.01) d1(l1, r1);
DELAY #(0.01) de(re, le);
// prsim stuff
initial
begin
// @haco@ channel-source-sink.haco-c
$prsim("channel-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
$prsim_cmd("mode fatal");
$from_prsim("L.d[0]","TOP.l0");
$from_prsim("L.d[1]","TOP.l1");
$to_prsim("TOP.le", "L.e");
$to_prsim("TOP.r0", "R.d[0]");
$to_prsim("TOP.r1", "R.d[1]");
$from_prsim("R.e", "TOP.re");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel L e:1 :0 d:2");
$prsim_cmd("channel R e:1 :0 d:2");
$prsim_cmd("channel-source-args-loop L 0 1 1 0 0 1");
$prsim_cmd("channel-sink R");
$prsim_cmd("channel-expect-args-loop R 0 1 1 0 0 0");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-reset-all");
// $prsim_cmd("channel-show-all");
#1
$prsim_cmd("channel-release-all");
// $prsim_cmd("channel-show-all");
#5
$prsim_cmd("channel-show-all");
$finish;
end
endmodule
|
#include <bits/stdc++.h> int kx[8] = {+2, +2, -2, -2, +1, +1, -1, -1}; int ky[8] = {+1, -1, +1, -1, +2, -2, +2, -2}; int d9x[9] = {+1, +1, +1, +0, +0, +0, -1, -1, -1}; int d9y[9] = {+1, +0, -1, +1, +0, -1, +1, +0, -1}; int dx4[4] = {+0, +0, +1, -1}; int dy4[4] = {+1, -1, +0, +0}; long long int gcd(unsigned long long int a, unsigned long long int b) { return (a == 0) ? b : gcd(b % a, a); } long long int lcm(unsigned long long int a, unsigned long long int b) { return a * (b / gcd(a, b)); } const long long INF = 1e18; using namespace std; int main() { int T; cin >> T; while (T--) { int n; cin >> n; int a[n]; int earliest[n + 1]; memset(earliest, -1, sizeof(earliest)); for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 0; i < n; ++i) { if (earliest[a[i]] == -1) { earliest[a[i]] = i; } else if (earliest[a[i]] < i - 1) { cout << YES n ; goto end_of_loop; } } cout << NO n ; end_of_loop:; } }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_ctlif #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg irq,
output reg start,
input busy,
output reg [6:0] vertex_hlast,
output reg [6:0] vertex_vlast,
output reg [5:0] brightness,
output reg chroma_key_en,
output reg [15:0] chroma_key,
output reg [28:0] vertex_adr,
output reg [fml_depth-1-1:0] tex_fbuf,
output reg [10:0] tex_hres,
output reg [10:0] tex_vres,
output reg [17:0] tex_hmask,
output reg [17:0] tex_vmask,
output reg [fml_depth-1-1:0] dst_fbuf,
output reg [10:0] dst_hres,
output reg [10:0] dst_vres,
output reg signed [11:0] dst_hoffset,
output reg signed [11:0] dst_voffset,
output reg [10:0] dst_squarew,
output reg [10:0] dst_squareh,
output reg alpha_en,
output reg [5:0] alpha,
input [21:0] c_req_a,
input [21:0] c_hit_a,
input [21:0] c_req_b,
input [21:0] c_hit_b,
input [21:0] c_req_c,
input [21:0] c_hit_c,
input [21:0] c_req_d,
input [21:0] c_hit_d
);
reg old_busy;
always @(posedge sys_clk) begin
if(sys_rst)
old_busy <= 1'b0;
else
old_busy <= busy;
end
wire csr_selected = csr_a[13:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
irq <= 1'b0;
start <= 1'b0;
vertex_hlast <= 7'd32;
vertex_vlast <= 7'd24;
brightness <= 6'd63;
chroma_key_en <= 1'b0;
chroma_key <= 16'd0;
vertex_adr <= 29'd0;
tex_fbuf <= {fml_depth{1'b0}};
tex_hres <= 11'd512;
tex_vres <= 11'd512;
tex_hmask <= {18{1'b1}};
tex_vmask <= {18{1'b1}};
dst_fbuf <= {fml_depth{1'b0}};
dst_hres <= 11'd640;
dst_vres <= 11'd480;
dst_hoffset <= 12'd0;
dst_voffset <= 12'd0;
dst_squarew <= 11'd16;
dst_squareh <= 11'd16;
alpha_en <= 1'b0;
alpha <= 6'd63;
end else begin
irq <= old_busy & ~busy;
csr_do <= 32'd0;
start <= 1'b0;
if(csr_selected) begin
if(csr_we) begin
case(csr_a[4:0])
5'b00000: begin
start <= csr_di[0];
chroma_key_en <= csr_di[1];
end
5'b00001: vertex_hlast <= csr_di[6:0];
5'b00010: vertex_vlast <= csr_di[6:0];
5'b00011: brightness <= csr_di[5:0];
5'b00100: chroma_key <= csr_di[15:0];
5'b00101: vertex_adr <= csr_di[31:3];
5'b00110: tex_fbuf <= csr_di[fml_depth-1:1];
5'b00111: tex_hres <= csr_di[10:0];
5'b01000: tex_vres <= csr_di[10:0];
5'b01001: tex_hmask <= csr_di[17:0];
5'b01010: tex_vmask <= csr_di[17:0];
5'b01011: dst_fbuf <= csr_di[fml_depth-1:1];
5'b01100: dst_hres <= csr_di[10:0];
5'b01101: dst_vres <= csr_di[10:0];
5'b01110: dst_hoffset <= csr_di[11:0];
5'b01111: dst_voffset <= csr_di[11:0];
5'b10000: dst_squarew <= csr_di[10:0];
5'b10001: dst_squareh <= csr_di[10:0];
5'b10010: begin
alpha_en <= csr_di[5:0] != 6'd63;
alpha <= csr_di[5:0];
end
default:;
endcase
end
case(csr_a[4:0])
5'b00000: csr_do <= {chroma_key_en, busy};
5'b00001: csr_do <= vertex_hlast;
5'b00010: csr_do <= vertex_vlast;
5'b00011: csr_do <= brightness;
5'b00100: csr_do <= chroma_key;
5'b00101: csr_do <= {vertex_adr, 3'd0};
5'b00110: csr_do <= {tex_fbuf, 1'd0};
5'b00111: csr_do <= tex_hres;
5'b01000: csr_do <= tex_vres;
5'b01001: csr_do <= tex_hmask;
5'b01010: csr_do <= tex_vmask;
5'b01011: csr_do <= {dst_fbuf, 1'd0};
5'b01100: csr_do <= dst_hres;
5'b01101: csr_do <= dst_vres;
5'b01110: csr_do <= dst_hoffset;
5'b01111: csr_do <= dst_voffset;
5'b10000: csr_do <= dst_squarew;
5'b10001: csr_do <= dst_squareh;
5'b10010: csr_do <= alpha;
5'b10100: csr_do <= c_req_a;
5'b10101: csr_do <= c_hit_a;
5'b10110: csr_do <= c_req_b;
5'b10111: csr_do <= c_hit_b;
5'b11000: csr_do <= c_req_c;
5'b11001: csr_do <= c_hit_c;
5'b11010: csr_do <= c_req_d;
5'b11011: csr_do <= c_hit_d;
default: csr_do <= 32'bx;
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long sum[500001], ans; long long solve(long long a, long long b, long long c, long long hh) { if (a < b + c) return 0ll; long long now = min(a - b - c, hh); return (now + 1) * (now + 2) / 2; } int main() { long long a, b, c, l, i; scanf( %lld%lld%lld%lld , &a, &b, &c, &l); sum[0] = 1; for (i = 1; i <= l; i++) sum[i] = sum[i - 1] + (i + 1) * (i + 2) / 2; ans = sum[l]; for (i = 0; i <= l; i++) ans -= solve(a + i, b, c, l - i) + solve(b + i, a, c, l - i) + solve(c + i, a, b, l - i); printf( %lld , ans); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> #pragma GCC optimization( unroll-loops ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4 ) using namespace std; const int BASE = 1000000; char what[1 << 20]; pair<int, int> nxt[10][1 << 20]; inline long long Calc(long long x) { long long suff = x / BASE, pref = x % BASE; long long ans = suff; while (suff > 0) { ans += nxt[what[suff]][pref].first; pref = nxt[what[suff]][pref].second; pref += BASE - max(what[suff], what[pref]); --suff; } return ans + nxt[0][pref].first; } int main() { for (int i = 1; i <= BASE; ++i) { int val = 0; for (int x = i; x > 0; x /= 10) { val = max(val, x % 10); } what[i] = val; for (int d = 0; d < 10; ++d) { if (i >= max(d, val)) { nxt[d][i] = make_pair(nxt[d][i - max(d, val)].first + 1, nxt[d][i - max(d, val)].second); } else { nxt[d][i] = make_pair(0, i); } } } long long n; cin >> n; cout << Calc(n) << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:09:30
// Design Name:
// Module Name: Display
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display(
input clk_display,
input [31:0] num,
input [7:0] puntos,
output [7:0] segmentos,
output reg [7:0] anodos
);
reg [2:0] counter;
reg [3:0] X;
always @(posedge clk_display) begin
counter <= counter+3'b1;
end
always @(counter) begin
case (counter)
4'd0: anodos= 8'b01111111;
4'd1: anodos= 8'b10111111;
4'd2: anodos= 8'b11011111;
4'd3: anodos= 8'b11101111;
4'd4: anodos= 8'b11110111;
4'd5: anodos= 8'b11111011;
4'd6: anodos= 8'b11111101;
4'd7: anodos= 8'b11111110;
default: anodos=8'b11111111;
endcase
end
always @(*) begin
case(anodos)
8'b01111111: X=num[31:28];
8'b10111111: X=num[27:24];
8'b11011111: X=num[23:20];
8'b11101111: X=num[19:16];
8'b11110111: X=num[15:12];
8'b11111011: X=num[11:8];
8'b11111101: X=num[7:4];
8'b11111110: X=num[3:0];
default: X=4'b0 ;
endcase
end
Dec_4b_seg Dec(
. NUM(X),
. CATODOS({segmentos})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[60]; int abs(int x) { return x > 0 ? x : -x; } int f(int x) { int sum = 0; for (int i = 0; i < n / 2; ++i) sum += abs(i * 2 + x - a[i]); return sum; } int main() { scanf( %d , &n); for (int i = 0; i < n / 2; ++i) scanf( %d , a + i); sort(a, a + n / 2); printf( %d , min(f(1), f(2))); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_SYMBOL_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s4s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_SYMBOL_V
|
/* b2d.v - A decoder from 4-bit input to 7seg Displays
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module b2d(SW,HEX0,HEX1,HEX2,HEX3);
// Input Port(s)
input [17:0] SW;
// Output Port(s)
output [0:6] HEX0,HEX1,HEX2,HEX3;
b2d_7seg B0 (SW[3:0], HEX0);
b2d_7seg B1 (SW[7:4], HEX1);
b2d_7seg B2 (SW[11:8], HEX2);
b2d_7seg B3 (SW[15:12], HEX3);
endmodule
/*
***************************************************************
Truth Table "A 4-to-7 Decoder"
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
|SW15|SW14|SW13|SW12|HEX0|HEX1 |HEX2|HEX3|HEX4|HEX5|HEX6 | BCD |
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 2 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 3 |
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 4 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 5 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 6 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 7 |
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 9 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
HEX3 [0:6]
+----------0---------+
||+----------------+|| HEX3[0] = (~SW[15] & ~SW[14] & ~SW[13] & SW[12])
|||| ||||
|||| ||||
|||| ||||
|||| ||||
||5| ||1|
|||| ||||
|||| ||||
|||| ||||
|||| ||||
|||+------6-------++||
|||+--------------++||
|||| ||||
|||| ||||
|||| ||||
|4|| ||2|
|||| ||||
|||| ||||
|||| ||||
|||| ||||
||+--------3-------+||
+--------------------+
*****************************************************************
*/
module b2d_7seg (X,SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & X[0]));
assign SSD[2] = ((~X[3] & ~X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & X[0]));
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[4] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & ~X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; void qread(int &x) { int neg = 1; x = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) neg = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = 10 * x + c - 0 , c = getchar(); x *= neg; } const int maxn = 405; int test, n, mod; int dp[maxn][maxn * 2], fac[maxn]; int quickpow(int x, int pow) { int res = 1; for (; pow; pow >>= 1) { if (pow & 1) res = 1LL * res * x % mod; x = 1LL * x * x % mod; } return res; } void work() { for (int(i) = 1; (i) <= 400; i++) dp[i][i + 400] = 1; for (int(i) = 1; (i) <= 400; i++) { int inv = quickpow(dp[i][i], mod - 2); for (int j = i + 1; j <= 2 * 400; j++) dp[i][j] = 1LL * dp[i][j] * inv % mod; dp[i][i] = 1; for (int j = i + 1; j <= 400; j++) { for (int k = i + 1; k <= 2 * 400; k++) dp[j][k] = (dp[j][k] - 1LL * dp[j][i] * dp[i][k] % mod + mod) % mod; dp[j][i] = 0; } } } int main() { scanf( %d%d , &test, &mod); fac[0] = 1; for (int(i) = 1; (i) <= 400; i++) fac[i] = 1LL * fac[i - 1] * i % mod; for (int(i) = 1; (i) <= 400; i++) { dp[i][1] = fac[i]; for (int k = 2; k <= i; k++) { for (int m = 0; m <= i - k; m++) dp[i][k] = (dp[i][k] + 1LL * fac[m + 1] * dp[i - m - 1][k - 1] % mod) % mod; } } work(); while (test--) { scanf( %d , &n); if (n == 2) { puts( 2 ); continue; } int ans = ((mod - dp[n][401]) % mod + ((n & 1) ? 2 : -2) + mod) % mod; printf( %d n , ans); } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_V
|
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