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#include <bits/stdc++.h> using namespace std; int main() { int test, i, k, j, sum1, sum, n, p; cin >> test; for (i = 0; i < test; i++) { cin >> n >> k; sum = 0; sum1 = 0; vector<int> v1, v2; for (j = 0; j < n; j++) { cin >> p; v1.push_back(p); } for (j = 0; j < n; j++) { cin >> p; v2.push_back(p); } sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); for (j = 0; j < k; j++) { if (v2[n - j - 1] > v1[j]) sum1 = sum1 + v2[n - j - 1]; else sum1 = sum1 + v1[j]; } for (j = k; j < n; j++) sum = sum + v1[j]; cout << sum + sum1 << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_V
|
module check (input unsigned [22:0] a, b, c);
wire unsigned [22:0] int_AB;
assign int_AB = a / b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 1;
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
end
#1 A = 0;
B = 1;
#1 A = 23'h7fffff;
#1 B = 23'h7fffff;
#1 B = 1;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = {$random} % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = {$random} % MAX;
if (B === 23'b0) B = 1;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = {$random} % MAX;
B = {$random} % MAX;
if (B === 23'b0) B = 1;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input unsigned [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [22:0] a, b;
wire unsigned [22:0] r;
stimulus stim (.A(a), .B(b));
udiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns/10ps
module PLL108_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("108.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/*
-- ============================================================================
-- FILE NAME : if_reg.v
-- DESCRIPTION : IF¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module if_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Õ¥§¥Ã¥Á¥Ç©`¥¿ **********/
input wire [`WordDataBus] insn, // ¥Õ¥§¥Ã¥Á¤·¤¿ÃüÁî
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
input wire [`WordAddrBus] new_pc, // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire br_taken, // ·Ö᪤γÉÁ¢
input wire [`WordAddrBus] br_addr, // ·ÖáªÏÈ¥¢¥É¥ì¥¹
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output reg [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output reg [`WordDataBus] if_insn, // ÃüÁî
output reg if_en // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
if_pc <= #1 `RESET_VECTOR;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else begin
/* ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿¤Î¸üР*/
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // ¥Õ¥é¥Ã¥·¥å
if_pc <= #1 new_pc;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else if (br_taken == `ENABLE) begin // ·Ö᪤γÉÁ¢
if_pc <= #1 br_addr;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end else begin // ´Î¤Î¥¢¥É¥ì¥¹
if_pc <= #1 if_pc + 1'd1;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
`include "def.v"
module OSECPU(clk, reset, dr, cr, pc);
input clk;
input reset;
output reg [31:0] dr = 0;
output [15:0] pc;
output [7:0] cr;
//
wire [31:0] alu_d0, alu_d1, alu_dout;
wire [3:0] alu_op;
wire alu_iscmp;
//
wire [5:0] ireg_rw, ireg_r0, ireg_r1;
wire [31:0] ireg_d0, ireg_d1, ireg_dw;
wire ireg_we;
//
wire [5:0] preg_p0, preg_p1, preg_pw;
wire [11:0] preg_lbid0, preg_lbid1, preg_lbidw;
wire [15:0] preg_ofs0, preg_ofs1, preg_ofsw;
wire preg_we, preg_pc_update_req;
//
wire [ 5:0] mmu_reqType;
wire [15:0] mmu_ofs;
wire [11:0] mmu_lbid;
wire [15:0] mmu_addr;
wire mmu_invalid;
//
wire [11:0] lbt_lbidw;
wire [ 5:0] lbt_typw;
wire [15:0] lbt_basew;
wire [15:0] lbt_countw;
wire lbt_we;
//
wire [15:0] mem_addr;
wire [31:0] mem_data;
wire [31:0] mem_wdata;
reg mem_we;
//
wire [31:0] instr0;
wire [31:0] instr1;
wire [3:0] current_state;
wire [15:0] pc;
//
Controller ctrl(clk, reset,
mem_data, mem_addr, ireg_d0[0],
instr0, instr1, current_state,
cr, pc,
preg_pc_update_req, mmu_addr);
ALUController alu(alu_d0, alu_d1, alu_dout, alu_op, alu_iscmp);
IntegerRegister ireg(clk,
ireg_r0, ireg_r1, ireg_rw,
ireg_d0, ireg_d1, ireg_dw,
ireg_we);
PointerRegister preg(clk,
preg_p0, preg_p1, preg_pw,
preg_lbid0, preg_lbid1, preg_lbidw,
preg_ofs0, preg_ofs1, preg_ofsw,
preg_we, preg_pc_update_req);
MMU mmu(clk,
mmu_reqType, mmu_ofs, mmu_lbid, mmu_addr, mmu_invalid,
lbt_lbidw, lbt_typw, lbt_basew, lbt_countw, lbt_we);
BlockRAM mem(clk, mem_addr, mem_wdata, mem_we, mem_data);
defparam mem.DataWidth = 32;
defparam mem.AddrWidth = 8;
defparam mem.InitFileName = "rom.hex";
DataPath datapath(
instr0, instr1, current_state,
alu_d0, alu_d1, alu_dout, alu_op, alu_iscmp,
ireg_r0, ireg_r1, ireg_rw, ireg_we,
ireg_d0, ireg_d1, ireg_dw,
lbt_lbidw, lbt_typw, lbt_basew, lbt_countw, lbt_we,
preg_p0, preg_p1, preg_pw,
preg_lbid0, preg_lbid1, preg_lbidw,
preg_ofs0, preg_ofs1, preg_ofsw,
preg_we,
mmu_reqType, mmu_ofs, mmu_lbid, mmu_addr, mmu_invalid);
wire [7:0] instr0_op;
assign instr0_op = instr0[31:24];
//
always @(posedge clk) begin
if(instr0_op == 8'hD3) begin
// CPDR
case (current_state)
`STATE_STORE_0: begin
dr = ireg_d0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, ans; string str; long long solve() { cin >> n >> str; long long x = -1, y = -1; long long i = 0; while (i < n) { if (str[i] == 1 ) { x = i; break; } i++; } i = n - 1; while (i >= 0) { if (str[i] == 1 ) { y = i; break; } i--; } ans = n; if (x != -1) { ans = max(ans, 2 * (x + 1)); ans = max(ans, 2 * (n - x)); } if (y != -1) { ans = max(ans, 2 * (y + 1)); ans = max(ans, 2 * (n - y)); } cout << ans << n ; return 0; } signed main() { ios::sync_with_stdio(0); long long t = 1; cin >> t; while (t--) solve(); return 0; }
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "pack.v"
module BrainfuckCPU(
CLK, RESET,
IA, IDIN, IEN,
DA, DDIN, DDOUT, DEN, DWE,
CIN, COUT, CRDA, CACK, CWR, CRDY
);
parameter FAST_LOOPEND = 1;
parameter IA_WIDTH = 11;
parameter DA_WIDTH = 11;
parameter DD_WIDTH = 8;
parameter STACK_DEPTH_POW = 7;
input CLK;
input RESET;
// Instruction bus
output reg [IA_WIDTH - 1:0] IA;
input [7:0] IDIN;
output reg IEN;
// Data bus
output [DA_WIDTH - 1:0] DA;
input [DD_WIDTH - 1:0] DDIN;
output [DD_WIDTH - 1:0] DDOUT;
output reg DEN;
output reg DWE;
// Console interface
input [7:0] CIN;
output reg [7:0] COUT;
input CRDA;
output reg CACK;
output reg CWR;
input CRDY;
reg [3:0] STATE;
wire [IA_WIDTH - 1:0] PC;
reg [DA_WIDTH - 1:0] DC;
wire [IA_WIDTH - 1:0] STACK_PC, LOOP_PC;
wire [8:0] DECODED;
wire ZERO;
reg STACK_PUSH, STACK_POP, LOOPSEEK;
reg [STACK_DEPTH_POW - 1:0] LOOP_DEPTH;
wire CONLOAD, PCLOAD;
InstructionDecoder decoder(
.OPCODE(IDIN),
.DECODED(DECODED)
);
GenericCounter #(
.WIDTH(DD_WIDTH)
) dcnt (
.CLK(CLK),
.RESET(RESET),
.D(CONLOAD ? CIN : DDIN),
.Q(DDOUT),
.EN((STATE == `STATE_DFETCH2) || (STATE == `STATE_DUPDATE) || CONLOAD),
.LOAD(STATE == `STATE_DFETCH2 || CONLOAD),
.DOWN(DECODED[`OP_DEC])
);
GenericCounter #(
.WIDTH(IA_WIDTH)
) pcnt (
.CLK(CLK),
.RESET(RESET),
.D(LOOP_PC),
.Q(PC),
.EN((STATE == `STATE_IFETCH) || PCLOAD),
.LOAD(PCLOAD),
.DOWN(1'b0)
);
Stack #(
.WIDTH(IA_WIDTH),
.DEPTH_POW(STACK_DEPTH_POW)
) stack (
.CLK(CLK),
.RESET(RESET),
.PUSH(STACK_PUSH),
.POP(STACK_POP),
.D(PC),
.Q(STACK_PC)
);
always @ (posedge CLK)
if(RESET)
begin
STATE <= `STATE_IFETCH;
IA <= 0;
DC <= 0;
IEN <= 1'b0;
DEN <= 1'b0;
DWE <= 1'b0;
STACK_PUSH <= 1'b0;
STACK_POP <= 1'b0;
LOOPSEEK <= 1'b0;
LOOP_DEPTH <= 0;
COUT <= 8'b0;
CWR <= 1'b0;
CACK <= 1'b0;
end
else
case(STATE)
`STATE_IFETCH:
begin
DEN <= 1'b0;
DWE <= 1'b0;
STACK_PUSH <= 1'b0;
CWR <= 1'b0;
IA <= PC;
IEN <= 1'b1;
STATE <= `STATE_IFETCH2;
end
`STATE_IFETCH2:
begin
IEN <= 1'b0;
if(LOOPSEEK)
STATE <= `STATE_LOOPSEEK;
else
STATE <= `STATE_DECODE;
end
`STATE_DECODE:
begin
if(DECODED[`OP_ILLEGAL])
STATE <= `STATE_IFETCH;
else if(DECODED[`OP_INC] || DECODED[`OP_DEC] || DECODED[`OP_LOOPBEGIN] ||
(DECODED[`OP_LOOPEND] && FAST_LOOPEND) || DECODED[`OP_COUT])
begin
DEN <= 1'b1;
STATE <= `STATE_DFETCH;
end
else if(!FAST_LOOPEND && DECODED[`OP_LOOPEND])
STATE <= `STATE_LOOPEND;
else if(DECODED[`OP_INCPTR])
begin
DC <= DC + 1;
STATE <= `STATE_IFETCH;
end
else if(DECODED[`OP_DECPTR])
begin
DC <= DC - 1;
STATE <= `STATE_IFETCH;
end
else if(DECODED[`OP_CIN])
STATE <= `STATE_CIN;
else
STATE <= `STATE_DECODE;
end
`STATE_DFETCH:
begin
DEN <= 1'b0;
STATE <= `STATE_DFETCH2;
end
`STATE_DFETCH2:
begin
if(DECODED[`OP_LOOPBEGIN])
STATE <= `STATE_LOOPBEGIN;
else if(DECODED[`OP_LOOPEND])
STATE <= `STATE_LOOPEND;
else if(DECODED[`OP_COUT])
STATE <= `STATE_COUT;
else
STATE <= `STATE_DUPDATE;
end
`STATE_DUPDATE:
begin
STATE <= `STATE_WRITEBACK;
end
`STATE_WRITEBACK:
begin
CACK <= 1'b0;
DEN <= 1'b1;
DWE <= 1'b1;
STATE <= `STATE_IFETCH;
end
`STATE_LOOPBEGIN:
begin
if(ZERO)
begin
LOOPSEEK <= 1'b1;
LOOP_DEPTH <= 1;
end
else
STACK_PUSH <= 1'b1;
STATE <= `STATE_IFETCH;
end
`STATE_LOOPEND:
begin
STACK_POP <= 1'b1;
STATE <= `STATE_LOOPEND2;
end
`STATE_LOOPEND2:
begin
STACK_POP <= 1'b0;
STATE <= `STATE_LOOPEND3;
end
`STATE_LOOPEND3:
begin
STATE <= `STATE_IFETCH;
end
`STATE_LOOPSEEK:
begin
if(DECODED[`OP_LOOPBEGIN])
LOOP_DEPTH <= LOOP_DEPTH + 1;
else if(DECODED[`OP_LOOPEND])
begin
if(LOOP_DEPTH == 1)
LOOPSEEK <= 1'b0;
LOOP_DEPTH <= LOOP_DEPTH - 1;
end
STATE <= `STATE_IFETCH;
end
`STATE_COUT:
begin
if(CRDY)
begin
COUT <= DDOUT;
CWR <= 1'b1;
STATE <= `STATE_IFETCH;
end
else
STATE <= `STATE_COUT;
end
`STATE_CIN:
if(CRDA)
begin
CACK <= 1'b1;
STATE <= `STATE_WRITEBACK;
end
else
STATE <= `STATE_CIN;
endcase
assign DA = DC;
assign CONLOAD = (STATE == `STATE_CIN) && CRDA;
assign PCLOAD = (!ZERO || !FAST_LOOPEND) && STATE == `STATE_LOOPEND3;
assign LOOP_PC = STACK_PC - 1;
assign ZERO = DDOUT == 0;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// ERROR_DETECT_GTP
//
//
// Description : The ERROR_DETECT module monitors the GTP to detect hard
// errors. It accumulates the Soft errors according to the
// leaky bucket algorithm described in the Aurora
// Specification to detect Hard errors. All errors are
// reported to the Global Logic Interface.
//
// * Supports GTP
//
`timescale 1 ns / 1 ps
module aur1_ERROR_DETECT
(
// Lane Init SM Interface
ENABLE_ERROR_DETECT,
HARD_ERROR_RESET,
// Global Logic Interface
SOFT_ERROR,
HARD_ERROR,
// GTP Interface
RX_BUF_ERR,
RX_DISP_ERR,
RX_NOT_IN_TABLE,
TX_BUF_ERR,
RX_REALIGN,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// Lane Init SM Interface
input ENABLE_ERROR_DETECT;
output HARD_ERROR_RESET;
// Global Logic Interface
output SOFT_ERROR;
output HARD_ERROR;
// GTP Interface
input RX_BUF_ERR;
input [1:0] RX_DISP_ERR;
input [1:0] RX_NOT_IN_TABLE;
input TX_BUF_ERR;
input RX_REALIGN;
// System Interface
input USER_CLK;
//**************************External Register Declarations****************************
reg HARD_ERROR;
reg SOFT_ERROR;
//**************************Internal Register Declarations****************************
reg [0:1] count_r;
reg bucket_full_r;
reg [0:1] soft_error_r;
reg [0:1] good_count_r;
reg soft_error_flop_r; // Traveling flop for timing.
reg hard_error_flop_r; // Traveling flop for timing.
//*********************************Main Body of Code**********************************
//____________________________ Error Processing _________________________________
// Detect Soft Errors
always @(posedge USER_CLK)
if(ENABLE_ERROR_DETECT)
begin
soft_error_r[0] <= `DLY RX_DISP_ERR[1]|RX_NOT_IN_TABLE[1];
soft_error_r[1] <= `DLY RX_DISP_ERR[0]|RX_NOT_IN_TABLE[0];
end
else
begin
soft_error_r[0] <= `DLY 1'b0;
soft_error_r[1] <= `DLY 1'b0;
end
always @(posedge USER_CLK)
begin
soft_error_flop_r <= `DLY |soft_error_r;
SOFT_ERROR <= `DLY soft_error_flop_r;
end
// Detect Hard Errors
always @(posedge USER_CLK)
if(ENABLE_ERROR_DETECT)
begin
hard_error_flop_r <= `DLY (RX_BUF_ERR | TX_BUF_ERR |
RX_REALIGN | bucket_full_r);
HARD_ERROR <= `DLY hard_error_flop_r;
end
else
begin
hard_error_flop_r <= `DLY 1'b0;
HARD_ERROR <= `DLY 1'b0;
end
// Assert hard error reset when there is a hard error. This assignment
// just renames the two fanout branches of the hard error signal.
assign HARD_ERROR_RESET = hard_error_flop_r;
//_______________________________Leaky Bucket__________________________________
// Good cycle counter: it takes 2 consecutive good cycles to remove a demerit from
// the leaky bucket
always @(posedge USER_CLK)
if(!ENABLE_ERROR_DETECT) good_count_r <= `DLY 2'b00;
else
begin
casez({soft_error_r, good_count_r})
4'b0000 : good_count_r <= `DLY 2'b10;
4'b0001 : good_count_r <= `DLY 2'b11;
4'b0010 : good_count_r <= `DLY 2'b00;
4'b0011 : good_count_r <= `DLY 2'b01;
4'b?1?? : good_count_r <= `DLY 2'b00;
4'b10?? : good_count_r <= `DLY 2'b01;
default : good_count_r <= `DLY good_count_r;
endcase
end
// Perform the leaky bucket algorithm using an up/down counter. A drop is
// added to the bucket whenever a soft error occurs and is allowed to leak
// out whenever the good cycles counter reaches 2. Once the bucket fills
// (3 drops) it stays full until it is reset by disabling and then enabling
// the error detection circuit.
always @(posedge USER_CLK)
if(!ENABLE_ERROR_DETECT) count_r <= `DLY 2'b00;
else
begin
casez({soft_error_r,good_count_r,count_r})
6'b000??? : count_r <= `DLY count_r;
6'b001?00 : count_r <= `DLY 2'b00;
6'b001?01 : count_r <= `DLY 2'b00;
6'b001?10 : count_r <= `DLY 2'b01;
6'b001?11 : count_r <= `DLY 2'b10;
6'b010000 : count_r <= `DLY 2'b01;
6'b010100 : count_r <= `DLY 2'b01;
6'b011000 : count_r <= `DLY 2'b01;
6'b011100 : count_r <= `DLY 2'b00;
6'b010001 : count_r <= `DLY 2'b10;
6'b010101 : count_r <= `DLY 2'b10;
6'b011001 : count_r <= `DLY 2'b10;
6'b011101 : count_r <= `DLY 2'b01;
6'b010010 : count_r <= `DLY 2'b11;
6'b010110 : count_r <= `DLY 2'b11;
6'b011010 : count_r <= `DLY 2'b11;
6'b011110 : count_r <= `DLY 2'b10;
6'b01??11 : count_r <= `DLY 2'b11;
6'b10??00 : count_r <= `DLY 2'b01;
6'b10??01 : count_r <= `DLY 2'b10;
6'b10??10 : count_r <= `DLY 2'b11;
6'b10??11 : count_r <= `DLY 2'b11;
6'b11??00 : count_r <= `DLY 2'b10;
6'b11??01 : count_r <= `DLY 2'b11;
6'b11??10 : count_r <= `DLY 2'b11;
6'b11??11 : count_r <= `DLY 2'b11;
endcase
end
always @(posedge USER_CLK)
if(!ENABLE_ERROR_DETECT) bucket_full_r <= `DLY 1'b0;
else
begin
casez({soft_error_r, good_count_r, count_r})
6'b010011 : bucket_full_r <= `DLY 1'b1;
6'b010111 : bucket_full_r <= `DLY 1'b1;
6'b011011 : bucket_full_r <= `DLY 1'b1;
6'b10??11 : bucket_full_r <= `DLY 1'b1;
6'b11??1? : bucket_full_r <= `DLY 1'b1;
default : bucket_full_r <= `DLY 1'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; int n, k, a[N]; long long seg[4 * N + 4], dp[N + 1][12]; void update(int p, int l, int r, int indx, long long val) { if (l == r) { seg[p] = val; return; } int mid = l + (r - l) / 2; if (indx <= mid) update(p * 2, l, mid, indx, val); else update(p * 2 + 1, mid + 1, r, indx, val); seg[p] = seg[p * 2] + seg[p * 2 + 1]; } long long get(int p, int l, int r, int a, int b) { if (l >= a && r <= b) { return seg[p]; } if (l > b || r < a) { return 0; } int mid = l + (r - l) / 2; return get(p * 2, l, mid, a, b) + get(p * 2 + 1, mid + 1, r, a, b); } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) scanf( %d , a + i); for (int i = 0; i <= N; ++i) dp[i][1] = 1; for (int j = 2; j <= k + 1; ++j) { memset(seg, 0, sizeof seg); for (int i = 0; i < n; ++i) { dp[i][j] = get(1, 0, n - 1, 1, a[i] - 1); update(1, 0, n - 1, a[i], dp[i][j - 1]); } } long long ans = 0; for (int i = 0; i < n; ++i) { ans += dp[i][k + 1]; } printf( %lld n , ans); }
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#include <bits/stdc++.h> using namespace std; int n, k; int id[105]; int A[105]; int B[105]; long long dp[77][77]; bool check(int left, int right, int pos1, int pos2) { for (int i = 0; i < k; i++) { if (A[i] == pos1) { if (B[i] == pos2 && id[i] == 1) return false; if (B[i] <= left || B[i] >= right) { return false; } } else if (A[i] == pos2) { if (B[i] == pos1 && id[i] == 1) return false; if (B[i] <= left || B[i] >= right) { return false; } } else if (B[i] == pos1) { if (A[i] == pos2 && id[i] == 1) return false; if (A[i] <= left || A[i] >= right) { if (id[i] == 0) return false; } } else if (B[i] == pos2) { if (A[i] == pos1 && id[i] == 1) return false; if (A[i] <= left || A[i] >= right) { if (id[i] == 0) return false; } } } return true; } int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 0; i < k; i++) { string s; cin >> A[i] >> s >> B[i]; if (s == < ) { id[i] = 1; } else if (s == > ) { id[i] = 1; swap(A[i], B[i]); } else if (s == = ) { id[i] = 0; } else if (s == <= ) { id[i] = 2; } else { id[i] = 2; swap(A[i], B[i]); } } dp[0][2 * n + 1] = 1; for (int i = 0; i <= 2 * n - 2; i++) { for (int j = 2 * n + 1; j >= i + 3; j--) { long long x = dp[i][j]; if (x == 0) continue; if (j - i > 3 && check(i, j, i + 1, i + 2)) dp[i + 2][j] += x; if (check(i, j, i + 1, j - 1)) dp[i + 1][j - 1] += x; if (j - i > 3 && check(i, j, j - 2, j - 1)) dp[i][j - 2] += x; } } long long answer = 0; for (int i = 1; i < 2 * n; i++) { answer += dp[i][i + 1]; } cout << answer << endl; }
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#include <bits/stdc++.h> long long INF = (long long)1e18; struct node { int n; double rat; }; bool operator<(const node& n1, const node& n2) { return n1.rat > n2.rat; } std::vector<int> edge[100010]; int ch[100010], ne[100010]; int main() { int x, a, b, k, n, m, q, t, num, in = 0, to, i; double d, s; scanf( %d%d%d , &n, &m, &q); for (k = 1; k <= q; k++) { scanf( %d , &x); ch[x] = -1; } for (k = 1; k <= m; k++) { scanf( %d%d , &a, &b); edge[a].push_back(b); edge[b].push_back(a); } double max = -1; std::priority_queue<node> PQ; for (k = 1; k <= n; k++) { if (ch[k] == -1) continue; t = 0; for (i = 0; i < edge[k].size(); i++) { int j = edge[k][i]; if (ch[j] == 0) t++; } ne[k] = t; PQ.push(node{k, (double)t / (double)edge[k].size()}); } num = n - q; in = 1; while (num != 0) { a = PQ.top().n; d = PQ.top().rat; PQ.pop(); if (ch[a] != 0) continue; ch[a] = in++; if (d > max) { max = d; to = in; } num--; for (i = 0; i < edge[a].size(); i++) { int j = edge[a][i]; if (ch[j] != 0) continue; ne[j]--; s = (double)ne[j] / (double)edge[j].size(); PQ.push(node{j, s}); } } int ans = 0; for (k = 1; k <= n; k++) { if (ch[k] >= to - 1) ans++; } printf( %d n , ans); for (k = 1; k <= n; k++) { if (ch[k] >= to - 1) printf( %d , k); } }
|
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition"
// CREATED "Sun Oct 25 12:01:05 2015"
module vga(
CLOCK_50,
KEY,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HSYNC,
VGA_VSYNC
);
input wire CLOCK_50;
input wire [0:0] KEY;
output wire VGA_RED;
output wire VGA_GREEN;
output wire VGA_BLUE;
output wire VGA_HSYNC;
output wire VGA_VSYNC;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire [15:0] SYNTHESIZED_WIRE_4;
wire [10:0] SYNTHESIZED_WIRE_5;
wire [10:0] SYNTHESIZED_WIRE_6;
wire [15:0] SYNTHESIZED_WIRE_7;
vga_bw b2v_inst(
.CLOCK_PIXEL(SYNTHESIZED_WIRE_0),
.RESET(SYNTHESIZED_WIRE_9),
.PIXEL(SYNTHESIZED_WIRE_2),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE),
.VGA_HS(VGA_HSYNC),
.VGA_VS(VGA_VSYNC),
.PIXEL_H(SYNTHESIZED_WIRE_5),
.PIXEL_V(SYNTHESIZED_WIRE_6));
frame_buffer b2v_inst1(
.clk(CLOCK_50),
.load(SYNTHESIZED_WIRE_3),
.data_in(SYNTHESIZED_WIRE_4),
.vga_h(SYNTHESIZED_WIRE_5),
.vga_v(SYNTHESIZED_WIRE_6),
.write_address(SYNTHESIZED_WIRE_7),
.pixel_out(SYNTHESIZED_WIRE_2));
image_generator b2v_inst5(
.clk(CLOCK_50),
.reset(SYNTHESIZED_WIRE_9),
.load(SYNTHESIZED_WIRE_3),
.address(SYNTHESIZED_WIRE_7),
.out(SYNTHESIZED_WIRE_4));
clock_25 b2v_pixel_clock_25(
.CLOCK_50(CLOCK_50),
.CLOCK_25(SYNTHESIZED_WIRE_0));
assign SYNTHESIZED_WIRE_9 = ~KEY;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; vector<int> v[maxn]; int ma = 0; int h = 0; int f = 0; int root = 0; int g[maxn]; bool mark[maxn]; void dfs(int k) { if (mark[k] == false) { mark[k] = true; } else { return; } for (int i = 0; i < v[k].size(); i++) { int child = v[k][i]; if (mark[child] == false) { g[h]++; dfs(child); } } if (v[k].size() == 1 && root != k) { if (g[h] + 1 > ma) { ma = g[h] + 1; } f = 1; } if (f == 1) { g[h]--; } } int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { int u; cin >> u; if (u == -1) { mark[i] = true; } else { v[i].push_back(u); v[u].push_back(i); } } for (int i = 1; i <= n; i++) { if (mark[i] == true) { mark[i] = false; root = i; dfs(i); h++; } } if (ma == 0) { cout << 1; return 0; } cout << ma; }
|
#include <bits/stdc++.h> using namespace std; int main() { int len; string s; cin >> len; cin >> s; vector<char> vect; while (len != 0) { if (len % 2 == 1) { vect.push_back(s[0]); } else { vect.insert(vect.begin(), s[0]); } s.erase(0, 1); len = s.length(); } for (int i = 0; i < vect.size(); i++) { cout << vect[i]; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_TB_V
`define SKY130_FD_SC_MS__A32OI_TB_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_TB_V
|
module dv_elink_tb();
parameter AW=32;
parameter DW=32;
parameter CW=2; //number of clocks to send int
parameter MW=104;
parameter MAW=10;
parameter MD=1<<MAW;//limit test to 1K transactions
//TODO:generealize
/* verilator lint_off STMTDLY */
/* verilator lint_off UNOPTFLAT */
//REGS
reg [1:0] clk;
reg reset;
reg go;
reg [1:0] datamode;
reg ext_access;
reg ext_write;
reg [1:0] ext_datamode;
reg [3:0] ext_ctrlmode;
reg [31:0] ext_dstaddr;
reg [31:0] ext_data;
reg [31:0] ext_srcaddr;
reg ext_wr_wait;
reg ext_rd_wait;
reg init;
reg [MW-1:0] stimarray[MD-1:0];
reg [MW-1:0] transaction;
reg [MAW-1:0] stim_addr;
integer i;
`ifdef MANUAL
//TODO: make test name a parameter, fancify,...
initial
begin
for(i=0;i<MD;i++)
stimarray[i]='d0;
//$readmemh(`TESTNAME,stimarray,0,`TRANS-1);//How to?
$readmemh("test.memh",stimarray,0,`TRANS-1);
end
`endif
//Forever clock
always
#1 clk[0] = ~clk[0];//clock for elink
always
#10 clk[1] = ~clk[1];//clock for axi interface
//should make variable to really test all fifos
wire clkstim = clk[1];
//Reset
initial
begin
#0
reset = 1'b1; // reset is active
go = 1'b0;
clk[1:0] = 2'b0;
datamode = 2'b10;
#400
`ifdef AUTO
//clock config (fast /2)
dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0113;
//tx config (enable)
dv_elink.elink.ecfg.ecfg_tx_reg[8:0] = 9'h001;
//rx config (enable)
dv_elink.elink.ecfg.ecfg_rx_reg[4:0] = 5'h01;
`endif
reset = 1'b0; // at time 100 release reset
#1000
go = 1'b1;
#2000
`ifdef AUTO
go = 1'b0;
`endif
#10000
$finish;
end
//Notes:The testbench connects a 64 bit master to a 32 bit slave
//To make this work, we limit the addresses to 64 bit aligned
always @ (posedge clkstim)
if(reset | ~go)
begin
ext_access <= 1'b0; //empty
ext_write <= 1'b0;
ext_datamode[1:0] <= 2'b0;
ext_ctrlmode[3:0] <= 4'b0;
ext_data[31:0] <= 32'b0;
ext_dstaddr[31:0] <= 32'b0;
ext_srcaddr[31:0] <= 32'b0;
ext_rd_wait <= 1'b0;
ext_wr_wait <= 1'b0;
stim_addr[MAW-1:0] <= 'd0;
transaction[MW-1:0] <= 'd0;
end
else if (go & ~(dut_wr_wait|dut_rd_wait))
//else if ((go & ~ext_access) | (go & ext_access & ~dut_wr_wait))
begin
`ifdef MANUAL
transaction[MW-1:0] <= stimarray[stim_addr];
ext_access <= transaction[0];
ext_write <= transaction[1];
ext_datamode[1:0] <= transaction[3:2];
ext_ctrlmode[3:0] <= transaction[7:4];
ext_dstaddr[31:0] <= transaction[39:8];
ext_data[31:0] <= transaction[71:40];
ext_srcaddr[31:0] <= transaction[103:72];
stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1;
`else
ext_access <= 1'b1;
ext_data[31:0] <= ext_data[31:0] + 32'b1;
ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
ext_datamode[1:0] <= datamode[1:0];
`endif
end
//Waveform dump
`ifndef TARGET_VERILATOR
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, dv_elink_tb);
end
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dut_access; // From dv_elink of dv_elink.v
wire [3:0] dut_ctrlmode; // From dv_elink of dv_elink.v
wire [31:0] dut_data; // From dv_elink of dv_elink.v
wire [1:0] dut_datamode; // From dv_elink of dv_elink.v
wire [31:0] dut_dstaddr; // From dv_elink of dv_elink.v
wire dut_failed; // From dv_elink of dv_elink.v
wire dut_passed; // From dv_elink of dv_elink.v
wire dut_rd_wait; // From dv_elink of dv_elink.v
wire [31:0] dut_srcaddr; // From dv_elink of dv_elink.v
wire dut_wr_wait; // From dv_elink of dv_elink.v
wire dut_write; // From dv_elink of dv_elink.v
// End of automatics
//dut
dv_elink dv_elink(/*AUTOINST*/
// Outputs
.dut_passed (dut_passed),
.dut_failed (dut_failed),
.dut_rd_wait (dut_rd_wait),
.dut_wr_wait (dut_wr_wait),
.dut_access (dut_access),
.dut_write (dut_write),
.dut_datamode (dut_datamode[1:0]),
.dut_ctrlmode (dut_ctrlmode[3:0]),
.dut_dstaddr (dut_dstaddr[31:0]),
.dut_srcaddr (dut_srcaddr[31:0]),
.dut_data (dut_data[31:0]),
// Inputs
.clk (clk[CW-1:0]),
.reset (reset),
.ext_access (ext_access),
.ext_write (ext_write),
.ext_datamode (ext_datamode[1:0]),
.ext_ctrlmode (ext_ctrlmode[3:0]),
.ext_dstaddr (ext_dstaddr[31:0]),
.ext_data (ext_data[31:0]),
.ext_srcaddr (ext_srcaddr[31:0]),
.ext_rd_wait (ext_rd_wait),
.ext_wr_wait (ext_wr_wait));
endmodule // dv_elink_tb
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000005; int n; char s1[maxn], s2[maxn]; int main() { scanf( %d%s%s , &n, s1 + 1, s2 + 1); reverse(s1 + 1, s1 + n); for (int i = 1; i < n; ++i) { if (s1[i] == N ) s1[i] = S ; else if (s1[i] == S ) s1[i] = N ; else if (s1[i] == W ) s1[i] = E ; else s1[i] = W ; } unsigned long long h1 = 0, h2 = 0, fa = 1; for (int i = 1; i < n; ++i) { h1 = h1 + s1[i] * fa; h2 = h2 * 233u + s2[n - i]; fa *= 233u; if (h1 == h2) return puts( NO ), 0; } puts( YES ); return 0; }
|
#include <bits/stdc++.h> int a[100 + 10]; int main() { int n, m, min_, max_; scanf( %d %d %d %d , &n, &m, &min_, &max_); int i, j, t = 0; for (i = 0; i < m; i++) { scanf( %d , &a[i]); } for (i = 0; i < m; i++) { for (j = i + 1; j < m; j++) { if (a[j] < a[i]) { t = a[i]; a[i] = a[j]; a[j] = t; } } } if (a[0] < min_ || a[m - 1] > max_) printf( Incorrect n ); else if (a[0] == min_ && a[m - 1] == max_) printf( Correct n ); else if (a[0] != min_ && a[m - 1] != max_) { if (n - m >= 2) printf( Correct n ); else printf( Incorrect n ); } else { if (n - m >= 1) printf( Correct n ); else printf( Incorrect n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int in() { int x, y; y = scanf( %d , &x); return x; } const int N = -1; int main() { int X = in(), d = in(); vector<long long> v; v.push_back(0); int b = 0; while (X) { if (X % 2) { v.push_back(v.back() + d); long long back = v.back(); for (int j = 0; j < b; j++) v.push_back(back + d); } X /= 2; b++; } cout << (int)v.size() - 1 << endl; for (int i = 1; i < v.size(); i++) cout << v[i] << ; cout << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic use_AnB;
logic [1:0] active_command [8:0];
logic [1:0] command_A [8:0];
logic [1:0] command_B [8:0];
logic [1:0] active_command2 [8:0];
logic [1:0] command_A2 [8:0];
logic [1:0] command_B2 [8:0];
logic [1:0] active_command3 [1:0][2:0][3:0];
logic [1:0] command_A3 [1:0][2:0][3:0];
logic [1:0] command_B3 [1:0][2:0][3:0];
logic [2:0] use_A4nB4;
logic [8:0][1:0] active_command4;
logic [8:0][1:0] command_A4;
logic [8:0][1:0] command_B4;
logic [8:0] pipe1 [7:0];
logic [8:0] pipe1_input;
integer cyc;
assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0];
assign active_command2 = (use_AnB) ? command_A2 : command_B2;
// Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing
assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0];
// Check we can cope with things other than packed arrays
assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4;
always @ (posedge clk) begin
pipe1_input <= pipe1_input + 1;
pipe1[0] <= pipe1_input;
pipe1[7:1] <= pipe1[6:0];
end
logic [3:0][13:0] iq_read_data [15:0];
logic [3:0][13:0] iq_data;
logic [3:0] sel;
assign iq_data = iq_read_data[sel];
always @ (posedge clk) begin
sel = sel + 1;
end
initial begin
cyc = 0;
use_AnB = 0;
for (int i = 0; i < 7; ++i) begin
command_A[i] = 2'b00;
command_B[i] = 2'b11;
command_A2[i] = 2'b00;
command_B2[i] = 2'b11;
pipe1_input = 9'b0;
end
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
for (int k = 0; k < 4; ++k) begin
command_A3[i][j][k] = 2'b00;
command_B3[i][j][k] = 2'b11;
end
end
end
end
always @ (posedge clk) begin
use_AnB <= ~use_AnB;
cyc <= cyc + 1;
if (use_AnB) begin
if (active_command[3] != 2'b00) begin
$stop;
end
if (active_command2[3] != 2'b00) begin
$stop;
end
if (active_command3[0][1][2] != 2'b00) begin
$stop;
end
end
if (!use_AnB) begin
if (active_command[3] != 2'b11) begin
$stop;
end
if (active_command2[3] != 2'b11) begin
$stop;
end
if (active_command3[3][1][2] != 2'b11) begin
$stop;
end
end
end
logic [8:0] last_pipe;
always @(posedge clk) begin
if (cyc < 3) begin
last_pipe <= pipe1[0];
end
else begin
if (last_pipe + 1 != pipe1[0]) begin
$stop;
end
else begin
last_pipe <= pipe1[0];
end
end
if (cyc > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule : t
|
#include <bits/stdc++.h> using namespace std; const int64_t INF = 0x3f3f3f3f; const int64_t INFLL = 0x3f3f3f3f3f3f3f3f; const int64_t MOD = 1e9 + 7; const double EPS = 1e-9; const double PI = acos(-1); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int64_t rand(int64_t x, int64_t y) { return uniform_int_distribution<int64_t>(x, y)(rng); } int64_t mul(int64_t a, int64_t b) { int64_t ret = (1ll * (a % MOD) * (b % MOD)) % MOD; return (ret + MOD) % MOD; } int64_t add(int64_t a, int64_t b) { int64_t ret = (1ll * (a % MOD) + (b % MOD)) % MOD; return (ret + MOD) % MOD; } int64_t pow_exp(int64_t n, int64_t p) { if (!p) return 1; if (p & 1) return mul(n, pow_exp(n, p - 1)); int64_t tmp = pow_exp(n, p / 2); return mul(tmp, tmp); } const int64_t MAX = 2e5 + 10; const int64_t NMAX = 2e5 + 10; const int64_t MMAX = 2e5 + 10; const int64_t LOG_MAX = ceil(log2(double(NMAX))); const int64_t BLOCK = ceil(sqrt(double(NMAX))); int64_t n; string str[20]; map<int64_t, vector<int64_t> > mp[20]; int64_t tot[20]; int64_t mem[1 << 20]; int64_t go(int64_t msk, int64_t sm) { if (msk + 1 == 1 << n) { return 0; } int64_t &ret = mem[msk]; if (ret + 1) return ret; int64_t ans = 0; for (int64_t i = 0; i < n; i++) if (((msk >> i) & 1) == 0) { int64_t mn = mp[i].begin()->first; if (sm + mn >= 0) { int64_t cans = 0; cans += go(msk ^ (1 << i), sm + tot[i]); auto it = mp[i].find(-sm); if (it != mp[i].end()) cans += it->second.size(); ans = max(ans, cans); } else { auto it = mp[i].find(-sm); if (it == mp[i].end()) { continue; } if (it == mp[i].begin()) { int64_t cans = it->second.size(); ans = max(ans, cans); } else { auto &v = mp[i][-sm]; int64_t r = (--it)->second.front(); int64_t cans = lower_bound(v.begin(), v.end(), r) - v.begin(); ans = max(ans, cans); } } } return ret = ans; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int64_t i = 0; i < n; i++) { cin >> str[i]; } for (int64_t i = 0; i < n; i++) { int64_t sm = 0; for (int64_t j = 0; j < str[i].size(); j++) { sm += str[i][j] == ( ? +1 : -1; mp[i][sm].push_back(j); } tot[i] = sm; } memset(mem, -1, sizeof mem); cout << go(0, 0) << n ; }
|
// testbench_8.v
////////////////////////////////////////////////////////////////////////////////
// CPU testbench using the suggested program of lab 8
////////////////////////////////////////////////////////////////////////////////
// Dimitrios Paraschas ()
////////////////////////////////////////////////////////////////////////////////
// inf.uth.gr
// ce232 Computer Organization and Design
////////////////////////////////////////////////////////////////////////////////
// lab 8
// implementation of a subset of MIPS instructions executing CPU
////////////////////////////////////////////////////////////////////////////////
`include "constants.h"
`timescale 1ns/1ps
module cpu_tb;
// unchangeable parameters
// http://www.edaboard.com/thread194570.html
localparam N_REGISTERS = 32;
localparam IMS = 32;
localparam DMS = 32;
reg clock, reset; // clock and reset signals
integer i;
// CPU (clock, reset);
// module with multiple parameters
// http://www.asic-world.com/verilog/para_modules1.html
CPU #(.INSTR_MEM_SIZE(IMS), .DATA_MEM_SIZE(DMS)) CPU_0 (clock, reset);
always begin
#5;
clock = ~clock;
end
initial begin
// specify a VCD dump file and variables
// http://verilog.renerta.com/source/vrg00056.htm
$dumpfile("dumpfile_8.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
// clock and reset signals
clock = 1;
reset = 0;
// load the program to the instruction memory
//$readmemh("program_8.mhex", CPU_0.InstructionMemory_0.data);
$readmemb("program_8.mbin", CPU_0.InstructionMemory_0.data);
// TODO
// zero waiting time is preferred
//#0;
#5;
reset = 1;
// initialize the registers
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#55;
#30;
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 2) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 4) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 8) &&
(CPU_0.Registers_0.data[9] == 1) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 13) &&
(CPU_0.Registers_0.data[14] == 14) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 17) &&
(CPU_0.Registers_0.data[18] == 12) &&
(CPU_0.Registers_0.data[19] == 19) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 29) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31) &&
(CPU_0.DataMemory_0.data[16] == 12) &&
// NOTE
// the program counter would be 20 just after the program
// execution in a sinlge cycle CPU.
(CPU_0.ProgramCounter_0.pc == 32)) begin
$display("\n");
$display("program 8 completed successfully");
$display("\n");
end // if
else begin
$display("\n");
$display("program 8 failed");
$display("\n");
end // else
$finish;
end // initial
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__OR2_BEHAVIORAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100 + 10; int a[N]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n + n; i++) scanf( %d , &a[i]); sort(a, a + n + n); if (a[n] > a[n - 1]) puts( YES ); else puts( NO ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_8_V
`define SKY130_FD_SC_HDLL__DIODE_8_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_8 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_8 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> int b[1010]; double dp[1010][1010]; int main() { int n, m, i, j, x, y; double ans = 0; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) scanf( %d , &b[i]); for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (b[i] > b[j]) dp[i][j] = 1; else dp[i][j] = 0; } } while (m--) { scanf( %d%d , &x, &y); x--; y--; dp[x][y] = dp[y][x] = 0.5; for (i = 0; i < n; i++) { if (x == i || y == i) continue; dp[x][i] = (dp[x][i] + dp[y][i]) * 0.5; dp[y][i] = dp[x][i]; dp[i][x] = 1 - dp[x][i]; dp[i][y] = dp[i][x]; } } for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { ans += dp[i][j]; } } printf( %.10f n , ans); return 0; }
|
#include <bits/stdc++.h> template <typename T> void MACRO_VAR_Scan(T& t) { std::cin >> t; } template <typename First, typename... Rest> void MACRO_VAR_Scan(First& first, Rest&... rest) { std::cin >> first; MACRO_VAR_Scan(rest...); } template <typename T> void MACRO_VEC_ROW_Init(int n, T& t) { t.resize(n); } template <typename First, typename... Rest> void MACRO_VEC_ROW_Init(int n, First& first, Rest&... rest) { first.resize(n); MACRO_VEC_ROW_Init(n, rest...); } template <typename T> void MACRO_VEC_ROW_Scan(int p, T& t) { std::cin >> t[p]; } template <typename First, typename... Rest> void MACRO_VEC_ROW_Scan(int p, First& first, Rest&... rest) { std::cin >> first[p]; MACRO_VEC_ROW_Scan(p, rest...); } template <class T> inline T CHMAX(T& a, const T b) { return a = (a < b) ? b : a; } template <class T> inline T CHMIN(T& a, const T b) { return a = (a > b) ? b : a; } template <class T> std::vector<std::vector<T>> VV(int n, int m, T init = T()) { return std::vector<std::vector<T>>(n, std::vector<T>(m, init)); } template <typename S, typename T> std::ostream& operator<<(std::ostream& os, std::pair<S, T> p) { os << ( << p.first << , << p.second << ) ; return os; } using ll = long long; using ull = unsigned long long; using ld = long double; using PAIR = std::pair<int, int>; using PAIRLL = std::pair<ll, ll>; constexpr int INFINT = 1 << 30; constexpr int INFINT_LIM = (1LL << 31) - 1; constexpr ll INFLL = 1LL << 60; constexpr ll INFLL_LIM = (1LL << 62) - 1 + (1LL << 62); constexpr double EPS = 1e-10; constexpr int MOD = 998244353; constexpr double PI = 3.141592653589793238462643383279; template <class T, size_t N> void FILL(T (&a)[N], const T& val) { for (auto& x : a) x = val; } template <class ARY, size_t N, size_t M, class T> void FILL(ARY (&a)[N][M], const T& val) { for (auto& b : a) FILL(b, val); } template <class T> void FILL(std::vector<T>& a, const T& val) { for (auto& x : a) x = val; } template <class ARY, class T> void FILL(std::vector<std::vector<ARY>>& a, const T& val) { for (auto& b : a) FILL(b, val); } bool g[20][20]; bool h[20][20]; bool dp[16][1 << 16][16]; signed main() { std::ios::sync_with_stdio(false); std::cin.tie(0); ; int n, m; MACRO_VAR_Scan(n, m); ; std::vector<std::vector<int>> a(n, std::vector<int>(m)); for (auto& R : a) for (auto& w : R) std::cin >> w; ; auto check = [&](int d) { FILL(g, true); FILL(h, true); FILL(dp, false); for (int i = 0; i < int(n); ++i) for (int j = 0; j < int(n); ++j) { for (int k = 0; k < int(m); ++k) { if (std::abs(a[i][k] - a[j][k]) < d) { g[i][j] = false; break; } } for (int k = 0; k < int(m - 1); ++k) { if (std::abs(a[i][k] - a[j][k + 1]) < d) { h[i][j] = false; break; } } } for (int root = 0; root < int(n); ++root) { dp[root][1 << root][root] = true; for (int mask = 0; mask < int(1 << n); ++mask) for (int i = 0; i < int(n); ++i) { if (!dp[root][mask][i]) continue; if (!(mask & 1 << i)) continue; for (int j = 0; j < int(n); ++j) { if (!g[i][j]) continue; if (mask & 1 << j) continue; dp[root][mask | 1 << j][j] = true; } } for (int i = 0; i < int(n); ++i) if (n == 1 || i != root) { if (dp[root][(1 << n) - 1][i] && h[i][root]) return true; } } return false; }; int ng = 1000000009, ok = 0; while (ng - ok > 1) { int me = (ok + ng) / 2; if (check(me)) ok = me; else ng = me; } std::cout << (ok); std::cout << n ; ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n == 1 && m == 2) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 1 << << 2 << endl; cout << 1 << << 1 << endl; return 0; } if (n == 2 && m == 1) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 2 << << 1 << endl; cout << 1 << << 1 << endl; return 0; } if ((n % 2 && m % 2) || n == 1 || m == 1) { cout << 1 << endl; if (n == 1) { cout << 1 << << m; cout << << 1 << << 1 << endl; } else if (m == 1) { cout << 1 << << 1 << << n << << 1 << endl; } else if (n % 2 == 1 && m % 2 == 1) { cout << n << << m << ; cout << n << << 1 << endl; } else { cout << n << << 1; cout << << 1 << << 1 << endl; } } else cout << 0 << endl; if (m % 2 == 0) { for (int i = 1; i <= m; i++) cout << 1 << << i << endl; for (int j = m; j >= 1; j -= 2) { for (int i = 2; i <= n; i++) cout << i << << j << endl; for (int i = n; i > 1; i--) cout << i << << j - 1 << endl; } cout << 1 << << 1 << endl; } else { cout << 1 << << 1 << endl; for (int i = 1; i <= n; i += 2) { for (int j = 2; j <= m; j++) cout << i << << j << endl; if (i != n) for (int j = m; j >= 2; j--) cout << i + 1 << << j << endl; } if (n % 2 == 1 && m % 2 == 0) { for (int i = 2; i <= n; i++) cout << i << << 1 << endl; cout << 1 << << 1 << endl; } else for (int i = n; i >= 1; i--) cout << i << << 1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; cin >> s1 >> s2; int n = s1.length(), k = 0, s; for (int i = 0; i < n; i++) if (s1[i] != s2[i]) k++; if (k % 2 == 1) printf( impossible ); else { int s = k / 2; string ans; for (int i = 0; i < n; i++) if (s1[i] != s2[i]) if (s > 0) { ans += s1[i]; s--; } else ans += s2[i]; else ans += s1[i]; cout << ans; } return 0; }
|
/*
* Rx_Header Module
* Author: Benjamin Huntsman
*
* This module controls the receiving and appropriate transimission of the
* TLP Header. This module is instantiated in the Rx_Engine and will control
* the loading of the TLP header into the Tx_Header_FIFO and into registers
* that will be holding the header data for translation into OCP Signals.
*/
module rx_fsm(
// Module Ports /*{{{*/
// Command Signals /*{{{*/
input wire rx_reset,
/*}}}*/
// PCIe Core AXI Interface/*{{{*/
input wire rx_clk, // clock for entire bridge
input wire rx_valid, //
input wire [keep_width - 1:0] rx_keep,
input wire rx_last,
output reg rx_ready,
/*}}}*/
// Tx Header AXI FIFO/*{{{*/
input wire tx_header_fifo_ready,
output reg tx_header_fifo_valid,
/*}}}*/
// OCP Registers/*{{{*/
input wire [1:0] optype, // Indicates that the header will be 4DW, not 3DW and if data is present or not
output reg [2:0] ocp_reg_ctl, // Controls the inputs to the OCP registers for translation and data
// OCP Controller/*{{{*/
input wire ocp_ready, // Indicates that the OCP interface is ready for transmission of data
output reg ocp_valid, // Indicates to the OCP interface that a transaction is ready
output reg ocp_readreq, // Indicates to the OCP interface that a read request is being made
output reg ocp_writereq // Indicates to the OCP interface that a write request is being made
/*}}}*/
);
/*}}}*/
/*}}}*/
// Declarations/*{{{*/
// Parameters for parameterization of module
parameter keep_width = 8;
// State encodings
localparam IDLE = 3'b000;
localparam H1 = 3'b001;
localparam H2 = 3'b010;
localparam DATA3 = 3'b011;
localparam DATA4 = 3'b100;
// State Registers
reg [3:0] state;
reg [3:0] next;
/*}}}*/
// Begin FSM Blocks/*{{{*/
// State transition logic/*{{{*/
always @(posedge clk) begin
if (reset) begin
state <= 4'b0; // Reset state value to zero
state[IDLE] <= 1'b1; end // Set to RESET state
else begin
state <= next; end // Transition to next state
end
/*}}}*/
// Next state logic/*{{{*/
always @(state) begin
next <= 4'b0;
case (1'b1)
// IDLE/*{{{*/
// System Idles while waiting for valid TLP to be presented
// Stays until rx_valid and tx_header_fifo_ready asserted
state[IDLE]: begin
if (rx_valid && tx_header_fifo_ready) begin // TLP ready to receive
next[H1] = 1'b1; end
else begin // Not valid so stay
next[IDLE] = 1'b1; end
end
/*}}}*/
// H1/*{{{*/
// First header slice transmitted
// Stays unless PCIe Core holds valid high and tx header fifo is
// ready
state[H1]: begin
if (rx_valid && tx_header_fifo_ready) begin // Received first slice, move to second
next[H2] = 1'b1; end
else begin // Not valid so stay
next[H1] = 1'b1; end
end
/*}}}*/
// H2/*{{{*/
// Second header slice transmitted
state[H2]: begin
if (rx_valid && tx_header_fifo_ready && optype[1]) begin
if (optype[0] == 0) begin // Mem write 3 DW, transmit data
next[DATA3] = 1'b1; end
else begin // Mem write 4 DW, transmit data
next[DATA4] = 1'b1; end
end
else if (rx_valid && tx_header_fifo_ready && rx_last) begin // Read op, only header
next[IDLE] = 1'b1; end
else begin // Not valid so stay
next[H2] = 1'b1; end
end
/*}}}*/
// Data transmission/*{{{*/
// Controls transmission of data on a 96 bit shift register
state[DATA3]: begin
if (rx_valid && ocp_ready && rx_last) begin // Written last data, finish operation
next[IDLE] = 1'b1; end
else begin // Still data left to transmit or not valid, so stay
next[DATA3] = 1'b1; end
state[DATA4]: begin
if (rx_valid && ocp_ready && rx_last) begin // Written last data, finish operation
next[IDLE] = 1'b1; end
else begin // Still data left to transmit or not valid, so stay
next[DATA4] = 1'b1; end
//*}}}*/
default: begin
next[IDLE] = 1'b1; end // If nothing matches return to default
endcase
end
/*}}}*/
// Output logic/*{{{*/
always @(posedge rx_clk) begin
case (1'b1)
// IDLE/*{{{*/
// System Idles while waiting for valid TLP to be presented
// All outputs should be set to default
state[IDLE]: begin // IDLE - Waiting for TLP
rx_ready <= 1'b0; // Rx waiting
tx_header_fifo_valid <= 1'b0; // Nothing being presented to tx header fifo
ocp_reg_ctl <= IDLE; // OCP registers do nothing
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
/*}}}*/
// H1/*{{{*/
// First header slice transmitted
state[H1]: begin
if (rx_valid && tx_header_fifo_ready) begin // Receiving first slice
rx_ready <= 1'b1; // Ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H1; // Slice goes into H1 OCP register
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else if (rx_valid && ~tx_header_fifo_ready) begin // Not ready to receive due to tx_header FIFO
rx_ready <= 1'b0; // Not ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H1; // Stay on H1
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else begin // Valid data not being presented
rx_ready <= 1'b0; // Not ready to receive due to no valid data
tx_header_fifo_valid <= 1'b0; // Not presenting valid data to tx fifo
ocp_reg_ctl <= H1; // Stay on H1
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
/*}}}*/
// H2/*{{{*/
// Second header slice transmitting
state[H2]: begin
if (rx_valid && tx_header_fifo_ready) begin // Receiving second slice
rx_ready <= 1'b1; // Ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H2; // Slice goes into H2 OCP register
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else if (rx_valid && ~tx_header_fifo_ready) begin // Not ready to receive due to tx_header FIFO
rx_ready <= 1'b0; // Not ready to receive
tx_header_fifo_valid <= 1'b1; // Valid data being presented to tx fifo
ocp_reg_ctl <= H2; // Stay on H2
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
else begin // Valid data not being presented
rx_ready <= 1'b0; // Not ready to receive due to no valid data
tx_header_fifo_valid <= 1'b0; // Not presenting valid data to tx fifo
ocp_reg_ctl <= H2; // Stay on H2
ocp_valid <= 1'b0; // Nothing being presented to OCP interface
ocp_readreq <= 1'b0; // No read request being made to OCP
ocp_writereq <= 1'b0; // No write request being made to OCP
end
/*}}}*/
// Data transmission/*{{{*/
// Controls transmission of data on a 96 bit shift register
state[DATA3]: begin
if (rx_valid && ocp_ready) begin // Writing data onto OCP lines
rx_ready <= 1'b1; // Ready to transmit data
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA3; // Stay on DATA3
ocp_valid <= 1'b1; // Data being presented to OCP interface
if (optype[1]) == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
else begin // No data transmitting due to OCP or no valid data
rx_ready <= 1'b0; // Not ready to transmit
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA3; // Stay on DATA3
ocp_valid <= rx_valid; // Data only being presented if valid on AXI int.
if (optype[1] == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
end
state[DATA4]: begin
if (rx_valid && ocp_ready) begin // Writing data onto OCP lines
rx_ready <= 1'b1; // Ready to transmit data
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA4; // Stay on DATA4
ocp_valid <= 1'b1; // Data being presented to OCP interface
if (optype[1] == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
else begin // No data transmitting due to OCP or no valid data
rx_ready <= 1'b0; // Not ready to transmit
tx_header_fifo_valid <= 1'b0; // Not presenting header to tx fifo
ocp_reg_ctl <= DATA4; // Stay on DATA4
ocp_valid <= rx_valid; // Data begin presented only if valid on AXI int.
if (optype[1] == 1'b0) begin
ocp_readreq <= 1'b1; // Read request being made to OCP
ocp_writereq <= 1'b0;
end
else begin
ocp_readreq <= 1'b0;
ocp_writereq <= 1'b1; // Write request being made to OCP
end
end
end
//*}}}*/
// Default/*{{{*/
default: begin
next[IDLE] = 1'b1; end // If nothing matches return to default
endcase
end/*}}}*//*}}}*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_PP_BLACKBOX_V
|
/*
* Copyright (c) 2006 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: casesynth3.v,v 1.1 2006/01/21 21:53:09 stevewilliams Exp $"
*/
/*
* This case tests the handling very wide (but sparse) case statements.
*/
module main;
reg clk, rst, set;
reg [3:0] out, load;
reg [10:0] op;
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
if (rst) begin
out <= 0;
end else if (set) begin
out <= load;
end else
case (op)
10'b0000000001: /* increment */ out <= out + 1;
10'b1000000000: /* decrement */ out <= out - 1;
10'b1000000001: /* Invert */ out <= ~out;
/* Other ops cause out to not change. */
endcase // case(mod)
(* ivl_synthesis_off *)
initial begin
/* Test rst behavior. */
op = 10'b0000000000;
rst = 1;
set = 0;
load = 0;
clk = 0;
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b0000) begin
$display("FAILED -- out=%b (reset)", out);
$finish;
end
/* Test set behavior */
rst = 0;
set = 1;
load = 4'b0100;
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b0100) begin
$display("FAILED -- out=%b (load)", out);
$finish;
end
/* Test increment behavior */
op = 10'b0000000001;
rst = 0;
set = 0;
load = 0;
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b0101) begin
$display("FAILED -- out=%b (increment 1)", out);
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b0110) begin
$display("FAILED -- out=%b (increment 2)", out);
$finish;
end
/* Test invert behavior */
op = 10'b1000000001;
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b1001) begin
$display("FAILED == out=%b (invert)", out);
$finish;
end
/* Test NO-OP behavior */
op = 10'b0000000000;
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b1001) begin
$display("FAILED -- out=%b (noop)", out);
$finish;
end
/* Test decrement behavior */
op = 10'b1000000000;
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b1000) begin
$display("FAILED -- out=%b (decrement 1)", out);
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (out !== 4'b0111) begin
$display("FAILED -- out=%b (decrement 2)", out);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; pair<double, double> midpoint(double x1, double y1, double x2, double y2) { return {(x1 + x2) / 2, (y1 + y2) / 2}; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; map<pair<double, double>, int> mp; pair<double, double> pr[n + 5]; for (int i = 0; i < n; i++) { cin >> pr[i].first >> pr[i].second; mp[pr[i]]++; } int ans = 0; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (mp.find(midpoint(pr[i].first, pr[i].second, pr[j].first, pr[j].second)) != mp.end()) ans++; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_4_V
`define SKY130_FD_SC_HD__A41OI_4_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, b; cin >> n >> b; vector<int> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; } vector<int> s; for (int i = 0; i < n - 1; i++) { if (arr[i] <= b) { int m = INT_MIN; for (int j = i + 1; j < n; j++) m = max(m, arr[j]); if (arr[i] < m) s.push_back(b + (m - arr[i]) * (b / arr[i])); } } if (!s.empty()) cout << *max_element(s.begin(), s.end()) << endl; else cout << b << endl; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_pgmrom.v when simulating
// the core, upd77c25_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [23 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [23 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(24),
.C_READ_WIDTH_B(24),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long t, v; cin >> t >> v; long long a[t]; for (int i = 0; i < t; i++) cin >> a[i]; long long minx = 0; sort(a, a + t); for (int z = 0; z < t - 1; z++) { minx = max(a[z + 1] - a[z], minx); } long long diff = max(a[0] - 0, v - a[t - 1]); double re; re = max(double(diff), double(minx) / 2.0); cout << setprecision(10) << fixed << re; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR4BB_PP_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a[20][110], b[20][110], c[20][110]; vector<int> res; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < n; i++) { char st[15]; scanf( %s , st); for (int j = 0; j < m; j++) scanf( %d%d%d , &a[i][j], &b[i][j], &c[i][j]); } int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; res.clear(); for (int h = 0; h < m; h++) for (int ik = 0; ik < c[i][h]; ik++) res.push_back(b[j][h] - a[i][h]); sort(res.begin(), res.end()); reverse(res.begin(), res.end()); int v = 0; for (int kp = 0; kp < k && kp < (int)res.size(); kp++) v += max(res[kp], 0); ans = max(ans, v); } } printf( %d n , ans); return 0; }
|
// This tests SystemVerilog interfaces
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// error counter
bit err = 0;
logic clk = 1'b1;
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// clock generator
always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// counters
int cnt;
int cnt_src;
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
// finish report
initial begin
wait (cnt == 3*16);
if (!err) $display("PASSED");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
);
endmodule
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
);
// modport signals
logic req; // request
logic grt; // grant
logic inc; // increment
// local signals
integer cnt; // counter
// source
modport src (
output req,
input grt
);
// drain
modport drn (
input req,
output grt
);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + inc;
endinterface
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// request signal
assign inf.req = rnd[0];
endmodule
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// grant signal
assign inf.grt = rnd[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int t[107][107]; int mini; int a; int maxi; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { mini = 1000000009; for (int j = 1; j <= m; j++) { scanf( %d , &a); if (a < mini) { mini = a; } } if (mini > maxi) maxi = mini; } printf( %d , maxi); return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/counter.v
*/
// Behavioral model for the 32-bit program counter
module program_counter2 (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
reg [0:31] temp_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
temp_pc<=32'd0;
end
else
begin
temp_pc<=temp_pc+32'd4;
next_pc<=temp_pc>>2;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int ss = 1000; int n, k, ans, x; bool flag1, flag2; bool a[5000][5000]; int b[1002], tot; int main() { scanf( %d%d , &n, &k); memset(a, false, sizeof(a)); memset(b, false, sizeof(b)); flag1 = flag2 = false; n += ss; for (int i = 1; i <= k; ++i) { scanf( %d , &x); a[0][x + ss] = true; if (x + ss > n) flag1 = true; if (x + ss < n) flag2 = true; } tot = 0; for (int i = 0; i <= 1000 + ss; ++i) { if (a[0][i]) b[++tot] = i; } if (a[0][n]) ans = 1; else if (flag1 ^ flag2 || (k == 1)) ans = -1; else for (int i = 1; i <= 5010; ++i) { for (int j = 0; j <= 3000; ++j) if (a[i - 1][j]) { for (int k = 1; k <= tot; ++k) { if (j + b[k] - n >= 0 && j + b[k] - n <= 3000) { a[i][j + b[k] - n] = true; } } } if (a[i][n]) { ans = i + 1; break; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int n, x_num; x_num = 0; std::string x; std::cin >> n; for (int i = 0; i < n; i++) { std::cin >> x; if (x.substr(0, 2) == -- || x.substr(1, 2) == -- ) x_num--; else x_num++; } std::cout << x_num; return 0; }
|
// File: write_pointerTBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:09:01 2018
`timescale 1ns/10ps
module write_pointerTBV (
);
// myHDL->Verilog Testbench for `write_pointer module`
reg wr = 0;
reg fifo_full = 0;
wire [4:0] wptr;
wire fifo_we;
reg clk = 0;
reg rst_n = 0;
wire write_pointer0_0_fifo_we_i;
reg [4:0] write_pointer0_0_wptr_i = 0;
always @(wr, fifo_full, rst_n, wptr, clk, fifo_we) begin: WRITE_POINTERTBV_PRINT_DATA
$write("%h", wr);
$write(" ");
$write("%h", fifo_full);
$write(" ");
$write("%h", wptr);
$write(" ");
$write("%h", fifo_we);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", rst_n);
$write("\n");
end
assign write_pointer0_0_fifo_we_i = ((!fifo_full) && wr);
always @(posedge clk, negedge rst_n) begin: WRITE_POINTERTBV_WRITE_POINTER0_0_POINTERUPDATE
if (rst_n) begin
write_pointer0_0_wptr_i <= 0;
end
else if (write_pointer0_0_fifo_we_i) begin
write_pointer0_0_wptr_i <= (write_pointer0_0_wptr_i + 1);
end
else begin
write_pointer0_0_wptr_i <= write_pointer0_0_wptr_i;
end
end
assign fifo_we = write_pointer0_0_fifo_we_i;
assign wptr = write_pointer0_0_wptr_i;
initial begin: WRITE_POINTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: WRITE_POINTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h0: begin
wr <= 1;
end
'ha: begin
wr <= 0;
end
'hc: begin
wr <= 1;
end
'he: begin
fifo_full <= 1;
end
'h10: begin
rst_n <= 1;
end
'h12: begin
rst_n <= 0;
end
'h14: begin
$finish;
end
default: begin
// pass
end
endcase
i = i + 1;
@(posedge clk);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_2_V
`define SKY130_FD_SC_HS__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; vector<int> s(6); for (int i = 0; i < 6; i++) { if ((1 << i) & a) s[i]++; } int res = 0; res += (16 * s[0]); res += (2 * s[1]); res += (8 * s[2]); res += (4 * s[3]); res += s[4]; res += (32 * s[5]); cout << res << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 10005; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } int T, n, A, B, C, cnt, p[N], mu[N], du[N], fe[N], tot; long long a[N], b[N], c[N]; bool np[N]; void init() { mu[1] = 1; for (int i = 2; i <= n; i++) { if (!np[i]) p[++cnt] = i, mu[i] = -1; for (int j = 1; j <= cnt && i * p[j] <= n; j++) { np[i * p[j]] = 1; if (i % p[j] == 0) break; mu[i * p[j]] = -mu[i]; } } } struct edge { int u, v, w; }; struct _ { int v, w; }; vector<_> G[N]; int main() { n = 10000; init(); scanf( %d%d%d , &A, &B, &C); n = max(A, max(B, C)); for (int i = 0; i <= n; i++) a[i] = b[i] = c[i] = du[i] = 0, G[i].clear(); for (int i = 1; i <= A; i++) for (int j = i; j <= A; j += i) a[i] += A / j; for (int i = 1; i <= B; i++) for (int j = i; j <= B; j += i) b[i] += B / j; for (int i = 1; i <= C; i++) for (int j = i; j <= C; j += i) c[i] += C / j; long long ans = 0; for (int i = 1; i <= n; i++) ans += mu[i] * mu[i] * mu[i] * a[i] * b[i] * c[i]; vector<edge> e; for (int d = 1; d <= n; d++) for (int i = 1, l = n / d; i <= l; i++) if (mu[i * d]) for (int j = i + 1, r = n / d / i; j <= r; j++) if (mu[j * d] && gcd(i, j) == 1) { int u = i * d, v = j * d, lcm = i * j * d; ans += mu[u] * mu[u] * mu[v] * (a[u] * b[lcm] * c[lcm] + a[lcm] * b[u] * c[lcm] + a[lcm] * b[lcm] * c[u]); ans += mu[u] * mu[v] * mu[v] * (a[v] * b[lcm] * c[lcm] + a[lcm] * b[v] * c[lcm] + a[lcm] * b[lcm] * c[v]); ++du[u]; ++du[v]; e.push_back((edge){u, v, lcm}); } for (auto &f : e) if (du[f.u] > du[f.v] || (du[f.u] == du[f.v] && f.u < f.v)) G[f.u].push_back((_){f.v, f.w}); else G[f.v].push_back((_){f.u, f.w}); for (int u = 1; u <= n; u++) { for (auto &f : G[u]) fe[f.v] = f.w; for (auto &f : G[u]) for (auto &p : G[f.v]) if (fe[p.v]) ans += mu[u] * mu[f.v] * mu[p.v] * (a[f.w] * b[p.w] * c[fe[p.v]] + a[f.w] * b[fe[p.v]] * c[p.w] + a[p.w] * b[f.w] * c[fe[p.v]] + a[fe[p.v]] * b[f.w] * c[p.w] + a[fe[p.v]] * b[p.w] * c[f.w] + a[p.w] * b[fe[p.v]] * c[f.w]); for (auto &f : G[u]) fe[f.v] = 0; } printf( %d n , int(ans & ((1 << 30) - 1))); }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 5; const long long MOD = 1e9 + 7; long long n, ct; long long a[N], vis[N]; vector<long long> g[N]; void dfs(long long k) { if (vis[k]) return; vis[k] = 1; ct++; for (auto it : g[k]) dfs(it); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; g[i].push_back(a[i]); } vector<long long> ans; for (long long i = 1; i <= n; i++) { if (!vis[i]) { ct = 0; dfs(i); ans.push_back(ct); } } sort(ans.rbegin(), ans.rend()); long long answer = 0; long long sz = ans.size(); for (long long i = 0; i < sz; i++) { answer += ans[i] * ans[i]; } if (sz >= 2) { answer -= ans[0] * ans[0]; answer -= ans[1] * ans[1]; answer += (ans[0] + ans[1]) * (ans[0] + ans[1]); } cout << answer; }
|
#include <bits/stdc++.h> using namespace std; long long n, m; long long x, y, z; vector<pair<long long, long long> > v[200005]; long long dp[300]; bool used[2000005]; long long len[100005]; void dfs(long long x) { used[x] = true; for (long long i = 0; i < v[x].size(); ++i) { long long to = v[x][i].first; if (used[to]) { long long l = len[x] ^ len[to] ^ v[x][i].second; for (long long j = 32; j >= 0; --j) if ((!dp[j] || dp[j] > l) && l & (1 << j)) { dp[j] = l; } else l = min(l, l ^ dp[j]); } else { len[to] = len[x] ^ v[x][i].second; dfs(to); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (long long i = 1; i <= m; ++i) { cin >> x >> y >> z; v[x].push_back(make_pair(y, z)); v[y].push_back(make_pair(x, z)); } dfs(1); long long ans = len[n]; for (long long i = 32; i >= 0; --i) ans = min(ans, ans ^ dp[i]); cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; long long int n, ans, c = 1, i; cin >> t; while (t--) { cin >> n; c = 1, ans = 0, i = 1; while (n > 0) { if (n <= 4) { if (i % 2 != 0) { ans = ans + max(c, n - 1); } else ans += n - max(c, n - 1); break; } else if (n > 4 && (n % 2 != 0 || n % 4 == 0)) { if (i % 2 != 0) ans = ans + 1; i++; n--; } else { if (i % 2 != 0) { ans = ans + n / 2; } i++; n = n / 2; } } cout << ans << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_sio_macro (
VCCD,
VCCHIB,
VDDA,
VDDIO,
VDDIO_Q,
VSSD,
VSSIO,
VSSIO_Q,
VSWITCH,
VSSA,
IN,
IN_H,
TIE_LO_ESD,
AMUXBUS_A,
AMUXBUS_B,
PAD,
PAD_A_ESD_0_H,
PAD_A_ESD_1_H,
PAD_A_NOESD_H,
VINREF_DFT,
VOUTREF_DFT,
DFT_REFGEN,
DM0,
DM1,
HLD_H_N,
HLD_H_N_REFGEN,
HLD_OVR,
IBUF_SEL,
IBUF_SEL_REFGEN,
INP_DIS,
ENABLE_H,
ENABLE_VDDA_H,
OE_N,
OUT,
SLOW,
VOH_SEL,
VOHREF,
VREF_SEL,
VREG_EN,
VREG_EN_REFGEN,
VTRIP_SEL,
VTRIP_SEL_REFGEN
);
wire VOUTREF;
wire VINREF;
wire REFLEAK_BIAS;
inout VCCD;
inout VCCHIB;
inout VDDA;
inout VDDIO;
inout VDDIO_Q;
inout VSSD;
inout VSSIO;
inout VSSIO_Q;
inout VSWITCH;
inout VSSA;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout VINREF_DFT;
inout VOUTREF_DFT;
input DFT_REFGEN;
input HLD_H_N_REFGEN;
input IBUF_SEL_REFGEN;
input ENABLE_VDDA_H;
input ENABLE_H;
input VOHREF;
input VREG_EN_REFGEN;
input VTRIP_SEL_REFGEN;
output [1:0] TIE_LO_ESD;
output [1:0] IN_H;
output [1:0] IN;
inout [1:0] PAD_A_NOESD_H;
inout [1:0] PAD;
inout [1:0] PAD_A_ESD_1_H;
inout [1:0] PAD_A_ESD_0_H;
input [1:0] SLOW;
input [1:0] VTRIP_SEL;
input [1:0] HLD_H_N;
input [1:0] VREG_EN;
input [2:0] VOH_SEL;
input [1:0] INP_DIS;
input [1:0] HLD_OVR;
input [1:0] OE_N;
input [1:0] VREF_SEL;
input [1:0] IBUF_SEL;
input [2:0] DM0;
input [2:0] DM1;
input [1:0] OUT;
reg notifier_enable_h_refgen,
notifier_vtrip_sel_refgen,
notifier_vreg_en_refgen,
notifier_ibuf_sel_refgen,
notifier_vref_sel,
notifier_vref_sel_int,
notifier_voh_sel,
notifier_dft_refgen;
reg notifier_enable_h_0;
reg notifier_hld_ovr_0;
reg notifier_dm_0;
reg notifier_inp_dis_0;
reg notifier_vtrip_sel_0;
reg notifier_slow_0;
reg notifier_oe_n_0;
reg notifier_out_0;
reg notifier_vreg_en_0;
reg notifier_ibuf_sel_0;
reg notifier_enable_h_1;
reg notifier_hld_ovr_1;
reg notifier_dm_1;
reg notifier_inp_dis_1;
reg notifier_vtrip_sel_1;
reg notifier_slow_1;
reg notifier_oe_n_1;
reg notifier_out_1;
reg notifier_vreg_en_1;
reg notifier_ibuf_sel_1;
wire enable_vdda_h_and_enable_h = ENABLE_VDDA_H==1'b1 && ENABLE_H==1'b1;
sky130_fd_io__top_refgen_new REFGEN (
.VSWITCH (VSWITCH),
.VSSIO_Q (VSSIO_Q),
.VDDIO_Q (VDDIO_Q),
.VSSIO (VSSIO),
.VSSD (VSSD),
.VCCHIB (VCCHIB),
.VDDIO (VDDIO),
.VCCD (VCCD),
.VDDA (VDDA),
.VSSA (VSSA),
.VOH_SEL (VOH_SEL[2:0]),
.VREF_SEL (VREF_SEL[1:0]),
.VOHREF (VOHREF),
.VINREF_DFT (VINREF_DFT),
.VOUTREF_DFT (VOUTREF_DFT),
.DFT_REFGEN (DFT_REFGEN),
.AMUXBUS_A (AMUXBUS_A),
.AMUXBUS_B (AMUXBUS_B),
.VOUTREF (VOUTREF),
.VREG_EN (VREG_EN_REFGEN),
.IBUF_SEL (IBUF_SEL_REFGEN),
.VINREF (VINREF),
.VTRIP_SEL (VTRIP_SEL_REFGEN),
.ENABLE_H (ENABLE_H),
.ENABLE_VDDA_H (ENABLE_VDDA_H),
.HLD_H_N (HLD_H_N_REFGEN),
.REFLEAK_BIAS (REFLEAK_BIAS)
);
sky130_fd_io__top_sio SIO_PAIR_1_ (
.VDDIO (VDDIO),
.VCCD (VCCD),
.VDDIO_Q (VDDIO_Q),
.VCCHIB (VCCHIB),
.VSSIO (VSSIO),
.VSSIO_Q (VSSIO_Q),
.VSSD (VSSD),
.PAD (PAD[1]),
.IN_H (IN_H[1]),
.DM (DM1[2:0]),
.HLD_H_N (HLD_H_N[1]),
.PAD_A_ESD_1_H (PAD_A_ESD_1_H[1]),
.PAD_A_ESD_0_H (PAD_A_ESD_0_H[1]),
.ENABLE_H (ENABLE_H),
.OUT (OUT[1]),
.OE_N (OE_N[1]),
.SLOW (SLOW[1]),
.VTRIP_SEL (VTRIP_SEL[1]),
.INP_DIS (INP_DIS[1]),
.TIE_LO_ESD (TIE_LO_ESD[1]),
.IN (IN[1]),
.VINREF (VINREF),
.VOUTREF (VOUTREF),
.REFLEAK_BIAS (REFLEAK_BIAS),
.PAD_A_NOESD_H (PAD_A_NOESD_H[1]),
.VREG_EN (VREG_EN[1]),
.IBUF_SEL (IBUF_SEL[1]),
.HLD_OVR (HLD_OVR[1])
);
sky130_fd_io__top_sio SIO_PAIR_0_ (
.VDDIO (VDDIO),
.VCCD (VCCD),
.VDDIO_Q (VDDIO_Q),
.VCCHIB (VCCHIB),
.VSSIO (VSSIO),
.VSSIO_Q (VSSIO_Q),
.VSSD (VSSD),
.PAD (PAD[0]),
.IN_H (IN_H[0]),
.DM (DM0[2:0]),
.HLD_H_N (HLD_H_N[0]),
.PAD_A_ESD_1_H (PAD_A_ESD_1_H[0]),
.PAD_A_ESD_0_H (PAD_A_ESD_0_H[0]),
.ENABLE_H (ENABLE_H),
.OUT (OUT[0]),
.OE_N (OE_N[0]),
.SLOW (SLOW[0]),
.VTRIP_SEL (VTRIP_SEL[0]),
.INP_DIS (INP_DIS[0]),
.TIE_LO_ESD (TIE_LO_ESD[0]),
.IN (IN[0]),
.VINREF (VINREF),
.VOUTREF (VOUTREF),
.REFLEAK_BIAS (REFLEAK_BIAS),
.PAD_A_NOESD_H (PAD_A_NOESD_H[0]),
.VREG_EN (VREG_EN[0]),
.IBUF_SEL (IBUF_SEL[0]),
.HLD_OVR (HLD_OVR[0])
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 30896 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w128,
w129,
w4,
w133,
w2064,
w1931,
w30896;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w133 = w129 + w4;
assign w1931 = w2064 - w133;
assign w2064 = w129 << 4;
assign w30896 = w1931 << 4;
assign w4 = w1 << 2;
assign o_data0 = w30896;
//multiplier_block area estimate = 4720.16161940588;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
module not_32(
input [31:0] a, //input value
output [31:0] out //output value
);
//output is the inverse of a
assign out[0] = !a[0];
assign out[1] = !a[1];
assign out[2] = !a[2];
assign out[3] = !a[3];
assign out[4] = !a[4];
assign out[5] = !a[5];
assign out[6] = !a[6];
assign out[7] = !a[7];
assign out[8] = !a[8];
assign out[9] = !a[9];
assign out[10] = !a[10];
assign out[11] = !a[11];
assign out[12] = !a[12];
assign out[13] = !a[13];
assign out[14] = !a[14];
assign out[15] = !a[15];
assign out[16] = !a[16];
assign out[17] = !a[17];
assign out[18] = !a[18];
assign out[19] = !a[19];
assign out[20] = !a[20];
assign out[21] = !a[21];
assign out[22] = !a[22];
assign out[23] = !a[23];
assign out[24] = !a[24];
assign out[25] = !a[25];
assign out[26] = !a[26];
assign out[27] = !a[27];
assign out[28] = !a[28];
assign out[29] = !a[29];
assign out[30] = !a[30];
assign out[31] = !a[31];
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << , ; err(++it, args...); } namespace fastIO { bool IOerror = 0; inline char nc() { static char buf[100000], *p1 = buf + 100000, *pend = buf + 100000; if (p1 == pend) { p1 = buf; pend = buf + fread(buf, 1, 100000, stdin); if (pend == p1) { IOerror = 1; return -1; } } return *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } inline void read(int &x) { char ch; while (blank(ch = nc())) ; if (IOerror) return; for (x = ch - 0 ; (ch = nc()) >= 0 && ch <= 9 ; x = x * 10 + ch - 0 ) ; } } // namespace fastIO using namespace fastIO; const double PI = acos(-1.0); const double eps = 1e-8; const int mod = 1e9 + 7; long long qp(long long b, long long n) { long long r = 1; if (n < 0) n += mod - 1; b %= mod; for (; n; n >>= 1, b = b * b % mod) if (n & 1) r = r * b % mod; return r; } int sgn(double x) { if (x < -eps) return -1; return x > eps ? 1 : 0; } const int maxn = 3e5 + 7; const int N = 1e5 + 10; int n; int sum[N], dif[N], a[N]; pair<int, int> p[N]; int main() { scanf( %d , &n); long long ans = 0; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); sum[a[i]]++; ans += (1LL * a[i] * (n - a[i] + 1)); } for (int i = 1; i <= n; ++i) sum[i] += sum[i - 1]; for (int i = 1; i < n; ++i) { p[i].first = a[i]; p[i].second = a[i + 1]; if (p[i].first > p[i].second) swap(p[i].first, p[i].second); ans -= 1LL * p[i].first * (n - p[i].second + 1); } printf( %lld n , ans); }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninjasymbol.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ninjasymbol (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/ninjasymbol.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/ninjasymbol.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//扫描计数器，异步复位高有效
module display_cnt_3bit(input reset, input display_clk,
output reg [2:0] display_cnt_3bit_num);
always @( posedge reset or posedge display_clk) begin
if ( reset) display_cnt_3bit_num <= 0;
else display_cnt_3bit_num <= display_cnt_3bit_num + 1;
end
endmodule
//38译码器，输出低有效，如000译码为11111110
module decod38 (input [2:0] decod_38_in,
output reg [7:0] decod_38_out); //译码输出低有效
always @(decod_38_in ) begin
case(decod_38_in)
3'd0: decod_38_out = ~8'h01;
3'd1: decod_38_out = ~8'h02;
3'd2: decod_38_out = ~8'h04;
3'd3: decod_38_out = ~8'h08;
3'd4: decod_38_out = ~8'h10;
3'd5: decod_38_out = ~8'h20;
3'd6: decod_38_out = ~8'h40;
3'd7: decod_38_out = ~8'h80;
default: decod_38_out = ~8'h00;
endcase
end
endmodule
//多路复用器，8路，4位宽
module mux_8path_4b(
input [2:0] mux_sel, //多路复用器选择信号，111选择mux_in7
input [3:0] mux_in7,
input [3:0] mux_in6,
input [3:0] mux_in5,
input [3:0] mux_in4,
input [3:0] mux_in3,
input [3:0] mux_in2,
input [3:0] mux_in1,
input [3:0] mux_in0,
output reg [3:0] mux_out);
always @(mux_sel or mux_in7 or
mux_in6 or mux_in5 or
mux_in4 or mux_in3 or
mux_in2 or mux_in1 or mux_in0)
begin
mux_out = 4'd0;
case(mux_sel)
3'd0: mux_out = mux_in0;
3'd1: mux_out = mux_in1;
3'd2: mux_out = mux_in2;
3'd3: mux_out = mux_in3;
3'd4: mux_out = mux_in4;
3'd5: mux_out = mux_in5;
3'd6: mux_out = mux_in6;
3'd7: mux_out = mux_in7;
default: mux_out = 4'h0;
endcase
end
endmodule
//七段译码，将bcd转为显示码，低有效，低电平对应的段亮
module SEG7_LUT (iBCD_, oSEG_);
input [3:0] iBCD_;
output [7:0] oSEG_; //低有效
reg [7:0] oSEG_;
always @(iBCD_) //
begin
case(iBCD_)
0:oSEG_=8'hc0;
1:oSEG_=8'hf9;
2:oSEG_=8'ha4;
3:oSEG_=8'hb0;
4:oSEG_=8'h99;
5:oSEG_=8'h92;
6:oSEG_=8'h82;
7:oSEG_=8'hf8;
8:oSEG_=8'h80;
9:oSEG_=8'h90;
10:oSEG_=8'h88;
11:oSEG_=8'h83;
12:oSEG_=8'hc6;
13:oSEG_=8'ha1;
14:oSEG_=8'h86;
//15:oSEG_=8'h8e;
15:oSEG_=8'hbf;
default:oSEG_=8'h00;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long fact[(long long)(1e6 + 10)], mod_inv[(long long)(1e6 + 10)]; long long _pow(long long a, long long n) { if (n == 0) return 1; if (n % 2 == 1) return (a * _pow(a, n - 1)) % (long long)(1e9 + 7); long long x = _pow(a, n / 2) % (long long)(1e9 + 7); return (x * x) % (long long)(1e9 + 7); } void inv() { mod_inv[0] = 1; for (int i = 1; i < (long long)(1e6 + 10) - 1; i++) { mod_inv[i] = _pow(fact[i], (long long)(1e9 + 7) - 2); } } void f() { fact[0] = 1; mod_inv[0] = 1; for (int i = 1; i < (long long)(1e6 + 10) - 1; i++) { fact[i] = fact[i - 1] * i; fact[i] %= (long long)(1e9 + 7); mod_inv[i] = _pow(fact[i], (long long)(1e9 + 7) - 2); } } void init() { f(); } long long nCr(long long n, long long r) { return (((mod_inv[n - r] * mod_inv[r]) % (long long)(1e9 + 7)) * fact[n]) % (long long)(1e9 + 7); } pair<long long, long long> black[2010]; bool cmp(pair<long long, long long> a, pair<long long, long long> b) { return (a.first == b.first) ? a.second < b.second : a.first < b.first; } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); init(); int h, w, n; cin >> h >> w >> n; for (int i = 0; i < n; i++) { cin >> black[i].first >> black[i].second; black[i].first--; black[i].second--; } long long dp[n + 1]; memset(dp, 0, sizeof(dp)); black[n] = make_pair(h - 1, w - 1); sort(black, black + n, cmp); for (int i = 0; i < n + 1; i++) { dp[i] = nCr(black[i].first + black[i].second, black[i].first); for (int j = 0; j < i; j++) { if (black[j].second > black[i].second) continue; dp[i] -= (dp[j] * nCr(black[i].first - black[j].first + black[i].second - black[j].second, black[i].second - black[j].second)) % (long long)(1e9 + 7); dp[i] += (long long)(1e9 + 7); dp[i] %= (long long)(1e9 + 7); } } cout << dp[n] << endl; return 0; }
|
/*!
* <b>Module:</b>clock_inverter
* @file clock_inverter.v
* @date 2016-02-11
* @author Andrey Filippov
*
* @brief Glitch-free clock controlled inverter
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* clock_inverter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* clock_inverter.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module clock_inverter(
input rst, // just for simulation
input clk_in,
input invert,
output clk_out
);
`ifdef SUPPORTED_BUFGCTRL_INVERION
BUFGCTRL #(
.INIT_OUT (0),
.IS_CE0_INVERTED (1'b0),
.IS_CE1_INVERTED (1'b0),
.IS_I0_INVERTED (1'b1),
.IS_I1_INVERTED (1'b0),
.IS_IGNORE0_INVERTED (1'b0),
.IS_IGNORE1_INVERTED (1'b0),
.IS_S0_INVERTED (1'b1),
.IS_S1_INVERTED (1'b0),
.PRESELECT_I0 ("TRUE"),
.PRESELECT_I1 ("FALSE")
) BUFGCTRL_i (
.O (clk_out), // output
.CE0 (1'b1), // input
.CE1 (1'b1), // input
.I0 (clk_in), // input
.I1 (clk_in), // input
.IGNORE0 (1'b0), // input
.IGNORE1 (1'b0), // input
.S0 (invert), // input
.S1 (invert) // input
);
`else
reg invert_r;
reg pos_r;
reg neg_r;
// poor man's ddr
always @ (posedge clk_in) begin
invert_r <= invert;
pos_r <= !rst && !pos_r;
end
always @ (negedge clk_in) begin
neg_r <= pos_r;
end
BUFGCTRL #(
.INIT_OUT (0),
.PRESELECT_I0 ("TRUE"),
.PRESELECT_I1 ("FALSE")
) BUFGCTRL_i (
.O (clk_out), // output
.CE0 (1'b1), // input
.CE1 (1'b1), // input
.I0 (pos_r ^ neg_r), // input
.I1 (pos_r == neg_r), // input
.IGNORE0 (1'b0), // input
.IGNORE1 (1'b0), // input
.S0 (!invert_r), // input
.S1 ( invert_r) // input
);
`endif
endmodule
|
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
task write_data;
begin
$uart_put(bus_wr_val[7:0]);
end
endtask
task read_data;
begin
$uart_get(uart_buf);
end
endtask
reg [8:0] uart_buf = 9'b0;
wire uart_rdy = uart_buf[8];
wire [31:0] status_reg = (uart_rdy ? 32'b10 : 32'b0);
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_rdy && ~cs)
read_data();
ff<=ffold;
if (uart_rdy && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
write_data();
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= status_reg;
end
end
end
bus_ack <= cs;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO0P_PP_BLACKBOX_V
/**
* iso0p: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename F, typename S> ostream& operator<<(ostream& os, const pair<F, S>& p) { return os << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& os, vector<T> const& x) { os << { ; for (auto& y : x) os << y << ; return os << } ; } template <class T> ostream& operator<<(ostream& os, set<T> const& x) { os << { ; for (auto& y : x) os << y << ; return os << } ; } template <typename T> ostream& operator<<(ostream& os, const multiset<T>& v) { os << [ ; typename multiset<T>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename F, typename S> ostream& operator<<(ostream& os, const map<F, S>& v) { os << [ ; typename map<F, S>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } string s[200]; vector<pair<int, int> > ans; void cng(int x1, int y1, int x2, int y2, int x3, int y3) { s[x1][y1] = s[x1][y1] == 1 ? 0 : 1 ; s[x2][y2] = s[x2][y2] == 1 ? 0 : 1 ; s[x3][y3] = s[x3][y3] == 1 ? 0 : 1 ; ans.push_back({x1, y1}); ans.push_back({x2, y2}); ans.push_back({x3, y3}); } void _main_main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; ans.clear(); for (int i = 0; i < n - 2; i++) { for (int j = 0; j < m - 1; j++) { if (s[i][j] == 1 ) cng(i, j, i, j + 1, i + 1, j); } if (s[i][m - 1] == 1 ) cng(i, m - 1, i + 1, m - 1, i + 1, m - 2); } for (int j = 0; j < m - 2; j++) { if (s[n - 2][j] == 1 ) cng(n - 2, j, n - 2, j + 1, n - 1, j + 1); if (s[n - 1][j] == 1 ) cng(n - 1, j, n - 2, j + 1, n - 1, j + 1); } int j = m - 2; while (1) { int cnt = 0; if (s[n - 2][j] == 1 ) cnt++; if (s[n - 2][j + 1] == 1 ) cnt++; if (s[n - 1][j] == 1 ) cnt++; if (s[n - 1][j + 1] == 1 ) cnt++; if (cnt == 0) break; else if (cnt == 1) { if (s[n - 2][j] == 1 ) cng(n - 2, j, n - 2, j + 1, n - 1, j); else if (s[n - 2][j + 1] == 1 ) cng(n - 2, j, n - 2, j + 1, n - 1, j); else if (s[n - 1][j] == 1 ) cng(n - 2, j, n - 2, j + 1, n - 1, j); else if (s[n - 1][j + 1] == 1 ) cng(n - 1, j + 1, n - 2, j + 1, n - 1, j); } else if (cnt == 2) { if (s[n - 2][j] == 1 ) cng(n - 1, j + 1, n - 2, j + 1, n - 1, j); else if (s[n - 2][j + 1] == 1 ) cng(n - 2, j, n - 1, j + 1, n - 1, j); else if (s[n - 1][j] == 1 ) cng(n - 2, j, n - 2, j + 1, n - 1, j + 1); else if (s[n - 1][j + 1] == 1 ) cng(n - 2, j, n - 2, j + 1, n - 1, j); } else if (cnt == 3) { if (s[n - 2][j] == 0 ) cng(n - 1, j + 1, n - 2, j + 1, n - 1, j); else if (s[n - 2][j + 1] == 0 ) cng(n - 2, j, n - 1, j + 1, n - 1, j); else if (s[n - 1][j] == 0 ) cng(n - 2, j, n - 2, j + 1, n - 1, j + 1); else if (s[n - 1][j + 1] == 0 ) cng(n - 2, j, n - 2, j + 1, n - 1, j); } else { cng(n - 2, j, n - 2, j + 1, n - 1, j); } } cout << ans.size() / 3 << endl; int cnt = 0; for (auto i : ans) { cnt++; cout << i.first + 1 << << i.second + 1 << ; if (cnt == 3) { cnt = 0; cout << endl; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int testCase = 1; cin >> testCase; for (int i = 0; i < testCase; i++) { _main_main(); } }
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1.0); const int MAXN = 1e6 + 5; int n, m, t; int v[MAXN]; char s[MAXN]; int main() { cin >> t; while (t--) { cin >> n >> s + 1; int sum1 = 0, sum2 = 0, now = 0; for (int i = 1; i <= n * 2; i++) { if (s[i] == 1 ) now++; else { sum1 += max(now - 1, 0); now = 0; } } if (now) sum1 += now - 1; now = 0; for (int i = 1; i <= n * 2; i++) { if (s[i] == 0 ) now++; else { sum2 += max(now - 1, 0); now = 0; } } if (now) sum2 += now - 1; cout << max(sum1, sum2) << endl; } }
|
#include <bits/stdc++.h> template <typename T> void MACRO_VAR_Scan(T& t) { std::cin >> t; } template <typename First, typename... Rest> void MACRO_VAR_Scan(First& first, Rest&... rest) { std::cin >> first; MACRO_VAR_Scan(rest...); } template <typename T> void MACRO_VEC_ROW_Init(int n, T& t) { t.resize(n); } template <typename First, typename... Rest> void MACRO_VEC_ROW_Init(int n, First& first, Rest&... rest) { first.resize(n); MACRO_VEC_ROW_Init(n, rest...); } template <typename T> void MACRO_VEC_ROW_Scan(int p, T& t) { std::cin >> t[p]; } template <typename First, typename... Rest> void MACRO_VEC_ROW_Scan(int p, First& first, Rest&... rest) { std::cin >> first[p]; MACRO_VEC_ROW_Scan(p, rest...); } template <class T> inline T CHMAX(T& a, const T b) { return a = (a < b) ? b : a; } template <class T> inline T CHMIN(T& a, const T b) { return a = (a > b) ? b : a; } template <class T> using V = std::vector<T>; template <class T> using VV = V<V<T>>; template <typename S, typename T> std::ostream& operator<<(std::ostream& os, std::pair<S, T> p) { os << ( << p.first << , << p.second << ) ; return os; } using ll = long long; using ull = unsigned long long; using ld = long double; using PAIR = std::pair<ll, ll>; using PAIRLL = std::pair<ll, ll>; constexpr ll INFINT = 1 << 30; constexpr ll INFINT_LIM = (1LL << 31) - 1; constexpr ll INFLL = 1LL << 60; constexpr ll INFLL_LIM = (1LL << 62) - 1 + (1LL << 62); constexpr double EPS = 1e-6; constexpr ll MOD = 1000000007; constexpr double PI = 3.141592653589793238462643383279; template <class T, size_t N> void FILL(T (&a)[N], const T& val) { for (auto& x : a) x = val; } template <class ARY, size_t N, size_t M, class T> void FILL(ARY (&a)[N][M], const T& val) { for (auto& b : a) FILL(b, val); } template <class T> void FILL(std::vector<T>& a, const T& val) { for (auto& x : a) x = val; } template <class ARY, class T> void FILL(std::vector<std::vector<ARY>>& a, const T& val) { for (auto& b : a) FILL(b, val); } signed main() { std::ios::sync_with_stdio(false); std::cin.tie(0); ; ll n, m; MACRO_VAR_Scan(n, m); ; std::vector<ll> a, b; MACRO_VEC_ROW_Init(m, a, b); for (ll w_ = 0; w_ < m; ++w_) { MACRO_VEC_ROW_Scan(w_, a, b); }; std::vector<std::vector<ll>> g(n); for (ll i = 0; i < ll(m); ++i) { --a[i]; --b[i]; g[a[i]].emplace_back(b[i]); } std::vector<ll> min(n, INFLL); for (ll i = 0; i < ll(n); ++i) { for (ll x : g[i]) { ll cost = x - i; if (cost <= 0) cost += n; CHMIN(min[i], cost); } } for (ll i = 0; i < ll(n); ++i) { ll ans = 0; for (ll j = 0; j < ll(n); ++j) { ll J = (i + j) % n; if (g[J].empty()) continue; ll len = g[J].size(); ll sum = (len - 1) * n + j + min[J]; CHMAX(ans, sum); } std::cout << (ans); std::cout << (i + 1 == n ? n : ); ; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2004 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file fifo.v when simulating
// the core, fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module fifo(
clk,
sinit,
din,
wr_en,
rd_en,
dout,
full,
empty);
input clk;
input sinit;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
// synopsys translate_off
SYNC_FIFO_V5_0 #(
1, // c_dcount_width
0, // c_enable_rlocs
0, // c_has_dcount
0, // c_has_rd_ack
0, // c_has_rd_err
0, // c_has_wr_ack
0, // c_has_wr_err
1, // c_memory_type
0, // c_ports_differ
1, // c_rd_ack_low
1, // c_rd_err_low
8, // c_read_data_width
512, // c_read_depth
8, // c_write_data_width
512, // c_write_depth
1, // c_wr_ack_low
1) // c_wr_err_low
inst (
.CLK(clk),
.SINIT(sinit),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_ACK(),
.WR_ACK(),
.RD_ERR(),
.WR_ERR(),
.DATA_COUNT());
// synopsys translate_on
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of fifo is "true"
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fifo is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_LP_V
`define SKY130_FD_SC_LP__AND4_LP_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_lp (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_lp (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_LP_V
|
#include <bits/stdc++.h> using namespace std; double us1[210]; double us2[210]; int deal(double *us, int s, int e, int p) { int flag = 0; for (int i = 1; i <= 200; i++) { if (us[i] < 1e-4 / 200.) continue; double dd = us[i] * (100 - p) / 100.; dd /= (e - s + 1); us[i] = us[i] / 100. * p; flag = 1; for (int ss = s; ss <= e; ss++) { us[max(i - ss, 0)] += dd; } } return flag; } int main() { int hp1, t1, s1, e1, p1; int hp2, t2, s2, e2, p2; cin >> hp1 >> t1 >> s1 >> e1 >> p1; cin >> hp2 >> t2 >> s2 >> e2 >> p2; if (p1 == 100) { cout << 0.0; return 0; } if (p2 == 100) { cout << 1.0; return 0; } int nt1 = 0, nt2 = 0; for (int i = 0; i <= 200; i++) { us1[i] = 0.; us2[i] = 0.; } us1[hp1] = 1.; us2[hp2] = 1.; double ret = 0; while (1) { if (nt1 <= nt2) { nt1 += t1; deal(us2, s1, e1, p1); ret += (1. - us1[0]) * us2[0]; us2[0] = 0; } else if (nt1 > nt2) { nt2 += t2; if (!deal(us1, s2, e2, p2)) break; } } cout << ret << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int z[1000005]; string s; void z_function() { int n = (int)s.length(); for (int i = 0; i < n; i++) z[i] = 0; for (int i = 1, l = 0, r = 0; i < n; ++i) { if (i <= r) z[i] = min(r - i + 1, z[i - l]); while (i + z[i] < n && s[z[i]] == s[i + z[i]]) ++z[i]; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; } } long long power(long long a, long long b, long long m) { long long x = 1; a %= m; while (b) { if ((1 & b)) x = x * a % m; a = a * a % m; b >>= 1; } return x; } int y[1000005]; int main() { int n, m; scanf( %d , &n); scanf( %d , &m); cin >> s; z_function(); int p = s.length(); for (int i = 1; i <= m; i++) { scanf( %d , &y[i]); } y[m + 1] = n + 1; int pos = 0; pos += y[1] - 1; for (int i = 2; i <= m + 1; i++) { if (y[i] < y[i - 1] + p) { if (z[y[i] - y[i - 1]] < p - y[i] + y[i - 1]) { printf( 0 ); return 0; } } else pos += y[i] - y[i - 1] - p; } printf( %lld n , power(26, pos, 1000000007)); }
|
module FrameTrans(Reset,Clock100M,Mode,Clock,DataIn);
input Reset;
input Clock100M;
input [1:0] Mode;
output Clock;
output reg DataIn;
reg [31:0] Counter;
reg Clk_10ms;
reg [7:0] StateCnt256;
reg [1:0] FrameCnt4;
reg FrameStart;
reg ScrambEn;
wire ScrambOut;
parameter DELAY_NUM = 5;
parameter FRAMEHEAD = 8'b1001_1011;
parameter FRAMEHEAD_WRONG = 8'b1000_1001;
assign Clock = Clk_10ms;
// Generate Clk_400ms Signal;
always@(negedge Reset or posedge Clock100M)
begin
if(Reset == 1'b0)
begin
Counter <= 0;
Clk_10ms <= 0;
end
else
begin
Counter <= Counter + 1;
if(Counter == DELAY_NUM)
begin
Counter <= 0;
Clk_10ms <= ~Clk_10ms;
end
end
end
// Transmission Control
always@(negedge Reset or posedge Clk_10ms)
begin
if(Reset == 1'b0)
begin
StateCnt256 <= 0;
DataIn <= 0;
FrameStart <= 0;
ScrambEn <= 0;
FrameCnt4 <= 0;
end
else if(Mode > 0)
begin
FrameStart <= 0;
StateCnt256 <= StateCnt256 + 1;
if(StateCnt256)
FrameCnt4 <= FrameCnt4 + 1;
if(StateCnt256 < 8)
begin
ScrambEn <= 0;
if(Mode == 3 && FrameCnt4 == 2)
DataIn <= FRAMEHEAD_WRONG>>(7 - StateCnt256);
else
DataIn <= FRAMEHEAD>>(7 - StateCnt256);
if(StateCnt256 == 5)
FrameStart<=1;
else if (StateCnt256 > 5)
ScrambEn <= 1;
end
else
begin
DataIn <= ScrambOut;
if(StateCnt256 == 255 && Mode == 1)
begin
StateCnt256 <= 255;
ScrambEn <= 0;
DataIn <= 0;
end
end
end
else
begin
StateCnt256 <= 0;
DataIn <= 0;
FrameStart <= 0;
ScrambEn <= 0;
FrameCnt4 <= 0;
end
end
scrambler U1(.clk(Clk_10ms),
.rst(Reset),
.frame_start(FrameStart),
.scramb_en(ScrambEn),
.din(0),
.dout(ScrambOut),
.scramb_out_en());
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_rx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
/*
* UART interface
*/
input wire rxd,
/*
* Status
*/
output wire busy,
output wire overrun_error,
output wire frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg rxd_reg = 1;
reg busy_reg = 0;
reg overrun_error_reg = 0;
reg frame_error_reg = 0;
reg [DATA_WIDTH-1:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign busy = busy_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
overrun_error_reg <= 0;
frame_error_reg <= 0;
end else begin
rxd_reg <= rxd;
overrun_error_reg <= 0;
frame_error_reg <= 0;
if (output_axis_tvalid & output_axis_tready) begin
output_axis_tvalid_reg <= 0;
end
if (prescale_reg > 0) begin
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt > 0) begin
if (bit_cnt > DATA_WIDTH+1) begin
if (~rxd_reg) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
end else begin
bit_cnt <= 0;
prescale_reg <= 0;
end
end else if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
if (rxd_reg) begin
output_axis_tdata_reg <= data_reg;
output_axis_tvalid_reg <= 1;
overrun_error_reg <= output_axis_tvalid_reg;
end else begin
frame_error_reg <= 1;
end
end
end else begin
busy_reg <= 0;
if (~rxd_reg) begin
prescale_reg <= (prescale << 2)-2;
bit_cnt <= DATA_WIDTH+2;
data_reg <= 0;
busy_reg <= 1;
end
end
end
end
endmodule
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
// Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg foo;
initial begin
#0 foo=0;
forever #10 foo=~foo;
end
initial begin
#101 $finish(0);
end
initial
#1 $vpi_call(foo);
endmodule
|
`timescale 10ns/1ps
module main(
input clk_pin_i,
input rst_pin_i,
output[7:0] led_o
);
// Logic analyzer part
// -------------------
// This block consists of ICON controller, with 2 submodules: logic analyzer
// (ILA) nad GPIO module (VIO). They use la_ctl0 and la_ctl1 busses
// respectively.
wire[35:0] la_ctl0;
wire[35:0] la_ctl1;
wire[31:0] la_data;
wire[7:0] la_trig;
wire la_trig_out;
wire[7:0] la_async_in = { 8'd0 };
wire[7:0] la_async_out;
wire[7:0] la_sync_in = { 8'd0 };
wire[7:0] la_sync_out;
chipscope_icon la_icon(
.CONTROL0(la_ctl0[35:0]),
.CONTROL1(la_ctl1[35:0]),
.CONTROL2(),
.CONTROL3()
);
chipscope_ila la_ila(
.CONTROL(la_ctl0[35:0]),
.CLK(clk_pin_i),
.DATA(la_data),
.TRIG0(la_trig),
.TRIG_OUT(la_trig_out)
);
chipscope_vio la_vio(
.CONTROL(la_ctl1[35:0]),
.CLK(clk_pin_i),
.ASYNC_IN(la_async_in[7:0]),
.ASYNC_OUT(la_async_out[7:0]),
.SYNC_IN(la_sync_in[7:0]),
.SYNC_OUT(la_sync_out[7:0])
);
`define G_FREQ 25000000
wire clk_i = clk_pin_i;
wire rst_i = rst_pin_i;
// Actual logic gets generated here.
reg[31:0] clkdiv_r = 0;
wire[31:0] clkdiv = (clkdiv_r[31:0] < `G_FREQ) ? (clkdiv_r[31:0] + 1) : 0;
wire led_change = clkdiv_r[31:0] == 0;
reg[3:0] cnt_r = 0;
wire[3:0] cnt = led_change ? cnt_r + 1 : cnt_r;
always @(posedge clk_i) begin
clkdiv_r <= rst_i ? 0 : clkdiv;
cnt_r <= rst_i ? 0 : cnt;
end
wire dna_dout;
wire dna_din;
reg[7:0] dna_cnt_r = 0;
wire dna_ready = dna_cnt_r[7:0] > 57;
wire[7:0] dna_cnt = !dna_ready ? dna_cnt_r[7:0] + 8'd1 : dna_cnt_r[7:0];
wire dna_read = dna_cnt_r[7:0] == 8'd0;
reg dna_read_r = 0;
wire dna_shift = ~dna_read && ~dna_ready;
reg[63:0] dna_reg_r = 64'd0;
wire[63:0] dna_reg_shifted = { dna_reg_r[62:0], (dna_dout === 1'b1) };
// DNA_PORT simulation block puts 1'b1 in the register and you see it while
// simulating. To get rid of that, we ignore gather data at start.
wire dna_start = dna_read_r && dna_shift; // start
wire dna_end = (dna_read | dna_shift) == 0; // finish
wire[63:0] dna_reg = (dna_start || dna_end) ? dna_reg_r : dna_reg_shifted;
initial begin
#1000;
$finish;
end
integer cycle_num = 0;
always @(posedge clk_i) begin
cycle_num <= cycle_num + 1;
dna_cnt_r <= rst_i ? 8'd0 : dna_cnt;
dna_reg_r <= rst_i ? 64'd0 : dna_reg;
dna_read_r <= rst_i ? 1'b0 : dna_read;
$display("%d %d dna_dout=%d dna_read:%d dna_read_r:%d dna_shift:%d dna_cnt_r=%x dna_reg_r=%x",
$time, cycle_num, dna_dout, dna_read, dna_read_r, dna_shift, dna_cnt_r, dna_reg_r);
end
DNA_PORT #(
.SIM_DNA_VALUE(57'habcdef12) // while picking 64-bit literal was easier
) dna (
.CLK(clk_i),
.DOUT(dna_dout),
.READ(dna_read),
.SHIFT(dna_shift),
.DIN(1'd0)
);
assign la_trig[7:0] = { cnt_r[3:0], 2'd0, rst_pin_i, clk_pin_i };
assign la_data[31:0] = { dna_reg_r };
assign led_o[7:0] = { cnt_r[3:0], la_sync_out[3:0] };
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[100005], dist[100005], sad[100005], subt[100005], ans = 0LL; vector<pair<long long, long long> > adj[100005]; void dfs(long long node, long long par, long long min_vertex) { if (par != -1) sad[node] = (a[node] < dist[node] - dist[min_vertex]); min_vertex = (dist[node] < dist[min_vertex]) ? node : min_vertex; for (auto i : adj[node]) if (par != i.first) { dist[i.first] += (dist[node] + i.second); dfs(i.first, node, min_vertex); subt[node] += subt[i.first]; } subt[node]++; } void dfs1(long long node, long long par) { if (sad[node]) { ans += subt[node]; return; } for (auto i : adj[node]) if (i.first != par) dfs1(i.first, node); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { long long n, i, j, k; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n - 1; i++) { long long x, wt; cin >> x >> wt; adj[i + 1].push_back(make_pair(x, wt)); adj[x].push_back(make_pair(i + 1, wt)); } dfs(1, -1, 1); dfs1(1, -1); cout << ans; } return 0; }
|
// nios_tester_mm_interconnect_0_avalon_st_adapter_003.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_tester_mm_interconnect_0_avalon_st_adapter_003 #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_tester_mm_interconnect_0_avalon_st_adapter_003_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
module tail_offset (ir, toff_0_0, toff_1_0, toff_2_0, toff_3_0, toff_4_0, toff_5_0, toff_6_0, toff_7_0, toff_8_0, toff_9_0, toff_10_0, toff_11_0, toff_12_0, toff_13_0, toff_14_0, toff_15_0);
input [63:0] ir;
output [3:0] toff_0_0, toff_1_0, toff_2_0, toff_3_0, toff_4_0, toff_5_0, toff_6_0, toff_7_0, toff_8_0, toff_9_0, toff_10_0, toff_11_0, toff_12_0, toff_13_0, toff_14_0, toff_15_0;
reg [3:0] toff_0_0, toff_1_1, toff_2_2, toff_3_3, toff_4_4, toff_5_5, toff_6_6, toff_7_7, toff_8_8, toff_9_9, toff_10_10, toff_11_11, toff_12_12, toff_13_13, toff_14_14, toff_15_15;
reg [3:0] ir0, ir1, ir2, ir3, ir4, ir5, ir6, ir7, ir8, ir9, ir10, ir11, ir12, ir13, ir14, ir15;
reg [3:0] toff_1_0, toff_3_2, toff_2_0, toff_3_0, toff_5_4, toff_7_6, toff_6_4, toff_7_4, toff_4_0, toff_5_0, toff_6_0, toff_7_0, toff_9_8, toff_11_10, toff_10_8, toff_11_8, toff_8_0, toff_9_0, toff_10_0, toff_11_0;
wire [3:0] tlen_1, tlen_2, tlen_3, tlen_4, tlen_5, tlen_6, tlen_7, tlen_8, tlen_9, tlen_10, tlen_11, tlen_12, tlen_13, tlen_14;
tail_length u_len1 (.ir(ir1), .len(tlen_1));
tail_length u_len2 (.ir(ir2), .len(tlen_2));
tail_length u_len3 (.ir(ir3), .len(tlen_3));
tail_length u_len4 (.ir(ir4), .len(tlen_4));
tail_length u_len5 (.ir(ir5), .len(tlen_5));
tail_length u_len6 (.ir(ir6), .len(tlen_6));
tail_length u_len7 (.ir(ir7), .len(tlen_7));
tail_length u_len8 (.ir(ir8), .len(tlen_8));
tail_length u_len9 (.ir(ir9), .len(tlen_9));
tail_length u_len10 (.ir(ir10), .len(tlen_10));
tail_length u_len11 (.ir(ir11), .len(tlen_11));
tail_length u_len12 (.ir(ir12), .len(tlen_12));
tail_length u_len13 (.ir(ir13), .len(tlen_13));
always @ (ir) { ir15, ir14, ir13, ir12, ir11, ir10, ir9, ir8, ir7, ir6, ir5, ir4, ir3, ir2, ir1, ir0 } = ir;
always @ ( toff_0_0, toff_1_1, toff_2_2, toff_3_3, toff_4_4, toff_5_5, toff_6_6, toff_7_7, toff_8_8, toff_9_9, toff_10_10, toff_11_11 )
begin
toff_1_0 = toff_1_1 + toff_0_0;
toff_3_2 = toff_3_3 + toff_2_2;
toff_2_0 = toff_2_2 + toff_1_0;
toff_3_0 = toff_3_2 + toff_1_0;
toff_5_4 = toff_5_5 + toff_4_4;
toff_7_6 = toff_7_7 + toff_6_6;
toff_6_4 = toff_6_6 + toff_5_4;
toff_7_4 = toff_7_6 + toff_5_4;
toff_4_0 = toff_4_4 + toff_3_0;
toff_5_0 = toff_5_4 + toff_3_0;
toff_6_0 = toff_6_4 + toff_3_0;
toff_7_0 = toff_7_4 + toff_3_0;
toff_9_8 = toff_9_9 + toff_8_8;
toff_11_10 = toff_11_11 + toff_10_10;
toff_10_8 = toff_10_10 + toff_9_8;
toff_11_8 = toff_11_10 + toff_9_8;
toff_8_0 = toff_8_8 + toff_7_0;
toff_9_0 = toff_9_8 + toff_7_0;
toff_10_0 = toff_10_8 + toff_7_0;
toff_11_0 = toff_11_8 + toff_7_0;;
end
/*
mux16 #(.W(4)) u_offset_mux (
.sel(pc),
.i0000(of0001),
.i0001(of0010),
.i0010(of0011),
.i0011(of0100),
.i0100(of0101),
.i0101(of0110),
.i0110(of0111),
.i0111(of1000),
.i1000(of1001),
.i1001(of1010),
.i1010(of1011),
.i1011(of1100),
.i1100(of1101),
.i1101(4'b????),
.i1110(4'b????),
.i1111(4'b????),
.o(offset)
);
*/
/*
mux16 #(.W(3)) u_len_mux (
.sel(pc),
.i0000(len0001),
.i0001(len0010),
.i0010(len0011),
.i0011(len0100),
.i0100(len0101),
.i0101(len0110),
.i0110(len0111),
.i0111(len1000),
.i1000(len1001),
.i1001(len1010),
.i1010(len1011),
.i1011(len1100),
.i1100(len1101),
.i1101(len1110),
.i1110(len1111),
.i1111(len1111),
.o(len)
);
*/
/*
mux16 #(.W(4)) imm3_0_mux (
.sel(offset),
.i0000(ir1111),
.i0001(ir1110),
.i0010(ir1101),
.i0011(ir1100),
.i0100(ir1011),
.i0101(ir1010),
.i0110(ir1001),
.i0111(ir1000),
.i1000(ir0111),
.i1001(ir0110),
.i1010(ir0101),
.i1011(ir0100),
.i1100(4'b????),
.i1101(4'b????),
.i1110(4'b????),
.i1111(4'b????),
.o(imm3_0)
);
*/
/*
always @ (imm31_16, imm15_8, imm7_4, imm3_0) imm = {imm31_16, imm15_8, imm7_4, imm3_0};
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; long long gMin = 1e12, gMax = -1e12, rMin = 1e12, rMax = -1e12, bMin = 1e12, bMax = -1e12, lasty = -1e12, ret = 0; vector<long long> notGreen[2]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(18); cin >> N; for (int i = 0; i <= N; i++) { long long x = 1e12; char c = G ; if (i < N) cin >> x >> c; if (c == G ) { if (i < N) { gMin = min(gMin, x); gMax = max(gMax, x); } long long add1 = x - lasty, add2 = add1 * 2; if (add1 >= 1e10) add1 = 0; for (int j = 0; j < 2; j++) { if (notGreen[j].size() == 0) continue; add1 += x - lasty; long long maxi = max(notGreen[j].front() - lasty, x - notGreen[j].back()); for (int k = 0; k < notGreen[j].size() - 1; k++) maxi = max(maxi, notGreen[j][k + 1] - notGreen[j][k]); add1 -= maxi; notGreen[j] = vector<long long>(); } ret += min(add1, add2); lasty = x; } else if (c == R ) { notGreen[0].push_back(x); rMin = min(rMin, x); rMax = max(rMax, x); } else { notGreen[1].push_back(x); bMin = min(bMin, x); bMax = max(bMax, x); } } if (gMin > gMax) ret = max(0ll, rMax - rMin) + max(0ll, bMax - bMin); cout << ret << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 1000000000000000000; long long mod = 1000000000; long double pi = 3.141592653589793238; void pls() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } long long n, k, d; vector<vector<int>> res; void backtrack(vector<int> &temp) { if (res.size() == n) return; if (temp.size() == d) { res.push_back(temp); return; } for (int i = 1; i <= k; i++) { temp.push_back(i); backtrack(temp); if (res.size() == n) return; temp.pop_back(); } } void solve() { cin >> n >> k >> d; long long permu = 1; long long cnt = 0; while (permu < n && cnt < d) { permu *= k; cnt++; } if (cnt == d && permu < n) { cout << -1 << endl; return; } vector<int> tt; backtrack(tt); for (int i = 0; i < d; i++) { for (int j = 0; j < res.size(); j++) { cout << res[j][i] << ; } cout << endl; } } int main() { pls(); solve(); return 0; }
|
// Author: Hugues CREUSY
// February 2004
// Verilog model
// project: M25P40 25 MHz,
// release: 1.1
// These Verilog HDL models are provided "as is" without warranty
// of any kind, included but not limited to, implied warranty
// of merchantability and fitness for a particular purpose.
`timescale 1ns/1ns
`include "parameter.v"
module memory_access (add_mem, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, data_to_write, page_add_index, data_to_read);
input[(`NB_BIT_ADD_MEM - 1):0] add_mem;
input be_enable;
input se_enable;
input add_pp_enable;
input pp_enable;
input read_enable;
input data_request;
input[(`NB_BIT_DATA - 1):0] data_to_write;
input[(`LSB_TO_CODE_PAGE-1):0] page_add_index;
output[(`NB_BIT_DATA - 1):0] data_to_read;
reg[(`NB_BIT_DATA - 1):0] data_to_read;
reg[(`NB_BIT_DATA - 1):0] p_prog[0:(`PLENGTH-1)];
reg[(`NB_BIT_DATA - 1):0] content[0:`TOP_MEM];
reg[`BIT_TO_CODE_MEM - 1:0] cut_add;
integer i;
integer deb_zone;
integer int_add;
integer int_add_mem;
parameter initfile = "initM25P40.txt"; // Modification introduced on 14/11/02
//to create default initialization file
initial
begin
cut_add = 0;
deb_zone = 0;
int_add = 0;
int_add_mem = `BIT_TO_CODE_MEM ;
//-------------------------------
// initialisation of memory array
//-------------------------------
$display("%t : NOTE : Load memory with Initial content",$realtime);
$readmemh(initfile, content);
$display("%t : NOTE : Initial Load End",$realtime);
for(i = 0; i <= (`PLENGTH-1); i = i + 1)
begin
p_prog[i] = 8'b11111111 ;
end
end
//--------------------------------------------------
// PROCESS MEMORY
//--------------------------------------------------
always
begin
@(negedge add_pp_enable )
for(i = 0; i <= (`PLENGTH-1); i = i + 1)
begin
p_prog[i] = 8'b11111111 ;
end
end
always
begin
@(page_add_index)
if ($time != 0)
begin
if (page_add_index !== 8'bxxxxxxxx)
begin
if (add_pp_enable == 1'b1 && pp_enable == 1'b0)
begin
p_prog[page_add_index] <= data_to_write ;
end
end
end
end
always
@(posedge se_enable or posedge read_enable or add_pp_enable)
if ($time != 0)
begin
for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
begin
cut_add[i] = add_mem[i];
end
end
wire #1 delayed_data_request = data_request;
always
@(posedge delayed_data_request)
if ($time != 0)
begin
if (read_enable)
begin
int_add = cut_add;
//---------------------------------------------------------
// Read instruction
//---------------------------------------------------------
if (int_add > `TOP_MEM)
begin
for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1)
begin
cut_add[i] = 1'b0;
end
int_add = 0; // roll over at the end of mem array
end
data_to_read <= content[int_add] ;
//cut_add <= cut_add + 1; // next address
end
end
always
@(negedge data_request)
if ($time != 0)
begin
cut_add <= cut_add+1;
end
always
@(negedge read_enable)
if ($time != 0)
begin
for(i = 0; i <= `NB_BIT_DATA - 1; i = i + 1)
begin
data_to_read[i] <= 1'b0 ;
end
end
//--------------------------------------------------------
// Page program instruction
// To find the first adress of the memory to be programmed
//--------------------------------------------------------
always
@(add_pp_enable)
if (add_pp_enable == 1'b1)
begin
int_add_mem = cut_add;
int_add = `TOP_MEM + 1;
while (int_add > int_add_mem)
begin
int_add = int_add - `PLENGTH ;
end
end
//----------------------------------------------------
// Sector erase instruction
// To find the first adress of the sector to be erased
//----------------------------------------------------
always
@(posedge se_enable)
begin
int_add = cut_add & `MASK_SECTOR ;
end
//----------------------------------------------------
// Write or erase cycle execution
//----------------------------------------------------
always
@(posedge pp_enable)
if ($time != 0) // to avoid any corruption at initialization of variables
begin
for(i = 0; i <= (`PLENGTH - 1); i = i + 1)
begin
content[int_add + i] = p_prog[i] & content[int_add + i];
end
end
always
@(negedge be_enable)
if ($time != 0) // to avoid any corruption at initialization of variables
begin
for(i = 0; i <= `TOP_MEM; i = i + 1)
begin
content[i] = 8'b11111111;
end
end
always
@(negedge se_enable)
if ($time != 0) // to avoid any corruption at initialization of variables
begin
for(i = int_add; i <= (int_add + (`SSIZE / `NB_BIT_DATA) - 1); i = i + 1)
begin
content[i] = 8'b11111111;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void setIO(string s = ) { ios_base::sync_with_stdio(0); cin.tie(0); if ((int)s.size()) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } } int main() { setIO(); int n; string s; cin >> n >> s; string result; result += s[0]; for (int i = 1; i < n; i++) { if (i % 2) { result = s[i] + result; } else { result += s[i]; } } if (n % 2) { cout << result << endl; } else { reverse((result).begin(), (result).end()); cout << result << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9; const int maxN = 1.1e4; vector<int> g[maxN]; map<string, int> m[maxN]; int len = 1; void add(int v, string s) { if (m[v][s] == 0) { m[v][s] = len; g[v].push_back(len); len++; } } void parse(string s) { s = s + ; string cur; int v = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == && cur.size()) { add(v, cur); v = m[v][cur]; cur = ; } else { cur.push_back(s[i]); } } cout << endl; } int mx[2]; pair<int, int> dfs(int v, int d) { pair<int, int> ans = {0, g[v].size() == 0}; for (auto u : g[v]) { pair<int, int> p = dfs(u, d + 1); ans.first += p.first; ans.second += p.second; } if (d >= 2) { mx[0] = max(mx[0], ans.first); mx[1] = max(mx[1], ans.second); } if (g[v].size()) ans.first++; return ans; } int main() { string s; while (cin >> s) { parse(s); } dfs(0, 0); cout << mx[0] << << mx[1] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void getar(T a, int n, int m) { for (int i = 0; i < n; i++) for (int j = 0; j < m; ++j) { scanf( %d , &a[i][j]); } } inline void getar(int *a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %d , a + ii); } } inline void getar(pair<int, int> *a, int n) { for (int ii = 0; ii < n; ii++) { scanf( d , &a[ii].first, &a[ii].second); } } inline void getar(long long *a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %I64d , a + ii); } } inline void getv(vector<int> &a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %d , &a[ii]); } } inline void getv(vector<long long> &a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %I64d , &a[ii]); } } inline void getv(vector<pair<int, int> > &a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %d , &a[ii].first, &a[ii].second); } } inline void getv(vector<pair<long long, long long> > &a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %I64d , &a[ii].first, &a[ii].second); } } inline void getvv(vector<vector<int> > &a, int n, int m) { for (int i = 0; i < n; i++) for (int j = 0; j < m; ++j) { scanf( %d , &a[i][j]); } } inline void printa(int *a, int i, int j) { for (int ii = i; ii <= j; ii++) { printf( %d , a[ii]); } } inline void printa(long long *a, int i, int j) { for (int ii = i; ii <= j; ii++) { printf( %I64d , a[ii]); } } inline void printv(vector<int> &a, int i, int j) { for (int ii = i; ii <= j; ii++) { printf( %d , a[ii]); } } inline void printv(vector<long long> &a, int n, int i, int j) { for (int ii = i; ii <= j; ii++) { printf( %I64d , a[ii]); } } inline long long max(long long a, long long b) { return (a > b) ? a : b; } inline int max(int a, int b) { return (a > b) ? a : b; } inline double max(double a, double b) { return (a > b) ? a : b; } inline long long max(long long a, long long b, long long c) { return max(a, max(b, c)); } inline int max(int a, int b, int c) { return max(a, max(b, c)); } inline double max(double a, double b, double c) { return max(a, max(b, c)); } inline long long min(long long a, long long b) { return (a < b) ? a : b; } inline int min(int a, int b) { return (a < b) ? a : b; } inline double min(double a, double b) { return (a < b) ? a : b; } inline long long min(long long a, long long b, long long c) { return min(a, min(b, c)); } inline int min(int a, int b, int c) { return min(a, min(b, c)); } inline double min(double a, double b, double c) { return min(a, min(b, c)); } inline long long pow(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res *= x; x *= x; n >>= 1; } return res; } inline long long powmod(long long x, long long n, long long _mod) { long long res = 1; while (n) { if (n & 1) res = (res * x) % _mod; x = (x * x) % _mod; n >>= 1; } return res; } inline long long gcd(long long a, long long b) { long long t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } inline int gcd(int a, int b) { int t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } inline long long lcm(int a, int b) { return a / gcd(a, b) * (long long)b; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long gcd(long long a, long long b, long long c) { return gcd(gcd(a, b), c); } inline int gcd(int a, int b, int c) { return gcd(gcd(a, b), c); } inline long long lcm(long long a, long long b, long long c) { return lcm(lcm(a, b), c); } inline long long lcm(int a, int b, int c) { return lcm(lcm(a, b), (long long)c); } inline int bits_count(int v) { v = v - ((v >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); return ((v + (v >> 4) & 0xF0F0F0F) * 0x1010101) >> 24; } inline int bits_count(long long v) { long long t = v >> 32; long long p = (v & ((1LL << 32) - 1)); return bits_count(t) + bits_count(p); } inline bool ispow2(int x) { return (x != 0 && (x & (x - 1)) == 0); } const char nl = n ; string s; int n, k; string rgb; vector<vector<int> > dp; void intialize_dp() { for (int i = 0; i < 3; i++) for (int j = 0; j < k; j++) dp[i][0] += (s[j] != rgb[(j + i) % 3]); } void solve() { rgb = RGB ; cin >> n >> k; cin >> s; dp = vector<vector<int> >(3, vector<int>(n, 0)); intialize_dp(); bool prev_first, cur_last; int ans = min(dp[0][0], dp[1][0], dp[2][0]); for (int i = 0; i < 3; i++) for (int j = 1; j < n - k + 1; j++) { prev_first = (s[j - 1] != rgb[(j - 1 + i) % 3]); cur_last = (s[j + k - 1] != rgb[(j + i + k - 1) % 3]); dp[(i + j) % 3][j] = dp[(i + j - 1) % 3][j - 1] + cur_last - prev_first; ans = min(ans, dp[(i + j) % 3][j]); } cout << ans << nl; } int main() { clock_t clk = clock(); cerr << Hey P.. n ; int t; cin >> t; while (t--) solve(); cerr << Look at the sky. n ; cerr << Time (in ms): << (double)(clock() - clk) * 1000.0 / CLOCKS_PER_SEC << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A222O_PP_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double d, h, v, e; cin >> d >> h >> v >> e; double ans = 3.14159265359 * d * d * h / (4 * v - 3.14159265359 * d * d * e); if (ans < 0) cout << NO << n ; else { cout.precision(17); cout << YES << n << ans << n ; } }
|
#include <bits/stdc++.h> template <typename T> inline void read(T &x) { char c; bool nega = 0; while ((!isdigit(c = getchar())) && (c != - )) ; if (c == - ) { nega = 1; c = getchar(); } x = c - 48; while (isdigit(c = getchar())) x = x * 10 + c - 48; if (nega) x = -x; } template <typename T> inline void writep(T x) { if (x > 9) writep(x / 10); putchar(x % 10 + 48); } template <typename T> inline void write(T x) { if (x < 0) { putchar( - ); x = -x; } writep(x); putchar( ); } template <typename T> inline void writeln(T x) { write(x); putchar( n ); } using namespace std; int u, v, l, r; vector<pair<int, int> > ans; map<pair<int, int>, bool> dd; int main() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); cin >> u >> v; int up = 1, down = u; l = 1, r = v; while (up <= down) { if (l == 1) { for (int i = (1); i <= (v); ++i) { ans.push_back(make_pair(up, l)); ++l; ans.push_back(make_pair(down, r)); --r; } ++up; --down; --l; ++r; } else { for (int i = (1); i <= (v); ++i) { ans.push_back(make_pair(up, l)); --l; ans.push_back(make_pair(down, r)); ++r; } ++up; --down; ++l; --r; } } for (auto v : ans) { if (dd[v]) continue; dd[v] = 1; cout << v.first << << v.second << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b; cin >> n; if (n == 1) { cout << 9 8 << endl; } else { cout << n * 3 << << n * 2 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& i : v) is >> i; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto& i : v) os << i << ; return os; } long long mystoi(string str) { stringstream ss(str); long long ans = 0; ss >> ans; return ans; } long long exp(long long x, long long ex) { long long ans = 1ll; while (ex > 0) { if (ex & 1ll) ans = (ans * x); ex >>= 1ll; x = (x * x); } return ans; } bool sort_cond(const pair<long long, long long>& a, const pair<long long, long long>& b) { if (a.first == b.first) return a.second < b.second; return a.first < b.first; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; long long lo; while (t--) { long long n; cin >> n; vector<long long> a(2 * n); cin >> a; vector<long long> o, e; for (long long i = (0); i < (long long)(2 * n); i++) { if (a[i] % 2) o.push_back(i + 1); else e.push_back(i + 1); } long long cnt = 0; if (o.size() % 2) o.pop_back(); if (e.size() % 2) e.pop_back(); if (o.size() > e.size()) { for (long long i = (0); i < (long long)(o.size()); i++) { if (cnt == n - 1) break; cout << o[i] << << o[i + 1] << endl; cnt++; i++; } for (long long i = (0); i < (long long)(e.size()); i++) { if (cnt == n - 1) break; cout << e[i] << << e[i + 1] << endl; cnt++; i++; } } else { for (long long i = (0); i < (long long)(e.size()); i++) { if (cnt == n - 1) break; cout << e[i] << << e[i + 1] << endl; cnt++; i++; } for (long long i = (0); i < (long long)(o.size()); i++) { if (cnt == n - 1) break; cout << o[i] << << o[i + 1] << endl; cnt++; i++; } } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_4_V
`define SKY130_FD_SC_HD__O22A_4_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_1_V
`define SKY130_FD_SC_LP__O41A_1_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_1 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_1 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_1_V
|
#include <bits/stdc++.h> using namespace std; string s[2005]; char str[2005][2005]; int a[2005][2005]; int v[2005][2005]; long long dp[8005][2005]; int pool[8005], top = 0; int child[8005]; int ID = 0, n; int getID() { return pool[--top]; } void pre() { for (int i = 8000; i >= 0; i--) pool[top++] = i; } void delID(int x) { pool[top++] = x; } int K; int combine(int me, int you, int D) { int ret = getID(); child[ret] = min(K, child[me] + child[you]); for (int i = 0; i <= child[ret]; i++) dp[ret][i] = 0; for (int i = 0; i <= child[me]; i++) for (int j = 0; j <= child[you] && i + j <= K; j++) dp[ret][i + j] = max(dp[ret][i + j], dp[me][i] + dp[you][j] + i * j * D); return ret; } int go(int L, int R, int D) { int me = getID(); int c = 0; while (L <= R && str[L][D] == 0 ) ++c, ++L; child[me] = c; for (int i = 0; i <= c; i++) dp[me][i] = i * (i - 1) / 2 * D; for (int i = L, j = L; i <= R; i = j) { for (j = i; j <= R && str[i][D] == str[j][D]; j++) ; int you = go(i, j - 1, D + 1); int nxt = combine(me, you, D); delID(me); delID(you); me = nxt; } return me; } int main(void) { pre(); scanf( %d%d , &n, &K); for (int i = 1; i <= n; i++) cin >> s[i]; sort(s + 1, s + 1 + n); for (int i = 1; i <= n; i++) strcpy(str[i], s[i].c_str()); int me = go(1, n, 0); printf( %I64d n , dp[me][K]); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* use_dsp48 = "yes" *) module matrix_mult_mac_mdEe_DSP48_1(
input clk,
input rst,
input ce,
input [8 - 1:0] in0,
input [8 - 1:0] in1,
input [16 - 1:0] in2,
output [16 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
reg signed [43 - 1:0] m_reg;
reg signed [25 - 1:0] a_reg;
reg signed [18 - 1:0] b_reg;
assign a = $signed(in0);
assign b = $signed(in1);
assign c = $signed(in2);
assign m = a_reg * b_reg;
assign p = m_reg + c;
always @(posedge clk) begin
if (ce) begin
m_reg <= m;
a_reg <= a;
b_reg <= b;
end
end
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module matrix_mult_mac_mdEe(
clk,
reset,
ce,
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
matrix_mult_mac_mdEe_DSP48_1 matrix_mult_mac_mdEe_DSP48_1_U(
.clk( clk ),
.rst( reset ),
.ce( ce ),
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll MOD = 1e9 + 7, N = 1e5 + 10; int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); ll a[3]; cin >> a[0] >> a[1] >> a[2]; cout << First << endl; vector<ll> b(3); iota(b.begin(), b.end(), 0); sort(b.begin(), b.end(), [&](ll u, ll v) { return a[u] < a[v]; }); sort(a, a + 3); cout << 2 * a[2] - a[1] - a[0] << endl; ll x; cin >> x; --x; if (x == -1) return 0; if (x == b[0]) { cout << a[2] - a[1] << endl; cin >> x; return 0; } else if (x == b[1]) { cout << a[2] - a[0] << endl; cin >> x; return 0; } cout << 6 * a[2] - 3 * a[1] - 3 * a[0] << endl; cin >> x; --x; if (x == -1) return 0; if (x == b[0]) { cout << 3 * a[2] - a[0] - a[1] - a[1] << endl; cin >> x; return 0; } cout << 3 * a[2] - a[0] - a[1] - a[0] << endl; cin >> x; return 0; }
|
module alu16(
input clk,rst,
input [2:0] operator, // will depend on operatorSize
input [15:0] op1,op2,
output reg [15:0] out, status
);
`define numBits 16
`define operatorSize 4
//wire [0:`operatorSize - 1] operator;
//wire signed [0:`numBits - 1] op1,op2;
//reg [0:`numBits - 1] out, status;
//wire [15:0] mult_out;
//mult mult0 (op1,op2,mult_out);
always@(*) begin
if(rst == 1'b0) begin
out <= `numBits'd0;
end else begin
case(operator)
`operatorSize'h0: // ADD
out <= op1 + op2;
`operatorSize'h1: // SUB
out <= op2 - op1;
`operatorSize'h2: // MULT
out <= (op1 * op2);//mult_out;
`operatorSize'h3: // NAND
out <= ~(op1 & op2);
`operatorSize'h4: // DIV
out <= op1 / op2;
`operatorSize'h5: // MOD
out <= op1 % op2;
`operatorSize'h6: // LESS THAN
out <= op1 < op2;
`operatorSize'h7: // LESS THAN OR EQUAL
out <= op1 <= op2;
default: // NOP
out <= `numBits'd0;
endcase
end
end
always@(posedge clk or negedge rst) begin
if(rst == 1'b0) begin
status = `numBits'd0;
end else begin
status <= out;
end
end
endmodule
|
// Sequential Modules
module latch(
input d,
output reg q,
input clk
);
always @(clk)
q <= d;
endmodule
module flip_flop(
input d,
output reg q,
input clk
);
always @(posedge clk)
q <= d;
endmodule
// Testbenches for sequential logic
// Testbench for Latch
module latch_tb;
reg t_d, t_clk;
wire t_q;
latch tb_latch( .d(t_d), .q(t_q), .clk(t_clk) );
initial
begin
$monitor(t_clk, t_d, t_q);
t_d = 1'b0;
t_clk = 1'b0;
#3 t_d = 1'b1;
#3 t_d = 1'b1;
#3 t_d = 1'b0;
end
always
#5 t_clk = !t_clk;
endmodule
// Testbench for Flip_Flop
module flip_flop_tb;
reg t_d, t_clk;
wire t_q;
flip_flop tb_flip_flop( .d(t_d), .q(t_q), .clk(t_clk) );
initial
begin
$monitor(t_clk, t_d, t_q);
t_d = 1'b0;
t_clk = 1'b0;
#3 t_d = 1'b1;
#3 t_d = 1'b1;
#3 t_d = 1'b0;
end
always
#5 t_clk = !t_clk;
endmodule
// Testbench for both
module top_tb;
reg t_d, t_clk;
wire t_q_latch, t_q_flip_flop;
latch tb_latch( .d(t_d), .q(t_q_latch), .clk(t_clk) );
flip_flop tb_flip_flop( .d(t_d), .q(t_q_flip_flop), .clk(t_clk) );
initial
begin
$monitor(t_clk, t_d, t_q_latch, t_q_flip_flop);
t_d = 1'b0;
t_clk = 1'b0;
#3 t_d = 1'b1;
#3 t_d = 1'b1;
#3 t_d = 1'b0;
end
always
#5 t_clk = !t_clk;
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 200031; int n, m, a[N], b[N]; vector<int> g[N]; int used[N]; int dep[N]; vector<int> this_comp; vector<pair<int, int> > order; vector<pair<int, pair<int, int> > > solution; int par[N]; int in_st[N]; int used_edge[N]; int par_edge[N]; set<int> sons[N]; vector<int> with_dep[N]; vector<int> not_st_list[N]; set<int>::iterator it; void trace(int v) { used[v] = 1; this_comp.push_back(v); for (int i = 0; i < g[v].size(); i++) { int id = g[v][i]; int to = a[id] + b[id] - v; if (used[to]) continue; par[to] = v; sons[v].insert(to); par_edge[to] = id; dep[to] = dep[v] + 1; in_st[id] = 1; trace(to); } } void process_vertex(int v) { vector<int> free_edges; for (int i = 0; i < g[v].size(); i++) { int id = g[v][i]; if (used_edge[id]) continue; if (in_st[id]) continue; free_edges.push_back(id); } while (free_edges.size() > 1) { int a = free_edges.back(); free_edges.pop_back(); int b = free_edges.back(); free_edges.pop_back(); used_edge[a] = 1; used_edge[b] = 1; solution.push_back(make_pair(v, make_pair(a, b))); } if (free_edges.size() == 1) { if (par[v] == 0) { int id = free_edges[0]; used_edge[id] = 1; return; } solution.push_back(make_pair(v, make_pair(par_edge[v], free_edges[0]))); used_edge[par_edge[v]] = 1; used_edge[free_edges[0]] = 1; sons[par[v]].erase(v); return; } } int get_out_of_st(int v) { while (not_st_list[v].size() > 0) { int id = not_st_list[v].back(); if (used_edge[id] == 0) return id; not_st_list[v].pop_back(); } return -1; } void resolve(int v) { if (par[v] == 0) return; if (used_edge[par_edge[v]]) return; if (sons[par[v]].size() > 1) { sons[par[v]].erase(v); it = sons[par[v]].begin(); int othr = (*it); sons[par[v]].erase(othr); used_edge[par_edge[othr]] = 1; used_edge[par_edge[v]] = 1; solution.push_back( make_pair(par[v], make_pair(par_edge[othr], par_edge[v]))); return; } int edge_in_father = get_out_of_st(par[v]); if (edge_in_father != -1) { sons[par[v]].erase(v); solution.push_back( make_pair(par[v], make_pair(par_edge[v], edge_in_father))); used_edge[par_edge[v]] = 1; used_edge[edge_in_father] = 1; return; } if (dep[v] == 1) return; int v2 = par[par[v]]; sons[par[v]].erase(v); sons[v2].erase(par[v]); solution.push_back( make_pair(par[v], make_pair(par_edge[v], par_edge[par[v]]))); used_edge[par_edge[v]] = 1; used_edge[par_edge[par[v]]] = 1; } void solve(int v) { this_comp.clear(); trace(v); int max_dep = 0; for (int i = 0; i < this_comp.size(); i++) { max_dep = max(max_dep, dep[this_comp[i]]); } order.clear(); for (int i = 0; i < this_comp.size(); i++) { int cur_v = this_comp[i]; for (int j = 0; j < g[cur_v].size(); j++) { int e_id = g[cur_v][j]; if (in_st[e_id]) continue; not_st_list[cur_v].push_back(e_id); } order.push_back(make_pair(dep[cur_v], cur_v)); with_dep[dep[cur_v]].push_back(cur_v); } for (int i = max_dep; i >= 0; --i) { for (int j = 0; j < with_dep[i].size(); j++) { int v_id = with_dep[i][j]; process_vertex(v_id); } for (int j = 0; j < with_dep[i].size(); j++) { int v_id = with_dep[i][j]; resolve(v_id); } with_dep[i].clear(); } } int get_other(int id, int v) { return a[id] + b[id] - v; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; cin >> m; for (int i = 1; i <= m; i++) { cin >> a[i] >> b[i]; g[a[i]].push_back(i); g[b[i]].push_back(i); } for (int i = 1; i <= n; i++) { if (used[i]) continue; solve(i); } cout << solution.size() << endl; for (int i = 0; i < solution.size(); i++) { int id1 = solution[i].second.first; int id2 = solution[i].second.second; cout << get_other(id1, solution[i].first) << << solution[i].first << << get_other(id2, solution[i].first) << n ; } cin.get(); cin.get(); return 0; }
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#include <bits/stdc++.h> using namespace std; int n; string s; set<vector<int> > DP[10001]; bool R[4]; int main() { cin >> n; cin >> s; for (int i = 0; i < s.size(); i++) if (s[i] == G ) s[i] = 0 ; else if (s[i] == S ) s[i] = 1 ; else if (s[i] == H ) s[i] = 2 ; else if (s[i] == R ) s[i] = 3 ; vector<int> E(4, 0); DP[0].insert(E); for (int i = 0; i < n; i++) { set<vector<int> >::iterator it; for (it = DP[i].begin(); it != DP[i].end(); it++) { vector<int> T; T = *it; int q = min(T[0], min(T[1], min(T[2], T[3]))); for (int j = 0; j < 4; j++) { if ((s[i] != ? && (j == (s[i] - 0 )) || (s[i] == ? && T[j] == q))) { vector<int> N; N = T; N[j]++; int p = min(N[0], min(N[1], min(N[2], N[3]))); for (int l = 0; l < 4; l++) N[l] -= p; DP[i + 1].insert(N); } } } } set<vector<int> >::iterator it; for (it = DP[n].begin(); it != DP[n].end(); it++) { vector<int> T; T = *it; int q = min(T[0], min(T[1], min(T[2], T[3]))); for (int j = 0; j < 4; j++) if (T[j] == q) R[j] = true; } if (R[0]) cout << Gryffindor << endl; if (R[2]) cout << Hufflepuff << endl; if (R[3]) cout << Ravenclaw << endl; if (R[1]) cout << Slytherin << endl; cin >> n; return 0; }
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