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module i2s_tx #(parameter DATA_WIDTH = 16
) (clk, left_chan, right_chan, sdata, lrclk, mck, sck);
input wire clk; //general clock of project (top level) 50 MHz
input wire [DATA_WIDTH-1:0] left_chan;
input wire [DATA_WIDTH-1:0] right_chan;
output reg sdata; initial sdata <= 1'b0;
//output reg mck; initial mck <= 1'b0;
output wire mck, sck, lrclk;
reg [9:0] mck_div; initial mck_div<=10'd0;
/* тактуем счетчик от 50 мгц
бит - частота
0 - 25.000.000
1 - 12.500.000
2 - 6.250.000
3 - 3.125.000
4 - 1.562.500
5 - 781.250
6 - 390.625
7 - 195.312.5
8 - 97.656.25
9 - 48.828.125
*/
parameter LR_BIT = 7; // 9 for 48 khz; 7 for 195 khz
parameter SCK_BIT = LR_BIT - 6; // lr*64
parameter MCK_BIT = 0;
assign mck = mck_div[MCK_BIT];
assign lrclk = mck_div[LR_BIT];
assign sck = mck_div[SCK_BIT];
reg lrclk_prev; initial lrclk_prev <= 1'b1;
wire lrclk_change = ~(lrclk_prev == lrclk);
reg [DATA_WIDTH-1:0] ch_data; initial ch_data <= {DATA_WIDTH{1'b0}};
reg sck_prev; initial sck_prev <= 1'b0;
wire sck_neg = (sck_prev==1'b1 && sck==1'b0);
reg [31:0] fake_data; initial fake_data <= 32'd0;
wire [31:0] sgnd_data = fake_data - 32'b10000000000000000000000000000000;//saw
//wire [31:0] sgnd_data = (fake_data[31]) ? 32'h00000000 - 32'b10000000000000000000000000000000 : 32'hffffffff - 32'b10000000000000000000000000000000;
always @(posedge clk) begin
mck_div <= mck_div + 1'b1;
lrclk_prev <= lrclk;
sck_prev <= sck;
if (sck_neg) begin
if (lrclk_change) begin
//ch_data <= (lrclk) ? left_chan : right_chan;
ch_data <= sgnd_data;
//fake_data <= fake_data + 32'd44739243; //195 khz -> 4000 hz
//fake_data <= fake_data + 32'd11184811; //195khz -> 1000 hz
fake_data <= fake_data + 32'd178956972; //48 khz -> 4000 hz
end else begin
ch_data <= ch_data << 1;
end
sdata <= ch_data[DATA_WIDTH-1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long read() { char c; long long num, f = 1; while (c = (char)getchar(), !isdigit(c)) if (c == - ) f = -1; num = (long long)(c - 0 ); while (c = (char)getchar(), isdigit(c)) num = num * 10 + (long long)(c - 0 ); return num * f; } long long n, m; vector<long long> a; long long greaterCount(long long m) { vector<long long> s(2 * n + 1); long long sum = n, result = 0, add = 0; s[sum] = 1; for (long long i = 0; i < n; i++) { if (a[i] < m) sum--, add -= s[sum]; else add += s[sum], sum++; result += add; s[sum]++; } return result; } void work() { n = read(); m = read(); a = vector<long long>(n); for (long long i = 0; i < n; i++) a[i] = read(); cout << greaterCount(m) - greaterCount(m + 1) << endl; return; } signed main() { long long T = 1; for (long long Case = 1; Case <= T; Case++) { work(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int N = 5e5; int main() { long long n, a, b, c, t; cin >> n >> a >> b >> c >> t; long long arr[n + 1]; for (long long i = 1; i <= n; i++) { cin >> arr[i]; } long long s = n * a; if (b >= c) { cout << s << endl; } else { long long q = 1; long long s2 = 0; long long q2 = 1; long long s3 = 0; for (long long i = 1; i <= n; i++) { if (arr[i] != t) { s2 += (t - arr[i]) * c; q++; } } for (long long i = 1; i <= n; i++) { arr[i] = a - (t - arr[i]) * b; } for (long long i = 1; i <= n; i++) { s3 += arr[i]; } cout << s2 + s3; } }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2018 Miodrag Milanovic <>
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
wire dummy;
AL_MAP_ADDER #(
.ALUTYPE("ADD_CARRY"))
adder_cin (
.a(CI),
.b(1'b0),
.c(1'b0),
.o({CIx, dummy})
);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
AL_MAP_ADDER #(
.ALUTYPE("ADD")
) adder_i (
.a(AA[i]),
.b(BB[i]),
.c(C[i]),
.o({COx[i],Y[i]})
);
wire cout;
AL_MAP_ADDER #(
.ALUTYPE("ADD"))
adder_cout (
.a(1'b0),
.b(1'b0),
.c(COx[i]),
.o({cout, CO[i]})
);
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
/*************************************************************************
* *
* Copyright (C) 2016,2017 Alves, Fredy. *
* All rights reserved. Email: *
* *
* This design is free software; you can redistribute it and/or *
* modify it under the terms of EITHER: *
* (1) The GNU Lesser General Public License as published by the Free *
* Software Foundation; either version 2.1 of the License, or (at *
* your option) any later version. The text of the GNU Lesser *
* General Public License is included with this design in the *
* file LICENSE. *
* *
* This design is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the files *
* LICENSE.TXT and LICENSE-BSD.TXT for more details. *
* *
*************************************************************************/
module dCalcPointsDistance3
(
input CLK,
input [31:0] a1,
input [31:0] a2,
input [31:0] a3,
input [31:0] b1,
input [31:0] b2,
input [31:0] b3,
input RST,
output [31:0] res,
output reg out_rdy
);
wire CLK2;
wire [31:0] b1_neg;
wire [31:0] b2_neg;
wire [31:0] b3_neg;
wire [31:0] out_add1;
wire output_z_ack_wire;
wire done_add1;
wire input_a_ack_wire;
wire input_b_ack_wire;
wire [31:0] out_add2;
wire output_z_ack_wire1;
wire done_add2;
wire input_a_ack_wire1;
wire input_b_ack_wire1;
wire [31:0] out_add3;
wire output_z_ack_wire2;
wire done_add3;
wire input_a_ack_wire2;
wire input_b_ack_wire2;
wire out_rdy_calclen;
reg resetlen = 1'b1;
assign b1_neg = {~b1[31],b1[30:0]};
assign b2_neg = {~b2[31],b2[30:0]};
assign b3_neg = {~b3[31],b3[30:0]};
assign CLK2 = (done_add1 & done_add2 & done_add3) ? 1:0;
//jtag_debug jtag8(.in_debug(debugtest1));
//
//jtag_debug debug6(.in_debug(out_add2));
//
//jtag_debug debug9(.in_debug(out_add3));
add_comb add1 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa ( a1 ),
.datab ( b1_neg ),
.result ( out_add1 ),
.reset(RST),
.done(done_add1)
);
add_comb add2 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa ( a2 ),
.datab ( b2_neg ),
.result ( out_add2 ),
.reset(RST),
.done(done_add2)
);
add_comb add3 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa ( a3 ),
.datab ( b3_neg ),
.result ( out_add3 ),
.reset(RST),
.done(done_add3)
);
dCalcVectorLength3 calcLen
(
.CLK(CLK),
.a1(out_add1),
.a2(out_add2),
.a3(out_add3),
.b1(out_add1),
.b2(out_add2),
.b3(out_add3),
.RST(resetlen),
.res(res),
.out_rdy(out_rdy_calclen)
);
reg [31:0] debugtest1;
reg debugtest2;
always @(posedge CLK2 or negedge RST or posedge out_rdy_calclen)
begin
if(RST == 1'b0)
begin
resetlen <= 1'b0;
out_rdy <= 1'b0;
end
else
begin
if(CLK2)
begin
resetlen <= 1'b1;
end
if(out_rdy_calclen)
begin
out_rdy <= 1'b1;
debugtest1 <= res;
end
end
end
endmodule
|
module DC_8_databanks #(parameter Width = 36, Size =512, Forward=0, REQ_BITS=7)
// 36 bit data per data bank= 32 bit data+4 bit valid bits
//tag 10+counter 2[19,20]+states 3[21,22,23] =15 for tag bank
//data bank gets pos+ data to write or output data from read
(
input clk
,input reset
,input req_valid
,input write
,input [2:0] bank_sel
,input ack_retry
,input [2:0] way
,input row_even_odd
,input[4:0] req_Index
,input [35:0] req_data //32 bit data+4 bit valid bit
,input [4:0] Load_req
,input Load_req_valid
,output Load_req_retry
,input [6:0] STD_req
,input STD_req_valid
,output STD_req_retry
,input write_musk_reset //when Invalidate
,output ack_valid
,output req_retry
,output [35:0] ack_data //64 bit data output for sign extension
);
logic [4:0] req_Index_add_to_1_bank;
assign req_Index_add_to_1_bank= req_Index;
logic [35:0] req_data_bank=req_data;
logic bank_sel0,write_bank;
logic bank_sel1,bank_sel2,bank_sel3,bank_sel4,bank_sel5,bank_sel6,bank_sel7;
logic [2:0] bank_sel_8bank;
assign bank_sel_8bank=bank_sel;
assign write_bank=write;
always@(bank_sel) begin
bank_sel_8bank=bank_sel;//3 bit select for 8 banks in a bank;VA[1:0] byte selection
end
always@(bank_sel_8bank) begin
case(bank_sel_8bank)
0: begin bank_sel0=1;bank_sel1=0;;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
1: begin bank_sel0=0;bank_sel1=1;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
2: begin bank_sel0=0;bank_sel1=0;bank_sel2=1;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
3: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=1;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
4: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=1;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
5: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=1;bank_sel6=0;bank_sel7=0;end
6: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=1;bank_sel7=0;end
7:begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=1;end
endcase
end
DC_1_databank #(.Width(Width), .Size(Size))
databank0 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel0)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank1 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel1)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank2 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel2)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank3 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel3)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank4 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel4)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank5(
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel5)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank6 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel6)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);DC_1_databank #(.Width(Width), .Size(Size))
databank7 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel7)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
endmodule
|
#include <bits/stdc++.h> int main(void) { int n, m; scanf( %d%d , &n, &m); char c; scanf( %c , &c); int i, j; char word[n + 2][m + 2]; for (i = 0; i < n + 2; i++) for (j = 0; j < m + 2; j++) word[i][j] = W ; int v[n + 1], h[m + 1]; for (i = 0; i <= n; i++) v[i] = 0; for (j = 0; j <= m; j++) h[j] = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { scanf( %c , &word[i][j]); if (word[i][j] == B ) { v[i] += 1; h[j] += 1; } } scanf( %c , &c); } int left = m + 1, right = 0; for (j = 1; j <= m; j++) { if ((h[j] > 0) && (j < left)) left = j; if ((h[j] > 0) && (j > right)) right = j; } int up = 0, down = n + 1; for (i = 1; i <= n; i++) { if ((v[i] > 0) && (i > up)) up = i; if ((v[i] > 0) && (i < down)) down = i; } int notTrue = 0; for (i = down; i <= up; i++) { if (v[i] == 0) notTrue = 1; else { int black = 0; for (j = left; j <= right; j++) { if ((word[i][j] == B ) && (black == 0)) black = 1; if ((word[i][j] == W ) && (black == 1)) black = 2; if ((word[i][j] == B ) && (black == 2)) notTrue = 1; } } } for (j = left; j <= right; j++) { if (h[j] == 0) notTrue = 1; else { int black = 0; for (i = down; i <= up; i++) { if ((word[i][j] == B ) && (black == 0)) black = 1; if ((word[i][j] == W ) && (black == 1)) black = 2; if ((word[i][j] == B ) && (black == 2)) notTrue = 1; } } } while (up > down) { int lv = right, pv = left, ln = right, pn = left; for (j = left; j <= right; j++) { if ((word[up][j] == B ) && (lv > j)) lv = j; if ((word[up][j] == B ) && (pv < j)) pv = j; if ((word[down][j] == B ) && (ln > j)) ln = j; if ((word[down][j] == B ) && (pn < j)) pn = j; } if (lv > ln) lv = ln; if (ln > lv) ln = lv; if (pn < pv) pn = pv; if (pv < pn) pv = pn; if (((word[up][ln] == W ) && (word[up][pn] == B ) && (word[down][lv] == B ) && (word[down][pv] == W )) || ((word[down][lv] == W ) && (word[down][pv] == B ) && (word[up][ln] == B ) && (word[up][pn] == W ))) notTrue = 1; --up; ++down; } if (notTrue == 0) { printf( YES ); } else { printf( NO ); } return 0; }
|
/*!
* \file norm.v
* \brief Hardware normalization core
* \author Luca Maggiani, Cedric Bourrasset
*
* \version v0.1 (23Mar15) Initial release
* \date Mar 2015
* \param[in] in_fv, in_dv, in_data
* \param[out] out_fv, out_dv, out_data
*/
module norm(
clk_proc,
reset_n,
in_fv,
in_dv,
in_data,
out_fv,
out_dv,
out_data,
addr_rel_i,
wr_i,
datawr_i,
rd_i,
datard_o
);
/* Flows size */
parameter IN_SIZE = 16;
parameter OUT_SIZE = 16;
/* Clock param */
parameter CLK_PROC_FREQ = 50000000;
localparam NWORDS = 8;
localparam NPIPELINE = 10;
input clk_proc;
input reset_n;
input in_fv;
input in_dv;
input [IN_SIZE-1:0] in_data;
output out_fv;
output out_dv;
output [OUT_SIZE-1:0] out_data;
input addr_rel_i;
input wr_i;
input [31:0] datawr_i;
input rd_i;
output [31:0] datard_o;
wire dv_s;
wire acc_clear;
wire [23:0] shiftout_ext;
wire [IN_SIZE-1:0] shiftout;
reg [5:0] counter;
reg [18:0] acc;
reg [18:0] acc_d;
reg fsm, fsm_new;
/* Data valid gating */
assign dv_s = (in_fv & in_dv) | (out_fv & ~in_fv);
altshift_taps #(
.lpm_hint("RAM_BLOCK_TYPE=AUTO"),
.lpm_type("altshift_taps"),
.number_of_taps(1),
.tap_distance(NWORDS),
.width(IN_SIZE)
) altshift_taps_inst_0 (
.clock (clk_proc),
.clken (dv_s),
.shiftin (in_data),
.shiftout (shiftout),
.taps ()
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
/* counter reaches 7 */
assign acc_clear = (counter == 5'd7);
/* Counter (ACC control) */
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 1'b0)
counter <= 0;
else
if (acc_clear | ~in_fv)
counter <= 0;
else
if(dv_s)
counter <= counter + 1'b1;
else
counter <= counter;
/* Accumulator */
always@(posedge clk_proc or negedge reset_n)
begin
if (reset_n == 1'b0)
acc <= 0;
else
if(acc_clear)
acc <= 0;
else
if (dv_s)
acc <= acc + in_data;
else
acc <= acc;
end
/* acc_token */
wire shift_dv;
reg [7:0] acc_token;
always@(posedge clk_proc or negedge reset_n)
begin
if(reset_n == 1'b0)
acc_token <= {8{1'b0}};
else
if(dv_s)
acc_token[7:0] <= {acc_token[6:0], in_dv};
else
acc_token <= acc_token;
end
assign shift_dv = acc_token[7];
/* Registered accumulator value */
always@(posedge clk_proc or negedge reset_n)
begin
if (reset_n == 1'b0)
acc_d <= 0;
else
if(acc_clear)
if (acc)
acc_d <= acc + in_data;
else
acc_d <= 1;
else
acc_d <= acc_d;
end
/* Pre-normalisation compute */
assign shiftout_ext = {shiftout, 8'd0};
/* div_token distribution */
reg [NPIPELINE-1:0] div_token;
always@(posedge clk_proc or negedge reset_n)
begin
if(reset_n == 1'b0)
div_token <= {NPIPELINE{1'b0}};
else
if (dv_s)
div_token[NPIPELINE-1:0] <= {div_token[NPIPELINE-2:0], shift_dv};
else
div_token <= div_token;
end
assign out_dv = div_token[NPIPELINE-1] & dv_s;
/* Pipelined Divisor */
wire [23:0] out_div;
lpm_divide #(
.lpm_type("lpm_divide"),
.lpm_widthn(24),
.lpm_widthd(19),
.lpm_nrepresentation("UNSIGNED"),
.lpm_drepresentation("UNSIGNED"),
.lpm_pipeline(NPIPELINE),
.lpm_hint("LPM_REMAINDERPOSITIVE=TRUE")
) lpm_divide_inst (
.quotient(out_div),
.remain(),
.numer(shiftout_ext),
.denom(acc_d),
.clock(clk_proc),
.clken((shift_dv | div_token[NPIPELINE-1]) & dv_s),
.aclr(1'b0)
);
assign out_data = {8'd0, out_div[7:0]- out_div[8]} ;
/* Output signals generations */
localparam FVTOKEN = NPIPELINE+8;
reg [FVTOKEN-1:0] fv_token;
always@(posedge clk_proc or negedge reset_n)
begin
if(reset_n == 1'b0)
fv_token <= {FVTOKEN{1'b0}};
else
if (dv_s)
fv_token <= {fv_token[FVTOKEN-2:0], in_fv};
else
fv_token <= fv_token;
end
assign out_fv = fv_token[FVTOKEN-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRBP_PP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_PP_BLACKBOX_V
|
`include "defines.v"
`include "nodeRouter.v"
`timescale 1ns/1ps
/*
input `control_w port0_ci,
input `control_w port1_ci,
input `control_w portl0_ci,
input `control_w portl1_ci,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_co,
output `control_w port1_co,
output `control_w portl0_co,
output `control_w portl1_co,
*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
nodeRouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.portl0_ci(144'h0), .portl0_co(portl0_co),
.portl1_ci(144'h0), .portl1_co(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0aaaaaaaaaabcdef0123456789abcdef1857;
flit1c = 144'h11111111111bcdef0123456789abcdef1854;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
#1;
clk = 1;
#1;
clk = 0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
#1;
clk = 1;
#1;
clk = 0;
//flit1c = 144'h0123456789abcdef0123456789abcdef1852;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_SYMBOL_V
`define SKY130_FD_SC_LP__DLXTN_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n; cin >> n; int cnt = 0; int jump = 1; int arr[n]; for (int k = 1; k <= n; k++) { arr[k] = k; } for (i = 1; i <= n * n; i++) { jump += i; if (jump <= n) { cout << arr[jump] << ; } else { cout << arr[jump % n] << ; } cnt++; if (cnt == n - 1) { break; } } }
|
/*
* Simple 8-bit FPGA softcore CPU.
* Copyright (C) 2015 P. Heinonen.
* Licensed under the MIT License. For more details, read the LICENSE file.
*
* compiler: Icarus Verilog 0.9.7
* Timing analysis with GTKWave
*
*/
module waterbear(
input clk,
input rst,
output[7:0] PC);
// Control Unit stages
// Classic RISC type pipeline without MEM stage
parameter IF=2'b00;
parameter ID=2'b01;
parameter EX=2'b10;
parameter WB=2'b11;
// index for memcopy in store step
integer i;
// Control Unit registers
reg[1:0] control_unit_current;
reg[1:0] control_unit_next;
// mnemonics of opcodes
parameter LDR = 4'b001; // load
parameter STR = 4'b010; // store
parameter ADD = 4'b011; // add
parameter SUB = 4'b100; // substract
parameter EQU = 4'b101; // compare equal
parameter JMP = 4'b110; // jump
parameter HLT = 4'b111; // halt
// memory structure
reg[15:0] MEM[0:255]; // Main Memory - 16 bit wide 256 memory cells
reg[5:0] WORKMEM[0:127]; // ALU intermediate register
reg[5:0] DESTMEM[0:127]; // destination register
reg[5:0] R1; // accumulator
reg[7:0] PC; // program counter
reg[7:0] MAR; // Memory Address register
reg[15:0] MDR; // Memory Data/Buffer Register
reg[15:0] CIR; // Current Instruction Register
// instruction set structure
reg[4:0] reserved = 5'b00000;
reg[3:0] op_code = 0;
reg numbit = 0;
reg[5:0] operand = 0;
/*
RAM memory layout contains 256 memorycells which are 16-bit wide
to store instruction set.
+-----5----+---4----+---1----+---6-----+
INSTRUCTION SET | | | | |
STRUCTURE | RESERVED | OPCODE | NUMBIT | OPERAND |
| | | | |
+----------+--------+--------+---------+
*/
// initial cpu bootup
initial begin
// initialize memory and registers
init_regs();
// memory initialization for testbench
// Sample program calculates equation: x=5+7;
/*
MEM[0] = {reserved, LDR, 1'b1, 6'b000101}; //Load value 5 into R1, mcode: 00000 001 1 000010
MEM[1] = {reserved, STR, 1'b0, 6'b001101}; //Store value from R1 in memory addr 13
MEM[2] = {reserved, LDR, 1'b1, 6'b000111}; //Load value 7 into R1
MEM[3] = {reserved, STR, 1'b0, 6'b001110}; //Store value from R1 in memory addr 14
MEM[4] = {reserved, LDR, 1'b0, 6'b001101}; //Load value from memory addr 13 into R1
MEM[5] = {reserved, ADD, 1'b0, 6'b001110}; //Add value from memory addr 14 to R1
MEM[6] = {reserved, STR, 1'b0, 6'b000010}; //Store value from R1 into memory addr 15
MEM[7] = {reserved, HLT, 1'b0, 6'b000000}; //Stop execution
*/
// Sample program: Counter to count from 0 to some user coded limit, here 5.
MEM[0] = {reserved, LDR, 1'b1, 6'b000101}; //set count value to 5
MEM[1] = {reserved, STR, 1'b0, 6'b001111}; //store count value to address 15
MEM[2] = {reserved, LDR, 1'b1, 6'b000000}; //initialize count to zero
MEM[3] = {reserved, EQU, 1'b0, 6'b001111}; //check if count is complete, if yes skip next
MEM[4] = {reserved, JMP, 1'b1, 6'b000110}; //set PC to 6
MEM[5] = {reserved, HLT, 1'b0, 6'b000000}; //stop program
MEM[6] = {reserved, ADD, 1'b1, 6'b000001}; //increment counter in accumulator
MEM[7] = {reserved, JMP, 1'b1, 6'b000011}; //set PC to 3
end
// clock cycles
always @ (clk, rst) begin
if(rst) begin
init_regs();
end
else begin
// Control Unit Finite state machine
case(control_unit_current)
IF: begin
MAR = PC;
PC = PC +1;
MDR = MEM[MAR];
CIR = MDR;
control_unit_next=ID;
end
ID: begin
control_unit_next=EX;
InstructionDecoder(CIR, op_code, numbit, operand);
end
EX: begin
// execute ALU instructions
case(op_code)
LDR: begin
if(numbit==1) begin
R1 = operand; // direct assign
end else begin
R1 = WORKMEM[operand]; // assign from address
end
control_unit_next=WB;
end
STR: begin
WORKMEM[operand] = R1;
control_unit_next=WB;
end
ADD: begin
if(numbit==1) begin
R1=R1+operand;
end else begin
R1=R1+WORKMEM[operand];
end
control_unit_next=WB;
end
JMP : begin
PC=operand;
control_unit_next=WB;
end
EQU: begin
if(R1 == WORKMEM[operand]) begin
PC=PC+1;
end
control_unit_next=WB;
end
HLT: begin
control_unit_next=EX; // continue loop
end
default: begin end
endcase
end // end of execute ALU instructions
WB: begin
// Loop is synthesizable:
// http://www.lcdm-eng.com/papers/snug13_SNUG-SV-2013_Synthesizable-SystemVerilog_paper.pdf
for (i=0; i<127; i=i+1 ) begin
DESTMEM[i] <= WORKMEM[i];
end
control_unit_next=IF;
end
default: begin end
endcase
control_unit_current=control_unit_next;
end
end
// task to initialize registers and memory
task init_regs;
begin
PC = 0;
R1 = 0;
MDR = 0;
MAR = 0;
CIR = 0;
//WORKMEM = 0; //{0,128'h80};
//DESTMEM = 0; //{0,128'h80};
control_unit_current = IF;
numbit = 0;
operand = 0;
op_code = 0;
reserved = 0;
end
endtask
// in execute, Control Unit
task InstructionDecoder;
input[15:0] CIR;
output[3:0] op_code;
output numbit;
output[5:0] operand;
begin
op_code= CIR[10:7];
numbit=CIR[6:6];
operand=CIR[5:0];
end
endtask
endmodule
// For the test 4 core test
module multicore(
input clk,
input rst,
output[7:0] PC);
waterbear core1(clk, reset, PC);
waterbear core2(clk, reset, PC);
waterbear core3(clk, reset, PC);
waterbear core4(clk, reset, PC);
endmodule
|
// Copyright (c) 2013, Simon Que
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// SPI memory interface.
`include "spi_memory.vh"
module SPIMemory(_select, sck, mosi, miso,
addr, data_out, data_in, rd, wr,
);
// SPI interface.
input _select, sck, mosi;
output miso;
// Memory interface.
output [`SPI_MEM_ADDR_WIDTH-1:0] addr;
input [`SPI_MEM_DATA_WIDTH-1:0] data_in;
output [`SPI_MEM_DATA_WIDTH-1:0] data_out;
output rd, wr;
reg [`BYTE_COUNTER_WIDTH-1:0] spi_counter;
reg [`BYTE_WIDTH-1:0] spi_data;
// Upper and lower address bytes.
reg [`BYTE_WIDTH-1:0] spi_addr_0;
reg [`BYTE_WIDTH-1:0] spi_addr_1;
// Read in data from MOSI.
always @ (posedge sck)
if (~_select)
spi_data <= {spi_data[`BYTE_WIDTH-2:0], mosi};
// Read at the start of a byte, before the rising edge of SCK.
assign rd = (spi_counter == 0) & (spi_state == `SPI_MEM_STATE_DATA_READ);
// Write at the end of a byte.
assign wr = (spi_counter == `BYTE_WIDTH-1) &
(spi_state == `SPI_MEM_STATE_DATA_WRITE);
// Connect memory address and data buses.
assign addr = {spi_addr_1, spi_addr_0};
assign data_out = spi_data;
// Register for reading data in.
reg [`SPI_MEM_DATA_WIDTH-1:0] read_data;
always @ (posedge sck) // Store the old data at the start of a new byte.
if (spi_counter == 0)
read_data <= data_in;
// Clock out data to MISO.
assign miso = (spi_counter == 0) ? data_in[`BYTE_WIDTH - 1]
: read_data[`BYTE_WIDTH - 1 - spi_counter];
// SPI memory interface state machine.
reg [`SPI_MEM_STATE_WIDTH-1:0] spi_state;
// Previous state is used to detect transition from address to data bytes.
reg [`SPI_MEM_STATE_WIDTH-1:0] spi_prev_state;
// This bit indicates that the current operation is a write operation.
reg write_op;
always @ (posedge _select or negedge sck) begin
// Reset logic.
if (_select) begin
// Reset the state when nSS goes low.
spi_state <= `SPI_MEM_STATE_ADDR_H;
spi_prev_state <= `SPI_MEM_STATE_ADDR_H;
spi_counter <= 1'b0;
write_op <= 0;
end else begin
// Falling edge of SCK means increment to next bit.
if (spi_counter == `BYTE_WIDTH - 1) begin
case (spi_state)
`SPI_MEM_STATE_ADDR_H:
begin
spi_state <= `SPI_MEM_STATE_ADDR_L;
// Mask out the highest bit, which indicates read or write.
spi_addr_1 <= {1'b0, spi_data[`BYTE_WIDTH-2:0]};
write_op <= spi_data[`BYTE_WIDTH-1];
end
`SPI_MEM_STATE_ADDR_L:
begin
spi_state <= write_op ? `SPI_MEM_STATE_DATA_WRITE
: `SPI_MEM_STATE_DATA_READ;
spi_addr_0 <= spi_data;
end
`SPI_MEM_STATE_DATA_READ:
begin
// Increment the address after writing a byte. Be sure to mask out
// the highest bit.
spi_addr_0 <= spi_addr_0 + 1'b1;
if (spi_addr_0 == {`BYTE_WIDTH{1'b1}})
spi_addr_1 <= (spi_addr_1 + 1'b1) & {(`BYTE_WIDTH-1){1'b1}};
end
endcase
// Save the previous state.
spi_prev_state <= spi_state;
end else if (spi_counter == 0 & spi_state == `SPI_MEM_STATE_DATA_WRITE &
spi_prev_state == spi_state) begin
// Increment the address after writing a byte. Be sure to mask out
// the highest bit.
spi_addr_0 <= spi_addr_0 + 1'b1;
if (spi_addr_0 == {`BYTE_WIDTH{1'b1}})
spi_addr_1 <= (spi_addr_1 + 1'b1) & {(`BYTE_WIDTH-1){1'b1}};
end
// Update the counter. It should wrap around on its own.
spi_counter <= spi_counter + 1'b1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
// system_top.v
// Author: Thierry Moreau
// Email:
//-----------------------------------------------------------------------------
module system_top
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP
);
`include "macros.inc"
`include "params.inc"
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB;
input processing_system7_0_PS_CLK;
input processing_system7_0_PS_PORB;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
// clock and reset
wire clk, rst_n;
// from PS7
wire evento;
wire arready;
wire rvalid;
wire [63:0] rdata;
wire awready;
wire wready;
wire bvalid;
// to PS7
wire eventi;
wire arvalid;
wire awvalid;
wire rready;
wire wlast;
wire wvalid;
wire [3:0] arlen;
wire [3:0] awlen;
wire [31:0] araddr;
wire [31:0] awaddr;
wire [63:0] wdata;
reg [63:0] counter;
reg [63:0] counter_out;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB ( processing_system7_0_PS_SRSTB ),
.processing_system7_0_PS_CLK ( processing_system7_0_PS_CLK ),
.processing_system7_0_PS_PORB ( processing_system7_0_PS_PORB ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB ( processing_system7_0_DDR_WEB ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
// From NPU to PS7
.processing_system7_0_EVENT_EVENTI ( eventi ),
.processing_system7_0_S_AXI_ACP_ARVALID ( arvalid ),
.processing_system7_0_S_AXI_ACP_AWVALID ( awvalid ),
.processing_system7_0_S_AXI_ACP_RREADY ( rready ),
.processing_system7_0_S_AXI_ACP_WLAST ( wlast ),
.processing_system7_0_S_AXI_ACP_WVALID ( wvalid ),
.processing_system7_0_S_AXI_ACP_ARLEN ( arlen ),
.processing_system7_0_S_AXI_ACP_AWLEN ( awlen ),
.processing_system7_0_S_AXI_ACP_ARADDR ( araddr ),
.processing_system7_0_S_AXI_ACP_AWADDR ( awaddr ),
.processing_system7_0_S_AXI_ACP_WDATA ( wdata ),
// From PS7 to NPU
.processing_system7_0_EVENT_EVENTO ( evento ),
.processing_system7_0_S_AXI_ACP_ARREADY ( arready ),
.processing_system7_0_S_AXI_ACP_RVALID ( rvalid ),
.processing_system7_0_S_AXI_ACP_RDATA ( rdata ),
.processing_system7_0_S_AXI_ACP_AWREADY ( awready ),
.processing_system7_0_S_AXI_ACP_WREADY ( wready ),
.processing_system7_0_S_AXI_ACP_BVALID ( bvalid ),
.processing_system7_0_FCLK_CLK0 ( clk ),
.processing_system7_0_FCLK_RESET0_N ( rst_n )
);
zynqWrapper zynqWrapper(
.CLK ( clk ),
.RST_N ( rst_n ),
.evento ( evento ),
.arready ( arready ),
.rvalid ( rvalid ),
.rdata ( rdata ),
.awready ( awready ),
.wready ( wready ),
.bvalid ( bvalid ),
.eventi ( eventi ),
.arvalid ( arvalid ),
.awvalid ( awvalid ),
.rready ( rready ),
.wlast ( wlast ),
.wvalid ( wvalid ),
.arlen ( arlen ),
.awlen ( awlen ),
.araddr ( araddr ),
.awaddr ( awaddr ),
.wdata ( wdata )
);
always @ (posedge clk) begin
if ( rst_n == 1'b0 ) begin
counter <= 0;
counter_out <= 0;
end else begin
counter <= counter + {{63{1'b0}},1'b1};
counter_out <= counter;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void pv(vector<T> &vec) { for (int i = 0; i < (int)(vec).size(); i++) cout << vec[i] << (i == (int)(vec).size() - 1 ? n : ); } bool ok(int x) { return (x % 10 == 7); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int a, b, x, ans = 0; cin >> x >> a >> b; while (1) { if (ok(a) || ok(b)) break; if (b >= x) b -= x; else { b = 60 - abs(b - x); a = (a ? a - 1 : 23); } ans++; } cout << ans << n ; return 0; }
|
// nios_mm_interconnect_0_avalon_st_adapter_003.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mm_interconnect_0_avalon_st_adapter_003 #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 0,
parameter inDataWidth = 10,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 10,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [9:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [9:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_mm_interconnect_0_avalon_st_adapter_003_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; int add[N << 6], num[N << 6], lazy[N << 6], ls[N << 6], rs[N << 6], total; int init() { num[total] = add[total] = lazy[total] = 0; ls[total] = rs[total] = -1; return total++; } void down(int l, int r, int o) { if (ls[o] == -1) ls[o] = init(); if (rs[o] == -1) rs[o] = init(); int ll = ls[o], rr = rs[o]; add[ll] += add[o]; add[rr] += add[o] + num[o] * ((l + r) / 2 + 1 - l); num[ll] += num[o]; num[rr] += num[o]; lazy[ll] += lazy[o]; lazy[rr] += lazy[o]; num[o] = add[o] = lazy[o] = 0; } int L, R, V, op; void update(int l, int r, int o) { if (L <= l && r <= R) { if (op == 0) { lazy[o] += V; } else { add[o] += l - L + 1; num[o]++; } return; } down(l, r, o); int ll = ls[o], rr = rs[o]; if (L <= (l + r) / 2) update(l, (l + r) / 2, ll); if (R > (l + r) / 2) update((l + r) / 2 + 1, r, rr); } int query(int l, int r, int o, int x) { if (l == r) { return add[o] + lazy[o]; } down(l, r, o); int ll = ls[o], rr = rs[o]; if (x <= (l + r) / 2) return query(l, (l + r) / 2, ll, x); else return query((l + r) / 2 + 1, r, rr, x); } struct Node { int l, t, fg; Node() {} Node(int l, int t, int fg) : l(l), t(t), fg(fg) {} bool operator<(const Node& th) const { if (l != th.l) return l < th.l; if (fg != th.fg) return fg > th.fg; return t < th.t; } } node[N * 2]; int ll[N * 4], rr[N * 4], tt[N * 4]; multiset<int> st; int main() { int n, m; while (scanf( %d%d , &n, &m) != EOF) { int tot = 0; for (int i = 0; i < m; i++) { int l, r, t; scanf( %d%d%d , &l, &r, &t); r--; node[tot++] = Node(l, t, 1); node[tot++] = Node(r, t, -1); } sort(node, node + tot); int cnt = 0, pre; st.clear(); for (int i = 0; i < tot; i++) { int l = node[i].l, t = node[i].t, fg = node[i].fg; if (st.size() == 0) { pre = l; st.insert(t); continue; } if (l > pre) { ll[cnt] = pre; rr[cnt] = l - 1; tt[cnt] = *st.begin(); cnt++; pre = l; } if (fg == -1) { if (pre == l) { ll[cnt] = pre; rr[cnt] = l; tt[cnt] = *st.begin(); cnt++; pre = l + 1; } st.erase(st.lower_bound(t)); } else { st.insert(t); } } int ed = 1e9; total = 0; init(); for (int i = 0; i < cnt; i++) { int l = ll[i], r = rr[i], t = tt[i]; op = 0; V = r - l + 1; L = max(0, t - l + 1), R = ed; if (L <= R) update(0, ed, 0); L = t - r, R = t - l; op = 1; if (R >= 0) update(0, ed, 0); } for (int i = 0; i < n; i++) { int a; scanf( %d , &a); printf( %d n , query(0, ed, 0, a)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; int n; bool good(int x) { int res = x; while (x > 0) { res += x % 10; x /= 10; } return (res == n); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; vector<int> ans; for (int m = n; m >= max(1, n - 100000); m--) { if (good(m)) { ans.emplace_back(m); } } int len = ans.size(); sort(ans.begin(), ans.end()); cout << len << n ; for (int i = 0; i < len; i++) { cout << ans[i] << (i == len - 1 ? n : ); } return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart_transceiver(
input sys_rst,
input sys_clk,
input uart_rx,
output reg uart_tx,
input [15:0] divisor,
output reg [7:0] rx_data,
output reg rx_done,
input [7:0] tx_data,
input tx_wr,
output reg tx_done,
output reg break
);
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;
wire enable16;
assign enable16 = (enable16_counter == 16'd0);
always @(posedge sys_clk) begin
if(sys_rst)
enable16_counter <= divisor - 16'b1;
else begin
enable16_counter <= enable16_counter - 16'd1;
if(enable16)
enable16_counter <= divisor - 16'b1;
end
end
//-----------------------------------------------------------------
// Synchronize uart_rx
//-----------------------------------------------------------------
reg uart_rx1;
reg uart_rx2;
always @(posedge sys_clk) begin
uart_rx1 <= uart_rx;
uart_rx2 <= uart_rx1;
end
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg uart_rx_r;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rx_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
rx_done <= 1'b0;
rx_busy <= 1'b0;
rx_count16 <= 4'd0;
rx_bitcount <= 4'd0;
break <= 1'b0;
uart_rx_r <= 1'b0;
end else begin
rx_done <= 1'b0;
break <= 1'b0;
if(enable16) begin
uart_rx_r <= uart_rx2;
if(~rx_busy) begin // look for start bit
if(~uart_rx2 & uart_rx_r) begin // start bit found
rx_busy <= 1'b1;
rx_count16 <= 4'd7;
rx_bitcount <= 4'd0;
end
end else begin
rx_count16 <= rx_count16 + 4'd1;
if(rx_count16 == 4'd0) begin // sample
rx_bitcount <= rx_bitcount + 4'd1;
if(rx_bitcount == 4'd0) begin // verify startbit
if(uart_rx2)
rx_busy <= 1'b0;
end else if(rx_bitcount == 4'd9) begin
rx_busy <= 1'b0;
if(uart_rx2) begin // stop bit ok
rx_data <= rx_reg;
rx_done <= 1'b1;
end else if(rx_reg == 8'h00) // break condition
break <= 1'b1;
end else
rx_reg <= {uart_rx2, rx_reg[7:1]};
end
end
end
end
end
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] tx_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
tx_done <= 1'b0;
tx_busy <= 1'b0;
uart_tx <= 1'b1;
end else begin
tx_done <= 1'b0;
if(tx_wr) begin
tx_reg <= tx_data;
tx_bitcount <= 4'd0;
tx_count16 <= 4'd1;
tx_busy <= 1'b1;
uart_tx <= 1'b0;
`ifdef SIMULATION
$display("UART: %c", tx_data);
`endif
end else if(enable16 && tx_busy) begin
tx_count16 <= tx_count16 + 4'd1;
if(tx_count16 == 4'd0) begin
tx_bitcount <= tx_bitcount + 4'd1;
if(tx_bitcount == 4'd8) begin
uart_tx <= 1'b1;
end else if(tx_bitcount == 4'd9) begin
uart_tx <= 1'b1;
tx_busy <= 1'b0;
tx_done <= 1'b1;
end else begin
uart_tx <= tx_reg[0];
tx_reg <= {1'b0, tx_reg[7:1]};
end
end
end
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eb_e
//
// Generated
// by: wig
// on: Mon Sep 25 09:53:03 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eb_e.v,v 1.1 2006/09/25 15:14:59 wig Exp $
// $Date: 2006/09/25 15:14:59 $
// $Log: inst_eb_e.v,v $
// Revision 1.1 2006/09/25 15:14:59 wig
// Adding testcase for `foo support
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.93 2006/09/25 08:24:10 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eb_e
//
// No user `defines in this module
module inst_eb_e
//
// Generated Module inst_eb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eba
inst_eba_e inst_eba (
);
// End of Generated Instance Port Map for inst_eba
// Generated Instance Port Map for inst_ebb
inst_ebb_e inst_ebb (
);
// End of Generated Instance Port Map for inst_ebb
// Generated Instance Port Map for inst_ebc
inst_ebc_e inst_ebc (
);
// End of Generated Instance Port Map for inst_ebc
endmodule
//
// End of Generated Module rtl of inst_eb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100 + 5; const long long MOD = 1000000007; long long pow2[MAXN]; char x[MAXN]; int main() { scanf( %s , x); int n = strlen(x); pow2[0] = 1; for (int i = 1; i < n; i++) pow2[i] = (pow2[i - 1] * 2) % MOD; long long d = pow2[n - 1], ans = 0; for (int i = 0; i < n; i++) if (x[i] == 1 ) ans = (ans + pow2[n - i - 1] * d) % MOD; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, i, j, k, sum = 0, cnt = 0, a[101]; cin >> n >> m; vector<long long int> o; for (i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } for (i = 0; i < m; i++) { cin >> j; j--; sum -= a[j]; o.push_back(a[j]); } sort(o.rbegin(), o.rend()); for (i = 0; i < m; i++) { if (o[i] < sum) sum += sum; else sum += o[i]; } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int SQRTN = 320; const int LOGN = 20; const double PI = acos(-1); int n, val; map<int, int> dp; int dp2[N]; int range[N]; bool en[N]; int grundy(long long n) { if (n < 1e6) return dp2[n]; if (dp.find(n) != dp.end()) return dp[n]; int& mex = dp[n]; int st = 0; double e = sqrt(n); double s = sqrt(e); int i = ceil(s), _ = floor(e); while (i < n && i <= _) { i = range[i]; st = st | (1 << grundy(i)); i++; } while (st & (1 << mex)) mex++; return mex; } int calc(int n) { int& mex = dp2[n]; int st = 0; double e = sqrt(n); double s = sqrt(e); for (int i = ceil(s), _ = floor(e); i < n && i <= _; i++) { st = st | (1 << dp2[i]); } while (st & (1 << mex)) mex++; return mex; } int main() { for (int i = 0; i < 1000000; i++) { calc(i); } range[999999] = 999999; en[999999] = 1; for (int i = 999998; i > -1; i--) { if (dp2[i] != dp2[i + 1]) range[i] = i, en[i] = 1; else range[i] = range[i + 1]; } cin >> n; long long a; for (int i = 0; i < n; i++) { scanf( %lld , &a); val = val ^ grundy(a); } cout << (val ? Furlo : Rublo ) << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, m, s1, s2, t1, t2, l1, l2; vector<int> adj[3333]; int dist[3333][3333]; void bfs(int index) { queue<int> q; q.push(index); dist[index][index] = 0; while (!q.empty()) { int cur = q.front(); q.pop(); for (int to : adj[cur]) { if (dist[index][to] != -1) continue; dist[index][to] = dist[index][cur] + 1; q.push(to); } } } int main() { while (scanf( %d %d , &n, &m) == 2) { memset(dist, -1, sizeof dist); for (int i = 0; i < n; i++) adj[i].clear(); for (int i = 0; i < m; i++) { int a, b; scanf( %d %d , &a, &b); adj[--a].push_back(--b); adj[b].push_back(a); } scanf( %d %d %d , &s1, &t1, &l1); --s1, --t1; scanf( %d %d %d , &s2, &t2, &l2); --s2, --t2; for (int i = 0; i < n; i++) bfs(i); if (dist[s1][t1] > l1 || dist[s2][t2] > l2) { puts( -1 ); continue; } int ans = dist[s1][t1] + dist[s2][t2]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { { int p1 = dist[s1][i] + dist[i][j] + dist[j][t1]; int p2 = dist[s2][i] + dist[i][j] + dist[j][t2]; if (p1 <= l1 && p2 <= l2) ans = min(ans, p1 + p2 - dist[i][j]); } { int p1 = dist[t1][i] + dist[i][j] + dist[j][s1]; int p2 = dist[s2][i] + dist[i][j] + dist[j][t2]; if (p1 <= l1 && p2 <= l2) ans = min(ans, p1 + p2 - dist[i][j]); } } ans = m - ans; printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_SYMBOL_V
`define SKY130_FD_SC_LP__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e6 + 5, inf = 1e9 + 7; long long n, k, cumm[N], m[26]; set<pair<long long, long long> > st; string s; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long i, j, a, b, ans = 1; cin >> n >> k >> s; s = # + s; for (i = 0; i < k; i++) st.insert(pair<long long, long long>(m[i], i)); for (i = 1; i < n + s.size(); i++) { if (i < s.size()) a = s[i] - a ; else a = st.begin()->second; st.erase(st.find(pair<long long, long long>(m[a], a))); if (m[a]) cumm[i] = cumm[i - 1] - cumm[m[a] - 1]; else cumm[i] = cumm[i - 1] + 1; m[a] = i; st.insert(pair<long long, long long>(m[a], a)); cumm[i] = (cumm[i] % inf + cumm[i - 1] + inf) % inf; } cout << (cumm[i - 1] + 1) % inf; }
|
#include <bits/stdc++.h> using namespace std; inline int max3(int a, int b, int c) { return max(a, max(b, c)); } inline int min3(int a, int b, int c) { return min(a, min(b, c)); } const int INF = 1e9; const long long LINF = 1e18; const double EPS = 1e-6; const double PI = acos(-1.0); const int maxn = 150; int n, m, k; int a[maxn][maxn][maxn]; int ans; int main() { scanf( %d %d %d n , &n, &m, &k); char b[maxn]; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { gets(b); for (int p = 0; p < k; ++p) a[i][j][p] = b[p] == 1 ; } if (i < n - 1) gets(b); } ans = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { for (int p = 0; p < k; ++p) { if (!a[i][j][p]) continue; if ((p > 0 && p < k - 1 && a[i][j][p - 1] && a[i][j][p + 1]) || (p > 0 && j < m - 1 && a[i][j][p - 1] && a[i][j + 1][p] && !a[i][j + 1][p - 1]) || (p > 0 && i < n - 1 && a[i][j][p - 1] && a[i + 1][j][p] && !a[i + 1][j][p - 1]) || (j > 0 && j < m - 1 && a[i][j - 1][p] && a[i][j + 1][p]) || (j > 0 && p < k - 1 && a[i][j - 1][p] && a[i][j][p + 1] && !a[i][j - 1][p + 1]) || (j > 0 && i < n - 1 && a[i][j - 1][p] && a[i + 1][j][p] && !a[i + 1][j - 1][p]) || (i > 0 && i < n - 1 && a[i - 1][j][p] && a[i + 1][j][p]) || (i > 0 && j < m - 1 && a[i - 1][j][p] && a[i][j + 1][p] && !a[i - 1][j + 1][p]) || (i > 0 && p < k - 1 && a[i - 1][j][p] && a[i][j][p + 1] && !a[i - 1][j][p + 1])) ++ans; } } } printf( %d n , ans); return 0; }
|
// DESCRIPTION: Verilator: Interface parameter getter
//
// A test of the import parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader
interface test_if #(parameter integer FOO = 1);
// Interface variable
logic data;
// Modport
modport mp(
import getFoo,
output data
);
function integer getFoo ();
return FOO;
endfunction
endinterface // test_if
function integer identity (input integer x);
return x;
endfunction
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if #( .FOO (identity(5)) ) the_interface ();
testmod testmod_i (.clk (clk),
.intf (the_interface),
.intf_no_mp (the_interface)
);
localparam THE_TOP_FOO = the_interface.FOO;
initial begin
if (THE_TOP_FOO != 5) begin
$display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO);
$stop;
end
end
endmodule
module testmod
(
input clk,
test_if.mp intf,
test_if intf_no_mp
);
localparam THE_FOO = intf.FOO;
localparam THE_OTHER_FOO = intf_no_mp.FOO;
always @(posedge clk) begin
if (THE_FOO != 5) begin
$display("%%Error: THE_FOO = %0d", THE_FOO);
$stop;
end
if (THE_OTHER_FOO != 5) begin
$display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO);
$stop;
end
if (intf.FOO != 5) begin
$display("%%Error: intf.FOO = %0d", intf.FOO);
$stop;
end
if (intf_no_mp.FOO != 5) begin
$display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO);
$stop;
end
// if (i.getFoo() != 5) begin
// $display("%%Error: i.getFoo() = %0d", i.getFoo());
// $stop;
// end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fLL; const double EPS = 1e-8; const int MOD = 998244353; const int dy[] = {1, 0, -1, 0}, dx[] = {0, -1, 0, 1}; int mod = MOD; struct ModInt { unsigned val; ModInt() : val(0) {} ModInt(long long x) : val(x >= 0 ? x % mod : x % mod + mod) {} ModInt pow(long long exponent) { ModInt tmp = *this, res = 1; while (exponent > 0) { if (exponent & 1) res *= tmp; tmp *= tmp; exponent >>= 1; } return res; } ModInt &operator+=(const ModInt &rhs) { if ((val += rhs.val) >= mod) val -= mod; return *this; } ModInt &operator-=(const ModInt &rhs) { if ((val += mod - rhs.val) >= mod) val -= mod; return *this; } ModInt &operator*=(const ModInt &rhs) { val = (unsigned long long)val * rhs.val % mod; return *this; } ModInt &operator/=(const ModInt &rhs) { return *this *= rhs.inv(); } bool operator==(const ModInt &rhs) const { return val == rhs.val; } bool operator!=(const ModInt &rhs) const { return val != rhs.val; } bool operator<(const ModInt &rhs) const { return val < rhs.val; } bool operator<=(const ModInt &rhs) const { return val <= rhs.val; } bool operator>(const ModInt &rhs) const { return val > rhs.val; } bool operator>=(const ModInt &rhs) const { return val >= rhs.val; } ModInt operator-() const { return ModInt(-val); } ModInt operator+(const ModInt &rhs) const { return ModInt(*this) += rhs; } ModInt operator-(const ModInt &rhs) const { return ModInt(*this) -= rhs; } ModInt operator*(const ModInt &rhs) const { return ModInt(*this) *= rhs; } ModInt operator/(const ModInt &rhs) const { return ModInt(*this) /= rhs; } friend ostream &operator<<(ostream &os, const ModInt &rhs) { return os << rhs.val; } friend istream &operator>>(istream &is, ModInt &rhs) { long long x; is >> x; rhs = ModInt(x); return is; } private: ModInt inv() const { unsigned a = val, b = mod; int x = 1, y = 0; while (b) { unsigned tmp = a / b; a -= tmp * b; swap(a, b); x -= tmp * y; swap(x, y); } return ModInt(x); } }; ModInt abs(const ModInt &x) { return x.val; } struct Combinatorics { Combinatorics(int MAX = 5000000) { MAX <<= 1; fact.resize(MAX + 1); fact_inv.resize(MAX + 1); fact[0] = 1; for (int i = (1); i < (MAX + 1); ++i) fact[i] = fact[i - 1] * i; fact_inv[MAX] = ModInt(1) / fact[MAX]; for (int i = MAX; i > 0; --i) fact_inv[i - 1] = fact_inv[i] * i; } ModInt nCk(int n, int k) { if (n < 0 || n < k || k < 0) return ModInt(0); return fact[n] * fact_inv[k] * fact_inv[n - k]; } ModInt nPk(int n, int k) { if (n < 0 || n < k || k < 0) return ModInt(0); return fact[n] * fact_inv[n - k]; } ModInt nHk(int n, int k) { if (n < 0 || k < 0) return ModInt(0); return (k == 0 ? ModInt(1) : nCk(n + k - 1, k)); } private: vector<ModInt> fact, fact_inv; }; int main() { cin.tie(0); ios::sync_with_stdio(false); int n, m; cin >> n >> m; vector<int> a(n); for (int i = (0); i < (n); ++i) cin >> a[i]; vector<int> w(n); for (int i = (0); i < (n); ++i) cin >> w[i]; int dl = 0, l = 0; for (int i = (0); i < (n); ++i) (a[i] == 0 ? dl : l) += w[i]; vector<vector<ModInt> > dp(m + 1, vector<ModInt>(m + 1, 0)); dp[0][0] = 1; for (int i = (0); i < (m); ++i) for (int j = (0); j < (m); ++j) { int sum = l + dl - j + (i - j); if (j > dl || j > i || sum <= 0) continue; dp[i + 1][j + 1] += dp[i][j] * (dl - j) / sum; dp[i + 1][j] += dp[i][j] * (l + (i - j)) / sum; } vector<ModInt> ans(2, 0); ModInt tmp = 1; for (int i = (0); i < (dl + 1); ++i) { if (i > m) break; ans[0] += tmp * dp[m][i]; if (i < dl) tmp *= (ModInt(1) - ModInt(1) / (dl - i)); } tmp = 1; for (int i = (0); i < (m + 1); ++i) { ans[1] += tmp * dp[m][m - i]; tmp *= (ModInt(1) + ModInt(1) / (l + i)); } for (int i = (0); i < (n); ++i) cout << ans[a[i]] * w[i] << n ; return 0; }
|
// Copyright 2007, Martin Whitaker
// This file may be freely copied for any purpose.
module macro_with_args();
`define forward_and_reverse(str1,str2,str3) /* comment */ \
$write("%0s", str1); /* comment */ \
$write(".."); /* comment */ \
$write("%0s", str3); /* comment */ \
$write("%0s", str2); /* comment */ \
$write("%0s", str3); /* comment */ \
$write(".."); /* comment */ \
$write("%0s", str1); /* comment */ \
$write("\n")
`define sqr( x ) (x * x) // comment
`define sum( a /* comment */ , b /* comment */ ) /* comment */ \
(a + b)
`define sumsqr(
a // comment
,
b // comment
) \
`sum ( \
`sqr(a) \
, \
`sqr(b) \
)
`define no_args (a,b,c)
`define null1 // null
`define null2
integer value;
reg [79:0] astr, bstr, cstr;
initial begin
`forward_and_reverse("first"," first,last ","last");
$sformat(astr, "(a%s)", ``null1);
$sformat(bstr, " %s ", ``no_args);
$sformat(cstr, "(c%s)", ``null2);
`forward_and_reverse // comment
( // comment
astr // comment
, // comment
bstr // comment
, // comment
cstr // comment
); // comment
value = `sumsqr(3,4);
$display("sumsqr(3,4) = %1d", value);
if (value != `sqr(5)) $display("sumsqr expansion failed");
value = `sumsqr
(
(2 + 3) /* 5 */
,
(4 + 8) /* 12 */
);
$display("sumsqr(5,12) = %1d", value);
if (value != `sqr(13)) $display("sumsqr expansion failed");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } template <class T> T gcd(T a, T b) { return !b ? a : gcd(b, a % b); } template <class T> inline void cmin(T &x, T y) { x = x < y ? x : y; } template <class T> inline void cmax(T &x, T y) { x = x > y ? x : y; } const int N = 100010; int n, q, head[N], nxt[N], v[N], cnt, son[N], top[N], si[N], wp[N], totw, id[N], fa[N]; inline void add(int x, int y) { nxt[++cnt] = head[x]; head[x] = cnt; v[cnt] = y; } struct seg { int l, r, sum, sufma, al; } t[N << 2]; void dfs(int now) { int mx = -1; si[now] = 1; for (register int i = head[now]; i; i = nxt[i]) { dfs(v[i]); si[now] += si[v[i]]; if (si[v[i]] > mx) son[now] = v[i]; } } void _dfs(int now, int tf) { top[now] = tf; wp[now] = ++totw; id[totw] = now; if (!son[now]) return; _dfs(son[now], tf); for (register int i = head[now]; i; i = nxt[i]) { if (son[now] != v[i]) _dfs(v[i], v[i]); } } void merge(seg &a, seg b, seg c) { a.sum = b.sum + c.sum; a.sufma = max(c.sufma, c.sum + b.sufma); } void build(int p, int l, int r) { t[p].l = l; t[p].r = r; if (l == r) { t[p].sum = t[p].sufma = -1; return; } int mid = (l + r) >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); merge(t[p], t[p << 1], t[p << 1 | 1]); } void pushdown(int p) { if (t[p].al != 0) { t[p << 1].al = t[p << 1 | 1].al = t[p].al; t[p << 1].sum = (t[p << 1].r - t[p << 1].l + 1) * t[p << 1].al; t[p << 1 | 1].sum = (t[p << 1 | 1].r - t[p << 1 | 1].l + 1) * t[p << 1 | 1].al; t[p << 1].sufma = t[p << 1 | 1].sufma = -1; t[p].al = 0; } } void change(int p, int x, int dt) { if (t[p].l == t[p].r) { t[p].sufma += dt; t[p].sum += dt; return; } pushdown(p); int mid = (t[p].l + t[p].r) >> 1; if (x <= mid) change(p << 1, x, dt); else change(p << 1 | 1, x, dt); merge(t[p], t[p << 1], t[p << 1 | 1]); } void modify(int p, int l, int r, int dt) { if (t[p].l >= l && t[p].r <= r) { t[p].al = dt; t[p].sum = (t[p].r - t[p].l + 1) * t[p].al; t[p].sufma = -1; return; } pushdown(p); int mid = (t[p].l + t[p].r) >> 1; if (l <= mid) modify(p << 1, l, r, dt); if (r > mid) modify(p << 1 | 1, l, r, dt); merge(t[p], t[p << 1], t[p << 1 | 1]); } seg maxsuf(int p, int l, int r) { if (t[p].l >= l && t[p].r <= r) { return t[p]; } pushdown(p); int mid = (t[p].l + t[p].r) >> 1; if (r <= mid) return maxsuf(p << 1, l, r); if (l > mid) return maxsuf(p << 1 | 1, l, r); seg tmp; merge(tmp, maxsuf(p << 1, l, r), maxsuf(p << 1 | 1, l, r)); return tmp; } int query(int x) { seg res = maxsuf(1, wp[top[x]], wp[x]); x = fa[top[x]]; while (x) { merge(res, maxsuf(1, wp[top[x]], wp[x]), res); x = fa[top[x]]; } return res.sufma; } int main() { read(n); read(q); for (register int i = (2); i <= (n); i++) { read(fa[i]); add(fa[i], i); } dfs(1); _dfs(1, 1); build(1, 1, n); for (register int i = (1); i <= (q); i++) { int opt, x; read(opt); read(x); if (opt == 1) { change(1, wp[x], 1); } else if (opt == 2) { modify(1, wp[x], wp[x] + si[x] - 1, -1); change(1, wp[x], -(query(x) + 1)); } else { if (query(x) >= 0) { printf( black n ); } else { printf( white n ); } } } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:34:23 02/26/2016
// Design Name: Alu
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab3/test_for_Alu.v
// Project Name: lab3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_Alu;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
reg [3:0] aluCtr;
// Outputs
wire zero;
wire [31:0] aluRes;
// Instantiate the Unit Under Test (UUT)
Alu uut (
.input1(input1),
.input2(input2),
.aluCtr(aluCtr),
.zero(zero),
.aluRes(aluRes)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
aluCtr = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0000;
end
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0001;
end
#100
begin
input1 = 1;
input2 = 1;
aluCtr = 'b0010;
end
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0110;
end
#100
begin
input1 = 1;
input2 = 1;
aluCtr = 'b0110;
end
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0111;
end
#100
begin
input1 = 170;
input2 = 255;
aluCtr = 'b0111;
end
#100
begin
input1 = 0;
input2 = 1;
aluCtr = 'b1100;
end
end
endmodule
|
//------------------------------------------------------------------------------
// File : gmii_if.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This module creates a Gigabit Media Independent
// Interface (GMII) by instantiating Input/Output buffers
// and Input/Output flip-flops as required.
//
// This interface is used to connect the Ethernet MAC to
// an external Ethernet PHY via GMII connection.
//
// The GMII receiver clocking logic is also defined here: the
// receiver clock received from the PHY is unique and cannot be
// shared across multiple instantiations of the core. For the
// receiver clock:
//
// A BUFIO/BUFR combination is used for the input clock to allow
// the use of IODELAYs on the DATA.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gmii_if (
// Synchronous resets
input tx_reset,
input rx_reset,
// The following ports are the GMII physical interface: these will be at
// pins on the FPGA
output reg [7:0] gmii_txd,
output reg gmii_tx_en,
output reg gmii_tx_er,
output gmii_tx_clk,
input gmii_crs,
input gmii_col,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
// The following ports are the internal GMII connections from IOB logic to
// the TEMAC core
input [7:0] txd_from_mac,
input tx_en_from_mac,
input tx_er_from_mac,
input tx_clk,
output crs_to_mac,
output col_to_mac,
output reg [7:0] rxd_to_mac,
output reg rx_dv_to_mac,
output reg rx_er_to_mac,
// Receiver clock for the MAC and Client Logic
output rx_clk
);
//----------------------------------------------------------------------------
// internal signals
//----------------------------------------------------------------------------
(* ASYNC_REG = "TRUE" *)
reg gmii_col_reg;
reg gmii_col_reg_reg ;
wire gmii_rx_dv_delay;
wire gmii_rx_er_delay;
wire [7:0] gmii_rxd_delay;
wire gmii_rx_clk_bufio;
wire rx_clk_int;
//----------------------------------------------------------------------------
// GMII Transmitter Clock Management :
// drive gmii_tx_clk through IOB onto GMII interface
//----------------------------------------------------------------------------
// Instantiate a DDR output register. This is a good way to drive
// GMII_TX_CLK since the clock-to-PAD delay will be the same as that
// for data driven from IOB Ouput flip-flops eg gmii_rxd[7:0].
// This is set to produce an inverted clock w.r.t. gmii_tx_clk_int
// so that the rising edge is centralised within the
// gmii_rxd[7:0] valid window.
ODDR gmii_tx_clk_ddr_iob (
.Q (gmii_tx_clk),
.C (tx_clk),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (1'b0),
.S (1'b0)
);
//---------------------------------------------------------------------------
// GMII Transmitter Logic : drive TX signals through IOBs registers onto
// GMII interface
//---------------------------------------------------------------------------
// Infer IOB Output flip-flops.
always @(posedge tx_clk)
begin
gmii_tx_en <= tx_en_from_mac;
gmii_tx_er <= tx_er_from_mac;
gmii_txd <= txd_from_mac;
end
// GMII_CRS is an asynchronous signal which is routed straight through to the
// core
assign crs_to_mac = gmii_crs;
// GMII_COL is an asynchronous signal. Here is registered, then 'stretched'
// to ensure that the MAC will see it.
always @(posedge tx_clk)
begin
if (tx_reset == 1'b1) begin
gmii_col_reg <= 1'b0;
gmii_col_reg_reg <= 1'b0;
end
else begin
gmii_col_reg <= gmii_col;
gmii_col_reg_reg <= gmii_col_reg;
end
end
assign col_to_mac = gmii_col_reg_reg | gmii_col_reg | gmii_col;
//---------------------------------------------------------------------------
// GMII Receiver Clock Logic
//---------------------------------------------------------------------------
// Route gmii_rx_clk through a BUFIO/BUFR and onto regional clock routing
BUFIO bufio_gmii_rx_clk (
.I (gmii_rx_clk),
.O (gmii_rx_clk_bufio)
);
// Route rx_clk through a BUFR onto regional clock routing
BUFR bufr_gmii_rx_clk (
.I (gmii_rx_clk),
.CE (1'b1),
.CLR (1'b0),
.O (rx_clk_int)
);
// Assign the internal clock signal to the output port
assign rx_clk = rx_clk_int;
//---------------------------------------------------------------------------
// GMII Receiver Logic : receive RX signals through IOBs from GMII interface
//---------------------------------------------------------------------------
// Use IDELAY to delay data to the capturing register.
// Note: Delay value is set in UCF file
// Please modify the IOBDELAY_VALUE according to your design.
// For more information on IDELAYCTRL and IDELAY, please refer to
// the User Guide.
IODELAYE1 #(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("I")
)
delay_gmii_rx_dv (
.IDATAIN (gmii_rx_dv),
.ODATAIN (1'b0),
.DATAOUT (gmii_rx_dv_delay),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b1),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (1'b0),
.CNTVALUEIN (5'h0),
.CNTVALUEOUT (),
.INC (1'b0),
.RST (1'b0)
);
IODELAYE1 #(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("I")
)
delay_gmii_rx_er (
.IDATAIN (gmii_rx_er),
.ODATAIN (1'b0),
.DATAOUT (gmii_rx_er_delay),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b1),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (1'b0),
.CNTVALUEIN (5'h0),
.CNTVALUEOUT (),
.INC (1'b0),
.RST (1'b0)
);
genvar i;
generate for (i=0; i<8; i=i+1)
begin : gmii_data_bus0
IODELAYE1 #(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("I")
)
delay_gmii_rxd (
.IDATAIN (gmii_rxd[i]),
.ODATAIN (1'b0),
.DATAOUT (gmii_rxd_delay[i]),
.DATAIN (1'b0),
.C (1'b0),
.T (1'b1),
.CE (1'b0),
.CINVCTRL (1'b0),
.CLKIN (1'b0),
.CNTVALUEIN (5'h0),
.CNTVALUEOUT (),
.INC (1'b0),
.RST (1'b0)
);
end
endgenerate
// Infer IOB Input flip-flops.
always @(posedge gmii_rx_clk_bufio)
begin
rx_dv_to_mac <= gmii_rx_dv_delay;
rx_er_to_mac <= gmii_rx_er_delay;
rxd_to_mac <= gmii_rxd_delay;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; while (scanf( %d%d%d , &n, &m, &k) != EOF) { if (n == m) { if (n == 2 && k == 1) { printf( 4 n ); printf( 1 2 3 4 n ); } else { printf( %d n , 2 * k + 1); printf( 1 ); for (int i = 1; i < k; i++) { printf( 1 ); } printf( %d , n); for (int i = 1; i < k; i++) { printf( %d , n + 1); } if (k == 1) printf( %d n , 2 * n - 1); else printf( %d n , 2 * n); } } else if (m == n - 1) { if (k > 1) { printf( %d n , 2 * k); printf( 1 ); for (int i = 1; i < k; i++) { printf( 1 ); } printf( %d , n); for (int i = 1; i < k; i++) { printf( %d , n + 1); } printf( n ); } else { printf( %d n , 2 * k + 1); printf( 1 ); for (int i = 1; i < k; i++) { printf( 1 ); } printf( %d , n); for (int i = 1; i < k; i++) { printf( %d , n + 1); } printf( %d n , n + m); } } else { printf( %d n , 2 * k); printf( 1 ); for (int i = 1; i < k; i++) { printf( 1 ); } printf( %d , n); for (int i = 1; i < k; i++) { printf( %d , n + 1); } printf( n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long w = 0, x = 0; char c = getchar(); while (!isdigit(c)) w |= c == - , c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); return w ? -x : x; } namespace star { const long long maxn = 1005, maxm = 2e5 + 10, delta = 3e8 + 10, INF = 0x3f3f3f3f3f3f3f3f; long long ecnt = 1, n, head[maxn], to[maxm], nxt[maxm], v[maxm], S, T, ans; inline void addedge(long long a, long long b, long long val) { to[++ecnt] = b, nxt[ecnt] = head[a], head[a] = ecnt, v[ecnt] = val; to[++ecnt] = a, nxt[ecnt] = head[b], head[b] = ecnt, v[ecnt] = 0; } long long dep[maxn]; inline bool bfs() { memset(dep, -1, sizeof dep); queue<long long> q; dep[S] = 0; q.push(S); while (!q.empty()) { long long x = q.front(); q.pop(); for (long long i = head[x]; i; i = nxt[i]) { long long u = to[i]; if (v[i] and dep[u] == -1) dep[u] = dep[x] + 1, q.push(u); } } return dep[T] != -1; } long long dfs(long long x, long long flow) { if (x == T) return flow; long long w = 0, used = 0; for (long long i = head[x]; i; i = nxt[i]) { long long u = to[i]; if (v[i] and dep[u] == dep[x] + 1) { w = dfs(u, min(v[i], flow - used)); used += w; v[i] -= w, v[i ^ 1] += w; if (used == flow) return flow; } } if (!used) dep[x] = -1; return used; } inline void work() { n = read(); S = n * 2 + 1, T = n * 2 + 2; for (long long i = 1; i <= n; i++) { long long x = read(); while (x--) { long long u = read(); addedge(i, n + u, INF); } } for (long long tmp, i = 1; i <= n; i++) addedge(S, i, tmp = delta - read()), ans += tmp; for (long long i = 1; i <= n; i++) addedge(i + n, T, delta); while (bfs()) ans -= dfs(S, INF); printf( %lld n , min(0LL, -ans)); } } // namespace star signed main() { star::work(); return 0; }
|
module data_path();
wire[31:0] input_data_1;
wire[31:0] input_data_2;
wire[31:0] output_data;
wire[31:0] memory_data;
wire[31:0] alu_data_output;
wire alu_carry_output;
// instruction fetch stage
program_counter_adder pcadder_0(clock, if_program_counter);
instruction_memory im_0(if_program_counter, if_instruction_value);
interstage_buffer_if_id ib_0(if_instruction_value,
clock,
id_instruction_value);
// instruction decode stage
instruction_decoder id_0(id_instruction_value,
id_alu_opcode,
id_input_type_1,
id_input_register_selector_1,
id_input_immediate_1,
id_input_type_2,
id_input_register_selector_2,
id_input_immediate_2,
id_output_enable,
id_output_source_selector,
id_output_register_selector);
register_file rf_0(id_input_register_selector_1,
id_input_register_selector_2,
wb_output_register_selector,
wb_output_data,
wb_output_enable,
id_input_data_1,
id_input_data_2);
interstage_buffer_id_ex(id_alu_opcode,
id_operand_1,
id_operand_2,
id_input_immediate_1,
id_output_enable,
id_output_source_selector,
id_output_register_selector,
clock,
ex_alu_opcde,
ex_operand_1,
ex_operand_2,
ex_input_immediate_1,
ex_output_enable,
ex_output_source_selector,
ex_output_register_selector);
// execute stage
alu alu_0(ex_alu_opcode,
ex_operand_1,
ex_operand_2,
ex_alu_data_output,
ex_alu_carry_output);
interstage_buffer_ex_mem(ex_alu_data_output,
ex_input_immediate_1,
ex_output_source_selector,
ex_output_register_selector, clock,
mem_alu_data_output,
mem_input_immediate_1
mem_output_source_selector,
mem_output_register_selector);
// memory stage
interstage_buffer_mem_wb(mem_alu_data_output,
mem_input_immediate_1,
mem_output_source_selector,
mem_output_register_selector,
clock,
wb_alu_data_output,
wb_input_immediate_1,
wb_ouput_source_selector,
wb_output_register_selector);
// writeback stage
multiplexor_4x1 output_mux_0(wb_output_source_selector,
wb_alu_data_output,
b_input_immediate_1,
0,
wb_memory_data,
wb_output_data);
endmodule
|
`timescale 1ns/1ps
`define CLOG2(x) \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7 : \
(x <= 256) ? 8 : \
(x <= 512) ? 9 : \
(x <= 1024) ? 10 : \
(x <= 2048) ? 11 : \
(x <= 4096) ? 12 : \
-1
module tb_cocotb #(
parameter DATA_WIDTH = 32, //This is the output bus
parameter ADDR_WIDTH = 32,
parameter MAX_PACKET_SIZE = 4096,
parameter MAX_PACKET_WIDTH = `CLOG2(MAX_PACKET_SIZE),
parameter INTERRUPT_WIDTH = 32
)(
//Virtual Host Interface Signals
input clk,
input rst,
input [31:0] test_id,
input CMD_EN,
output CMD_ERROR,
output CMD_ACK,
input [ADDR_WIDTH - 1:0] CMD_ADR,
input CMD_ADR_FIXED,
input CMD_ADR_WRAP,
input CMD_WR_RD, //1 = wRITE, 0 = rEAD
input [MAX_PACKET_WIDTH - 1: 0]CMD_COUNT,
output [31:0] CMD_STATUS,
output CMD_INTERRUPT,
//Data FIFOs
//write side
input WR_CLK,
output [1:0] WR_RDY,
input [1:0] WR_ACT,
output [23:0] WR_SIZE,
input WR_STB,
input [DATA_WIDTH - 1: 0] WR_DATA,
output WR_STARVED,
//read side
input RD_CLK,
input RD_STB,
output RD_RDY,
input RD_ACT,
output [23:0] RD_SIZE,
output [DATA_WIDTH - 1: 0] RD_DATA,
//NOT IMPLEMENTED YET
/*
input [2:0] i_cmd_txrx_width, //0 = 8-bit, 1 = 16-bit, 16-bit, 2 = 32-bit...
input [3:0] i_cmd_aw_id, //Add an ide to the write/command paths
input [3:0] i_cmd_w_id,
input [3:0] i_cmd_ar_id,
output [3:0] o_cmd_r_id,
output [3:0] o_cmd_b_id,
*/
//***************** AXI Bus ************************************************
//bus write addr path
output [3:0] AXIS_AWID, //Write ID
output [ADDR_WIDTH - 1:0] AXIS_AWADDR, //Write Addr Path Address
output [7:0] AXIS_AWLEN, //Write Addr Path Burst Length
output [2:0] AXIS_AWSIZE, //Write Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_AWBURST, //Write Addr Path Burst Type
// 0 = Fixed
// 1 = Incrementing
// 2 = wrap
output [1:0] AXIS_AWLOCK, //Write Addr Path Lock (atomic) information
// 0 = Normal
// 1 = Exclusive
// 2 = Locked
output [3:0] AXIS_AWCACHE, //Write Addr Path Cache Type
output [2:0] AXIS_AWPROT, //Write Addr Path Protection Type
output AXIS_AWVALID, //Write Addr Path Address Valid
input AXIS_AWREADY, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output [3:0] AXIS_WID, //Write ID
output [DATA_WIDTH - 1: 0] AXIS_WDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output [(DATA_WIDTH >> 3) - 1:0] AXIS_WSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
output AXIS_WLAST, //Write Last transfer in a write burst
output AXIS_WVALID, //Data through this bus is valid
input AXIS_WREADY, //Slave is ready for data
//Write Response Channel
input [3:0] AXIS_BID, //Response ID (this must match awid)
input [1:0] AXIS_BRESP, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input AXIS_BVALID, //Write Response is:
// 1 = Available
// 0 = Not Available
output AXIS_BREADY, //WBM Ready
//bus read addr path
output [3:0] AXIS_ARID, //Read ID
output [ADDR_WIDTH - 1:0] AXIS_ARADDR, //Read Addr Path Address
output [7:0] AXIS_ARLEN, //Read Addr Path Burst Length
output [2:0] AXIS_ARSIZE, //Read Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_ARBURST, //Read Addr Path Burst Type
output [1:0] AXIS_ARLOCK, //Read Addr Path Lock (atomic) information
output [3:0] AXIS_ARCACHE, //Read Addr Path Cache Type
output [2:0] AXIS_ARPROT, //Read Addr Path Protection Type
output AXIS_ARVALID, //Read Addr Path Address Valid
input AXIS_ARREADY, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] AXIS_RID, //Write ID
input [DATA_WIDTH - 1: 0] AXIS_RDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
input [1:0] AXIS_RRESP,
input [(DATA_WIDTH >> 3) - 1:0] AXIS_RSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
input AXIS_RLAST, //Write Last transfer in a write burst
input AXIS_RVALID, //Data through this bus is valid
output AXIS_RREADY, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
input [INTERRUPT_WIDTH - 1:0] i_interrupts
);
//Local Parameters
localparam INVERT_AXI_RESET = 0;
localparam FIFO_DEPTH = 8; //256
localparam ENABLE_NACK = 0; //Enable timeout
localparam DEFAULT_TIMEOUT = 32'd100000000; //1 Second at 100MHz
//Registers/Wires
reg r_rst;
wire [INTERRUPT_WIDTH - 1:0] w_interrupts;
//Submodules
axi_master #(
.INVERT_AXI_RESET (INVERT_AXI_RESET ),
.MAX_PACKET_SIZE (MAX_PACKET_SIZE ),
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH ),
.INTERRUPT_WIDTH (INTERRUPT_WIDTH ),
.ENABLE_NACK (ENABLE_NACK ),
.DEFAULT_TIMEOUT (DEFAULT_TIMEOUT )
) am (
.clk (clk ),
.rst (r_rst ),
//************* User Facing Side *******************************************
.i_cmd_en (CMD_EN ),
.o_cmd_error (CMD_ERROR ),
.o_cmd_ack (CMD_ACK ),
.o_cmd_status (CMD_STATUS ),
.o_cmd_interrupt (CMD_INTERRUPT ),
.i_cmd_addr (CMD_ADR ),
.i_cmd_adr_fixed_en (CMD_ADR_FIXED ),
.i_cmd_adr_wrap_en (CMD_ADR_WRAP ),
.i_cmd_wr_rd (CMD_WR_RD ),
.i_cmd_data_count (CMD_COUNT ),
//Data FIFOs
.i_ingress_clk (WR_CLK ),
.o_ingress_rdy (WR_RDY ),
.i_ingress_act (WR_ACT ),
.i_ingress_stb (WR_STB ),
.i_ingress_data (WR_DATA ),
.o_ingress_size (WR_SIZE ),
.i_egress_clk (RD_CLK ),
.o_egress_rdy (RD_RDY ),
.i_egress_act (RD_ACT ),
.i_egress_stb (RD_STB ),
.o_egress_data (RD_DATA ),
.o_egress_size (RD_SIZE ),
//***************** AXI Bus ************************************************
//bus write addr path
.o_awid (AXIS_AWID ),
.o_awaddr (AXIS_AWADDR ),
.o_awlen (AXIS_AWLEN ),
.o_awsize (AXIS_AWSIZE ),
.o_awburst (AXIS_AWBURST ),
.o_awlock (AXIS_AWLOCK ),
.o_awcache (AXIS_AWCACHE ),
.o_awprot (AXIS_AWPROT ),
.o_awvalid (AXIS_AWVALID ),
.i_awready (AXIS_AWREADY ),
//bus write data
.o_wid (AXIS_WID ),
.o_wdata (AXIS_WDATA ),
.o_wstrobe (AXIS_WSTRB ),
.o_wlast (AXIS_WLAST ),
.o_wvalid (AXIS_WVALID ),
.i_wready (AXIS_WREADY ),
//Write Response Channel
.i_bid (AXIS_BID ),
.i_bresp (AXIS_BRESP ),
.i_bvalid (AXIS_BVALID ),
.o_bready (AXIS_BREADY ),
//bus read addr path
.o_arid (AXIS_ARID ),
.o_araddr (AXIS_ARADDR ),
.o_arlen (AXIS_ARLEN ),
.o_arsize (AXIS_ARSIZE ),
.o_arburst (AXIS_ARBURST ),
.o_arlock (AXIS_ARLOCK ),
.o_arcache (AXIS_ARCACHE ),
.o_arprot (AXIS_ARPROT ),
.o_arvalid (AXIS_ARVALID ),
.i_arready (AXIS_ARREADY ),
//bus read data
.i_rid (AXIS_RID ),
.i_rdata (AXIS_RDATA ),
.i_rresp (AXIS_RRESP ),
.i_rstrobe (AXIS_RSTRB ),
.i_rlast (AXIS_RLAST ),
.i_rvalid (AXIS_RVALID ),
.o_rready (AXIS_RREADY ),
//nterrupts
.i_interrupts (i_interrupts )
);
//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 1020; int n, m, d, tmp; int h[maxn], dis1[maxn], dis2[maxn]; bool mark[maxn], isaffected[maxn]; vector<int> adj[maxn]; pair<int, int> temp; void dfsa(int v) { for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (!mark[u]) { mark[u] = true; h[u] = h[v] + 1; dfsa(u); if (h[u] > tmp && isaffected[u]) { tmp = h[u]; temp.first = u; } } } } void dfsb(int v) { for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (!mark[u]) { mark[u] = true; h[u] = h[v] + 1; dfsb(u); if (h[u] > tmp && isaffected[u]) { tmp = h[u]; temp.second = u; } } } } void dfs1(int v) { for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (!mark[u]) { mark[u] = true; dis1[u] = dis1[v] + 1; dfs1(u); } } } void dfs2(int v) { for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (!mark[u]) { mark[u] = true; dis2[u] = dis2[v] + 1; dfs2(u); } } } int main() { cin >> n >> m >> d; for (int i = 1; i <= m; i++) { int x; cin >> x; isaffected[x] = true; } for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } mark[1] = true; dfsa(1); for (int i = 1; i <= n; i++) { h[i] = 0; mark[i] = false; } h[temp.first] = 0; tmp = 0; mark[temp.first] = true; dfsb(temp.first); for (int i = 1; i <= n; i++) { mark[i] = false; } dis1[temp.first] = 0; mark[temp.first] = true; dfs1(temp.first); for (int i = 1; i <= n; i++) { mark[i] = false; } dis2[temp.second] = 0; mark[temp.second] = true; dfs2(temp.second); for (int i = 1; i <= n; i++) { mark[i] = false; } int ans = 0; for (int i = 1; i <= n; i++) { if (max(dis1[i], dis2[i]) <= d) { ans++; } } cout << ans; }
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : er1.v
// Description:
// This module is where the ER1 register implemented. ER1 and ER2 registers
// can be registers implemented in Lattice FPGAs using normal FPGA's
// programmable logic resources. Once they are implemented, they can be
// accessed as if they are JTAG data registers through the FPGA JTAG port.
// In order to accessing these registers, JTAG instructions ER1(0x32) or
// ER2(0x38) needs to be written to the JTAG IR register for enabling the
// ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be
// enabled one at a time. Once they are enabled, they will be disabled if
// another JTAG instruction is written into the JTAG instruction register.
// The registers allow dynamically accessing the FPGA internal information
// even when the device is running. Therefore, they are very useful for some
// of the IP cores. In order to let ER1/ER2 registers shared by multiple IP
// cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
// The ER1/ER2 structure allows only one ER1 register but more than one ER2
// registers in an FPGA device. Please refer to the related document for
// this patterned ER1/ER2 structure.
// Dependencies : None
// Version : 6.0.14
// : Initial Version
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
module ER1 (input JTCK,
input JTDI,
output JTDO1,
output reg JTDO2,
input JSHIFT,
input JUPDATE,
input JRSTN,
input JCE1,
input [14:0] ER2_TDO,
output reg [14:0] IP_ENABLE,
input ISPTRACY_ER2_TDO,
output ISPTRACY_ENABLE,
output CONTROL_DATAN)/* synthesis syn_hier = hard */;
wire controlDataNBit;
wire ispTracyEnableBit;
wire [3:0] encodedIpEnableBits;
wire [9:0] er1TdiBit;
wire captureDrER1;
assign JTDO1 = er1TdiBit[0];
TYPEB BIT0 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[1]),
.TDO(er1TdiBit[0]),
.DATA_IN(1'b0),
.CAPTURE_DR(captureDrER1));
TYPEB BIT1 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[2]),
.TDO(er1TdiBit[1]),
.DATA_IN(1'b0),
.CAPTURE_DR(captureDrER1));
TYPEB BIT2 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[3]),
.TDO(er1TdiBit[2]),
.DATA_IN(1'b1),
.CAPTURE_DR(captureDrER1));
TYPEA BIT3 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[4]),
.TDO(er1TdiBit[3]),
.DATA_OUT(controlDataNBit),
.DATA_IN(controlDataNBit),
.CAPTURE_DR(captureDrER1),
.UPDATE_DR(JUPDATE));
assign CONTROL_DATAN = controlDataNBit;
TYPEA BIT4 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[5]),
.TDO(er1TdiBit[4]),
.DATA_OUT(ispTracyEnableBit),
.DATA_IN(ispTracyEnableBit),
.CAPTURE_DR(captureDrER1),
.UPDATE_DR(JUPDATE)
);
assign ISPTRACY_ENABLE = ispTracyEnableBit;
TYPEA BIT5 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[6]),
.TDO(er1TdiBit[5]),
.DATA_OUT(encodedIpEnableBits[0]),
.DATA_IN(encodedIpEnableBits[0]),
.CAPTURE_DR(captureDrER1),
.UPDATE_DR(JUPDATE));
TYPEA BIT6 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[7]),
.TDO(er1TdiBit[6]),
.DATA_OUT(encodedIpEnableBits[1]),
.DATA_IN(encodedIpEnableBits[1]),
.CAPTURE_DR(captureDrER1),
.UPDATE_DR(JUPDATE));
TYPEA BIT7 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[8]),
.TDO(er1TdiBit[7]),
.DATA_OUT(encodedIpEnableBits[2]),
.DATA_IN(encodedIpEnableBits[2]),
.CAPTURE_DR(captureDrER1),
.UPDATE_DR(JUPDATE));
TYPEA BIT8 (.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(JCE1),
.TDI(er1TdiBit[9]),
.TDO(er1TdiBit[8]),
.DATA_OUT(encodedIpEnableBits[3]),
.DATA_IN(encodedIpEnableBits[3]),
.CAPTURE_DR(captureDrER1),
.UPDATE_DR(JUPDATE)
);
assign er1TdiBit[9] = JTDI;
assign captureDrER1 = !JSHIFT & JCE1;
always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
begin
case (encodedIpEnableBits)
4'h0: begin
IP_ENABLE <= 15'b000000000000000;
JTDO2 <= ISPTRACY_ER2_TDO;
end
4'h1: begin
IP_ENABLE <= 15'b000000000000001;
JTDO2 <= ER2_TDO[0];
end
4'h2: begin
IP_ENABLE <= 15'b000000000000010;
JTDO2 <= ER2_TDO[1];
end
4'h3: begin
IP_ENABLE <= 15'b000000000000100;
JTDO2 <= ER2_TDO[2];
end
4'h4: begin
IP_ENABLE <= 15'b000000000001000;
JTDO2 <= ER2_TDO[3];
end
4'h5: begin
IP_ENABLE <= 15'b000000000010000;
JTDO2 <= ER2_TDO[4];
end
4'h6: begin
IP_ENABLE <= 15'b000000000100000;
JTDO2 <= ER2_TDO[5];
end
4'h7: begin
IP_ENABLE <= 15'b000000001000000;
JTDO2 <= ER2_TDO[6];
end
4'h8: begin
IP_ENABLE <= 15'b000000010000000;
JTDO2 <= ER2_TDO[7];
end
4'h9: begin
IP_ENABLE <= 15'b000000100000000;
JTDO2 <= ER2_TDO[8];
end
4'hA: begin
IP_ENABLE <= 15'b000001000000000;
JTDO2 <= ER2_TDO[9];
end
4'hB: begin
IP_ENABLE <= 15'b000010000000000;
JTDO2 <= ER2_TDO[10];
end
4'hC: begin
IP_ENABLE <= 15'b000100000000000;
JTDO2 <= ER2_TDO[11];
end
4'hD: begin
IP_ENABLE <= 15'b001000000000000;
JTDO2 <= ER2_TDO[12];
end
4'hE: begin
IP_ENABLE <= 15'b010000000000000;
JTDO2 <= ER2_TDO[13];
end
4'hF: begin
IP_ENABLE <= 15'b100000000000000;
JTDO2 <= ER2_TDO[14];
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[100005] = {0}, b[100005] = {0}, t, j, i, rn = 0, r[100005] = {0}, dis[100005] = {0}; vector<int> v; vector<int> ht; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] == 1) ht.push_back(i); } for (i = 1; i <= n; i++) { scanf( %d , &b[i]); dis[b[i]]++; } for (i = 0; i < ht.size(); i++) { v.clear(); v.push_back(ht[i]); while (1) { t = v.size(); if (b[v[t - 1]] == 0) { break; } if (dis[b[v[t - 1]]] == 1) v.push_back(b[v[t - 1]]); else break; } if (rn < v.size()) { rn = v.size(); for (j = 0; j < rn; j++) r[j] = v[j]; } } printf( %d n , rn); for (i = rn - 1; i >= 0; i--) printf( %d%c , r[i], i ? : n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int mod, h1, a1, x1, y1, h2, a2, x2, y2, c1, c2, i, ans = 0, temp, j, m1, m2, h11, h12; cin >> mod; cin >> h1 >> a1; cin >> x1 >> y1; cin >> h2 >> a2; cin >> x2 >> y2; temp = h2; ans = 0; h11 = h1; h12 = h2; for (i = 1; i <= mod + 10; i++) { ans++; h11 = (x1 * h11 + y1) % mod; h12 = (x2 * h12 + y2) % mod; if (h11 == a1 && h12 == a2) { cout << ans << endl; return 0; } } ans = 0; for (i = 1; i <= mod + 10 && h1 != a1; i++) { ans++; h1 = (x1 * h1 + y1) % mod; h2 = (x2 * h2 + y2) % mod; } if (h1 != a1) { cout << -1 << endl; return 0; } if (h1 == a1 && h2 == a2) { cout << ans << endl; return 0; } c1 = 0; for (i = 1; i <= mod + 10 && temp != a2; i++) { c1++; temp = (x2 * temp + y2) % mod; } if (temp != a2) { cout << -1 << endl; return 0; } long long int p, q, r, s; p = ans; q = c1; a1 = h1; h1 = (x1 * h1 + y1) % mod; ans = 1; for (i = 1; i <= mod + 10 && h1 != a1; i++) { ans++; h1 = (x1 * h1 + y1) % mod; } if (h1 != a1) { cout << -1 << endl; return 0; } r = ans; ans = 1; a2 = temp; h2 = temp; h2 = (x2 * h2 + y2) % mod; for (i = 1; i <= mod + 10 && h2 != a2; i++) { ans++; h2 = (x2 * h2 + y2) % mod; } if (h2 != a2) { cout << -1 << endl; return 0; } s = ans; if (p + r == q + s) { cout << p + r << endl; return 0; } for (i = 1; i <= mod + 10; i++) { j = (p - q + r * i) / s; if (p + i * r == q + j * s) { cout << p + i * r << endl; return 0; } } cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) const long long INF = 0x3f3f3f3f3f3f3f3f; const long long llinf = (1LL << 61); const int inf = (1 << 30); const int nmax = 1e3 + 50; const int mod = 1e9 + 7; using namespace std; int n, m, i, j, a[nmax][nmax], aa[nmax][nmax], b[nmax][nmax], bb[nmax][nmax], ca[nmax][nmax], cb[nmax][nmax], mn; char c[nmax][nmax]; vector<pair<pair<int, int>, int> > ans; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n >> m; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) cin >> c[i][j]; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) if (c[i][j] == * ) a[i][j] = a[i][j - 1] + 1; for (j = m; j >= 1; j--) if (c[i][j] == * ) aa[i][j] = aa[i][j + 1] + 1; } for (i = 1; i <= m; i++) { for (j = 1; j <= n; j++) if (c[j][i] == * ) b[j][i] = b[j - 1][i] + 1; for (j = n; j >= 1; j--) if (c[j][i] == * ) bb[j][i] = bb[j + 1][i] + 1; } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (c[i][j] == * ) { mn = min(min(a[i][j], aa[i][j]), min(b[i][j], bb[i][j])); if (mn > 1) { ca[i][j - mn + 1]++; ca[i][j + mn]--; cb[i - mn + 1][j]++; cb[i + mn][j]--; ans.push_back({{i, j}, mn - 1}); } } } } for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) ca[i][j] += ca[i][j - 1]; for (i = 1; i <= m; i++) for (j = 1; j <= n; j++) cb[j][i] += cb[j - 1][i]; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) if (c[i][j] == * && !ca[i][j] && !cb[i][j]) return cout << -1 << endl, 0; cout << ans.size() << endl; for (i = 0; i < ans.size(); i++) cout << ans[i].first.first << << ans[i].first.second << << ans[i].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; struct data { int t, g; }; int memo[250][4][66000]; int n, t; data in[20]; int f(int time, int genre, int bit) { if (memo[time][genre][bit] != -1) return memo[time][genre][bit]; if (time == t) return memo[time][genre][bit] = 1; if (time > t) return memo[time][genre][bit] = 0; int RE = 0; for (int i = 0; i < n; i++) if (in[i].g != genre && !(bit & (1 << i))) { RE = (RE + f(time + in[i].t, in[i].g, bit | (1 << i))) % mod; } return memo[time][genre][bit] = RE; } int main() { cin >> n >> t; for (int i = 0; i < n; i++) cin >> in[i].t >> in[i].g; memset(memo, -1, sizeof(memo)); cout << f(0, 0, 0); }
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#include <bits/stdc++.h> using namespace std; const int N = 3003 * 6006; const int qwq = 303030; const int inf = 0x3f3f3f3f; int n, m, k; int f[N], fa[N], st[123], cnt; int ans; int ff[] = {1, 1, 1, 0, -1, -1, -1, 0}; int gg[] = {1, 0, -1, -1, -1, 0, 1, 1}; inline int read() { int sum = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum * f; } inline int dian(int x, int y) { if (y == 0) y = 2 * m; if (y == 2 * m + 1) y = 1; return (x - 1) * (m << 1) + y; } int find(int u) { while (fa[u] != u) u = fa[u]; return u; } int Splay(int u) { return fa[u] == u ? u : fa[u] = Splay(fa[u]); } int main() { int x, y; n = read(); m = read(); k = read(); if (m == 1) { cout << 0; return 0; } for (int i = 1; i <= n * m * 2; i++) fa[i] = i; while (k--) { cnt = 0; x = read(); y = read(); for (int i = 0; i <= 8; i++) { if (x + ff[i] < 1 || x + ff[i] > n) continue; int u = dian(x + ff[i], y + gg[i]); if (!f[u]) continue; int aa = find(u); int bb = find(dian(x, y)); if (aa == bb) continue; st[++cnt] = bb; fa[bb] = aa; } y += m; for (int i = 0; i < 8; i++) { if (x + ff[i] < 1 || x + ff[i] > n) continue; int u = dian(x + ff[i], y + gg[i]); if (!f[u]) continue; int aa = find(u); int bb = find(dian(x, y)); if (aa == bb) continue; st[++cnt] = bb; fa[bb] = aa; } y -= m; if (find(dian(x, y)) != find(dian(x, y + m))) { ans++; for (int i = 0; i < 8; i++) { if (x + ff[i] < 1 || x + ff[i] > n) continue; Splay(dian(x + ff[i], y + gg[i])); } y += m; for (int i = 0; i < 8; i++) { if (x + ff[i] < 1 || x + ff[i] > n) continue; Splay(dian(x + ff[i], y + gg[i])); } y -= m; f[dian(x, y)] = f[dian(x, y + m)] = 1; } else { for (int i = 1; i <= cnt; i++) fa[st[i]] = st[i]; } } cout << ans; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer i;
reg [63:0] b;
real r, r2;
integer cyc=0;
realtime uninit;
initial if (uninit != 0.0) $stop;
sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
initial begin
if (1_00_0.0_1 != 1000.01) $stop;
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
// bug
r = $bitstoreal($realtobits(1.414));
if (r != 1.414) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_cast_bug374(input clk, input [4:0] cyc5);
integer i;
always @(posedge clk) begin
i <= integer'(cyc5);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[5050][5050], q[5050][5050]; int ans[5050], len; char s[5050]; void init() { for (int i = 0; i < len; i++) { int l = 0; while (i - l >= 0 && i + l < len && s[i - l] == s[i + l]) dp[i - l][i + l] = 1, l++; l = 0; while (i - l >= 0 && i + 1 + l < len && s[i - l] == s[i + l + 1]) dp[i - l][i + l + 1] = 1, l++; } } void solve() { for (int t = 0; t < len; t++) { for (int j = 0; j + t < len; j++) { if (!dp[j][j + t]) continue; int mid; if (t % 2 == 0) mid = (j + j + t) / 2 - 1; else mid = (j + j + t) / 2; if (mid < j) q[j][j + t] = 1; else q[j][j + t] = q[j][mid] + 1; ans[q[j][j + t]]++; } } } int main() { scanf( %s , s); len = strlen(s); memset(dp, 0, sizeof(dp)), memset(ans, 0, sizeof(ans)), memset(q, 0, sizeof(q)); init(); solve(); for (int i = len - 1; i >= 1; i--) ans[i] += ans[i + 1]; for (int i = 1; i <= len; i++) { if (i == 1) printf( %d , ans[i]); else printf( %d , ans[i]); } printf( n ); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1(clk, ce, a, b, p);
input clk;
input ce;
input[8 - 1 : 0] a; // synthesis attribute keep a "true"
input[6 - 1 : 0] b; // synthesis attribute keep b "true"
output[14 - 1 : 0] p;
reg[14 - 1 : 0] p;
wire [14 - 1 : 0] tmp_product;
assign tmp_product = a * b;
always @ (posedge clk) begin
if (ce) begin
p <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105][105], b, c, d, e, f, g, h, i, j, k, l, m, n; inline bool pd(int x, int y, int s) { return a[x - 1][y] == s || a[x + 1][y] == s || a[x][y - 1] == s || a[x][y + 1] == s; } int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) if (!a[i][j]) { if (i == 3 && j == 21) { k = 1; } for (k = 1; k <= 26; k++) if (!pd(i, j, k)) { for (l = 1; l <= n; l++) { if (i + l > n || j + l > m) break; d = 0; for (g = j; g <= j + l; g++) if (a[i + l][g] || pd(i + l, g, k)) { d = 1; break; } if (d) break; for (g = i; g <= i + l; g++) if (a[g][j + l] || pd(g, j + l, k)) { d = 1; break; } if (d) break; for (g = 1; g < k; g++) if (!pd(i, j + l, g)) d = 1; if (d) break; } l--; for (d = i; d <= i + l; d++) for (e = j; e <= j + l; e++) a[d][e] = k; break; } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) putchar(a[i][j] + A - 1); printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> long long arr[100005]; using namespace std; int main() { cin.tie(0); std::ios::sync_with_stdio(false); ; int n; cin >> n; for (int i = 0; i < n; cin >> arr[i++]) ; sort(arr, arr + n); cout << arr[n - 1] << ; for (int i = 1; i < n - 1; i++) { cout << arr[i] << ; } cout << arr[0]; }
|
// taken from the Apple II project by Alex Freed
// and modified for own use
module ramcard(mclk28,reset_in,addr,ram_addr, we, card_ram_we,card_ram_rd, bank1);
input mclk28;
input reset_in;
input [15:0] addr;
output [17:0] ram_addr;
input we;
output card_ram_we;
output card_ram_rd;
output bank1;
reg bank1, read_en, write_en, pre_wr_en, bankB, sat_read_en, sat_write_en, sat_pre_wr_en, sat_en;
reg [2:0] bank16k;
reg [15:0] addr2;
wire Dxxx,DEF;
always @(posedge mclk28) begin
addr2 <= addr;
if(reset_in) begin
bank1 <= 0;
read_en <= 0;
write_en <= 1;
pre_wr_en <= 0;
bankB <= 0;
sat_read_en <= 0;
sat_write_en <= 0;
sat_pre_wr_en <= 0;
end
else
begin
if((addr[15:4] == 'hC08) & (addr2 != addr)) begin
// Looks like a Language Card in slot 0
bank1 <= addr[3];
pre_wr_en <= addr[0] & ~we;
write_en <= addr[0] & pre_wr_en & ~we;
read_en <= ~(addr[0] ^ addr[1]);
end
if((addr[15:4] == 'hC0D) & (addr2 != addr)) begin
// Looks like Saturn128 Card in slot 5
if(addr[2] == 0) begin
// State selection
bankB <= addr[3];
sat_pre_wr_en <= addr[0];
sat_write_en <= addr[0] & sat_pre_wr_en;
sat_read_en <= ~(addr[0] ^ addr[1]);
end
else
begin
// 16K bank selection
bank16k <= {addr[3], addr[1], addr[0]};
end
end
end
end
assign Dxxx = (addr[15:12] == 4'b1101);
assign DEF = ((addr[15:14] == 2'b11) & (addr[13:12] != 2'b00));
assign ram_addr = ((sat_write_en || sat_read_en) && DEF)?{1'b1, bank16k, addr[13], addr[12] & ~(bankB & Dxxx), addr[11:0]}:{2'b0,addr[15:13], addr[12] & ~(bank1 & Dxxx), addr[11:0]};
assign card_ram_we = (write_en | sat_write_en);
assign card_ram_rd = (read_en | sat_read_en);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); double fixAngle(double A) { return A > 1 ? 1 : (A < -1 ? -1 : A); } double dcmp(double a, double b) { return fabs(a - b) < 1e-6 ? 0 : a > b ? 1 : -1; } const int MAX_SIZE = 3e5 + 5; const int MOD = 1e9 + 7; int r = 0; long long segtree[MAX_SIZE * 4]; void update(long long L, long long R, long long t, long long val, long long idx) { if (L == R && R == t) { segtree[idx] += val; segtree[idx] %= MOD; return; } if (L > t || R < t) return; update(L, (L + R) / 2, t, val, idx * 2); update((L + R) / 2 + 1, R, t, val, idx * 2 + 1); segtree[idx] = (segtree[idx * 2] + segtree[idx * 2 + 1]) % MOD; } long long query(long long L, long long R, long long tl, long long tr, long long idx) { if (L >= tl && R <= tr) { return segtree[idx] % MOD; } if (L > tr || R < tl) return 0; return (query(L, (L + R) / 2, tl, tr, idx * 2) + query((L + R) / 2 + 1, R, tl, tr, idx * 2 + 1)) % MOD; } map<long long, long long> rnk; int main() { set<long long> tmp; long long n, m, a, b; vector<pair<long long, long long> > data; cin >> n >> m; tmp.insert(0); tmp.insert(n); for (long long i = 0; i < m; i++) { cin >> a >> b; data.push_back({b, a}); tmp.insert(a); tmp.insert(b); tmp.insert(b - 1); } for (long long x : tmp) { rnk[x] = ++r; } sort(data.begin(), data.end()); update(0, MAX_SIZE - 1, 1, 1, 1); for (int i = 0; i < m; i++) { swap(data[i].second, data[i].first); int x = query(0, MAX_SIZE - 1, rnk[data[i].first], rnk[data[i].second - 1], 1); update(0, MAX_SIZE - 1, rnk[data[i].second], x, 1); } cout << query(0, MAX_SIZE - 1, rnk[n], rnk[n], 1) % MOD; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__BUFINV_FUNCTIONAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0); int t; cin >> t; while (t--) { map<int, int>L, R; int bal = 0; string s; cin >> s; for (char &c : s) { if (c == 1 ) { R[bal]++; bal++; } else { L[bal]++; bal--; } } int cur = 0; while (L[cur] > 0 || R[cur] > 0) { if (L[cur] > 0 && R[cur - 1] > 0 || (!R[cur] && !L[cur + 1])) { L[cur]--; cur--; cout << 0; } else { R[cur]--; cur++; cout << 1; } } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 234567; int n; vector<int> e[N]; int f[N]; void dfs(int u, int p) { int go_before_parent = 0; int go_after_parent = 0; for (int i = 0; i < e[u].size(); ++i) { int v = e[u][i]; if (v == p) { continue; } dfs(v, u); if (f[v] == 0) { ++go_before_parent; } else { ++go_after_parent; } } int son_degree = go_after_parent; if (son_degree & 1) { f[u] = 0; } else { f[u] = 1; } } void print_solution(int u, int p) { for (int i = 0; i < e[u].size(); ++i) { int v = e[u][i]; if (v == p) { continue; } if (f[v] == 0) { print_solution(v, u); } } cout << u << endl; for (int i = 0; i < e[u].size(); ++i) { int v = e[u][i]; if (v == p) { continue; } if (f[v] == 1) { print_solution(v, u); } } } int main() { cin >> n; for (int i = 1, j; i <= n; ++i) { cin >> j; if (j != 0) { e[i].push_back(j); e[j].push_back(i); } } dfs(1, 0); if (f[1] == 0) { cout << NO << endl; return 0; } cout << YES << endl; print_solution(1, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if (b == 1 && a == 9) { cout << 9 10 << endl; } else if (b - a == 1) { cout << a << << b << endl; } else if (a == b) { cout << a << 1 << b << 2 << endl; } else { cout << -1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 100000; const long long oops = 1LL << 60; class Ball { public: long long value, color; } arr[MAXN + 5]; long long colorBest[MAXN + 5]; long long n; void addToTopTwo(vector<pair<long long, int> >& toptwo, long long best, long long color) { if (toptwo.size() != 2) toptwo.push_back(make_pair(best, color)); else { long long c, c2; bool khalas = 0; for (c = 0; c < 2; c++) if (toptwo[c].second == color) { toptwo[c].first = max(toptwo[c].first, best); khalas = 1; } if (!khalas) { if (toptwo[0].first > toptwo[1].first) { if (toptwo[1].first < best) toptwo[1] = make_pair(best, color); } else { if (toptwo[0].first < best) toptwo[0] = make_pair(best, color); } } } return; } int main() { long long c, c2; long long qs; scanf( %I64d%I64d , &n, &qs); for (c = 0; c < n; c++) scanf( %I64d , &arr[c].value); for (c = 0; c < n; c++) scanf( %I64d , &arr[c].color); for (long long loops = 0; loops < qs; loops++) { for (c = 0; c <= n; c++) { colorBest[c] = -oops; } long long a, b; scanf( %I64d%I64d , &a, &b); long long ret = -oops; vector<pair<long long, int> > toptwo; for (c = 0; c < n; c++) { long long best = b * (long long)arr[c].value; if (colorBest[arr[c].color] != -oops) best = max(best, colorBest[arr[c].color] + a * (long long)arr[c].value); for (c2 = 0; c2 < toptwo.size(); c2++) if (toptwo[c2].second != arr[c].color) best = max(best, toptwo[c2].first + b * (long long)arr[c].value); colorBest[arr[c].color] = max(colorBest[arr[c].color], best); addToTopTwo(toptwo, best, arr[c].color); ret = max(ret, best); } printf( %I64d n , max(ret, 0LL)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string tos(int a) { ostringstream os( ); os << a; return os.str(); } const int MAXN = 1000000; bool isp[MAXN + 100]; int main() { ios_base::sync_with_stdio(0); for (int i = 0; i <= MAXN; ++i) isp[i] = 1; isp[0] = isp[1] = 1; for (int i = 2; i <= MAXN; ++i) if (isp[i]) for (int j = i + i; j <= MAXN; j += i) isp[j] = 0; int n; while (cin >> n) { int x, y; for (int i = 2; i < MAXN; ++i) { x = i, y = n - x; if (!isp[x] && !isp[y]) break; } cout << x << << y << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool debug = 0; long long a[26], dp[26][26]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tc = 1; while (tc--) { string s; cin >> s; int n = s.length(); long long mx = 0; for (int i = 0; i < n; i++) { int x = s[i] - a ; for (int j = 0; j < 26; j++) { dp[j][x] += a[j]; mx = mx > dp[j][x] ? mx : dp[j][x]; } a[x]++; mx = mx > a[x] ? mx : a[x]; } cout << mx; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void smin(T& a, T val) { if (a > val) a = val; } template <class T> void smax(T& a, T val) { if (a < val) a = val; } template <typename T> inline std::ostream& operator<<(std::ostream& os, const std::vector<T>& v) { bool first = true; os << [ ; for (auto i : v) { if (!first) os << , ; os << i; first = false; } return os << ] ; } const int MAX = 100010; int n, u, e[MAX]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> u; cout << fixed << setprecision(20); for (int i = 0; i < n; ++i) { cin >> e[i]; } int l = 0, r = 0, tot = 0; long double ans1 = -1.0; while (l < n) { tot = 0; while (r < n and (e[r] - e[l]) <= u) { ++r; } if ((r - l) > 2) { int t = r - 1; ans1 = max(ans1, (long double)(1. * (e[t] - e[l + 1])) / (1. * (e[t] - e[l]))); } ++l; } cout << ans1; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> V; void dfs(long long x) { if (x < 1000000000) { V.push_back(x); dfs(x * 10 + 4); dfs(x * 10 + 7); } } int main() { dfs(0); V.push_back(INT_MAX); sort(V.begin(), V.end()); int pl, pr, vl, vr, k; cin >> pl >> pr >> vl >> vr >> k; double cnt = 0; double all = ((vr - vl) + 1.0) * ((pr - pl) + 1.0); for (int i = 1; i < V.size() - k; i++) { int hll = V[i - 1] + 1; int hl = V[i]; int hr = V[(i + k) - 1]; int hrr = V[(i + k)] - 1; if (pl <= hl && pr >= hll && vl <= hrr && vr >= hr) { cnt += (min(pr, hl) - max(pl, hll) + 1.0) * (min(vr, hrr) - max(vl, hr) + 1.0); } if (vl <= hl && vr >= hll && pl <= hrr && pr >= hr) { cnt += (min(vr, hl) - max(vl, hll) + 1.0) * (min(pr, hrr) - max(pl, hr) + 1.0); if (k == 1) cnt -= 1.0; } } printf( %.12f , cnt / all); exit: return (0); }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 16:49:02 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../open.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.5 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: inst_t_e.v,v $
// Revision 1.5 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [2:0] non_open;
wire non_open_bit;
wire [3:0] wire_open;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
wire [3:0] mix_dmy_open_0; //__I_OPEN_DUMMY
wire mix_dmy_open_1; //__I_OPEN_DUMMY
wire mix_dmy_open_2; //__I_OPEN_DUMMY
wire mix_dmy_open_3; //__I_OPEN_DUMMY
wire [2:0] mix_dmy_open_4; //__I_OPEN_DUMMY
inst_a_e inst_a (
.open_bit(),
.open_bus(),
.open_bus_9(),
.open_in_bit_11(),
.open_in_bus_10(),
.open_part12({ non_open_bit, mix_dmy_open_0, non_open }), // __W_PORT // from 5 to 3 // __W_PORT // __I_BIT_TO_BUSPORT // __I_COMBINE_SPLICES
.open_part13({ mix_dmy_open_3, non_open_bit, mix_dmy_open_2, mix_dmy_open_1, non_open }), // __W_PORT // __I_BIT_TO_BUSPORT (x4) // __I_COMBINE_SPLICES
.openport14(), // check width and type
.wire_open({ mix_dmy_open_4, wire_open }), // __W_PORT (x2) // __I_COMBINE_SPLICES
.wire_open_in(wire_open)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.mix_key_open(), // replace name
.non_open(non_open),
.non_open_bit(non_open_bit),
.open_bit_2(),
.open_bit_3(),
.open_bit_4()
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[500005], b[500005], reach[500005][19]; int tree[4 * 500005][19]; void build(int i, int layer, int low, int high) { if (low == high) { tree[i][layer] = reach[low][layer]; return; } int mid = (low + high) / 2; build(2 * i, layer, low, mid); build(2 * i + 1, layer, mid + 1, high); tree[i][layer] = min(tree[2 * i][layer], tree[2 * i + 1][layer]); } int get(int i, int layer, int low, int high, int u, int v) { if (v < low || high < u) return 500005; if (u <= low && high <= v) return tree[i][layer]; int mid = (low + high) / 2; return min(get(2 * i, layer, low, mid, u, v), get(2 * i + 1, layer, mid + 1, high, u, v)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); a[i + n] = a[i]; } m = 2 * n - 1; for (int i = 1; i <= m; i++) { b[i] = i - a[i]; reach[i][0] = max(1, b[i]); } build(1, 0, 1, m); for (int j = 1; j < 19; j++) { for (int i = 1; i <= m; i++) reach[i][j] = get(1, j - 1, 1, m, reach[i][j - 1], i); build(1, j, 1, m); } long long ret = 0; for (int end = n; end <= m; end++) { int moves = 0; int prev = end; for (int j = 19 - 1; j >= 0; j--) { int tmp = get(1, j, 1, m, prev, end); if (tmp > end - n + 1) { moves += 1 << j; prev = tmp; } } moves++; ret += moves; } cout << ret << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, sum = 0, s[100005], ans[100005], an = 0; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &s[i]); sum += s[i]; } if (sum % k) { printf( No ); return 0; } int m = sum / k; int now = 0, len = 0; for (int i = 1; i <= n; i++) { if (now + s[i] > m) { printf( No ); return 0; } now += s[i]; len++; if (now == m) { ans[++an] = len; now = len = 0; } } printf( Yes n ); for (int i = 1; i <= k; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 5e2 + 10; const int P = 239017; const int INF = 1e9; const int MOD = 1e9 + 7; int dp[MaxN][MaxN][2], n, m, q; char s[MaxN][MaxN]; int get(int xl, int yl, int xr, int yr, int c) { if (c == 0 && xl > xr) { return 0; } if (c == 1 && yl > yr) { return 0; } return dp[xr][yr][c] + dp[xl - 1][yl - 1][c] - dp[xr][yl - 1][c] - dp[xl - 1][yr][c]; } int main() { scanf( %d%d n , &n, &m); for (int i = 1; i <= n; ++i) { gets(s[i] + 1); } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { dp[i][j][0] = dp[i - 1][j][0] + dp[i][j - 1][0] - dp[i - 1][j - 1][0] + (s[i - 1][j] == s[i][j] && s[i][j] == . ); dp[i][j][1] = dp[i - 1][j][1] + dp[i][j - 1][1] - dp[i - 1][j - 1][1] + (s[i][j - 1] == s[i][j] && s[i][j] == . ); } } scanf( %d , &q); while (q-- > 0) { int xl, yl, xr, yr; scanf( %d%d%d%d , &xl, &yl, &xr, &yr); printf( %d n , get(xl + 1, yl, xr, yr, 0) + get(xl, yl + 1, xr, yr, 1)); } return 0; }
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description :
// / /
// /__/ /\ Filename : MUXF9.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/unified/chen/g2ltw/g2ltw.pl
// Revision: 1.0
// 09/26/12 - 680234 - ncsim compile error
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MUXF9
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I0,
input I1,
input S
);
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1 ns / 1 ps
/*Copyright (c) 2015, EmbeddedCentric.com
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company: EmbeddedCentric.com
// Author: Ali Aljaani
// Create Date: 08/10/2015
// Description: AXI IP core to communicate with the 128x32 OLED screen on the Zedboard.
// ZedboardOLED_v1_0 is the top-level wrapper for the AXI-lite IP core
// Design Name: Lab3
// Module Name: ZedboardOLED_v1_0
// Project Name: ZedboardOLED
// Target Devices: XC7Z02CLG484
// Tool versions: Vivado 2015.2
//////////////////////////////////////////////////////////////////////////////////
module ZedboardOLED_v1_0 #
(
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
)
(
// Interface with the SSD1306 starts here
output wire SDIN,
output wire SCLK,
output wire DC,
output wire RES,
output wire VBAT,
output wire VDD,
// Interface with the SSD1306 ends here
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
ZedboardOLED_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) ZedboardOLED_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.SDIN(SDIN),
.SCLK(SCLK),
.DC(DC),
.RES(RES),
.VBAT(VBAT),
.VDD(VDD),
.S_AXI_RREADY(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long sign = 1; long long x = 0; char ch; while (!isdigit(ch = getchar())) if (ch == - ) sign = -1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * sign; } inline void wonl() { putchar( n ); } inline void wws() { putchar( ); } inline void dbg() { cout << endl; } inline void ww(long long k) { if (k < 0) putchar( - ), k *= -1; char ch[20]; int num = 0; while (k) ch[++num] = k % 10, k /= 10; if (num == 0) ch[++num] = 0; while (num) putchar(ch[num--] + 0 ); } const int N = 1e5 + 4; template <typename T, typename... V> inline void wonl(T t, V... v) { ww(t); if (sizeof...(v)) putchar( ); wonl(v...); } template <typename T, typename... V> inline void wws(T t, V... v) { ww(t); if (sizeof...(v)) putchar( ); wws(v...); } template <typename T, typename... V> inline void dbg(T t, V... v) { cout << << t; dbg(v...); } void solve() { int n = read(), a; map<int, int> ma; for (int i = 0; i < n; i++) a = read(), ma[a]++; vector<int> v; for (auto it : ma) v.push_back(it.second); sort(v.begin(), v.end()); reverse(v.begin(), v.end()); long long num = 1; while (v[0] >= num) num *= 2; long long fans = 0; while (num) { long long ter = num; long long a = INT_MAX; int k = 0; while (ter != 0 && k < v.size()) { a = min(a, v[k] / ter), ter = ter / 2, k++; } if (ter == 0) fans = max(fans, a * (num * 2 - 1)); num = num / 2; } wonl(fans); } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > &P, priority_queue<pair<long long, int> > &N, vector<long long> &ans, int k, int x) { while (k > 0) { int ps = P.size(), pn = N.size(); if (ps && pn) { pair<long long, int> pt = P.top(); P.pop(); pair<long long, int> nt = N.top(); N.pop(); int sign = (pn & 1) ? -1 : 1; if (nt.first * -1 <= pt.first) { nt.first += sign * x; if (nt.first >= 0) { P.push(nt); P.push(pt); } else { N.push(nt); P.push(pt); } } else { pt.first -= sign * x; if (pt.first < 0) { N.push(nt); N.push(pt); } else { N.push(nt); P.push(pt); } } } else if (ps) { pair<long long, int> pt = P.top(); P.pop(); pt.first -= x; if (pt.first < 0) { N.push(pt); } else { P.push(pt); } } else { pair<long long, int> nt = N.top(); N.pop(); int sign = (pn & 1) ? -1 : 1; nt.first += sign * x; if (nt.first >= 0) { P.push(nt); } else { N.push(nt); } } k--; } while (!P.empty()) { pair<long long, int> it = P.top(); P.pop(); ans[it.second] = it.first; } while (!N.empty()) { pair<long long, int> it = N.top(); N.pop(); ans[it.second] = it.first; } } int main() { int n, k, x, t; while (cin >> n >> k >> x) { priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > Qp; priority_queue<pair<long long, int> > Qn; for (int i = 0; i < n; i++) { cin >> t; if (t >= 0) Qp.push(make_pair(t, i)); else Qn.push(make_pair(t, i)); } vector<long long> ans(n); solve(Qp, Qn, ans, k, x); for (int i = 0; i < n; i++) cout << ans[i] << ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int arr[100000]; int n; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > q; int rankHash[100000]; int indHash[100000]; vector<pair<int, int> > ans; int main(void) { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , arr + i); bool isSorted = true; int lucky = -1; for (int i = 0; i < n - 1; i++) { if (arr[i + 1] < arr[i]) { isSorted = false; break; } } if (isSorted) { printf( 0 n ); return 0; } for (int i = 0; i < n; i++) { int tar = arr[i]; bool isLucky = true; while (tar) { if (tar % 10 != 4 && tar % 10 != 7) { isLucky = false; break; } tar /= 10; } if (isLucky) { lucky = i; break; } } if (lucky == -1) { printf( -1 n ); return 0; } for (int i = 0; i < n; i++) q.push(make_pair(arr[i], i)); for (int i = 0; i < n; i++) { rankHash[i] = q.top().second; q.pop(); } for (int i = 0; i < n; i++) indHash[rankHash[i]] = i; for (int i = 0; i < n; i++) { if (i != lucky) { ans.push_back(make_pair(i + 1, lucky + 1)); rankHash[indHash[i]] = lucky; rankHash[indHash[lucky]] = i; swap(indHash[i], indHash[lucky]); lucky = i; } if (lucky != rankHash[i]) { ans.push_back(make_pair(lucky + 1, rankHash[i] + 1)); int r1 = i; int r2 = indHash[lucky]; int i1 = rankHash[r1]; int i2 = rankHash[r2]; rankHash[r2] = i1; rankHash[r1] = lucky; swap(indHash[i1], indHash[i2]); lucky = i1; } } printf( %d n , (int)ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d %d n , ans[i].first, ans[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct TP {}; int ar[5][5]; int ans = 0; int nums[5]; bool used[10]; void cal(int pos) { if (pos == 5) { int tmp = 0; for (int x = 0; x < 5; x++) { for (int y = x; y < 4; y += 2) { tmp += ar[nums[y]][nums[y + 1]]; tmp += ar[nums[y + 1]][nums[y]]; } } ans = max(ans, tmp); return; } for (int i = 0; i < 5; i++) { if (!used[i]) { nums[pos] = i; used[i] = 1; cal(pos + 1); used[i] = 0; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); for (int i = 0; i < 5; i++) for (int j = 0; j < 5; j++) scanf( %d , &ar[i][j]); cal(0); printf( %d , ans); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int x[1000] = {4, 1, 1, 1, 2, 2, 2, 3, 3, 3}; int y[1000] = {2, 1, 2, 3, 1, 2, 3, 1, 2, 3}; int X[1005], Y[1005]; int main(int argc, char** argv) { int n; string a; cin >> n >> a; int mnx = 1e9, mny = 1e9, mxx = 0, mxy = 0; for (int i = 1; i < a.size(); i++) { X[i] = x[a[i] - 0 ] - x[a[i - 1] - 0 ]; Y[i] = y[a[i] - 0 ] - y[a[i - 1] - 0 ]; } int cnt = 0; for (int i = 1; i <= 4; i++) { for (int j = 1; j <= 3; j++) { if (i == 4 && j != 2) continue; ++cnt; int nowx = i, nowy = j; for (int k = 1; k < a.size(); k++) { nowx += X[k], nowy += Y[k]; if (nowx <= 3 && nowy <= 3 && nowx >= 1 && nowy >= 1 || (nowx == 4 && nowy == 2)) { } else { --cnt; break; } } } } if (cnt > 1) puts( NO ); else puts( YES ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &t) { t = 0; char ch = getchar(); int f = 1; while ( 0 > ch || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } do { (t *= 10) += ch - 0 ; ch = getchar(); } while ( 0 <= ch && ch <= 9 ); t *= f; } int n, pos, ans[2010], vis[2010]; struct node { long long x, y; bool operator<(node t) { if (x != t.x) return y < t.y; return x < t.x; } node operator-(node t) { return (node){x - t.x, y - t.y}; } long long operator*(node t) { return x * t.y - y * t.x; } } d[2010]; long long t; char s[2010]; int main() { read(n); for (int i = 1; i <= n; i++) read(d[i].x), read(d[i].y); scanf( %s , s + 1); for (int i = 1; i <= n; i++) if (!pos || d[i] < d[pos]) pos = i; ans[1] = pos; vis[pos] = 1; int tmp; for (int i = 2; i < n; i++) { tmp = 0; for (int j = 1; j <= n; j++) if (!vis[j]) { t = (d[j] - d[pos]) * (d[tmp] - d[pos]); if (!tmp || (s[i - 1] == L && t > 0) || (s[i - 1] == R && t < 0)) tmp = j; } ans[i] = pos = tmp; vis[pos] = 1; } for (int i = 1; i <= n; i++) if (!vis[i]) { ans[n] = i; break; } for (int i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100; const int M = 2e6 + 7; const int inf = 1e9; int n, m, mx, p[N], minn[N], D[M][2], sum = 0; int a[N][N]; bool check() { for (int t = 0, tE = (1 << mx) - 1; t <= tE; t++) { int ds = 0, bs = 0; for (int i = 1, iE = mx; i <= iE; i++) if (t & (1 << (i - 1))) ds += p[i]; if (!ds) continue; for (int i = 1, iE = mx; i <= iE; i++) if (t & (1 << (i - 1))) for (int j = 1, jE = mx; j <= jE; j++) if (t & (1 << (j - 1))) bs += a[i][j]; if (bs >= ds) return 0; } return 1; } int Cnt(int x) { return x == 0 ? 0 : Cnt(x / 10) + 1; } char sa[N], sb[N]; bool get() { for (int x = 1, xE = mx; x <= xE; x++) for (int i = 1, iE = mx; i <= iE; i++) if (a[x][i]) { a[x][i]--, p[x]--; if (check()) return printf( %d %d n , minn[x] + p[x], minn[i]), 1; a[x][i]++, p[x]++; a[x][i]--, p[i]--; if (check()) return printf( %d %d n , minn[x], minn[i] + p[i]), 1; a[x][i]++, p[i]++; } return 0; } int main() { scanf( %d , &n), mx = Cnt(n); for (int i = 1, iE = n; i <= iE; i++) p[Cnt(i)]++; minn[1] = 1; for (int i = 2, iE = mx; i <= iE; i++) minn[i] = minn[i - 1] * 10; for (int i = 1, iE = n - 1; i <= iE; i++) scanf( %s%s , sa, sb), D[i][0] = strlen(sa), D[i][1] = strlen(sb), a[D[i][0]][D[i][1]]++; if (!check()) return puts( -1 ), 0; while (get()) sum++; for (int x = 1, xE = mx; x <= xE; x++) for (int i = 1, iE = mx; i <= iE; i++) if (a[x][i]) printf( %d %d n , minn[x] + p[x] - 1, minn[i] + p[i] - 1), sum++; if (sum != n - 1) assert(0); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_SYMBOL_V
`define SKY130_FD_SC_LP__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_SYMBOL_V
|
#include <bits/stdc++.h> char ansStr[1000000]; int nextInt() { char ch; int s, x; do { ch = getchar(); } while (ch <= 32); if (ch == - ) { s = -1; ch = getchar(); } else s = 1; x = 0; while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return s * x; } int main(void) { int i, j; int n, ans, q, cnt; n = nextInt(); ans = 0; for (i = 0; i < n * n; i++) { int a; a = nextInt(); if (i % (n + 1) == 0) ans ^= a; } q = nextInt(); cnt = 0; while (q--) { int t; t = nextInt(); if (t == 3) ansStr[cnt++] = 0 + ans; else { nextInt(); ans ^= 1; } } puts(ansStr); return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_2_r_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_2_r_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=3,NUM_PORTS=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_r_0 (
In0,
In1,
In2,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
input wire [0 : 0] In2;
output wire [2 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(3),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> g[100005]; long long int vis[100005]; vector<double> ans; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; cin >> t; while (t--) { long long int a, b, c, d; cin >> a >> b >> c >> d; if ((b - a) % (c + d) == 0) cout << (b - a) / (c + d); else cout << -1; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int gi() { int x = 0, w = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) w = 0, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return w ? x : -x; } const int N = 3e5 + 5; int n, m, to[N << 1], nxt[N << 1], head[N], cnt, ls[N], rs[N], dis[N], rt[N], top[N], vis[N], key[N], tag[N]; long long ans; void cover(int x, int v) { if (!x) return; key[x] += v; tag[x] += v; } void down(int x) { if (!tag[x]) return; cover(ls[x], tag[x]); cover(rs[x], tag[x]); tag[x] = 0; } int merge(int x, int y) { if (!x || !y) return x | y; if (key[x] > key[y]) swap(x, y); down(x); rs[x] = merge(rs[x], y); if (dis[ls[x]] < dis[rs[x]]) swap(ls[x], rs[x]); dis[x] = dis[rs[x]] + 1; return x; } void dfs(int u, int f) { for (int e = head[u]; e; e = nxt[e]) if (to[e] ^ f) dfs(to[e], u), rt[u] = merge(rt[u], rt[to[e]]); if (u ^ 1) { vis[u] = 1; while (vis[top[rt[u]]]) rt[u] = merge(ls[rt[u]], rs[rt[u]]); if (!rt[u]) puts( -1 ), exit(0); ans += key[rt[u]]; cover(rt[u], -key[rt[u]]); } } int main() { n = gi(); m = gi(); for (int i = 1; i < n; ++i) { int u = gi(), v = gi(); to[++cnt] = v; nxt[cnt] = head[u]; head[u] = cnt; to[++cnt] = u; nxt[cnt] = head[v]; head[v] = cnt; } for (int i = 1; i <= m; ++i) { int u = gi(); top[i] = gi(); key[i] = gi(); rt[u] = merge(rt[u], i); } dfs(1, 0); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 55, M = 105, T = 20005, K = 20; const double S = 1e5, inf = 1e9, PI = acos(-1); template <class T> void read(T &x) { int sgn = 1; char ch; x = 0; for (ch = getchar(); (ch < 0 || ch > 9 ) && ch != - ; ch = getchar()) ; if (ch == - ) ch = getchar(), sgn = -1; for (; 0 <= ch && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; x *= sgn; } template <class T> void write(T x) { if (x < 0) putchar( - ), write(-x); else if (x < 10) putchar(x + 0 ); else write(x / 10), putchar(x % 10 + 0 ); } int n, m, t; double c, cost[M], dist[N], f[N][T], val[M][T]; complex<double> w[K][T << 3]; struct node { int id, to; vector<double> vec; }; vector<node> g[N]; vector<int> h[N]; queue<int> q; bool vis[N]; void spfa() { for (int i = 1; i <= n; i++) dist[i] = inf, vis[i] = false; dist[n] = true, q.push(n), dist[n] = 0.0; while (!q.empty()) { int u = q.front(); for (int i = 0; i < g[u].size(); i++) { int v = g[u][i].to; if (dist[v] > dist[u] + cost[g[u][i].id]) { dist[v] = dist[u] + cost[g[u][i].id]; if (!vis[v]) vis[v] = true, q.push(v); } } q.pop(), vis[u] = false; } } void init() { for (int i = 1, j = 0; i <= (t + 2 << 3); i <<= 1, j++) { for (int k = 0; k <= i; k++) w[j][k] = complex<double>(cos(2.0 * k * PI / i), sin(2.0 * k * PI / i)); } } int bitrev[T << 3]; void dft(complex<double> *x, int len, int ty) { bitrev[0] = 0; for (int i = 1; i < len; i++) { bitrev[i] = bitrev[i >> 1] >> 1; if (i & 1) bitrev[i] |= (len >> 1); } for (int i = 0; i < len; i++) { if (bitrev[i] < i) swap(x[bitrev[i]], x[i]); } for (int i = 1, label = 1; i < len; i <<= 1, label++) { for (int j = 0; j < len; j += (i << 1)) { for (int k = 0; k < i; k++) { complex<double> u = x[j + k], v = x[j + k + i]; complex<double> r = ty > 0 ? w[label][k] : w[label][(i << 1) - k]; x[j + k] = u + r * v, x[j + k + i] = u - r * v; } } } if (ty < 0) { for (int i = 0; i < len; i++) x[i] /= len; } } complex<double> tmp1[T << 3], tmp2[T << 3], tmp[T << 3]; void solve(int l, int r) { int mid = l + r >> 1; if (l < r) { solve(mid + 1, r); int l1 = r - mid, l2 = r - l, len = 1; while (len <= l1 + l2) len <<= 1; for (int i = 1; i <= n; i++) { if (r - l <= 1000) { for (int j = 0; j < g[i].size(); j++) { for (int k = l; k <= mid; k++) { for (int T = mid + 1 - k; T <= r - k; T++) val[g[i][j].id][k] += g[i][j].vec[T] * f[i][k + T]; } } continue; } for (int j = 0; j < len; j++) tmp1[j] = complex<double>(0.0, 0.0); for (int j = 0; j < r - mid; j++) tmp1[j] = complex<double>(f[i][mid + 1 + j], 0.0); dft(tmp1, len, 1); for (int j = 0; j < g[i].size(); j++) { for (int k = 0; k < len; k++) tmp2[k] = complex<double>(0.0, 0.0); for (int k = 0; k <= l2; k++) tmp2[k] = complex<double>(g[i][j].vec[l2 - k], 0.0); dft(tmp2, len, 1); for (int k = 0; k < len; k++) tmp[k] = tmp1[k] * tmp2[k]; dft(tmp, len, -1); for (int k = l; k <= mid; k++) val[g[i][j].id][k] += tmp[k + l2 - mid - 1].real(); } } solve(l, mid); } else { for (int i = 1; i <= n; i++) { for (int j = 0; j < h[i].size(); j++) f[i][mid] = min(f[i][mid], val[h[i][j]][mid] + cost[h[i][j]]); } } } int main() { read(n), read(m), read(t); scanf( %lf , &c); for (int i = 1; i <= m; i++) { int u, v; vector<double> vec(t + 1); read(u), read(v); scanf( %lf , &cost[i]); for (int j = 1; j <= t; j++) { int x; read(x); vec[j] = x / S; } node x = {i, u, vec}; g[v].push_back(x), h[u].push_back(i); } spfa(); for (int i = 1; i <= n; i++) f[i][t + 1] = dist[i] + c; for (int i = 1; i <= n; i++) { for (int j = 0; j <= t; j++) f[i][j] = (i == n) ? 0.0 : inf; } for (int i = 1; i <= m; i++) { for (int j = 0; j <= t; j++) val[i][j] = 0.0; } for (int i = 1; i <= n; i++) { for (int j = 0; j < g[i].size(); j++) { double x = 0.0; for (int k = 0; k <= t; k++) val[g[i][j].id][k] += x * f[i][t + 1], x += g[i][j].vec[t - k]; } } init(); solve(0, t); printf( %lf n , f[1][0]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:55 06/01/2016
// Design Name:
// Module Name: MUX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX(
input clk,
input [7:0] Estado,
input [5:0] Cuenta_Segundos,
input [5:0] Cuenta_Minutos,
input [4:0] Cuenta_Horas,
input [4:0] Cuenta_Year,
input [3:0] Cuenta_Mes,
input [6:0] Cuenta_Dia,
output reg [7:0] Salida_1,
output reg [7:0] Salida_2,
output reg [7:0] Salida_3
);
always @(posedge clk)
if (Estado == 8'h6C || Estado == 8'h75)
begin
Salida_1 <= Cuenta_Segundos;
Salida_2 <= Cuenta_Minutos;
Salida_3 <= Cuenta_Horas;
end
else
begin
Salida_1 <= Cuenta_Year;
Salida_2 <= Cuenta_Mes;
Salida_3 <= Cuenta_Dia;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100, PI = 3.14159265359, M = 1e9 + 7; long long a[N], ans = 1; int main() { long long n; cin >> n; long long x = 0, y = 0; for (int i = 0; i < n; i++) { long long a, b; cin >> a >> b; long long t1 = a - x, t2 = b - x; if (x == y) { ans += min(a, b) - x; } else if (x < y) { if (y <= a) { x = y; ans += min(a, b) - x + 1; } } else if (x > y) { if (x <= b) { y = x; ans += min(a, b) - x + 1; } } x = a, y = b; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int temp; int a[6] = {0}; int i = 0; while (n > 0) { a[i] = n % 2; n = n / 2; i++; } temp = a[0]; a[0] = a[4]; a[4] = temp; temp = a[2]; a[2] = a[3]; a[3] = temp; int count = 1; int sum = 0; for (int i = 0; i < 6; i++) { sum = sum + a[i] * count; count = count * 2; } cout << sum; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__FAHCIN_PP_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_PP_BLACKBOX_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_onchip_memory2_0 (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clk2,
clken,
clken2,
reset,
reset2,
reset_req,
reset_req2,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "nios_onchip_memory2_0.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 11: 0] address;
input [ 11: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clk2;
input clken;
input clken2;
input reset;
input reset2;
input reset_req;
input reset_req2;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire clocken1;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
assign clocken1 = clken2 & ~reset_req2;
assign wren2 = chipselect2 & write2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.numwords_b = 4096,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 12,
the_altsyncram.widthad_b = 12,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long n; long long deg[N], ans[N]; vector<pair<long long, long long> > g[N]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t = 1; while (t--) { long long x1, x2, y1, y2, z1, z2; cin >> x1 >> y1 >> z1; cin >> x2 >> y2 >> z2; bool x = x1 ^ x2; x = !x; bool y = y1 ^ y2; y = !y; bool z = z1 ^ z2; z = !z; if (x || y || z) cout << YES << n ; else cout << NO << n ; } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
module data_memory();
parameter ROWS = 133;
parameter COLS = 200;
// -- Modelo de memoria -------------------------------------- >>>>>
reg [7:0] MEM [0:(ROWS*COLS)-1];
// -- Rutina de inicializacion de memoria -------------------- >>>>>
initial
$readmemh("/home/hcabrera/Dropbox/tesis/noc/work/verilog/project_lancetfish/shared/scripts/python/data/133x200.dat", MEM);
// -- Task --------------------------------------------------- >>>>>
reg [0:63] memory_data;
task read;
input [31:0] address;
begin
address = address * 8;
$display("Address: ",address);
memory_data = {MEM[address], MEM[address + 1],
MEM[address + 2], MEM[address + 3],
MEM[address + 4], MEM[address + 5],
MEM[address + 6], MEM[address + 7]};
end
endtask : read
endmodule // data_memory
|
module test();
localparam [7:0] dly1 = 1;
wire [7:0] dly2 = 2;
reg [7:0] dly3 = 3;
reg i;
wire [6:1] o;
buf #(dly1, dly2) buf1(o[1], i);
buf #(dly2, dly1) buf2(o[2], i);
buf #(dly1, dly3) buf3(o[3], i);
buf #(dly3, dly1) buf4(o[4], i);
buf #(dly2, dly3+1) buf5(o[5], i);
buf #(4, 2) buf6(o[6], i);
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
i = 1'b1;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
i = 1'b0;
#0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1;
i = 1'bx;
#0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'b0)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
i = 1'bz;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; long long x; for (int i = 0; i < m; i++) { cin >> x; if (x > n) cout << 0 << endl; else { if (x % 2 == 1) cout << x / 2 + 1 << endl; else { long long a = x, b, c = n; while (1) { if (a % 2 == 1) break; b = a + (c - a / 2); a = b; } cout << a / 2 + 1 << endl; } } } }
|
module wb_ppfifo_2_mem(
input clk,
input rst,
output [31:0] debug,
//Control
input i_enable,
input [31:0] i_memory_0_base,
input [31:0] i_memory_0_size,
output [31:0] o_memory_0_count,
input i_memory_0_ready,
output o_memory_0_finished,
output o_memory_0_empty,
output [31:0] o_default_mem_0_base,
input [31:0] i_memory_1_base,
input [31:0] i_memory_1_size,
output [31:0] o_memory_1_count,
input i_memory_1_ready,
output o_memory_1_finished,
output o_memory_1_empty,
output [31:0] o_default_mem_1_base,
output reg o_write_finished,
input i_flush,
//master control signal for memory arbitration
output reg o_mem_we,
output reg o_mem_stb,
output reg o_mem_cyc,
output reg [3:0] o_mem_sel,
output [31:0] o_mem_adr,
output reg [31:0] o_mem_dat,
//output [31:0] o_mem_dat,
input [31:0] i_mem_dat,
input i_mem_ack,
input i_mem_int,
//Ping Pong FIFO Interface
input i_ppfifo_rdy,
output reg o_ppfifo_act,
output reg o_ppfifo_stb,
input [23:0] i_ppfifo_size,
input [31:0] i_ppfifo_data
);
//Local Parameters
//States
localparam IDLE = 4'h0;
localparam GET_MEMORY_BLOCK = 4'h1;
localparam WRITE_DATA = 4'h2;
localparam FINISHED = 4'h3;
//Registers/Wires
reg [23:0] r_ppfifo_count; //Ping Pong FIFO Count
reg [31:0] r_mem_read_size; //Current Memory Size to read
wire [31:0] w_mem_base [1:0];
reg [31:0] r_mem_ptr [1:0];
wire [31:0] r_mem_count [1:0];
wire [31:0] w_mem_0_ptr;
wire [31:0] w_mem_1_ptr;
wire [31:0] w_mem_0_count;
wire [31:0] w_mem_1_count;
wire [31:0] w_mem_0_base;
reg r_active_bank;
reg r_memory_ready;
reg [3:0] state;
//Submodules
//Asynchronous Logic
assign o_default_mem_0_base = 32'h00000000;
assign o_default_mem_1_base = 32'h00200000;
//assign o_mem_dat = i_ppfifo_data;
assign o_mem_adr = w_mem_base[r_active_bank] + r_mem_ptr[r_active_bank];
assign r_mem_count[0] = (i_memory_0_size > 0) ? i_memory_0_size - r_mem_ptr[0] : 32'h0;
assign r_mem_count[1] = (i_memory_1_size > 0) ? i_memory_1_size - r_mem_ptr[1] : 32'h0;
assign o_memory_0_empty = (r_mem_count[0] == 0) || (i_memory_0_size == 0);
assign o_memory_1_empty = (r_mem_count[1] == 0) || (i_memory_1_size == 0);
assign o_memory_0_finished = (r_mem_count[0] == 0) && (i_memory_0_size > 0);
assign o_memory_1_finished = (r_mem_count[1] == 0) && (i_memory_1_size > 0);
assign o_memory_0_count = r_mem_count[0];
assign o_memory_1_count = r_mem_count[1];
assign w_mem_0_ptr = r_mem_ptr[0];
assign w_mem_1_ptr = r_mem_ptr[1];
assign w_mem_base[0] = i_memory_0_base;
assign w_mem_base[1] = i_memory_1_base;
assign debug[0] = i_enable;
assign debug[1] = o_mem_cyc;
assign debug[2] = o_mem_stb;
assign debug[3] = o_mem_we;
assign debug[4] = i_mem_ack;
assign debug[5] = o_write_finished;
assign debug[8:6] = state;
assign debug[9] = o_ppfifo_act;
assign debug[10] = o_ppfifo_stb;
assign debug[11] = r_memory_ready;
assign debug[12] = r_active_bank;
assign debug[23:16] = o_mem_adr;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_write_finished <= 0;
//Wishbone Bus Signals
o_mem_we <= 0;
o_mem_stb <= 0;
o_mem_cyc <= 0;
o_mem_sel <= 4'b1111;
o_mem_dat <= 32'h00000000;
//Ping Pong FIFO Signals
o_ppfifo_act <= 0;
o_ppfifo_stb <= 0;
r_ppfifo_count <= 0;
//Memory Interface
r_mem_read_size <= 0;
r_mem_ptr[0] <= 0;
r_mem_ptr[1] <= 0;
state <= IDLE;
end
else begin
//De-assert Strobes
o_ppfifo_stb <= 0;
o_write_finished <= 0;
//Grab an Available FIFO if the core is activated
if (i_enable) begin
if (i_ppfifo_rdy && !o_ppfifo_act) begin
r_ppfifo_count <= 0;
o_ppfifo_act <= 1;
end
end
case (state)
IDLE: begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
o_mem_we <= 1;
if (i_enable) begin
state <= GET_MEMORY_BLOCK;
end
end
GET_MEMORY_BLOCK: begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
o_mem_we <= 1;
//Check if there is a memory block available
//If so get a reference to it
if (r_memory_ready) begin
r_mem_read_size <= r_mem_count[r_active_bank];
state <= WRITE_DATA;
r_mem_ptr[r_active_bank] <= 0;
end
else begin
if (!i_enable) begin
state <= IDLE;
end
end
end
WRITE_DATA: begin
if ((r_mem_ptr[r_active_bank] < r_mem_read_size) && r_memory_ready) begin
if (o_ppfifo_act) begin
//If the FIFO has data
//if (r_mem_ptr[r_active_bank] < i_ppfifo_size) begin
if (r_ppfifo_count < i_ppfifo_size) begin
o_mem_dat <= i_ppfifo_data;
o_mem_cyc <= 1;
o_mem_stb <= 1;
//Ping Pong FIFO has room
//if we received an ack, we have written a peice of data
if (i_mem_ack && o_mem_stb) begin
r_ppfifo_count <= r_ppfifo_count + 1;
r_mem_ptr[r_active_bank] <= r_mem_ptr[r_active_bank] + 1;
o_ppfifo_stb <= 1;
o_mem_stb <= 0;
end
end
else begin
//Release the Activate
//Release the Wishbone cycle so the host has a chance to write
//data
o_mem_cyc <= 0;
o_mem_stb <= 0;
o_ppfifo_act <= 0;
end
end
else begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
end
end
else begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
state <= FINISHED;
end
end
FINISHED: begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
//If a memory block is not active but there is data in a PPFIFO
//Then we need to flush it, this usually happens at the end of
//a write
o_write_finished <= 1; //Launch a signal to indicate that we
//consumed a block of memory
state <= GET_MEMORY_BLOCK;
end
endcase
end
//Reset the pointers
if (i_memory_0_ready || (i_memory_0_size == 0)) begin
r_mem_ptr[0] <= 0;
end
if (i_memory_1_ready || (i_memory_1_size == 0)) begin
r_mem_ptr[1] <= 0;
end
end
//Bank Select and Memory Ready
always @ (posedge clk) begin
if (rst) begin
r_active_bank <= 0;
r_memory_ready <= 0;
end
else begin
//Activate Memory Logic
if (!r_memory_ready) begin
//If there is any data at all in the memory blocks
if (r_mem_count[0] > 0) begin
r_memory_ready <= 1;
r_active_bank <= 0;
end
else if (r_mem_count[1] > 0) begin
r_memory_ready <= 1;
r_active_bank <= 1;
end
end
else begin
//If we're currently active and the active block is empty
//disable the block
if ((r_active_bank == 0) && (r_mem_count[0] == 0)) begin
r_memory_ready <= 0;
end
else if ((r_active_bank == 1) && (r_mem_count[1] == 0)) begin
r_memory_ready <= 0;
end
end
end
end
//Simulation information
always @ (posedge clk) begin
if (o_ppfifo_stb) begin
`ifdef VERBOSE: $display ("\twb_ppfifo_2_mem: Wrote: %h: Write Count: %h", i_ppfifo_data, r_ppfifo_count); `endif
end
end
endmodule
|
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter SRL_COUNT = 4;
parameter PRESCALER = 4;
// UART loopback
assign tx = rx;
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL32 testers
wire sim_error = sw[2];
wire [SRL_COUNT-1:0] srl_q31;
wire [SRL_COUNT-1:0] error;
genvar i;
generate for(i=0; i<SRL_COUNT; i=i+1) begin
wire srl_d;
wire srl_sh;
srl_shift_tester #
(
.FIXED_DELAY (32)
)
tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q31[i] ^ sim_error),
.srl_a (),
.error (error[i])
);
SRLC32E srl
(
.CLK (clk),
.CE (srl_sh),
.A (5'd0),
.D (srl_d),
.Q31 (srl_q31[i])
);
end endgenerate
// ============================================================================
// Error latch
reg [SRL_COUNT-1:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// Create a non-GND/VCC source for additional LED outputs.
// This is a side affect of the ROI disallowing GND/VCC connections to synth
// IO pads.
wire net_0;
LUT2 #(.INIT(4'hC)) lut_0 (.I0(|sw), .I1(&sw), .O(net_0));
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
if (j < SRL_COUNT) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q31[j];
end else begin
assign led[j ] = net_0;
assign led[j+8] = net_0;
end
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500009; const int mod = 1000000007; int n, m, x, y; vector<int> v[N]; vector<bool> vis; bool is; void pre() { vis.assign(N, 0); } void dfs(int ver, int par) { vis[ver] = 1; for (auto &it : v[ver]) { if (it == par) continue; if (vis[it] == 1) { is = 1; continue; } dfs(it, ver); } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin.exceptions(cin.failbit); ; pre(); cin >> n >> m; for (int i = 0; i < m; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } int ans = 0; for (int i = 1; i <= n; i++) { if (vis[i]) continue; is = 0; dfs(i, -1); ans++; if (is) ans--; } cout << ans << n ; return 0; }
|
// Test bench for our 6 bit shift register.
module main;
reg clk, rst_n;
reg [(32*5-1):0] values;
wire [31:0] rows;
wire [4:0] n;
shader sc (clk, rst_n, values, rows);
always #10 clk = ~clk;
task assert(input condition);
if(!condition)
$finish(2);
endtask // assert
integer i;
initial begin
clk = 0;
rst_n = 0;
values = 0;
`define set(i) values[4+(5*i):5*i] = i
`set(0);
`set(1);
`set(2);
`set(3);
`set(4);
`set(5);
`set(6);
`set(7);
`set(8);
`set(9);
`set(10);
`set(11);
`set(12);
`set(13);
`set(14);
`set(15);
`set(16);
`set(17);
`set(18);
`set(19);
`set(20);
`set(21);
`set(22);
`set(23);
`set(24);
`set(25);
`set(26);
`set(27);
`set(28);
`set(29);
`set(30);
`set(31);
#20 rst_n = 1;
for(i=0;i<31;i=i+1)
begin
$display("rows = %b, n = %d, expected = %b", rows, n, (-32'b1) << (i+1));
assert(rows == ((-32'b1) << (i+1)));
#20;
end
$finish;
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout << fixed; int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; int cost = 0; if (e > f) { int suits = min(a, d); cost += e * suits; a -= suits; d -= suits; if (d != 0) { suits = min({b, c, d}); cost += f * suits; } } else { int suits = min({b, c, d}); cost += f * suits; b -= suits; c -= suits; d -= suits; if (d != 0) { suits = min(a, d); cost += e * suits; } } cout << cost << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; int a[t + 10]; for (int i = 0; i < t; i++) { long int b, p, f, c, h, c1 = 0, c2 = 0; cin >> b >> p >> f; cin >> h >> c; b = b / 2; if (b == 0) { cout << 0 << endl; continue; } if (h > c) { if (b >= p) { c1 += (p * h); b -= p; if (f >= b) { c1 += b * c; } else { c1 += f * c; } } else { c1 += b * h; } } else { if (b >= f) { b -= f; c1 += c * f; if (b > p) { c1 += p * h; } else { c1 += b * h; } } else { c1 += b * c; } } cout << c1 << endl; c1 = 0; } }
|
#include <bits/stdc++.h> using namespace std; pair<long long int, long long int> p[300002]; int see(long long int a, long long int b, long long int c) { for (long long int i = 0; i < c; i++) { if (p[i].first == a || p[i].first == b || p[i].second == a || p[i].second == b) continue; if (b == -1) return see(a, p[i].first, c) || see(a, p[i].second, c); else return 0; } return 1; } int main() { long long int n, m, i; cin >> n >> m; for (i = 0; i < m; i++) cin >> p[i].first >> p[i].second; if (see(p[0].first, -1, m) || see(p[0].second, -1, m)) cout << YES << endl; else cout << NO << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 12:45:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_xlconstant_0_3 -prefix
// system_xlconstant_0_3_ system_xlconstant_0_3_stub.v
// Design : system_xlconstant_0_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_3(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[9:0]" */;
output [9:0]dout;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_adapter_64_8;
// parameters
localparam INPUT_DATA_WIDTH = 64;
localparam INPUT_KEEP_WIDTH = (INPUT_DATA_WIDTH/8);
localparam OUTPUT_DATA_WIDTH = 8;
localparam OUTPUT_KEEP_WIDTH = (OUTPUT_DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [INPUT_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [INPUT_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [OUTPUT_DATA_WIDTH-1:0] output_axis_tdata;
wire [OUTPUT_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_adapter_64_8.lxt");
$dumpvars(0, test_axis_adapter_64_8);
end
axis_adapter #(
.INPUT_DATA_WIDTH(INPUT_DATA_WIDTH),
.INPUT_KEEP_WIDTH(INPUT_KEEP_WIDTH),
.OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH),
.OUTPUT_KEEP_WIDTH(OUTPUT_KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[52][52], d[52], dd[52], c[52], b[52][52]; bool check(int pos) { int t[n + 2]; for (int i = 1; i <= n; i++) t[i] = d[i]; for (int i = 1; i <= n; i++) if (t[i] == n && i != pos) t[i] = n - 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { if (i == j) b[i][j] = 0; else { b[i][j] = min(t[i], t[j]); } } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (a[i][j] != b[i][j]) return 0; return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> a[i][j]; for (int i = 1; i <= n; i++) { for (int j = 0; j < n + 1; j++) dd[j] = 0; for (int j = 1; j <= n; j++) dd[a[i][j]] = 1; if (dd[n - 1] == 1) { c[n] = 1; d[i] = n; } if (d[i]) continue; for (int j = 0; j < n + 1; j++) { if (dd[j] == 0 && c[j - 1] == 0) { c[j - 1] = 1; d[i] = j - 1; break; } } } int pos = -1; for (int i = 1; i <= n; i++) { if (d[i] == n) { if (check(i)) { pos = i; break; } } } for (int i = 1; i <= n; i++) if (d[i] == n && i != pos) d[i] = n - 1; for (int i = 1; i <= n; i++) cout << d[i] << ; }
|
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