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#include <bits/stdc++.h> using namespace std; int main() { int n, i; cin >> n; string s; map<char, int> m; for (i = 0; i < n; i++) { cin >> s; m[s[0]]++; } int ans = 0, f1, f2; for (auto it = m.begin(); it != m.end(); it++) { f1 = it->second / 2; f2 = it->second - f1; ans += f1 * (f1 - 1) / 2 + f2 * (f2 - 1) / 2; } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:19:07 04/23/2015
// Design Name: modBigNumbers
// Module Name: U:/public/Final Project Elec 245/PrimeFactorization/test_mod_big_numbers.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: modBigNumbers
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_mod_big_numbers;
// Inputs
reg [63:0] exponent;
reg [63:0] number;
reg [7:0] logNum;
reg clk, reset;
reg start;
// Outputs
wire [63:0] result;
wire isDone;
// Instantiate the Unit Under Test (UUT)
modBigNumbers uut (
.reset(reset),
.start(start),
.clk(clk),
.exponent(exponent),
.number(number),
.logNum(logNum),
.result(result),
.isDone(isDone)
);
always #5 clk = ~clk;
initial begin
// Initialize Inputs
start = 0;
reset = 0;
clk = 0;
exponent = 0;
number = 0;
logNum = 0;
// Wait 100 ns for global reset to finish
#100;
start = 1;
reset = 1;
exponent = 64'd96;
number = 485;
logNum = 9;
#15;
reset = 0;
#10000000;
reset = 1;
exponent = 12;
number = 87;
logNum = 6;
#15;
reset = 0;
#600;
reset = 1;
exponent = 13;
number = 311;
logNum = 8;
#15;
reset = 0;
# 100;
// Add stimulus here
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Double-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common double-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// double-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// ////
//// To Do: ////
//// - add additional RAMs ////
//// - xilinx rams need external tri-state logic ////
//// ////
//// Author(s): ////
//// - Nir Mor, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2005 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dpram_256x32(
// Generic synchronous double-port RAM interface
clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
clk_b, rst_b, ce_b, we_b, addr_b, di_b
);
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 32;
//
// Generic synchronous double-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(16'h0000),
.ENA(ce_a),
.WEA(1'b0),
.DOA(do_a[15:0]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB()
);
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(16'h0000),
.ENA(ce_a),
.WEA(1'b0),
.DOA(do_a[31:16]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB()
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36_S36 ramb16_s36_s36(
.CLKA(clk_a),
.SSRA(rst_a),
.ADDRA({1'b0, addr_a}),
.DIA(32'h00000000),
.DIPA(4'h0),
.ENA(ce_a),
.WEA(1'b0),
.DOA(do_a),
.DOPA(),
.CLKB(clk_b),
.SSRB(rst_b),
.ADDRB({1'b0, addr_b}),
.DIB(di_b),
.DIPB(4'h0),
.ENB(ce_b),
.WEB(we_b),
.DOB(),
.DOPB()
);
`else
//
// Generic double-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_a_reg; // RAM address registered
//
// Data output drivers
//
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
//
// RAM read
//
always @(posedge clk_a or posedge rst_a)
if (rst_a)
addr_a_reg <= #1 {aw{1'b0}};
else if (ce_a)
addr_a_reg <= #1 addr_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b && we_b)
mem[addr_b] <= #1 di_b;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always begin : id block_defines some_statements ; end
module main ;
reg [3:0] value1,value2,value3;
always begin : block_id
reg [3:0] value4 ;
value4 = 1;
#5 ;
value1 = value4;
end
initial
begin
value1 = 0;
value2 = 0;
if(value1 != 0)
begin
$display("FAILED - 3.1.11B always begin : id defines statement end");
value2 = 1;
end
#6;
if(value1 != 1)
begin
$display("FAILED - 3.1.11B always begin : id defines statement end");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
$finish ;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: dma_engine_alignment.v
// Project: CPCI (PCI Control FPGA)
// Description: Re-alignment module to handle unaligned transfers
//
// Note: read and write are from the perspective of the driver.
// Read means retrieve a packet from the CNET and place in memory.
// Write means send a packet from memory to CNET.
//
// Change history: 12/08/07 - Split the alignment block from the main
// processing block to aid in readability
// and maintainability
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module dma_engine_alignment (
// PCI Signals
input [`PCI_DATA_WIDTH-1:0] pci_data, // Data being read from host
input dma_data_vld, // Indicates data should be captured
// from pci_data during a read or
// that a data transaction has
// occured during a write.
// CPCI register interface signals
input host_is_le, // The host is little endian
// CNET DMA interface signals
input [31:0] dma_data_frm_cnet, // DMA data to be transfered
output dma_rd_en, // Read a word from the buffer
input dma_empty, // Is the buffer empty?
// DMA engine signals
output [`PCI_DATA_WIDTH - 1 : 0] wr_buf_data, // Output of the write buffer
output [`PCI_DATA_WIDTH - 1 : 0] rd_buf_data, // Output of the read buffer
input xfer_is_rd, // Transfer direction
input last_word_pci, // Transfering last word on the PCI bus
input first_word_pci,// Transfering first word on the PCI bus
input last_word_from_cnet, // Transferring last word from CNET
input rd_full, // The read FIFO is full
input discard, // Discard a word from the read fifo
// (ignore it in processint
output reg wr_data_rdy, // Write data is being output in this cycle
output rd_data_rdy, // Read data is being output in this cycle
input [1:0] non_aligned_bytes, // Number of non-aligned bytes
output read_from_cnet,// Indicates read of word from CNET
input ld_xfer_cnt,
input [8:0] xfer_cnt_start, // Number of words to transfer
input [8:0] to_cnet_cnt_start, // Number of words to transfer
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Is there currently data being OP on dma_data_frm_cnet?
reg data_frm_cnet_ready;
// Byte swaped version of data from PCI bus
wire [`PCI_DATA_WIDTH-1:0] pci_data_swapped;
// Byte swapped version of data from cnet
wire [31:0] dma_data_frm_cnet_swapped;
// Instruct the read buffer to write a word
wire rdb_wr_en;
// Deal with non-aligned DMA transfers
reg [55:0] wr_realign_buf, rd_realign_buf;
reg wr_pci_done;
reg wr_dma_done;
reg rd_cnet_done;
reg rd_fifo_done;
// Input to the read and write FIFOs
reg [`PCI_DATA_WIDTH - 1 : 0] wr_buf_data_swapped;
reg [`PCI_DATA_WIDTH - 1 : 0] rd_buf_data_swapped;
// Word available in write/read buffers
reg rdb_data_avail;
// Transfer counters
reg [8:0] to_wr_fifo_cnt;
reg [8:0] to_rd_fifo_cnt;
// Last word being written into write or read FIFO
wire last_word_to_wr_fifo;
wire last_word_to_rd_fifo;
// ==================================================================
// Sample the write data for non-aligned transfers
// ==================================================================
assign pci_data_swapped = host_is_le ?
{pci_data[7:0], pci_data[15:8], pci_data[23:16], pci_data[31:24]} :
pci_data;
always @(posedge clk)
begin
if (reset || cnet_reprog)
begin
wr_data_rdy <= 1'b0;
wr_pci_done <= 1'b0;
wr_dma_done <= 1'b0;
end
else
begin
// Shift data in the realignment buffer when either:
// - we're doing a write over the PCI bus
// - the PCI transaction has finished and we've still got data
// to transfer over the DMA bus
if ((dma_data_vld && !xfer_is_rd) ||
(wr_pci_done && !wr_dma_done ))
wr_realign_buf <= {wr_realign_buf[31:0], pci_data_swapped};
// Record that there's data ready to push out of the module when:
// - a PCI write has occurred and the transfer is aligned
// - a PCI write has occurred and there's already data in the buffer
// - PCI transaction is done, DMA transfer is not done and we're not
// currently writing
// - PCI transaction is done, DMA transfer is not done and we're
// transfering something other than the last word
if (dma_data_vld && !xfer_is_rd)
wr_data_rdy <= (non_aligned_bytes == 2'b00) || !first_word_pci;
else if (wr_data_rdy || wr_pci_done)
wr_data_rdy <= wr_pci_done && !wr_dma_done &&
(!wr_data_rdy || !last_word_to_wr_fifo);
// Record when we've transferred the last word over the PCI and DMA
// buses
if (dma_data_vld && !xfer_is_rd)
wr_pci_done <= last_word_pci;
if (dma_data_vld && !xfer_is_rd || wr_data_rdy)
wr_dma_done <= last_word_to_wr_fifo || (wr_dma_done && wr_data_rdy);
end
end
// ==================================================================
// Sample the read data for non-aligned transfers
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
begin
rdb_data_avail <= 1'b0;
rd_cnet_done <= 1'b0;
end
else
begin
// Shift data into the buffer when we've got a word from the CNET or
// when we need to do a shift of the last word to ensure we push all
// data to the host.
if (rdb_wr_en || rd_data_rdy)
case (non_aligned_bytes)
2'b01 : rd_realign_buf <= {rd_realign_buf[23:0], dma_data_frm_cnet_swapped};
2'b10 : rd_realign_buf <= {rd_realign_buf[23:8], dma_data_frm_cnet_swapped, 8'b0};
2'b11 : rd_realign_buf <= {rd_realign_buf[23:16], dma_data_frm_cnet_swapped, 16'b0};
default : rd_realign_buf <= {dma_data_frm_cnet_swapped, 24'b0};
endcase
// Record when there is data available
if (rdb_wr_en)
rdb_data_avail <= 1'b1;
else if (rd_data_rdy)
rdb_data_avail <= rd_cnet_done && !rd_fifo_done &&
(!rdb_data_avail || !last_word_to_rd_fifo);
// Record when we've transferred the last word from the CNET and to
// the read FIFO
if (rdb_wr_en)
rd_cnet_done <= last_word_from_cnet;
if (rdb_wr_en || rd_data_rdy)
rd_fifo_done <= last_word_to_rd_fifo || (rd_data_rdy && rd_fifo_done);
end
end
// ==================================================================
// Work out the data to input into the Write FIFO
// ==================================================================
always @*
begin
case (non_aligned_bytes)
2'b00 : wr_buf_data_swapped <= wr_realign_buf[31:0];
2'b01 : wr_buf_data_swapped <= wr_realign_buf[39:8];
2'b10 : wr_buf_data_swapped <= wr_realign_buf[47:16];
default : wr_buf_data_swapped <= wr_realign_buf[55:24];
endcase
end
assign wr_buf_data = {wr_buf_data_swapped[7:0],
wr_buf_data_swapped[15:8],
wr_buf_data_swapped[23:16],
wr_buf_data_swapped[31:24]};
// ==================================================================
// Work out the data to input into the Read FIFO
// ==================================================================
always @*
rd_buf_data_swapped <= rd_realign_buf[55:24];
assign rd_buf_data = host_is_le ?
{rd_buf_data_swapped[7:0],
rd_buf_data_swapped[15:8],
rd_buf_data_swapped[23:16],
rd_buf_data_swapped[31:24]} :
rd_buf_data_swapped;
assign dma_data_frm_cnet_swapped = {
dma_data_frm_cnet[7:0],
dma_data_frm_cnet[15:8],
dma_data_frm_cnet[23:16],
dma_data_frm_cnet[31:24]
};
// ==================================================================
// Rd/Wr FIFO transfer counters
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
to_wr_fifo_cnt <= 'h0;
else if (ld_xfer_cnt)
to_wr_fifo_cnt <= to_cnet_cnt_start;
else if (wr_data_rdy)
to_wr_fifo_cnt <= to_wr_fifo_cnt - 'h1;
end
always @(posedge clk)
begin
if (reset || cnet_reprog)
to_rd_fifo_cnt <= 'h0;
else if (ld_xfer_cnt)
to_rd_fifo_cnt <= xfer_cnt_start;
else if (rd_data_rdy)
to_rd_fifo_cnt <= to_rd_fifo_cnt - 'h1;
end
assign last_word_to_wr_fifo = to_wr_fifo_cnt == 'h1;
assign last_word_to_rd_fifo = to_rd_fifo_cnt == 'h1;
// ==================================================================
// Miscelaneous signal generation
// ==================================================================
// Record when there is data available from the CNET
always @(posedge clk)
begin
if (reset || cnet_reprog)
data_frm_cnet_ready <= 1'b0;
else if (dma_rd_en)
data_frm_cnet_ready <= 1'b1;
else if (rd_data_rdy || discard)
data_frm_cnet_ready <= 1'b0;
end
// Write a word into the read buffer if data is available and we're not
// discarding and the output fifo isn't backed up
assign rdb_wr_en = data_frm_cnet_ready && !discard && !rd_full;
assign read_from_cnet = rdb_wr_en;
// Generate the read ready signal
assign rd_data_rdy = rdb_data_avail && !rd_full;
// Pull the next word from the CNET if there's data available and either:
// - we don't currently have any data
// - we're discarding the current word
// - we're writing the current word into the realign buffer
assign dma_rd_en = !dma_empty &&
(!data_frm_cnet_ready || discard || rdb_wr_en);
endmodule // dma_engine_alignment
|
`timescale 1 ns / 1 ps
`include "axi_traffic_controller_v1_0_tb_include.vh"
module axi_traffic_controller_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M_AXI_INIT_AXI_TXN;
wire M_AXI_TXN_DONE;
wire M_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M_AXI_TXN_DONE(M_AXI_TXN_DONE),
.M_AXI_ERROR(M_AXI_ERROR),
.M_AXI_INIT_AXI_TXN(M_AXI_INIT_AXI_TXN));
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M_AXI_INIT_AXI_TXN = 1'b0;
#500 M_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M_AXI:");
wait( M_AXI_TXN_DONE == 1'b1);
$display("M_AXI: PTGEN_TEST_FINISHED!");
if ( M_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, st; int tmp, tmp2; vector<int> adj[200005]; int memo[200005][5]; bool vis[200005][5]; int stc, stn; pair<int, int> par[200005][5]; int dp(int node, int cur) { if (adj[node].size() == 0) { if (cur == 2) { stc = cur; stn = node; return 1; } if (cur == 1) { stc = cur; stn = node; } return cur; } if (memo[node][cur] != -1) return memo[node][cur]; int ret = 0; pair<int, int> cp; cp.first = node; cp.second = cur; for (int i = 0; i < adj[node].size(); i++) { if (cur == 2) { if (vis[adj[node][i]][cur]) { if (ret == 0) ret = 2; continue; } vis[adj[node][i]][cur] = 1; par[adj[node][i]][cur] = cp; int now = dp(adj[node][i], cur); if (now == 1) ret = 1; vis[adj[node][i]][cur] = 0; } else { if (vis[adj[node][i]][(cur + 1) % 2]) { if (ret == 0) ret = 2; continue; } vis[adj[node][i]][(cur + 1) % 2] = 1; par[adj[node][i]][(cur + 1) % 2] = cp; int now = dp(adj[node][i], (cur + 1) % 2); if (now == 1) ret = 1; else if (now == 2 && ret == 0) ret = 2; vis[adj[node][i]][(cur + 1) % 2] = 0; } } return memo[node][cur] = ret; } void dfs(int node, int cur) { if (node == st && cur == 0) { printf( %d , node); return; } dfs(par[node][cur].first, par[node][cur].second); printf( %d , node); return; } int main() { memset(memo, -1, sizeof(memo)); scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &tmp); for (int j = 1; j <= tmp; j++) { scanf( %d , &tmp2); adj[i].push_back(tmp2); } } scanf( %d , &st); int ans = dp(st, 0); if (ans == 0) { printf( Lose n ); } else if (ans == 2) { printf( Draw n ); } else { printf( Win n ); dfs(stn, stc); } return 0; }
|
/*
* This file was generated by the scsynth tool, and is availablefor use under
* the MIT license. More information can be found at
* https://github.com/arminalaghi/scsynth/
*/
module ReSC_wrapper_varied_bin_lengths_test( //handles stochastic/binary conversion for ReSC
input [5:0] x_bin, //binary value of input
input start, //signal to start counting
output reg done, //signal that a number has been computed
output reg [9:0] z_bin, //binary value of output
input clk,
input reset
);
wire [9:0] x_bin_shifted;
assign x_bin_shifted = x_bin << 4;
//the weights of the Bernstein polynomial
reg [9:0] w0_bin = 10'd104;
reg [9:0] w1_bin = 10'd204;
reg [9:0] w2_bin = 10'd308;
reg [9:0] w3_bin = 10'd408;
reg [9:0] w4_bin = 10'd716;
reg [9:0] w5_bin = 10'd820;
wire [4:0] x_stoch;
wire [5:0] w_stoch;
wire z_stoch;
wire init;
wire running;
//RNGs for binary->stochastic conversion
wire [9:0] randx0;
LFSR_10_bit_added_zero_varied_bin_lengths_test rand_gen_x_0 (
.seed (10'd0),
.data (randx0),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_stoch[0] = randx0 < x_bin_shifted;
wire [9:0] randx1;
LFSR_10_bit_added_zero_varied_bin_lengths_test rand_gen_x_1 (
.seed (10'd93),
.data (randx1),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_stoch[1] = randx1 < x_bin_shifted;
wire [9:0] randx2;
LFSR_10_bit_added_zero_varied_bin_lengths_test rand_gen_x_2 (
.seed (10'd186),
.data (randx2),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_stoch[2] = randx2 < x_bin_shifted;
wire [9:0] randx3;
LFSR_10_bit_added_zero_varied_bin_lengths_test rand_gen_x_3 (
.seed (10'd279),
.data (randx3),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_stoch[3] = randx3 < x_bin_shifted;
wire [9:0] randx4;
LFSR_10_bit_added_zero_varied_bin_lengths_test rand_gen_x_4 (
.seed (10'd372),
.data (randx4),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_stoch[4] = randx4 < x_bin_shifted;
wire [9:0] randw;
LFSR_10_bit_added_zero_varied_bin_lengths_test rand_gen_w (
.seed (10'd683),
.data (randw),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign w_stoch[0] = randw < w0_bin;
assign w_stoch[1] = randw < w1_bin;
assign w_stoch[2] = randw < w2_bin;
assign w_stoch[3] = randw < w3_bin;
assign w_stoch[4] = randw < w4_bin;
assign w_stoch[5] = randw < w5_bin;
ReSC_varied_bin_lengths_test ReSC (
.x (x_stoch),
.w (w_stoch),
.z (z_stoch)
);
reg [9:0] count; //count clock cycles
wire [9:0] neg_one;
assign neg_one = -1;
//Finite state machine. States:
//0: finished, in need of resetting
//1: initialized, start counting when start signal falls
//2: running
reg [1:0] cs; //current FSM state
reg [1:0] ns; //next FSM state
assign init = cs == 1;
assign running = cs == 2;
always @(posedge clk or posedge reset) begin
if (reset) cs <= 0;
else begin
cs <= ns;
if (running) begin
if (count == neg_one) done <= 1;
count <= count + 1;
z_bin <= z_bin + z_stoch;
end
end
end
always @(*) begin
case (cs)
0: if (start) ns = 1; else ns = 0;
1: if (start) ns = 1; else ns = 2;
2: if (done) ns = 0; else ns = 2;
default ns = 0;
endcase
end
always @(posedge init) begin
count <= 0;
z_bin <= 0;
done <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long const N = 2e5 + 70; long long n, k, a[N], cnt[N], ans, fi = -1, la = -1; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; for (long long i = 0; i <= n; i++) { cin >> a[i]; cnt[i] = a[i]; } for (long long i = 0; i < n + 50; i++) { if (cnt[i] < 0) { cnt[i + 1] += cnt[i]; cnt[i] = -cnt[i]; } cnt[i + 1] += cnt[i] / 2; cnt[i] &= 1; if (cnt[i]) { if (fi == -1) fi = i; la = i; } } if (cnt[n + 50]) { fi = la = -1; memset(cnt, 0, sizeof cnt); for (long long i = 0; i <= n; i++) a[i] = -a[i], cnt[i] = a[i]; for (long long i = 0; i < n + 50; i++) { if (cnt[i] < 0) { cnt[i + 1] += cnt[i]; cnt[i] = -cnt[i]; } cnt[i + 1] += cnt[i] / 2; cnt[i] &= 1; if (cnt[i]) { if (fi == -1) fi = i; la = i; } } } if (la - fi >= 35) return cout << 0 n , 0; long long res = 0; for (long long i = fi; i <= la; i++) res += (1 << (i - fi)) * cnt[i]; long long cur = res; for (long long i = fi; i >= 0 && cur <= 2e9; i--) { if (i <= n && a[i] - cur >= -k && (i != n || a[i] - cur != 0)) ans++; cur *= 2; } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; long long int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p = 0, q = 0, r, s, t, u, v, w, x, y, z, temp = 0, ans = 0, t1, t2, sum = 0; vector<long long int> v1, v2, v3, v4, v5, v6; vector<string> vs1, vs2, vs3, vs4; double f1, f2 = 0, f3, f4; vector<double> v10; vector<pair<long long int, long long int>> v11, v12, v13, v14; string s1, s2, s3, s4, s5, s6; long long int a10[100][3]; long long int a1[1000000], a2[1000000]; char c1, c2, c3; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (i = 0; i < n; i++) { p = 0; cin >> g >> h; while (g != 0) { if (g % h == 0) { g = g / h; p++; } else { p = p + g % h; g = g - g % h; } } cout << p << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_BLACKBOX_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
// Allows simultaneous ENQ and DEQ (at the expense of potentially
// causing combinational loops).
module FIFOL1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg empty_reg ;
reg [width - 1 : 0] D_OUT;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ;
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg || DEQ;
assign EMPTY_N = empty_reg ;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && ! DEQ)
begin
enqerror = 1 ;
$display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ;
end
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long int, long long int> > v1, v2; int main() { long long int p, q, l, r, w, x, y, z, i, j, flag, tot = 0, k; scanf( %lld , &p); scanf( %lld , &q); scanf( %lld , &l); scanf( %lld , &r); for (i = 0; i < p; i++) { scanf( %lld , &x); scanf( %lld , &y); v1.push_back(make_pair(x, y)); } for (i = 0; i < q; i++) { scanf( %lld , &x); scanf( %lld , &y); v2.push_back(make_pair(x, y)); } for (i = l; i <= r; i++) { flag = 0; for (j = 0; j < v1.size(); j++) { for (k = 0; k < v2.size(); k++) { if (v1[j].second < v2[k].first + i || v1[j].first > v2[k].second + i) ; else flag = 1; } } if (flag == 1) tot++; } cout << tot << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int p[100001], w[100001]; bool combine(int x, int y) { while (p[x] != x) x = p[x] = p[p[x]]; while (p[y] != y) y = p[y] = p[p[y]]; if (x == y) return false; if (w[x] < w[y]) w[p[x] = y] += w[x]; else w[p[y] = x] += w[y]; return true; } int main() { int n, m, x, y, ans = 1; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) w[p[i] = i] = 1; while (m--) { scanf( %d%d , &x, &y); if (!combine(x, y)) ans = ans * 2 % 1000000009; printf( %d n , (ans + 1000000008) % 1000000009); } }
|
#include <bits/stdc++.h> const int N = 2001, INF = 1e9 + 7; long long g[N][N], f[N][N]; int main() { int n, k; std::cin >> n >> k; std::string s; std::cin >> s; f[0][0] = g[0][0] = 1; for (int i = 1; i <= n; ++i) for (int j = 0; j <= k; ++j) { g[i][j] = f[i - 1][j] * (s[n - i] - a ) + g[i - 1][j]; f[i][j] = g[i][j]; for (int p = 1; p <= i + 1 - p && p * (i + 1 - p) <= j; ++p) { f[i][j] += f[i - p][j - p * (i + 1 - p)] * ( z - s[n - i + p - 1]); if (p < i + 1 - p) f[i][j] += f[p - 1][j - p * (i + 1 - p)] * ( z - s[n - p]); } g[i][j] %= INF; f[i][j] %= INF; } std::cout << f[n][k]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_8_V
`define SKY130_FD_SC_HDLL__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__bufbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_8_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module proj2_testbench_2;
reg clk;
wire [15:0] sum1, sum2;
reg [15:0] A, B;
wire cout1;
wire cout2;
wire P, G;
add16_LA A1(A, B, 1'b0, sum1, cout1, P, G);
ripple_adder DUT1(A[7:0],B[7:0], 1'b0, sum2[7:0], add1_to_add2);
ripple_adder DUT2(A[15:8],B[15:8], add1_to_add2, sum2[15:8], cout2);
always
#10 clk =~clk;
initial begin
clk = 1'b0;
A = 16'h1;
B = 16'h1;
end
always @(posedge clk)
A=A+1;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module decodes a NTSC video stream. *
* *
******************************************************************************/
module altera_up_video_itu_656_decoder (
// Inputs
clk,
reset,
TD_DATA,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] TD_DATA;
input ready;
// Bidirectional
// Outputs
output [15: 0] data;
output startofpacket;
output endofpacket;
output valid;
//output reg [15: 0] data;
//output reg startofpacket;
//output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire timing_reference; // 4-Bytes: FF 00 00 XY
wire start_of_an_even_line;
wire start_of_an_odd_line;
wire [ 7: 0] last_data;
// Internal Registers
reg [ 7: 0] io_register;
reg [ 7: 0] video_shift_reg [ 5: 1];
reg possible_timing_reference;
reg [ 6: 1] active_video;
reg last_line;
reg [15: 0] internal_data;
reg internal_startofpacket;
reg internal_valid;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
io_register <= TD_DATA;
// Output Registers
/*
always @ (posedge clk)
data <= {video_shift_reg[5], video_shift_reg[4]};
always @ (posedge clk)
begin
if (~last_line & start_of_an_odd_line)
startofpacket <= 1'b1;
else if (last_line & start_of_an_even_line)
startofpacket <= 1'b1;
else if (valid)
startofpacket <= 1'b0;
end
always @(posedge clk)
begin
if (active_video[5])
valid <= valid ^ 1'b1;
else
valid <= 1'b0;
end
*/
// Internal Registers
always @ (posedge clk)
begin
for (i = 5; i > 1; i = i - 1)
video_shift_reg[i] <= video_shift_reg[(i - 1)];
video_shift_reg[1] <= io_register;
end
always @(posedge clk)
begin
if ((video_shift_reg[3] == 8'hFF) &&
(video_shift_reg[2] == 8'h00) &&
(video_shift_reg[1] == 8'h00))
possible_timing_reference <= 1'b1;
else
possible_timing_reference <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
active_video <= 6'h00;
else if (start_of_an_even_line | start_of_an_odd_line)
active_video <= {active_video[5:1], 1'b1};
else if (timing_reference == 1'b1)
active_video <= 6'h00;
else
active_video[6:2] <= active_video[5:1];
end
always @ (posedge clk)
begin
if (reset)
last_line <= 1'b0;
else if (start_of_an_odd_line)
last_line <= 1'b1;
else if (start_of_an_even_line)
last_line <= 1'b0;
end
always @ (posedge clk)
internal_data <= {video_shift_reg[5], video_shift_reg[4]};
always @ (posedge clk)
begin
if (~last_line & start_of_an_odd_line)
internal_startofpacket <= 1'b1;
else if (last_line & start_of_an_even_line)
internal_startofpacket <= 1'b1;
else if (valid)
internal_startofpacket <= 1'b0;
end
always @(posedge clk)
begin
if (active_video[5])
internal_valid <= internal_valid ^ 1'b1;
else
internal_valid <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign last_data = video_shift_reg[1];
assign timing_reference =
( possible_timing_reference &
( (last_data[5] ^ last_data[4]) == last_data[3]) &
( (last_data[6] ^ last_data[4]) == last_data[2]) &
( (last_data[6] ^ last_data[5]) == last_data[1]) &
( (last_data[6] ^ last_data[5] ^ last_data[4]) == last_data[0])
);
assign start_of_an_even_line = timing_reference &
last_data[6] & ~last_data[5] & ~last_data[4];
assign start_of_an_odd_line = timing_reference &
~last_data[6] & ~last_data[5] & ~last_data[4];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_decoder_add_endofpacket Add_EndofPacket (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (1'b0),
.stream_in_valid (internal_valid),
.stream_out_ready (ready),
// Bidirectional
// Outputs
.stream_in_ready (),
.stream_out_data (data),
.stream_out_startofpacket (startofpacket),
.stream_out_endofpacket (endofpacket),
.stream_out_valid (valid)
);
defparam
Add_EndofPacket.DW = 15;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MXN = 3e5 + 5; const int MOD = 998244353; const int LOG = 19; int add(int x, int y) { return (x += y) < MOD ? x : x - MOD; } int sub(int x, int y) { return (x -= y) >= 00 ? x : x + MOD; } int mul(int x, int y) { return (ll)x * y % MOD; } int pwr(int x, int p) { if (p == 0) return 1; if (p % 2) return mul(x, pwr(x, p - 1)); return pwr(mul(x, x), p / 2); } int inv(int x) { return pwr(x, MOD - 2); } int sol = 1; int ok[MXN]; int val[MXN]; int dep[MXN]; int lca[MXN]; int nxt[MXN]; int dp[MXN][2]; int anc[MXN][LOG]; vector<int> adj[MXN]; int getlca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); int diff = dep[x] - dep[y]; for (int i = 0; i < LOG; ++i) { if (diff >> i & 1) x = anc[x][i]; } if (x == y) return x; for (int i = LOG - 1; i >= 0; --i) { if (anc[x][i] != anc[y][i]) { x = anc[x][i]; y = anc[y][i]; } } return anc[x][0]; } void dfs1(int x, int p) { if (val[x]) { if (lca[val[x]]) { lca[val[x]] = getlca(lca[val[x]], x); } else { lca[val[x]] = x; } } for (int y : adj[x]) { if (y == p) continue; anc[y][0] = x; dep[y] = dep[x] + 1; for (int i = 0; i < LOG - 1; ++i) { anc[y][i + 1] = anc[anc[y][i]][i]; } dfs1(y, x); } } void dfs2(int x, int p) { vector<int> vec; for (int y : adj[x]) { if (y == p) continue; dfs2(y, x); if (ok[y]) { ok[x] = 1; vec.push_back(y); } if (val[y] && y != lca[val[y]]) { if (val[x] && val[x] != val[y]) { cout << 0 n ; exit(0); } val[x] = val[y]; } } if (val[x]) { dp[x][0] = ok[x] = 1; for (int y : vec) { sol = mul(sol, add(mul(dp[y][0], nxt[y] + 1), dp[y][1])); } } else if (vec.size() > 1) { dp[x][1] = 1; for (int y : vec) { int tmp = add(dp[y][1], mul(dp[y][0], nxt[y] + 1)); dp[x][1] = mul(dp[x][1], tmp); } for (int y : vec) { int tmp = add(dp[y][1], mul(dp[y][0], nxt[y] + 1)); dp[x][0] = add(dp[x][0], mul(mul(dp[x][1], inv(tmp)), dp[y][0])); } } else if (vec.size() == 1) { dp[x][0] = dp[vec[0]][0]; dp[x][1] = dp[vec[0]][1]; nxt[x] = nxt[vec[0]] + 1; } } int main() { ios::sync_with_stdio(0), cin.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= n; ++i) { cin >> val[i]; } for (int i = 2; i <= n; ++i) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } dfs1(1, 0); dfs2(1, 0); if (dp[1][0]) sol = mul(sol, dp[1][0]); cout << sol << n ; }
|
#include <bits/stdc++.h> using namespace std; long long solve() { long long n; cin >> n; string str1, str2; cin >> str1 >> str2; long long freq1[26] = {0}; long long freq2[26] = {0}; for (long long i = 0; i < n; i++) { freq1[str1[i] - a ]++; freq2[str2[i] - a ]++; } for (long long i = 0; i < 26; i++) { if (freq1[i] != freq2[i]) { cout << NO n ; return 0; } } for (long long i = 0; i < 26; i++) { if (freq1[i] >= 2) { cout << YES n ; return 0; } } for (long long i = 0; i < n - 2; i++) { long long pos = -1; for (long long j = i; j < n; j++) { if (str1[i] == str2[j]) { pos = j; break; } } long long cnt = 0; while (pos > i) { swap(str2[pos], str2[pos - 1]); cnt++; pos--; } cnt = cnt % 2; if (cnt == 0) continue; else swap(str2[n - 1], str2[n - 2]); } for (long long i = 0; i < n; i++) { if (str1[i] != str2[i]) { cout << NO n ; return 0; } } cout << YES n ; return 0; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; long long t = 1; cin >> t; while (t-- != 0) { long long stat = solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100001; int main() { char c[3][3], cc[3][3]; char s[3][3]; int ind1, ind2; int ii = 0; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { cin >> c[i][j]; cc[i][j] = c[i][j]; } for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { cin >> s[i][j]; } for (ii = 0; ii < 60; ii++) { int t = 0; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { if (c[i][j] == X ) { ind1 = i; ind2 = j; } } } if (ind1 == 0 && ind2 == 0) swap(c[0][0], c[1][0]); if (ind1 == 0 && ind2 == 1) swap(c[0][1], c[0][0]); if (ind1 == 1 && ind2 == 0) swap(c[1][0], c[1][1]); if (ind1 == 1 && ind2 == 1) swap(c[1][1], c[0][1]); for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { if (s[i][j] != c[i][j]) { t = 1; break; } } if (t == 0) { cout << YES << endl; return 0; } } for (ii = 0; ii < 60; ii++) { int t = 0; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { if (cc[i][j] == X ) { ind1 = i; ind2 = j; } } } if (ind1 == 0 && ind2 == 0) swap(c[0][0], c[0][1]); if (ind1 == 0 && ind2 == 1) swap(c[0][1], c[1][1]); if (ind1 == 1 && ind2 == 0) swap(c[1][0], c[0][0]); if (ind1 == 1 && ind2 == 1) swap(c[1][1], c[1][0]); for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { if (s[i][j] != c[i][j]) { t = 1; break; } } if (t == 0) { cout << YES << endl; return 0; } } cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { char a[200]; char c; int i = 0; while ((c = getchar()) != n ) { a[i] = c; i++; } for (int k = 0; k < i - 2; k++) { if (a[k] == W && a[k + 1] == U && a[k + 2] == B ) { a[k] = ; a[k + 1] = ; a[k + 2] = ; } } int s; for (s = 0; s < i; s++) { if (a[s] != ) { cout << a[s]; break; } } for (int j = s + 1; j < i; j++) { if (a[j] != && a[j - 1] != ) cout << a[j]; if (a[j] != && a[j - 1] == ) cout << << a[j]; } }
|
#include <bits/stdc++.h> int n, m, x, i, ans; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &x); if (x == 2) ++m; } if (n == 1) ans = 1; if (n == 2 && m == 0) ans = 2; if (n == 2 && m == 1) ans = 2; if (n == 2 && m == 2) ans = 2; if (n == 3 && m == 0) ans = 4; if (n == 3 && m == 1) ans = 6; if (n == 3 && m == 2) ans = 6; if (n == 3 && m == 3) ans = 6; if (n == 4 && m == 0) ans = 10; if (n == 4 && m == 1) ans = 16; if (n == 4 && m == 2) ans = 24; if (n == 4 && m == 3) ans = 24; if (n == 4 && m == 4) ans = 24; if (n == 5 && m == 0) ans = 26; if (n == 5 && m == 1) ans = 50; if (n == 5 && m == 2) ans = 80; if (n == 5 && m == 3) ans = 120; if (n == 5 && m == 4) ans = 120; if (n == 5 && m == 5) ans = 120; if (n == 6 && m == 0) ans = 76; if (n == 6 && m == 1) ans = 156; if (n == 6 && m == 2) ans = 300; if (n == 6 && m == 3) ans = 480; if (n == 6 && m == 4) ans = 720; if (n == 6 && m == 5) ans = 720; if (n == 6 && m == 6) ans = 720; if (n == 7 && m == 0) ans = 232; if (n == 7 && m == 1) ans = 532; if (n == 7 && m == 2) ans = 1092; if (n == 7 && m == 3) ans = 2100; if (n == 7 && m == 4) ans = 3360; if (n == 7 && m == 5) ans = 5040; if (n == 7 && m == 6) ans = 5040; if (n == 7 && m == 7) ans = 5040; if (n == 8 && m == 0) ans = 764; if (n == 8 && m == 1) ans = 1856; if (n == 8 && m == 2) ans = 4256; if (n == 8 && m == 3) ans = 8736; if (n == 8 && m == 4) ans = 16800; if (n == 8 && m == 5) ans = 26880; if (n == 8 && m == 6) ans = 40320; if (n == 8 && m == 7) ans = 40320; if (n == 8 && m == 8) ans = 40320; if (n == 9 && m == 0) ans = 2620; if (n == 9 && m == 1) ans = 6876; if (n == 9 && m == 2) ans = 16704; if (n == 9 && m == 3) ans = 38304; if (n == 9 && m == 4) ans = 78624; if (n == 9 && m == 5) ans = 151200; if (n == 9 && m == 6) ans = 241920; if (n == 9 && m == 7) ans = 362880; if (n == 9 && m >= 8) ans = 362880; if (n == 10 && m == 0) ans = 9496; if (n == 10 && m == 1) ans = 26200; if (n == 10 && m == 2) ans = 68760; if (n == 10 && m == 3) ans = 167040; if (n == 10 && m == 4) ans = 383040; if (n == 10 && m == 5) ans = 786240; if (n == 10 && m == 6) ans = 1512000; if (n == 10 && m == 7) ans = 2419200; if (n == 10 && m >= 8) ans = 3628800; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; struct substring { int f, b; bool operator>(const substring &o) const { int cmp = s.compare(f, b - f + 1, s, o.f, o.b - o.f + 1); return cmp != 0 ? cmp > 0 : f > o.f; } }; string kthSubstring(int k) { priority_queue<substring, vector<substring>, greater<substring>> pq; int len = s.length(); for (int i = 0; i < len; i++) { pq.push({i, i}); } while (!pq.empty()) { int f = pq.top().f, b = pq.top().b; pq.pop(); if (--k == 0) return s.substr(f, b - f + 1); if (++b < len) { pq.push({f, b}); } } return ; } int main() { int k; cin >> s >> k; int len = s.length(); long long possible = ((long long)len * (len + 1)) / 2; if (k > possible) cout << No such line. << n ; else cout << kthSubstring(k) << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__OR3B_FUNCTIONAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_FUNCTIONAL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A D/Q flip flop.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ff
(
input CLK,
input D,
output reg Q
);
always @ (posedge CLK) begin
Q <= #1 D;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:02:55 03/24/2015
// Design Name:
// Module Name: arithm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module arithm(
input clk,
input ce,
input [13:0] A,
input [13:0] B,
input [13:0] C,
output [28:0] O
);
wire signed [14:0] a_plus_b;
wire signed [13:0] opoz_c;
wire signed [28:0] wynik;
//latency = 2
add dodawanie (
.a(A), // input [13 : 0] a
.b(B), // input [13 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(a_plus_b) // output [14 : 0] s
);
delay # (
.DELAY(2),
.N(14))
opoznienie
(
.d(C),
.ce(ce),
.clk(clk),
.q(opoz_c)
);
//latency = 3
mul mnozenie (
.clk(clk), // input clk
.a(a_plus_b), // input [13 : 0] a
.b(opoz_c), // input [13 : 0] b
.p(wynik) // output [28 : 0] p
);
assign O = wynik;//powinno byc 11111101111001101101011110000
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const int maxn = 3000 + 10; int n, m, A[maxn], B[maxn]; long long f[maxn][maxn]; void init() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &A[i]); A[i] -= i; B[i] = A[i]; } } void solve() { sort(B + 1, B + n + 1); m = 1; for (int i = 2; i <= n; ++i) if (B[m] != B[i]) B[++m] = B[i]; for (int i = 1; i <= n; ++i) for (int j = 0; j <= m; ++j) f[i][j] = inf; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) f[i][j] = min(f[i][j - 1], f[i - 1][j] + abs(A[i] - B[j])); long long ans = inf; for (int i = 1; i <= m; ++i) ans = min(ans, f[n][i]); printf( %I64d n , ans); } int main() { init(); solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__TAP_FUNCTIONAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long n, m; char c; long hi[600000][3], hj[600000][3], ans; long temp; long l, u; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> c; if (c == . ) continue; temp = c - 48; if (temp < 3) l = 1; else l = 0; if (l % 2 == j % 2) hi[i][1] = 1; else hi[i][0] = 1; if (temp == 1 || temp == 4) u = 1; else u = 0; if (u % 2 == i % 2) hj[j][1] = 1; else hj[j][0] = 1; } ans = 1; for (int i = 1; i <= n; i++) { temp = 2; temp -= hi[i][0] + hi[i][1]; ans = ans * temp % 1000003; } for (int i = 1; i <= m; i++) { temp = 2; temp -= hj[i][0] + hj[i][1]; ans = ans * temp % 1000003; } cout << ans << endl; cin.get(); cin.get(); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
sub a (.inst(1));
sub b (.inst(2));
initial begin
a.test1;
b.test1;
a.test2;
b.test2;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input integer inst);
import "DPI-C" context function int dpic_line();
import "DPI-C" context function int dpic_save(int value);
import "DPI-C" context function int dpic_restore();
import "DPI-C" context function int unsigned dpic_getcontext();
int result;
task test1;
// Check line numbering
`ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test
result = dpic_line(); if (!result) $stop;
`else
result = dpic_line(); if (result !== `__LINE__) $stop;
//
result = dpic_line(); if (result !== `__LINE__) $stop;
`endif
// Check save-restore
result = dpic_save(23+inst);
if (result==0) $stop;
endtask
task test2;
if (dpic_restore() != 23+inst) $stop;
endtask
int unsigned cntxt1;
int unsigned cntxt2;
initial begin
cntxt1 = dpic_getcontext();
begin : caller_context
// call from a different scope - should still get the context of the function declaration
cntxt2 = dpic_getcontext();
end
// svContext should be the context of the function declaration, not the context of the function call
if (cntxt1 != cntxt2) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class p1328D { public: void solve() { int q; cin >> q; while (q--) { int n; cin >> n; vector<int> t(n); for (int i = 0; i < n; i++) cin >> t[i]; int sum = 1; for (int i = 1; i < n; i++) { if (t[i] == t[i - 1]) sum++; } if (sum == n) { cout << 1 << endl; for (int i = 0; i < n; i++) cout << 1 << ; cout << endl; } else if (n % 2 == 0 || t.back() == t.front()) { cout << 2 << endl; for (int i = 0; i < n; i++) cout << i % 2 + 1 << ; cout << endl; } else if (sum > 1) { cout << 2 << endl; bool can = true; for (int i = 0; i < n; i++) { if (can && i > 0 && t[i] == t[i - 1]) { cout << (i - 1) % 2 + 1 << ; can = false; } else if (!can) cout << (i - 1) % 2 + 1 << ; else cout << i % 2 + 1 << ; } cout << endl; } else { cout << 3 << endl; for (int i = 0; i < n - 1; i++) cout << i % 2 + 1 << ; cout << 3 << endl; } } } }; class p1327E { public: long long MOD = 998244353; long long fastpow(long long x, long long n) { if (n == 0) return 1ll; if (n == 1) return x; long long temp = fastpow(x, n / 2); if (n % 2 == 0) return (temp * temp) % MOD; else return (((x * temp) % MOD) * temp) % MOD; } void solve() { int n; cin >> n; if (n < 2) { cout << 10 << endl; return; } int maxn = 2e5 + 10; vector<long long> dp(maxn, 1); for (int i = 1; i <= maxn; i++) { dp[i] = (dp[i - 1] * 10) % MOD; } for (int i = 1; i < n; i++) { long long res = 2 * 10 * 9 * dp[n - i - 1] % MOD; res += (n - i - 1) * 10 * 9 * 9 * dp[n - i - 2] % MOD; cout << res % MOD << ; } cout << 10 << endl; } }; class p161D { public: long long res, k, n; vector<vector<int>> e; vector<vector<long long>> dp; void dfs(int cur, int fa) { dp[cur][0] = 1; for (int c : e[cur]) { if (c == fa) continue; dfs(c, cur); for (int i = 1; i <= k; i++) { dp[cur][i] += dp[c][i - 1]; } } res += dp[cur][k]; long long temp = 0; for (int c : e[cur]) { if (c == fa) continue; for (int i = 0; k - 2 - i >= 0; i++) { temp += dp[c][i] * (dp[cur][k - i - 1] - dp[c][k - i - 2]); } } res += temp / 2; } void solve() { cin >> n >> k; e = vector<vector<int>>(n + 1); dp = vector<vector<long long>>(n + 1, vector<long long>(k + 1, 0)); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; e[a].push_back(b); e[b].push_back(a); } res = 0; dfs(1, 0); cout << res << endl; } }; class p1437C { public: void solve() { int q; cin >> q; while (q--) { int n; cin >> n; vector<int> t(n); for (int i = 0; i < n; i++) cin >> t[i]; sort(t.begin(), t.end()); vector<vector<int>> dp(2 * n + 1, vector<int>(n + 1, 0x3f3f3f3f)); dp[0][0] = 0; int res = 0x3f3f3f3f; for (int k = 1; k <= 2 * n; k++) { for (int i = 1; i <= n; i++) { for (int pre = 0; pre <= k - 1; pre++) { dp[k][i] = min(dp[k][i], dp[pre][i - 1] + abs(t[i - 1] - k)); } } res = min(res, dp[k][n]); } cout << res << endl; } } }; class p1038D { public: void solve() { int n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; if (n == 1) { cout << a[0] << endl; return; } long long ans = 0, minval = 0x3f3f3f3f; bool pos = 0, neg = 0; for (int i = 0; i < n; i++) { ans += abs(a[i]); pos |= (a[i] >= 0); neg |= (a[i] <= 0); minval = min(minval, abs(a[i])); } if (pos && neg) cout << ans << endl; else cout << ans - 2 * minval << endl; } }; class p1286A { public: void solve() { int n; cin >> n; vector<int> p(n); unordered_set<int> cnt; for (int i = 1; i <= n; i++) cnt.insert(i); for (int i = 0; i < n; i++) { cin >> p[i]; if (p[i] != 0) cnt.erase(p[i]); } int odd = 0, even = 0; for (int i : cnt) if (i % 2) odd++; else even++; vector<vector<vector<int>>> dp( n + 1, vector<vector<int>>(n + 1, vector<int>(2, 0x3f3f3f3f))); dp[0][0][0] = dp[0][0][1] = 0; for (int i = 1; i <= n; i++) { int cur = p[i - 1] % 2; for (int j = 0; j <= min(odd, i); j++) { if (p[i - 1] != 0) { dp[i][j][cur] = min(dp[i - 1][j][0] + (0 ^ cur), dp[i - 1][j][1] + (1 ^ cur)); } else { if (j >= 1) { dp[i][j][1] = min( dp[i][j][1], min(dp[i - 1][j - 1][0] + 1, dp[i - 1][j - 1][1])); } dp[i][j][0] = min(dp[i][j][0], min(dp[i - 1][j][0], dp[i - 1][j][1] + 1)); } } } cout << min(dp[n][odd][0], dp[n][odd][1]) << endl; } }; class p580D { public: void solve() { int n, m, k; cin >> n >> m >> k; vector<long long> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<long long>> cost(n + 1, vector<long long>(n + 1, 0)); vector<vector<long long>> dp(1 << n, vector<long long>(n + 1, 0)); for (int i = 0; i < k; i++) { long long x, y, c; cin >> x >> y >> c; cost[x][y] = c; } long long ans = 0; for (int i = 1; i <= n; i++) { dp[1 << (i - 1)][i] = a[i]; } for (int i = 1; i < (1 << n); i++) { int cnt = bitset<32>(i).count(); for (int j = 1; j <= n; j++) { if ((i & (1 << (j - 1))) != 0) { int pre = i ^ (1 << (j - 1)); for (int k = 1; k <= n; k++) { if ((pre & (1 << (k - 1))) == 0) continue; dp[i][j] = max(dp[i][j], dp[pre][k] + cost[k][j] + a[j]); } if (cnt == m) ans = max(ans, dp[i][j]); } } } cout << ans << endl; } }; class p1335E2 { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<int>> sum(n + 1, vector<int>(205, 0)); vector<vector<int>> pos(205); int res = 0; for (int i = 1; i <= n; i++) { sum[i][a[i]]++; for (int j = 1; j <= 200; j++) { sum[i][j] += sum[i - 1][j]; res = max(res, sum[i][j]); } pos[a[i]].push_back(i); } for (int i = 1; i <= 200; i++) { int len = pos[i].size(); for (int k = 0; k < len - 1 - k; k++) { int l = pos[i][k], r = pos[i][len - 1 - k] - 1; int mid = 0; for (int j = 1; j <= 200; j++) { mid = max(mid, sum[r][j] - sum[l][j]); } res = max(res, 2 * (k + 1) + mid); } } cout << res << endl; } } }; class p1221D { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<long long> a(n + 1), b(n + 1); a[0] = 0; for (int i = 1; i <= n; i++) cin >> a[i] >> b[i]; vector<vector<long long>> dp(n + 1, vector<long long>(4, -1)); dp[0][0] = dp[0][1] = dp[0][2] = dp[0][3] = 0; long long res = LONG_LONG_MAX; for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= 2; j++) { for (int k = 0; k <= 2; k++) { if (a[i] + j != a[i - 1] + k) { auto cur = j * b[i] + dp[i - 1][k]; dp[i][j] = dp[i][j] == -1 ? cur : min(dp[i][j], cur); } } if (i == n) res = min(res, dp[i][j]); } } cout << res << endl; } } }; class p543A { public: void solve() { int n, m, b, md; cin >> n >> m >> b >> md; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<int>> dp(m + 1, vector<int>(b + 1, 0)); dp[0][0] = 1; for (int i = 1; i <= n; i++) { for (int k = 0; k <= m; k++) { for (int j = 0; j <= b; j++) { if (j >= a[i] && k > 0) dp[k][j] = (dp[k][j] + dp[k - 1][j - a[i]]) % md; } } } long long res = 0; for (int i = 0; i <= b; i++) res = (res + dp[m][i]) % md; cout << res << endl; } }; class p1142A { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int left = a[0]; bool ok = 1; int mx = 0; for (int i = 1; i < n; i++) { if (mx > a[i]) { ok = false; break; } a[i] -= mx; if (left >= a[i]) left = a[i]; else { mx += a[i] - left; } } if (ok) cout << YES << endl; else cout << NO << endl; } } }; class p1244D { public: vector<int> node; vector<vector<int>> e; void dfs(int cur, int fa) { node.push_back(cur); for (int c : e[cur]) { if (c == fa) continue; dfs(c, cur); } } void solve() { int n; cin >> n; vector<vector<long long>> cost(n + 1, vector<long long>(3, 0)); for (int j = 0; j < 3; j++) { for (int i = 1; i <= n; i++) { cin >> cost[i][j]; } } e = vector<vector<int>>(n + 1); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; e[u].push_back(v); e[v].push_back(u); if (e[u].size() > 2 || e[v].size() > 2) { cout << -1 << endl; return; } } int start = -1; for (int i = 1; i <= n; i++) { if (e[i].size() == 1) { start = i; break; } } dfs(start, -1); long long res = 4e18; int x = -1, y = -1; for (int i = 0; i < 3; i++) { for (int k = 0; k < 3; k++) { if (k == i) continue; long long temp = 0; temp += cost[node[0]][i] + cost[node[1]][k]; int a = i, b = k; for (int j = 2; j < node.size(); j++) { for (int l = 0; l < 3; l++) { if (l == a || l == b) continue; temp += cost[node[j]][l]; a = b; b = l; break; } } if (temp < res) { res = temp; x = i; y = k; } } } cout << res << endl; vector<int> ans(n + 1, 0); ans[node[0]] = x; ans[node[1]] = y; for (int i = 2; i < node.size(); i++) { for (int l = 0; l < 3; l++) { if (l == x || l == y) continue; ans[node[i]] = l; x = y; y = l; break; } } for (int i = 1; i <= n; i++) cout << ans[i] + 1 << ; cout << endl; } }; class p519D { public: void solve() { vector<long long> cnt(26, 0); for (int i = 0; i < 26; i++) cin >> cnt[i]; string s; cin >> s; int n = s.size(); vector<long long> sum(n + 1, 0); for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + cnt[s[i - 1] - a ]; } long long res = 0; unordered_map<long long, long long> mp[26]; for (int i = 1; i <= n; i++) { int cur = s[i - 1] - a ; res += mp[cur][sum[i] - cnt[cur]]; mp[cur][sum[i]]++; } cout << res << endl; } }; class p1096D { public: void solve() { int n; cin >> n; string s; cin >> s; vector<long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } unordered_map<char, int> cnt; cnt[ h ] = 0; cnt[ a ] = 1; cnt[ r ] = 2; cnt[ d ] = 3; vector<long long> dp(4, 0); for (int i = 0; i < n; i++) { if (!cnt.count(s[i])) continue; if (s[i] == h ) dp[0] += a[i]; else dp[cnt[s[i]]] = min(dp[cnt[s[i]] - 1], dp[cnt[s[i]]] + a[i]); } cout << dp[3] << endl; } }; class p1296E1 { public: void solve() { int n; cin >> n; string s; cin >> s; vector<int> res(n); res[0] = 0; char first = s[0]; char second = a - 1; for (int i = 1; i < n; i++) { if (s[i] >= first) { res[i] = 0; first = s[i]; } else { if (s[i] >= second) { res[i] = 1; second = s[i]; } else { cout << NO << endl; return; } } } cout << YES << endl; for (int i : res) cout << i; cout << endl; } }; class p1296E2 { public: void solve() { int n; cin >> n; string s; cin >> s; vector<int> dp(26, 0); int res = 0; vector<int> ans; for (int i = 0; i < n; i++) { int d = 1; for (int j = s[i] - a + 1; j < 26; j++) { d = max(d, dp[j] + 1); } dp[s[i] - a ] = d; ans.emplace_back(d); } for (int i = 0; i < 26; i++) res = max(res, dp[i]); cout << res << endl; for (auto c : ans) cout << c << ; cout << endl; } }; class D { public: void solve() { int t; cin >> t; for (int i = 1; i <= t; i++) { int n, q; cin >> n >> q; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); vector<long long> sum(n + 1, 0); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i - 1]; unordered_set<long long> cnt; cnt.insert(sum[n]); queue<pair<long long, long long>> que; que.emplace(0, n - 1); while (!que.empty()) { auto u = que.front(); que.pop(); if (u.first > u.second) continue; auto l = a[u.first], r = a[u.second]; cnt.insert(sum[u.second + 1] - sum[u.first]); if (u.first == u.second) continue; long long mid = (l + r) / 2; auto it = upper_bound(a.begin() + u.first, a.begin() + u.second + 1, mid) - a.begin(); if (it - 1 >= u.first && it - 1 != u.second) que.emplace(u.first, it - 1); if (it <= u.second && it != u.first) que.emplace(it, u.second); } while (q--) { long long s; cin >> s; if (cnt.count(s)) cout << YES << endl; else cout << NO << endl; } } } }; class p1462F { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<pair<long long, long long>> c; vector<int> a, b; c.clear(); for (int i = 0; i < n; i++) { long long l, r; cin >> l >> r; a.push_back(l); b.push_back(r); c.emplace_back(l, r); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); int res = n; for (int i = 0; i < n; i++) { auto leftcnt = lower_bound(b.begin(), b.end(), c[i].first) - b.begin(); auto rightcnt = upper_bound(a.begin(), a.end(), c[i].second) - a.begin(); res = min(res, (int)(leftcnt + n - rightcnt)); } cout << res << endl; } } }; class p1324F { public: vector<int> a; vector<int> dp; int n; vector<vector<int>> e; vector<int> fa; int dfs(int cur, int f) { dp[cur] = a[cur]; for (int child : e[cur]) { if (child == f) continue; int next = dfs(child, cur); dp[cur] += max(0, next); } return dp[cur]; } void dfs2(int cur, int fa) { dp[cur] = max(dp[cur], dp[cur] + max(0, dp[fa] - max(0, dp[cur]))); for (int c : e[cur]) { if (c == fa) continue; dfs2(c, cur); } } void solve() { cin >> n; a = vector<int>(n + 1); e = vector<vector<int>>(n + 1); dp = vector<int>(n + 1, 0); fa = vector<int>(n + 1, 0); for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == 0) a[i] = -1; } for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; e[u].emplace_back(v); e[v].emplace_back(u); } dfs(1, 0); dfs2(1, 0); for (int i = 1; i <= n; i++) { cout << dp[i] << ; } cout << endl; } }; class p1446B { public: void solve() { int n, m; cin >> n >> m; string s, t; cin >> s >> t; vector<vector<int>> dp(n + 1, vector<int>(m + 1, 0)); int res = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (s[i - 1] == t[j - 1]) { dp[i][j] = max(dp[i][j], dp[i - 1][j - 1] + 2); } dp[i][j] = max(dp[i][j], max(dp[i - 1][j] - 1, dp[i][j - 1] - 1)); res = max(res, dp[i][j]); } } cout << res << endl; } }; class p1283E { public: void solve() { int n; cin >> n; vector<int> x(n); for (int i = 0; i < n; i++) cin >> x[i]; int maxn = 200005; int ans1 = 0, ans2 = 0; unordered_map<int, int> cnt; for (int i : x) cnt[i]++; for (int i = 1; i <= n; i++) { if (cnt[i] > 0) { ans1++; i += 2; } } for (int i = 1; i <= n + 1; i++) { if (cnt[i - 1] == 0 && cnt[i] > 0) { cnt[i - 1]++; cnt[i]--; } if (cnt[i] > 1) { cnt[i]--; cnt[i + 1]++; } } for (int i = 0; i <= n + 1; i++) { if (cnt[i] > 0) ans2++; } printf( %d %d n , ans1, ans2); } }; class p148D { public: vector<vector<vector<double>>> dp; double dfs(int w, int b, int cur) { if (dp[w][b][cur] >= 0.0) return dp[w][b][cur]; if (w == 0) { if (cur == 0) dp[w][b][cur] = 0.0; else dp[w][b][cur] = 1.0; return dp[w][b][cur]; } if (b == 0) { dp[w][b][cur] = 1.0; return 1.0; } dp[w][b][cur] = 1.0 * w / (w + b); if (cur == 0) { dp[w][b][cur] += (1.0 - dfs(w, b - 1, 1 - cur)) * (1.0 * b / (w + b)); } else { dp[w][b][cur] += (1.0 - dfs(w - 1, b - 1, 1 - cur)) * (1.0 * b / (w + b)) * (1.0 * w / (w + b - 1)); if (b >= 2) { dp[w][b][cur] += (1.0 - dfs(w, b - 2, 1 - cur)) * (1.0 * b / (w + b)) * (1.0 * (b - 1) / (w + b - 1)); } } return dp[w][b][cur]; } void solve() { int w, b; cin >> w >> b; dp = vector<vector<vector<double>>>( w + 1, vector<vector<double>>(b + 1, vector<double>(2, -1))); double res = dfs(w, b, 0); printf( %.9lf n , res); } }; class p95B { public: string ans, s; bool dfs(int id, int sum4, int sum7, bool ok) { if (id >= s.size()) return 1; if (ok) { ans.append(sum4, 4 ); ans.append(sum7, 7 ); return 1; } if (s[id] <= 4 && sum4) { ans.push_back( 4 ); if (dfs(id + 1, sum4 - 1, sum7, s[id] < 4 )) return true; ans.pop_back(); } if (s[id] <= 7 && sum7) { ans.push_back( 7 ); if (dfs(id + 1, sum4, sum7 - 1, s[id] < 7 )) return 1; ans.pop_back(); } return 0; } void solve() { cin >> s; ans.clear(); s.clear(); s.append(100000, 4 ); cout << s << endl; int n = s.size(); if (n % 2 || !dfs(0, n / 2, n / 2, 0)) { ans.append((n + 2) / 2, 4 ); ans.append((n + 2) / 2, 7 ); cout << ans << endl; } else cout << ans << endl; } }; class p182E { public: void solve() { int n, h; cin >> n >> h; vector<vector<vector<int>>> dp( h + 1, vector<vector<int>>(n + 1, vector<int>(2, 0))); for (int i = 0; i < n; i++) dp[0][i][0] = dp[0][i][1] = 1; vector<pair<long long, long long>> a(n); for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } long long res = 0; for (int i = 1; i <= h; i++) { for (int j = 0; j < n; j++) { int l = a[j].first, w = a[j].second; if (i == l) dp[i][j][0] = (dp[i][j][0] + 1) % 1000000007; if (i == w && l != w) dp[i][j][1] = (dp[i][j][1] + 1) % 1000000007; for (int k = 0; k < n; k++) { if (k == j) continue; int pl = a[k].first, pw = a[k].second; if (i > l) { dp[i][j][0] = (dp[i][j][0] + dp[i - l][k][0] * (l == pw)) % 1000000007; dp[i][j][0] = (dp[i][j][0] + dp[i - l][k][1] * (l == pl)) % 1000000007; } if (i > w && l != w) { dp[i][j][1] = (dp[i][j][1] + dp[i - w][k][0] * (w == pw)) % 1000000007; dp[i][j][1] = (dp[i][j][1] + dp[i - w][k][1] * (w == pl)) % 1000000007; } } if (i == h) res = (res + dp[i][j][0] + dp[i][j][1]) % 1000000007; } } cout << res << endl; } }; class p180E { public: void solve() { int n, m, k; cin >> n >> m >> k; unordered_map<int, vector<int>> cnt; for (int i = 0; i < n; i++) { int x; cin >> x; cnt[x].push_back(i); } int res = 0; for (auto it : cnt) { auto v = it.second; int sz = v.size(); deque<int> q; for (int r = 0; r < sz; r++) { q.push_back(v[r]); while (!q.empty() && q.back() - q.front() + 1 - q.size() > k) q.pop_front(); res = max(res, (int)q.size()); } } cout << res << endl; } }; class p30C { public: struct node { long long x, y, t; double p; node(long long xx, long long yy, long long tt, double pp) : x(xx), y(yy), t(tt), p(pp){}; node(){}; bool operator<(const node& rhs) const { return t < rhs.t; } }; void solve() { int n; cin >> n; vector<node> a; for (int i = 0; i < n; i++) { long long x, y, t; double p; cin >> x >> y >> t >> p; a.emplace_back(x, y, t, p); } sort(a.begin(), a.end()); vector<double> dp(a.size() + 1, 0.0); double res = 0.0; for (int i = 0; i < n; i++) { dp[i] = a[i].p; for (int j = 0; j < i; j++) { long long dis = abs(a[i].x - a[j].x) * abs(a[i].x - a[j].x) + abs(a[i].y - a[j].y) * abs(a[i].y - a[j].y); long long dt = (a[i].t - a[j].t) * (a[i].t - a[j].t); if (dis <= dt) dp[i] = max(dp[i], dp[j] + a[i].p); } res = max(res, dp[i]); } printf( %.7lf , res); } }; class p49D { public: void solve() { int n; cin >> n; string s; cin >> s; vector<vector<int>> dp(n, vector<int>(2, 0x3f3f3f3f)); dp[0][0] = s[0] != 0 ; dp[0][1] = s[0] != 1 ; for (int i = 1; i < n; i++) { dp[i][0] = s[i] != 0 ; dp[i][1] = s[i] != 1 ; dp[i][0] += dp[i - 1][1]; dp[i][1] += dp[i - 1][0]; } cout << min(dp[n - 1][0], dp[n - 1][1]) << endl; } }; class p721C { public: void solve() { int n, m, T; cin >> n >> m >> T; vector<vector<pair<long long, long long>>> e(n + 1); vector<int> in(n + 1, 0); for (int i = 0; i < m; i++) { int u, v, t; cin >> u >> v >> t; e[u].emplace_back(v, t); in[v]++; } queue<int> q; for (int i = 1; i <= n; i++) { if (!in[i]) q.push(i); } vector<vector<int>> dp(n + 1, vector<int>(n + 1, 0x3f3f3f3f)); vector<vector<int>> f(n + 1, vector<int>(n + 1, 0)); dp[1][1] = 0; while (!q.empty()) { int u = q.front(); q.pop(); for (auto& [v, w] : e[u]) { for (int j = 2; j <= n; j++) { if (dp[v][j] > dp[u][j - 1] + w) { dp[v][j] = dp[u][j - 1] + w; f[v][j] = u; } } in[v]--; if (!in[v]) q.push(v); } } int ans = -1; for (int j = n; j >= 1; j--) { if (dp[n][j] <= T) { ans = j; break; } } cout << ans << endl; vector<int> out; for (int i = n, j = ans; f[i][j] != 0; i = f[i][j], j--) out.push_back(i); out.push_back(1); reverse(out.begin(), out.end()); for (int i : out) cout << i << ; cout << endl; } }; class p830A { public: void solve() { long long n, k, p; cin >> n >> k >> p; vector<long long> a(n + 1, 0); vector<long long> b(k + 1, 0); for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= k; i++) cin >> b[i]; sort(a.begin(), a.end()); sort(b.begin(), b.end()); vector<vector<long long>> dp(n + 1, vector<long long>(k + 1, 1e18)); for (int i = 0; i <= k; i++) dp[0][i] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= k; j++) { dp[i][j] = min(dp[i][j - 1], max(dp[i - 1][j - 1], abs(a[i] - b[j]) + abs(p - b[j]))); } } cout << dp[n][k] << endl; } }; class p983B { public: void solve() { int n; cin >> n; vector<int> a(n + 1); vector<vector<int>> f(n + 1, vector<int>(n + 1, 0)); vector<vector<int>> dp(n + 1, vector<int>(n + 1, 0)); for (int i = 1; i <= n; i++) { cin >> a[i]; dp[i][i] = f[i][i] = a[i]; } for (int i = n; i >= 1; i--) { for (int j = i + 1; j <= n; j++) { f[i][j] = f[i][j - 1] ^ f[i + 1][j]; dp[i][j] = max(dp[i][j], f[i][j]); dp[i][j] = max(dp[i][j], max(dp[i + 1][j], dp[i][j - 1])); } } int q; cin >> q; while (q--) { int l, r; cin >> l >> r; cout << dp[l][r] << endl; } } }; class p671A { public: struct node { long long x, y, id; double dist, disa, disb; node(int _x, int _y, int _id, double t, double a, double b) { x = _x; y = _y; id = _id; dist = t; disa = a; disb = b; } }; void solve() { long long ax, ay, bx, by, tx, ty; cin >> ax >> ay >> bx >> by >> tx >> ty; int n; cin >> n; vector<node> bt1, bt2; auto distance = [](long long x1, long long y1, long long x2, long long y2) { long long dx = abs(x1 - x2); long long dy = abs(y1 - y2); return 1.0 * sqrt(dx * dx + dy * dy); }; double res = 0.0; for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; auto dt = distance(x, y, tx, ty); auto da = distance(x, y, ax, ay); auto db = distance(x, y, bx, by); res += 2.0 * dt; bt1.emplace_back(x, y, i, dt, da, db); bt2.emplace_back(x, y, i, dt, da, db); } sort(bt1.begin(), bt1.end(), [](const node& a, const node& b) { return a.disa - a.dist < b.disa - b.dist; }); sort(bt2.begin(), bt2.end(), [](const node& a, const node& b) { return a.disb - a.dist < b.disb - b.dist; }); int i = 0, j = 0; double temp = min(res + bt1[i].disa - bt1[i].dist, res + bt2[j].disb - bt2[j].dist); if (bt1[i].id != bt2[j].id) { res += bt1[i].disa - bt1[i].dist; res += bt2[j].disb - bt2[j].dist; } else { res += min(bt1[0].disa - bt1[0].dist + (bt2.size() > 1 ? bt2[1].disb - bt2[1].dist : 0), bt2[0].disb - bt2[0].dist + (bt1.size() > 1 ? bt1[1].disa - bt1[1].dist : 0)); } res = min(temp, res); printf( %.15f n , res); } }; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); p671A ans; ans.solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:31:43 08/22/2017
// Design Name:
// Module Name: dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dma(
input clkin,
input reset,
input enable,
input [3:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_we_rising,
output loop_enable,
input BUS_RDY,
output BUS_RRQ,
output BUS_WRQ,
output [23:0] ROM_ADDR,
output [15:0] ROM_DATA_OUT,
output ROM_WORD_ENABLE,
input [15:0] ROM_DATA_IN
);
parameter ST_IDLE = 0;
parameter ST_READ = 1;
parameter ST_WRITE = 2;
parameter ST_DONE = 3;
parameter OP_COPY = 0;
parameter OP_RESET = 1;
parameter OP_SET = 2;
parameter OP_DEBUG = 3;
// Register bank
reg [7:0] dma_r[15:0];
reg [2:0] state; initial state = ST_IDLE;
initial begin
dma_r[0] = 8'h00; // dst bank
dma_r[1] = 8'h00; // src bank
dma_r[2] = 8'h00; // dst[7:0]
dma_r[3] = 8'h00; // dst[15:8]
dma_r[4] = 8'h00; // src[7:0]
dma_r[5] = 8'h00; // src[15:0]
dma_r[6] = 8'h00; // len[7:0]
dma_r[7] = 8'h00; // len[15:8]
dma_r[8] = 8'h00; // len[23:16]
dma_r[9] = 8'h00; // opcode[7:3], loop, direction, trigger
end
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
integer i;
always @(posedge clkin) begin
if(reg_oe_falling & enable) begin
case(reg_addr)
4'h0: data_out_r <= 8'h53;
4'h1: data_out_r <= 8'h2D;
4'h2: data_out_r <= 8'h44;
4'h3: data_out_r <= 8'h4D;
4'h4: data_out_r <= 8'h41;
4'h5: data_out_r <= 8'h31;
4'h9: data_out_r <= dma_r[reg_addr];
default: data_out_r <= 8'h00;
endcase
end
end
always @(posedge clkin) begin
if (reset) begin
for (i = 0; i < 10; i = i + 1) dma_r[i] <= 0;
end
else if(reg_we_rising & enable) begin
dma_r[reg_addr] <= reg_data_in;
end
else if (state == ST_DONE) begin
dma_r[9][0] <= 0;
end
end
wire [23:0] SRC_ADDR, DST_ADDR, LEN;
wire [4:0] OPCODE;
wire LOOP, DIR, TRIG, WORD_MODE;
assign SRC_ADDR = {dma_r[1], dma_r[3], dma_r[2]};
assign DST_ADDR = {dma_r[0], dma_r[5], dma_r[4]};
assign LEN = {dma_r[8], dma_r[7], dma_r[6]};
assign OPCODE = dma_r[9][7:3];
assign LOOP = dma_r[9][2];
assign DIR = dma_r[9][1];
assign TRIG = dma_r[9][0];
// this covers misaligned addresses, misaligned length, as well as byte overlaps
assign WORD_MODE = !SRC_ADDR[0] && !DST_ADDR[0] && !LEN[0];
reg [15:0] data;
reg [4:0] opcode_r;
reg loop_r; initial loop_r = 0;
reg dir_r;
reg trig_r; initial trig_r = 0;
reg word_mode_r;
reg [23:0] src_addr_r, dst_addr_r, length_r, mod_r;
assign BUS_RRQ = BUS_RDY && (state == ST_READ);
assign BUS_WRQ = BUS_RDY && (state == ST_WRITE);
assign ROM_ADDR = (state == ST_READ) ? src_addr_r : dst_addr_r;
assign ROM_DATA_OUT = (opcode_r == OP_COPY) ? (dst_addr_r[0] ? {ROM_DATA_IN[7:0],ROM_DATA_IN[15:8]} : ROM_DATA_IN)
: (opcode_r == OP_RESET) ? 16'h0000
: (opcode_r == OP_SET) ? 16'hFFFF
: (opcode_r == OP_DEBUG) ? {dst_addr_r[3:0],loop_enable,ROM_WORD_ENABLE,mod_r[1:0],dst_addr_r[3:0],loop_enable,ROM_WORD_ENABLE,mod_r[1:0]}
: 0;
assign ROM_WORD_ENABLE = word_mode_r;
assign loop_enable = loop_r;
wire [23:0] length_next = length_r - (word_mode_r ? 2 : 1);
always @(posedge clkin) begin
if (reset) begin
loop_r <= 0;
state <= ST_IDLE;
trig_r <= 0;
end
else begin
trig_r <= TRIG;
case (state)
ST_IDLE: begin
if (TRIG && (trig_r ^ TRIG)) begin
src_addr_r <= SRC_ADDR;
dst_addr_r <= DST_ADDR;
length_r <= LEN;
mod_r <= WORD_MODE ? (DIR ? -2 : 2) : (DIR ? -1 : 1);
opcode_r <= OPCODE;
loop_r <= LOOP;
dir_r <= DIR;
word_mode_r <= WORD_MODE;
if (OPCODE == OP_COPY) state <= ST_READ;
else state <= ST_WRITE;
end
end
ST_READ: begin
if (BUS_RDY) begin
src_addr_r <= src_addr_r + mod_r;
state <= ST_WRITE;
end
end
ST_WRITE: begin
if (BUS_RDY) begin
dst_addr_r <= dst_addr_r + mod_r;
length_r <= length_next;
if (length_next == 0) state <= ST_DONE;
else if (opcode_r == OP_COPY) state <= ST_READ;
else state <= ST_WRITE;
end
end
ST_DONE: begin
loop_r <= 0;
state <= ST_IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; char buf[100], name[100], op[100], tmp[100]; struct widget { long long x, y; bool finish; int type, border, spacing; vector<int> w; widget(long long xx = 0, long long yy = 0, int t = 0) { x = xx; y = yy; type = t; w = vector<int>(); finish = false; border = spacing = 0; } void gao(){}; } wid[110]; map<string, int> mp; void gao(int id) { if (wid[id].finish || wid[id].type == 0) return; long long &x = wid[id].x; long long &y = wid[id].y; x = y = 0; for (int i = 0; i < ((int)wid[id].w.size()); ++i) { int z = wid[id].w[i]; gao(z); if (wid[id].type == 1) { x += wid[z].x + wid[id].spacing; y = max(y, wid[z].y); } else { y += wid[z].y + wid[id].spacing; x = max(x, wid[z].x); } } wid[id].finish = true; if (((int)wid[id].w.size()) == 0) return; if (wid[id].type == 1) { x += wid[id].border * 2 - wid[id].spacing; y += wid[id].border * 2; } else { y += wid[id].border * 2 - wid[id].spacing; x += wid[id].border * 2; } } void solve() { mp.clear(); int x, y, tot = 0; for (int i = 0; i < n; ++i) { scanf( %s , buf); if (string(buf) == Widget ) { scanf( %s , buf); sscanf(buf, %[^(](%d,%d) , name, &x, &y); mp[name] = tot; wid[tot++] = widget(x, y, 0); } else if (string(buf) == HBox ) { scanf( %s , buf); mp[buf] = tot; wid[tot++] = widget(-1, -1, 1); } else if (string(buf) == VBox ) { scanf( %s , buf); mp[buf] = tot; wid[tot++] = widget(-1, -1, 2); } else { sscanf(buf, %[^.].%[^(](%[^)] , name, op, tmp); int id = mp[name]; if (string(op) == set_border ) { sscanf(tmp, %d , &x); wid[id].border = x; } else if (string(op) == set_spacing ) { sscanf(tmp, %d , &x); wid[id].spacing = x; } else { wid[id].w.push_back(mp[tmp]); } } } map<string, int>::iterator it = mp.begin(); for (; it != mp.end(); ++it) { int id = it->second; gao(id); printf( %s %I64d %I64d n , it->first.c_str(), wid[id].x, wid[id].y); } puts( ); } int main() { while (scanf( %d , &n) != EOF) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long input[(long long)1e5 + 1]; long long ans = 0; long long n; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> input[i]; for (int i = n - 2; i >= 0; i--) { if (input[i] > input[i + 1]) ans += input[i] - input[i + 1]; } cout << ans << endl; return 0; }
|
// File ifchain.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module test(
clk,
rstn
);
input clk, rstn;
wire clk;
wire rstn;
wire [3:0] a;
wire [3:0] b;
reg status;
reg [31:0] c[3:0];
always @(posedge clk) begin
if({b[1],a[3:2]} == 3'b 001) begin
status <= 1'b 1;
c[0] <= 16'h FFFF;
end
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module MakeResetA (
CLK,
RST_N,
ASSERT_IN,
ASSERT_OUT,
DST_CLK,
OUT_RST_N
);
parameter RSTDELAY = 2 ; // Width of reset shift reg
parameter init = 1 ;
input CLK ;
input RST_N ;
input ASSERT_IN ;
output ASSERT_OUT ;
input DST_CLK ;
output OUT_RST_N ;
reg rst ;
wire OUT_RST_N ;
assign ASSERT_OUT = !rst ;
SyncResetA #(RSTDELAY) rstSync (.CLK(DST_CLK),
.IN_RST_N(rst),
.OUT_RST_N(OUT_RST_N));
always@(posedge CLK or negedge RST_N) begin
if (RST_N == 0)
rst <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (ASSERT_IN)
rst <= `BSV_ASSIGNMENT_DELAY 1'b0;
else // if (rst == 1'b0)
rst <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
#0 ;
rst = 1'b1 ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // MakeResetA
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:57:49 04/12/2014
// Design Name:
// Module Name: Test_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NIST(
input wire clk,
input wire rst,
input wire rand,
output wire [7:0] test_result
);
assign test_result[7] = 0;
Frequency test1(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[0])
);
Frequency_Block test2(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[1])
);
Runs test3(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[2])
);
Longest_Run_of_Ones test4(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[3])
);
Nonoverlapping_template test7(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[4])
);
Overlapping_template test8(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[5])
);
Cumulative_Sums test13(
.clk(clk),
.rst(rst),
.rand(rand),
.pass(test_result[6])
);
endmodule
|
/**
* bsg_cache_to_axi_rx.v
*
* @author tommy
*/
`include "bsg_defines.v"
module bsg_cache_to_axi_rx
#(parameter `BSG_INV_PARAM(num_cache_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter tag_fifo_els_p=num_cache_p
,parameter `BSG_INV_PARAM(axi_id_width_p)
,parameter `BSG_INV_PARAM(axi_addr_width_p)
,parameter `BSG_INV_PARAM(axi_data_width_p)
,parameter `BSG_INV_PARAM(axi_burst_len_p)
,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
,parameter data_width_ratio_lp=(axi_data_width_p/data_width_p)
)
(
input clk_i
,input reset_i
,input v_i
,output logic yumi_o
,input [lg_num_cache_lp-1:0] tag_i
,input [axi_addr_width_p-1:0] axi_addr_i
// cache dma read channel
,output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
,output logic [num_cache_p-1:0] dma_data_v_o
,input [num_cache_p-1:0] dma_data_ready_i
// axi read address channel
,output logic [axi_id_width_p-1:0] axi_arid_o
,output logic [axi_addr_width_p-1:0] axi_araddr_o
,output logic [7:0] axi_arlen_o
,output logic [2:0] axi_arsize_o
,output logic [1:0] axi_arburst_o
,output logic [3:0] axi_arcache_o
,output logic [2:0] axi_arprot_o
,output logic axi_arlock_o
,output logic axi_arvalid_o
,input axi_arready_i
// axi read data channel
,input [axi_id_width_p-1:0] axi_rid_i
,input [axi_data_width_p-1:0] axi_rdata_i
,input [1:0] axi_rresp_i
,input axi_rlast_i
,input axi_rvalid_i
,output logic axi_rready_o
);
// suppress unused
//
wire [axi_id_width_p-1:0] unused_rid = axi_rid_i;
wire [1:0] unused_rresp = axi_rresp_i;
wire unused_rlast = axi_rlast_i;
// tag fifo
//
logic tag_fifo_v_li;
logic tag_fifo_ready_lo;
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
logic [lg_num_cache_lp-1:0] tag_lo;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(tag_fifo_els_p)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tag_fifo_v_li)
,.ready_o(tag_fifo_ready_lo)
,.data_i(tag_i)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_lo)
,.yumi_i(tag_fifo_yumi_li)
);
// yumi when both tag_fifo and axi_ar are ready
assign yumi_o = v_i & axi_arready_i & tag_fifo_ready_lo;
// tag_fifo is valid when axi_ar is ready
assign tag_fifo_v_li = v_i & axi_arready_i;
// axi read address channel
//
assign axi_arid_o = {axi_id_width_p{1'b0}};
assign axi_araddr_o = axi_addr_i;
assign axi_arlen_o = (8)'(axi_burst_len_p-1); // burst length
assign axi_arsize_o = (3)'(`BSG_SAFE_CLOG2(axi_data_width_p>>3));
assign axi_arburst_o = 2'b01; // incr
assign axi_arcache_o = 4'b0000; // non-bufferable
assign axi_arprot_o = 2'b00; // unprevileged
assign axi_arlock_o = 1'b0; // normal access
// axi_ar is valid when tag_fifo is ready
assign axi_arvalid_o = v_i & tag_fifo_ready_lo;
// axi read data channel
//
logic piso_v_lo;
logic [data_width_p-1:0] piso_data_lo;
logic piso_yumi_li;
bsg_parallel_in_serial_out #(
.width_p(data_width_p)
,.els_p(data_width_ratio_lp)
) piso (
.clk_i(clk_i)
,.reset_i(reset_i)
,.valid_i(axi_rvalid_i)
,.data_i(axi_rdata_i)
,.ready_and_o(axi_rready_o)
,.valid_o(piso_v_lo)
,.data_o(piso_data_lo)
,.yumi_i(piso_yumi_li)
);
logic [num_cache_p-1:0] cache_sel;
// demux
//
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
assign dma_data_v_o = cache_sel & {num_cache_p{piso_v_lo}};
for (genvar i = 0; i < num_cache_p; i++) begin
assign dma_data_o[i] = piso_data_lo;
end
// counter
//
logic [`BSG_SAFE_CLOG2(block_size_in_words_p)-1:0] count_lo;
logic counter_clear_li;
logic counter_up_li;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p-1)
,.init_val_p(0)
) counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear_li)
,.up_i(counter_up_li)
,.count_o(count_lo)
);
assign piso_yumi_li = dma_data_ready_i[tag_lo] & piso_v_lo & tag_fifo_v_lo;
always_comb begin
if (count_lo == block_size_in_words_p-1) begin
counter_clear_li = piso_yumi_li;
counter_up_li = 1'b0;
tag_fifo_yumi_li = piso_yumi_li;
end
else begin
counter_clear_li = 1'b0;
counter_up_li = piso_yumi_li;
tag_fifo_yumi_li = 1'b0;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_axi_rx)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_TB_V
`define SKY130_FD_SC_HD__SDFRBP_TB_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfrbp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_TB_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("call1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 33;
reg [STACK_DEPTH:0] index = 0;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("call1_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#29
`assert(result, 42);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#17
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
module sender(iClock, iReset, iTxDone, iStartSignal, oAddress, oFinished, oTxSend);
parameter IDLE = 3'b000,
SENDING = 3'b001,
SEND_PACKET = 3'b010, // So serve para fazer o pulso de envio.
SENDING_PACKET = 3'b011,
INCREMENTING_ADDR = 3'b100,
FINISHED_SENDING = 3'b101;
input iClock;
input iReset;
input iTxDone;
input iStartSignal;
output oTxSend;
output oFinished;
output [15:0] oAddress;
reg [2:0] state = IDLE;
wire [2:0] next_state;
assign next_state = fsm_function(state, oAddress, iTxDone, iStartSignal);
function [2:0] fsm_function(input [2:0] state, input [15:0] current_address,
input tx_done, input sampling_finished);
case (state)
IDLE:
if (sampling_finished) begin
fsm_function = SENDING;
end else begin
fsm_function = IDLE;
end
SENDING:
if (current_address < 16'd100) begin
fsm_function = SEND_PACKET;
end else begin
fsm_function = FINISHED_SENDING; // Acabou de enviar os dados.
end
SEND_PACKET:
fsm_function = SENDING_PACKET;
SENDING_PACKET:
if (tx_done) begin
fsm_function = INCREMENTING_ADDR;
end else begin
fsm_function = SENDING_PACKET;
end
INCREMENTING_ADDR:
fsm_function = SENDING;
FINISHED_SENDING:
fsm_function = IDLE;
default:
fsm_function = IDLE;
endcase
endfunction
always@ (posedge iClock) begin
if (iReset) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
always@ (posedge iClock) begin
oTxSend <= 0;
oFinished <= 0;
case (state)
IDLE: begin
oAddress <= 16'h0;
end
SENDING: begin
end
SEND_PACKET: begin
oTxSend <= 1;
end
SENDING_PACKET: begin
end
INCREMENTING_ADDR: begin
oAddress <= oAddress + 16'b1;
end
FINISHED_SENDING: begin
oFinished <= 1;
end
default: begin
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int m[100005], v[100005], selected[100005]; vector<pair<pair<int, int>, int> > V; int k, n, h; bool check(long double time) { long double pos = 1.0; int id = 0; for (int i = 0; i < n; i++) { if (V[i].first.second * 1.0 * time >= pos * h) { selected[id++] = V[i].second; pos += 1.0; } } return (id >= k); } int main() { V.clear(); cin >> n >> k >> h; for (int i = 0; i < n; ++i) cin >> m[i]; for (int i = 0; i < n; ++i) cin >> v[i]; for (int i = 0; i < n; ++i) V.push_back(make_pair(make_pair(m[i], v[i]), i)); sort((V).begin(), (V).end()); long double l = 0, r = 1000000009, mid; for (int i = 0; i < 200; i++) { mid = (l + r) * 0.5; if (check(mid)) r = mid; else l = mid; } check(r); for (int i = 0; i < k; ++i) { if (i != 0) cout << ; cout << selected[i] + 1; } cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1100000000000000000; void solve() { long long n, k; cin >> n >> k; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long dp[k + 5][k + 5]; memset(dp, 0, sizeof(dp)); long long x = n % k, c = (n + k - 1) / k, s = n / k; ; long long y = k - x; for (long long i = 0; i <= x; i++) for (long long j = 0; j <= y; j++) dp[i][j] = inf; dp[0][0] = 0; for (long long i = 0; i <= x; i++) { if (i) for (long long j = 0; j <= y; j++) { long long idx = (i - 1) * c + s * j; dp[i][j] = min(dp[i][j], abs(a[idx + c - 1] - a[idx]) + dp[i - 1][j]); } for (long long j = 1; j <= y; j++) { long long idx = i * c + s * (j - 1); dp[i][j] = min(dp[i][j], abs(a[idx + s - 1] - a[idx]) + dp[i][j - 1]); } } cout << dp[x][y]; } signed main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); long long T = 1; while (T--) { solve(); cout << n ; } return 0; }
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for BfbIntersectionMutex
//defines for state names used internally
`define STATE_s_init 0
`define STATE_s_N_S_Go 1
`define STATE_s_E_W_Go 2
module FB_BfbIntersectionMutex
(
input wire clk,
//input events
input wire Start_eI,
input wire N_S_Done_eI,
input wire E_W_Done_eI,
//output events
output wire N_S_Start_eO,
output wire E_W_Start_eO,
input reset
);
////BEGIN internal copies of I/O
//input events
wire Start;
assign Start = Start_eI;
wire N_S_Done;
assign N_S_Done = N_S_Done_eI;
wire E_W_Done;
assign E_W_Done = E_W_Done_eI;
//output events
reg N_S_Start;
assign N_S_Start_eO = N_S_Start;
reg E_W_Start;
assign E_W_Start_eO = E_W_Start;
////END internal copies of I/O
////BEGIN internal vars
////END internal vars
//BEGIN STATE variables
reg [1:0] state = `STATE_s_init;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_s_init;
//reset I/O registers
N_S_Start = 1'b0;
E_W_Start = 1'b0;
//reset internal vars
end else begin
//BEGIN clear output events
N_S_Start = 1'b0;
E_W_Start = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_s_init: begin
if(Start) begin
state = `STATE_s_N_S_Go;
entered = 1'b1;
end
end
`STATE_s_N_S_Go: begin
if(N_S_Done) begin
state = `STATE_s_E_W_Go;
entered = 1'b1;
end
end
`STATE_s_E_W_Go: begin
if(E_W_Done) begin
state = `STATE_s_N_S_Go;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
if(entered) begin
case(state)
`STATE_s_init: begin
end
`STATE_s_N_S_Go: begin
N_S_Start = 1'b1;
end
`STATE_s_E_W_Go: begin
E_W_Start = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
//END algorithms
//BEGIN update external output variables on relevant events
//END update external output variables
end
end
endmodule
|
module omega_network_ff(clk, push, d_in, valid, d_out, control);
parameter WIDTH = 8;
parameter IN_PORTS = 8;
parameter OUT_PORTS = IN_PORTS;
parameter ADDR_WIDTH_PORTS = log2(OUT_PORTS-1);
input clk;
input [0:IN_PORTS-1] push;
input [IN_PORTS*WIDTH-1:0] d_in;
output [0:OUT_PORTS-1] valid;
output [OUT_PORTS*WIDTH-1:0] d_out;
input [ADDR_WIDTH_PORTS-1:0] control;
genvar g1, g2;
wire [WIDTH:0] stage [0:ADDR_WIDTH_PORTS][0:IN_PORTS-1];
generate
for(g1 = 0; g1 < IN_PORTS; g1 = g1 + 1) begin: generate_start
assign stage[0][g1][0] = push[g1];
assign stage[0][g1][WIDTH:1] = d_in[(g1+1)*WIDTH-1 -:WIDTH];
end
for(g1 = 0; g1 < ADDR_WIDTH_PORTS; g1 = g1 + 1) begin: generate_stage
for(g2 = 0; g2 < IN_PORTS/2; g2 = g2 + 1) begin: generate_switch
basic_switch_ff #(WIDTH+1) sw(clk, stage[g1][g2], stage[g1][g2+IN_PORTS/2], stage[g1+1][g2*2], stage[g1+1][g2*2+1], control[ADDR_WIDTH_PORTS-1-g1]);
end
end
for(g1 = 0; g1 < IN_PORTS; g1 = g1 + 1) begin: generate_end
assign valid[g1] = stage[ADDR_WIDTH_PORTS][g1][0];
assign d_out[(g1+1)*WIDTH-1 -:WIDTH] = stage[ADDR_WIDTH_PORTS][g1][WIDTH:1];
end
endgenerate
`include "log2.vh"
endmodule
|
#include <bits/stdc++.h> const long long mod = 998244353; const long long inf = 1e18 + 10; using namespace std; long long modpow(long long a, long long b) { long long res = 1; while (b) { if (b % 2) { res *= a; } a *= a; res %= mod; a %= mod; b /= 2; } return res; } long long nCr(long long n, long long r) { long long f = 1; for (long long i = 2; i <= n; i++) { f *= i; f %= mod; } long long q = 1; for (long long i = 2; i <= r; i++) { q *= i; q %= mod; } long long q2 = 1; for (long long i = 2; i <= n - r; i++) { q2 *= i; q2 %= mod; } q = modpow(q, mod - 2); q2 = modpow(q2, mod - 2); f *= q; f %= mod; f *= q2; f %= mod; return f; } int32_t main() { std::ios::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; long long a[2 * n]; for (long long i = 0; i < 2 * n; i++) cin >> a[i]; sort(a, a + 2 * n); long long l = 0, r = 0; for (long long i = 0; i < n; i++) l += a[i]; for (long long i = n; i < 2 * n; i++) r += a[i]; long long ans = r - l; ans %= mod; cout << ((ans * nCr(2 * n, n)) % mod) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long modexpo(long long x, long long p) { long long res = 1; x = x % 1000000007; while (p) { if (p % 2) res = res * x; p >>= 1; x = x * x % 1000000007; res %= 1000000007; } return res; } struct compare { bool operator()(const pair<long long, long long> a, const pair<long long, long long> b) const { return a.first < b.first; } }; const long long nax = 2005; long long n, m; vector<pair<long long, long long>> robber, light, moves; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; robber.assign(n, {0, 0}); light.assign(m, {0, 0}); for (long long i = 0; i < n; i++) { cin >> robber[i].first >> robber[i].second; } for (long long i = 0; i < m; i++) { cin >> light[i].first >> light[i].second; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { long long a = light[j].first - robber[i].first + 1; long long b = light[j].second - robber[i].second + 1; a = max(a, 0LL); b = max(b, 0LL); moves.push_back({a, b}); } } long long sz = moves.size(); sort(moves.begin(), moves.end()); vector<long long> suf(sz); suf[sz - 1] = moves[sz - 1].second; for (long long i = sz - 2; i >= 0; i--) { suf[i] = max(suf[i + 1], moves[i].second); } long long ans = suf[0]; for (long long i = 0; i < sz; i++) { ans = min(ans, moves[i].first + (i + 1 < sz ? suf[i + 1] : 0)); } cout << ans << n ; }
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: denise_hamgenerator_ram_mf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module denise_hamgenerator_ram_mf (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [3:0] byteena_a;
input clock;
input [31:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.byteena_a (byteena_a),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_hamgenerator_ram_mf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_hamgenerator_ram_mf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_hamgenerator_ram_mf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_hamgenerator_ram_mf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_hamgenerator_ram_mf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL denise_hamgenerator_ram_mf_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } const long long N = 200005, INF = 2000000000000000000; void solve() { long long n, m; cin >> n >> m; long long i = 0, j = 0; char v[50][50]; long long a = 1000000, b = 10000, c = 0, d = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> v[i][j]; if (v[i][j] == * ) { a = min(i, a); b = min(j, b); c = max(i, c); d = max(j, d); } } } for (i = a; i < c + 1; i++) { for (j = b; j < d + 1; j++) { cout << v[i][j]; } cout << n ; } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_PP_V
|
#include <iostream> #include <vector> #include <string> #include <algorithm> #include <utility> #include <set> #include <queue> #include <deque> #include <stack> #include <map> #include <math.h> #include <iomanip> #include <fstream> #include <bitset> #include <sstream> using namespace std; //#define M_PI (ldb)3.14159265358979323846 // pi #define forr(i,a,b,c) for(int i=a;i<b;i+=c) #define forrb(i,a,b,c) for(int i=a;i>b;i-=c) #define fori(i,n) forr(i,0,n,1) #define forit(it,arr) for(auto it=arr.begin();it != arr.end();it++) #define forib(i,n) forrb(i,n-1,-1,1) #define forn(i,n) forr(i,1,n,1) #define fornb(i,n) forrb(i,n-1,0,1) #define fort(i,m,n) forr(i,m,n,1) #define fortb(i,m,n) forrb(i,n-1,m-1,1) #define forin(i,arr) fori(i,arr.size()) #define forinb(i,arr) forib(i,arr.size()) #define forrl(i,a,b,c) for(lol i=a;i<b;i+=c) #define forrbl(i,a,b,c) for(lol i=a;i>b;i-=c) #define foril(i,n) forrl(i,0,n,1) #define foribl(i,n) forrbl(i,n-1,-1,1) #define fornl(i,n) forrl(i,1,n,1) #define fornbl(i,n) forrbl(i,n-1,0,1) #define fortl(i,m,n) forrl(i,m,n,1) #define fortbl(i,m,n) forrbl(i,n-1,m-1,1) #define forinl(i,arr) foril(i,arr.size()) #define forinbl(i,arr) foribl(i,arr.size()) #define forpm(i) forr(i,-1,2,2) #define into(i) cin >> i; #define intov(arr,n) fori(kkkk,n){into(arr[kkkk])} #define def(i) lol i; into(i) #define deft(t,i) t i; into(i) #define defl(i) lol i; into(i) #define defs(i) string i; into(i) #define defn def(n) #define defp def(p) #define defm def(m) #define defk def(k) #define defa def(a) #define defb def(b) #define defc def(c) #define defd def(d) //#define vec(a) vector<a> #define co cout << #define out(a) cout << (a) << ; #define el << endl; #define ell << n ; #define outv(arr,n) fori(iii,n){out(arr[iii])} co el #define outvv(arr,n,m) fori(jjj,n){outv(arr[jjj],m)} #define cas(p) co Case # << p+1 << : ; #define ex return 0; #define qii queue<int> #define sti stack<int> #define dei deque<int> #define seti set<int> #define con continue; #define br break; #define maxi 1000000007 // 998244353 #define maxiu 4294967295 #define lmaxi 2000000000000000007 #define mod %maxi #define wne(arr) while(!arr.empty()) #define all(arr) arr.begin(),arr.end() #define getv(arr,n) fori(i,n) {into(arr[i])} #define defv(arr,n) veci arr(n); fori(i,n) {into(arr[i])} #define min2(a,b) a=min(a,b); #define max2(a,b) a=max(a,b); #define vec vector #define ff first #define ss second #define pow2(x) (x)*(x) #define pow3(x) (x)*(x)*(x) #define getgraph(m,cons) fori(i,m){defa defb a--; b--; cons[a].push_back(b);cons[b].push_back(a);} #define getdirectedgraph(m,cons) fori(i,m){defa defb a--; b--; cons[a].push_back(b);} #define getwightedgraph(m,cons) fori(i,m){defa defb defc a--; b--; cons[a].push_back({b,c});cons[b].push_back({a,c});} #define getwighteddirectedgraph(m,cons) fori(i,m){defa defb defc a--; b--; cons[a].push_back({b,c});} typedef vector<int> veci; typedef long long lol; typedef unsigned long long ulol; typedef unsigned int uint; typedef long double ldb; typedef vector<lol> vecl; typedef vector<uint> vecui; typedef vector<ulol> vecul; #define table(name,n,m) vector<veci> name(n,veci (m)); #define tablel(name,n,m) vector<vecl> name(n,vecl (m)); typedef pair<lol, lol> point; #define setp set<point> #define bmod %99999999999899999 typedef pair<point, point> poin; typedef pair<long double, long double> pointd; typedef pair<lol, point> poing; typedef pair<point, lol> poinf; typedef vector<point> vecp; #define poi(x,y) make_pair(x,y) struct BigNum { #define sizer (lol) 1e9 #define digss (lol) 9 vecl value; void set(lol x) { value = *(new vecl); value.push_back(x); } void duplicate(BigNum other) { value = other.value; } void add(BigNum other) { vecl o = other.value; if (o.size() > value.size()) { vecl t = value; value = o; o = t; } forin(i, o) { value[i] += o[i]; if (i < value.size() - 1 && value[i] >= sizer) { value[i + 1] += value[i] / sizer; value[i] = value[i] % sizer; } } if (value.back() >= sizer) { value.push_back(value.back() / sizer); value[value.size() - 2] = value[value.size() - 2] % sizer; } } void mul(lol mul) { forin(i, value) { value[i] *= mul; } fori(i, value.size() - 1) { if (value[i] >= sizer) { value[i + 1] += value[i] / sizer; value[i] = value[i] % sizer; } } if (value.back() >= sizer) { value.push_back(value.back() / sizer); value[value.size() - 2] = value[value.size() - 2] % sizer; } } long double div(BigNum other1, BigNum other2) { int s = value.size(); long double current = value.back(); if (s >= 2) { current += ((long double)value[s - 2]) / sizer; } if (s >= 3) { current += ((long double)value[s - 3]) / (sizer * sizer); } int s1 = other1.value.size(); int s2 = other2.value.size(); long double other = 0; if (s1 + s2 - 1 == s) { other += other1.value.back() * other2.value.back(); if (s1 >= 2) { other += ((long double)other1.value[s1 - 2] * other2.value.back()) / sizer; } if (s2 >= 2) { other += ((long double)other2.value[s2 - 2] * other1.value.back()) / sizer; } if (s1 >= 3) { other += ((long double)other1.value[s1 - 3] * other2.value.back()) / (sizer * sizer); } if (s2 >= 3) { other += ((long double)other2.value[s2 - 3] * other1.value.back()) / (sizer * sizer); } } if (s1 + s2 - 1 == s - 1) { other += other1.value.back() * other2.value.back(); if (s1 >= 2) { other += ((long double)other1.value[s1 - 2] * other2.value.back()) / sizer; } if (s2 >= 2) { other += ((long double)other2.value[s2 - 2] * other1.value.back()) / sizer; } other /= sizer; } if (s1 + s2 - 1 == s - 2) { other += other1.value.back() * other2.value.back(); other /= sizer * sizer; } return other / current; } string stringify() { string out = to_string(value.back()); forib(i, value.size() - 1) { string cur = to_string(value[i] + sizer); out += cur.substr(1); } return out; } }; lol gcd(lol a, lol b) { if (b == 0) { return a; } return gcd(b, a % b); } lol triangle(lol x) { return ((x - 1) * x) / 2; } lol antitriangle(lol x) { lol low = 0, high = 2 * maxi; while (low < high) { lol mid = (low + high + 1) / 2; if (triangle(mid) <= x) { low = mid; } else { high = mid - 1; } } return low; } lol modInverse(lol a) { lol m = maxi; lol y = 0, x = 1; while (a > 1) { lol q = a / m; lol t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) { x += maxi; } return x; } lol modInverse(lol a, lol b) { lol m = b; lol y = 0, x = 1; while (a > 1) { lol q = a / m; lol t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) { x += b; } return x; } lol poww(lol a, lol b) { if (b == 0) { return 1; } if (b % 2 == 0) { return poww((a * a)mod, b / 2)mod; } return (a * poww((a * a)mod, b / 2))mod; } lol pow(lol a, lol b, lol m) { if (b == 0) { return 1; } if (b % 2 == 0) { return pow((a * a) % m, b / 2, m) % m; } return (a * pow((a * a) % m, b / 2, m)) % m; } vecl dev(vecp divisors) { if (divisors.size() == 0) { vecl cur; cur.push_back(1); return cur; } lol x = divisors.back().first; lol n = divisors.back().second; divisors.pop_back(); vecl ans = dev(divisors); vecl cur; lol xi = 1; fori(i, n + 1) { forin(j, ans) { cur.push_back(ans[j] * xi); } xi *= x; } return cur; } bool isprime(lol a) { if (a == 1) { return false; } for (int i = 2; i * i <= a; i++) { if (a % i == 0) { return false; } } return true; } void add(veci & x, veci & y) { forin(i, x) { x[i] += y[i]; } } vecl mul(vecl x, lol a) { forin(i, x) { x[i] = (x[i] * a)mod; } return x; } vecl add(vecl x, vecl & y) { forin(i, x) { x[i] = (x[i] + y[i])mod; } return x; } #define logn 18 int lca(vector<veci> & f, veci & depth, int a, int b) { if (depth[a] < depth[b]) { swap(a, b); } fori(k, logn) { if ((depth[a] - depth[b]) & (1 << k)) { a = f[k][a]; } } if (a == b) { return a; } forib(k, logn) { if (f[k][a] != f[k][b]) { a = f[k][a]; b = f[k][b]; } } return f[0][a]; } int tredist(vector<veci>& f, veci& depth, int a, int b) { return depth[a]+ depth[b]- 2*depth[lca(f,depth,a,b)]; } struct pt { #define intopt(a) into(a.x) into(a.y) #define defpt(a) pt a;intopt(a) lol x, y; lol d() const // squared length { return x * x + y * y; } }; typedef vector<pt> vecpp; inline pt operator-(const pt & a) { return { -a.x, -a.y }; } inline pt operator+(const pt & a, const pt & b) { return { a.x + b.x, a.y + b.y }; } inline pt operator-(const pt & a, const pt & b) { return { a.x - b.x, a.y - b.y }; } inline lol operator*(const pt & a, const pt & b) { return a.x* b.y - a.y * b.x; } // cross product inline bool operator<(const pt& a, const pt& b) { if (a * b != 0) return a * b < 0; return a.d() < b.d(); } bool llll(const pt & a, const pt & b) { return a * b > 0; } inline bool operator<=(const pt & a, const pt & b) { return a * b <= 0; } inline lol operator/(const pt & a, const pt & b) { return a.x* b.x + a.y * b.y; } // dot product inline bool operator==(const pt & a, const pt & b) { return a.x == b.x && a.y == b.y; } // equal inline bool operator!=(const pt & a, const pt & b) { return a.x != b.x || a.y != b.y; } // not equal pt o = { 0 ,0 }; bool comp(pt a, pt b) { if ((a - o) * (b - o) != 0) return (a - o) * (b - o) < 0; return (a - o).d() < (b - o).d(); } bool decreasing(int a, int b) { return a > b; } #define digits 30 struct booleantree { booleantree* left = NULL; booleantree* right = NULL; void add(int val) { booleantree* cur = this; forib(i, digits) { if ((val & (1 << i))) { if (cur->right == NULL) { cur->right = new booleantree(); } cur = cur->right; } else { if (cur->left == NULL) { cur->left = new booleantree(); } cur = cur->left; } } } int find(int val) { booleantree* cur = this; int ans = 0; forib(i, digits) { if ((val & (1 << i))) { if (cur->left == NULL) { cur = cur->right; } else { cur = cur->left; ans += (1 << i); } } else { if (cur->right == NULL) { cur = cur->left; } else { cur = cur->right; ans += (1 << i); } } } return ans; } }; struct segtremin { vector<vecl> arr; int n; int curlogn; segtremin(int size, int logni) { n = size; curlogn = logni; arr.resize(curlogn); fori(i, curlogn) { arr[i].resize(size + 1); } } inline lol val(int start, int end) { if (end >= n) { end = n - 1; } if (start < 0) { start = 0; } lol mini = lmaxi; fori(i, curlogn) { if (start > end) { br } if ((end & 1) == 0) { min2(mini, arr[i][end]); end--; if (end < 0) { br } } if ((start & 1)) { min2(mini, arr[i][start]) start++; } start /= 2; end /= 2; } return mini; } inline void add(int start, lol num) { arr[0][start] = num; forn(i, curlogn) { arr[i][start >> i] = min(arr[i - 1][(start >> i) * 2], arr[i - 1][(start >> i) * 2 + 1]); } } }; struct segtreminplus { vecl arr; vector<vecl> arr2; vector<vecl> arr3; vector<vecl> arr4; int n; int curlogn; segtreminplus(int size, int logni) { n = size; curlogn = logni; arr.resize(size + 1); arr2.resize(curlogn); fori(i, curlogn) { arr2[i].resize(size + 1); } arr3.resize(curlogn); fori(i, curlogn) { arr3[i].resize(size + 1); } arr4.resize(curlogn); fori(i, curlogn) { arr4[i].resize(size + 1); } } inline void fixcate(int i, int j) { if (j < 0) { return; } if (i == 0) { arr2[i][j] = 1; arr3[i][j] = 1; arr4[i][j] = 1; return; } arr2[i][j] = max(arr2[i-1][2*j], arr2[i - 1][2 * j+1]); arr3[i][j] = arr3[i - 1][2 * j]; arr4[i][j] = arr4[i - 1][2 * j+1]; if (((2 * j + 1) << (i - 1)) < n && arr[((2 * j + 1) << (i - 1))] > arr[((2 * j + 1) << (i - 1)) - 1]) { arr2[i][j] = max(arr2[i][j], arr4[i - 1][2 * j]+ arr3[i - 1][2 * j+1]); if (arr2[i - 1][2 * j+1] == (1 << (i - 1))) { arr4[i][j] = arr4[i - 1][2 * j + 1] + arr4[i - 1][2 * j]; } if (arr2[i - 1][2 * j] == (1 << (i - 1))) { arr3[i][j] = arr3[i - 1][2 * j + 1] + arr3[i - 1][2 * j]; } } } inline lol val(int start) { if (start > 0) { return arr[start]; } return arr2[curlogn-1][0]; } inline void change(int start, lol num) { arr[start] = num; fori(i, curlogn) { fixcate(i, start >> i); } } }; struct segtresum { vector<vecl> arr; int n; int curlogn; segtresum(int size, int logni) { n = size; curlogn = logni; arr.resize(curlogn); fori(i, curlogn) { arr[i].resize(size + 1); } } inline lol val(int start, int end) { /*if (end >= n) { end = n - 1; } if (start < 0) { start = 0; }*/ lol mini = 0; fori(i, curlogn) { if (start > end) { br } if ((end & 1) == 0) { mini += arr[i][end]; end--; if (end < 0) { br } } if ((start & 1)) { mini += arr[i][start]; start++; } start /= 2; end /= 2; } return mini; } inline void add(int start, lol num) { arr[0][start] = num; forn(i, curlogn) { arr[i][start >> i] = arr[i - 1][(start >> i) * 2] + arr[i - 1][(start >> i) * 2 + 1]; } } inline void radd(int start, lol num) { arr[0][start] += num; forn(i, curlogn) { arr[i][start >> i] = arr[i - 1][(start >> i) * 2] + arr[i - 1][(start >> i) * 2 + 1]; } } }; struct segtresumplus { vector<vecl> arr; vector<vecl> arrplus; vector<vecl> truearrplus; int n; int curlogn; segtresumplus(int size, int logni) { n = size; curlogn = logni; arr.resize(curlogn); fori(i, curlogn) { arr[i].resize(size + 1); } arrplus.resize(curlogn); fori(i, curlogn) { arrplus[i].resize(size + 1); } truearrplus.resize(curlogn); fori(i, curlogn) { truearrplus[i].resize(size + 1); } } inline void fix(int h, int s) { /*if (arrplus[h][s] == 0) { return; } arr[h][s] += arrplus[h][s] << h; if (h > 0) { arrplus[h - 1][2 * s] += arrplus[h][s]; arrplus[h - 1][2 * s+ 1] += arrplus[h][s]; } arrplus[h][s] = 0;*/ } inline lol val(int start, int end) { /*if (end >= n) { end = n - 1; } if (start < 0) { start = 0; }*/ forib(i, curlogn) { fix(i, start >> i); fix(i, end >> i); } lol mini = 0; fori(i, curlogn) { if (start > end) { br } if ((end & 1) == 0) { fix(i, end); mini += arr[i][end]; mini += arrplus[i][end]; fort(j, i + 1, curlogn) { mini += truearrplus[j][end >> (j-i)]<< i; } end--; if (end < 0) { br } } if ((start & 1)) { fix(i, start); mini += arr[i][start]; mini += arrplus[i][start]; fort(j, i + 1, curlogn) { mini += truearrplus[j][start >> (j - i)] << i; } start++; } start /= 2; end /= 2; } return mini; } inline void add(int start, lol num) { arr[0][start] = num; forn(i, curlogn) { arr[i][start >> i] = arr[i - 1][(start >> i) * 2] + arr[i - 1][(start >> i) * 2 + 1]; } } inline void radd(int start,int end, lol num) { fori(i, curlogn) { if (start > end) { br } if ((end & 1) == 0) { truearrplus[i][end]+=num; fort(j,i, curlogn) { arrplus[j][end >> (j-i)] += num << i; } end--; if (end < 0) { br } } if ((start & 1)) { truearrplus[i][start] += num; fort(j, i, curlogn) { arrplus[j][start >> (j - i)] += num << i; } start++; } start /= 2; end /= 2; } } }; struct unionfind{ veci arr; veci arr2; int num; unionfind(int size) { arr.resize(size); arr2.resize(size); num = size; fori(i, size) { arr[i] = i; arr2[i] = 1; } } int find(int a) { if (arr[a] == a) { return a; } return arr[a] = find(arr[a]); } inline void unioner(int a, int b) { a = find(a), b = find(b); if (a != b) { num--; if (arr2[a] > arr2[b]) { swap(a, b); } arr[a] = b; arr2[b] += arr2[a]; } } }; string op(string s) { string ans; forinb(i, s) { ans.push_back(s[i]); } return ans; } void merge(veci& color, vector<veci>& allcolor, int l, int r) { if (color[l] == color[r]) { return; } l = color[l]; r = color[r]; if (allcolor[l].size() < allcolor[r].size()) { swap(l, r); } forin(j, allcolor[r]) { color[allcolor[r][j]] = l; allcolor[l].push_back(allcolor[r][j]); } allcolor[r].resize(0); } vecpp conv(vecpp a) { pt left = { 99999999999999,999999999999999 }; forin(i, a) { if (a[i].x < left.x || a[i].x == left.x && a[i].y > left.y) { left = a[i]; } } o = left; forin(i, a) { if (a[i] == left) { a[i] = a.back(); a.pop_back(); br } } sort(all(a), comp); vecpp conv(1, left); forin(i, a) { while (conv.size() > 1) { if ((a[i] - conv.back()) * (conv.back() - conv[conv.size() - 2]) <= 0) { conv.pop_back(); } else { br } } conv.push_back(a[i]); } while (conv.size() > 1) { if ((left - conv.back()) * (conv.back() - conv[conv.size() - 2]) <= 0) { conv.pop_back(); } else { br } } return conv; } int main() { ios::sync_with_stdio(0); cin.tie(0); defn defm veci a(n); intov(a,n) vector<veci> primer(100000); vector<veci> nekt(logn, veci(n+1, n)); fori(i, n) { fort(j,2, 400) { if (a[i] % j == 0) { primer[j].push_back(i); while (a[i] % j == 0) { a[i] /= j; } } } if (a[i] > 1) { primer[a[i]].push_back(i); } } forin(i, primer) { fori(j, ((int)primer[i].size())-1) { min2(nekt[0][primer[i][j]], primer[i][j + 1]); } } forib(i, n-1) { min2(nekt[0][i], nekt[0][i+1]); forn(j, logn) { nekt[j][i] = nekt[j - 1][nekt[j - 1][i]]; } } fori(i, m) { defa defb int ans = 1; a--; int k = logn - 1; while (k >= 0) { if (nekt[k][a] < b) { a = nekt[k][a]; ans += 1 << k; } else { k--; } } co ans el } ex }
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#include <bits/stdc++.h> using namespace std; const long long N = 100100, mod = 1e9 + 7, mod2 = 1e9 + 9, mod3 = 998244353, sq = 450, base = 727, lg = 30; long long n, m, x, y, z, w, ans, t, l[N], r[N]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> l[i] >> r[i]; if (i == 0) { x = l[i]; y = r[i]; continue; } x = min(x, l[i]); y = max(y, r[i]); } for (int i = 0; i < n; i++) { if (l[i] == x && r[i] == y) return cout << i + 1, 0; } cout << -1; return 0; }
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#include <bits/stdc++.h> int main() { int a, b; scanf( %d %d , &a, &b); int diff, same, total; total = a + b; if (a > b) { diff = b; } else { diff = a; } same = (total - (2 * diff)) / 2; printf( %d %d n , diff, same); return 0; }
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/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC7 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* this value should be placed in the top bits of the last byte
* CCCCCCC1
* C = CRC bit
*
* Hold in reset when not using
*
* Changes:
* 2015.08.08: Initial Add
*/
module crc7 #(
parameter POLYNOMIAL = 8'h09,
parameter SEED = 8'h00
)(
input clk,
input rst,
input bit,
output reg [6:0] crc,
input en
);
//local parameters
//registes/wires
wire inv;
//submodules
//asynchronous logic
assign inv = bit ^ crc[6]; // XOR required?
//synchronous logic
//XXX: Does this need to be asynchronous?
always @ (posedge clk) begin
if (rst) begin
crc <= SEED;
end
else begin
//Shift the output value
if (en) begin
crc[6] <= crc[5];
crc[5] <= crc[4];
crc[4] <= crc[3];
crc[3] <= crc[2] ^ inv;
crc[2] <= crc[1];
crc[1] <= crc[0];
crc[0] <= inv;
end
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &t) { t = 0; char ch = getchar(); int f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } do { (t *= 10) += ch - 0 ; ch = getchar(); } while ( 0 <= ch && ch <= 9 ); t *= f; } template <typename T> void write(T t) { if (t < 0) { putchar( - ); write(-t); return; } if (t > 9) write(t / 10); putchar( 0 + t % 10); } template <typename T> void writeln(T t) { write(t); puts( ); } const int maxn = 610; const int maxm = 300010; int n, a[maxm]; namespace xyr { const int maxm = 1000000; int n, tot, head[maxn], id[610][610]; int nxt[maxm], to[maxm], ans; void Add(int x, int y) { tot++; nxt[tot] = head[x]; head[x] = tot; to[tot] = y; } void add(int x, int y, int z) { if (id[x][y]) return; id[x][y] = id[y][x] = z; Add(x, y); Add(y, x); } int match[maxn], pre[maxn], vis[maxn], fa[maxn]; queue<int> q; int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } int mk[maxn], cnt; int lca(int x, int y) { cnt++; while (1) { if (x) { x = find(x); if (mk[x] == cnt) return x; mk[x] = cnt; x = pre[match[x]]; } swap(x, y); } } void blossom(int x, int y, int z) { while (find(x) != z) { pre[x] = y; y = match[x]; if (vis[y] == 2) vis[y] = 1, q.push(y); if (find(x) == x) fa[x] = z; if (find(y) == y) fa[y] = z; x = pre[y]; } } int dfs(int s) { for (int i = 1; i <= n; i++) vis[i] = pre[i] = 0, fa[i] = i; q = queue<int>(); q.push(s); vis[s] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int i = head[u], v; i; i = nxt[i]) { v = to[i]; if (find(u) == find(v) || vis[v] == 2) continue; if (!vis[v]) { vis[v] = 2; pre[v] = u; if (!match[v]) { for (int x = v, lst; x; x = lst) lst = match[pre[x]], match[x] = pre[x], match[pre[x]] = x; return 1; } vis[match[v]] = 1; q.push(match[v]); } else { int z = lca(u, v); blossom(u, v, z); blossom(v, u, z); } } } return 0; } void solve() { for (int i = n; i >= 1; i--) if (!match[i]) ans += dfs(i); } }; // namespace xyr bool ban[610]; int mx, used[maxm]; vector<pair<int, int>> V, V2; namespace BF { vector<int> g[610]; int tim[610]; queue<int> q; void link(int x, int y) { g[x].push_back(y), g[y].push_back(x); } void solve() { for (int i = 1; i <= mx; i++) tim[i] = -1; for (int i = 1; i <= mx; i++) if (ban[i]) tim[i] = 0, q.push(i); while (!q.empty()) { int x = q.front(); q.pop(); for (int &y : g[x]) if (tim[y] == -1) tim[y] = tim[x] + 1, q.push(y); } } }; // namespace BF int dir[maxm], bel[maxn]; bool MK[maxm]; namespace Forest { bool oncyc[610], vis[610]; int fa[610], from[610]; vector<pair<int, int>> g[610]; void add(int x, int y, int z) { g[x].push_back(make_pair(y, z)), g[y].push_back(make_pair(x, z)); } int X, Y, Z; vector<int> V[610]; int D[610], tot, S, dis[610]; void dfs(int x, int p, int w) { vis[x] = 1; fa[x] = p; from[x] = w; V[S].push_back(x); dis[x] = dis[p] + 1; for (auto [y, z] : g[x]) { if (z == from[x]) continue; if (vis[y]) { if (dis[x] > dis[y]) Y = x, X = y, Z = z; } else dfs(y, x, z); } } int VIS[610]; void DFS(int x, int f) { VIS[x] = 1; for (auto [y, z] : g[x]) if (!oncyc[y] && z != f && !VIS[y]) { DFS(y, z); dir[z] = y; } } int TREE[610]; void solve() { for (int i = 1; i <= mx; i++) if (!vis[i]) { X = Y = 0; S = i; dfs(i, 0, -1); if (X) { tot = 0; dir[Z] = X; while (1) { D[++tot] = Y; if (Y == X) break; dir[from[Y]] = Y; Y = fa[Y]; } for (int j = 1; j <= tot; j++) oncyc[D[j]] = 1; for (int j = 1; j <= tot; j++) DFS(D[j], 0); } else { TREE[i] = 1; for (int &x : V[i]) { bel[x] = i; } } } tot = 0; } int XYR[610]; void insert(int x) { XYR[bel[x]] = x; } void insert(int x, int y) { insert(x), insert(y); } void solve_again() { memset(vis, 0, sizeof(vis)); for (int i = 1; i <= mx; i++) if (bel[i] == i && TREE[i]) { if (XYR[i]) { S = i; V[i].clear(); dfs(XYR[i], 0, -1); } else XYR[i] = i; for (int &x : V[i]) if (x != XYR[i]) dir[from[x]] = x; } } }; // namespace Forest int now, R[maxm]; int GETNXT() { while (used[now]) now++; used[now] = 1; return now; } int main() { read(n); int F1 = 1, F2 = 1; for (int i = 1; i <= n; i++) read(a[i]), R[i] = a[i], mx = max(mx, a[i]), used[a[i]] = 1, F1 &= (a[i] == 0), F2 &= (a[i] != 0); if (F1) { for (int i = 0; i < n; i++) printf( %d , i / 2 + 1); puts( ); return 0; } if (F2) { for (int i = 1; i <= n; i++) printf( %d , a[i]); puts( ); return 0; } now = 1; for (int l = 1, r; l <= n; l = r + 1) if (!a[l]) { r = l; while (r < n && !a[r + 1]) r++; int x = a[l - 1], y = a[r + 1], len = r - l + 1; if (l == 1) { if (len & 1) { for (int i = 1; i < r; i += 2) a[i] = a[i + 1] = GETNXT(); a[r] = a[r + 1]; } else { for (int i = 1; i <= r; i += 2) a[i] = a[i + 1] = GETNXT(); } } else if (r == n) { if (len & 1) { for (int i = l + 1; i <= n; i += 2) a[i] = a[i + 1] = GETNXT(); a[l] = a[l - 1]; } else { for (int i = l; i <= n; i += 2) a[i] = a[i + 1] = GETNXT(); } } else { assert(x && y); if (x == y) { if (len & 1) { a[l] = a[l - 1]; for (int i = l + 1; i <= r; i += 2) a[i] = a[i + 1] = GETNXT(); } else { for (int i = l; i <= r; i += 2) a[i] = a[i + 1] = GETNXT(); } } else { V.push_back(make_pair(l, r)); } } } else r = l; for (int i = 1; i < n; i++) if (a[i] && a[i + 1] && a[i] == a[i + 1] && a[i] <= mx) ban[a[i]] = 1; for (pair<int, int> &A : V) if ((A.second - A.first + 1) % 2 == 1) BF::link(a[A.first - 1], a[A.second + 1]); BF::solve(); for (int i = 1; i <= mx; i++) ban[i] = (BF::tim[i] != -1); for (auto [l, r] : V) { int x = a[l - 1], y = a[r + 1], len = r - l + 1; if (ban[y] && (!ban[x] || BF::tim[y] <= BF::tim[x])) { if (len & 1) { for (int i = l + 1; i <= r; i += 2) a[i] = a[i + 1] = GETNXT(); a[l] = a[l - 1]; } else { for (int i = l; i <= r; i += 2) a[i] = a[i + 1] = GETNXT(); } } else if (ban[x] && (!ban[y] || BF::tim[y] >= BF::tim[x])) { if (len & 1) { for (int i = l; i < r; i += 2) a[i] = a[i + 1] = GETNXT(); a[r] = a[r + 1]; } else { for (int i = l; i <= r; i += 2) a[i] = a[i + 1] = GETNXT(); } } else V2.push_back(make_pair(l, r)); } for (int i = 0; i < V2.size(); i++) { int l = V2[i].first, r = V2[i].second, x = a[l - 1], y = a[r + 1], len = r - l + 1; if (len & 1) Forest::add(x, y, i); } Forest::solve(); xyr::n = mx; for (int i = 0; i < V2.size(); i++) { int l = V2[i].first, r = V2[i].second, x = a[l - 1], y = a[r + 1], len = r - l + 1; if (len & 1 ^ 1) xyr::add(bel[x], bel[y], i + 1); } xyr::solve(); for (int i = 1; i <= mx; i++) if (xyr::match[i] && xyr::match[i] < i) { int z = xyr::id[i][xyr::match[i]] - 1; MK[z] = 1; int x = a[V2[z].first - 1], y = a[V2[z].second + 1]; Forest::insert(x, y); } Forest::solve_again(); for (int i = 0; i < V2.size(); i++) { int l = V2[i].first, r = V2[i].second, x = a[l - 1], y = a[r + 1], len = r - l + 1; if (MK[i]) { a[l] = a[l - 1], a[r] = a[r + 1]; for (int j = l + 1; j < r; j += 2) a[j] = a[j + 1] = GETNXT(); } else if (dir[i]) { if (dir[i] == x) { for (int j = l + 1; j <= r; j += 2) a[j] = a[j + 1] = GETNXT(); a[l] = a[l - 1]; } else { for (int j = l; j < r; j += 2) a[j] = a[j + 1] = GETNXT(); a[r] = a[r + 1]; } } else if (len & 1) { for (int j = l; j < r; j += 2) a[j] = a[j + 1] = GETNXT(); a[r] = GETNXT(); } else { for (int j = l; j <= r; j += 2) a[j] = a[j + 1] = GETNXT(); } } for (int i = 1; i <= n; i++) printf( %d , a[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFLL = 1e18; const int MOD = 1e9 + 7; const int MAXN = 2e5 + 5; vector<int> G[MAXN]; int n; long long s[MAXN]; long long a[MAXN]; void dfs(int v, int p) { if (s[v] == -1) { long long aux = INF; for (auto u : G[v]) if (u != p) { aux = min(aux, s[u]); } if (aux == -1 || aux - s[p] < 0) { a[v] = -1; return; } if (aux == INF) { a[v] = 0; return; } a[v] = aux - s[p]; s[v] = a[v] + s[p]; } else { if (p == v) a[v] = s[v]; else a[v] = s[v] - s[p]; } for (auto u : G[v]) if (u != p) dfs(u, v); } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x; scanf( %d , &x); x--; G[x].push_back(i); G[i].push_back(x); } for (int i = 0; i < n; i++) scanf( %lld , &s[i]); dfs(0, 0); long long ans = 0; for (int i = 0; i < n; i++) { if (a[i] < 0) { printf( -1 n ); return 0; } ans += a[i]; } printf( %lld n , ans); return 0; }
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
//LCD Code taken from John Loomis
//Speakers code taken from Altera
module control (
input CLOCK_50,
input CLOCK_27,
input [3:0] KEY,
input [3:0] SW,
output [17:0] LEDR,
output [7:6] LEDG,
output [2:0] GPIO_1,
output [6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,
// LCD Module 16X2
output LCD_ON,
output LCD_BLON,
output LCD_RW,
output LCD_EN,
output LCD_RS,
inout [7:0] LCD_DATA,
// Speakers
input AUD_ADCDAT,
// Bidirectionals
inout AUD_BCLK,
inout AUD_ADCLRCK,
inout AUD_DACLRCK,
inout I2C_SDAT,
// Outputs
output AUD_XCK,
output AUD_DACDAT,
output I2C_SCLK
);
// 1hz Clock
wire Clk_1hz;
clk_convert c0 (CLOCK_50, 1, 1, Clk_1hz);
// reset delay gives some time for peripherals to initialize
wire DLY_RST;
Reset_Delay r0(.iCLK(CLOCK_50),.oRESET(DLY_RST));
// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
// assignments to incorporate lcd display
LCD_Display u1(
// Host Side
.iCLK_50MHZ(CLOCK_50),
.iRST_N(DLY_RST),
.state_code(STATE),
// LCD Side
.DATA_BUS(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_E(LCD_EN),
.LCD_RS(LCD_RS)
);
// assignments to incorporate the speakers
DE2_Audio_Example ex1 (
CLOCK_50,
CLOCK_27,
AUD_ADCDAT,
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
I2C_SDAT,
AUD_XCK,
AUD_DACDAT,
I2C_SCLK,
ME
);
//Feed Beep FSM
reg [4:0] STATE;
wire O;
assign O = KEY[0];
parameter [4:0] A = 5'b00000, B = 5'b00001,
C = 5'b00010, D = 5'b00100,
E = 5'b01000, F = 5'b10000;
assign LEDR[16]=STATE[0];//enableB
assign LEDR[15]=STATE[1];//enC
assign LEDR[14]=STATE[2];//enD
assign LEDR[13]=STATE[3];//enE
assign LEDR[12]=STATE[4];//enF
//The FSM controls bellow circuit using the ones of the One-Hot-Encoding
always @(posedge O)
case(STATE)
A:
if(O) STATE=B;
else STATE=A;
B:
if(O) STATE=C;
else STATE=B;
C:
if(O) STATE=D;
else STATE=C;
D:
if(O) STATE=E;
else STATE=D;
E:
if(O) STATE=F;
else STATE=E;
F:
if(O) STATE=A;
else STATE=F;
default: STATE=5'bxxxxx;
endcase
// Operations with state dependance
wire
RExe = KEY[3], Add = KEY[1], RClk = KEY[2], SDispl = SW[0];
// Need different times.
wire [3:0] hour2, hour1, minute2, minute1, second2, second1;//initial time
wire [3:0] chour2, chour1, cminute2, cminute1, csecond2, csecond1;//current time
wire [3:0] mhour2, mhour1, mminute2, mminute1, msecond2, msecond1;//meal time
reg [3:0] dhour2, dhour1, dminute2, dminute1, dsecond2, dsecond1;//display time
// Circuits and variables for Setting Up (initial and meal) Time and Running (current time)))
//SW[5]&~SW[4] to set hours, opposite for setting minutes
set_time s0 (Add, SW[2]&(STATE[0]|STATE[2]), SW[1]&(STATE[0]|STATE[2]), hour2, hour1, minute2, minute1, second2, second1);
set_time s1 (Add, SW[2]&(STATE[0]|STATE[2]), SW[1]&(STATE[0]|STATE[2]), mhour2, mhour1, mminute2, mminute1, msecond2, msecond1);
run_clock rclk0 (RClk, Clk_1hz, hour2, hour1, minute2, minute1, second2, second1, chour2, chour1, cminute2, cminute1, csecond2, csecond1);
// Circuits and variables for Control of motor
// Motor Enable, Motor Terminal 1 & 2
wire ME, MT1, MT2;
assign LEDR[0] = ME; assign LEDG[7] = MT1; assign LEDG[6] = MT2;
assign GPIO_1[2] = ME; assign GPIO_1[1] = MT1; assign GPIO_1[0] = MT2;
reg [31:0] delay;
always @(SW[3])
if(~SW[3]) delay = 32'd100000000;
else delay = 32'd250000000;
executer e0 (CLOCK_50, KEY[3], delay, ,
mhour2, mhour1, mminute2, mminute1, msecond2, msecond1,
chour2, chour1, cminute2, cminute1, csecond2, csecond1,
ME, MT1, MT2);
//Circuits for displaying time
always @ (SDispl)
if (~SDispl)
begin
dhour2 = hour2; dhour1 = hour1; dminute2 = minute2; dminute1 = minute1; dsecond2 = second2; dsecond1 = second1;
end
else
begin
dhour2 = chour2; dhour1 = chour1; dminute2 = cminute2; dminute1 = cminute1; dsecond2 = csecond2; dsecond1 = csecond1;
end
display_time d0 (dhour2, dhour1, dminute2, dminute1, dsecond2, dsecond1, HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dec_table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dec_table (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "dec_table.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "dec_table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "dec_table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long q; cin >> q; while (q--) { long long n, count = 0; cin >> n; long long a[100005]; for (int i = 0; i < n; i++) cin >> a[i]; if (n == 1) cout << 1 << endl; else { for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if ((a[i] - a[j]) == 1 || (a[i] - a[j] == -1)) count++; } } if (count > 0) cout << 2 << endl; else cout << 1 << endl; } } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:36:03 02/26/2016
// Design Name: Register
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab4/test_Register.v
// Project Name: lab4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_Register;
// Inputs
reg clock_in;
reg regWrite;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg [31:0] writeData;
// Outputs
wire [31:0] readData1;
wire [31:0] readData2;
parameter PERIOD = 200;
// Instantiate the Unit Under Test (UUT)
Register uut (
.clock_in(clock_in),
.regWrite(regWrite),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.readData1(readData1),
.readData2(readData2)
);
always #(PERIOD/2) clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
regWrite = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
#285;
regWrite = 'b1;
writeReg = 5'b10101;
writeData = 32'b11111111111111110000000000000000;
#200;
writeReg = 5'b01010;
writeData = 32'b00000000000000001111111111111111;
#200;
regWrite = 'b0;
writeReg = 'b00000;
writeData = 32'b00000000000000000000000000000000;
#50;
readReg1 = 'b10101;
readReg2 = 'b01010;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n; x = 1; y = n * n; while (x < y) { cout << x << << y << endl; x++; y--; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; const int inf = INT_MAX; const long long inff = 1e18; const long long mod = 1e9 + 7; vector<int> dx = {0, 1, 1, 1, 0, -1, -1, -1}; vector<int> dy = {1, 1, 0, -1, -1, -1, 0, 1}; int can[507][507]; set<pair<int, int> > second[32][9]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); int n; int a[35]; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int j = 250; j <= 250 + a[1] - 1; j++) can[250][j] = 1; second[1][0].insert(make_pair(250, 250 + a[1] - 1)); for (int i = 1; i < n; i++) { for (int j = 0; j < 8; j++) { for (pair<int, int> k : second[i][j]) { for (int l = 1; l <= a[i + 1]; l++) { can[k.first + dx[(j + 1) % 8] * l][k.second + dy[(j + 1) % 8] * l] = 1; can[k.first + dx[(j + 7) % 8] * l][k.second + dy[(j + 7) % 8] * l] = 1; } second[i + 1][(j + 1) % 8].insert( make_pair(k.first + dx[(j + 1) % 8] * a[i + 1], k.second + dy[(j + 1) % 8] * a[i + 1])); second[i + 1][(j + 7) % 8].insert( make_pair(k.first + dx[(j + 7) % 8] * a[i + 1], k.second + dy[(j + 7) % 8] * a[i + 1])); } } } int ans = 0; for (int i = 0; i <= 500; i++) for (int j = 0; j <= 500; j++) ans += can[i][j]; cout << ans << n ; }
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#include <bits/stdc++.h> using namespace std; int const maxn = 1e6 + 5; int a[maxn], b[maxn]; pair<int, int> c[maxn]; int all_elem[2 * maxn]; int cur, inf = 1e9 + 7; int f[2 * maxn]; int psh[8 * maxn]; pair<int, int> imin[4 * maxn]; inline pair<int, int> unions(pair<int, int> c, pair<int, int> d) { if (c.first < d.first || (c.first == d.first && c.second > d.second)) return c; return d; } void build(int i, int l, int r) { psh[i] = 0; if (r - l == 1) imin[i] = {0, l}; else { int m = (r + l) / 2; build(2 * i + 1, l, m); build(2 * i + 2, m, r); imin[i] = unions(imin[2 * i + 1], imin[2 * i + 2]); } } inline void push(int i) { imin[i].first += psh[i]; psh[2 * i + 1] += psh[i]; psh[2 * i + 2] += psh[i]; psh[i] = 0; } void adds(int i, int l, int r, int lq, int rq, int x) { push(i); if (lq >= r || l >= rq) return; if (lq <= l && r <= rq) { psh[i] += x; push(i); return; } int m = (r + l) / 2; adds(2 * i + 1, l, m, lq, rq, x); adds(2 * i + 2, m, r, lq, rq, x); imin[i] = unions(imin[2 * i + 1], imin[2 * i + 2]); } pair<int, int> get(int i, int l, int r, int lq, int rq) { push(i); if (lq >= r || l >= rq) return {inf, inf}; if (lq <= l && r <= rq) return imin[i]; int m = (r + l) / 2; return unions(get(2 * i + 1, l, m, lq, rq), get(2 * i + 2, m, r, lq, rq)); } inline void add(int i) { while (i <= cur) { f[i]++; i = (i | (i + 1)); } } inline int get(int i) { int ans = 0; while (i > 0) { ans += f[i]; i = (i & (i + 1)) - 1; } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cur = 0; cin >> n >> m; build(0, 0, n + 1); for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= m; ++i) cin >> b[i]; sort(b + 1, b + m + 1); for (int i = 1; i <= n; ++i) { all_elem[++cur] = a[i]; } for (int i = 1; i <= m; ++i) { all_elem[++cur] = b[i]; } sort(all_elem + 1, all_elem + cur + 1); for (int i = 1; i <= n; ++i) { a[i] = lower_bound(all_elem + 1, all_elem + cur + 1, a[i]) - all_elem; } for (int i = 1; i <= m; ++i) { b[i] = lower_bound(all_elem + 1, all_elem + cur + 1, b[i]) - all_elem; } long long ans = 0; for (int i = 0; i <= cur; ++i) f[i] = 0; for (int i = n; i >= 1; --i) { ans += get(a[i]); add(a[i] + 1); } for (int i = 1; i <= n; ++i) c[i] = {a[i], i}; sort(c + 1, c + n + 1); int pos = n; for (int i = 1; i <= n; ++i) { adds(0, 0, n + 1, 0, i, 1); } int lptr = n, rptr = n; for (int i = m; i >= 1; --i) { if (b[i] != b[i + 1]) { while (rptr > lptr) { adds(0, 0, n + 1, c[rptr].second, n + 1, 1); rptr--; } } while (rptr > 0 && b[i] < c[rptr].first) { adds(0, 0, n + 1, 0, c[rptr].second, -1); adds(0, 0, n + 1, c[rptr].second, n + 1, 1); rptr--; } lptr = min(lptr, rptr); while (lptr > 0 && b[i] == c[lptr].first) { adds(0, 0, n + 1, 0, c[lptr].second, -1); lptr--; } pair<int, int> best = get(0, 0, n + 1, 0, pos + 1); ans += best.first; pos = best.second; } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t{}; cin >> t; while (t--) { long long int n{}; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; bool visit[n]; memset(visit, 0, sizeof(visit)); vector<pair<long long int, long long int>> vec{}; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < n; j++) { if (i != j && a[i] != a[j] && (!visit[i] || !visit[j])) { visit[i] = 1; visit[j] = 1; vec.push_back({i + 1, j + 1}); } } } if (vec.size() == n - 1) { cout << YES << n ; for (long long int i = 0; i < n - 1; i++) { cout << vec[i].first << << vec[i].second << n ; } } else { cout << NO << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; long long ans; int a, b, c, d, e, f, g; int main() { scanf( %d%d%d%d%d%d , &a, &b, &c, &d, &e, &f); if (e > f) ans += min(a, d); a -= ans, d -= ans; ans *= e; g = min(min(b, c), d); ans += f * g; b -= g, c -= g, d -= g; ans += e * min(a, d); printf( %lld , ans); }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 5010; int v[MAXN], n, k; int vec[1000100][12]; bool vis[1000100]; void crivo() { for (int i = 1; i <= 1000001; i++) { set<int> s; for (int j = 0; j <= 1000000; j += i) { for (int t = 1; t <= 11; t++) { int at = vec[j][t]; if (at == -1) break; s.insert(at); if (s.size() > 2 * k) { vis[i] = true; break; } } if (vis[i] == true) break; } if (vis[i] == true) continue; int q = 0; unordered_map<int, int> mp; for (auto j : s) mp[v[j] % i]++; for (auto j : mp) q += j.second - 1; if (q > k) vis[i] = true; if (vis[i] == false) { printf( %d n , i); return; } } } vector<int> vet[1000100]; int cnt[1000100]; int main() { memset(cnt, 0, sizeof cnt); memset(vec, -1, sizeof vec); scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j) continue; int h = abs(v[i] - v[j]); if (cnt[h] > 10) continue; vec[h][cnt[h] + 1] = i, cnt[h]++; } } crivo(); }
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#include <bits/stdc++.h> using namespace std; int T, n, cnt; struct poi { double x, y, alp; poi() {} poi(double x, double y) : x(x), y(y) { alp = atan2(y, x); } friend bool operator<(const poi &r1, const poi &r2) { return r1.alp < r2.alp; } friend poi operator+(const poi &r1, const poi &r2) { return poi(r1.x + r2.x, r1.y + r2.y); } friend poi operator-(const poi &r1, const poi &r2) { return poi(r1.x - r2.x, r1.y - r2.y); } friend double operator^(const poi &r1, const poi &r2) { return r1.x * r2.y - r2.x * r1.y; } friend double operator*(const poi &r1, const poi &r2) { return r1.x * r2.x + r1.y * r2.y; } friend poi operator*(double v, const poi &r1) { return poi(r1.x * v, r1.y * v); } } a[210000 << 1], p, w[210000 << 2]; struct line { poi p, v; line() {} line(poi p, poi v) : p(p), v(v) {} } b[210000 << 2], q[210000 << 2]; void init() { cnt = 0; double t = 1e6; poi p1(t, t), p2(-t, t), p3(-t, -t), p4(t, -t); b[++cnt] = line(p1, p2 - p1); b[++cnt] = line(p2, p3 - p2); b[++cnt] = line(p3, p4 - p3); b[++cnt] = line(p4, p1 - p4); } int insert(poi p1, poi p2) { double t = (p2 - p1) ^ (p - p1); if (fabs(t) < 1e-12) return 0; if (t > 0) b[++cnt] = line(p1, p2 - p1); else b[++cnt] = line(p2, p1 - p2); return 1; } int onleft(poi p1, line l1) { return (l1.v ^ (p1 - l1.p)) > 0; } int cmp(const line &l1, const line &l2) { if (fabs(l1.v.alp - l2.v.alp) < 1e-12) return onleft(l1.p, l2); return l1.v.alp < l2.v.alp; } poi intersect(line l1, line l2) { poi u = l1.p - l2.p; double tmp = (u ^ l2.v) / (l2.v ^ l1.v); return l1.p + tmp * l1.v; } double HPI() { int h, r; sort(b + 1, b + 1 + cnt, cmp); q[h = r = 1] = b[1]; for (int i = 2; i <= cnt; i++) { if (fabs(b[i].v.alp - b[i - 1].v.alp) < 1e-12) continue; while (h < r && !onleft(w[r], b[i])) r--; while (h < r && !onleft(w[h + 1], b[i])) h++; q[++r] = b[i]; w[r] = intersect(q[r], q[r - 1]); } while (h < r && !onleft(w[r], q[h])) r--; w[h] = intersect(q[h], q[r]); if (h + 1 >= r) return 0; w[r + 1] = w[h]; double ret = 0; for (int i = h; i <= r; i++) ret += w[i] ^ w[i + 1]; return fabs(ret); } int main() { scanf( %d , &T); for (; T--;) { init(); scanf( %d , &n); n--; scanf( %lf%lf , &p.x, &p.y); for (int i = 1; i <= n; i++) { scanf( %lf%lf , &a[i].x, &a[i].y); a[i] = a[i] - p; } sort(a + 1, a + 1 + n); int flag = 0; for (int i = 1; i <= n; i++) { a[i + n] = a[i]; insert(a[i] + p, a[i + 1] + p); if (fabs(a[i].alp - a[i + 1].alp) < 1e-12) flag = 1; } for (int i = 1, j = 2; i <= n; i++) { for (; j < i + n && ((a[j] - a[i]) ^ a[i]) < 1e-12; j++) ; if (i != j - 1 && !insert(a[i] + p, a[j - 1] + p)) flag = 1; } if (flag) { puts( 0 ); continue; } printf( %.8lf n , HPI() / 2.0); } return 0; }
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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } using namespace std; const int N = 20; pair<double, double> p1[N], p2[N]; int n, m; bool tag; int p[N], vis[N]; bool ok(pair<double, double> a, pair<double, double> b, pair<double, double> c, pair<double, double> d) { if (!(min(a.first, b.first) <= max(c.first, d.first) && min(c.second, d.second) <= max(a.second, b.second) && min(c.first, d.first) <= max(a.first, b.first) && min(a.second, b.second) <= max(c.second, d.second))) return 0; double u, v, w, z; u = (c.first - a.first) * (b.second - a.second) - (b.first - a.first) * (c.second - a.second); v = (d.first - a.first) * (b.second - a.second) - (b.first - a.first) * (d.second - a.second); w = (a.first - c.first) * (d.second - c.second) - (d.first - c.first) * (a.second - c.second); z = (b.first - c.first) * (d.second - c.second) - (d.first - c.first) * (b.second - c.second); return (u * v <= 0.00000001 && w * z <= 0.00000001); } void dfs(int now) { bool flag; if (tag) return; if (now > n) { flag = 1; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (!ok(p1[i], p2[p[i]], p1[j], p2[p[j]])) return; tag = 1; return; } for (int i = 1; i <= m; i++) if (!vis[i]) { p[now] = i; dfs(now + 1); } } int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) scanf( %lf%lf , &p1[i].first, &p1[i].second); for (int i = 1; i <= m; i++) scanf( %lf%lf , &p2[i].first, &p2[i].second); if (n != m) { puts( No ); return 0; } tag = 0; dfs(1); if (tag) puts( Yes ); else puts( No ); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_1_V
`define SKY130_FD_SC_HDLL__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_1_V
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) if (n == i * (i + 1) / 2) { cout << YES ; return 0; } cout << NO ; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_PP_BLACKBOX_V
/**
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_bleeder (
SHORT,
VPWR ,
VGND ,
VPB ,
VNB
);
input SHORT;
inout VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_PP_BLACKBOX_V
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#include <bits/stdc++.h> int main(void) { char z[201], *p; const int H[] = {0, 1, 2, 3, 4, 2, 6, 7, 5, 6}; int s = 999, n = 2, Q[2][8] = {}; while (n--) for (gets(p = z); *p; ++Q[n][H[*p++ - 0 ]]) ; while (s && 8 ^ ++n) if (Q[1][n]) s = std::min(s, Q[0][n] / Q[1][n]); printf( %d , s); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int z = 0, f = 0, n, a; cin >> n; while (n--) { cin >> a; a == 0 ? z++ : f++; } if (z > 0 && f > 8) { f -= f % 9; while (f--) cout << 5 ; while (z--) cout << 0 ; cout << endl; } else if (z > 0) cout << 0 n ; else cout << -1 n ; }
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#include <bits/stdc++.h> using namespace std; const double Pi = acos(-1), eps = 1e-10; int n, m, k, Q, id[100005], rt, siz[100005], f[100005]; int fir[100005], tot; int sgn(double x) { return x > -eps && x < eps ? 0 : 1; } struct node { double ang; int to, s; bool operator<(const node &p) const { return sgn(ang - p.ang) ? ang < p.ang : s < p.s; } }; vector<node> G[100005]; struct Point { long long x, y; Point(long long x = 0, long long y = 0) : x(x), y(y) {} Point operator-(const Point &p) { return Point(x - p.x, y - p.y); } long long operator*(const Point &p) { return x * p.y - y * p.x; } double angle() { return atan2(y, x); } } a[100005]; int find(int x) { return !f[x] ? x : f[x] = find(f[x]); } void dfs(int u, int ff) { siz[u] = 1; for (int i = 0, v; i < G[u].size() - 1; i++) { if (G[u][i].to == ff) swap(G[u].back(), G[u][i]); dfs(v = G[u][i].to, u), siz[u] += siz[v]; } } int main() { scanf( %d%d , &n, &m); for (int i = 1, x, y; i <= m; i++) { scanf( %d%d , &x, &y); if (find(x) != find(y)) G[x].push_back((node){0, y, 0}), G[y].push_back((node){0, x, 0}), f[find(x)] = find(y); } for (int i = 1; i <= n; i++) scanf( %lld%lld , &a[i].x, &a[i].y), (!rt || a[i].x < a[rt].x) && (rt = i); G[rt].push_back((node){0, 0, 0}), a[0].x = -2e9, a[0].y = a[rt].y; dfs(rt, 0); for (int u = 1; u <= n; u++) { for (int i = 0; i < G[u].size(); i++) G[u][i].ang = (a[G[u][i].to] - a[u]).angle(); sort(G[u].begin(), G[u].end() - 1); for (int i = 0; i < G[u].size() - 1; i++) G[u][i].s = siz[G[u][i].to] + (i ? G[u][i - 1].s : 0); } scanf( %d , &Q); while (Q--) { scanf( %d , &k); for (int i = 0; i < k; i++) scanf( %d , &id[i]); long long area = 0; for (int i = 0; i < k; i++) area += a[id[i]] * a[id[(i + 1) % k]]; if (area < 0) reverse(id, id + k); int ans = 0; for (int o = 0; o < k; o++) { int i = id[o]; double L = (a[id[(o + k - 1) % k]] - a[i]).angle(), R = (a[id[(o + 1) % k]] - a[i]).angle(); if (L < R) { if (L + eps < G[i].back().ang && G[i].back().ang + eps < R) ans += siz[i]; int l = lower_bound(G[i].begin(), G[i].end() - 1, (node){L, 0, 1000000000}) - G[i].begin() - 1; int r = lower_bound(G[i].begin(), G[i].end() - 1, (node){R, 0, -1}) - G[i].begin() - 1; ans -= (r >= 0 ? G[i][r].s : 0) - (l >= 0 ? G[i][l].s : 0); } else { if (L + eps < G[i].back().ang || G[i].back().ang + eps < R) ans += siz[i]; int l = lower_bound(G[i].begin(), G[i].end() - 1, (node){R, 0, -1}) - G[i].begin() - 1; int r = lower_bound(G[i].begin(), G[i].end() - 1, (node){L, 0, 1000000000}) - G[i].begin() - 1; ans -= (G[i].size() >= 2 ? G[i][G[i].size() - 2].s : 0) - (r >= 0 ? G[i][r].s : 0) + (l >= 0 ? G[i][l].s : 0); } } printf( %d n , ans); } }
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#include <bits/stdc++.h> using namespace std; int n; int ara[200010]; string res; string str; void func(int le, int ri, int chk, int past) { if (res.size() < str.size()) { res = str; } if (le > ri) { return; } if (chk == 0) { if ((past < ara[le]) && (ara[le] < ara[ri])) { str += L ; func(le + 1, ri, chk, ara[le]); str.pop_back(); } else if ((past < ara[ri]) && (ara[ri] < ara[le])) { str += R ; func(le, ri - 1, chk, ara[ri]); str.pop_back(); } else if ((past < ara[ri]) && (ara[ri] == ara[le])) { str += L ; func(le + 1, ri, 1, ara[le]); str.pop_back(); str += R ; func(le, ri - 1, 2, ara[ri]); str.pop_back(); } else if (past < ara[le]) { str += L ; func(le + 1, ri, chk, ara[le]); str.pop_back(); } else if (past < ara[ri]) { str += R ; func(le, ri - 1, chk, ara[ri]); str.pop_back(); } } else if (chk == 1) { if (past < ara[le]) { str += L ; func(le + 1, ri, chk, ara[le]); str.pop_back(); } } else { if (past < ara[ri]) { str += R ; func(le, ri - 1, chk, ara[ri]); str.pop_back(); } } } int main() { cin >> n; for (int i = 0; i <= n - 1; i++) { cin >> ara[i]; } str = ; res = ; func(0, n - 1, 0, 0); cout << res.size() << n ; cout << res << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, x; long long k, count = 0; char c; cin >> n >> x; for (int i = 1; i <= n; i++) { cin >> c >> k; if (c == + ) { x += k; } else { if (x >= k) { x -= k; } else { count++; } } } cout << x << << count; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100000 + 2; int lis[N], where[N], length[N], link[N], a[N], b[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } a[n] = INT_MAX; int m; cin >> m; for (int i = 0; i < m; ++i) { cin >> b[i]; } sort(b, b + m); fill(lis, lis + n + 2, INT_MAX); fill(where, where + n + 2, -1); lis[0] = 0; for (int i = 0; i <= n; ++i) { if (a[i] == -1) { int fill = m - 1; for (int index = n + 1; index > 0; --index) { while (fill > 0 && b[fill - 1] > lis[index - 1]) { --fill; } if (b[fill] > lis[index - 1] && b[fill] <= lis[index]) { lis[index] = b[fill], where[index] = i; } } link[i] = i - 1; while (link[i] >= 0 && a[link[i]] != -1) { --link[i]; } length[i] = -1; } else { int index = lower_bound(lis, lis + n + 2, a[i]) - lis; lis[index] = a[i], where[index] = i; link[i] = where[index - 1]; length[i] = index; } } int index = n, prv = -1; while (index != -1) { if (a[index] == -1) { length[index] = length[prv] - 1; int fill = m - 1; while (b[fill] >= a[prv]) { --fill; } a[index] = b[fill]; b[fill] = INT_MAX; prv = index; if (length[index] == 1) { index = -1; } else { for (int i = 0; i < index; ++i) { if (a[i] < a[index] && length[i] + 1 == length[index]) { index = i; break; } } if (index == prv) { index = link[index]; } } } else { prv = index, index = link[index]; } } int ptr = 0; for (int i = 0; i < n; ++i) { if (a[i] == -1) { while (b[ptr] == INT_MAX) { ++ptr; } a[i] = b[ptr++]; } cout << a[i] << ; } cout << n ; }
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// Remodified for the course: Application of FPGA by Prof. Chu and Prof. Chen
// Team mate: Wei cheng (³Ìΰ)
// Institution: Zhejiang University
// This module is designed for the course: Design of the digital system.
// Author: Pengwei Wu
// Teacher: Peiyong Zhang
// ״̬»úÄ£ÐͲÉÓÿα¾ËùÊöµÄÁ½¸ö״̬»úÀ´Íê³É¡£(ÆäʵҲ²»ËãÌرðµäÐ͵Ä״̬»úµÄ˵£©
// ´úÂëÃüÃû¹æÔò£ºÏ±ê½Ø¶Ïʽ¡£
// ´úÂëÃüÃû£º°´ÕÕSPARTAN-3AÊÖ²áÒý½Å¶¨ÒåʾÀýÎļþ£¨UCF-TEST)½øÐÐÃüÃû¡£
// Ò»ÇÐ×¢ÊÍÖÐûÓÐÌáµ½µÄÐÅÏ¢£¬»òÕßÊôÓÚ³£Ê¶ÐÔ֪ʶ£¬±ÈÈç¿ÉÒÔÔÚWIKIPEDIAÖÐÑ°ÕÒµ½¡£»òÕß¿ÉÒÔÔÚ¸½´øµÄPDFÎļþÖÐÕÒµ½¡£
// Èç¹ûÄã¿´µ½µÄ´úÂëÖÐûÓÐPDFÎļþ£¬Äã¿ÉÒÔÔÚÎÒµÄGITHUBÖ÷Ò³ÉÏÕÒµ½£ºÎÒµÄGITHUBÃû×ÖÊÇpwwu£¬»¶ÓFORK¡£
// You should not open this code in ISE
// chinese will not be supported
// ¼¸µã˵Ã÷£º´úÂë±¾ÉíÔÚÊä³öµÄʱºòʹÓÃÁËËø´æ¡£
module vga_sync
(
input wire clk, reset,
output wire hsync, vsync, video_on, p_tick,
// hysnc, vsync is the output sync signal
// ptick is used for other circuit such as the pixel generation circuit
output wire [9:0] pixel_x, pixel_y
// piexl_x and pixel_y output the counter of hsync and vsync
);
// constant declaration
// VGA 640-by-480 sync parameters
localparam HD = 640; // horizontal display area
localparam HF = 48 ; // h. front (left) border
localparam HB = 16 ; // h. back (right) border
localparam HR = 96 ; // h. retrace
localparam VD = 480; // vertical display area
localparam VF = 10; // v. front (top) border
localparam VB = 33; // v. back (bottom) border
localparam VR = 2; // v. retrace
// mod-2 counter
reg mod2_reg;
wire mod2_next;
// sync counters
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg, v_count_next;
// output buffer
reg v_sync_reg, h_sync_reg;
wire v_sync_next, h_sync_next;
// status signal
wire h_end, v_end, pixel_tick;
// First and foremost, let us make another clock.
// The clock information and any other information that can not be found in this document will be found in the pdf file
// converted from a md file.
// Or the information can be found in my Github pages: named ZJUPWWU
// mod-2 circuit to generate 25 MHz enable tick
assign mod2_next = ~mod2_reg;
assign pixel_tick = mod2_reg;
// clock finished
// state switch
always @(posedge clk, posedge reset)
if (reset)
begin
mod2_reg <= 1'b0;
v_count_reg <= 0;
h_count_reg <= 0;
v_sync_reg <= 1'b0;
h_sync_reg <= 1'b0;
end
else
// next is inputted to the state machine
begin
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end
// status signals
// end of horizontal counter (799)
// end of vertical counter (524)
assign h_end = (h_count_reg==(HD+HF+HB+HR-1));
assign v_end = (v_count_reg==(VD+VF+VB+VR-1));
// next-state logic of mod-800 horizontal sync counter
always @ (*)
if (pixel_tick) // 25 MHz pulse
if (h_end)
h_count_next = 0;
else
h_count_next = h_count_reg + 1;
else
h_count_next = h_count_reg;
// next-state logic of mod-525 vertical sync counter
always @ (*)
if (pixel_tick & h_end)
if (v_end)
v_count_next = 0;
else
v_count_next = v_count_reg + 1;
else
v_count_next = v_count_reg;
// horizontal and vertical sync, buffered to avoid glitch
// h_sync_next asserted between 656 and 751
assign h_sync_next = (h_count_reg>=(HD+HB) &&
h_count_reg<=(HD+HB+HR-1));
// vh_sync_next asserted between 490 and 491
assign v_sync_next = (v_count_reg>=(VD+VB) &&
v_count_reg<=(VD+VB+VR-1));
// video on/off
assign video_on = (h_count_reg<HD) && (v_count_reg<VD);
// output
assign hsync = h_sync_reg;
assign vsync = v_sync_reg;
assign pixel_x = h_count_reg;
assign pixel_y = v_count_reg;
assign p_tick = pixel_tick;
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND2_TB_V
`define SKY130_FD_SC_LP__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND2_TB_V
|
//==================================================================================================
// Filename : FPU_Interface.v
// Created On : 2016-10-29 12:45:25
// Last Modified : 2016-10-30 15:01:39
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module FPU_Interface2 #(parameter W = 64, EW = 11, SW = 52, SWR = 55, EWR = 6)
(
//Input Signals
input wire clk,
input wire rst,
input wire begin_operation,
input wire ack_operation,
input wire [2:0] operation,
input wire [1:0] region_flag,
input wire [W-1:0] Data_1,
input wire [W-1:0] Data_2,
input wire [1:0] r_mode,
//Output Signals
output wire overflow_flag,
output wire underflow_flag,
output wire NaN_flag,
output wire operation_ready,
output wire [W-1:0] op_result,
output wire busy
);
//Signal declaration
wire beg_fsm_mult;
wire beg_fsm_addsubt;
wire beg_fsm_cordic;
wire beg_add_subt_cordic;
wire beg_add_subt;
wire ack_fsm_mult;
wire ack_fsm_addsubt;
wire ack_fsm_cordic;
wire ack_add_subt_cordic;
wire ack_add_subt;
wire op_mod_add_subt;
wire op_mod_cordic;
wire op_addsubt_cordic;
wire op_addsubt;
wire [W-1:0] add_subt_dataA;
wire [W-1:0] add_subt_dataB;
wire [W-1:0] add_subt_data1;
wire [W-1:0] add_subt_data2;
wire [W-1:0] result_add_subt;
wire ready_add_subt;
wire ready_cordic;
wire ready_mult;
wire overflow_flag_addsubt;
wire underflow_flag_addsubt;
wire overflow_flag_mult;
wire underflow_flag_mult;
wire [W-1:0] cordic_result;
wire [W-1:0] mult_result;
wire [1:0] operation_reg;
wire [W-1:0] dataA, dataB;
wire NaN_reg;
//----------------------------------------------------------------------------------------------------------------------------
d_ff_en # (.W(2)) operation_dff
(
.clk (clk),//system clock
.rst (rst), //system reset
.enable(1'b1), //load signal
.D (operation[2:1]), //input signal
.Q (operation_reg) //output signal
);
d_ff_en # (.W(W)) reg_dataA
(
.clk (clk),//system clock
.rst (rst), //system reset
.enable(1'b1), //load signal
.D (Data_1), //input signal
.Q (dataA) //output signal
);
d_ff_en # (.W(W)) reg_dataB
(
.clk (clk),//system clock
.rst (rst), //system reset
.enable(1'b1), //load signal
.D (Data_2), //input signal
.Q (dataB) //output signal
);
generate
case(W)
32:
begin : BLKNaN1
NaN_mod_32 NaN_flag_32
(
.operation(operation_reg),
.data1 (dataA),
.data2 (dataB),
.NaN_flag (NaN_reg)
);
end
64:
begin : BLKNaN2
NaN_mod_64 NaN_flag_64
(
.operation(operation_reg),
.data1 (dataA),
.data2 (dataB),
.NaN_flag (NaN_reg)
);
end
default:
begin : BLKNaN3
NaN_mod_32 NaN_flag_32
(
.operation(operation_reg),
.data1 (dataA),
.data2 (dataB),
.NaN_flag (NaN_reg)
);
end
endcase
endgenerate
d_ff_en # (.W(1)) NaN_dff
(
.clk (clk),//system clock
.rst (rst), //system reset
.enable(1'b1), //load signal
.D (NaN_reg), //input signal
.Q (NaN_flag) //output signal
);
//----------------------------------------------------------------------------------------------------------------------------
demux_1x3 demux_beg_op
(
.data (begin_operation),
.select(operation[2:1]),
.ch1 (beg_fsm_addsubt),
.ch2 (beg_fsm_cordic),
.ch3 (beg_fsm_mult)
);
demux_1x3 demux_ack_op
(
.data (ack_operation),
.select(operation[2:1]),
.ch1 (ack_fsm_addsubt),
.ch2 (ack_fsm_cordic),
.ch3 (ack_fsm_mult)
);
deco_op deco_operation
(
.operation (operation[1:0]),
.op_mod_add_subt(op_mod_add_subt),
.op_mod_cordic (op_mod_cordic)
);
///******************MUXES TO HANDLE THE INTERFACE BETWEEN ADD-SUB AND CORDIC***************
Mux_2x1 #(.W(1)) mux_beg_addsubt
(
.select (operation[1]),
.ch_0 (beg_fsm_addsubt),
.ch_1 (beg_add_subt_cordic),
.data_out(beg_add_subt)
);
// Mux_2x1 #(.W(1)) mux_ack_addsubt
// (
// .select (operation[1]),
// .ch_0 (ack_fsm_addsubt),
// .ch_1 (ack_add_subt_cordic),
// .data_out(ack_add_subt)
// );
Mux_2x1 #(.W(1)) mux_operation_add_cordic
(
.select (operation[1]),
.ch_0 (op_mod_add_subt),
.ch_1 (op_addsubt_cordic),
.data_out(op_addsubt)
);
Mux_2x1 #(.W(W)) mux_data_in1
(
.select (operation[1]),
.ch_0 (Data_1),
.ch_1 (add_subt_dataA),
.data_out(add_subt_data1)
);
Mux_2x1 #(.W(W)) mux_data_in2
(
.select (operation[1]),
.ch_0 (Data_2),
.ch_1 (add_subt_dataB),
.data_out(add_subt_data2)
);
///////////////******************************************************************************
// CORDIC_Arch3v1 #(.W(W),.EW(EW),.SW(SW),.SWR(SWR)) FPSENCOS (
// .clk (clk), //global clk
// .rst (rst), //glbl rst signal
// .beg_fsm_cordic (beg_fsm_cordic), //init signal
// .ack_cordic (ack_fsm_cordic), //ackleg signal from extrnl module
// .operation (op_mod_cordic), //sine or cosine
// .data_in (Data_1), //input angle in radians
// .shift_region_flag (region_flag), // region of the Signal
// .ready_cordic (ready_cordic), //output signal as a ready
// .data_output (cordic_result), //ouput date in single or double precision
// .beg_add_subt (beg_add_subt_cordic), //
// .ack_add_subt (ack_add_subt_cordic),
// .add_subt_dataA (add_subt_dataA),
// .add_subt_dataB (add_subt_dataB),
// .result_add_subt (result_add_subt),
// .op_add_subt (op_addsubt_cordic),
// .ready_add_subt (ready_add_subt)
// );
wire enab_cont_iter;
CORDIC_Arch3v1 #(.W(W),.EW(EW),.SW(SW),.SWR(SWR)) FPSENCOS
(
.clk (clk),
.rst (rst),
.beg_fsm_cordic (beg_fsm_cordic),
.ack_cordic (ack_fsm_cordic),
.operation (op_mod_cordic),
.data_in (Data_1),
.shift_region_flag (region_flag),
.ready_cordic (ready_cordic),
.data_output (cordic_result),
.beg_add_subt (beg_add_subt_cordic),
.add_subt_dataA (add_subt_dataA),
.add_subt_dataB (add_subt_dataB),
.result_add_subt (result_add_subt),
.op_add_subt (op_addsubt_cordic),
.ready_add_subt (ready_add_subt),
.enab_cont_iter (enab_cont_iter)
);
FPU_Multiplication_Function #(.W(W),.EW(EW),.SW(SW)) FPMULT (
.clk (clk),
.rst (rst),
.beg_FSM (beg_fsm_mult),
.ack_FSM (ack_fsm_mult),
.Data_MX (Data_1),
.Data_MY (Data_2),
.round_mode (r_mode),
.overflow_flag (overflow_flag_mult),
.underflow_flag (underflow_flag_mult),
.ready (ready_mult),
.final_result_ieee (mult_result)
);
// FPU_PIPELINED_FPADDSUB #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) FPADDSUB (
// .clk (clk),
// .rst (rst),
// .beg_FSM (beg_add_subt),
// .ack_FSM (ack_add_subt),
// .Data_X (add_subt_data1),
// .Data_Y (add_subt_data2),
// .add_subt (op_addsubt),
// .r_mode (r_mode),
// .overflow_flag (overflow_flag_addsubt),
// .underflow_flag (underflow_flag_addsubt),
// .ready (ready_add_subt),
// .final_result_ieee (result_add_subt)
// );
FPU_PIPELINED_FPADDSUB #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) FPADDSUB (
.clk (clk),
.rst (rst|enab_cont_iter),
.beg_OP (beg_add_subt),
.Data_X (add_subt_data1),
.Data_Y (add_subt_data2),
.add_subt (op_addsubt),
.busy (busy),
.overflow_flag (overflow_flag_addsubt),
.underflow_flag (underflow_flag_addsubt),
.zero_flag (zero_flag),
.ready (ready_add_subt),
.final_result_ieee (result_add_subt)
);
//----------------------------------------------------------------------------------------------------------------------------
Mux_2x1 #(.W(1)) overflow_flag_mux
(
.select (operation[2]),
.ch_0 (overflow_flag_addsubt),
.ch_1 (overflow_flag_mult),
.data_out(overflow_flag)
);
Mux_2x1 #(.W(1)) underflow_flag_mux
(
.select (operation[2]),
.ch_0 (underflow_flag_addsubt),
.ch_1 (underflow_flag_mult),
.data_out(underflow_flag)
);
Mux_3x1_b #(.W(1)) mux_ready_op
(
.select (operation[2:1]),
.ch_0 (ready_add_subt),
.ch_1 (ready_cordic),
.ch_2 (ready_mult),
.data_out(operation_ready)
);
Mux_3x1_b #(.W(W)) mux_result_op
(
.select (operation[2:1]),
.ch_0 (result_add_subt),
.ch_1 (cordic_result),
.ch_2 (mult_result),
.data_out(op_result)
);
endmodule
|
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//=======================================================
// This code is partially generated by Terasic System Builder
//=======================================================
module de10_nano_top(
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
//////////// HPS //////////
inout HPS_CONV_USB_N,
output [14: 0] HPS_DDR3_ADDR,
output [ 2: 0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CKE,
output HPS_DDR3_CS_N,
output [ 3: 0] HPS_DDR3_DM,
inout [31: 0] HPS_DDR3_DQ,
inout [ 3: 0] HPS_DDR3_DQS_N,
inout [ 3: 0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
//////////// LED //////////
output [ 7: 0] LED
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire hps_fpga_reset_n;
wire fpga_clk_50;
// connection of internal logics
assign fpga_clk_50 = FPGA_CLK1_50;
//=======================================================
// Structural coding
//=======================================================
soc_system u0(
//Clock&Reset
.clk_clk(FPGA_CLK1_50), // clk.clk
.reset_reset_n(hps_fpga_reset_n), // reset.reset_n
//HPS ddr3
.memory_mem_a(HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba(HPS_DDR3_BA), // .mem_ba
.memory_mem_ck(HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n(HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke(HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n(HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n(HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n(HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n(HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n(HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq(HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs(HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n(HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt(HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm(HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin(HPS_DDR3_RZQ), // .oct_rzqin
//FPGA
.hps_0_h2f_reset_reset_n(hps_fpga_reset_n) // hps_0_h2f_reset.reset_n
);
// Blink LED, to indicate everything is working
reg [25: 0] counter;
reg led_level;
always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n) begin
if (~hps_fpga_reset_n) begin
counter <= 0;
led_level <= 0;
end
else if (counter == 24999999) begin
counter <= 0;
led_level <= ~led_level;
end
else
counter <= counter + 1'b1;
end
assign LED[0] = led_level;
endmodule
|
`timescale 1ns / 100ps
/*
* The GPIA_DWORD module describes a 64-bit collection of GPIA_BITs. Each
* octet of bits can be independently masked by its own stb_i input.
*/
module GPIA_DWORD(
input clk_i,
input res_i,
input [1:0] mode_i,
input [63:0] d_i,
input [7:0] stb_i,
output [63:0] q_o
);
GPIA_BYTE byte0(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[7:0]),
.stb_i(stb_i[0]),
.q_o(q_o[7:0])
);
GPIA_BYTE byte1(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[15:8]),
.stb_i(stb_i[1]),
.q_o(q_o[15:8])
);
GPIA_BYTE byte2(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[23:16]),
.stb_i(stb_i[2]),
.q_o(q_o[23:16])
);
GPIA_BYTE byte3(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[31:24]),
.stb_i(stb_i[3]),
.q_o(q_o[31:24])
);
GPIA_BYTE byte4(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[39:32]),
.stb_i(stb_i[4]),
.q_o(q_o[39:32])
);
GPIA_BYTE byte5(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[47:40]),
.stb_i(stb_i[5]),
.q_o(q_o[47:40])
);
GPIA_BYTE byte6(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[55:48]),
.stb_i(stb_i[6]),
.q_o(q_o[55:48])
);
GPIA_BYTE byte7(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[63:56]),
.stb_i(stb_i[7]),
.q_o(q_o[63:56])
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_PP_V
|
/*!
memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
/*
Top level module: glues everything together.
*/
`define IDX(x) (((x)+1)*(8)-1):((x)*(8))
module memfifo (
input fxclk_in,
input ifclk_in,
input reset,
input [1:0] mode,
// debug
output [9:0] led1,
output [19:0] led2,
input SW8,
input SW10,
// ddr3
inout [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n,
inout [1:0] ddr3_dqs_p,
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [1:0] ddr3_dm,
output [0:0] ddr3_odt,
// ez-usb
inout [15:0] fd,
output SLWR, SLRD,
output SLOE, FIFOADDR0, FIFOADDR1, PKTEND,
input FLAGA, FLAGB
);
wire reset_mem, reset_usb;
wire ifclk;
reg reset_ifclk;
wire [24:0] mem_free;
wire [9:0] status;
wire [3:0] if_status;
reg [1:0] mode_buf;
// input fifo
reg [127:0] DI;
wire FULL, WRERR, USB_DO_valid;
reg WREN, wrerr_buf;
wire [15:0] USB_DO;
reg [127:0] in_data;
reg [3:0] wr_cnt;
reg [6:0] test_cnt;
reg [13:0] test_cs;
reg in_valid;
wire test_sync;
reg [1:0] clk_div;
// output fifo
wire [127:0] DO;
wire EMPTY, RDERR, USB_DI_ready;
reg RDEN, rderr_buf, USB_DI_valid;
reg [127:0] rd_buf;
reg [2:0] rd_cnt;
dram_fifo #(
.FIRST_WORD_FALL_THROUGH("TRUE"), // Sets the FIFO FWFT to FALSE, TRUE
.ALMOST_EMPTY_OFFSET2(13'h0008),
) dram_fifo_inst (
.fxclk_in(fxclk_in), // 48 MHz input clock pin
.reset(reset || reset_usb),
.reset_out(reset_mem), // reset output
.clkout2(), // PLL clock outputs not used for memory interface
.clkout3(),
.clkout4(),
.clkout5(),
// Memory interface ports
.ddr3_dq(ddr3_dq),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_addr(ddr3_addr),
.ddr3_ba(ddr3_ba),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_ck_p(ddr3_ck_p),
.ddr3_ck_n(ddr3_ck_n),
.ddr3_cke(ddr3_cke),
.ddr3_dm(ddr3_dm),
.ddr3_odt(ddr3_odt),
// input fifo interface, see "7 Series Memory Resources" user guide (ug743)
.DI(DI),
.FULL(FULL), // 1-bit output: Full flag
.ALMOSTFULL1(), // 1-bit output: Almost full flag
.ALMOSTFULL2(), // 1-bit output: Almost full flag
.WRERR(WRERR), // 1-bit output: Write error
.WREN(WREN), // 1-bit input: Write enable
.WRCLK(ifclk), // 1-bit input: Rising edge write clock.
// output fifo interface, see "7 Series Memory Resources" user guide (ug743)
.DO(DO),
.EMPTY(EMPTY), // 1-bit output: Empty flag
.ALMOSTEMPTY1(), // 1-bit output: Almost empty flag
.ALMOSTEMPTY2(), // 1-bit output: Almost empty flag
.RDERR(RDERR), // 1-bit output: Read error
.RDCLK(ifclk), // 1-bit input: Read clock
.RDEN(RDEN), // 1-bit input: Read enable
// free memory
.mem_free_out(mem_free),
// for debugging
.status(status)
);
ezusb_io #(
.OUTEP(2), // EP for FPGA -> EZ-USB transfers
.INEP(6), // EP for EZ-USB -> FPGA transfers
) ezusb_io_inst (
.ifclk(ifclk),
.reset(reset), // asynchronous reset input
.reset_out(reset_usb), // synchronous reset output
// pins
.ifclk_in(ifclk_in),
.fd(fd),
.SLWR(SLWR),
.SLRD(SLRD),
.SLOE(SLOE),
.PKTEND(PKTEND),
.FIFOADDR({FIFOADDR1, FIFOADDR0}),
.EMPTY_FLAG(FLAGA),
.FULL_FLAG(FLAGB),
// signals for FPGA -> EZ-USB transfer
.DI(rd_buf[15:0]), // data written to EZ-USB
.DI_valid(USB_DI_valid), // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
.DI_ready(USB_DI_ready), // 1 if new data are accepted
.DI_enable(1'b1), // setting to 0 disables FPGA -> EZ-USB transfers
.pktend_timeout(16'd73), // timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed
// setting to 0 disables this feature
// signals for EZ-USB -> FPGA transfer
.DO(USB_DO), // data read from EZ-USB
.DO_valid(USB_DO_valid), // 1 indicated valid data
.DO_ready((mode_buf==2'd0) && !reset_ifclk && !FULL), // setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
// debug output
.status(if_status)
);
/* BUFR ifclkin_buf (
.I(ifclk_in),
.O(ifclk)
); */
// assign ifclk = ifclk_in;
// debug board LEDs
assign led1 = SW10 ? status : { EMPTY, FULL, wrerr_buf, rderr_buf, if_status, FLAGB, FLAGA };
assign led2[0] = mem_free != { 1'b1, 24'd0 };
assign led2[1] = mem_free[23:19] < 5'd30;
assign led2[2] = mem_free[23:19] < 5'd29;
assign led2[3] = mem_free[23:19] < 5'd27;
assign led2[4] = mem_free[23:19] < 5'd25;
assign led2[5] = mem_free[23:19] < 5'd24;
assign led2[6] = mem_free[23:19] < 5'd22;
assign led2[7] = mem_free[23:19] < 5'd20;
assign led2[8] = mem_free[23:19] < 5'd19;
assign led2[9] = mem_free[23:19] < 5'd17;
assign led2[10] = mem_free[23:19] < 5'd15;
assign led2[11] = mem_free[23:19] < 5'd13;
assign led2[12] = mem_free[23:19] < 5'd12;
assign led2[13] = mem_free[23:19] < 5'd10;
assign led2[14] = mem_free[23:19] < 5'd8;
assign led2[15] = mem_free[23:19] < 5'd7;
assign led2[16] = mem_free[23:19] < 5'd5;
assign led2[17] = mem_free[23:19] < 5'd3;
assign led2[18] = mem_free[23:19] < 5'd2;
assign led2[19] = mem_free == 25'd0;
assign test_sync = wr_cnt[0] || (wr_cnt == 4'd14);
always @ (posedge ifclk)
begin
reset_ifclk <= reset || reset_usb || reset_mem;
if ( reset_ifclk )
begin
rderr_buf <= 1'b0;
wrerr_buf <= 1'b0;
end else
begin
rderr_buf <= rderr_buf || RDERR;
wrerr_buf <= wrerr_buf || WRERR;
end
// FPGA -> EZ-USB FIFO
if ( reset_ifclk )
begin
rd_cnt <= 3'd0;
USB_DI_valid <= 1'd0;
end else if ( USB_DI_ready )
begin
USB_DI_valid <= !EMPTY;
if ( !EMPTY )
begin
if ( rd_cnt == 3'd0 )
begin
rd_buf <= DO;
end else
begin
rd_buf[111:0] <= rd_buf[127:16];
end
rd_cnt <= rd_cnt+1;
end
end
RDEN <= !reset_ifclk && USB_DI_ready && !EMPTY && (rd_cnt==3'd0);
if ( reset_ifclk )
begin
in_data <= 128'd0;
in_valid <= 1'b0;
wr_cnt <= 4'd0;
test_cnt <= 7'd0;
test_cs <= 12'd47;
WREN <= 1'b0;
clk_div <= 2'd3;
end else if ( !FULL )
begin
if ( in_valid ) DI <= in_data;
if ( mode_buf == 2'd0 ) // input from USB
begin
if ( USB_DO_valid )
begin
in_data <= { USB_DO, in_data[127:16] };
in_valid <= wr_cnt[2:0] == 3'd7;
wr_cnt <= wr_cnt + 1;
end else
begin
in_valid <= 1'b0;
end
end else if ( clk_div == 2'd0 ) // test data generator
begin
if ( wr_cnt == 4'd15 )
begin
test_cs <= 12'd47;
in_data[126:120] <= test_cs[6:0] ^ test_cs[13:7];
in_valid <= 1'b1;
end else
begin
test_cnt <= test_cnt + 7'd111;
test_cs <= test_cs + { test_sync, test_cnt };
in_data[126:120] <= test_cnt;
in_valid <= 1'b0;
end
in_data[127] <= test_sync;
in_data[119:0] <= in_data[127:8];
wr_cnt <= wr_cnt + 1;
end else
begin
in_valid <= 1'b0;
end
if ( (mode_buf==2'd1) || ((mode_buf==2'd3) && SW8 ) )
begin
clk_div <= 2'd0; // data rate: 48 MByte/s
end else
begin
clk_div <= clk_div + 1; // data rate: 12 MByte/s
end
end
WREN <= !reset_ifclk && in_valid && !FULL;
mode_buf<=mode;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; const long long inf = 1e17; long long v[N]; long long c[N]; long long dp[N]; bool mark[N]; long long n, q; long long a, b; void solver() { cin >> a >> b; long long max1 = 0; long long color1 = 0; long long max2 = 0; long long color2 = 1; for (long long i = 0; i < N; i++) { dp[i] = -inf; mark[i] = 0; } for (long long i = 0; i < n; i++) { long long color = c[i]; long long value = v[i]; long long maxi = max1; if (color1 == color) { maxi = max2; } if (mark[color]) { dp[color] = max(dp[color], dp[color] + value * a); } dp[color] = max(dp[color], maxi + value * b); mark[color] = true; if (color != color1 && color != color2) { if (dp[color] > max1) { max2 = max1; color2 = color1; max1 = dp[color]; color1 = color; continue; } if (dp[color] > max2) { max2 = dp[color]; color2 = color; } } if (color == color1) { max1 = dp[color]; color1 = color; } if (color == color2) { max2 = dp[color]; if (max2 > max1) { swap(max2, max1); swap(color1, color2); } } } long long ans = 0; for (long long i = 0; i < n; i++) { ans = max(ans, dp[i]); } cout << ans << endl; } int main() { cin >> n >> q; for (long long i = 0; i < n; i++) { cin >> v[i]; } for (long long i = 0; i < n; i++) { cin >> c[i]; } for (long long i = 0; i < q; i++) { solver(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i, j, curr, n; cin >> curr >> n; int arr[curr + 1]; int temp; arr[0] = 1; int count = curr - 1; for (i = 1; i <= curr; i++) arr[i] = 0; for (i = 0; i < n; i++) { cin >> temp; if (temp == 1) { int a, b; cin >> a >> b; arr[a] = 1; arr[b] = 1; count = count - 2; } else { int a; cin >> a; arr[a] = 1; count = count - 1; } } arr[curr] = 1; int min = 0; for (i = 1; i < curr; i++) { if (arr[i] == 0 && arr[i + 1] == 0) { min += 1; i++; continue; } else if (arr[i] == 0) { min += 1; } } cout << min << << count << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:54:55 11/18/2013
// Design Name: i2s_out
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/tec-drums/i2sgen_test.v
// Project Name: tec-drums
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: i2s_out
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module i2sgen_test;
// Inputs
reg clock;
reg reset;
reg [15:0] left_data;
reg [15:0] right_data;
// Outputs
wire mclk;
wire lrck;
wire sclk;
wire sdin;
// Instantiate the Unit Under Test (UUT)
i2s_out uut (
.clock(clock),
.reset(reset),
.left_data(left_data),
.right_data(right_data),
.mclk(mclk),
.lrck(lrck),
.sclk(sclk),
.sdin(sdin)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
left_data = 0;
right_data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_SYNC_FIFO *
* Description: *
* This module is a FIFO with same clock for both reads and writes. *
* *
*****************************************************************************/
module Altera_UP_SYNC_FIFO (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
parameter DATA_DEPTH = 128;
parameter ADDR_WIDTH = 7;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DATA_WIDTH:1] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [ADDR_WIDTH:1] words_used;
output [DATA_WIDTH:1] read_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data)
// Unused
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone IV E",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DATA_WIDTH,
Sync_FIFO.lpm_widthu = ADDR_WIDTH,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
`timescale 1ns/1ps
//-----------------------------------------------------------------------------
// Title : DBG
// Project : KPU
//-----------------------------------------------------------------------------
// File : dbg.v
// Author : acorallo <>
// Created : 08.06.2017
//-----------------------------------------------------------------------------
// Description :
// Debug support logic implementation for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2017 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 08.06.2017 : created
//-----------------------------------------------------------------------------
`ifndef _dbg
`define _dbg
`include "kpu_conf.v"
`define DEBUG_CONF_DEFAULT 8'b0
`define DEBUG_IR_DEFAULT (`MOV_OP << 26) // That's a NOP
`define DEBUG_DATA_SEND_DEFAULT `N'b0
`define DEBUG_DATA_RECV_DEFAULT `N'b0
module dgb(
input wire clk_i,
// JTAG pads
input wire tms_pad_i,
input wire tck_pad_i,
input wire trstn_pad_i,
input wire tdi_pad_i,
output wire tdo_pad_o,
output wire tdo_padoe_o,
// KPU pads
output reg kpu_clk_o,
output reg kpu_wait_o,
input wire [3:0] kpu_d_sel_i,
input wire [`N-1:0] kpu_d_data_i,
output reg [`N-1:0] kpu_i_data_o,
output reg [`N-1:0] kpu_d_data_o,
// MEM pads
input wire mem_kpu_wait_i,
output reg [3:0] mem_d_sel_o,
input wire [`N-1:0] mem_i_data_i,
input wire [`N-1:0] mem_d_data_i,
output reg [`N-1:0] mem_d_data_o,
output reg debug_o
);
////////////////////////////////////////////////////////////////////////////////////////////
// Debug configuration register //
// //
// bit0 KPU clk is substituted by jtag clk when cycling in run_test/idle state //
// bit1 Provide to KPU the content of debug_ir as instruction fetched //
// bit2 Provide to KPU the content of debug_data_send as data fetched //
// bit3 Fetch data from KPU into debug_data_recv //
// bit4 When asserted let the cpu increment PC each clock //
////////////////////////////////////////////////////////////////////////////////////////////
reg [7:0] debug_conf = `DEBUG_CONF_DEFAULT;
reg [`N-1:0] debug_ir = `DEBUG_IR_DEFAULT;
reg [`N-1:0] debug_data_send = `DEBUG_DATA_SEND_DEFAULT;
reg [`N-1:0] debug_data_recv = `DEBUG_DATA_RECV_DEFAULT;
reg [`N-1:0] debug_data_recv_buf = `DEBUG_DATA_RECV_DEFAULT;
wire debug_conf_select;
wire debug_ir_select;
wire debug_data_send_select;
wire debug_data_recv_select;
wire debug_conf_tdo;
wire debug_ir_tdo;
wire debug_data_send_tdo;
wire debug_data_recv_tdo;
wire test_logic_reset;
wire run_test_idle;
wire capture_dr;
wire shift_dr;
tap tap_i (// JTAG
.tms_pad_i(tms_pad_i),
.tck_pad_i(tck_pad_i),
.trstn_pad_i(trstn_pad_i),
.tdi_pad_i(tdi_pad_i),
.tdo_pad_o(tdo_pad_o),
.tdo_padoe_o(tdo_padoe_o),
// States
.test_logic_reset_o(test_logic_reset),
.run_test_idle_o(run_test_idle),
.debug_conf_select_o(debug_conf_select),
.debug_conf_tdo_i(debug_conf_tdo),
.debug_ir_select_o(debug_ir_select),
.debug_ir_tdo_i(debug_ir_tdo),
.debug_data_send_select_o(debug_data_send_select),
.debug_data_send_tdo_i(debug_data_send_tdo),
.debug_data_recv_select_o(debug_data_recv_select),
.debug_data_recv_tdo_i(debug_data_recv_tdo),
.bs_chain_tdo_i(1'b0),
.capture_dr_o(capture_dr),
.shift_dr_o(shift_dr));
/////////////////////////////////////////////////
// Debug configuration register logic //
/////////////////////////////////////////////////
always @ (posedge tck_pad_i or negedge trstn_pad_i) begin
if(trstn_pad_i == 0)
debug_conf <= #1 `DEBUG_CONF_DEFAULT; // DEBUG REG after reset
else if (test_logic_reset)
debug_conf <= #1 `DEBUG_CONF_DEFAULT; // DEBUG REG after reset
else if(debug_conf_select & capture_dr)
debug_conf <= #1 `DEBUG_CONF_DEFAULT;
else if(debug_conf_select & shift_dr)
debug_conf <= #1 {tdi_pad_i, debug_conf[7:1]};
end
assign debug_conf_tdo = debug_conf[0];
always @(debug_conf)
if (`KPU_SIM_TRACE >= 3)
$display("KPU-DBG: DEBUG CONF REG <= %b", debug_conf);
////////////////////////////////////////////////////////
// End of debug configuration register logic //
////////////////////////////////////////////////////////
/////////////////////////////////
// Debug ir logic //
/////////////////////////////////
always @ (posedge tck_pad_i or negedge trstn_pad_i) begin
if(trstn_pad_i == 0)
debug_ir <= #1 `DEBUG_IR_DEFAULT; // DEBUG IR after reset
else if (test_logic_reset)
debug_ir <= #1 `DEBUG_IR_DEFAULT; // DEBUG IR OAafter reset
else if(debug_ir_select & capture_dr)
debug_ir <= #1 `DEBUG_IR_DEFAULT;
else if(debug_ir_select & shift_dr)
debug_ir <= #1 {tdi_pad_i, debug_ir[`N-1:1]};
end
assign debug_ir_tdo = debug_ir[0];
always @(debug_ir)
if (`KPU_SIM_TRACE >= 3)
$display("KPU-DBG: DEBUG IR <= %b", debug_ir);
////////////////////////////////////////
// End of debug ir logic //
////////////////////////////////////////
//////////////////////////////////
// Debug data_send logic //
//////////////////////////////////
always @ (posedge tck_pad_i or negedge trstn_pad_i) begin
if(trstn_pad_i == 0)
debug_data_send <= #1 `DEBUG_DATA_SEND_DEFAULT; // DEBUG DATA SEND after reset
else if (test_logic_reset)
debug_data_send <= #1 `DEBUG_DATA_SEND_DEFAULT; // DEBUG DATA SEND after reset
else if(debug_data_send_select & capture_dr)
debug_data_send <= #1 `DEBUG_DATA_SEND_DEFAULT;
else if(debug_data_send_select & shift_dr)
debug_data_send <= #1 {tdi_pad_i, debug_data_send[`N-1:1]};
end
assign debug_data_send_tdo = debug_data_send[0];
always @(debug_data_send)
if (`KPU_SIM_TRACE >= 3)
$display("KPU-DBG: DEBUG DATA SEND <= %b", debug_data_send);
////////////////////////////////////////
// End of debug data send logic //
////////////////////////////////////////
//////////////////////////////////
// Debug data_recv logic //
//////////////////////////////////
always @ (posedge tck_pad_i or negedge trstn_pad_i) begin
if(trstn_pad_i == 0)
debug_data_recv <= #1 `DEBUG_DATA_RECV_DEFAULT; // DEBUG DATA RECV after reset
else if (test_logic_reset)
debug_data_recv <= #1 `DEBUG_DATA_RECV_DEFAULT; // DEBUG DATA RECV after reset
else if(debug_data_recv_select & shift_dr)
debug_data_recv <= #1 {tdi_pad_i, debug_data_recv[`N-1:1]};
else
debug_data_recv <= #1 debug_data_recv_buf;
end
assign debug_data_recv_tdo = debug_data_recv[0];
always @(debug_data_recv)
if (`KPU_SIM_TRACE >= 3)
$display("KPU-DBG: DEBUG DATA RECV <= %b", debug_data_recv);
////////////////////////////////////////
// End of debug data recv logic //
////////////////////////////////////////
always @(*) begin
if (run_test_idle) begin
if (debug_conf[0]) begin
debug_o = ~debug_conf[4];
kpu_clk_o = ~tck_pad_i;
end
else begin
debug_o = 1'b0;
// We run at sys clk
kpu_clk_o = clk_i;
end
end
else begin
debug_o = 1'b0;
if (test_logic_reset)
kpu_clk_o = clk_i;
else
kpu_clk_o = 1'b0;
end
if (run_test_idle && debug_conf[1])
kpu_i_data_o = debug_ir;
else
kpu_i_data_o = mem_i_data_i;
if (debug_conf[2]) begin
kpu_d_data_o = debug_data_send;
kpu_wait_o = 1'b0;
end
else begin
kpu_d_data_o = mem_d_data_i;
kpu_wait_o = mem_kpu_wait_i;
end
if (debug_conf[3]) begin
debug_data_recv_buf = kpu_d_data_i;
mem_d_data_o = `N'b0;
mem_d_sel_o = 4'b0;
end
else begin
debug_data_recv_buf = `DEBUG_DATA_RECV_DEFAULT;
mem_d_data_o = kpu_d_data_i;
mem_d_sel_o = kpu_d_sel_i;
end
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:09:03 05/21/2016
// Design Name:
// Module Name: Test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Test(
input Clk_100M,
input Reset,
input Rx,
output Tx,
output reg [15:0]LEDs
);
reg [7:0] userData[0:99];
wire Rx_Ready;
reg Rx_Ack;
wire [7:0] Rx_Data;
reg [7:0] Tx_Data;
reg Tx_Send;
wire Tx_Busy;
reg Tx_Reset;
reg [7:0] Tx_DataIndex;
reg Tx_DataIndexLocked;
reg [7:0] sizeOfDataInByte;
reg [7:0] charCount;
reg receivingData;
reg prevBusyState;
initial prevBusyState = 1'b0;
initial sizeOfDataInByte = 1'b0;
reg doneReceiving;
//initial doneReceiving = 1'b1;
// RECEIVE
always @(posedge Clk_100M) begin
if (Reset) begin
Rx_Ack <= 0;
charCount <= 0;
doneReceiving <= 0;
end
else begin
if (prevBusyState & Rx_Ready) begin
// very first byte expected to be # characters in data.
if (sizeOfDataInByte == 0) begin
sizeOfDataInByte <= Rx_Data; // get number of charcters in data.
receivingData <= 1'b1; // next up start receiving data.
end
// actual data starts from byte 2.
else if (receivingData) begin
//userData[99 - charCount] <= Rx_Data; // actual data.
userData[charCount] <= Rx_Data; // actual data.
charCount <= charCount + 1'b1;
// if done receiving data, receive key.
if (charCount == sizeOfDataInByte - 1) begin
receivingData <= 1'b0; // to indicate finish receiving data.
doneReceiving <= 1;
end
end
Rx_Ack <= 1'b1;
end else if(~Rx_Ready) begin
Rx_Ack <= 1'b0;
end
prevBusyState <= !Rx_Ready;
end
end
// SEND.
always @(posedge Clk_100M) begin
if (Reset) begin
Tx_Data <= 1'b0;
Tx_Send <= 1'b0;
Tx_Reset <= 1'b0;
Tx_DataIndex <= 1'b0;
Tx_DataIndexLocked <= 1'b1; // used to lock Tx_DataIndex to prevent uncontrolled increments.
end
else if (doneReceiving) begin
//***********************************************************************************************
if (Tx_Busy == 0 && Tx_DataIndex < sizeOfDataInByte) begin
Tx_Data <= userData[Tx_DataIndex];
Tx_Send <= 1'b1;
Tx_DataIndexLocked <= 1'b0;
end
else begin
if (~Tx_DataIndexLocked) begin
Tx_DataIndex <= Tx_DataIndex + 1'b1;
Tx_DataIndexLocked <= 1'b1;
end
Tx_Send <= 1'b0;
end
//***********************************************************************************************
end
end
UART_Sender #(14, 14'd9999) sender(
Clk_100M,
//Tx_Reset,
Reset,
Tx_Data,
Tx_Send,
Tx_Busy,
Tx
);
UART_Receiver #(14, 14'd9999) receiver(
Clk_100M,
Reset,
Rx_Data,
Rx_Ready,
Rx_Ack,
Rx
);
always @(*) begin
// displays characters on the LEDs. Characters are shifted using btn P17 and M17
// going from left to right and right to left respectively.
//LEDs[15:8] <= Tx_DataIndex; // check
//LEDs[15:8] <= result[currentCharIndex];
//LEDs[15:8] <= encrypt_Data;
//LEDs[15:8] <= byteOfUserData;
//LEDs[15:8] <= keys[currentCharIndex%3]; // check
//LEDs[15:8] <= index; // check
//LEDs[15:8] <= sizeOfKeyInByte; // check
//LEDs[7:0] <= userData[99-currentCharIndex];
LEDs[15:8] <= Tx_DataIndex;
LEDs[7:0] <= userData[2]; // check
//LEDs[15:0] <= 16'b1111111111111111;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_top_rptr2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ctu_top_rptr2(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; vector<long long> g[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { long long n; cin >> n; string s; cin >> s; long long i, j; long long ans = 1e16; for (int i = 0; i < n - 3; i++) { long long sm = 0, c = 0; for (int j = i; j < i + 4; j++) { if (c % 4 == 0) { sm += min(abs(s[j] - A ), abs(s[j] - Z ) + 1); } if (c % 4 == 1) { sm += min(abs(s[j] - C ), abs(s[j] - Z ) + 3); } if (c % 4 == 2) { sm += min(abs(s[j] - T ), abs(s[j] - A ) + 7); } if (c % 4 == 3) { sm += min(abs(s[j] - G ), abs(s[j] - Z ) + 7); } c++; } ans = min(ans, sm); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> int read() { int ans = 0, c, f = 1; while (!isdigit(c = getchar())) if (c == - ) f *= -1; do ans = ans * 10 + c - 0 ; while (isdigit(c = getchar())); return ans * f; } const int N = 10050; int n, A[N], B[N]; int m, a[N], b[N], c[N], d[N]; void por(int x1, int y1, int x2, int y2) { a[m] = x1; b[m] = y1; c[m] = x2; d[m] = y2; ++m; } int main() { n = read(); for (int i = 1; i <= n; ++i) A[i] = read(); for (int i = 1; i <= n; ++i) B[i] = read(); for (int k = 1; k <= n; ++k) { int ti = 0, tj = 0; for (int i = k; i <= n; ++i) { if (A[i] == k) ti = i; if (B[i] == k) tj = i; } if (ti == k && tj == k) ; else if (ti == k) por(k, k, k, tj); else if (tj == k) por(k, k, ti, k); else por(ti, k, k, tj); std::swap(A[k], A[ti]); std::swap(B[k], B[tj]); } printf( %d n , m); for (int i = 0; i < m; ++i) printf( %d %d %d %d n , a[i], b[i], c[i], d[i]); return 0; }
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module wishbone_mem_interconnect (
clk,
rst,
i_m_we,
i_m_cyc,
i_m_stb,
i_m_sel,
o_m_ack,
i_m_dat,
o_m_dat,
i_m_adr,
o_m_int,
o_s0_we,
o_s0_cyc,
o_s0_stb,
o_s0_sel,
i_s0_ack,
o_s0_dat,
i_s0_dat,
o_s0_adr,
i_s0_int
);
localparam MEM_SEL_0 = 0;
localparam MEM_OFFSET_0 = 0;
localparam MEM_SIZE_0 = 4096;
//state
//control signals
input clk;
input rst;
//wishbone master signals
input i_m_we;
input i_m_stb;
input i_m_cyc;
input [3:0] i_m_sel;
input [31:0] i_m_adr;
input [31:0] i_m_dat;
output reg [31:0] o_m_dat;
output reg o_m_ack;
output reg o_m_int;
//wishbone mem signals
output o_s0_we;
output o_s0_cyc;
output o_s0_stb;
output [3:0] o_s0_sel;
output [31:0] o_s0_adr;
output [31:0] o_s0_dat;
input [31:0] i_s0_dat;
input i_s0_ack;
input i_s0_int;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h1;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 0;
endmodule
|
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