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// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [1:0] bus_s [7:0];
wire [15:0] bus_a [7:0];
wire [31:0] bus_d [7:0];
wire [7:0] pll;
wire [31:0] outx [7:0];
wire [31:0] dirx [7:0];
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
genvar i;
generate
for (i=0; i<8; i=i+1)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena;
endmodule
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#include <bits/stdc++.h> using namespace std; char a[100010]; int c[100010]; const int mod = 1000000007; long long Pow(long long a, long long b, long long c) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % c; b >>= 1; a = a * a % c; } return ans; } int main() { scanf( %s , a); int n = strlen(a), k; int cnt0 = count(a, a + n, 0 ); int cnt5 = count(a, a + n, 5 ); int cnt = 0; for (int i = 0; i <= n - 1; i++) { if (a[i] == 0 || a[i] == 5 ) { c[cnt++] = i; } } scanf( %d , &k); long long tmp1 = Pow(2, (long long)n * k, mod); tmp1 -= 1; if (tmp1 < 0) tmp1 += mod; long long tmp2 = Pow(2, n, mod); tmp2 -= 1; if (tmp2 < mod) tmp2 += mod; tmp2 = Pow(tmp2, mod - 2, mod); long long ans = 0; for (int i = 0; i <= cnt - 1; i++) { ans += Pow(2, c[i], mod) * tmp1 % mod * tmp2 % mod; if (ans >= mod) ans -= mod; } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; #pragma comment(linker, /STACK:100000000 ) using namespace std; const int L = 350; const int B = 1000000; const int LB = 6; class Long { public: int m[L], l; int &operator[](int i) { return m[i]; } Long operator=(long long x) { for (l = 1, m[l - 1] = x % B, x /= B; x; m[l++] = x % B, x /= B) ; return *this; } Long operator=(int x) { for (l = 1, m[l - 1] = x % B, x /= B; x; m[l++] = x % B, x /= B) ; return *this; } Long operator=(char *s) { int i, j, n; for (n = 0; s[n] >= 0 && s[n] <= 9 ; n++) ; for (l = (n + LB - 1) / LB, i = 0; i < l; i++) for (m[i] = 0, j = 0; j < LB; j++) if (n - i * LB - LB + j >= 0) m[i] = m[i] * 10 + s[n - i * LB - LB + j] - 0 ; return *this; } bool inp() { char s[L * LB + 10]; if (scanf( %s , s) == EOF) return 0; else { *this = s; return 1; } } void out() { int i; char s[8]; for (sprintf(s, %%0%dd , LB), printf( %d , m[l - 1]), i = l - 2; i >= 0; printf(s, m[i]), i--) ; } }; bool operator<(Long x, Long y) { int i; if (x.l != y.l) return x.l < y.l; for (i = x.l - 1; i >= 0 && x[i] == y[i]; i--) ; return i >= 0 && x[i] < y[i]; } Long operator+(Long x, Long y) { int i; long long h; for (h = 0, i = 0; i < x.l || i < y.l || h; h += (i < x.l) * x[i] + (i < y.l) * y[i], x[i] = h % B, h /= B, i++) ; x.l = i; return x; } Long operator-(Long x, Long y) { int i; long long h; for (h = 0, i = 0; i < x.l; h += x[i] - (i < y.l) * y[i] + B, x[i] = h % B, h /= B, h--, i++) ; for (; x.l > 1 && !x[x.l - 1]; x.l--) ; return x; } Long operator*(Long x, int y) { int i; long long h; for (h = 0, i = 0; i < x.l || h; h += (i < x.l) * (long long)x[i] * y, x[i] = h % B, h /= B, i++) ; for (x.l = i; x.l > 1 && !x[x.l - 1]; x.l--) ; return x; } Long operator/(Long x, int y) { int i; long long h; for (h = 0, i = x.l - 1; i >= 0; h = h * B + x[i], x[i] = h / y, h %= y, i--) ; for (; x.l > 1 && !x[x.l - 1]; x.l--) ; return x; } int operator%(Long x, int y) { int i; long long h; for (h = 0, i = x.l - 1; i >= 0; h = h * B + x[i], h %= y, i--) ; return h; } Long operator*(Long x, Long y) { int i, j; long long h; Long z; for (h = 0, z.l = x.l + y.l, i = 0; i < z.l; z[i] = h % B, h /= B, i++) for (j = i < x.l - 1 ? i : x.l - 1; j >= 0 && i - j < y.l; h += (long long)x[j] * y[i - j], j--) ; for (; z.l > 1 && !z[z.l - 1]; z.l--) ; return z; } Long operator/(Long x, Long y) { int i; Long h, t; if (y.l == 1) return x / y[0]; for (h = 0, i = x.l - 1; i >= 0; h = h - y * x[i], i--) for (t = x[i], h = h * B + t, x[i] = ((h.l > y.l) * ((long long)h[h.l - 1] * B * B + (long long)h[h.l - 2] * B + h[h.l - 3]) + (h.l == y.l) * ((long long)h[h.l - 1] * B + h[h.l - 2])) / ((long long)y[y.l - 1] * B + y[y.l - 2]); x[i] && h < y * x[i]; x[i]--) ; for (; x.l > 1 && !x[x.l - 1]; x.l--) ; return x; } Long operator%(Long x, Long y) { int i; Long h, t; if (y.l == 1) return h = x % y[0]; for (h = 0, i = x.l - 1; i >= 0; h = h - y * x[i], i--) for (t = x[i], h = h * B + t, x[i] = ((h.l > y.l) * ((long long)h[h.l - 1] * B * B + (long long)h[h.l - 2] * B + h[h.l - 3]) + (h.l == y.l) * ((long long)h[h.l - 1] * B + h[h.l - 2])) / ((long long)y[y.l - 1] * B + y[y.l - 2]); x[i] && h < y * x[i]; x[i]--) ; return h; } const int maxN = 4000; const long long P = 1000000007LL; int digits[maxN], n; long long d[2][maxN][2][2]; int p, a; void set0(long long d[maxN][2][2]) { for (int i = 0; i < maxN; ++i) { for (int j = 0; j < 2; ++j) { for (int k = 0; k < 2; ++k) { d[i][j][k] = 0; } } } } int w[10][2][2]; int sw[10][2][2]; int tw[2][2]; void add(long long &x, long long value) { x = (x + value) % P; } void precalc(int p) { for (int i = 0; i < p; ++i) { for (int j = 0; j < p; ++j) { for (int carry = 0; carry < 2; ++carry) { ++w[(i + j + carry) % p][carry][(i + j + carry) / p]; for (int k = (i + j + carry) % p; k < p; ++k) { ++sw[k][carry][(i + j + carry) / p]; } ++tw[carry][(i + j + carry) / p]; } } } } long long getWays(long long s) { if (s < p) { return s + 1; } if (s > p + p - 2) { return 0; } return p - (s - (p - 1)); } long long getWaysUpTo(long long s) { if (s < 0) { return 0; } if (s < p) { return (s + 1LL) * (s + 2LL) / 2LL; } if (s > p + p - 2) { s = p + p - 2; } return (s + 2) * ((long long)(p + p) - s - 1) / 2LL + (s - p + 1) * p; } long long getWays(long long l, long long r) { return getWaysUpTo(r) - getWaysUpTo(l - 1); } int getTotalWays(int carried, int carry) { return getWays(p * carry - carried, p * (carry + 1) - 1 - carried) % P; } int getWays(int digit, int carried, int carry) { return getWays(p * carry + digit - carried) % P; } int getWaysUpTo(int digit, int carried, int carry) { return getWays(p * carry - carried, p * carry + digit - carried) % P; } void solve() { int u = 0, v = 1; set0(d[u]); d[u][0][0][0] = 1; int tw00 = getTotalWays(0, 0); int tw01 = getTotalWays(0, 1); int tw10 = getTotalWays(1, 0); int tw11 = getTotalWays(1, 1); for (int len = 0; len < n; ++len, swap(u, v)) { set0(d[v]); int dg = digits[len]; int dg00 = getWays(dg, 0, 0); int dg01 = getWays(dg, 0, 1); int dg10 = getWays(dg, 1, 0); int dg11 = getWays(dg, 1, 1); int pg00 = getWaysUpTo(dg - 1, 0, 0); int pg01 = getWaysUpTo(dg - 1, 0, 1); int pg10 = getWaysUpTo(dg - 1, 1, 0); int pg11 = getWaysUpTo(dg - 1, 1, 1); for (int tot = 0; tot <= len; ++tot) { add(d[v][tot][1][0], d[u][tot][1][0] * tw00); add(d[v][tot][1][1], d[u][tot][1][0] * tw10); add(d[v][tot + 1][1][0], d[u][tot][1][1] * tw01); add(d[v][tot + 1][1][1], d[u][tot][1][1] * tw11); add(d[v][tot][0][0], d[u][tot][0][0] * dg00); add(d[v][tot][0][1], d[u][tot][0][0] * dg10); add(d[v][tot + 1][0][0], d[u][tot][0][1] * dg01); add(d[v][tot + 1][0][1], d[u][tot][0][1] * dg11); if (dg > 0) { add(d[v][tot][1][0], d[u][tot][0][0] * pg00); add(d[v][tot][1][1], d[u][tot][0][0] * pg10); add(d[v][tot + 1][1][0], d[u][tot][0][1] * pg01); add(d[v][tot + 1][1][1], d[u][tot][0][1] * pg11); } } } long long res = 0; for (int i = a; i <= n; ++i) { add(res, d[u][i][0][0] + d[u][i][1][0]); } printf( %d n , (int)(res % P)); } int main() { scanf( %d%d , &p, &a); Long A; A.inp(); Long zero; zero = 0; n = 0; while (zero < A) { digits[n++] = (A % p); A = (A / p); } reverse(digits, digits + n); solve(); return 0; }
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/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
test tt();
defparam foo = 3; /* This should generate a warning. */
defparam tt.foo = 4;
endmodule // main
module test;
parameter foo = 10;
reg [foo-1:0] bar;
initial begin
if ($bits(bar) != 4) begin
$display("FAILED -- $bits(bar) = %d", $bits(bar));
$finish;
end
$display("PASSED");
end
endmodule // test
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#include <bits/stdc++.h> using namespace std; const int N = 3e3 + 10; vector<pair<int, int> > v[N]; int ps[N], mx[N], cnt, wr; void dfs(int u, int par) { for (auto y : v[u]) { if (y.first == par) continue; ps[y.first] = ps[u]; if (y.second == 1) ps[y.first]++; else { wr++; ps[y.first]--; } mx[y.first] = max(mx[u], ps[y.first]); cnt = min(cnt, ps[y.first] - mx[y.first]); dfs(y.first, u); } } int main() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; v[a].push_back(make_pair(b, 1)); v[b].push_back(make_pair(a, 2)); } int ans = n - 1; for (int i = 0; i < n; i++) { fill(mx, mx + N, 0); fill(ps, ps + N, 0); cnt = 0; wr = 0; dfs(i, -1); ans = min(ans, wr + cnt); } cout << ans; return 0; }
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:30:28 11/17/2015
// Design Name: I2C_Top
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/I2C_Module/top_tst.v
// Project Name: I2C_Module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: I2C_Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_tst;
// Inputs
reg clk;
reg clk_frame;
reg rst;
reg en;
reg start;
reg stop;
reg ack_o;
reg rw;
reg [7:0] out_byte;
// Outputs
wire busy;
wire err;
wire [7:0] in_byte;
wire SCL;
// Bidirs
wire SDA;
reg SDA_in, SDA_out, SDA_oen;
assign SDA = SDA_oen? 1'bz : SDA_out;
// Instantiate the Unit Under Test (UUT)
I2C_Top uut (
.clk(clk),
.clk_frame(clk_frame),
.rst(rst),
.en(en),
.start(start),
.stop(stop),
.ack_o(ack_o),
.rw(rw),
.out_byte(out_byte),
.busy(busy),
.err(err),
.in_byte(in_byte),
.SCL(SCL),
.SDA(SDA)
);
initial begin
// Initialize Inputs
clk = 0;
clk_frame = 0;
rst = 1;
en = 0;
start = 0;
stop = 0;
ack_o = 1;
rw = 0;
out_byte = 0;
SDA_oen = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
out_byte = 8'hAA;
#115;
en = 1;
start = 1;
stop = 0;
#150;
en = 0;
start = 0;
out_byte = 8'h00;
#3750;
SDA_oen = 0;
SDA_out = 0;
#355;
SDA_out = 1;
en = 1;
rw = 0;
#3625;
SDA_oen = 1;
SDA_out = 0;
end
always #5 clk = ~clk;
always #55 clk_frame = ~clk_frame;
endmodule
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#include <bits/stdc++.h> using namespace std; struct point { long long x, y, z; point() {} point(long long a, long long b, long long c) : x(a), y(b), z(c) {} double operator()(point y) { return sqrt((this->x - y.x) * (this->x - y.x) + (this->y - y.y) * (this->y - y.y) + (this->z - y.z) * (this->z - y.z)); } }; vector<pair<int, int>> ans; int taken[10005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; long long a, b, c; point arr[n]; for (int i = 0; i < n; i++) { cin >> a >> b >> c; point p(a, b, c); arr[i] = p; } for (int i = 0; i < n; i++) { double minimum = 1e11; int correct; if (taken[i]) continue; for (int j = 0; j < n; j++) { if (i == j || taken[j]) continue; double x = arr[i](arr[j]); if (x < minimum) { minimum = x; correct = j; } } taken[correct] = 1; taken[i] = 1; ans.push_back({i, correct}); } for (int i = 0; i < n / 2; i++) cout << ans[i].first + 1 << << ans[i].second + 1 << n ; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A21BO_PP_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_PP_SYMBOL_V
|
`include "sixbitadd.v"
`include "sixbitsub.v"
`include "sixbitmul.v"
`include "sixbitdiv.v"
`include "sixbitpow.v"
//`include "sixbitlog.v"
`include "sixbitfactorial.v"
`include "sixbitexp.v"
`include "sixbitsin.v"
`include "sixbitcos.v"
//`include "sixbittan.v"
`include "multiplexer.v"
module calculator (data_in1, data_in2, operator, data_out, error);
input[5:0] data_in1;
input[5:0] data_in2;
input[3:0] operator;
output[5:0] data_out;
output error;
wire[5:0] sum;
wire[5:0] diff;
wire[5:0] prod;
wire[5:0] quotient;
wire[5:0] remainder;
wire[5:0] power;
wire[5:0] log;
wire[5:0] factorial;
wire[5:0] exp;
wire[5:0] sin;
wire[5:0] cos;
wire[5:0] tan;
wire[12:0] overflow;
sixbitadd add1 (data_in1, data_in2, sum, overflow[0]);
sixbitsub sub1 (data_in1, data_in2, diff, overflow[1]);
sixbitmul mul1 (data_in1, data_in2, prod, overflow[2]);
sixbitdiv div1 (data_in1, data_in2, quotient, remainder, overflow[3]);
sixbitpow pow1 (data_in1, data_in2, power, overflow[5]);
//overflow[6], log
sixbitfactorial fact1 (data_in1, factorial, overflow[7]);
sixbitexp exp1 (data_in1, exp, overflow[8]);
sixbitsin sin1 (data_in1, sin, overflow[9]);
sixbitcos cos1 (data_in1, cos, overflow[10]);
sixbittan tan1 (data_in1, tan, overflow[11]);
assign overflow[4] = overflow[3];
multiplexer mux1 (sum, diff, prod, quotient, remainder, power, log, factorial, exp, sin, cos, tan, 0, 0, 0, 0, operator, data_out);
assign error = overflow[operator];
endmodule
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#include <bits/stdc++.h> const double pi = acos(-1.0); using namespace std; inline long long MAX2(long long a, long long b) { return (a) > (b) ? (a) : (b); } inline long long MAX3(long long a, long long b, long long c) { return (a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)); } inline long long MIN2(long long a, long long b) { return (a) < (b) ? (a) : (b); } inline long long MIN3(long long a, long long b, long long c) { return (a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c)); } int mod = 1e9 + 7; int64_t extGcd(int64_t a, int64_t b, int64_t& x, int64_t& y) { if (!a) { x = 0; y = 1; return b; } int64_t x1, y1; int64_t d = extGcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } inline long long addmod(long long a, long long b) { a = a % mod + b % mod; if (a > mod) a %= mod; return a; } inline long long submod(long long a, long long b) { a = a % mod - b % mod; if (a < 0) a += mod; return a; } inline long long mulmod(long long a, long long b) { return (a % mod * b % mod) % mod; } int dx[] = {1, 1, 0, -1, -1, -1, 0, 1}; int dy[] = {0, 1, 1, 1, 0, -1, -1, -1}; inline long long exp(long long a, long long b) { if (a == 0) return 0ll; long long r = 1LL; while (b > 0) { if (b & 1) { r = r * (a % mod); r = (r + mod) % mod; } b /= 2; a = (a % mod) * (a % mod); a = (a + mod) % mod; } return (r + mod) % mod; } long long gcd(long long a, long long b) { if (b == 0) return a; if (a == 0) return b; return gcd(b, a % b); } unsigned long int setbits(long long n) { unsigned long int count = 0; while (n) { n &= (n - 1); count++; } return count; } int main() { if (fopen( input.txt , r )) freopen( input.txt , r , stdin), freopen( output.txt , w , stdout); ; int t; cin >> t; while (t--) { int n, k, z; cin >> n >> k >> z; long long a[n]; long long pre[n + 1]; pre[0] = 0; for (long long i = (long long)(0); i < (long long)(n); i++) { cin >> a[i]; pre[i + 1] = pre[i] + a[i]; } long long ans = 0; long long curr_sum = a[0]; for (int i = 1; i <= min(k, n - 1); i++) { curr_sum += a[i]; long long prev = a[i - 1]; long long last = a[i]; int rem = (k - i); int resz = z; long long res = curr_sum; int nxt = i; while (resz > 0 and rem > 0) { if (rem <= 0) { nxt = i; break; } res += prev; resz--; rem--; if (rem <= 0) { nxt = i - 1; break; } res += last; rem--; } res += pre[nxt + rem + 1] - pre[nxt + 1]; ans = MAX2(ans, res); } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; double p; cin >> n >> p >> t; vector<vector<double> > dp(2010, vector<double>(2010, 0)); vector<vector<double> > now(2010, vector<double>(2010, 0)); dp[0][0] = 1; for (int i = 0; i < t; i++) { for (int j = 0; j < n + 1; j++) { if (j == n) { dp[i + 1][j] += dp[i][j]; continue; } dp[i + 1][j + 1] += dp[i][j] * p; dp[i + 1][j] += dp[i][j] * (1 - p); } } double fa = 0; for (int i = 0; i < n + 1; i++) fa += dp[t][i] * i; cout << setprecision(20) << fa; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, m, har[27]; string s; int sum[200005][27]; int main() { cin >> t; while (t--) { cin >> n >> m; cin >> s; for (int i = 0; i <= 25; i++) har[i] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < 26; j++) sum[i][j] = 0; } for (int i = 0; i < n; i++) { if (i != 0) { for (int j = 0; j <= 25; j++) { sum[i][j] = sum[i - 1][j]; } } sum[i][s[i] - a ]++; } int l = 0; for (int i = 0; i < m; i++) { cin >> l; for (int j = 0; j < 26; j++) { har[j] += sum[l - 1][j]; } } for (int j = 0; j < 26; j++) { har[j] += sum[n - 1][j]; } for (int i = 0; i < 26; i++) { cout << har[i] << ; } cout << endl; } }
|
// file: pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____80.000______0.000______50.0______196.659____144.334
// CLK_OUT2____80.000______0.000______50.0______196.659____144.334
// CLK_OUT3____80.000______0.000______50.0______196.659____144.334
// CLK_OUT4____50.000______0.000______50.0______222.587____144.334
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________50.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=20.0,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (16),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (10),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (10),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (16),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (20.0),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (LOCKED),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISO1N_BEHAVIORAL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a[100005], i, j, m, n, ans = 0, pos = 1; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 3; i <= n;) { if (a[i] == a[i - 1] + a[i - 2]) { while (a[i] == a[i - 1] + a[i - 2] && i <= n) { i++; } ans = max(i - pos, ans); pos = i - 2; } else i++, pos = i - 2; } cout << max(ans, min(n, 2)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); int n, p, q; cin >> n; vector<pair<int, int>> v1; int x1, x2; for (size_t i = 0; i < n; i++) { cin >> x1 >> x2; v1.push_back(make_pair(x1, x2)); } bool s = true; sort(v1.begin(), v1.end()); for (size_t i = 0; i < n; i++) { if (v1[i].second > v1[i + 1].second && i + 1 < n) { s = false; break; } } if (s == true) { cout << Poor Alex ; } else { cout << Happy Alex ; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file instructionMemory.v when simulating
// the core, instructionMemory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module instructionMemory(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [31 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(32),
.C_ADDRB_WIDTH(32),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("instructionMemory.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; class Node { public: int vol, l, r, tot; Node(int val) { tot = vol = val; l = r = 0; } Node() { tot = vol = 0; l = r = 0; } }; int main() { int H, q; cin >> H >> q; vector<Node> tree(1); string s; int v, val; for (int query = 0; query < q; ++query) { cin >> s; if (s[0] == a ) { cin >> v >> val; vector<int> vbit; while (v) { vbit.push_back(v % 2); v /= 2; } int it = 0; for (int h = (int)vbit.size() - 2; h >= 0; --h) { if (!tree[it].r) { tree[it].l = tree.size(); tree[it].r = tree.size() + 1; tree.resize(tree.size() + 2); } tree[it].tot += val; int nextit = tree[it].l; if (vbit[h]) { nextit = tree[it].r; } it = nextit; } tree[it].vol += val; tree[it].tot += val; } else { double res = 0.; int it = 0; int ma = 0; int h = H; for (; h > 0 && tree[it].r; --h) { int nextit = tree[it].r; if (tree[it].vol + tree[tree[it].r].tot > tree[tree[it].l].tot) { res += max(ma, tree[it].vol + tree[tree[it].r].tot) * (double)(1 << (h - 1)); ma = max(ma, tree[it].vol + tree[tree[it].l].tot); } else { res += max(ma, tree[it].vol + tree[tree[it].l].tot) * (double)(1 << (h - 1)); ma = max(ma, tree[it].vol + tree[tree[it].r].tot); nextit = tree[it].l; } it = nextit; } res += max(ma, tree[it].vol) * (double)(1 << h); printf( %lf n , res / (1 << (H))); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T Abs(const T& x) { return x < 0 ? -x : x; } template <class T> inline T Sqr(const T& x) { return x * x; } const int maxn = 110; const int maxk = 210; double a[maxn][maxn][maxk]; int n, k; int Get(int l, int r, int pos) { if (pos < l || pos > r) { return pos; } else { return l + r - pos; } } int main() { ios_base::sync_with_stdio(false); cin >> n >> k; vector<int> p(n); for (int i = 0; i < n; ++i) { cin >> p[i]; } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { a[i][j][0] = (i < j ? 1.0 : 0.0); } } double cnt = 0; for (int i = 0; i < n; ++i) { for (int j = i; j < n; ++j) { cnt += 1.0; } } for (int iter = 1; iter <= k; ++iter) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { a[i][j][iter] = 0; for (int l = 0; l < n; ++l) { for (int r = l; r < n; ++r) { int i1 = Get(l, r, i); int j1 = Get(l, r, j); a[i][j][iter] += 1 / cnt * a[i1][j1][iter - 1]; } } } } } double ans = 0.0; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (p[i] < p[j]) { ans += a[j][i][k]; } else { ans += a[i][j][k]; } } } printf( %.12lf n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } int p[100009]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) p[i] = i; if (n & 1) { for (int i = n; i > 1; i -= 2) swap(p[i], p[i - 1]); } else { for (int i = 1; i < n; i += 2) swap(p[i], p[i + 1]); } for (int i = 1; i <= n; i++) printf( %d , p[i]); puts( ); return 0; }
|
`timescale 1 ns / 1 ps
module axis_red_pitaya_adc #
(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
output wire adc_clk,
// ADC signals
output wire adc_csn,
input wire adc_clk_p,
input wire adc_clk_n,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_a,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_b,
// Master side
output wire m_axis_tvalid,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata
);
localparam PADDING_WIDTH = AXIS_TDATA_WIDTH/2 - ADC_DATA_WIDTH;
reg [ADC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [ADC_DATA_WIDTH-1:0] int_dat_b_reg;
wire int_clk;
IBUFGDS adc_clk_inst (.I(adc_clk_p), .IB(adc_clk_n), .O(int_clk));
always @(posedge int_clk)
begin
int_dat_a_reg <= adc_dat_a;
int_dat_b_reg <= adc_dat_b;
end
assign adc_clk = int_clk;
assign adc_csn = 1'b1;
assign m_axis_tvalid = 1'b1;
assign m_axis_tdata = {
{(PADDING_WIDTH+1){int_dat_b_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_b_reg[ADC_DATA_WIDTH-2:0],
{(PADDING_WIDTH+1){int_dat_a_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_a_reg[ADC_DATA_WIDTH-2:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int x; scanf( %d , &x); bool found = 0; for (int n = 1; n <= 200000; n++) { int lo = 1, hi = n; bool done = 0; while (lo <= hi) { int m = lo + hi >> 1; long long val = 1ll * n * n - 1ll * (n / m) * (n / m); if (val == x) { done = 1; printf( %d %d n , n, m); break; } if (val < x) lo = m + 1; if (val > x) hi = m - 1; } if (done) { found = 1; break; } } if (!found) puts( -1 ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int min(int a, int b) { return a < b ? a : b; } long long max(long long a, long long b) { return a > b ? a : b; } int read() { int x = 0, w = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 0 , ch = getchar(); return x * w; } void bmax(long long &t1, long long t2) { t1 = max(t1, t2); } void bmin(long long &t1, long long t2) { t1 = min(t1, t2); } const int N = 2e5 + 10; const long long INF = 1e16; struct Node { long long mx, mn, ans; Node(long long _mx = -INF, long long _mn = INF, long long _ans = -INF) : mx(_mx), mn(_mn), ans(_ans) {} Node operator+(const Node &tmp) const { Node res = Node(mx, mn); res.ans = max(tmp.mx - mn, max(ans, tmp.ans)); bmax(res.mx, tmp.mx); bmin(res.mn, tmp.mn); return res; } }; int n, m; long long h[N], s[N]; struct SegmentTree { Node tr[N << 2]; void Build(int pos, int l, int r) { if (l == r) { tr[pos].mx = h[l] + s[l - 1]; tr[pos].mn = s[l - 1] - h[l]; tr[pos].ans = -INF; return; } int mid = (l + r) >> 1; Build(pos << 1, l, mid); Build(pos << 1 | 1, mid + 1, r); tr[pos] = tr[pos << 1] + tr[pos << 1 | 1]; } Node Query(int pos, int L, int R, int l, int r) { if (R < l || L > r) return Node(); if (l <= L && R <= r) return tr[pos]; int mid = (L + R) >> 1; Node res1 = Query(pos << 1, L, mid, l, r), res2 = Query(pos << 1 | 1, mid + 1, R, l, r); Node res = res1 + res2; return res; } } Tr; int main() { n = read(); m = read(); s[0] = 0; for (int i = 1; i <= n; i++) s[i] = read(), s[i + n] = s[i]; for (int i = 1; i <= n; i++) h[i] = read() * 2, h[n + i] = h[i]; for (int i = 1; i <= 2 * n; i++) s[i] += s[i - 1]; Tr.Build(1, 1, 2 * n); while (m--) { int l = read(), r = read(); Node ans; if (l <= r) ans = Tr.Query(1, 1, 2 * n, r + 1, l + n - 1); else ans = Tr.Query(1, 1, 2 * n, r + 1, l - 1); printf( %lld n , ans.ans); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
logic [3:0] array_oned;
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
// IEEE says '{} allowed only on assignments, not !=, ==.
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if (array_simp !== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if (array_simp !== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
end
//====================
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size
localparam NO = 11; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_bg <= '0;
else if (cnt[30:2]== 1) array_bg <= '0;
else if (cnt[30:2]== 2) array_bg <= '0;
else if (cnt[30:2]== 3) array_bg <= '0;
else if (cnt[30:2]== 4) array_bg <= '0;
else if (cnt[30:2]== 5) array_bg <= '0;
else if (cnt[30:2]== 6) array_bg <= '0;
else if (cnt[30:2]== 7) array_bg <= '0;
else if (cnt[30:2]== 8) array_bg <= '0;
else if (cnt[30:2]== 9) array_bg <= '0;
else if (cnt[30:2]==10) array_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_bg <= '{default:13};
else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13};
else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_lt <= '0;
else if (cnt[30:2]== 1) array_lt <= '0;
else if (cnt[30:2]== 2) array_lt <= '0;
else if (cnt[30:2]== 3) array_lt <= '0;
else if (cnt[30:2]== 4) array_lt <= '0;
else if (cnt[30:2]== 5) array_lt <= '0;
else if (cnt[30:2]== 6) array_lt <= '0;
else if (cnt[30:2]== 7) array_lt <= '0;
else if (cnt[30:2]== 8) array_lt <= '0;
else if (cnt[30:2]== 9) array_lt <= '0;
else if (cnt[30:2]==10) array_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_lt <= '{default:13};
else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int diri[4] = {-1, 0, 1, 0}; const int dirj[4] = {0, 1, 0, -1}; int A, B; int va[110000], vb[110000]; bool esquerra(int a, int b) { if (b < 0) return false; if (a == 0) return true; return va[a - 1] < vb[b]; } bool dreta(int a, int b) { if (b + 1 >= B) return false; if (a + 1 == A) return true; return va[a + 1] > vb[b + 1]; } int main() { int spam; cin >> A >> B >> spam >> spam; for (int i = 0; i < int(A); ++i) cin >> va[i]; for (int i = 0; i < int(B); ++i) cin >> vb[i]; vector<int> dist(B, -1); int res = A; int b = -1; for (int a = 0; a < A; ++a) { while (b + 1 < B and vb[b + 1] <= va[a]) ++b; int d = INF; if (0 <= b and b < B) d = min(d, abs(va[a] - vb[b])); if (b + 1 < B) d = min(d, abs(va[a] - vb[b + 1])); if (esquerra(a, b) and d == abs(va[a] - vb[b])) { if (dist[b] == -1 or dist[b] == d) { dist[b] = d; --res; continue; } } if (dreta(a, b) and d == abs(va[a] - vb[b + 1])) { dist[b + 1] = d; --res; continue; } } cout << res << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_2_V
`define SKY130_FD_SC_MS__O2BB2A_2_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110; const int INF = 1e9; int _w; int n, a[MAXN], b[MAXN]; namespace MCMF { const int MAXV = 1000000; const int MAXE = 1000000; struct Edge { int u, v, c, f, w; Edge() {} Edge(int u, int v, int c, int f, int w) : u(u), v(v), c(c), f(f), w(w) {} }; int n, m, s, t; int head[MAXV], nxt[MAXE << 1]; Edge edge[MAXE << 1]; void init(int nn) { n = nn, m = 0; for (int i = 1; i <= n; ++i) head[i] = -1; } void adde(int u, int v, int c, int w) { edge[m] = Edge(u, v, c, 0, w); nxt[m] = head[u], head[u] = m++; edge[m] = Edge(v, u, 0, 0, -w); nxt[m] = head[v], head[v] = m++; } queue<int> q; int inq[MAXV], dis[MAXV], res[MAXV], pre[MAXV]; bool spfa() { for (int i = 1; i <= n; ++i) inq[i] = 0, dis[i] = -INF; q.push(s), inq[s] = 1, dis[s] = 0, res[s] = INF; while (!q.empty()) { int u = q.front(); q.pop(); inq[u] = 0; for (int i = head[u]; ~i; i = nxt[i]) { Edge &e = edge[i]; if (e.c > e.f && dis[e.v] < dis[u] + e.w) { dis[e.v] = dis[u] + e.w; res[e.v] = min(res[u], e.c - e.f); pre[e.v] = i; if (!inq[e.v]) { inq[e.v] = 1; q.push(e.v); } } } } return dis[t] != -INF; } void augment() { int u = t, f = res[t]; while (u != s) { int i = pre[u]; edge[i].f += f; edge[i ^ 1].f -= f; u = edge[i].u; } } int solve(int ss, int tt) { s = ss, t = tt; int ans = 0, flow = 0; while (spfa()) { augment(); ans += dis[t] * res[t]; flow += res[t]; } return ans; } } // namespace MCMF int id1[27], id2[27][MAXN], id3[MAXN], s, t, nid; void solve() { for (int i = 1; i <= 26; ++i) id1[i] = ++nid; for (int i = 1; i <= 26; ++i) for (int j = 1; j <= n / 2; ++j) id2[i][j] = id2[i][n - j + 1] = ++nid; for (int i = 1; i <= n; ++i) id3[i] = ++nid; s = ++nid, t = ++nid; MCMF::init(nid); for (int i = 1; i <= n; ++i) MCMF::adde(s, id1[a[i]], 1, 0); for (int i = 1; i <= 26; ++i) for (int j = 1; j <= n / 2; ++j) MCMF::adde(id1[i], id2[i][j], 1, 0); for (int i = 1; i <= 26; ++i) for (int j = 1; j <= n; ++j) MCMF::adde(id2[i][j], id3[j], 1, a[j] == i ? b[j] : 0); for (int i = 1; i <= n; ++i) MCMF::adde(id3[i], t, 1, 0); printf( %d n , MCMF::solve(s, t)); } int main() { _w = scanf( %d , &n); for (int i = 1; i <= n; ++i) { char c; _w = scanf( %c , &c); a[i] = c - a + 1; } for (int i = 1; i <= n; ++i) _w = scanf( %d , b + i); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_4_V
`define SKY130_FD_SC_LP__EINVP_4_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_4 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_4 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:25:19 11/02/2015
// Design Name:
// Module Name: MainBoard
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MainBoard(
`ifndef SIMULATION
//clk
input clk,
input clk_50M,
//for debug
input[4:0] RegNum,
`endif
output[31:0] RegData,
output[31:0] ProgramCounter,
output[31:0] ExtraOut,
output[31:0] IR,
//vga
output hsync, //ÐÐͬ²½ÐźÅ
output vsync, //³¡Í¬²½ÐźÅ
output vga_r,
output vga_g,
output vga_b,
`ifndef SIMULATION
//KeyBoard
input PS2C,
input PS2D,
`endif
//Serial Port
input RxD,
output TxD
);
`ifdef SIMULATION
reg clk;
reg clk_50M;
reg[4:0] RegNum;
reg PS2C;
reg PS2D;
initial begin
// Initialize Inputs
RegNum = 8;
clk = 0;
clk_50M = 0;
clk = 0;
PS2C = 0;
PS2D = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always#10 begin
clk_50M = ~clk_50M;
end
always#10 begin
clk = ~clk;
end
always #200 begin
PS2C = ~PS2C;
end
always #330 begin
PS2D = ~PS2D;
end
`endif
//Multicycle CPU
reg[31:0] MemReadData;
reg MemOK;
initial begin
MemReadData <= 0;
MemOK <= 0;
end
wire OutINTE;
wire[31:0] OutCause;
wire[31:0] RequestedMemAddr;
wire RequestedMemWrite;
wire RequestedMemRead;
wire RequestedSaveHalf;
wire RequestedLoadHalf;
wire[31:0] RequestedMemWriteData;
wire InteAccept;
wire[31:0] MMCExtraOut;
MultiCycleCpu MCC (
//input
.clk(clk),
// .clk_50M(clk_50M),
.MemOK(MemOK),
.MemReadData(MemReadData),
.OutINTE(OutINTE),
.OutCause(OutCause),
//output
.MemAddr(RequestedMemAddr),
.MemWrite(RequestedMemWrite),
.MemRead(RequestedMemRead),
.SaveHalf(RequestedSaveHalf),
.LoadHalf(RequestedLoadHalf),
.MemWriteData(RequestedMemWriteData),
.InteAccept(InteAccept),
//for debug
.RegNum(RegNum),
.ProgramCounter(ProgramCounter),
.IR(IR),
.ExtraOut(MMCExtraOut),
.RegData(RegData)
);
reg[31:0] MemAddr;
reg MemWrite;
reg MemRead;
reg SaveHalf;
reg LoadHalf;
reg[31:0] MemWriteData;
reg[1:0] state;
initial begin
MemAddr <= 0;
MemWrite <= 0;
MemRead <= 0;
SaveHalf <= 0;
LoadHalf <= 0;
MemWriteData <= 0;
state <= 0;
end
assign ExtraOut = MemAddr;
//Block Memory
wire BlockMemChipSelect;
wire BlockMemOK;
wire[31:0] BlockMemReadData;
assign BlockMemChipSelect = (0 <= MemAddr) && (MemAddr < 16'h5000);
MemoryManagerUnit MMU (
.clk(clk),
.clk_50M(clk_50M),
.MemAddr(MemAddr[14:0]),
.MemWrite(MemWrite),
.MemRead(MemRead),
.SaveHalf(SaveHalf),
.LoadHalf(LoadHalf),
.MemWriteData(MemWriteData),
.ChipSelect(BlockMemChipSelect),
.MemReadData(BlockMemReadData),
.MemOK(BlockMemOK),
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
//VHDControler
wire VHDChipSelect;
wire VHDMemOK;
wire[31:0] VHDMemReadData;
assign VHDChipSelect = (MemAddr >= 32'h50FC) && (MemAddr < 32'h5200);
VHDControler vhd (
.clk(clk),
.RxD(RxD),
.TxD(TxD),
.VHDControlerAddr(MemAddr[8:0]), //[8:0]
.ChipSelect(VHDChipSelect),
.WriteData(MemWriteData), //[31:0]
.SaveHalf(SaveHalf),
.LoadHalf(LoadHalf),
.MemWrite(MemWrite),
.MemRead(MemRead),
.MemReadData(VHDMemReadData), //[31:0]
.MemOK(VHDMemOK)
);
wire TimerInte;
Timer t(
.clk(clk_50M),
.TimerInte(TimerInte)
);
//KeyBoard
wire[15:0] KeyBoardReadData;
wire KeyBoardChipSelect;
wire KeyBoardOK;
wire KeyBoardInte;
wire KeyBoardInteAccept;
assign KeyBoardChipSelect = (MemAddr==32'h5000);
assign KeyBoardOK = 1;
KeyBoardControler kbc (
.clk(clk_50M),
.PS2C(PS2C),
.PS2D(PS2D),
.InteAccept(KeyBoardInteAccept),
.scanCode(KeyBoardReadData),
.KeyBoardInte(KeyBoardInte)
);
assign OutINTE = KeyBoardInte | TimerInte;
assign OutCause= {32{KeyBoardInte}} & 32'h1 | {32{(~KeyBoardInte) & TimerInte}} & 32'h2;
assign KeyBoardInteAccept = InteAccept & KeyBoardInte;
always@(posedge clk) begin
case(state)
0: begin
if(RequestedMemRead | RequestedMemWrite) begin
state <= 1;
MemAddr <= RequestedMemAddr;
MemWrite <= RequestedMemWrite;
MemRead <= RequestedMemRead;
SaveHalf <= RequestedSaveHalf;
LoadHalf <= RequestedLoadHalf;
MemWriteData <= RequestedMemWriteData;
end
else begin
state <= 0;
end
end
1: begin
if( BlockMemOK & BlockMemChipSelect |
KeyBoardChipSelect & KeyBoardOK |
VHDChipSelect & VHDMemOK
) begin
state <= 2;
MemOK <= 1;
MemReadData <=
{32{BlockMemChipSelect}} & BlockMemReadData |
{32{KeyBoardChipSelect}} & {16'h0,KeyBoardReadData} |
{32{VHDChipSelect}} & VHDMemReadData ;
MemWrite <= 0;
MemRead <= 0;
end
end
2: begin
state <= 0;
MemOK <= 0;
end
default: begin
MemAddr <= 0;
MemWrite <= 0;
MemRead <= 0;
SaveHalf <= 0;
LoadHalf <= 0;
MemWriteData <= 0;
state <= 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 5; int n, m; bool used[MAXN]; set<int> graph[MAXN]; stack<int> path; vector<int> cycle; int fake; vector<pair<int, int> > edges; vector<pair<int, int> > answer; void EulerCycle(int x) { cycle.clear(); edges.clear(); path.push(x); while (path.empty() == false) { used[x] = true; if (graph[x].empty() == false) { path.push(*graph[x].begin()); int y = *graph[x].begin(); graph[x].erase(y); graph[y].erase(x); x = y; } else { cycle.push_back(x); path.pop(); if (path.empty() == false) x = path.top(); } } for (int i = 0; i < cycle.size() - 1; i++) { edges.push_back({cycle[i], cycle[i + 1]}); } } bool isFake(pair<int, int> x) { if (x.first == fake || x.second == fake) return true; return false; } void solve(int x) { EulerCycle(x); for (int i = 0; i < edges.size(); i++) { bool toDelete; if (isFake(edges[i]) == true) { continue; } if (i % 2 != 0) toDelete = true; else toDelete = false; if (i != 0 && isFake(edges[i - 1]) == true) toDelete = false; if (i == 0 && isFake(edges[edges.size() - 1]) == true) toDelete = false; if (i != edges.size() - 1 && isFake(edges[i + 1]) == true) toDelete = false; if (i == edges.size() - 1 && isFake(edges[0]) == true) toDelete = false; if (toDelete == false) { answer.push_back(edges[i]); } } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; graph[u].insert(v); graph[v].insert(u); } fake = -1; for (int i = 1; i <= n; i++) { if (graph[i].size() % 2 != 0) { fake = n + 1; graph[i].insert(fake); graph[fake].insert(i); } } for (int x = 1; x <= n + 1; x++) { if (used[x] == false) { solve(x); } } cout << answer.size() << n ; for (int i = 0; i < answer.size(); i++) { cout << answer[i].first << << answer[i].second << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, d, f; cin >> n; if (n % 3 == 2) d = n / 3 + 1; else d = n / 3; f = d / 12; d = d % 12; cout << f << << d << endl; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:26:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_1_stub.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mo = 1e9 + 7; int main() { long long a, b, n; while (cin >> a >> b) { n = b - 1; long long ans = 0; for (int k = 1; k <= a; ++k) { ans = (ans + (((((k * b) % mo) * ((n * (n + 1) / 2) % mo)) % mo + (n * (n + 1) / 2) % mo)) % mo) % mo; } cout << ans % mo << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; void __print(long long int x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename Th, typename V> void __print(const pair<Th, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename Th> void __print(const Th &x) { long long int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename Th, typename... V> void _print(Th t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void binary_rock() { string a; cin >> a; long long int m; cin >> m; long long int i, j, k, l; vector<long long int> b(m); for (i = 0; i < m; i++) cin >> b[i]; vector<long long int> fre(26); for (i = 0; i < 26; i++) fre[i] = 0; long long int n = a.size(); for (i = 0; i < n; i++) { fre[a[i] - a ]++; }; long long int pos = 25; string ans = ; long long int nikal = 0; for (i = 0; i < m; i++) ans.push_back(( - )); ; ; while (1) { long long int zero = 0; vector<long long int> id; for (i = 0; i < m; i++) { if (b[i] == 0) id.push_back(i); } zero = id.size(); while (1) { if (fre[pos] >= zero) break; else { pos--; } } for (i = 0; i < zero; i++) { ans[id[i]] = a + pos; }; for (i = 0; i < zero; i++) { long long int x = id[i]; for (j = 0; j < m; j++) { if (b[j] == 0) continue; b[j] -= abs(x - j); } }; for (i = 0; i < zero; i++) { b[id[i]] = -1; } nikal += zero; if (nikal >= m) break; pos--; } cout << ans << endl; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); clock_t t1 = clock(); long long int t = 1; cin >> t; while (t--) { binary_rock(); } clock_t t2 = clock(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_SYMBOL_V
/**
* sdfrtp_ov2: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp_ov2 (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using D = double; using uint = unsigned int; template <typename T> using pair2 = pair<T, T>; using pii = pair<int, int>; using pli = pair<ll, int>; using pll = pair<ll, ll>; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int maxn = 100005; vector<int> pos[maxn]; int n, bulls, cows; priority_queue<pair2<int>> freq; int a[maxn], b[maxn]; vector<pair2<int>> all; void solve() { scanf( %d%d%d , &n, &bulls, &cows); cows -= bulls; for (int i = 0; i < n + 1; i++) pos[i].clear(); for (int i = 0; i < n; i++) { scanf( %d , &b[i]); b[i]--; pos[b[i]].push_back(i); } for (int i = 0; i < n; i++) a[i] = -1; int missing_color = -1; while (!freq.empty()) freq.pop(); for (int i = 0; i < n + 1; i++) { if (pos[i].empty()) missing_color = i; freq.push({(int)pos[i].size(), i}); } assert(missing_color != -1); for (int i = 0; i < bulls; i++) { int color = freq.top().second; freq.pop(); a[pos[color].back()] = color; pos[color].pop_back(); freq.push({(int)pos[color].size(), color}); } all.clear(); int max_occ = freq.top().first; while (!freq.empty()) { int color = freq.top().second; freq.pop(); for (auto t : pos[color]) all.push_back({color, t}); } int max_cows = (int)all.size(); if (2 * max_occ > (int)all.size()) max_cows -= 2 * max_occ - (int)all.size(); if (cows > max_cows) { printf( NO n ); return; } int shift = (int)all.size() / 2; for (int i = 0; i < (int)all.size(); i++) { int j = (i + shift) % (int)all.size(); int color = all[j].first; if (all[i].first == all[j].first || cows == 0) color = missing_color; if (color != missing_color) cows--; a[all[i].second] = color; } printf( Yes n ); for (int i = 0; i < n; i++) printf( %d , a[i] + 1); printf( n ); } int main() { int NT; scanf( %d , &NT); for (int T = 0; T < NT; T++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int l, r, a; cin >> l >> r >> a; int total = 0; while (l > 0 && r > 0) { l--, r--, total += 2; } while (l > 0 && a > 0) { l--, a--, total += 2; } while (r > 0 && a > 0) { r--, a--, total += 2; } if (a > 0) if (a % 2 == 0) total += a; else total += a - 1; cout << total; return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) { return a; } return gcd(b, a % b); } int a[300005]; bool notprime[8000005]; map<int, int> prims; vector<int> primes; void factor(int num) { for (int i = 0; i < primes.size() && primes[i] * primes[i] <= num; i++) { if (num % primes[i] == 0) { prims[primes[i]]++; while (num % primes[i] == 0) { num /= primes[i]; } if (num == 1) { break; } } } if (num != 1) prims[num]++; } int main() { std::ios_base::sync_with_stdio(false); notprime[0] = true; notprime[1] = true; int i; for (i = 2; i * i <= 8000005; i++) { if (!notprime[i]) { primes.push_back(i); for (int j = i * i; j < 8000005; j += i) { notprime[j] = true; } } } for (; i < 8000005; i++) { if (!notprime[i]) primes.push_back(i); } int n; cin >> n; int commgcd; for (int i = 0; i < n; i++) { cin >> a[i]; if (i == 0) commgcd = a[i]; else commgcd = gcd(a[i], commgcd); } for (int i = 0; i < n; i++) { factor(a[i] / commgcd); } int maxprim = -1; for (auto par : prims) { if (par.second > maxprim) { maxprim = par.second; } } if (maxprim == -1) cout << -1 << endl; else cout << n - maxprim << endl; }
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
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// bsg_arb_round_robin
//
// generally prefer this arbiter instead of bsg_round_robin_arb
// if the interface works for you (eventually we would like to deprecate bsg_round_robin_arb
// as the interface is too complex)
//
// note: (| reqs_i) can be used to determine if something is available to route (i.e. v_o)
// bsg_encode_one_hot(grants_o) can be used to determine what item was selected
//
// compared to bsg_round_robin_arb this design is more scalable but uses more registers
//
// priority goes high-to-low, wrapping around
//
// todo: maybe use some hardcoded case statements to optimize small cases
//
//
`include "bsg_defines.v"
module bsg_arb_round_robin #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
, input [width_p-1:0] reqs_i // which items would like to go; OR this to get v_o equivalent
, output logic [width_p-1:0] grants_o // one hot, selected item
, input yumi_i // the user of the arbiter accepts the arb output, change MRU
);
if (width_p == 1)
begin: fi
assign grants_o = reqs_i;
end
else
begin: fi2
// the current start location is represented as a thermometer code
logic [width_p-1-1:0] thermocode_r, thermocode_n;
always_ff @(posedge clk_i)
if (reset_i)
thermocode_r <= '0; // initialize thermometer to all 0's
else
if (yumi_i)
thermocode_r <= thermocode_n;
// this is essentially implementing a cyclic scan
wire [width_p*2-1:0] scan_li = { 1'b0, thermocode_r & reqs_i[width_p-1-1:0], reqs_i };
wire [width_p*2-1:0] scan_lo;
// default is high-to-lo
bsg_scan #(.width_p(width_p*2)
,.or_p(1)
) scan
(
.i(scan_li)
,.o(scan_lo) // thermometer code of the next item
);
// finds the first 1
wire [width_p*2-1:0] edge_detect = ~(scan_lo >> 1) & scan_lo;
// collapse the cyclic scan
assign grants_o = edge_detect[width_p*2-1-:width_p] | edge_detect[width_p-1:0];
always_comb
begin
if (|scan_li[width_p*2-1-:width_p]) // no wrap around
thermocode_n = scan_lo[width_p*2-1-:width_p-1];
else // wrap around
thermocode_n = scan_lo[width_p-1:1];
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_arb_round_robin)
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#include <bits/stdc++.h> #define maxn 1086 using namespace std; typedef long long ll; int n, m; ll a[maxn][maxn]; ll sum[maxn], sum2[maxn]; map<ll, int> mp; int main(){ scanf( %d%d , &m, &n); for(int i = 1;i <= n;i++) for(int j = 1;j <= m;j++) scanf( %lld , &a[i][j]); for(int i = 1;i <= n;i++) for(int j = 1;j <= m;j++) sum[i] += a[i][j], sum2[i] += a[i][j] * a[i][j]; for(int i = 2;i <= n;i++) mp[sum[i] - sum[i - 1]]++; int mx = 0; ll d, val; for(map<ll, int>::iterator it = mp.begin();it != mp.end();++it){ if(it->second > mx) mx = it->second, d = it->first; } int x; for(int i = 2;i <= n;i++){ if(sum[i] - sum[i - 1] != d){ if(i == n) x = n, val = d - (sum[i] - sum[i - 1]); else if(sum[i + 1] - sum[i] != d) x = i, val = d - (sum[i] - sum[i - 1]); else x = 1, val = sum[i] - sum[i - 1] - d; break; } } ll d2; if(x > 3) d2 = (sum2[1] + sum2[3] - 2 * sum2[2]) / 2; else d2 = (sum2[n - 2] + sum2[n] - 2 * sum2[n - 1]) / 2; for(int i = 1;i <= m;i++){ if(x == 1){ if(sum2[x] - a[x][i] * a[x][i] + (a[x][i] + val) * (a[x][i] + val) + sum2[x + 2] - 2 * sum2[x + 1] == 2 * d2) return printf( %d %d , x - 1, a[x][i] + val), 0; }else if(x == n){ if(sum2[x - 2]+ sum2[x] - a[x][i] * a[x][i] + (a[x][i] + val) * (a[x][i] + val) - 2 * sum2[x - 1] == 2 * d2) return printf( %d %d , x - 1, a[x][i] + val), 0; }else{ if(sum2[x - 1] + sum2[x + 1] - 2 * (sum2[x] - a[x][i] * a[x][i] + (a[x][i] + val) * (a[x][i] + val)) == 2 * d2) return printf( %d %d , x - 1, a[x][i] + val), 0; } } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_TB_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_TB_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg LVPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LVPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LVPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 LVPWR = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 LVPWR = 1'b0;
#340 SLEEP_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SLEEP_B = 1'b1;
#540 LVPWR = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SLEEP_B = 1'bx;
#680 LVPWR = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .LVPWR(LVPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_TB_V
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#include <bits/stdc++.h> using namespace std; int main(){ int t,n,d; int a[110],b[110]; scanf( %d ,&t); while(t--){ scanf( %d%d ,&n,&d); int fir=200,sec=200; int fid,sid; int x[110]; int xid[110]; int c=0; for(int i=1;i<=n;i++){ scanf( %d ,&a[i]); if(a[i]<fir){ sec=fir;fir=a[i]; sid=fid;fid=i; } else if(a[i]<sec){sec=a[i];sid=i;} if(a[i]>d){ x[++c]=a[i]; xid[c]=i; } } if(fir>d||sec>d||(c>=1&&fir+sec>d))printf( NO n ); else printf( YES n ); } return 0; }
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// nios_dut_audio_in_dma.v
// This file was auto-generated from altera_msgdma_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_audio_in_dma (
output wire [25:0] mm_write_address, // mm_write.address
output wire mm_write_write, // .write
output wire [3:0] mm_write_byteenable, // .byteenable
output wire [31:0] mm_write_writedata, // .writedata
input wire mm_write_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_n_reset_n, // reset_n.reset_n
input wire [31:0] csr_writedata, // csr.writedata
input wire csr_write, // .write
input wire [3:0] csr_byteenable, // .byteenable
output wire [31:0] csr_readdata, // .readdata
input wire csr_read, // .read
input wire [2:0] csr_address, // .address
input wire descriptor_slave_write, // descriptor_slave.write
output wire descriptor_slave_waitrequest, // .waitrequest
input wire [127:0] descriptor_slave_writedata, // .writedata
input wire [15:0] descriptor_slave_byteenable, // .byteenable
output wire csr_irq_irq, // csr_irq.irq
input wire [31:0] st_sink_data, // st_sink.data
input wire st_sink_valid, // .valid
output wire st_sink_ready // .ready
);
wire dispatcher_internal_write_command_source_valid; // dispatcher_internal:src_write_master_valid -> write_mstr_internal:snk_command_valid
wire [255:0] dispatcher_internal_write_command_source_data; // dispatcher_internal:src_write_master_data -> write_mstr_internal:snk_command_data
wire dispatcher_internal_write_command_source_ready; // write_mstr_internal:snk_command_ready -> dispatcher_internal:src_write_master_ready
wire write_mstr_internal_response_source_valid; // write_mstr_internal:src_response_valid -> dispatcher_internal:snk_write_master_valid
wire [255:0] write_mstr_internal_response_source_data; // write_mstr_internal:src_response_data -> dispatcher_internal:snk_write_master_data
wire write_mstr_internal_response_source_ready; // dispatcher_internal:snk_write_master_ready -> write_mstr_internal:src_response_ready
dispatcher #(
.MODE (2),
.RESPONSE_PORT (2),
.DESCRIPTOR_INTERFACE (0),
.DESCRIPTOR_FIFO_DEPTH (8),
.ENHANCED_FEATURES (0),
.DESCRIPTOR_WIDTH (128),
.DESCRIPTOR_BYTEENABLE_WIDTH (16)
) dispatcher_internal (
.clk (clock_clk), // clock.clk
.reset (~reset_n_reset_n), // clock_reset.reset
.csr_writedata (csr_writedata), // CSR.writedata
.csr_write (csr_write), // .write
.csr_byteenable (csr_byteenable), // .byteenable
.csr_readdata (csr_readdata), // .readdata
.csr_read (csr_read), // .read
.csr_address (csr_address), // .address
.descriptor_write (descriptor_slave_write), // Descriptor_Slave.write
.descriptor_waitrequest (descriptor_slave_waitrequest), // .waitrequest
.descriptor_writedata (descriptor_slave_writedata), // .writedata
.descriptor_byteenable (descriptor_slave_byteenable), // .byteenable
.src_write_master_data (dispatcher_internal_write_command_source_data), // Write_Command_Source.data
.src_write_master_valid (dispatcher_internal_write_command_source_valid), // .valid
.src_write_master_ready (dispatcher_internal_write_command_source_ready), // .ready
.snk_write_master_data (write_mstr_internal_response_source_data), // Write_Response_Sink.data
.snk_write_master_valid (write_mstr_internal_response_source_valid), // .valid
.snk_write_master_ready (write_mstr_internal_response_source_ready), // .ready
.csr_irq (csr_irq_irq), // csr_irq.irq
.src_response_data (), // (terminated)
.src_response_valid (), // (terminated)
.src_response_ready (1'b0), // (terminated)
.snk_descriptor_data (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_descriptor_valid (1'b0), // (terminated)
.snk_descriptor_ready (), // (terminated)
.mm_response_waitrequest (), // (terminated)
.mm_response_byteenable (4'b0000), // (terminated)
.mm_response_address (1'b0), // (terminated)
.mm_response_readdata (), // (terminated)
.mm_response_read (1'b0), // (terminated)
.src_read_master_data (), // (terminated)
.src_read_master_valid (), // (terminated)
.src_read_master_ready (1'b0), // (terminated)
.snk_read_master_data (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.snk_read_master_valid (1'b0), // (terminated)
.snk_read_master_ready () // (terminated)
);
write_master #(
.DATA_WIDTH (32),
.LENGTH_WIDTH (21),
.FIFO_DEPTH (256),
.STRIDE_ENABLE (0),
.BURST_ENABLE (0),
.PACKET_ENABLE (0),
.ERROR_ENABLE (0),
.ERROR_WIDTH (8),
.BYTE_ENABLE_WIDTH (4),
.BYTE_ENABLE_WIDTH_LOG2 (2),
.ADDRESS_WIDTH (26),
.FIFO_DEPTH_LOG2 (8),
.SYMBOL_WIDTH (8),
.NUMBER_OF_SYMBOLS (4),
.NUMBER_OF_SYMBOLS_LOG2 (2),
.MAX_BURST_COUNT_WIDTH (1),
.UNALIGNED_ACCESSES_ENABLE (0),
.ONLY_FULL_ACCESS_ENABLE (1),
.BURST_WRAPPING_SUPPORT (0),
.PROGRAMMABLE_BURST_ENABLE (0),
.MAX_BURST_COUNT (1),
.FIFO_SPEED_OPTIMIZATION (1),
.STRIDE_WIDTH (1),
.ACTUAL_BYTES_TRANSFERRED_WIDTH (32)
) write_mstr_internal (
.clk (clock_clk), // Clock.clk
.reset (~reset_n_reset_n), // Clock_reset.reset
.master_address (mm_write_address), // Data_Write_Master.address
.master_write (mm_write_write), // .write
.master_byteenable (mm_write_byteenable), // .byteenable
.master_writedata (mm_write_writedata), // .writedata
.master_waitrequest (mm_write_waitrequest), // .waitrequest
.snk_data (st_sink_data), // Data_Sink.data
.snk_valid (st_sink_valid), // .valid
.snk_ready (st_sink_ready), // .ready
.snk_command_data (dispatcher_internal_write_command_source_data), // Command_Sink.data
.snk_command_valid (dispatcher_internal_write_command_source_valid), // .valid
.snk_command_ready (dispatcher_internal_write_command_source_ready), // .ready
.src_response_data (write_mstr_internal_response_source_data), // Response_Source.data
.src_response_valid (write_mstr_internal_response_source_valid), // .valid
.src_response_ready (write_mstr_internal_response_source_ready), // .ready
.master_burstcount (), // (terminated)
.snk_sop (1'b0), // (terminated)
.snk_eop (1'b0), // (terminated)
.snk_empty (2'b00), // (terminated)
.snk_error (8'b00000000) // (terminated)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 201; inline void NEXT(const char *T, int *next, int t_len) { next[0] = -1; for (int i = 1; i < t_len; i++) { int j = next[i - 1]; while (j >= 0 && T[i - 1] != T[j]) j = next[j]; if (j >= 0 && T[i - 1] == T[j]) next[i] = j + 1; else next[i] = 0; } } int COUNT_KMP(const char *S, const char *T, int s_len, int t_len) { int next[t_len]; NEXT(T, next, t_len); int index, count = 0; for (index = 0; index < s_len; ++index) { int pos = 0; int iter = index; while (pos < t_len && iter < s_len) { if (S[iter] == T[pos]) { ++iter; ++pos; } else { if (pos == 0) ++iter; else pos = next[pos - 1] + 1; } } if (pos == t_len && (iter - index) == t_len) ++count; } return count; } int my_substr(char *s, char *t, int pos, int len) { int i; for (i = 0; i < len; ++i) { if (t[i + pos] == 0 ) { break; } s[i] = t[i + pos]; } s[i] = 0 ; return i; } int64_t cal(const char *s, int n, int64_t k) { int64_t sum[MAX_N]; memset(sum, 0, sizeof(sum)); char f[MAX_N][MAX_N * 10 + 1]; int len[MAX_N]; memset(len, 0, sizeof(len)); int s_len = strlen(s); sprintf(f[0], 0 ); sprintf(f[1], 1 ); len[0] = len[1] = 1; if (s_len == 1) { if (s[0] == 0 ) { sum[0]++; } else if (s[0] == 1 ) { sum[1]++; } } int max_len = s_len - 1; char tmp_str[MAX_N * 10 + 1]; for (int i = 2; i <= n; ++i) { len[i] = len[i - 2] + len[i - 1]; sprintf(f[i], %s%s , f[i - 2], f[i - 1]); int start = 0; if (len[i - 2] > max_len) { start = len[i - 2] - max_len; } int my_len = my_substr(tmp_str, f[i - 2], start, max_len); my_len += my_substr(tmp_str + my_len, f[i - 1], 0, max_len); int64_t result = COUNT_KMP(tmp_str, s, my_len, s_len); sum[i] = sum[i - 2] + sum[i - 1] + result; if (sum[i] > k) { return sum[i]; } if (len[i] > max_len * 2) { int del_num = len[i] - (max_len * 2); for (int pos = max_len + del_num; pos < len[i]; ++pos) { f[i][pos - del_num] = f[i][pos]; } len[i] = max_len * 2; f[i][len[i]] = 0 ; } } return sum[n]; } int process() { int n, m; int64_t k; char suffix[] = 110101101011011010110101101101011011010110101101101011011010110101101101 011010110110101101101011010110110101101011011010110110101101011011010110 11010110101101101011010110110101101101011010110110101101 ; int suffix_len = strlen(suffix); cin >> n >> k >> m; char s[MAX_N]; memset(s, 0 , sizeof(s)); for (int i = 0; i < m; ++i) { int pos = suffix_len - i; int s_pos = 0; while (pos < suffix_len) { if (s[s_pos] != suffix[pos]) { break; } s_pos++; pos++; } if (pos == suffix_len && i > 0) { if (k == 1) { break; } k--; } if (i > 0 && s[i - 1] == 0 ) { s[i] = 1 ; s[i + 1] = 0 ; continue; } if (i > 1 && s[i - 1] == 1 && s[i - 2] == 1 ) { s[i] = 0 ; s[i + 1] = 0 ; continue; } s[i] = 0 ; s[i + 1] = 0 ; int64_t count = cal(s, n, k); if (count < k) { k = k - count; s[i] = 1 ; } } printf( %s n , s); return 0; } int main(int argc, char *argv[]) { process(); return 0; }
|
#include <bits/stdc++.h> using namespace std; using nagai = long long; const int N = 100; int matr[N][N]; const int K = 12; int de[N][K]; const int oo = 0x3f3f3f3f; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) cin >> matr[i][j]; int ans = oo; for (int i = 0; i < 30000; ++i) { memset(de, 0x3f, sizeof de); vector<int> col(n); for (int i = 0; i < n; ++i) col[i] = rnd() % 2; de[0][0] = 0; for (int l = 0; l < k; ++l) for (int a = 0; a < n; ++a) for (int b = 0; b < n; ++b) if (col[a] != col[b]) de[b][l + 1] = min(de[b][l + 1], de[a][l] + matr[a][b]); ans = min(ans, de[0][k]); } cout << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MOD(1000000007); const int Max_W(1000050); inline int Mult(const int &a, const int &b) { return (a * 1LL) * b % MOD; } constexpr int Add(int a, int b) { return a + b >= MOD ? a + b - MOD : a + b; } constexpr int Sub(int a, int b) { return a - b < 0 ? a - b + MOD : a - b; } void exgcd(const int &a, const int &b, int &x, int &y) { if (b == 0) x = 1, y = 0; else exgcd(b, a % b, y, x), y -= x * (a / b); } inline int inverse(const int &a) { int invx, invy; exgcd(a, MOD, invx, invy); return (invx % MOD + MOD) % MOD; } int power(int a, int n) { int Ret(1); while (n) { if (n & 1) Ret = Mult(Ret, a); a = Mult(a, a), n >>= 1; } return Ret; } int W, A[Max_W], Fac[Max_W], Inv[Max_W]; inline int P(const int &n, const int &m) { return (0 <= m && m <= n) ? Mult(Fac[n], Inv[n - m]) : 0; } int work(const int &N) { int Ans(0); if (W == 1) Ans = N; else Ans = Mult(Sub(power(W, N + 1), W), inverse(Sub(W, 1))); for (int len = N + 1; len - N <= W; ++len) if (len - N < N + 1) Ans = Add(Ans, Mult(Mult(A[len - N], A[len - N]), power(W, N - (len - N)))); else Ans = Add(Ans, Mult(A[len - N], P(W - ((len - N) - (N + 1) + 1), N))); return Ans; } int main() { int N; scanf( %d%d , &W, &N); A[0] = 1; for (int i = 1; i <= W; ++i) A[i] = Mult(A[i - 1], W - i + 1); Fac[0] = 1; for (int i = 1; i <= W; ++i) Fac[i] = Mult(Fac[i - 1], i); Inv[W] = inverse(Fac[W]); for (int i = W - 1; i >= 0; --i) Inv[i] = Mult(Inv[i + 1], i + 1); printf( %d , Sub(work(N), work(N - 1))); return 0; }
|
#include <bits/stdc++.h> const int N = 110; using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) { f = -1; } ch = getchar(); } while (ch <= 9 && ch >= 0 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } int n, a[N], cnt; int minn[N]; bool in_q(int x) { for (int i = 1; i <= cnt; i++) { if (x % minn[i] == 0) { return 1; } if (minn[i] % x == 0) { minn[i] = x; return 1; } } return 0; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { if (!in_q(a[i])) { minn[++cnt] = a[i]; } } cout << cnt << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, a, b, g[3005 * 3005], x, y, z, A[3005][3005], ans; deque<long long> q; vector<long long> v; vector<vector<long long> > V; vector<long long> fun(vector<long long> v, long long n, long long b) { vector<long long> ans; q.clear(); for (__typeof((b)) i = (0); i < (b); i++) { while ((long long)q.size() && v[i] <= v[q.back()]) q.pop_back(); q.push_back(i); } ans.push_back(v[q.front()]); for (__typeof((n)) i = (b); i < (n); i++) { while ((long long)q.size() && q.front() <= i - b) q.pop_front(); while ((long long)q.size() && v[i] <= v[q.back()]) q.pop_back(); q.push_back(i); ans.push_back(v[q.front()]); } return ans; } void solve() { cin >> n >> m >> a >> b >> g[0] >> x >> y >> z; for (__typeof((3005 * 3005)) i = (1); i < (3005 * 3005); i++) g[i] = (g[i - 1] * x + y) % z; for (__typeof((n + 1)) i = (1); i < (n + 1); i++) { for (__typeof((m + 1)) j = (1); j < (m + 1); j++) A[i][j] = g[(i - 1) * m + j - 1]; } for (__typeof((n + 1)) i = (1); i < (n + 1); i++) { v.clear(); for (__typeof((m + 1)) j = (1); j < (m + 1); j++) v.push_back(A[i][j]); V.push_back(fun(v, m, b)); } for (__typeof(((long long)V[0].size())) j = (0); j < ((long long)V[0].size()); j++) { v.clear(); for (__typeof((n)) i = (0); i < (n); i++) v.push_back(V[i][j]); vector<long long> res = fun(v, n, a); for (auto i : res) ans += i; } { cout << ans << n ; return; }; } void prep() {} int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; prep(); cout << fixed << setprecision(12); while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; vector<vector<int> > a[28]; vector<int> t, v1, v2; int ans = 1e9; void gen(int ind) { if (ind == 3) { a[t[0] + t[1] + t[2]].push_back(t); return; } for (int i = 0; i <= 9; i++) { t.push_back(i); gen(ind + 1); t.pop_back(); } } int dif(vector<int> aa, vector<int> bb) { int ret = 0; for (int i = 0; i < aa.size(); i++) ret += (aa[i] != bb[i]); return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> s; v1.push_back(s[0] - 0 ); v1.push_back(s[1] - 0 ); v1.push_back(s[2] - 0 ); v2.push_back(s[3] - 0 ); v2.push_back(s[4] - 0 ); v2.push_back(s[5] - 0 ); gen(0); for (int i = 0; i <= 27; i++) for (int j = 0; j < a[i].size(); j++) for (int k = 0; k < a[i].size(); k++) ans = min(ans, dif(v1, a[i][j]) + dif(v2, a[i][k])); cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
|
//----------------------------------------------------------------------------
//-- Unidad de transmision serie asincrona
//------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//--- Modulo de transmision serie
//--- La salida tx ESTA REGISTRADA
module uart_tx (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire rstn, //-- Reset global (activo nivel bajo)
input wire start, //-- Activar a 1 para transmitir
input wire [7:0] data, //-- Byte a transmitir
output reg tx, //-- Salida de datos serie (hacia el PC)
output wire ready //-- Transmisor listo / ocupado
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Reloj para la transmision
wire clk_baud;
//-- Bitcounter
reg [3:0] bitc;
//-- Datos registrados
reg [7:0] data_r;
//--------- Microordenes
wire load; //-- Carga del registro de desplazamiento. Puesta a 0 del
//-- contador de bits
wire baud_en; //-- Habilitar el generador de baudios para la transmision
//-------------------------------------
//-- RUTA DE DATOS
//-------------------------------------
always @(posedge clk)
if (start == 1 && state == IDLE)
data_r <= data;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Cuando la microorden load es 1 se carga la trama
//-- con load 0 se desplaza a la derecha y se envia un bit, al
//-- activarse la señal de clk_baud que marca el tiempo de bit
//-- Se introducen 1s por la izquierda
always @(posedge clk)
//-- Reset
if (rstn == 0)
shifter <= 10'b11_1111_1111;
//-- Modo carga
else if (load == 1)
shifter <= {data_r,2'b01};
//-- Modo desplazamiento
else if (load == 0 && clk_baud == 1)
shifter <= {1'b1, shifter[9:1]};
//-- Contador de bits enviados
//-- Con la microorden load (=1) se hace un reset del contador
//-- con load = 0 se realiza la cuenta de los bits, al activarse
//-- clk_baud, que indica el tiempo de bit
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono
//-- y hay que evitar que salgan pulsos espureos (glitches)
always @(posedge clk)
tx <= shifter[0];
//-- Divisor para obtener el reloj de transmision
baudgen #(BAUD)
BAUD0 (
.clk(clk),
.clk_ena(baud_en),
.clk_out(clk_baud)
);
//------------------------------
//-- CONTROLADOR
//------------------------------
//-- Estados del automata finito del controlador
localparam IDLE = 0; //-- Estado de reposo
localparam START = 1; //-- Comienzo de transmision
localparam TRANS = 2; //-- Estado: transmitiendo dato
//-- Estados del autómata del controlador
reg [1:0] state;
//-- Transiciones entre los estados
always @(posedge clk)
//-- Reset del automata. Al estado inicial
if (rstn == 0)
state <= IDLE;
else
//-- Transiciones a los siguientes estados
case (state)
//-- Estado de reposo. Se sale cuando la señal
//-- de start se pone a 1
IDLE:
if (start == 1)
state <= START;
else
state <= IDLE;
//-- Estado de comienzo. Prepararse para empezar
//-- a transmitir. Duracion: 1 ciclo de reloj
START:
state <= TRANS;
//-- Transmitiendo. Se esta en este estado hasta
//-- que se hayan transmitido todos los bits pendientes
TRANS:
if (bitc == 11)
state <= IDLE;
else
state <= TRANS;
//-- Por defecto. NO USADO. Puesto para
//-- cubrir todos los casos y que no se generen latches
default:
state <= IDLE;
endcase
//-- Generacion de las microordenes
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
//-- Señal de salida. Esta a 1 cuando estamos en reposo (listos
//-- para transmitir). En caso contrario esta a 0
assign ready = (state == IDLE) ? 1 : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_8_V
`define SKY130_FD_SC_HVL__DECAP_8_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_8_V
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg foo = 0;
initial #10 foo = 1;
initial #1 begin
if (foo !== 1'b0) begin
$display("FAILED -- foo before wait is %b", foo);
$finish;
end
// This wait without a statement has caused a few bugs.
wait (foo) ;
if (foo !== 1'b1) begin
$display("FAILED -- foo after wait is %b", foo);
$finish;
end
if ($time != 10) begin
$display("FAILED -- $time after wait is %t", $time);
$finish;
end
$display("PASSED");
end
endmodule // main
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
`timescale 1ns/100ps
module axi_ad9265_if (
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
adc_status,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
// nominal clock 125 MHz, up to 300 MHz
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
output adc_status;
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or = 'd0;
// internal signals
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
always @(posedge adc_clk)
begin
adc_status <= 1'b1;
adc_or <= adc_or_p_s | adc_or_n_s;
adc_data <= { adc_data_p_s[7], adc_data_n_s[7], adc_data_p_s[6], adc_data_n_s[6], adc_data_p_s[5], adc_data_n_s[5], adc_data_p_s[4], adc_data_n_s[4], adc_data_p_s[3], adc_data_n_s[3], adc_data_p_s[2], adc_data_n_s[2], adc_data_p_s[1], adc_data_n_s[1], adc_data_p_s[0], adc_data_n_s[0]};
end
// data interface
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[8]),
.up_dwdata (up_dwdata[44:40]),
.up_drdata (up_drdata[44:40]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> const int N = 105; char matrix[N][N]; void solve(int i, int j, int type) { char c = a ; switch (type) { case 0: while (1) { if (matrix[i - 1][j] == c || matrix[i - 1][j + 1] == c || matrix[i + 1][j] == c || matrix[i + 1][j + 1] == c || matrix[i][j - 1] == c || matrix[i][j + 2] == c) { c = (char)(c + 1); } else { break; } } matrix[i][j] = matrix[i][j + 1] = c; break; case 1: while (1) { if (matrix[i - 1][j] == c || matrix[i + 2][j] == c || matrix[i][j - 1] == c || matrix[i + 1][j - 1] == c || matrix[i][j + 1] == c || matrix[i + 1][j + 1] == c) { c = (char)(c + 1); } else { break; } } matrix[i][j] = matrix[i + 1][j] = c; break; case 2: while (1) { if (matrix[i - 1][j] == c || matrix[i - 1][j + 1] == c || matrix[i + 1][j] == c || matrix[i + 1][j + 1] == c || matrix[i][j - 1] == c || matrix[i + 1][j - 1] == c || matrix[i][j + 2] == c || matrix[i + 1][j + 2] == c) { c = (char)(c + 1); } else { break; } } matrix[i][j] = matrix[i + 1][j] = matrix[i][j + 1] = matrix[i + 1][j + 1] = c; break; } } int main() { int n, m, a, b, c, i, j; bool ok = true; scanf( %d%d%d%d%d , &n, &m, &a, &b, &c); if (n & 1 && m & 1) { ok = false; } else if (n & 1) { for (i = 1; i <= n - 1 && ok; i += 2) { for (j = 1; j <= m && ok; j += 2) { if (c) { solve(i, j, 2); c--; } else if (b >= 2) { solve(i, j, 1); solve(i, j + 1, 1); b -= 2; } else if (a >= 2) { solve(i, j, 0); solve(i + 1, j, 0); a -= 2; } else { ok = false; } } } for (j = 1; j <= m && ok; j += 2) { if (a) { solve(i, j, 0); a--; } else { ok = false; } } } else if (m & 1) { for (i = 1; i <= n && ok; i += 2) { for (j = 1; j <= m - 1 && ok; j += 2) { if (c) { solve(i, j, 2); c--; } else if (a >= 2) { solve(i, j, 0); solve(i + 1, j, 0); a -= 2; } else if (b >= 2) { solve(i, j, 1); solve(i, j + 1, 1); b -= 2; } else { ok = false; } } } for (i = 1; i <= n && ok; i += 2) { if (b) { solve(i, j, 1); b--; } else { ok = false; } } } else { for (i = 1; i <= n && ok; i += 2) { for (j = 1; j <= m && ok; j += 2) { if (c) { solve(i, j, 2); c--; } else if (a >= 2) { solve(i, j, 0); solve(i + 1, j, 0); a -= 2; } else if (b >= 2) { solve(i, j, 1); solve(i, j + 1, 1); b -= 2; } else { ok = false; } } } } if (ok) { for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { printf( %c , matrix[i][j]); } printf( n ); } } else { printf( IMPOSSIBLE n ); } return 0; }
|
//-----------------------------------------------------------------------------
// For reading TI tags, we need to place the FPGA in pass through mode
// and pass everything through to the ARM
//-----------------------------------------------------------------------------
module lo_passthru(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg, divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
reg [7:0] pck_divider;
reg ant_lo;
// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
// which is high for (divisor+1) pck0 cycles and low for the same duration
// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
ant_lo = !ant_lo;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
// the antenna is modulated when ssp_dout = 1, when 0 the
// antenna drivers stop modulating and go into listen mode
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign pwr_lo = ant_lo && ssp_dout;
assign pwr_hi = 1'b0;
assign adc_clk = 1'b0;
assign ssp_din = cross_lo;
assign dbg = cross_lo;
endmodule
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#include<cstdio> #include<cstring> #include<iostream> #include<algorithm> #include<cmath> #include<vector> #include<queue> #include<stack> #include<ctime> #include<map> #define ll long long #define MAXN 20105 #define uns unsigned #define INF 0x3f3f3f3f #define MOD 1000000007ll #define lowbit(x) ((x)&(-(x))) using namespace std; inline ll read(){ ll x=0;bool f=1;char s=getchar(); while((s< 0 ||s> 9 )&&s>0){if(s== - )f^=1;s=getchar();} while(s>= 0 &&s<= 9 )x=(x<<1)+(x<<3)+s- 0 ,s=getchar(); return f?x:-x; } int n,q,a[MAXN],st[MAXN][20],dp[MAXN][20][35],lg[MAXN]; int A[35],B[35],tmp[35]; inline int maxx(int x,int y){return x+a[x]>y+a[y]?x:y;} inline int rmq(int l,int r){ if(l>r)return 0;r=min(r,n);int k=lg[r-l+1]; return maxx(st[l][k],st[r-(1<<k)+1][k]); } signed main() { n=read(),q=read(); for(int i=1;i<=n;i++)a[i]=read(),st[i][0]=i; lg[1]=0; for(int i=2;i<=n;i++)lg[i]=lg[i>>1]+1; for(int i=n;i>0;i--) for(int j=1;i+(1<<j)-1<=n;j++) st[i][j]=maxx(st[i][j-1],st[i+(1<<(j-1))][j-1]); for(int i=1;i<=n;i++) for(int k=0;k<=30;k++)dp[i][0][k]=i+a[i]+k; for(int j=0;j<lg[n];j++) for(int i=1;i<=n;i++) for(int k=0;k<=30;k++){ for(int l=k;l<=30;l++) dp[i][j+1][l]=max(dp[i][j+1][l],dp[ rmq(i,dp[i][j][k]) ][j][l-k]); for(int l=k;l<=30;l++) dp[i][j+1][l]=max(dp[i][j+1][l],dp[i][j+1][k]+l-k); } while(q--){ int l=read(),r=read(),k=read(); if(l==r){printf( 0 n );continue;} if(r<=l+a[l]+k){printf( 1 n );continue;} int ans=2; for(int i=0;i<=k;i++)A[i]=l+a[l]+i; for(int e=lg[r-l+1];e>=0;e--){ for(int i=0;i<=k;i++)tmp[i]=A[i],B[i]=rmq(l,A[i]); bool off=0; for(int i=0;i<=k&&!off;i++) for(int j=i;j<=k&&!off;j++) if(dp[B[i]][e][j-i]>tmp[j]){ tmp[j]=dp[B[i]][e][j-i]; if(tmp[j]>=r)off=1; } if(off)continue;ans+=(1<<e); for(int i=0;i<=k;i++)A[i]=tmp[i]; } printf( %d n ,ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<string> mas; int n, m; void input() { cin >> n >> m; mas.clear(); mas.resize(n); for (int i = 0; i < n; ++i) cin >> mas[i]; } void solve() { string ans = mas[0]; for (int i = 0; i < m; ++i) { char save = ans[i]; for (char d = a ; d <= z ; d++) { ans[i] = d; bool f = 1; for (int j = 0; j < n; ++j) { int err = 0; for (int c = 0; c < m; ++c) { if (ans[c] != mas[j][c]) err++; } if (err > 1) { f = 0; break; } } if (f) { cout << ans << n ; return; } } ans[i] = save; } cout << -1 n ; } int main() { int Q; cin >> Q; while (Q--) { input(); solve(); } return 0; }
|
`default_nettype none
module dps_lsflags(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//
input wire iSCI_VALID,
input wire iSCI_SCITIE,
input wire iSCI_SCIRIE,
//
input wire iREAD_VALID,
//
output wire oLSFLAGS_VALID,
output wire [31:0] oLSFLAGS
);
reg [31:0] b_lsflags;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_lsflags <= 32'h0;
end
else if(iRESET_SYNC || iREAD_VALID)begin
b_lsflags <= 32'h0;
end
else begin
if(iSCI_VALID)begin
b_lsflags <= {30'h0, iSCI_SCIRIE, iSCI_SCITIE};
end
end
end
reg b_valid;
reg [31:0] b_buff_lsflags;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_valid <= 1'b0;
b_buff_lsflags <= 32'h0;
end
else if(iRESET_SYNC)begin
b_valid <= 1'b0;
b_buff_lsflags <= 32'h0;
end
else begin
b_valid <= iREAD_VALID;
b_buff_lsflags <= b_lsflags;
end
end
assign oLSFLAGS_VALID = b_valid;
assign oLSFLAGS = b_buff_lsflags;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int i, j, k, l, n, m, s, an, K, X; const int N = 5100; int a[1100000], g[1100000]; long long f[N][N]; int main() { scanf( %d%d , &n, &K); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(&a[1], &a[n + 1]); int v1 = n / K + 1; int v2 = n / K; if (n % K == 0) v1--; int ss = n % K; if (!ss) ss = K; ss = K - ss; memset(f, 120, sizeof(f)); f[0][0] = 0; for (int i = 0; i <= K; i++) for (int j = 0; j <= ss; j++) { int now = j * v2 + (i - j) * v1; f[i + 1][j] = min(f[i + 1][j], f[i][j] + a[now + v1] - a[now + 1]); f[i + 1][j + 1] = min(f[i + 1][j + 1], f[i][j] + a[now + v2] - a[now + 1]); } printf( %I64d n , f[K][ss]); return 0; }
|
module ABRO_blif(clk, rst, O, A, B, R);
input clk, rst;
output O;
input A;
input B;
input R;
wire A;
wire B;
wire R;
wire O;
wire w_0;
wire w_1;
wire R_O;
wire SM1_chk_0;
wire w_7;
wire w_8;
wire w_9;
wire SM3_chk_0;
wire w_10;
wire SM3_chk_1;
wire w_11;
wire SM10_chk_0;
wire w_12;
wire SM10_chk_1;
wire w_13;
wire B_O;
wire w_14;
wire w_15;
wire w_16;
wire w_17;
wire SM6_chk_0;
wire w_18;
wire SM6_chk_1;
wire w_19;
wire A_O;
wire w_20;
wire w_21;
wire w_22;
wire w_23;
wire w_24;
wire tick_O;
wire w_30;
wire w_31;
wire SM1_chk_1;
wire w_32;
wire SM1_goto_0;
wire SM1_goto_1;
wire SM1_hold;
wire w_36;
wire SM3_goto_0;
wire w_38;
wire SM3_goto_1;
wire SM3_hold;
wire SM6_goto_0;
wire w_42;
wire SM6_goto_1;
wire SM6_hold;
wire SM10_goto_0;
wire w_46;
wire SM10_goto_1;
wire SM10_hold;
wire ff_1_0_q;
wire ff_1_0_d;
wire g57;
wire ff_3_0_q;
wire ff_3_0_d;
wire g60;
wire ff_6_0_q;
wire ff_6_0_d;
wire g63;
wire ff_10_0_q;
wire ff_10_0_d;
wire g66;
assign O = w_24;
assign w_0 = 0;
assign w_1 = 1;
assign R_O = R;
assign SM1_chk_0 = !ff_1_0_q;
assign w_7 = R_O & SM1_chk_0;
assign w_8 = !R_O;
assign w_9 = w_8 & SM1_chk_0;
assign SM3_chk_0 = !ff_3_0_q;
assign w_10 = w_9 & SM3_chk_0;
assign SM3_chk_1 = ff_3_0_q;
assign w_11 = w_9 & SM3_chk_1;
assign SM10_chk_0 = !ff_10_0_q;
assign w_12 = w_11 & SM10_chk_0;
assign SM10_chk_1 = ff_10_0_q;
assign w_13 = w_11 & SM10_chk_1;
assign B_O = B;
assign w_14 = w_13 & B_O;
assign w_15 = !B_O;
assign w_16 = w_13 & w_15;
assign w_17 = w_14 | w_12;
assign SM6_chk_0 = !ff_6_0_q;
assign w_18 = w_11 & SM6_chk_0;
assign SM6_chk_1 = ff_6_0_q;
assign w_19 = w_11 & SM6_chk_1;
assign A_O = A;
assign w_20 = w_19 & A_O;
assign w_21 = !A_O;
assign w_22 = w_21 & w_19;
assign w_23 = w_20 | w_18;
assign w_24 = w_17 & w_23;
assign tick_O = w_1;
assign w_30 = !w_24;
assign w_31 = w_11 & w_30;
assign SM1_chk_1 = ff_1_0_q;
assign w_32 = w_9 | w_7 | SM1_chk_1;
assign SM1_goto_0 = w_32;
assign SM1_goto_1 = w_0;
assign SM1_hold = w_0;
assign w_36 = w_10 | w_24;
assign SM3_goto_0 = w_36;
assign w_38 = w_7 | w_31 | SM1_chk_1;
assign SM3_goto_1 = w_38;
assign SM3_hold = w_0;
assign SM6_goto_0 = w_23;
assign w_42 = w_7 | w_22 | SM1_chk_1;
assign SM6_goto_1 = w_42;
assign SM6_hold = w_0;
assign SM10_goto_0 = w_17;
assign w_46 = w_7 | w_16 | SM1_chk_1;
assign SM10_goto_1 = w_46;
assign SM10_hold = w_0;
d_ff1 u0(rst, clk, ff_1_0_q, ff_1_0_d);
assign ff_1_0_d = g57 | SM1_goto_1;
assign g57 = SM1_hold & ff_1_0_q;
d_ff0 u1(rst, clk, ff_3_0_q, ff_3_0_d);
assign ff_3_0_d = g60 | SM3_goto_1;
assign g60 = SM3_hold & ff_3_0_q;
d_ff0 u2(rst, clk, ff_6_0_q, ff_6_0_d);
assign ff_6_0_d = g63 | SM6_goto_1;
assign g63 = SM6_hold & ff_6_0_q;
d_ff0 u3(rst, clk, ff_10_0_q, ff_10_0_d);
assign ff_10_0_d = g66 | SM10_goto_1;
assign g66 = SM10_hold & ff_10_0_q;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:08:14 05/29/2015
// Design Name:
// Module Name: UART_RX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//De-serializer
module UART_RX(
input RxD_ser,
output CTS, // I am clear to receive (active high)
input sys_clk,
input Baud16Tick, // Oversampling by 16
output reg [7:0] TxD_par, //8 bit data
output TxD_ready
);
// Data synchronization ans stablization by passing it through 2 flip flops
reg [1:0] RxD_sync;
always @(posedge sys_clk) if(Baud16Tick) RxD_sync <= {RxD_sync[0], RxD_ser};
// Filter data
reg [2:0] RxD_cnt=7;
reg RxD_bit;
always @(posedge sys_clk)
if(Baud16Tick)
begin
if(RxD_sync[1] && RxD_cnt!=3'b111) RxD_cnt <= RxD_cnt + 1; // Count up no of times line is high
else if(~RxD_sync[1] && RxD_cnt!=3'b000) RxD_cnt <= RxD_cnt - 1; // Count down no of times line is low
// Determine data
if(RxD_cnt==3'b000) RxD_bit <= 0;
else if(RxD_cnt==3'b111) RxD_bit <= 1;
end
// State machine
reg [3:0] state=0;
always @(posedge sys_clk)
if(Baud16Tick)
case(state)
4'b0000: if(~RxD_bit) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
// Ready to receive
assign CTS = (state<2); //ready to receive
// Measure bit spacing
reg [3:0] bit_spacing;
always @(posedge sys_clk)
if(state==0)
bit_spacing <= 0;
else
if(Baud16Tick) bit_spacing <= bit_spacing + 1;
wire next_bit = (bit_spacing==15);
assign TxD_ready = (state==1);
// Collect data
//reg [7:0] TxD_par;
always @(posedge sys_clk) if(Baud16Tick && next_bit && state[3]) TxD_par <= {RxD_bit, TxD_par[7:1]};
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; struct hhh { long long x; long long y; long long v; } c[1000001]; bool operator<(hhh a, hhh b) { return (a.v != b.v ? a.v > b.v : (a.x != b.x ? a.x > b.x : a.y > b.y)); } vector<hhh> v; long long n, m, a, b, h[1001][1001], g[1001][1001], mi[1001][1001], minf[1001][1001], k; bool f[1001][1001]; long long pre[3][1001][1001]; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } bool check(hhh t) { if (f[t.x][t.y]) { return 0; } for (long long i = max(t.x - a + 1, (long long)1); i <= t.x + a - 1; i++) { for (long long j = max(t.y - b + 1, (long long)1); j <= t.y + b - 1; j++) { f[i][j] = 1; } } return 1; } int main() { n = read(); m = read(); a = read(); b = read(); for (long long i = 1; i <= (n); i++) { for (long long j = 1; j <= (m); j++) { h[i][j] = read(); } } for (long long i = 1; i <= (n); i++) { for (long long j = 1; j <= (m); j++) { pre[1][i][j] = pre[1][i][j - 1] + h[i][j]; pre[2][i][j] = pre[2][i - 1][j] + h[i][j]; } } for (long long i = 1; i <= (a); i++) { g[1][1] += pre[1][i][b]; } for (long long i = 2; i <= m - b + 1; i++) { g[1][i] = g[1][i - 1] + pre[2][a][i + b - 1] - pre[2][a][i - 1]; } for (long long i = 2; i <= n - a + 1; i++) { for (long long j = 1; j <= (m - b + 1); j++) { g[i][j] = g[i - 1][j] + pre[1][i + a - 1][j + b - 1] - pre[1][i + a - 1][j - 1] - pre[1][i - 1][j + b - 1] + pre[1][i - 1][j - 1]; } } for (long long i = 1; i <= (n); i++) { long long s = 1; long long t = 0; long long que[1001]; que[0] = INF; for (long long j = 1; j <= (m); j++) { while (s <= t && h[i][que[t]] >= h[i][j]) { t--; } que[++t] = j; if (j - b >= 0) { mi[i][j - b + 1] = h[i][que[s]]; } if (que[s] == j - b + 1) { s++; } } } for (long long j = 1; j <= (m - b + 1); j++) { long long s = 1; long long t = 0; long long que[1001]; que[0] = INF; for (long long i = 1; i <= (n); i++) { while (s <= t && mi[que[t]][j] >= mi[i][j]) { t--; } que[++t] = i; if (i - a >= 0) { minf[i - a + 1][j] = mi[que[s]][j]; } if (que[s] == i - a + 1) { s++; } } } for (long long i = 1; i <= (n - a + 1); i++) { for (long long j = 1; j <= (m - b + 1); j++) { g[i][j] -= a * b * minf[i][j]; hhh t; t.x = i; t.y = j; t.v = g[i][j]; v.push_back(t); } } make_heap(v.begin(), v.end()); while (!v.empty()) { hhh t = v.front(); pop_heap(v.begin(), v.end()); v.pop_back(); if (check(t)) { c[++k] = t; } } cout << k << endl; for (long long i = 1; i <= (k); i++) { printf( %I64d %I64d %I64d n , c[i].x, c[i].y, c[i].v); } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
// 1.2 11/8/2010 Fixed the PRBS Address generation.
//*****************************************************************************
`timescale 1ps/1ps
module cmd_prbs_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1)
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
// BL8: 0,8
//BL4: incremnt by 4
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 0)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = 1'b0;// lfsr_q[i+1];
prbs[logb2(MEM_BURST_LEN)-3:0] = {logb2(MEM_BURST_LEN) -3{1'b0}};
// prbs[2:0] = {3{1'b0}};
end
end
end endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
generate
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin
prbs = {ZEROS[SEED_WIDTH - 1:7],lfsr_q[6:1]};
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_pad_up.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS2 PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos2_pad_up(oe ,data ,to_core ,pad ,por_l, vddo );
output to_core ;
input oe ;
input data ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire rcvr_data ;
wire por ;
wire pad_up ;
wire net58 ;
wire net59 ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (vss ),
.bsr_up (net58 ),
.bsr_dn_l (net59 ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (vss ),
.bsr_mode (vss ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (vss ),
.bsr_up (vss ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (vss ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
bw_io_cmos2_term_up I18 (
.vddo (vddo ),
.out (pad ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x[5], y[5], i; cin >> n; for (i = 1; i <= n; i++) cin >> x[i] >> y[i]; if (n == 1) cout << -1; else if (n == 2) { if (x[1] != x[2] && y[1] != y[2]) cout << abs(x[1] - x[2]) * abs(y[1] - y[2]); else cout << -1; } else if (n == 3) { if (x[1] == x[2] && y[1] == y[3]) cout << abs(y[2] - y[1]) * abs(x[3] - x[1]); else if (x[1] == x[2] && y[2] == y[3]) cout << abs(y[2] - y[1]) * abs(x[3] - x[2]); else if (x[2] == x[3] && y[2] == y[1]) cout << abs(y[2] - y[3]) * abs(x[2] - x[1]); else if (x[2] == x[3] && y[3] == y[1]) cout << abs(y[2] - y[3]) * abs(x[3] - x[1]); else if (x[1] == x[3] && y[2] == y[1]) cout << abs(y[1] - y[3]) * abs(x[2] - x[1]); else if (x[1] == x[3] && y[3] == y[2]) cout << abs(y[1] - y[3]) * abs(x[3] - x[2]); } else if (n == 4) { int x1 = 10000, x2 = -10000, y1 = 10000, y2 = -10000; for (i = 1; i <= 4; i++) { if (x[i] < x1) x1 = x[i]; if (x[i] > x2) x2 = x[i]; if (y[i] < y1) y1 = y[i]; if (y[i] > y2) y2 = y[i]; } cout << (x2 - x1) * (y2 - y1); } }
|
#include <bits/stdc++.h> using namespace std; int n; double p, e[100010], dp[100010]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lf , &p); e[i] = p * (e[i - 1] + 1); dp[i] = dp[i - 1] + (2 * e[i - 1] + 1) * p; } printf( %.9lf , dp[n]); }
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module BrainfuckWrapper(
CLK, RESET,
CIN, COUT, CRDA, CACK, CWR, CRDY
);
parameter FAST_LOOPEND = 1;
parameter IA_WIDTH = 11;
parameter DA_WIDTH = 11;
parameter DD_WIDTH = 8;
parameter STACK_DEPTH_POW = 7;
input CLK;
input RESET;
input [7:0] CIN;
output [7:0] COUT;
input CRDA;
output CACK;
output CWR;
input CRDY;
wire [IA_WIDTH - 1:0] IA;
wire [7:0] IDIN;
wire IEN;
// Data bus
wire [DA_WIDTH - 1:0] DA;
wire [DD_WIDTH - 1:0] DDIN;
wire [DD_WIDTH - 1:0] DDOUT;
wire DEN;
wire DWE;
BrainfuckCPU #(
.FAST_LOOPEND(FAST_LOOPEND),
.IA_WIDTH(IA_WIDTH),
.DA_WIDTH(DA_WIDTH),
.DD_WIDTH(DD_WIDTH),
.STACK_DEPTH_POW(STACK_DEPTH_POW)
) cpu (
.CLK(CLK),
.RESET(RESET),
.IA(IA),
.IDIN(IDIN),
.IEN(IEN),
.DA(DA),
.DDIN(DDIN),
.DDOUT(DDOUT),
.DEN(DEN),
.DWE(DWE),
.CIN(CIN),
.COUT(COUT),
.CRDA(CRDA),
.CACK(CACK),
.CWR(CWR),
.CRDY(CRDY)
);
IRAM #(
.IA_WIDTH(IA_WIDTH)
) iram (
.CLK(CLK),
.A(IA),
.DOUT(IDIN),
.EN(IEN)
);
DRAM #(
.DA_WIDTH(DA_WIDTH),
.DD_WIDTH(DD_WIDTH)
) dram (
.CLK(CLK),
.A(DA),
.DIN(DDOUT),
.DOUT(DDIN),
.EN(DEN),
.WE(DWE)
);
endmodule
|
`timescale 1ns/10ps
module clock_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("11.288659 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("49.772727 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Comma separated parameter def used as a width subscript
//
//
// D: This validates that parameters can be used as literals
// D: in the width subscript.
//
module main();
parameter VAL_1 = 5,
VAL_2 = 0;
reg [VAL_1: VAL_2] temp_var;
initial // Excitation block
begin
temp_var = 6'h11;
#5 ;
end
initial // Validation block
begin
#1 ;
if(temp_var != 6'h11)
begin
$display("FAILED - parameter assignment didn't work\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLRBP_BEHAVIORAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_no_pg/sky130_fd_sc_hs__u_dl_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbp (
VPWR ,
VGND ,
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 65 + 5, maxk = (1 << 15) + 5, mod = 1e9 + 7, inf = 0x3f3f3f3f; long long n, m, Q, K, T, S; long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } long long a[maxn], jc[maxn], inv[maxn], du[maxn], ST[maxn]; long long q[maxn], top, cont[maxk], val[maxn]; long long cnt, tot, dp[maxn][maxk]; long long ans = 1; long long kpow(long long x, long long k) { long long ans = 1, now = x; while (k) { if (k & 1) ans = 1ll * ans * now % mod; now = 1ll * now * now % mod, k >>= 1; } return ans; } bool cmp(long long x, long long y) { return x > y; } long long C(long long a, long long b) { if (a < b) return 0; return 1ll * jc[a] * inv[b] % mod * inv[a - b] % mod; } void dfs(long long x, long long st) { if (ST[x]) return; ++tot, ST[x] = st; for (long long i = (1); i <= (n); ++i) if ((a[i] % a[x] == 0) || (a[x] % a[i] == 0)) dfs(i, st); } void clear() { top = 0; tot = 0; memset(cont, 0, sizeof(cont)); memset(dp, 0, sizeof(dp)); } signed main() { n = read(); jc[0] = inv[0] = 1; for (long long i = (1); i <= (n); ++i) jc[i] = 1ll * jc[i - 1] * i % mod, inv[i] = kpow(jc[i], mod - 2); for (long long i = (1); i <= (n); ++i) a[i] = read(); sort(a + 1, a + 1 + n); for (long long i = (1); i <= (n); ++i) for (long long j = (i + 1); j <= (n); ++j) if (!(a[j] % a[i])) ++du[j]; for (long long T = (1); T <= (n); ++T) { if (ST[T]) continue; clear(); dfs(T, T); for (long long i = (1); i <= (n); ++i) if (!du[i] && ST[i] == T) q[++top] = a[i]; if (tot - top <= 1) continue; for (long long i = (1); i <= (n); ++i) { if (!du[i] || ST[i] != T) continue; for (long long j = (1); j <= (top); ++j) if (!(a[i] % q[j])) val[i] |= (1 << (j - 1)); } S = (1 << top) - 1; for (long long s = (0); s <= (S); ++s) for (long long j = (1); j <= (n); ++j) if (ST[j] == T && du[j] && ((s & val[j]) == val[j])) ++cont[s]; for (long long i = (1); i <= (n); ++i) if (ST[i] == T && du[i]) ++dp[1][val[i]]; for (long long i = (1); i <= (tot - top - 1); ++i) for (long long s = (0); s <= (S); ++s) { if (!dp[i][s]) continue; if (cont[s] > i) dp[i + 1][s] = (dp[i + 1][s] + 1ll * dp[i][s] * (cont[s] - i) % mod) % mod; for (long long j = (1); j <= (n); ++j) if (ST[j] == T && du[j] && (s & val[j]) && ((s & val[j]) != val[j])) dp[i + 1][s | val[j]] = (dp[i + 1][s | val[j]] + dp[i][s]) % mod; } long long res = 0; tot -= top; for (long long s = (0); s <= (S); ++s) res = (res + dp[tot][s]) % mod; ans = 1ll * ans * res % mod * C(cnt + tot - 1, tot - 1) % mod; cnt += tot - 1; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int p = 0, cnt = 0, cplus, cminus, val[10005], Child[10005]; pair<int, int> F[10005][105], FF[105]; string s; vector<int> g[10005]; void DFS(int u) { while (p < s.size()) { p++; if (s[p - 1] == ( ) { g[u].push_back(++cnt); DFS(cnt); } else if ( 0 <= s[p - 1] && s[p - 1] <= 9 ) { val[++cnt] = s[p - 1] - 0 ; g[u].push_back(cnt); } else if (s[p - 1] == ) ) break; } } void FinalDFS(int u, int root) { for (int i = 0; i <= 100; i++) F[u][i] = pair<int, int>(1e9, -1e9); if (g[u].size() == 0) { F[u][0] = pair<int, int>(val[u], val[u]); return; } for (int i = 0; i < g[u].size(); i++) if (g[u][i] != root) FinalDFS(g[u][i], u); for (int i = 0; i <= 100; i++) F[u][i] = F[g[u][0]][i]; for (int i = 1; i < g[u].size(); i++) { int v = g[u][i]; for (int j = 0; j <= 100; j++) FF[j] = pair<int, int>(1e9, -1e9); for (int j = 0; j <= 100; j++) for (int jj = 0; jj <= j; jj++) { if (jj < j) { if (cplus <= 100) { FF[j].first = min(FF[j].first, F[u][j - jj - 1].first + F[v][jj].first); FF[j].second = max(FF[j].second, F[u][j - jj - 1].second + F[v][jj].second); } else { FF[j].first = min(FF[j].first, F[u][j - jj - 1].first - F[v][jj].second); FF[j].second = max(FF[j].second, F[u][j - jj - 1].second - F[v][jj].first); } } if (cplus <= 100) { FF[j].first = min(FF[j].first, F[u][j - jj].first - F[v][jj].second); FF[j].second = max(FF[j].second, F[u][j - jj].second - F[v][jj].first); } else { FF[j].first = min(FF[j].first, F[u][j - jj].first + F[v][jj].first); FF[j].second = max(FF[j].second, F[u][j - jj].second + F[v][jj].second); } } for (int j = 0; j <= 100; j++) F[u][j] = FF[j]; } } int main() { ios_base::sync_with_stdio(false); cin >> s >> cplus >> cminus; DFS(0); FinalDFS(1, 1); if (cplus <= 100) cout << F[1][cplus].second; else cout << F[1][cminus].second; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : MASTER_JTAG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 06/17/13 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MASTER_JTAG
`ifdef XIL_TIMING //Simprim adding LOC only
#(
parameter LOC = "UNPLACED"
)
`endif
(
output TDO,
input TCK,
input TDI,
input TMS
);
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2) cout << -1 ; else for (int i = 1; i <= n; i += 2) cout << i + 1 << << i << ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int main() { int T; cin >> T; while (T--) { long long n, m; cin >> n >> m; long long d = n / m; long long w = m % 10; long long sm = 0; for (int i = 0; i < 10; i++) { sm += (i * w) % 10; } long long fsm = 0; for (int i = 1; i <= d % 10; i++) { fsm += (i * w) % 10; } cout << sm * (d / 10) + fsm << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2_FUNCTIONAL_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Basic ifdef test with define
//
`define NOCODE
module ifdef2;
reg error ;
`ifdef NOCODE
initial
begin
#20;
error = 0;
#20;
end
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
`timescale 1ns/1ns
module usb_rx_nrzi
(input c_48,
input vp,
input vm,
input oe,
output d,
output dv,
output eop);
localparam J = 2'b10;
localparam K = 2'b01;
localparam SE0 = 2'b00;
// sharpen the inbound edges. synchronize them to c48
wire [1:0] rx;
sync #(2) input_sync(.in({vp, vm}), .clk(c_48), .out(rx));
// first task: when our driver is not enabled, watch for falling VP which
// implies start-of-packet
localparam ST_IDLE = 4'd0;
localparam ST_INIT = 4'd1;
localparam ST_K = 4'd2;
localparam ST_J = 4'd3;
localparam ST_SE0 = 4'd4;
localparam ST_EOP = 4'd5;
localparam ST_DONE = 4'd6;
localparam ST_ERROR = 4'd7;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(oe), .en(1'b1), .d(next_state), .q(state));
wire [1:0] cnt;
wire cnt_rst;
r #(2) cnt_r
(.c(c_48), .en(1'b1), .rst(cnt_rst), .d(cnt+1'b1), .q(cnt));
wire sample = cnt == 2'd1; // todo: shift this as needed to track tx clock?
wire num_ones_en, num_ones_rst;
wire [2:0] num_ones;
r #(3) num_ones_r
(.c(c_48), .en(num_ones_en), .rst(state == ST_IDLE | (num_ones_rst & sample)),
.d(num_ones+1'b1), .q(num_ones));
always @* begin
case (state)
ST_IDLE:
if (~oe & rx == K) ctrl = { ST_INIT , 5'b00100 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_INIT:
if (sample)
if (rx == K) ctrl = { ST_K , 5'b00001 };
else ctrl = { ST_ERROR, 5'b00000 };
else ctrl = { ST_INIT , 5'b00000 };
ST_K:
if (sample) begin
if (rx == SE0) ctrl = { ST_SE0 , 5'b00000 };
else if (rx == K) ctrl = { ST_K , 5'b01011 }; // same = 1
else if (rx == J) ctrl = { ST_J , 5'b10001 }; // flip = 0
else ctrl = { ST_ERROR, 5'b00000 };
end else ctrl = { ST_K , 5'b00000 };
ST_J:
if (sample) begin
if (rx == SE0) ctrl = { ST_SE0 , 5'b00000 };
else if (rx == J) ctrl = { ST_J , 5'b01011 }; // same = 1
else if (rx == K) ctrl = { ST_K , 5'b10001 }; // flip = 0
else ctrl = { ST_ERROR, 5'b00000 };
end else ctrl = { ST_J , 5'b00000 };
ST_SE0:
if (sample & rx == J) ctrl = { ST_EOP , 5'b00000 };
else ctrl = { ST_SE0 , 5'b00000 };
ST_EOP:
if (sample) ctrl = { ST_DONE , 5'b00000 };
else ctrl = { ST_EOP , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_ERROR, 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign cnt_rst = ctrl[2];
assign dv = ctrl[0] & num_ones != 3'd6;
assign d = ctrl[1];
assign num_ones_en = ctrl[3];
assign num_ones_rst = ctrl[4] | num_ones == 3'd6;
assign eop = state == ST_SE0;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); inline long long int rand(long long int x, long long int y) { ++y; return (rng() % (y - x)) + x; } long long int n, q, fw[300006], st[300006], en[300006], co, dist[300006], zero, line[300006], lines, sizee[300006]; vector<long long int> v[300006]; struct fen { long long int n; vector<long long int> fw; void init(long long int x) { fw.resize(x + 2 + 1); n = fw.size() - 1; } void update(long long int x, long long int y, long long int nv) { ++y; for (; x <= n; x += x & (-x)) fw[x] += nv; for (; y <= n; y += y & (-y)) fw[y] -= nv; } long long int sum(long long int x) { long long int res = 0; for (; x; x -= x & (-x)) res += fw[x]; return res; } } fen[300006]; struct fen2 { void update(long long int x, long long int y, long long int nv) { ++y; for (; x <= n; x += x & (-x)) fw[x] += nv; for (; y <= n; y += y & (-y)) fw[y] -= nv; } long long int sum(long long int x) { long long int res = 0; for (; x; x -= x & (-x)) res += fw[x]; return res; } } depth; void dfs(long long int x, long long int p) { st[x] = co++; if (p != 1) line[x] = line[p], sizee[line[p]]++; else if (x != 1) line[x] = lines++, sizee[line[x]]++; for (auto i : v[x]) { if (i == p) continue; dist[i] = dist[x] + 1; dfs(i, x); } en[x] = co; } int main() { cin >> n >> q; for (long long int i = 0; i < n - 1; i++) { long long int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } dfs(1, 1); for (long long int i = 0; i < lines; i++) fen[i].init(sizee[i]); for (long long int i = 1; i <= q; i++) { long long int op; cin >> op; if (op == 0) { long long int v, x, d; cin >> v >> x >> d; long long int overflow = d - dist[v]; if (overflow >= 0) depth.update(1, overflow + 1, x); if (v == 1) continue; if (overflow >= 0) fen[line[v]].update(overflow + 2, dist[v] + d + 1, x); else fen[line[v]].update(dist[v] - d + 1, dist[v] + d + 1, x); } else { long long int v; cin >> v; cout << depth.sum(dist[v] + 1) + fen[line[v]].sum(dist[v] + 1) << n ; } } }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module defines an iterator over work item space.
// Semantics:
//
// - Items for the same workgroup are issued contiguously.
// That is, items from different workgroups are never interleaved.
//
// - Subject to the previous constraint, we make the lower
// order ids (e.g. local_id[0]) iterate faster than
// higher order (e.g. local_id[2])
//
// - Id values start at zero and only increase.
//
// - Behaviour is unspecified if "issue" is asserted more than
// global_id[0] * global_id[1] * global_id[2] times between times
// that "start" is asserted.
module acl_work_item_iterator #(parameter WIDTH=32) (
input clock,
input resetn,
input start, // Assert to restart the iterators
input issue, // Assert to issue another item, i.e. advance the counters
// We assume these values are steady while "start" is not asserted.
input [WIDTH-1:0] local_size[2:0],
input [WIDTH-1:0] global_size[2:0],
// inputs from id_iterator
input [WIDTH-1:0] global_id_base[2:0],
// The counter values we export.
output reg [WIDTH-1:0] local_id[2:0],
output reg [WIDTH-1:0] global_id[2:0],
// output to id_iterator
output last_in_group
);
// This is the invariant relationship between the various ids.
// Keep these around for debugging.
wire [WIDTH-1:0] global_total = global_id[0] + global_size[0] * ( global_id[1] + global_size[1] * global_id[2] );
wire [WIDTH-1:0] local_total = local_id[0] + local_size[0] * ( local_id[1] + local_size[1] * local_id[2] );
function [WIDTH-1:0] incr_lid ( input [WIDTH-1:0] old_lid, input to_incr, input last );
if ( to_incr )
if ( last )
incr_lid = {WIDTH{1'b0}};
else
incr_lid = old_lid + 2'b01;
else
incr_lid = old_lid;
endfunction
//////////////////////////////////
// Handle local ids.
reg [WIDTH-1:0] max_local_id[2:0];
wire last_local_id[2:0];
assign last_local_id[0] = (local_id[0] == max_local_id[0] );
assign last_local_id[1] = (local_id[1] == max_local_id[1] );
assign last_local_id[2] = (local_id[2] == max_local_id[2] );
assign last_in_group = last_local_id[0] & last_local_id[1] & last_local_id[2];
wire bump_local_id[2:0];
assign bump_local_id[0] = (max_local_id[0] != 0);
assign bump_local_id[1] = (max_local_id[1] != 0) && last_local_id[0];
assign bump_local_id[2] = (max_local_id[2] != 0) && last_local_id[0] && last_local_id[1];
// Local id register updates.
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
local_id[0] <= {WIDTH{1'b0}};
local_id[1] <= {WIDTH{1'b0}};
local_id[2] <= {WIDTH{1'b0}};
max_local_id[0] <= {WIDTH{1'b0}};
max_local_id[1] <= {WIDTH{1'b0}};
max_local_id[2] <= {WIDTH{1'b0}};
end else if ( start ) begin
local_id[0] <= {WIDTH{1'b0}};
local_id[1] <= {WIDTH{1'b0}};
local_id[2] <= {WIDTH{1'b0}};
max_local_id[0] <= local_size[0] - 2'b01;
max_local_id[1] <= local_size[1] - 2'b01;
max_local_id[2] <= local_size[2] - 2'b01;
end else // We presume that start and issue are mutually exclusive.
begin
if ( issue ) begin
local_id[0] <= incr_lid (local_id[0], bump_local_id[0], last_local_id[0]);
local_id[1] <= incr_lid (local_id[1], bump_local_id[1], last_local_id[1]);
local_id[2] <= incr_lid (local_id[2], bump_local_id[2], last_local_id[2]);
end
end
end
// goes high one cycle after last_in_group. stays high until
// next cycle where 'issue' is high.
reg just_seen_last_in_group;
always @(posedge clock or negedge resetn) begin
if ( ~resetn )
just_seen_last_in_group <= 1'b1;
else if ( start )
just_seen_last_in_group <= 1'b1;
else if (last_in_group & issue)
just_seen_last_in_group <= 1'b1;
else if (issue)
just_seen_last_in_group <= 1'b0;
else
just_seen_last_in_group <= just_seen_last_in_group;
end
//////////////////////////////////
// Handle global ids.
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
global_id[0] <= {WIDTH{1'b0}};
global_id[1] <= {WIDTH{1'b0}};
global_id[2] <= {WIDTH{1'b0}};
end else if ( start ) begin
global_id[0] <= {WIDTH{1'b0}};
global_id[1] <= {WIDTH{1'b0}};
global_id[2] <= {WIDTH{1'b0}};
end else // We presume that start and issue are mutually exclusive.
begin
if ( issue ) begin
if ( !last_in_group ) begin
if ( just_seen_last_in_group ) begin
// get new global_id starting point from dispatcher.
// global_id_base will be one cycle late, so get it on the next cycle
// after encountering last element in previous group.
// id iterator will know to ignore the global id value on that cycle.
global_id[0] <= global_id_base[0] + bump_local_id[0];
global_id[1] <= global_id_base[1] + bump_local_id[1];
global_id[2] <= global_id_base[2] + bump_local_id[2];
end else begin
if ( bump_local_id[0] ) global_id[0] <= (last_local_id[0] ? (global_id[0] - max_local_id[0]) : (global_id[0] + 2'b01));
if ( bump_local_id[1] ) global_id[1] <= (last_local_id[1] ? (global_id[1] - max_local_id[1]) : (global_id[1] + 2'b01));
if ( bump_local_id[2] ) global_id[2] <= (last_local_id[2] ? (global_id[2] - max_local_id[2]) : (global_id[2] + 2'b01));
end
end
end
end
end
endmodule
// vim:set filetype=verilog:
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Icarus Verilog declares that $realtobits shall return a 64bit
* number that is the normalized IEEE754 encoding of the real value.
* Whatever it takes to get that, it does. It should be easy in
* general, as most modern processors think in IEEE754 floating point
* anyhow.
*/
module main;
real val;
initial begin
val = 0.0;
$display("val=%f (%h)", val, $realtobits(val));
if ($realtobits(val) !== 64'h0000000000000000) begin
$display("FAILED");
$finish;
end
val = 1.0;
$display("val=%f (%h)", val, $realtobits(val));
if ($realtobits(val) !== 64'h3ff0000000000000) begin
$display("FAILED");
$finish;
end
val = 0.5;
$display("val=%f (%h)", val, $realtobits(val));
if ($realtobits(val) !== 64'h3fe0000000000000) begin
$display("FAILED");
$finish;
end
val = 1.5;
$display("val=%f (%h)", val, $realtobits(val));
if ($realtobits(val) !== 64'h3ff8000000000000) begin
$display("FAILED");
$finish;
end
val = 1.125;
$display("val=%f (%h)", val, $realtobits(val));
if ($realtobits(val) !== 64'h3ff2000000000000) begin
$display("FAILED");
$finish;
end
val = 2.6;
$display("val=%f (%h)", val, $realtobits(val));
if ($realtobits(val) !== 64'h4004cccccccccccd) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule // main
|
//`timescale 1ps/1ps
module ict106_axilite_conv #
(
parameter integer C_AXI_ID_WIDTH = 12,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32 // CONSTANT
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire [31:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign read_req = S_AXI_ARVALID & ~write_active & ~busy & ~|areset_d;
assign write_req = (S_AXI_AWVALID & ~read_active & ~busy & ~S_AXI_ARVALID & ~|areset_d) | (write_active & ~busy);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (~ARESETN)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (~ARESETN)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (~ARESETN)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((S_AXI_AWVALID & M_AXI_AWREADY & ~read_req) | (S_AXI_ARVALID & M_AXI_ARREADY & ~write_req))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (~ARESETN) s_axid <= {C_AXI_ID_WIDTH{1'b0}};
else if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, c, d; scanf( %d %d %d %d %d , &n, &a, &b, &c, &d); long long ans = 0; for (int i = 1; i <= n; i++) { int sum = a + b + i; if (sum - a - c <= 0 || sum - a - c > n) continue; if (sum - b - d <= 0 || sum - b - d > n) continue; if (sum - c - d <= 0 || sum - c - d > n) continue; ans++; } ans *= n; printf( %I64d , ans); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:20:46 11/10/2015
// Design Name: clk_interruptor
// Module Name: C:/WINDOWS/system32/Timer/intr_clk_tst.v
// Project Name: Timer
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clk_interruptor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module intr_clk_tst;
// Inputs
reg clk;
reg en;
reg en_cnt;
reg [31:0] limit;
wire [31:0] count;
reg rst;
// Outputs
wire int_0;
// Instantiate the Unit Under Test (UUT)
clk_interruptor uut (
.clk(clk),
.en(en),
.limit(limit),
.count(count),
.int_0(int_0)
);
clk_counter counter(
.clk(clk),
.en(en_cnt),
.rst(rst),
.count(count)
);
initial begin
// Initialize Inputs
clk = 0;
en = 0;
en_cnt = 0;
limit = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
limit = 32'h000000FF;
#13;
en_cnt = 1;
#100;
en = 1;
while(int_0 == 0) #5
#100;
en = 0;
end
always #5 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; const long long int N = 2 * (1e5); const long long int maxo = 1e14; const long long int inf = 1e17; int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int x0, y0, ax, ay, bx, by; cin >> x0 >> y0 >> ax >> ay >> bx >> by; long long int xs, ys, t; cin >> xs >> ys >> t; vector<pair<long long int, long long int> > v; v.push_back({x0, y0}); for (long long int i = 0; i < 100; i++) { if (v.back().first > (inf - bx) / (ax)) break; if (v.back().second > (inf - by) / ay) break; long long int x1 = v.back().first * ax + bx; long long int y1 = v.back().second * ay + by; v.push_back({x1, y1}); } long long int n = v.size(); long long int ans = 0; for (long long int l = 0; l < n; l++) { for (long long int r = l; r < n; r++) { long long int d1 = abs(xs - v[l].first) + abs(ys - v[l].second); long long int d2 = abs(xs - v[r].first) + abs(v[r].second - ys); long long int len = abs(v[l].first - v[r].first) + abs(v[l].second - v[r].second); if (d1 + len <= t) { ans = max(ans, r - l + 1); } if (d2 + len <= t) { ans = max(ans, r - l + 1); } } } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_1_V
`define SKY130_FD_SC_HVL__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__conb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_1_V
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e5 + 1; const long long INF = 1e9 + 1; const long long MOD = 1e9; const long long BITS = 64; const long double EPS = 1e-12; void bye() { cout << n ; exit(0); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, k; cin >> n >> k; string s; cin >> s; vector<int> cnt(k); for (int i = 0; i < (long long)(s).size(); i++) { cnt[s[i] - A ]++; } cout << *min_element((cnt).begin(), cnt.end()) * k; bye(); }
|
#include <bits/stdc++.h> using namespace std; string s; long long pos = -1; const long long N = 5005; long long gundy[N]; long long mex[N]; void game() { long long len = s.length(); long long totXo = 0; gundy[0] = 0; for (long long i = 1; i < N; i++) { for (long long j = 0; j < N; j++) mex[j] = 0; for (long long j = 0; j < i; j++) { long long l = max(0LL, j - 1); long long r = max(0LL, i - j - 2); long long xo = gundy[l] ^ gundy[r]; if (xo < N) mex[xo] = 1; } long long gv = 0; while (gv < N && mex[gv] == 1) gv++; gundy[i] = gv; } for (long long i = 1; i < len - 1; i++) { if (s[i - 1] == s[i + 1]) { long long j = i; while (j + 2 < len && s[j] == s[j + 2]) j++; totXo ^= gundy[j - i + 1]; i = j + 1; } } if (totXo == 0) cout << Second << n ; else { cout << First << n ; for (long long i = 1; i < len - 1; i++) { if (s[i - 1] == s[i + 1]) { long long j = i; while (j + 2 < len && s[j] == s[j + 2]) j++; long long span = j - i + 1; long long remXo = totXo ^ gundy[span]; for (long long k = 0; k < span; k++) { long long l = max(0LL, k - 1LL); long long r = max(0LL, span - k - 2LL); long long xo = gundy[l] ^ gundy[r] ^ remXo; if (xo == 0) { pos = i + k + 1; cout << pos << n ; return; } } i = j + 1; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> s; game(); }
|
/**
* progmem.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
/* program memory */
module progmem(
input wire [ 7 : 0] pc,
output reg [15 : 0] instruction
);
/* ROM subsystem emulation */
always @(pc) begin
case(pc)
8'h00: instruction = 16'h7f00; /* start: ldi 0 */
8'h01: instruction = 16'h0100; /* sto 0x00 */
8'h02: instruction = 16'h0101; /* sto 0x01 */
8'h03: instruction = 16'h7200; /* loop: inc */
8'h04: instruction = 16'h74ff; /* cmp 0xff */
8'h05: instruction = 16'h0a0c; /* jz loop_e */
8'h06: instruction = 16'h0101; /* sto 0x01 */
8'h07: instruction = 16'h0000; /* add 0x00 */
8'h08: instruction = 16'h0100; /* sto 0x00 */
8'h09: instruction = 16'h01ff; /* sto 0xff */
8'h0a: instruction = 16'h0201; /* lo 0x01 */
8'h0b: instruction = 16'h0303; /* jmp loop */
8'h0c: instruction = 16'h030c; /* self: jmp self */
default:
begin
instruction = 16'hffff; /* end: halt */
end
endcase
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
//////////////////////////// **** JAI SHREE RAM **** ////////////////////////// #include<bits/stdc++.h> #include<unordered_map> using namespace std; #define int long long int #define double long double void fun() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin);freopen( output.txt , w , stdout); #endif } int __gcd(int a, int b) {if(b==0) return a; return __gcd(b, a%b);} int poww(int a, int b, int md) {if(b<0) return 0; if(a==0) return 0; int res=1; while(b) {if(b&1){res=(1ll*res*a)%md;}a=(1ll*a*a)%md;b>>=1;}return res;} int divide(int a, int b, int md) {int rr=a*(poww(b, md-2, md));rr%=md;return rr;} ////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////// const int siz = 2e5 + 5; int ans; ////////////////////////////////////////////////////////////////////////////////// int dfs(int node, int gpar, vector<int> g[]) { int minchild = 1e9; int maxchild = 0; vector<int> nodedepth; for(int child : g[node]) { if(child != gpar) { int returnpath = dfs(child, node, g) + 1; minchild = min(minchild, returnpath); maxchild = max(maxchild, returnpath); if(node == 1) { nodedepth.push_back(returnpath); } } } if(node == 1) { sort(nodedepth.begin(), nodedepth.end()); } if(minchild == 1e9) { ans = max(ans, 0ll); return 0; } if(node == 1) { if(g[node].size() > 1) { ans = max(ans, maxchild); minchild = nodedepth[nodedepth.size() - 2]; ans = max(ans, minchild + 1); } else { ans = max(ans, maxchild); } } else { if(g[node].size() > 2) { ans = max(ans, minchild); ans = max(ans, maxchild + 1); } else { ans = max(ans, minchild); } } return minchild; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); fun(); int t; cin >> t; while(t--) { int n, u, v; cin >> n; vector<int> g[n + 1]; for(int i = 1; i < n; i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } ans = INT_MIN; dfs(1, 0, g); cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; const long long M = 1000000007; long long a; int main() { scanf( %I64d , &a); a %= 360; a += 360; long long ans = 0, mx = -1; for (int i = 0; i < 4; i++) { if (mx < abs((a + i * 270) % 360 - 180)) { mx = abs((a + i * 270) % 360 - 180); ans = i; } } printf( %I64d n , ans); }
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_mulAddRecFN_mul#(parameter expWidth = 3, parameter sigWidth = 3);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(formatWidth - 1):0] a, b, expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recA, recB, recExpectOut;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_a(a, recA);
fNToRecFN#(expWidth, sigWidth) fNToRecFN_b(b, recB);
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(expectOut, recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
mulAddRecFN#(expWidth, sigWidth)
mulAddRecFN_mul(
control,
2'b0,
recA,
recB,
{recA[expWidth + sigWidth] ^ recB[expWidth + sigWidth],
{(expWidth + sigWidth){1'b0}}},
roundingMode,
recOut,
exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth) sameRecFN(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'mulAddRecF%0d_mul'", formatWidth);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000,
"%h %h %h %h",
a,
b,
expectOut,
expectExceptionFlags
) == 4
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut || (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'mulAddRecF%0d_mul', control %H, rounding mode %0d:",
formatWidth,
control,
roundingMode
);
end
$write("%H %H", recA, recB);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$write("=> %H %H", recOut, exceptionFlags);
if (formatWidth > 32) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", recExpectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'mulAddRecF%0d_mul', control %H, rounding mode %0d.",
count,
formatWidth,
control,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_mulAddRecF16_mul;
test_mulAddRecFN_mul#(5, 11) test_mulAddRecF16_mul();
endmodule
module test_mulAddRecF32_mul;
test_mulAddRecFN_mul#(8, 24) test_mulAddRecF32_mul();
endmodule
module test_mulAddRecF64_mul;
test_mulAddRecFN_mul#(11, 53) test_mulAddRecF64_mul();
endmodule
module test_mulAddRecF128_mul;
test_mulAddRecFN_mul#(15, 113) test_mulAddRecF128_mul();
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[1009]; int cmp(int a, int b) { return a > b; } int main() { long long T; scanf( %lld , &T); while (T--) { long long n, sum = 0; scanf( %lld , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); sum = sum + a[i]; } sort(a + 1, a + n + 1, cmp); if (a[1] > sum / 2) { printf( T n ); } else if (a[1] <= sum / 2) { if (sum % 2 == 1) { printf( T n ); } else if (sum % 2 == 0) { printf( HL n ); } } } return 0; }
|
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