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#include <bits/stdc++.h> #include<unordered_map> //#pragma GCC optimize(2) #define ll long long #define sc(n) scanf( %d ,&n) #define scl(n) scanf( %lld ,&n) //#define int ll using namespace std; inline int rd() { int x = 0, f = 1; char c = getchar(); while (c != - && c < 48)c = getchar(); if (c == - )f = -1, c = getchar(); while (c > 47)x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return f * x; } const int maxn = 500001, inf = 2147483647; const ll mod = 0 ? 998244353 : 1000000007, linf = 9223372036854775807; const double pi = acos(-1); inline ll mi(ll a, ll b, ll mm = mod) { a %= mm; ll u = 1; while (b) { if (b & 1)u = u * a % mm; a = a * a % mm, b >>= 1; }return u; } inline ll gcd(ll a, ll b) { ll c = a % b; while (c)a = b, b = c, c = a % b; return b; } inline void mem(int* a, int p = 0, int len = maxn) { for (int i = 0; i < len; i++)a[i] = p; } struct p { int r, c; }e[maxn]; static bool cmp(p i, p j) { return i.r < j.r; }; int t, n, m, a[maxn], b[maxn], c[maxn], x, y, xx, yy, su, q, k, u, l, r; string s; int g(int n) { int x = 1, y = n; while (y) x <<= 1, y >>= 1; x >>= 1; return x; } signed main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0);//sf和cin混用会出错 cin >> t; while (t--) { cin >> n >> m; map<int, int>ma; for (int i = 0; i < n; i++) cin >> a[i], ma[a[i]]++; su = 0; while (n) { su++; y = m, x = g(m); while (x) { while (ma[x] && y >= x) y -= x, n--, ma[x]--; x >>= 1; } } cout << su << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_2_V
`define SKY130_FD_SC_HS__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ebufn_2 (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__ebufn base (
.A(A),
.TE_B(TE_B),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ebufn_2 (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__ebufn base (
.A(A),
.TE_B(TE_B),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_2_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "mult.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
/*
r_A=31'h0402050f;
r_B=31'h0301020c;
e_r=31'h000c0006;
c_ww=`w8;
a_op=`aluwmuleu;
*/
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Write-back Mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// CPU's write-back stage of the pipeline ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_wbmux(
// Clock and reset
clk, rst,
// Internal i/f
wb_freeze, rfwb_op,
muxin_a, muxin_b, muxin_c, muxin_d,
muxout, muxreg, muxreg_valid
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Internal i/f
//
input wb_freeze;
input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
input [width-1:0] muxin_a;
input [width-1:0] muxin_b;
input [width-1:0] muxin_c;
input [width-1:0] muxin_d;
output [width-1:0] muxout;
output [width-1:0] muxreg;
output muxreg_valid;
//
// Internal wires and regs
//
reg [width-1:0] muxout;
reg [width-1:0] muxreg;
reg muxreg_valid;
//
// Registered output from the write-back multiplexer
//
always @(posedge clk or posedge rst) begin
if (rst) begin
muxreg <= #1 32'd0;
muxreg_valid <= #1 1'b0;
end
else if (!wb_freeze) begin
muxreg <= #1 muxout;
muxreg_valid <= #1 rfwb_op[0];
end
end
//
// Write-back multiplexer
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
2'b00: muxout = muxin_a;
2'b01: begin
muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
end
2'b10: begin
muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
end
2'b11: begin
muxout = muxin_d + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; int n, x; cin >> n; int i = 0; while (n--) { cin >> x; if (x > b && x < c) i++; } cout << i; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_TB_V
`define SKY130_FD_SC_HD__A32OI_TB_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int bs; int* cnt; int ans; class query { public: int l; int r; int index; }; bool cmp(const query a, const query b) { int s = a.l / bs; int e = b.l / bs; if (s == e) return a.r < b.r; return s < e; } void add(int x) { if (cnt[x] == x) ans--; else if (cnt[x] == x - 1) ans++; cnt[x]++; } void del(int x) { if (cnt[x] == x) ans--; else if (cnt[x] == x + 1) ans++; cnt[x]--; } int main() { int n, m, *a; query* q; scanf( %d %d , &n, &m); bs = sqrt(n); a = (int*)calloc(n + 1, sizeof(int)); cnt = (int*)calloc(n + 1, sizeof(int)); int* an = (int*)calloc(m + 1, sizeof(int)); q = (query*)calloc(m + 1, sizeof(query)); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < m; i++) { scanf( %d %d , &q[i].l, &q[i].r); q[i].index = i; q[i].l--; q[i].r--; } sort(q, q + m, cmp); ans = 0; int l = 0, r = -1; for (int i = 0; i < m; i++) { int left = q[i].l; int right = q[i].r; while (r < right) { r++; if (a[r] < n + 1) add(a[r]); } while (r > right) { if (a[r] < n + 1) del(a[r]); r--; } while (l < left) { if (a[l] < n + 1) del(a[l]); l++; } while (l > left) { l--; if (a[l] < n + 1) add(a[l]); } an[q[i].index] = ans; } for (int i = 0; i < m; i++) printf( %d n , an[i]); free(a); free(an); free(cnt); free(q); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; long long a[n], b[m]; for (long long i = 0; i < n; ++i) { cin >> a[i]; } for (long long i = 0; i < m; ++i) { cin >> b[i]; } long long ans = INF; for (long long i = 0; i < n; ++i) { long long res = -INF; for (long long j = 0; j < n; ++j) { if (i != j) { for (long long k = 0; k < m; ++k) { res = max(res, a[j] * b[k]); } } } ans = min(ans, res); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9; const int len = (int)2e5; int a[len]; int main() { int k, n; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } string s; cin >> s; long long ans = 0; for (int i = 0; i < n; i++) { int j = i; vector<int> v; while (j < n && s[j] == s[i]) { v.push_back(a[j]); j++; } sort(v.begin(), v.end(), greater<int>()); for (int l = 0; l < min(k, (int)v.size()); l++) { ans += v[l]; } i = j - 1; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; void qSort(long long **a, int first, int last) { long long i = first, j = last, x = a[(first + last) / 2][0]; do { while (a[i][0] < x) i++; while (a[j][0] > x) j--; if (i <= j) { if (i < j) { long long tmp0, tmp1; tmp0 = a[i][0]; tmp1 = a[i][1]; a[i][0] = a[j][0]; a[i][1] = a[j][1]; a[j][0] = tmp0; a[j][1] = tmp1; } i++; j--; } } while (i <= j); if (i < last) qSort(a, i, last); if (first < j) qSort(a, first, j); } void build(long long *t, long long *a, int v, int tl, int tr) { if (tl == tr) t[v] = max(a[tl], (long long)0); else { int tm = (tl + tr) / 2; build(t, a, v * 2, tl, tm); build(t, a, v * 2 + 1, tm + 1, tr); t[v] = max(t[v * 2], (long long)0) + max(t[v * 2 + 1], (long long)0); } } long long sum(long long *t, int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (l == tl && r == tr) return t[v]; int tm = (tl + tr) / 2; return sum(t, v * 2, tl, tm, l, min(r, tm)) + sum(t, v * 2 + 1, tm + 1, tr, max(l, tm + 1), r); } int main() { int n; std::cin >> n; long long *t = new long long[4 * n]; long long *forest = new long long[n]; long long **_forest = new long long *[n]; for (int i = 0; i < n; i++) _forest[i] = new long long[2]; long long tmp; for (int i = 0; i < n; i++) { std::cin >> tmp; forest[i] = tmp; _forest[i][0] = tmp; _forest[i][1] = i; } qSort(_forest, 0, n - 1); build(t, forest, 1, 0, n - 1); long long **couples = new long long *[(n / 2) + 1]; for (int i = 0; i < n / 2 + 1; i++) couples[i] = new long long[2]; int couple_count = 0; long long now = -1000000000000000000; int i = 0; while (i < n) { now = _forest[i][0]; int min = n, max = 0; while (i < n && _forest[i][0] == now) { if (_forest[i][1] < min) min = _forest[i][1]; if (_forest[i][1] > max) max = _forest[i][1]; i++; } if (min != max && max != 0) { couples[couple_count][0] = min; couples[couple_count][1] = max; couple_count++; } } long long max = -100000000000000000; int num = 0; for (int i = 0; i < couple_count; i++) { long long su = 0; su += sum(t, 1, 0, n - 1, couples[i][0] + 1, couples[i][1] - 1); su = su + forest[couples[i][0]] + forest[couples[i][1]]; if (su > max) { max = su; num = i; } } std::vector<int> toDelete; int del = 0; del = del + couples[num][0] + (n - 1 - couples[num][1]); for (int i = couples[num][0] + 1; i < couples[num][1]; i++) if (forest[i] < 0) { del++; toDelete.push_back(i); } std::cout << max << << del << std::endl; for (int i = 0; i < couples[num][0]; i++) std::cout << i + 1 << ; for (std::vector<int>::iterator it = toDelete.begin(); it != toDelete.end(); it++) std::cout << *(it) + 1 << ; for (int i = couples[num][1] + 1; i < n; i++) std::cout << i + 1 << ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = numeric_limits<int>::max(); const long long LLINF = numeric_limits<long long>::max(); const unsigned long long ULLINF = numeric_limits<unsigned long long>::max(); vector<vector<int>> g; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<pair<int, int>> a(n); for (int i = 0; i < n; i++) { int d, b; cin >> d >> b; a[i] = {d, b}; } queue<int> q; for (int i = 0; i < n; i++) { if (a[i].first == 1) q.push(i); } vector<pair<int, int>> ans; while (!q.empty()) { int v = q.front(); q.pop(); if (a[v].first == 0) continue; ans.push_back({v, a[v].second}); a[a[v].second].first--; a[a[v].second].second ^= v; if (a[a[v].second].first == 1) q.push(a[v].second); } cout << ans.size() << n ; for (auto k : ans) cout << k.first << << k.second << n ; return 0; }
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////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// dpram.v: Generic dual-ported RAM //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module dpram
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization hex file (don't pass extension), optional
)( input clk , // clock
input WEnb_A , // write enable for port A
input WEnb_B , // write enable for port B
input [`log2(MEMD)-1:0] Addr_A , // address for port A
input [`log2(MEMD)-1:0] Addr_B , // address for port B
input [DATW -1:0] WData_A, // write data for port A
input [DATW -1:0] WData_B, // write data for port B
output reg [DATW -1:0] RData_A, // read data for port A
output reg [DATW -1:0] RData_B // read data for port B
);
// initialize RAM, with zeros if ZERO or file if FILE.
integer i;
reg [DATW-1:0] mem [0:MEMD-1]; // memory array
initial
if (ZERO)
for (i=0; i<MEMD; i=i+1) mem[i] = {DATW{1'b0}};
else
if (FILE != "") $readmemh({FILE,".hex"}, mem);
// PORT A
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (WEnb_A) begin
mem[Addr_A] <= WData_A; // Change into blocking statement (=) to read new data
RData_A <= WData_A; // flow-through
end else
RData_A <= mem[Addr_A]; //Change into blocking statement (=) to read new data
end
// PORT B
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (WEnb_B) begin
mem[Addr_B] <= WData_B; // Change into blocking statement (=) to read new data
RData_B <= WData_B; // flow-through
end else
RData_B <= mem[Addr_B]; //Change into blocking statement (=) to read new data
end
endmodule
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//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module lr_old_IPV4(clk, raddr,waddr, data_in, data_out, we, reset);
input clk;
input [13:2] raddr;
input [13:2] waddr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input reset;
RAMB16_S4_2_altera localram0(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[3:0]),
.wren (we[0]),
.q (data_out[3:0])
);
defparam localram0.init_file = "lr_latest_ipv4_00.mif";
RAMB16_S4_2_altera localram1(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[7:4]),
.wren (we[0]),
.q (data_out[7:4])
);
defparam localram1.init_file = "lr_latest_ipv4_01.mif";
RAMB16_S4_2_altera localram2(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[11:8]),
.wren (we[1]),
.q (data_out[11:8])
);
defparam localram2.init_file = "lr_latest_ipv4_02.mif";
RAMB16_S4_2_altera localram3(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[15:12]),
.wren (we[1]),
.q (data_out[15:12])
);
defparam localram3.init_file = "lr_latest_ipv4_03.mif";
RAMB16_S4_2_altera localram4(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[19:16]),
.wren (we[2]),
.q (data_out[19:16])
);
defparam localram4.init_file = "lr_latest_ipv4_04.mif";
RAMB16_S4_2_altera localram5(
//.aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[23:20]),
.wren (we[2]),
.q (data_out[23:20])
);
defparam localram5.init_file = "lr_latest_ipv4_05.mif";
RAMB16_S4_2_altera localram6(
// .aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[27:24]),
.wren (we[3]),
.q (data_out[27:24])
);
defparam localram6.init_file = "lr_latest_ipv4_06.mif";
RAMB16_S4_2_altera localram7(
// .aclr (reset),
.rdaddress (raddr[13:2]),
.wraddress (waddr[13:2]),
.clock (clk),
.data (data_in[31:28]),
.wren (we[3]),
.q (data_out[31:28])
);
defparam localram7.init_file = "lr_latest_ipv4_07.mif";
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( avx2 ) #pragma GCC optimize( Os ) using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string str; long long i, j, k, x = 0, y = 0, n, m, t, sum = 0, a = 0, b, l, c, d, id; cin >> n; set<long long> s; for (i = 0; i < n; i++) { cin >> a; sum += a; s.insert(a); } x = s.size(); if (x >= 4) cout << -1; else { if (x == 1) cout << 0; else if (x == 2) { a = *next(s.begin(), 0); b = *next(s.begin(), 1); if ((a + b) % 2 != 0) cout << b - a; else cout << (b - a) / 2; } else { a = *next(s.begin(), 0); b = *next(s.begin(), 1); c = *next(s.begin(), 2); t = c - b; if (a + c == b * 2) cout << t; else cout << -1; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int OO = 1e9; const double EPS = 1e-9; template <class T> void _db(const char* dbStr, T e) { cout << dbStr << = << e << endl; } template <class T, class... L> void _db(const char* dbStr, T e, L... r) { while (*dbStr != , ) cout << *dbStr++; cout << = << e << , ; _db(dbStr + 1, r...); } template <class S, class T> ostream& operator<<(ostream& o, const map<S, T>& v) { o << [ ; int i = 0; for (const pair<S, T>& pr : v) o << (!i++ ? : , ) << { << pr.first << : << pr.second << } ; return o << ] ; } template <template <class, class...> class S, class T, class... L> ostream& operator<<(ostream& o, const S<T, L...>& v) { o << [ ; int i = 0; for (const auto& e : v) o << (!i++ ? : , ) << e; return o << ] ; } template <class S, class T> ostream& operator<<(ostream& o, const pair<S, T>& pr) { return o << ( << pr.first << , << pr.second << ) ; } ostream& operator<<(ostream& o, const string& s) { for (const char& c : s) o << c; return o; } template <class T> using V = vector<T>; template <class T> using VV = V<V<T>>; template <class T> using VVV = VV<V<T>>; using ll = long long; using pii = pair<int, int>; using vi = V<int>; using vii = V<pii>; using vvi = VV<int>; using mii = map<int, int>; using umii = unordered_map<int, int>; using si = set<int>; using usi = unordered_set<int>; int n, r, c; V<string> s; vi sum; vvi adj; vi path; pii ans = make_pair(0, 0); bool good(int i, int j) { return sum[j] - sum[i - 1] + (j - i) > c; } void dfs(int u, int p) { path.push_back(u); int l = path[max(int(path.size()) - 1 - r, 0)] - u; true; if (l > ans.first) ans = make_pair(l, u); for (auto& v : adj[u]) { if (v != p) dfs(v, u); } path.pop_back(); } int main() { ios::sync_with_stdio(false); cout.precision(10); cin.tie(0); cin >> n >> r >> c; s.assign(n + 2, ); sum.assign(n + 2, 0); adj.assign(n + 2, vi()); for (int i = 1; i <= n; ++i) { cin >> s[i]; sum[i] = sum[i - 1] + int(s[i].size()); } sum.back() = OO; vi next(n + 2, n + 1); for (int i = 1; i <= n; ++i) { int lo = i, hi = n + 1; while (lo < hi) { int mid = (lo + hi) / 2; if (good(i, mid)) hi = mid; else lo = mid + 1; } true; next[i] = lo; adj[next[i]].push_back(i); } true; for (int i = 1; i <= n + 1; ++i) { if (next[i] == i) dfs(i, i); } true; if (!ans.first) cout << n ; else { for (int l = ans.second, r = ans.second + ans.first, Sz = int(s[l].size()); l < r; ++l) { cout << s[l]; if (l + 1 == r || (l + 1 < r && Sz + 1 + int(s[l + 1].size()) > c)) { cout << n ; Sz = int(s[l + 1].size()); } else { cout << ; Sz += 1 + int(s[l + 1].size()); } } } return 0; }
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#include <bits/stdc++.h> const double eps = (1e-9); using namespace std; int dcmp(long double a, long double b) { return fabsl(a - b) <= eps ? 0 : (a > b) ? 1 : -1; } int getBit(long long num, int idx) { return ((num >> idx) & 1ll) == 1; } int setBit1(int num, int idx) { return num | (1 << idx); } long long setBit0(long long num, int idx) { return num & ~(1ll << idx); } long long flipBit(long long num, int idx) { return num ^ (1ll << idx); } void M() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int countNumBit1(int mask) { int ret = 0; while (mask) { mask &= (mask - 1); ++ret; } return ret; } string st; int n; int main() { M(); cin >> n >> st; char c1, c2, c3, F, S, T; int mi = INT_MAX; for (int i = 1; i <= 3; i++) { for (int j = 1; j <= 3; j++) { for (int k = 1; k <= 3; k++) { int cnt1 = 0, cnt2 = 0, cnt3 = 0; if (i == j || i == k || j == k) continue; c1 = (i == 1 ? R : (i == 2 ? B : G )); c2 = (j == 1 ? R : (j == 2 ? B : G )); c3 = (k == 1 ? R : (k == 2 ? B : G )); for (int l = 0; l < n; l += 3) { if (st[l] != c1) cnt1++; } for (int l = 1; l < n; l += 3) { if (st[l] != c2) cnt2++; } for (int l = 2; l < n; l += 3) { if (st[l] != c3) cnt3++; } long long ans = cnt1 + cnt2 + cnt3; if (ans < mi) { mi = ans; F = c1; S = c2; T = c3; } } } } for (int l = 0; l < n; l += 3) { st[l] = F; } for (int l = 1; l < n; l += 3) { st[l] = S; } for (int l = 2; l < n; l += 3) { st[l] = T; } cout << mi << endl << st << endl; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 2e5 + 5; inline int read() { int res = 0, ch, flag = 0; if ((ch = getchar()) == - ) flag = 1; else if (ch >= 0 && ch <= 9 ) res = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) res = res * 10 + ch - 0 ; return flag ? -res : res; } int n, m, cnt; struct node { int x, y; }; node p[N]; vector<int> data; int bit[N], t[N]; long long ans; void add(int i) { while (i <= m) { bit[i]++; i += i & -i; } } int sum(int i) { int res = 0; while (i > 0) { res += bit[i]; i -= i & -i; } return res; } bool cmp(node a, node b) { if (a.y != b.y) return a.y > b.y; return a.x < b.x; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &p[i].x, &p[i].y); data.push_back(p[i].x); } sort(data.begin(), data.end()); data.erase(unique(data.begin(), data.end()), data.end()); m = data.size(); for (int i = 1; i <= n; i++) p[i].x = lower_bound(data.begin(), data.end(), p[i].x) - data.begin() + 1; sort(p + 1, p + n + 1, cmp); for (int i = 1; i <= n;) { int j = i; while (j < n && p[j].y == p[j + 1].y) j++; t[i - 1] = 0; for (int k = i; k <= j; k++) { if (sum(p[k].x) - sum(p[k].x - 1) == 0) { add(p[k].x); cnt++; } t[k] = sum(p[k].x); } for (int k = i; k <= j; k++) ans += 1LL * (t[k] - t[k - 1]) * (cnt - t[k] + 1); i = j + 1; } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10; vector<int> tree[N]; int cnt[N]; int n, mx1, mx2; bool centr[N], ans[N]; int dfs(int v, int p = -1) { int u; cnt[v] = 1; for (int i = 0; i < tree[v].size(); i++) { u = tree[v][i]; if (u == p) continue; cnt[v] += dfs(u, v); } return cnt[v]; } void find_centr(int v, int p = -1) { int u; bool ok = (n - cnt[v]) <= n / 2; for (int i = 0; i < tree[v].size(); i++) { u = tree[v][i]; if (u == p) continue; find_centr(u, v); if (cnt[u] > n / 2) ok = false; } if (ok) centr[v] = 1; return; } void calc(int v, int p = -1, int mxC = -1) { int u; if (n - cnt[v] - mxC <= n / 2) ans[v] = true; else return; for (int i = 0; i < tree[v].size(); i++) { u = tree[v][i]; if (u == p) continue; calc(u, v, mxC); } return; } void solveC(int aim) { for (int i = 1; i <= n; i++) cnt[i] = 0; dfs(aim); mx1 = -1, mx2 = -1; int u = 0; for (int i = 0; i < tree[aim].size(); i++) { u = tree[aim][i]; if (cnt[u] > mx1) { mx2 = mx1; mx1 = cnt[u]; } else if (cnt[u] > mx2) mx2 = cnt[u]; } for (int i = 0; i < tree[aim].size(); i++) { u = tree[aim][i]; if (cnt[u] == mx1 && (cnt[u] != n / 2 || n / 2 * 2 != n)) calc(u, aim, mx2); else calc(u, aim, mx1); } } void solve() { cin >> n; int b, e; for (int i = 0; i < n - 1; i++) { scanf( %d %d n , &b, &e); tree[b].push_back(e); tree[e].push_back(b); } dfs(1); find_centr(1); for (int i = 1; i <= n; i++) { if (centr[i]) solveC(i); } for (int i = 1; i <= n; i++) if (centr[i] || ans[i]) printf( 1 ); else printf( 0 ); } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int num[100009]; int main() { int n; while (cin >> n) { for (int i = 0; i < n; ++i) cin >> num[i]; long long sum = n; long long count = 1; for (int i = 1; i < n; ++i) { if (num[i] == num[i - 1]) count++; else { sum += ((count - 1) * (count)) / 2; count = 1; } } if (count != 0) sum += ((count - 1) * (count)) / 2; cout << sum << endl; } return 0; }
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// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 18
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge reset, posedge wr, posedge rd)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, h, k, i, j, a[100100], pkp = 0, tmp, p, ans = 0; double d; scanf( %lld %lld %lld , &n, &h, &k); for (i = 0; i < n; i++) scanf( %lld , &a[i]); for (i = 0; i < n; i++) { if (pkp + a[i] <= h) { pkp += a[i]; } else { tmp = h - a[i]; p = pkp - tmp; d = ceil((double)p / (double)k); ans += (long long)d; pkp -= d * k; if (pkp < 0) pkp = 0; pkp += a[i]; } } d = ceil((double)pkp / (double)k); ans += (long long)d; printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 105; int l[M], r[M], t[M], c[M], res[M], p[M]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; ++i) { cin >> l[i] >> r[i] >> t[i] >> c[i]; } for (int i = 1; i <= n; ++i) p[i] = INT_MAX; for (int i = 0; i < m; ++i) for (int j = l[i]; j <= r[i]; ++j) if (t[i] < p[j]) p[j] = t[i], res[j] = i; int sum = 0; for (int i = 1; i <= n; ++i) if (p[i] != INT_MAX) sum += c[res[i]]; cout << sum << endl; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_25ns_32_3_MAC3S_1(clk, ce, a, b, p);
input clk;
input ce;
input[8 - 1 : 0] a; // synthesis attribute keep a "true"
input[25 - 1 : 0] b; // synthesis attribute keep b "true"
output[32 - 1 : 0] p;
reg [8 - 1 : 0] a_reg0;
reg [25 - 1 : 0] b_reg0;
wire [32 - 1 : 0] tmp_product;
reg [32 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_25ns_32_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
image_filter_mul_8ns_25ns_32_3_MAC3S_1 image_filter_mul_8ns_25ns_32_3_MAC3S_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1000000000000000; const int mod = 1000000007; int n, m, k; int s[1000010]; long long a[1000010]; bool pos[1000010]; int lst[1000010]; long long get(int l) { int r = 0; int i = -1; long long res = 0; while (r < n) { if (lst[r] <= i) { return inf; } i = lst[r]; r = lst[r] + l; ++res; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> k; for (int i = 0; i < m; i++) { cin >> s[i]; } for (int i = 0; i < k; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { pos[i] = true; } for (int i = 0; i < m; i++) { pos[s[i]] = false; } for (int i = 0; i < n; i++) { if (pos[i]) { lst[i] = i; } else if (i) { lst[i] = lst[i - 1]; } else lst[i] = -1; } long long ans = inf; for (int i = 0; i < k; i++) { long long t = get(i + 1); if (t != inf) { ans = min(ans, a[i] * t); } } if (ans == inf) { ans = -1; } cout << ans << n ; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Attribute Controller
// File : attr.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
// Serial Shifter
// attr_reg_dec
// final_cursor
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module attr
(
input h_reset_n, // power on reset
input [15:0] h_io_addr, // host address used for IO decoding
input h_dec_3cx, // IO decode of address range 3cx
input h_iowr, // IO write cycle
input h_iord, // IO read cycle
input h_hclk, // Host clock
input c_shift_ld, // Load signal to Attr serializer
input c_shift_ld_pulse, // Load signal to Attr serializer
input c_shift_clk, // Attribute serializer shift clock
input c_dclk_en, // dot clock
input c_9dot,
input [36:0] m_att_data, /* Memory data containing pixel
* information to the attribute
* module. */
input m_sr04_b3, // chain-4
input c_cr24_rd,
input c_cr26_rd,
input c_attr_de, // display enable for overscan
input c_t_vsync, // Vertical sync.
input c_dec_3ba_or_3da,
input c_cr0b_b5,
input c_cr0b_b6,
input c_cr0a_b5, // Disable Text cursor
input g_gr05_b5, // Serializer shift mode control bit
input g_gr05_b6, // Indicates 256 color mode
input t_crt_clk,
input h_io_16,
input [15:0] h_io_dbus,
input pre_load,
output [7:0] reg_ar10,
output [7:0] reg_ar11,
output [7:0] reg_ar12,
output [7:0] reg_ar13,
output [7:0] reg_ar14,
output [5:0] dport_out,
output [7:0] attr_index,
output [7:0] cr24_26_dbus,
output a_ready_n, // Ready from attribute module
output a_ar10_b6, // Pixel double control bit
output a_ar10_b5, // Screen B pixel pan enable control
output a_ar10_b0, // Graphics mode bit
output a_ar13_b3,
output a_ar13_b2,
output a_ar13_b1,
output a_ar13_b0,
output a_arx_b5, // Video display enable control bit
output a_is01_b5, // Video Diagnostic (pixel data) bit
output a_is01_b4, // Video Diagnostic (pixel data) bit
output [7:0] a_t_pix_data, // pixel data to RAMDAC VGA port
output attr_mod_rd_en_lb,
output attr_mod_rd_en_hb,
output color_256_mode // Mode 13 indicator
);
wire ar12_b4;
wire cursor_blink_rate;
wire finalcursor;
wire pal_reg_bank_b7_b6_rd;
wire [15:0] attr_io_dbus;
wire m_att_data_b32 = m_att_data[32];
wire char_blink_rate;
wire attr_data_wr;
wire dport_we;
final_cursor FC
(
.h_reset_n (h_reset_n),
.t_crt_clk (t_crt_clk),
.c_shift_ld (c_shift_ld_pulse),
.m_att_data_b32 (m_att_data_b32),
.c_cr0b_b6 (c_cr0b_b6),
.c_cr0b_b5 (c_cr0b_b5),
.c_cr0a_b5 (c_cr0a_b5),
.c_t_vsync (c_t_vsync),
.ar12_b4 (ar12_b4),
.cursor_blink_rate (cursor_blink_rate),
.char_blink_rate (char_blink_rate),
.finalcursor (finalcursor)
);
serial_shifter SS
(
.h_reset_n (h_reset_n),
.h_hclk (h_hclk),
.h_io_wr (h_iowr),
.h_io_16 (h_io_16),
.h_io_addr (h_io_addr),
.a_attr_index (attr_index[5:0]),
.attr_data_wr (attr_data_wr),
.g_gr05_b5 (g_gr05_b5),
.g_gr05_b6 (g_gr05_b6),
.c_shift_ld (c_shift_ld),
.c_shift_clk (c_shift_clk),
.c_dclk_en (c_dclk_en),
.c_9dot (c_9dot),
.m_att_data (m_att_data),
.m_sr04_b3 (m_sr04_b3),
.cursor_blink_rate (cursor_blink_rate),
.char_blink_rate (char_blink_rate),
.final_cursor (finalcursor),
.pal_reg_bank_b7_b6_rd (pal_reg_bank_b7_b6_rd),
.c_attr_de (c_attr_de),
.t_crt_clk (t_crt_clk),
.h_io_dbus (h_io_dbus),
.pre_load (pre_load),
.dport_we (dport_we),
//####################### OUTPUTS #######################################
.reg_ar10 (reg_ar10),
.reg_ar11 (reg_ar11),
.reg_ar12 (reg_ar12),
.reg_ar13 (reg_ar13),
.reg_ar14 (reg_ar14),
.dport_out (dport_out),
.ar12_b4 (ar12_b4),
.a_ar10_b6 (a_ar10_b6),
.a_ar10_b5 (a_ar10_b5),
.a_ar10_b0 (a_ar10_b0),
.a_ar13_b3 (a_ar13_b3),
.a_ar13_b2 (a_ar13_b2),
.a_ar13_b1 (a_ar13_b1),
.a_ar13_b0 (a_ar13_b0),
.a_is01_b5 (a_is01_b5),
.a_is01_b4 (a_is01_b4),
.a_t_pix_data (a_t_pix_data),
.color_256_mode (color_256_mode)
);
attr_reg_dec AD
(
.h_reset_n (h_reset_n),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_dec_3cx (h_dec_3cx),
.h_io_addr (h_io_addr),
.c_cr24_rd (c_cr24_rd),
.c_cr26_rd (c_cr26_rd),
.c_dec_3ba_or_3da (c_dec_3ba_or_3da),
.h_io_16 (h_io_16),
.h_hclk (h_hclk),
.h_io_dbus (h_io_dbus),
//####################### OUTPUTS #######################################
.attr_data_wr (attr_data_wr),
.dport_we (dport_we),
.attr_index (attr_index),
.int_io_dbus (cr24_26_dbus),
.a_ready_n (a_ready_n),
.attr_mod_rd_en_hb (attr_mod_rd_en_hb),
.attr_mod_rd_en_lb (attr_mod_rd_en_lb),
.a_arx_b5 (a_arx_b5),
.pal_reg_bank_b7_b6_rd (pal_reg_bank_b7_b6_rd)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> const long long inf = 0x3f3f3f3f; using namespace std; const long long maxn = 2e5 + 100; long long n, k; long long a[maxn]; int32_t main() { long long q; scanf( %lld , &(q)); while (q--) { scanf( %lld%lld , &(n), &(k)); long long maxx = 0, minn = 0x3f3f3f3f; for (long long i = (1); i <= (n); i++) { scanf( %lld , &(a[i])); if (maxx < a[i]) maxx = a[i]; if (minn > a[i]) minn = a[i]; } long long x = minn + k; if (abs(x - maxx) > k) printf( -1 ); else printf( %lld , (x)); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn(1e5 + 5); struct circle { int a, b; long long h; circle(){}; circle(int x) : a(0), b(x), h(0) {} inline void input() { cin >> a >> b >> h; } bool operator<(const circle &t) const { return b == t.b ? (a < t.a) : b < t.b; } } rings[maxn]; long long tree[maxn << 2]; void build(int p, int l, int r) { if (l == r) { tree[p] = rings[l].h; return; } int mid = l + r >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); tree[p] = max(tree[p << 1], tree[p << 1 | 1]); } void update(int p, int l, int r, int x) { if (l == r) { tree[p] = rings[x].h; return; } int mid = l + r >> 1; if (x <= mid) update(p << 1, l, mid, x); else update(p << 1 | 1, mid + 1, r, x); tree[p] = max(tree[p << 1], tree[p << 1 | 1]); } long long query(int p, int l, int r, int x, int y) { if (x <= l && r <= y) return tree[p]; int mid = l + r >> 1; if (y <= mid) return query(p << 1, l, mid, x, y); else if (x > mid) return query(p << 1 | 1, mid + 1, r, x, y); else { long long a = query(p << 1, l, mid, x, mid); long long b = query(p << 1 | 1, mid + 1, r, mid + 1, y); return max(a, b); } } int main() { int n; while (cin >> n) { for (int i = 1; i <= n; i++) rings[i].input(); sort(rings + 1, rings + n + 1); build(1, 1, n); for (int i = 2, j; i <= n; i++) { j = lower_bound(rings + 1, rings + i, circle(rings[i].a + 1)) - rings; if (j >= i) continue; rings[i].h += query(1, 1, n, j, i - 1); update(1, 1, n, i); } long long ans = 0; for (int i = 1; i <= n; i++) ans = max(ans, rings[i].h); cout << ans << endl; } return 0; }
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module LEDSpartan3StarterKit(
// Clock Sources
CLK50MHZ,
SOCKET,
// Fast, Asynchronous SRAM
SRAM_A,
SRAM_WE_X,
SRAM_OE_X,
SRAM_IO_A,
SRAM_CE_A_X,
SRAM_LB_A_X,
SRAM_UB_A_X,
SRAM_IO_B,
SRAM_CE_B_X,
SRAM_LB_B_X,
SRAM_UB_B_X,
// Four-Digit, Saven-Segment LED Display
LED_AN,
LED_A,
LED_B,
LED_C,
LED_D,
LED_E,
LED_F,
LED_G,
LED_DP,
// Switch
SW,
// Button
BTN,
// LED
LD,
// VGA Port
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
// PS2
PS2C,
PS2D,
// RS-232 Serial Port
RXD,
TXD,
RXDA,
TXDA,
// Platform Flash (XCF02S Serial PROM)
DIN,
INIT_B,
RCLK);
input CLK50MHZ;
input SOCKET;
output [17:0] SRAM_A;
output SRAM_WE_X;
output SRAM_OE_X;
inout [15:0] SRAM_IO_A;
output SRAM_CE_A_X;
output SRAM_LB_A_X;
output SRAM_UB_A_X;
inout [15:0] SRAM_IO_B;
output SRAM_CE_B_X;
output SRAM_LB_B_X;
output SRAM_UB_B_X;
output [ 3:0] LED_AN;
output LED_A;
output LED_B;
output LED_C;
output LED_D;
output LED_E;
output LED_F;
output LED_G;
output LED_DP;
input [ 7:0] SW;
input [ 3:0] BTN;
output [ 7:0] LD;
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
input PS2C;
input PS2D;
input RXD;
output TXD;
input RXDA;
output TXDA;
input DIN;
output INIT_B;
output RCLK;
wire clk;
wire rst_x;
reg r_clk3hz;
reg [23:0] r_clk3hz_count;
assign SRAM_A = 18'h00000;
assign SRAM_WE_X = 1'b0;
assign SRAM_OE_X = 1'b1;
assign SRAM_IO_A = 16'hffff;
assign SRAM_CE_A_X = 1'b1;
assign SRAM_LB_A_X = 1'b1;
assign SRAM_UB_A_X = 1'b1;
assign SRAM_IO_B = 16'hffff;
assign SRAM_CE_B_X = 1'b1;
assign SRAM_LB_B_X = 1'b1;
assign SRAM_UB_B_X = 1'b1;
assign LD = SW | { 1'b0, BTN, PS2D, PS2C, SOCKET };
assign VGA_R = 1'b0;
assign VGA_G = 1'b0;
assign VGA_B = 1'b0;
assign VGA_HS = 1'b1;
assign VGA_VS = 1'b1;
assign TXD = RXD;
assign TXDA = RXDA;
assign INIT_B = DIN;
assign RCLK = DIN;
assign clk = CLK50MHZ;
assign rst_x = !BTN[3];
assign LED_AN = 4'b1110;
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_clk3hz_count <= 24'h000000;
r_clk3hz <= 1'b1;
end else begin
r_clk3hz_count <= r_clk3hz_count + 24'h000001;
if (r_clk3hz_count == 24'h000000) begin
r_clk3hz <= !r_clk3hz;
end
end
end
LEDSample led(
.clk (r_clk3hz),
.rst_x(rst_x ),
.o_a (LED_A ),
.o_b (LED_B ),
.o_c (LED_C ),
.o_d (LED_D ),
.o_e (LED_E ),
.o_f (LED_F ),
.o_g (LED_G ),
.o_dp (LED_DP ));
endmodule // LEDSpartan3StarterKit
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int hr = s[0] - 0 ; hr = hr * 10 + s[1] - 0 ; if (hr >= 12) hr -= 12; int min = s[3] - 0 ; min = min * 10 + s[4] - 0 ; double b = min * 6; double a = ((double)hr + (double)min / 60) * 30; printf( %.9lf %.9lf , a, b); }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.01
// \ \ Filename: kcpsm3_int_test.v
// / / Date Last Modified: 08/04/2004
// /___/ /\ Date Created: 06/xx/2003
// \ \ / \
// \___\/\___\
//
//Device: Xilinx
//Purpose:
// Interrupt test for KCPSM3
//Reference:
// None
//Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, 06/xx/2003.
// Rev 1.01 - sus - Converted to verilog, 08/04/2004.
////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//////////////////////////////////////////////////////////////////////////////////
module kcpsm3_int_test
( counter,
waveforms,
interrupt_event,
clk );
output[7:0] counter;
output[7:0] waveforms;
input interrupt_event;
input clk;
reg [7:0] counter;
reg [7:0] waveforms;
wire interrupt_event;
wire clk;
//
//----------------------------------------------------------------------------------
//
// Start of test achitecture
//
//
//----------------------------------------------------------------------------------
// Signals used to connect KCPSM3 to program ROM and I/O logic
wire [9:0] address;
wire [17:0] instruction;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
wire reset;
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Start of circuit description
//
// Inserting KCPSM3 and the program memory
kcpsm3 processor
( .address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(reset),
.clk(clk));
int_test program
( .address(address),
.instruction(instruction),
.clk(clk));
// Unused inputs on processor
assign in_port = 8'b 00000000;
assign reset = 1'b 0;
// Adding the output registers to the processor
always @(posedge clk) begin
// waveform register at address 02
if(port_id[1] == 1'b 1 && write_strobe == 1'b 1)
begin
waveforms <= out_port;
end
// Interrupt Counter register at address 04
if(port_id[2] == 1'b 1 && write_strobe == 1'b 1)
begin
counter <= out_port;
end
end
// Adding the interrupt input
// Note that the initial value of interrupt (low) is
// defined at signal declaration.
always @(posedge clk) begin
if(interrupt_ack == 1'b 1)
begin
interrupt <= 1'b 0;
end
else if(interrupt_event == 1'b 1)
begin
interrupt <= 1'b 1;
end
else
begin
interrupt <= interrupt;
end
end
endmodule
//----------------------------------------------------------------------------------
//
// END OF FILE KCPSM3_INT_TEST.V
//
//----------------------------------------------------------------------------------
|
`default_nettype none
module latch_002_gate (dword, vect, sel, st);
output reg [63:0] dword;
input wire [7:0] vect;
input wire [7:0] sel;
input st;
always @*
case (|(st))
1'b 1:
case ((((8)*(sel)))+(0))
0:
dword[7:0] <= vect[7:0];
1:
dword[8:1] <= vect[7:0];
2:
dword[9:2] <= vect[7:0];
3:
dword[10:3] <= vect[7:0];
4:
dword[11:4] <= vect[7:0];
5:
dword[12:5] <= vect[7:0];
6:
dword[13:6] <= vect[7:0];
7:
dword[14:7] <= vect[7:0];
8:
dword[15:8] <= vect[7:0];
9:
dword[16:9] <= vect[7:0];
10:
dword[17:10] <= vect[7:0];
11:
dword[18:11] <= vect[7:0];
12:
dword[19:12] <= vect[7:0];
13:
dword[20:13] <= vect[7:0];
14:
dword[21:14] <= vect[7:0];
15:
dword[22:15] <= vect[7:0];
16:
dword[23:16] <= vect[7:0];
17:
dword[24:17] <= vect[7:0];
18:
dword[25:18] <= vect[7:0];
19:
dword[26:19] <= vect[7:0];
20:
dword[27:20] <= vect[7:0];
21:
dword[28:21] <= vect[7:0];
22:
dword[29:22] <= vect[7:0];
23:
dword[30:23] <= vect[7:0];
24:
dword[31:24] <= vect[7:0];
25:
dword[32:25] <= vect[7:0];
26:
dword[33:26] <= vect[7:0];
27:
dword[34:27] <= vect[7:0];
28:
dword[35:28] <= vect[7:0];
29:
dword[36:29] <= vect[7:0];
30:
dword[37:30] <= vect[7:0];
31:
dword[38:31] <= vect[7:0];
32:
dword[39:32] <= vect[7:0];
33:
dword[40:33] <= vect[7:0];
34:
dword[41:34] <= vect[7:0];
35:
dword[42:35] <= vect[7:0];
36:
dword[43:36] <= vect[7:0];
37:
dword[44:37] <= vect[7:0];
38:
dword[45:38] <= vect[7:0];
39:
dword[46:39] <= vect[7:0];
40:
dword[47:40] <= vect[7:0];
41:
dword[48:41] <= vect[7:0];
42:
dword[49:42] <= vect[7:0];
43:
dword[50:43] <= vect[7:0];
44:
dword[51:44] <= vect[7:0];
45:
dword[52:45] <= vect[7:0];
46:
dword[53:46] <= vect[7:0];
47:
dword[54:47] <= vect[7:0];
48:
dword[55:48] <= vect[7:0];
49:
dword[56:49] <= vect[7:0];
50:
dword[57:50] <= vect[7:0];
51:
dword[58:51] <= vect[7:0];
52:
dword[59:52] <= vect[7:0];
53:
dword[60:53] <= vect[7:0];
54:
dword[61:54] <= vect[7:0];
55:
dword[62:55] <= vect[7:0];
56:
dword[63:56] <= vect[7:0];
57:
dword[63:57] <= vect[7:0];
58:
dword[63:58] <= vect[7:0];
59:
dword[63:59] <= vect[7:0];
60:
dword[63:60] <= vect[7:0];
61:
dword[63:61] <= vect[7:0];
62:
dword[63:62] <= vect[7:0];
63:
dword[63:63] <= vect[7:0];
endcase
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; bool flag; long long Max = -1e18, tpMax = -1e18, dep[600005], a[600005]; int n, m, sz[600005], In[600005], TOT, LA[600005], NE[600005 << 1], EN[600005 << 1]; long long LE[600005 << 1]; void Link(int x, int y, int z) { EN[++TOT] = y; LE[TOT] = z; NE[TOT] = LA[x]; LA[x] = TOT; EN[++TOT] = x; LE[TOT] = z; NE[TOT] = LA[y]; LA[y] = TOT; } void pre_dfs(int x, int fa) { if (x == n) In[x] = x; int i, y; sz[x] = 1; long long tp = -1e18, ttp = -1e18; for (i = LA[x]; i; i = NE[i]) { y = EN[i]; if (y == fa) continue; dep[y] = dep[x] + LE[i]; pre_dfs(y, x); sz[x] += sz[y]; if (In[y]) In[x] = y; else a[x] = LE[i]; if (a[y] && In[y]) tp = max(tp, a[y] - dep[y]); if (In[y]) ttp = max(ttp, a[y] - dep[y]); } if (sz[x] - sz[In[x]] > 2) flag = 1; if (x == n && sz[x] > 2) flag = 1; if (In[x]) { Max = max(Max, a[x] + dep[x] + max(tpMax, tp)); if (a[x]) Max = max(Max, a[x] + dep[x] + ttp); for (i = LA[x]; i; i = NE[i]) { y = EN[i]; if (y == fa) continue; if (In[y]) tpMax = max(tpMax, a[y] - dep[y]); } } } int main() { int i, j, k, x, y, z; long long t; scanf( %d%d , &n, &m); for (i = 1; i < n; i++) { scanf( %d%d%d , &x, &y, &z); Link(x, y, z); } pre_dfs(1, 0); for (i = 1; i <= m; i++) { scanf( %I64d , &t); if (flag || t + Max >= 0) printf( %I64d n , dep[n]); else printf( %I64d n , dep[n] + t + Max); } return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_solo_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
Require Import Iron.Language.SystemF2Data.Exp.
Require Import Iron.Language.SystemF2Data.Step.Step.
(********************************************************************)
(* If we have a well typed case match on a data object then there
is a case alternative corresponding to that data constructor *)
Lemma getAlt_has
: forall ds dc ts xs alts t
, DEFSOK ds
-> TYPE ds nil nil (XCase (XCon dc ts xs) alts) t
-> (exists x, getAlt dc alts = Some (AAlt dc x)).
Proof.
intros.
eapply getAlt_exists.
inverts_type.
norm.
eapply H8.
have (getCtorOfType (TCon tc) = Some tc) as HC.
erewrite getCtorOfType_makeTApps in H5; eauto.
inverts H5.
eauto.
Qed.
Hint Resolve getAlt_has.
(* Well typed primitives applied to values can always progress. *)
Lemma progress_prim
: forall ds p tsArg tResult xs
, primDef p = DefPrim tsArg tResult
-> Forall2 (TYPE ds nil nil) xs tsArg
-> Forall wnfX xs
-> (exists x, STEP (XPrim p xs) x).
Proof.
intros.
destruct p.
- Case "PAdd".
snorm. inverts H.
inverts H0. inverts H5. inverts H6.
eapply value_form_nat in H4.
+ destruct H4 as [n]. subst.
eapply value_form_nat in H3.
* destruct H3 as [n']. subst.
exists (XLit (LNat (n + n'))).
eauto.
* have (closedX x0).
eauto.
+ have (closedX x).
eauto.
- Case "PIsZero".
snorm. inverts H.
inverts H0. inverts H5.
eapply value_form_nat in H4.
+ destruct H4 as [n]. subst.
exists (XLit (LBool (beq_nat n 0))).
eauto.
+ have (closedX x).
eauto.
Qed.
Hint Resolve progress_prim.
(********************************************************************)
(* A well typed expression is either a well formed value,
or can transition to the next state. *)
Theorem progress
: forall ds x t
, DEFSOK ds
-> TYPE ds nil nil x t
-> value x \/ (exists x', STEP x x').
Proof.
intros. gen t.
induction x using exp_mutind with
(PA := fun a => a = a);
intros.
(*************************************)
- Case "XVar".
(* Variables aren't values. *)
nope.
(*************************************)
- Case "XLAM".
(* Closed type abstractions are already values. *)
left. apply type_wfX in H0. auto.
(*************************************)
- Case "XAPP".
inverts keep H0.
edestruct IHx. eauto.
(* If the function part of a type application is a value then
is can only step if it is a type abstraction. *)
+ SCase "x value".
right.
inverts H1.
inverts H3; try nope.
(* The function part is a type abstraction,
so we can do the substitution. *)
* SSCase "x = XLAM".
exists (substTX 0 t2 x1).
eapply EsLAMAPP.
(* Can't happen, fully applied data constructors never have
quantified types. *)
* SSCase "x = XCon".
inverts_type.
have (takeTCon (TCon tc0) = takeTCon (TForall t0))
by (eapply makeTApps_takeTCon; eauto).
snorm. nope.
(* Can't happen, literals never have quantified types. *)
* SSCase "x = XLit".
destruct l0; snorm; congruence.
(* The function part can take a step. *)
+ SCase "x steps".
right.
dest x'.
exists (XAPP x' t2).
lets D: EsContext XcAPP H1.
eauto.
(*************************************)
(* Closed function abstractions are already values. *)
- Case "XLam".
left.
eapply type_wfX in H0. auto.
(*************************************)
- Case "XApp".
right.
inverts_type.
edestruct IHx1; eauto.
+ SCase "value x1".
edestruct IHx2; eauto.
* SSCase "value x2".
have (exists t x, x1 = XLam t x) as HF.
destruct HF as [t11].
destruct H2 as [x12].
subst.
exists (substXX 0 x2 x12).
apply EsLamApp; eauto.
* SSCase "x2 steps".
destruct H1 as [x2'].
exists (XApp x1 x2'). auto.
+ SCase "x1 steps".
destruct H0 as [x1'].
exists (XApp x1' x2).
eapply (EsContext (fun xx => XApp xx x2)); auto.
(*************************************)
- Case "XCon".
inverts_type.
(* All ctor args are either wnf or can step. *)
assert (Forall (fun x => wnfX x \/ (exists x', STEP x x')) xs) as HWS.
{ repeat nforall. intros.
have (exists t, TYPE ds nil nil x t).
destruct H2 as [t'].
have (value x \/ (exists x', STEP x x')).
intuition.
}
(* All ctor args are wnf, or there is a context where one can step *)
lets D: (@exps_ctx_run exp exp) HWS.
inverts D.
(* All ctor args are wnf *)
+ left.
have (Forall (wfT 0) ts)
by (rrwrite (0 = length (@nil ki));
eapply kind_wfT_Forall2; eauto).
have (Forall (wfX 0 0) xs)
by (have (0 = length (@nil ki)) as HKL;
rewrite HKL at 1;
rrwrite (0 = length (@nil ty)); eauto).
eauto.
+ (* There is a context where one ctor arg can step *)
right.
dest C. dest x'. rip.
lets D: step_context_XCon_exists H2 H4.
destruct D as [x'']. eauto.
(*************************************)
- Case "XCase".
right.
inverts keep H1.
have (value x \/ (exists x', STEP x x')) as HS.
inverts HS.
(* Scrutinee is a value *)
+ SCase "x value".
clear IHx.
(* Consider the forms of the scrutinee. *)
destruct x; nope.
(* Can't happen, TForall is not a data type. *)
* SSCase "XCase (XLAM x) alts".
have (exists t', tObj = TForall t').
dest t'. subst. nope.
(* Can't happen, tFun is not a data type. *)
* SSCase "XCase (XLam t x) alts".
have (exists t11 t12, tObj = tFun t11 t12).
dest t11. dest t12. subst.
unfold tFun in H6. simpl in H6. inverts H6.
have (DEFOK ds (DefDataType TyConFun ks dcs)) as HD.
inverts HD. nope.
(* When we have a well typed case match on some data object,
then there is a corresponding alternative. *)
* SSCase "XCase (XCon d ts xs) alts".
have (exists x, getAlt d aa = Some (AAlt d x)).
dest x. exists (substXXs 0 l0 x).
eapply EsCaseAlt; eauto.
(* Can't happen, prim types are not data types. *)
* SSCase "XCase (XLit l) alts".
inverts_type.
have HD: (DEFOK ds (DefDataType tcObj ks dcs)).
inverts HD.
destruct l; snorm; nope.
(* Discriminant steps *)
+ SCase "x steps".
destruct H2 as [x'].
exists (XCase x' aa).
lets D: EsContext XcCase; eauto.
(*************************************)
- Case "XPrim".
inverts_type.
right.
(* All prim args are either wnf or can step. *)
assert (Forall (fun x => wnfX x \/ (exists x', STEP x x')) xs) as HWS.
{ repeat nforall. intros.
have (exists t, TYPE ds nil nil x t).
destruct H2 as [t'].
eapply H0 in H1.
intuition. eauto.
}
(* All ctor args are wnf, or there is a context where one can step. *)
lets D: (@exps_ctx_run exp exp) HWS. inverts D.
(* All arguments are wnf. *)
+ eapply progress_prim; eauto.
(* One of the arguments can step. *)
+ dest C. dest x'. rip.
lets D: step_context_XPrim_exists H2 H5.
destruct D as [x'']. eauto.
(*************************************)
- Case "XLit".
(* Literals are already values. *)
inverts_type.
left. eauto.
(*************************************)
- Case "XAlt".
auto.
Qed.
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 20; int ans, a, m, n; long long ps0[N], ps1[N], arr[N], inf = 1e10 + 100; int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> arr[0]; arr[n] = inf; ps0[0] = 0; for (int i = 1; i < n; i++) { cin >> arr[i]; ps0[i] = ps0[i - 1] + arr[i] - arr[i - 1]; } ps1[n - 1] = 0; for (int i = n - 2; i >= 0; i--) { ps1[i] = arr[i + 1] - arr[i] + ps1[i + 1]; } cout << arr[1] - arr[0] << << ps1[0] << endl; for (int i = 1; i < n; i++) { cout << min(arr[i] - arr[i - 1], arr[i + 1] - arr[i]) << << max(ps0[i], ps1[i]) << endl; } }
|
// timer D
//----------------------------------------------------------------------------------
//----------------------------------------------------------------------------------
module cia_timerd
(
input clk, // clock
input clk7_en,
input wr, // write enable
input reset, // reset
input tlo, // timer low byte select
input tme, // timer mid byte select
input thi, // timer high byte select
input tcr, // timer control register
input [7:0] data_in, // bus data in
output reg [7:0] data_out, // bus data out
input count, // count enable
output irq // intterupt out
);
reg latch_ena; // timer d output latch enable
reg count_ena; // timer d count enable
reg crb7; // bit 7 of control register B
reg [23:0] tod; // timer d
reg [23:0] alarm; // alarm
reg [23:0] tod_latch; // timer d latch
reg count_del; // delayed count signal for interrupt requesting
// timer D output latch control
always @(posedge clk)
if (clk7_en) begin
if (reset)
latch_ena <= 1'd1;
else if (!wr)
begin
if (thi && !crb7) // if MSB read and ALARM is not selected, hold data for subsequent reads
latch_ena <= 1'd0;
else if (tlo) // if LSB read, update data every clock
latch_ena <= 1'd1;
end
end
always @(posedge clk)
if (clk7_en) begin
if (latch_ena)
tod_latch[23:0] <= tod[23:0];
end
// timer D and crb7 read
always @(*)
if (!wr)
begin
if (thi) // high byte of timer D
data_out[7:0] = tod_latch[23:16];
else if (tme) // medium byte of timer D (latched)
data_out[7:0] = tod_latch[15:8];
else if (tlo) // low byte of timer D (latched)
data_out[7:0] = tod_latch[7:0];
else if (tcr) // bit 7 of crb
data_out[7:0] = {crb7,7'b000_0000};
else
data_out[7:0] = 8'd0;
end
else
data_out[7:0] = 8'd0;
// timer D count enable control
always @(posedge clk)
if (clk7_en) begin
if (reset)
count_ena <= 1'd1;
else if (wr && !crb7) // crb7==0 enables writing to TOD counter
begin
if (thi/* || tme*/) // stop counting
count_ena <= 1'd0;
else if (tlo) // write to LSB starts counting again
count_ena <= 1'd1;
end
end
// timer D counter
always @(posedge clk)
if (clk7_en) begin
if (reset) // synchronous reset
begin
tod[23:0] <= 24'd0;
end
else if (wr && !crb7) // crb7==0 enables writing to TOD counter
begin
if (tlo)
tod[7:0] <= data_in[7:0];
if (tme)
tod[15:8] <= data_in[7:0];
if (thi)
tod[23:16] <= data_in[7:0];
end
else if (count_ena && count)
tod[23:0] <= tod[23:0] + 24'd1;
end
// alarm write
always @(posedge clk)
if (clk7_en) begin
if (reset) // synchronous reset
begin
alarm[7:0] <= 8'b1111_1111;
alarm[15:8] <= 8'b1111_1111;
alarm[23:16] <= 8'b1111_1111;
end
else if (wr && crb7) // crb7==1 enables writing to ALARM
begin
if (tlo)
alarm[7:0] <= data_in[7:0];
if (tme)
alarm[15:8] <= data_in[7:0];
if (thi)
alarm[23:16] <= data_in[7:0];
end
end
// crb7 write
always @(posedge clk)
if (clk7_en) begin
if (reset)
crb7 <= 1'd0;
else if (wr && tcr)
crb7 <= data_in[7];
end
// delayed count enable signal
always @(posedge clk)
if (clk7_en) begin
count_del <= count & count_ena;
end
// alarm interrupt request
assign irq = (tod[23:0]==alarm[23:0] && count_del) ? 1'b1 : 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_SYMBOL_V
`define SKY130_FD_SC_HD__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_SYMBOL_V
|
module top (
input CLK,
input BTN_N, BTN1, BTN2, BTN3,
output LED1, LED2, LED3, LED4, LED5,
output P1A1, P1A2, P1A3, P1A4, P1A7, P1A8, P1A9, P1A10,
output P1B1, P1B2, P1B3, P1B4, P1B7, P1B8, P1B9, P1B10
);
wire [7:0] ss_top, ss_bot;
reg [7:0] disp_top = 0, disp_bot = 0;
reg [7:0] lap_top = 0, lap_bot = 0;
reg [7:0] lap_timeout = 0;
wire [7:0] disp_top_inc, disp_bot_inc;
assign { P1A10, P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1 } = ss_top;
assign { P1B10, P1B9, P1B8, P1B7, P1B4, P1B3, P1B2, P1B1 } = ss_bot;
reg [20:0] clkdiv = 0;
reg clkdiv_pulse = 0;
reg running = 0;
always @(posedge CLK) begin
if (clkdiv == 120000) begin
clkdiv <= 0;
clkdiv_pulse <= 1;
end else begin
clkdiv <= clkdiv + 1;
clkdiv_pulse <= 0;
end
if (clkdiv_pulse && running) begin
{disp_top, disp_bot} <= {disp_top_inc, disp_bot_inc};
end
if (clkdiv_pulse && lap_timeout) begin
lap_timeout <= lap_timeout - 1;
end
// left button: start
if (BTN3) begin
running <= 1;
end
// center button: lap
if (BTN2) begin
lap_top <= disp_top;
lap_bot <= disp_bot;
lap_timeout <= 200;
end
// right button: stop
if (BTN1) begin
running <= 0;
end
// reset
if (!BTN_N) begin
{disp_top, disp_bot} <= 0;
running <= 0;
end
end
seven_seg_ctrl ss_ctrl_top (
.CLK(CLK),
.din(lap_timeout ? lap_top : disp_top),
.dout(ss_top)
);
seven_seg_ctrl ss_ctrl_bot (
.CLK(CLK),
.din(lap_timeout ? lap_bot : disp_bot),
.dout(ss_bot)
);
bcd16_increment bot_inc (
.din({disp_top, disp_bot}),
.dout({disp_top_inc, disp_bot_inc})
);
endmodule
module bcd16_increment (
input [15:0] din,
output reg [15:0] dout
);
always @* begin
case (1'b1)
din[15:0] == 16'h 9999:
dout = 0;
din[11:0] == 12'h 999:
dout = {din[15:12] + 4'd 1, 12'h 000};
din[7:0] == 8'h 99:
dout = {din[15:12], din[11:8] + 4'd 1, 8'h 00};
din[3:0] == 4'h 9:
dout = {din[15:8], din[7:4] + 4'd 1, 4'h 0};
default:
dout = {din[15:4], din[3:0] + 4'd 1};
endcase
end
endmodule
module seven_seg_ctrl (
input CLK,
input [7:0] din,
output reg [7:0] dout
);
wire [6:0] lsb_digit;
wire [6:0] msb_digit;
seven_seg_hex msb_nibble (
.din(din[7:4]),
.dout(msb_digit)
);
seven_seg_hex lsb_nibble (
.din(din[3:0]),
.dout(lsb_digit)
);
reg [9:0] clkdiv = 0;
reg clkdiv_pulse = 0;
reg msb_not_lsb = 0;
always @(posedge CLK) begin
clkdiv <= clkdiv + 1;
clkdiv_pulse <= &clkdiv;
msb_not_lsb <= msb_not_lsb ^ clkdiv_pulse;
if (clkdiv_pulse) begin
if (msb_not_lsb) begin
dout[6:0] <= ~msb_digit;
dout[7] <= 0;
end else begin
dout[6:0] <= ~lsb_digit;
dout[7] <= 1;
end
end
end
endmodule
module seven_seg_hex (
input [3:0] din,
output reg [6:0] dout
);
always @*
case (din)
4'h0: dout = 7'b ;
4'h1: dout = 7'b ;
4'h2: dout = 7'b ;
4'h3: dout = 7'b ;
4'h4: dout = 7'b ;
4'h5: dout = 7'b ;
4'h6: dout = 7'b ;
4'h7: dout = 7'b ;
4'h8: dout = 7'b ;
4'h9: dout = 7'b ;
4'hA: dout = 7'b ;
4'hB: dout = 7'b ;
4'hC: dout = 7'b ;
4'hD: dout = 7'b ;
4'hE: dout = 7'b ;
4'hF: dout = 7'b ;
endcase
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ulight_fifo_data_read_en_rx (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:07:08 03/14/2015
// Design Name:
// Module Name: deserializer_gen_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module deserializer_gen_test(
output rxd,
output clk
);
reg rxd_buf;
reg clk_buf;
reg [7:0] data_buf;
assign clk = clk_buf;
assign rxd = rxd_buf;
integer data_src;
integer i;
integer j;
initial
begin
rxd_buf = 0;
clk_buf = 1;
data_src = $fopen("test_serializer/data/serial_vector.txt", "rb");
#100;
for(i = 0; i < 16*(8+4); i = i + 1)
begin
#1;
data_buf = $fgetc(data_src);
if(data_buf == "1") rxd_buf = 1;
if(data_buf == "0") rxd_buf = 0;
#1;
clk_buf = 0;
#2;
clk_buf = 1;
end
#2;
clk_buf = 0;
#2;
clk_buf = 1;
#2;
clk_buf = 0;
#2;
clk_buf = 1;
#2;
clk_buf = 0;
#2;
clk_buf = 1;
$fclose(data_src);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> const double eps = 1e-8; const int oo = 0x3f3f3f3f; using namespace std; long long a, b, c, d; bool read() { if (!(cin >> a >> b >> c >> d)) return false; return true; } void process() { cout << b << << c << << c << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = -1; cin >> t; while (t-- && read()) { process(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DECAP_PP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__decap (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long int binary_exp(long long int a, long long int n) { long long int i = 1; while (n > 0) { if (n % 2 == 1) i = (i * a) % 1000000007; a = (a * a) % 1000000007; n /= 2; } return i; } long long int IsPrime(long long int n) { if (n == 0 || n == 1) return n; if (n % 2 == 0) return (long long int)2; if (n % 3 == 0) return (long long int)3; else { for (long long int i = 5; i * i <= n; i += 6) { if (n % i == 0) return i; if (n % (i + 2) == 0) return (i + 2); } return n; } } void solve() { int n, i, j, k, a, b, mex = 1, ans = 0; cin >> n; int ind[n + 1]; bool vis[n + 1]; memset(vis, false, sizeof(vis)); for (i = 1; i <= n; i++) { cin >> k; ind[k] = i; } for (i = 1; i <= n; i++) { cin >> k; vis[ind[k]] = true; while (mex <= n && vis[mex]) mex++; if (ind[k] > mex) ans++; } cout << ans; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); srand(time(NULL)); ; int t = 1; while (t--) solve(); }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 4'h0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 26,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 9
) (
input sys_clk,
input sys_clk_n,
/*
* Clock used to generate DQS.
* Typically sys_clk phased out by 90 degrees,
* as data is sent synchronously to sys_clk.
*/
input dqs_clk,
input dqs_clk_n,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Simple FML 4x64 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
output [3:0] sdram_dqm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
/* Interface to the DCM generating DQS */
output dqs_psen,
output dqs_psincdec,
input dqs_psdone,
input [1:0] pll_stat
);
/* Register all control signals, leaving the possibility to use IOB registers */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [12:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
sdram_cke <= sdram_cke_r;
sdram_cs_n <= sdram_cs_n_r;
sdram_we_n <= sdram_we_n_r;
sdram_cas_n <= sdram_cas_n_r;
sdram_ras_n <= sdram_ras_n_r;
sdram_ba <= sdram_ba_r;
sdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [12:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [12:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
wire idelay_rst;
wire idelay_ce;
wire idelay_inc;
hpdmc_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.dqs_psen(dqs_psen),
.dqs_psincdec(dqs_psincdec),
.dqs_psdone(dqs_psdone),
.pll_stat(pll_stat)
);
/* SDRAM management unit */
wire mgmt_stb;
wire mgmt_we;
wire [sdram_depth-3-1:0] mgmt_address;
wire mgmt_ack;
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(mgmt_stb),
.we(mgmt_we),
.address(mgmt_address),
.ack(mgmt_ack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Bus interface */
wire data_ack;
hpdmc_busif #(
.sdram_depth(sdram_depth)
) busif (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.mgmt_stb(mgmt_stb),
.mgmt_we(mgmt_we),
.mgmt_address(mgmt_address),
.mgmt_ack(mgmt_ack),
.data_ack(data_ack)
);
/* Data path controller */
wire direction;
wire direction_r;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.ack(data_ack),
.direction(direction),
.direction_r(direction_r),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_ddrio ddrio(
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.dqs_clk(dqs_clk),
.dqs_clk_n(dqs_clk_n),
.direction(direction),
.direction_r(direction_r),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DQM pins.
*/
.mo(~fml_sel),
.do(fml_di),
.di(fml_do),
.sdram_dqm(sdram_dqm),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:26 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.v
// Design : ip_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> int main() { long long int a, b, c, d, x; int t; scanf( %d , &t); while (t--) { scanf( %lld%lld%lld%lld , &a, &b, &c, &d); x = a / d + (((a / d) / b) * c); printf( %lld n , x); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> even_bag, odd_bag; int n, all, x; cin >> n; for (int i = 0; i < n; i++) { cin >> x; all += x; if (x & 1) odd_bag.push_back(x); else even_bag.push_back(x); } cout << ((all & 1) ? odd_bag.size() : even_bag.size()) << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/13/2016 08:15:39 PM
// Design Name:
// Module Name: CLA_Adder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CLA_Adder (
input [3:0] A,
input [3:0] B,
input Operation,
output [3:0] Sum,
output Error
);
wire [2:0] G;
wire [2:0] P;
wire [3:0] Cin;
assign G[0] = A[0] & (B[0] ^ Operation);
assign P[0] = A[0] ^ (B[0] ^ Operation);
assign G[1] = A[1] & B[1] ^ Operation;
assign P[1] = A[1] ^ (B[1] ^ Operation);
assign G[2] = A[2] & (B[2] ^ Operation);
assign P[2] = A[2] ^ (B[2] ^ Operation);
assign Cin[0] = Operation;
assign Cin[1] = G[0] | P[0] & Operation;
assign Cin[2] = G[1] | P[1] & (G[0] | P[0] & Operation);
assign Cin[3] = G[2] | P[2] & (G[1] | P[1] & (G[0] | P[0] & Operation));
AdderSlice Part1 (
.A(A[0]),
.B(B[0] ^ Operation),
.Cin(Cin[0]),
.S(Sum[0])
);
AdderSlice Part2 (
.A(A[1]),
.B(B[1] ^ Operation),
.Cin(Cin[1]),
.S(Sum[1])
);
AdderSlice Part3 (
.A(A[2]),
.B(B[2] ^ Operation),
.Cin(Cin[2]),
.S(Sum[2])
);
AdderSlice Part4 (
.A(A[3]),
.B(B[3] ^ Operation),
.Cin(Cin[3]),
.S(Sum[3])
);
ErrorDetection Part (
.A_MSB(A[3]),
.B_MSB(B[3]),
.Operation(Operation),
.S_MSB(Sum[3]),
.Error(Error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 305; vector<pair<int, int> > e; vector<int> b; int a[MAXN]; bool mark[MAXN], x[MAXN][MAXN]; int n, k, m, cnt; void add(int u, int v) { if (x[u][v]) return; cnt++; e.push_back(pair<int, int>(u, v)); x[u][v] = x[v][u] = true; } void ghi() { for (int i = 0; i < m; i++) printf( %d %d n , e[i].first, e[i].second); } int main() { if (0) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); }; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= k; i++) scanf( %d , &a[i]), mark[a[i]] = true; int nn = n - k; if (k == n) { puts( -1 ); return 0; } for (int i = 1; i <= n; i++) if (!mark[i]) b.push_back(i); add(a[1], b[0]); if (cnt == m) { ghi(); return 0; } for (int i = 0; i < nn - 1; i++) { add(b[i], b[i + 1]); if (cnt == m) { ghi(); return 0; } } add(b[nn - 1], a[2]); for (int i = 2; i < k; i++) { add(a[i], a[i + 1]); if (cnt == m) { ghi(); return 0; } } for (int i = 0; i < nn - 1; i++) for (int j = i + 1; j < nn; j++) { add(b[i], b[j]); if (cnt == m) { ghi(); return 0; } } for (int i = 2; i < k; i++) for (int j = i + 1; j <= k; j++) { add(a[i], a[j]); if (cnt == m) { ghi(); return 0; } } for (int i = 0; i < nn; i++) for (int j = 2; j <= k; j++) { add(b[i], a[j]); if (cnt == m) { ghi(); return 0; } } for (int i = 1; i < nn; i++) { add(a[1], b[i]); if (cnt == m) { ghi(); return 0; } } puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[6]; for (int i = 0; i < 6; i++) cin >> a[i]; a[5]++; int mn = 100000; for (int i = 0; i < 6; i++) { if (i == 4) continue; if (mn > a[i]) mn = a[i]; } cout << (mn > a[4] ? mn - a[4] : 0) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O221A_PP_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; reverse(b.begin(), b.end()); cout << atoi(a.c_str()) + atoi(b.c_str()) << endl; }
|
module jtflipfloptb;
wire q, qbar;
reg clk,rst;
reg t;
jtflipflop jtff(q,qbar,clk,rst,t);
always #5 clk = ~clk;
initial
begin
clk = 1'b0;
rst = 1; # 10; rst = 0; #10;
$display("RSLT\tt\tq\tqbar");
t = 0; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",t,q,qbar);
else
$display ("FAIL\t%d\t%d\t%d",t,q,qbar);
# 10; // JUST delay
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",t,q,qbar);
else
$display ("FAIL\t%d\t%d\t%d",t,q,qbar);
# 10; // JUST delay
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",t,q,qbar);
else
$display ("FAIL\t%d\t%d\t%d",t,q,qbar);
t = 1; # 10; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",t,q,qbar);
else
$display ("FAIL\t%d\t%d\t%d",t,q,qbar);
# 10; // JUST delay
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",t,q,qbar);
else
$display ("FAIL\t%d\t%d\t%d",t,q,qbar);
# 10; // JUST delay
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d",t,q,qbar);
else
$display ("FAIL\t%d\t%d\t%d",t,q,qbar);
$finish;
end
endmodule
|
module top (
input wire clk,
input wire sw,
output wire led
);
wire O_LOCKED;
wire RST;
wire clk0;
wire clk1;
wire clk_out;
wire clk_fb_i;
wire clk_fb_o;
reg [25:0] cnt;
assign RST = 1'b0;
BUFG bufg0 (
.I(clk_fb_i),
.O(clk_fb_o)
);
wire clk_ibuf;
IBUF ibuf0 (
.I(clk),
.O(clk_ibuf)
);
wire clk_bufg;
BUFG bufg1 (
.I(clk_ibuf),
.O(clk_bufg)
);
PLLE2_ADV #(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (16),
.CLKOUT0_DIVIDE (8),
.CLKOUT1_DIVIDE (32),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1)
)
pll (
.CLKIN1 (clk_bufg),
.CLKINSEL (1),
.RST (RST),
.PWRDWN (0),
.LOCKED (O_LOCKED),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (clk0),
.CLKOUT1 (clk1)
);
BUFGMUX bufgmux (
.I0(clk0),
.I1(clk1),
.S(sw[0]),
.O(clk_out)
);
always @(posedge clk_out) begin
cnt <= cnt + 1'b1;
end
assign led[0] = cnt[25];
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1000002]; int o = 0, len; int main() { cin >> s; if ((s[0] == 1 ) && (strlen(s) == 1)) { cout << 0; return 0; } for (int i = strlen(s); i >= 0; i--) { s[i + 1] = s[i]; } s[0] = 0 ; int i = strlen(s) - 1; while (i > 0) { if (s[i] == 0 ) { o += 1; i--; } else { if (i == 1) break; o++; while (s[i] == 1 ) { o++; i--; } s[i] = 1 ; } } cout << o; }
|
#include <bits/stdc++.h> using namespace std; list<int> adjList[200002]; int depth[200002]; int sz[200002]; class LCA_binary { int logn, timer; vector<int> tin, tout; vector<vector<int>> up; public: void innerdfs(int v, int p) { tin[v] = ++timer; up[v][0] = p; for (int i = 1; i <= logn; ++i) up[v][i] = up[up[v][i - 1]][i - 1]; for (int u : adjList[v]) { if (u != p) innerdfs(u, v); } tout[v] = ++timer; } bool is_ancestor(int u, int v) { return tin[u] <= tin[v] && tout[u] >= tout[v]; } int lca(int u, int v) { if (is_ancestor(u, v)) return u; if (is_ancestor(v, u)) return v; for (int i = logn; i >= 0; --i) { if (!is_ancestor(up[u][i], v)) u = up[u][i]; } return up[u][0]; } void preprocess(int n, int root) { tin.resize(n + 3); tout.resize(n + 3); timer = 0; logn = ceil(log2(n)); up.assign(n + 3, vector<int>(logn + 1)); innerdfs(root, root); } }; set<int> s; vector<int> univ; int deep(int i, int p, int d) { depth[i] = d++; if (s.count(i)) univ.push_back(i); sz[i] = 1; for (int v : adjList[i]) if (v != p) sz[i] += deep(v, i, d); return sz[i]; } int main() { int n, k; cin >> n >> k; for (int i = 0; i < (k << 1); i++) { int t; cin >> t; s.insert(t); } for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; adjList[a].push_back(b); adjList[b].push_back(a); } LCA_binary f; f.preprocess(n, 1); deep(1, 0, 0); long long ans = 0LL; for (int i = 0; i < k; i++) ans += (long long)(depth[univ[i]] + depth[univ[i + k]] - (depth[f.lca(univ[i], univ[i + k])] << 1)); cout << ans << n ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_32x24.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_32x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({8'h00, di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; int ans = 0; while (n % 3 == 0 || n % 6 == 0) { if (n % 6 == 0) { n /= 6; ans++; } else if (n % 3 == 0) { n /= 3; ans += 2; } } if (n != 1) { cout << -1 << endl; return; } cout << ans << endl; } int main() { int t = 1, i = 1; cin >> t; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_1_V
`define SKY130_FD_SC_LP__O211A_1_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_1_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_cmd.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
// User interface command port.
module ui_cmd #
(
parameter TCQ = 100,
parameter ADDR_WIDTH = 33,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter RANKS = 4,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
rd_accepted, wr_accepted, data_buf_addr,
// Inputs
rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
);
input rst;
input clk;
input accept_ns;
input rd_buf_full;
input wr_req_16;
wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
reg app_rdy_r = 1'b0;
always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
output wire app_rdy;
assign app_rdy = app_rdy_r;
input [ADDR_WIDTH-1:0] app_addr;
input [2:0] app_cmd;
input app_sz;
input app_hi_pri;
input app_en;
reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};
reg [2:0] app_cmd_r1;
reg [2:0] app_cmd_r2;
reg app_sz_r1;
reg app_sz_r2;
reg app_hi_pri_r1;
reg app_hi_pri_r2;
reg app_en_r1;
reg app_en_r2;
wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1;
wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;
wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;
wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;
wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;
wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;
wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;
wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;
wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);
wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);
always @(posedge clk) begin
app_addr_r1 <= #TCQ app_addr_ns1;
app_addr_r2 <= #TCQ app_addr_ns2;
app_cmd_r1 <= #TCQ app_cmd_ns1;
app_cmd_r2 <= #TCQ app_cmd_ns2;
app_sz_r1 <= #TCQ app_sz_ns1;
app_sz_r2 <= #TCQ app_sz_ns2;
app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
app_en_r1 <= #TCQ app_en_ns1;
app_en_r2 <= #TCQ app_en_ns2;
end // always @ (posedge clk)
wire use_addr_lcl = app_en_r2 && app_rdy_r;
output wire use_addr;
assign use_addr = use_addr_lcl;
output wire [RANK_WIDTH-1:0] rank;
output wire [BANK_WIDTH-1:0] bank;
output wire [ROW_WIDTH-1:0] row;
output wire [COL_WIDTH-1:0] col;
output wire size;
output wire [2:0] cmd;
output wire hi_priority;
assign col = app_rdy_r
? app_addr_r1[0+:COL_WIDTH]
: app_addr_r2[0+:COL_WIDTH];
generate
begin
if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
begin
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+:BANK_WIDTH];
end
else
begin
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];
end
end
endgenerate
assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign size = app_rdy_r
? app_sz_r1
: app_sz_r2;
assign cmd = app_rdy_r
? app_cmd_r1
: app_cmd_r2;
assign hi_priority = app_rdy_r
? app_hi_pri_r1
: app_hi_pri_r2;
wire request_accepted = use_addr_lcl && app_rdy_r;
wire rd = app_cmd_r2[1:0] == 2'b01;
wire wr = app_cmd_r2[1:0] == 2'b00;
wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
wire write = wr || wr_bytes;
output wire rd_accepted;
assign rd_accepted = request_accepted && rd;
output wire wr_accepted;
assign wr_accepted = request_accepted && write;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
endmodule // ui_cmd
// Local Variables:
// verilog-library-directories:(".")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_V
`define SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire u_vpwr_vgnd1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , u_vpwr_vgnd1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_V
|
#include <bits/stdc++.h> inline long long pow(long long a, long long b, long long mod) { long long ans = 1; a %= mod; for (; b; b >>= 1, a = a * a % mod) if (b & 1) ans = ans * a % mod; return ans; } struct Node { int L, R; mutable long long val; Node(int L, int R = -1, long long val = 0) : L(L), R(R), val(val) {} inline bool operator<(const Node& b) const { return L < b.L; } }; std::set<Node> Chtholly; inline std::set<Node>::iterator spilt(int pos) { std::set<Node>::iterator iter = Chtholly.lower_bound(Node(pos)); if (iter != Chtholly.end() && iter->L == pos) return iter; --iter; int L = iter->L, R = iter->R; long long V = iter->val; Chtholly.erase(iter); Chtholly.insert(Node(L, pos - 1, V)); return Chtholly.insert(Node(pos, R, V)).first; } inline void Add(int L, int R, long long val = 1) { std::set<Node>::iterator end = spilt(R + 1), iter = spilt(L); for (; iter != end; ++iter) iter->val += val; } inline void assign(int L, int R, long long val = 0) { std::set<Node>::iterator terR = spilt(R + 1), terL = spilt(L); Chtholly.erase(terL, terR); Chtholly.insert(Node(L, R, val)); } inline long long Rank(int L, int R, int k) { std::vector<std::pair<long long, int> > s; std::set<Node>::iterator end = spilt(R + 1), iter = spilt(L); for (; iter != end; ++iter) { s.push_back(std::pair<long long, int>(iter->val, iter->R - iter->L + 1)); } std::sort(s.begin(), s.end()); for (auto iter : s) { k -= iter.second; if (k <= 0) return iter.first; } return -1ll; } inline long long Sum(int L, int R, long long k, long long mod) { std::set<Node>::iterator end = spilt(R + 1), iter = spilt(L); long long ans = 0; for (; iter != end; ++iter) { ans = (ans + 1ll * (iter->R - iter->L + 1) * pow(iter->val, k, mod) % mod) % mod; } return ans; } long long n, m, seed, vmax; const int MOD = 1e9 + 7; inline long long rnd() { long long ret = seed; seed = (seed * 7 + 13) % MOD; return ret; } signed main() { int i; scanf( %lld%lld%lld%lld , &n, &m, &seed, &vmax); for (i = 1; i <= n; ++i) Chtholly.insert(Node(i, i, rnd() % vmax + 1)); Chtholly.insert(Node(n + 1, n + 1, 0)); for (i = 1; i <= m; ++i) { int op = rnd() % 4 + 1, L = rnd() % n + 1, R = rnd() % n + 1, x, y; if (L > R) L ^= R ^= L ^= R; x = rnd() % (op == 3 ? R - L + 1 : vmax) + 1; if (op == 4) y = rnd() % vmax + 1; if (op == 1) { Add(L, R, x); } if (op == 2) { assign(L, R, x); } if (op == 3) { printf( %lld n , Rank(L, R, x)); } if (op == 4) { printf( %lld n , Sum(L, R, x, y)); } } }
|
#include <bits/stdc++.h> using namespace std; bool comparator(string a, string b) { if (a.size() == b.size()) { return a > b; } return a.size() > b.size(); } int main() { int n, m; cin >> n >> m; string mat[n]; for (int i = 0; i < n; i++) { cin >> mat[i]; } vector<pair<int, int> > enemy; vector<int> adj[n * m]; int jugador; int end; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int pos = i * m + j; if (mat[i][j] == T ) continue; if (mat[i][j] == E ) { end = pos; } if (mat[i][j] - 0 >= 0 && mat[i][j] - 0 <= 9) { enemy.emplace_back(pair<int, int>(pos, mat[i][j] - 0 )); } if (mat[i][j] == S ) { jugador = pos; } if (i > 0 && mat[i - 1][j] != T ) { adj[pos].emplace_back(pos - m); adj[pos - m].emplace_back(pos); } if (i < n - 1 && mat[i + 1][j] != T ) { adj[pos].emplace_back(pos + m); adj[pos + m].emplace_back(pos); } if (j < m - 1 && mat[i][j + 1] != T ) { adj[pos].emplace_back(pos + 1); adj[pos + 1].emplace_back(pos); } if (j > 0 && mat[i][j - 1] != T ) { adj[pos].emplace_back(pos - 1); adj[pos - 1].emplace_back(pos); } } } queue<int> qu; int dist[n * m]; for (int i = 0; i < n * m; i++) { dist[i] = 1000000000; } dist[end] = 0; qu.push(end); while (!qu.empty()) { int u = qu.front(); qu.pop(); for (auto v : adj[u]) { if (dist[u] + 1 < dist[v]) { dist[v] = dist[u] + 1; qu.push(v); } } } long long ans = 0; for (auto ene : enemy) { if (dist[ene.first] <= dist[jugador]) { ans += ene.second; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; inline int Read() { int x(0); char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); return x; } const int maxn = 1e5 + 9, mod = 998244353, maxm = 409; int n, k, ans; int a[maxn], cnt[maxn], lst[maxn], fir[maxn], bl[maxm], br[maxm], col[maxn], v[maxn], lazy[maxm], f[maxn], sum[maxm][maxn]; inline int G(int x) { while (x > mod) x -= mod; return x; } inline void Fir() { int size(sqrt(n)), pieces(ceil(1.0 * n / size)); for (int i = 1; i < pieces; ++i) { bl[i] = (i - 1) * size + 1; br[i] = i * size; for (int j = bl[i]; j <= br[i]; ++j) col[j] = i; } bl[pieces] = (pieces - 1) * size + 1; br[pieces] = n; for (int j = bl[pieces]; j <= br[pieces]; ++j) col[j] = pieces; for (int i = 1; i <= n; ++i) { lst[i] = fir[a[i]]; fir[a[i]] = i; } } inline void Modify(int l, int r, int val) { int lt(col[l]), rt(col[r]); if (lt == rt) { for (int i = l; i <= r; ++i) { if (val == 1) { if (v[i] + lazy[lt] == k) ans = G(ans - f[i] + mod); } else { if (v[i] + lazy[lt] == k + 1) ans = G(ans + f[i]); } sum[lt][v[i]] = G(sum[lt][v[i]] - f[i] + mod), v[i] += val, sum[lt][v[i]] = G(sum[lt][v[i]] + f[i]); } } else { for (int i = l; i <= br[lt]; ++i) { if (val == 1) { if (v[i] + lazy[lt] == k) ans = G(ans - f[i] + mod); } else { if (v[i] + lazy[lt] == k + 1) ans = G(ans + f[i]); } sum[lt][v[i]] = G(sum[lt][v[i]] - f[i] + mod), v[i] += val, sum[lt][v[i]] = G(sum[lt][v[i]] + f[i]); } for (int i = bl[rt]; i <= r; ++i) { if (val == 1) { if (v[i] + lazy[rt] == k) ans = G(ans - f[i] + mod); } else { if (v[i] + lazy[rt] == k + 1) ans = G(ans + f[i]); } sum[rt][v[i]] = G(sum[rt][v[i]] - f[i] + mod), v[i] += val, sum[rt][v[i]] = G(sum[rt][v[i]] + f[i]); } for (int i = lt + 1; i <= rt - 1; ++i) { if (val == 1) ans = G(ans - sum[i][k - lazy[i]] + mod); else ans = G(ans + sum[i][k + 1 - lazy[i]]); lazy[i] += val; } } } inline void Solve() { ans = f[1] = sum[1][0] = 1; for (int i = 1; i <= n; ++i) { ++cnt[a[i]]; int p(lst[i]), q(lst[p]); if (cnt[a[i]] == 1) Modify(1, i, 1); else if (cnt[a[i]] == 2) { Modify(p + 1, i, 1); Modify(1, p, -1); } else { Modify(p + 1, i, 1); Modify(q + 1, p, -1); } f[i + 1] = ans; sum[col[i + 1]][v[i + 1]] = G(sum[col[i + 1]][v[i + 1]] + f[i + 1]); ans = G(ans + f[i + 1]); } printf( %d , f[n + 1]); } int main() { n = Read(); k = Read(); for (int i = 1; i <= n; ++i) a[i] = Read(); Fir(); Solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << (n - 1) * 2 + 1 << << 2 << endl; cout << 1 << << 2 << endl; }
|
`timescale 1ns / 1ps
//ALU para numeros de 32 bits con signo.
/*
* Números de 32 bits donde, si a es número, entonces:
* a[31] : signo de a.
* a[30:10] : parte entera de a.
* a[9:0] : parte decimal de a.
*/
module ALU(
input wire [31:0] a,
input wire [31:0] b,
input wire [3:0] s,
output reg [31:0] Z,
output reg le,
output reg eq,
output reg gt,
output reg ovf
);
//Operations
localparam SUMA = 4'd0;
localparam RESTA = 4'd1;
localparam MULT = 4'd2;
localparam DIV = 4'd3;
localparam LT = 4'd4;
localparam EQ = 4'd5;
localparam GT = 4'd6;
localparam AND = 4'd7;
localparam OR = 4'd8;
localparam NOT = 4'd9;
wire [31:0] rsuma;
wire ovfsuma;
wire [31:0] rresta;
wire ovfresta;
wire [31:0] rmult;
wire ovfmult;
wire [31:0] rdiv;
wire ovfdiv;
wire lesser;
wire greater;
wire equal;
//Modules
Comparador comp(
.a(a),
.b(b),
.lt(lesser),
.gt(greater),
.eq(equal)
);
Sumador suma(
.a(a),
.b(b),
.Z(rsuma),
.ovf(ovfsuma)
);
Sumador resta(
.a(a),
.b({~b[31],b[30:0]}),
.Z(rresta),
.ovf(ovfresta)
);
Multiplicador mult(
.a(a),
.b(b),
.Z(rmult),
.ovf(ovfmult)
);
Divisor divs(
.a(a),
.b(b),
.Z(rdiv),
.ovf(ovfdiv)
);
always @* begin
le = lesser;
gt = greater;
eq = equal;
case(s)
SUMA: begin
Z = rsuma;
ovf = ovfsuma;
end
RESTA: begin
Z = rresta;
ovf = ovfresta;
end
MULT: begin
Z = rmult;
ovf = ovfmult;
end
DIV: begin
Z = rdiv;
ovf = ovfdiv;
end
LT, EQ, GT: begin
Z = 32'b0;
ovf = 1'b0;
end
AND: begin
Z = a & b;
ovf = 1'b0;
end
OR: begin
Z = a | b;
ovf = 1'b0;
end
NOT: begin
Z = ~a;
ovf = 1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; long long ar[n]; for (int i = 0; i < n; i++) cin >> ar[i]; int maxi = -1000000001; long long sum = 0; for (int i = 0; i < n; i++) { if (ar[i] > maxi) maxi = ar[i]; sum += ar[i]; } float ans = (sum - maxi) / (float)(n - 1) + maxi; printf( %.9f , ans); cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::pair<T, U> operator+(const std::pair<T, U>& l, const std::pair<T, U>& r) { return {l.first + r.first, l.second + r.second}; } typedef void (*callback_function)(void); const long long ZERO = 0LL; const long long INF64 = 1e18; const long long INF32 = 1e9; const long long MOD = 1e9 + 7; const long double PI = acos(-1.0L); const long double EPS = static_cast<long double>(1e-9); inline long long Pow(long long a, long long k) { long long s = 1; for (; k; k >>= 1) { k& 1 ? s = 1LL * s * a % MOD : 0; a = 1LL * a * a % MOD; } return s; } const long long N = 1e6 + 7; void input() {} void output() {} void preprocess() {} void debug() { if (true) { } } void solve() { preprocess(); long long n; cin >> n; long long a[n]; for (long long i = (0); i < (n); i++) { cin >> a[i]; } long long L = 0, R = n - 1, res = 0; while (L < R) { while (L < R and a[L] < a[L + 1]) { L++; } while (L < R and a[R] < a[R - 1]) { R--; } if (L == R) { break; } if (a[L] < a[R]) { long long b = a[L] + 1; res += b - a[L + 1]; a[L + 1] = b; } else { long long b = a[R] + 1; res += b - a[R - 1]; a[R - 1] = b; } } cout << res << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(); { input(); solve(); output(); } return 0; }
|
// This part should pass OK
module t_lint_pragma_protected;
`pragma protect begin_protected
`pragma protect version=1
`pragma protect encrypt_agent="XXXXX"
`pragma protect encrypt_agent_info="YYYYY"
`pragma protect data_method="AES128-CBC"
`pragma protect key_keyowner="BIG3#1"
`pragma protect key_keyname="AAAAAA"
`pragma protect key_method="RSA"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg
KSAyMDA3IE==
`pragma protect key_keyowner="BIG3#2"
`pragma protect key_keyname="BBBBBB"
`pragma protect key_method="RSA"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv
cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs
bG93ZWQuCgoKICBUaGl=
`pragma protect key_keyowner="BIG3#3"
`pragma protect key_keyname="CCCCCCCC"
`pragma protect key_method="RSA"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g
MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg
YWRkaXRpb25hbCBwZXJ=
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295)
`pragma protect data_block
aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy
c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
ZCBXb3JrIGFzIG==
`pragma protect end_protected
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Thu Apr 14 23:40:55 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/FontROM_stub.v
// Design : FontROM
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0_9,Vivado 2015.4" *)
module FontROM(a, spo)
/* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[0:0]" */;
input [13:0]a;
output [0:0]spo;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:09:37 08/01/2014
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main( key_input, sysclk, speaker_out, led_out );
input [8:0] key_input;
input sysclk;
//output [7:0] seven_out;
output speaker_out;
output [4:0] led_out;
wire [4:0] key_code;
wire [12:0] slow_rate;
wire slowclk;
key_encoder encoder(
.key_input(key_input),
.key_code(key_code),
.clk(sysclk)
);
/*
keytofrequency ktof(
.key_code(key_code),
.clk(sysclk),
.slow_rate(slow_rate)
);
*/
bram_decoder ktof (
.addra(key_code),
.douta(slow_rate),
.clka(sysclk)
);
clk_divider clk_divider(
.sysclk(sysclk),
.slowclk(slowclk)
);
pwm_controller pwm_ctrl(
.clk(slowclk),
.slow_rate(slow_rate),
.speaker_out(speaker_out)
);
//seven_segment seven_seg(
//.key_input(key_input[2:0]),
//.a_to_g(seven_out)
//);
led_controller led_ctrl(
.key_input(key_input[8:7]),
.led_out(led_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N, Q, S[(int)1e5 + 5], i, L, R, p1, p2; long long Putere(long long p1, long long ex) { long long i, sol = 1; for (i = 0; (1 << i) <= ex; i++) { if (((1 << i) & ex) > 0) sol = (sol * p1) % 1000000007; p1 = (p1 * p1) % 1000000007; } return sol; } string str; int main() { cin >> N >> Q; cin >> str; for (i = 0; i < str.length(); i++) { if (str[i] == 1 ) S[i + 1] = S[i] + 1; else S[i + 1] = S[i]; } while (Q--) { cin >> L >> R; p1 = S[R] - S[L - 1]; p2 = R - L + 1 - p1; cout << ((Putere(2, p1) - 1 + (Putere(2, p1) - 1) * (Putere(2, p2) - 1))) % 1000000007 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[200005]; int n, k; int main() { scanf( %d%d , &n, &k); scanf( %s , s); if (n == 1) { if (k == 0) printf( %c n , s[0]); else printf( 0 n ); } else { if (k == 0) printf( %s n , s); else { if (s[0] != 1 ) k--; s[0] = 1 ; int t = 1; while (t < n && k) { if (s[t] != 0 ) { s[t] = 0 ; k--; } t++; } printf( %s , s); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; char s[N]; int main() { int T; scanf( %d , &T); while (T--) { int n, k; scanf( %d%d , &n, &k); scanf( %s , s); getchar(); vector<int> cnt(27, 0); for (int i = 0; i < n; ++i) ++cnt[s[i] - a ]; for (int len = n; len >= 1; --len) { vector<int> circ, c_cnt, used(len, 0); for (int i = 0; i < len; ++i) { if (used[i]) continue; used[i] = 1; int j = (i + k) % len; circ.push_back(1); while (!used[j]) { used[j] = 1; circ.back()++; j = (j + k) % len; } } c_cnt = cnt; sort(circ.begin(), circ.end()); sort(c_cnt.begin(), c_cnt.end()); int ok = 1; while (!circ.empty()) { if (circ.back() > c_cnt.back()) { ok = 0; break; } else { c_cnt.back() -= circ.back(); circ.pop_back(); sort(c_cnt.begin(), c_cnt.end()); } } if (ok) { printf( %d n , len); break; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; double t = 0; cin >> n; int i, a[n], b[n]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 0; i < n; i++) { b[i] = a[n - 1 - i]; } for (i = n - 1; i >= 0; i--) { if (i % 2 == 0) t += (b[i] * b[i]); else t -= (b[i] * b[i]); } t *= 3.141592653589793; printf( %.15f , t); return 0; }
|
module LCD_Driver(
input LCLK, //LCD CLK
input RST_n,
output reg HS,
output reg VS,
output DE,
output reg [9:0] Column,
output reg [9:0] Row,
output reg SPENA,
output reg SPDA_OUT,
input SPDA_IN,
output reg WrEn,
output reg SPCK,
input [7:0] Brightness,
input [7:0] Contrast
);
reg [9:0] Column_Counter;
reg [9:0] Row_Counter;
//Éú³ÉÁÐ
reg [9:0] Column_Reg;
always @(posedge LCLK) begin
if(VS & HS) begin
Column <= Column_Reg;
end
else begin
Column <= 10'd0;
end
end
always @(posedge LCLK) begin
if(Column_Counter <10'd1) begin
Column_Counter <= Column_Counter + 1'b1;
Column_Reg <= 10'd0;
HS <= 1'b0;
end
else if(Column_Counter <=10'd56) begin
Column_Counter <= Column_Counter + 1'b1;
Column_Reg <= 10'd0;
HS <= 1'b1;
end
else if(Column_Counter <=10'd70) begin
Column_Counter <= Column_Counter + 1'b1;
Column_Reg <= Column_Reg + 1'b1;
HS <= 1'b1;
end
else if(Column_Counter <10'd390) begin
Column_Counter <= Column_Counter + 1'b1;
Column_Reg <= Column_Reg + 1'b1;
HS <= 1'b1;
end
else if(Column_Counter <10'd408) begin
Column_Counter <= Column_Counter + 1'b1;
Column_Reg <= 10'd334;
HS <= 1'b1;
end
/*
else if(Column_Counter <10'd800) begin
Column_Counter <= Column_Counter + 1'b1;
Column_Reg <= 10'd334;
HS <= 1'b1;
end
*/
else begin
Column_Counter <= 10'd0;
end
end
//Éú³ÉÐÐ
always @(posedge HS) begin
if( Row_Counter < 10'd1) begin
Row_Counter <= Row_Counter + 1'b1;
Row <= 10'd0;
VS <= 1'b0;
end
else if( Row_Counter <= 10'd13) begin
Row_Counter <= Row_Counter + 1'b1;
Row <= 10'd0;
VS <= 1'b1;
end
else if( Row_Counter < 10'd253) begin
Row_Counter <= Row_Counter + 1'b1;
Row <= Row + 1'b1;
VS <= 1'b1;
end
else if( Row_Counter < 10'd263) begin
Row_Counter <= Row_Counter + 1'b1;
Row <= 10'd239;
VS <= 1'b1;
end
else begin
Row_Counter <=10'D0;
VS <= 1'b0;
end
end
//parameter setting
// no use
reg [7:0] SPCK_Counter;
wire SPCK_tmp;
always @(posedge LCLK) begin
SPCK_Counter <= SPCK_Counter + 1'b1;
end
assign SPCK_tmp = SPCK_Counter[4]; //1.5MHz
reg [7:0] SP_Counter;
parameter
WAKEUP = 16'b00000010_00000011;
wire [15:0] Snd_Data1;
wire [15:0] Snd_Data2;
assign Snd_Data1 ={8'h26,{1'b0,Brightness[7:1]}};
assign Snd_Data2 = {8'h22,{3'b0,Contrast[7:3]}};
reg [16:0] SP_DATA;
reg [15:0] Snd_Old1;
reg [15:0] Snd_Old2;
always @(posedge LCLK) begin
SPCK <= (~SPCK_tmp) | SPENA;
end
always @ (posedge SPCK_tmp or negedge RST_n) begin
if(~RST_n) begin
SP_Counter <= 8'd0;
SP_DATA <= WAKEUP;
SPENA <= 1'b1;
Snd_Old1 <= {8'h26,8'd0};
Snd_Old2 <= {8'h22,8'd0};
WrEn <= 1'b1;
end
else begin
if(SP_Counter < 8'd6) begin
SP_Counter <= SP_Counter + 1'b1;
SPDA_OUT <= SP_DATA[15];
SP_DATA <={SP_DATA[14:0],1'b0};
SPENA <= 1'b0;
WrEn <= 1'b1;
end
else if(SP_Counter == 8'd6) begin
SP_Counter <= SP_Counter + 1'b1;
SPENA <= 1'b0;
SPDA_OUT <= SP_DATA[15];
SP_DATA <={SP_DATA[14:0],1'b0};
if(SP_DATA[15] == 1'b1) begin //wr mode
WrEn <= 1'b1;
end
else begin
WrEn <= 1'b0;
end
end
else if(SP_Counter < 8'd16) begin
SP_Counter <= SP_Counter + 1'b1;
SPDA_OUT <= SP_DATA[15];
SP_DATA <={SP_DATA[14:0],1'b0};
SPENA <= 1'b0;
end
else if(SP_Counter < 8'd32)begin
SPENA <= 1'b1;
SP_Counter <= SP_Counter + 1'b1;
end
else begin
if(Snd_Data1 != Snd_Old1) begin
Snd_Old1 <= Snd_Data1;
SP_DATA <= Snd_Data1;
SP_Counter <= 8'd0;
WrEn <= 1'b1;
end
else if(Snd_Data2 != Snd_Old2) begin
Snd_Old2 <= Snd_Data2;
SP_DATA <= Snd_Data2;
SP_Counter <= 8'd0;
WrEn <= 1'b1;
end
else begin
WrEn <= 1'b0;
end
end
end
end
/*
//parameter setting
// no use
reg [7:0] SPCK_Counter;
wire SPCK_tmp;
always @(posedge LCLK) begin
SPCK_Counter <= SPCK_Counter + 1'b1;
end
assign SPCK_tmp = SPCK_Counter[4]; //1.5MHz
reg [7:0] SP_Counter;
parameter
WAKEUP = 16'b00000010_00000011;
wire [15:0] Snd_Data1;
wire [15:0] Snd_Data2;
wire [15:0] Snd_Data3;
wire UD; //0: down to up, 1 :up to down ,default :1;
wire LR; //0: right to left,1:left to right , default :1;
assign UD = 1'b0;
assign LR = 1'b0;
assign Snd_Data1 ={8'h26,{1'b0,Brightness[7:1]}};
assign Snd_Data2 = {8'h22,{3'b0,Contrast[7:3]}};
assign Snd_Data3 = {8'h0A,{6'b0,UD,LR}};
reg [16:0] SP_DATA;
reg [15:0] Snd_Old1;
reg [15:0] Snd_Old2;
reg [15:0] Snd_Old3;
always @(posedge LCLK) begin
SPCK <= (~SPCK_tmp) | SPENA;
end
always @ (posedge SPCK_tmp or negedge RST_n) begin
if(~RST_n) begin
SP_Counter <= 8'd0;
SP_DATA <= WAKEUP;
SPENA <= 1'b1;
Snd_Old1 <= {8'h26,8'd0};
Snd_Old2 <= {8'h22,8'd0};
Snd_Old3 <= {8'h0A,8'd03};
WrEn <= 1'b1;
end
else begin
if(SP_Counter < 8'd6) begin
SP_Counter <= SP_Counter + 1'b1;
SPDA_OUT <= SP_DATA[15];
SP_DATA <={SP_DATA[14:0],1'b0};
SPENA <= 1'b0;
WrEn <= 1'b1;
end
else if(SP_Counter == 8'd6) begin
SP_Counter <= SP_Counter + 1'b1;
SPENA <= 1'b0;
SPDA_OUT <= SP_DATA[15];
SP_DATA <={SP_DATA[14:0],1'b0};
if(SP_DATA[15] == 1'b1) begin //wr mode
WrEn <= 1'b1;
end
else begin
WrEn <= 1'b0;
end
end
else if(SP_Counter < 8'd16) begin
SP_Counter <= SP_Counter + 1'b1;
SPDA_OUT <= SP_DATA[15];
SP_DATA <={SP_DATA[14:0],1'b0};
SPENA <= 1'b0;
end
else if(SP_Counter < 8'd32)begin
SPENA <= 1'b1;
SP_Counter <= SP_Counter + 1'b1;
end
else begin
if(Snd_Data1 != Snd_Old1) begin
Snd_Old1 <= Snd_Data1;
SP_DATA <= Snd_Data1;
SP_Counter <= 8'd0;
WrEn <= 1'b1;
end
else if(Snd_Data2 != Snd_Old2) begin
Snd_Old2 <= Snd_Data2;
SP_DATA <= Snd_Data2;
SP_Counter <= 8'd0;
WrEn <= 1'b1;
end
else if(Snd_Data3 != Snd_Old3) begin
Snd_Old3 <= Snd_Data3;
SP_DATA <= Snd_Data3;
SP_Counter <= 8'd0;
WrEn <= 1'b1;
end
else begin
WrEn <= 1'b0;
end
end
end
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFRBP_PP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, i, j, k, sum = 0; scanf( %d%d%d , &n, &a, &b); int arr[n]; for (i = 0; i < n; i++) scanf( %d , &arr[i]); for (i = 0, j = n - 1; i <= j; i++, j--) { if (i != j && arr[i] != arr[j] && arr[i] != 2 && arr[j] != 2) { printf( -1 n ); return 0; } else if (arr[i] == 2 && arr[j] == 2) { if (i != j) sum += (2 * min(a, b)); else sum += min(a, b); } else if (arr[i] == 2 || arr[j] == 2) { if (arr[i] == 2 && arr[j] == 1) sum += b; else if (arr[i] == 2 && arr[j] == 0) sum += a; else if (arr[j] == 2 && arr[i] == 1) sum += b; else if (arr[j] == 2 && arr[i] == 0) sum += a; } } printf( %d n , sum); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; double x, cx; cin >> n >> x; cx = x; double a[n + 1], b[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == 1) { cout << -1; return 0; } } for (int i = 1; i <= n; i++) { cin >> b[i]; if (b[i] == 1) { cout << -1; return 0; } } x = x + x / (b[1] - 1); for (int i = n; i > 1; i--) { x = x * a[i] / (a[i] - 1); x = x * b[i] / (b[i] - 1); } x = x + x / (a[1] - 1); cout << setprecision(8) << x - cx; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 300010; long long n, a[N], t; map<long long, bool> vis; int solve() { scanf( %lld , &t); while (t--) { scanf( %lld , &n); vis.clear(); bool imp = 0; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); long long nw = (i + a[i]) % n; if (nw < 0) nw += n; if (vis[nw]) { imp = 1; } vis[nw] = 1; } if (imp) printf( NO n ); else printf( YES n ); } return 0; } int main() { return solve(); }
|
#include <bits/stdc++.h> using namespace std; template <class T> void miz(T &a, T b) { if (b < a) a = b; } template <class T> void maz(T &a, T b) { if (b > a) a = b; } template <class T> void clear(T &x) { T t; x.swap(t); } template <class T> T gcd(T a, T b) { while (b) { a %= b; swap(a, b); } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> T sqr(T x) { return x * x; } unsigned HASH(const char *p) { unsigned r = 0; while (*p) r = r * 257 + 1 + *p++; return r; } int ROUND(double x) { return x >= 0 ? x + 0.5 : x - 0.5; } int cnt[1000005]; int main() { int k, c, i, now = 0; long long ans = 0; scanf( %d , &k); cnt[0] = 1; for (i = 1; (c = getchar()) != n ; i++) { if (c == 1 ) now++; if (now >= k) ans += cnt[now - k]; cnt[now]++; } cout << ans << endl; return 0; }
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Robert Armstrong
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
module xadc_data_demux
(
input clk,
input reset,
input [15:0] xadc_data,
input xadc_data_ready,
input [4:0] channel,
output reg [15:0] xadc_vaux0_data,
output reg xadc_vaux0_ready,
output reg [15:0] xadc_vaux8_data,
output reg xadc_vaux8_ready
);
// Assignments for the XADC 0 data
always @(posedge clk) begin
if (reset) begin
xadc_vaux0_data <= 16'd0;
xadc_vaux0_ready <= 1'b0;
end
else
if (xadc_data_ready && (channel == 5'h10)) begin
xadc_vaux0_data <= xadc_data;
xadc_vaux0_ready <= 1'b1;
end
else
xadc_vaux0_ready <= 1'b0;
end
always @(posedge clk) begin
if (reset) begin
xadc_vaux8_data <= 16'd0;
xadc_vaux8_ready <= 1'b0;
end
else
if (xadc_data_ready && (channel == 5'h18)) begin
xadc_vaux8_data <= xadc_data;
xadc_vaux8_ready <= 1'b1;
end
else
xadc_vaux8_ready <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; int flag = 0; vector<char> arr(26, . ); for (int i = 0; i < s.length(); i++) { int a = int(s[i]); int b = int(t[i]); if (arr[a - 97] == t[i] || arr[a - 97] == . ) { arr[a - 97] = t[i]; if (arr[b - 97] == s[i] || arr[b - 97] == . ) arr[b - 97] = char(a); else { cout << -1; flag = -1; break; } } else { cout << -1; flag = -1; break; } } if (flag != -1) { for (int i = 0; i < 26; i++) { if (arr[i] != . ) { int x = (int)arr[i]; if (arr[x - 97] == char(i + 97) || arr[x - 97] == . ) { arr[x - 97] = . ; continue; } else { cout << -1; flag = -1; break; } } } } if (flag != -1) { int sum = 0; for (int i = 0; i < 26; i++) { if (arr[i] != . ) sum++; } cout << sum << endl; if (sum != 0) { for (int i = 0; i < 26; i++) { if (arr[i] != . ) cout << arr[i] << << char(i + 97) << endl; } } } return 0; }
|
// File: FramerCtrl.v
// Generated by MyHDL 0.8dev
// Date: Fri Dec 21 15:02:39 2012
`timescale 1ns/10ps
module FramerCtrl (
SOF,
state,
syncFlag,
clk,
reset_n
);
// Framing control FSM.
//
// SOF -- start-of-frame output bit
// state -- FramerState output
// syncFlag -- sync pattern found indication input
// clk -- clock input
// reset_n -- active low reset
output SOF;
reg SOF;
output [2:0] state;
reg [2:0] state;
input syncFlag;
input clk;
input reset_n;
reg [7:0] index;
always @(posedge clk, negedge reset_n) begin: FRAMERCTRL_FSM
if ((reset_n == 0)) begin
SOF <= 0;
index <= 0;
state <= 3'b001;
end
else begin
index <= ((index + 1) % 8);
SOF <= 0;
casez (state)
3'b??1: begin
index <= 1;
if (syncFlag) begin
state <= 3'b010;
end
end
3'b?1?: begin
if ((index == 0)) begin
if (syncFlag) begin
state <= 3'b100;
end
else begin
state <= 3'b001;
end
end
end
3'b1??: begin
if ((index == 0)) begin
if ((!syncFlag)) begin
state <= 3'b001;
end
end
SOF <= (index == (8 - 1));
end
default: begin
$finish;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const int N = 300010; int n, m, ans, ansx, ansy, s1, s2, max1; struct aa { int x, y, w; } a[N], b[N << 1]; multiset<int> q1, q2; void Init(int &x) { char y; while ((y = getchar()) < 0 || y > 9 ) ; x = y - 0 ; while ((y = getchar()) >= 0 && y <= 9 ) x = (x << 3) + (x << 1) + y - 0 ; } bool cmp(aa x, aa y) { return x.x < y.x || x.x == y.x && x.y < y.y; } int main() { scanf( %d%d , &n, &m); memset(a, 0, sizeof(a)); for (int i = 1; i <= n; ++i) scanf( %d%d , &a[i].x, &a[i].y); for (int i = 1; i <= n; ++i) b[(i << 1) - 1].x = a[i].x, b[(i << 1) - 1].y = 0, b[i << 1].x = a[i].y, b[i << 1].y = 1, b[i << 1].w = i; n <<= 1; sort(b + 1, b + n + 1, cmp); ans = 0; ansx = 0; ansy = 0; s1 = 0; s2 = 0; q1.clear(); q2.clear(); for (int i = 1; i <= n; ++i) if (b[i].y) { if (s1 == m && b[i].x - max1 + 1 > ans) { ansx = max1; ansy = b[i].x; ans = ansy - ansx + 1; } if (a[b[i].w].x > max1) q2.erase(q2.find(a[b[i].w].x)), --s2; else { q1.erase(q1.find(a[b[i].w].x)); --s1; if (s2) q1.insert(max1 = *q2.begin()), q2.erase(q2.begin()), ++s1, --s2; else if (s1) max1 = *q1.rbegin(); } } else { if (s1 < m) q1.insert(b[i].x), ++s1, max1 = b[i].x; else q2.insert(b[i].x), ++s2; } printf( %d n , ans); bool flag = 0; if (ans == 0) { for (int i = 1; i < m; ++i) printf( %d , i); printf( %d n , m); return 0; } for (int i = 1; i <= n && m; ++i) if (a[i].x <= ansx && a[i].y >= ansy) { if (flag) putchar( ); else flag = 1; printf( %d , i); --m; } putchar( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int b[255]; int main() { string a; cin >> a; for (int i = 0; i < a.size(); i++) { b[a[i]]++; } int u = b[ a ] - 1 + b[ a ]; int u2 = a.size(); cout << min(u, u2); return 0; }
|
#include <algorithm> #include <cmath> #include <cstring> #include <iostream> #include <limits> #include <queue> #include <set> #include <sstream> #include <stack> #include <unordered_map> #include <utility> #include <vector> using namespace std; typedef long long ll; typedef vector<int> vi; typedef vector<int>::iterator vit; typedef vector<vector<int>> vii; #define REP(i, a, b) for (int i = a; i < b; i++) #define VECITR(itr, v) for (vit itr = v.begin(); itr != v.end(); itr++) #define PB push_back #define MP make_pair #define F first #define S second #define sq(a) ((a) * (a)) int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } string next_valid_bracket_sequence(const string &x) { string s = x; int n = s.size(); int d = 0; for (int i = n - 1; i >= 1; i--) { if (s[i] == ) ) d++; else { d--; if (d > 0) { s[i] = ) ; s = s.substr(0, i + 1); REP(j, 0, (n - i - d) / 2) { s += ( ; } REP(j, 0, (n - i + d - 2) / 2) { s += ) ; } if (s.size() < n) return s + ) ; return s; } } } return ; } ll modulo(ll x, ll m) { int r = x % m; return r < 0 ? r + m : r; } int dfs(vector<vector<bool>> &change, vector<string> &arr, int i, int j, int k) { return 0; } void run() { ll n; cin >> n; ll copy = n; while(n % 4 == 0 && n > 4) n /= 4; if (n == 2 || n == 4) { cout << YES n ; return; } n = copy; if (n % 2 == 0 && (n / 2) == sq(ll(sqrt(double(n / 2))))) { cout << YES n ; return; } if (n % 4 == 0 && (n / 4) == sq(ll(sqrt(double(n / 4))))) { cout << YES n ; return; } else cout << NO n ; } int main() { cin.tie(NULL); ios_base::sync_with_stdio(false); int t = 1; cin >> t; REP(i, 0, t) { run(); } }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void chkMax(T &x, T y) { if (y > x) x = y; } template <typename T> void chkMin(T &x, T y) { if (y < x) x = y; } template <typename T> void inline read(T &x) { int f = 1; x = 0; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s <= 9 && s >= 0 ) x = x * 10 + (s ^ 48), s = getchar(); x *= f; } const int N = 2005; int n, f[10][10][10][10][10], g[10][10][10][10][10]; int ans = 2e9; int main() { read(n); memset(f, 0x3f, sizeof f); f[1][0][0][0][0] = 0; for (int i = 1; i <= n; i++) { int x, y; read(x), read(y); memcpy(g, f, sizeof f); memset(f, 0x3f, sizeof f); for (int p = 1; p <= 9; p++) { for (int a = 0; a <= 9; a++) { for (int b = 0; b <= 9; b++) { for (int c = 0; c <= 9; c++) { for (int d = 0; d <= 9; d++) { if (a == 0) { chkMin(f[x][y][b][c][d], g[p][a][b][c][d] + abs(p - x)); } if (b == 0) { chkMin(f[x][a][y][c][d], g[p][a][b][c][d] + abs(p - x)); } if (c == 0) { chkMin(f[x][a][b][y][d], g[p][a][b][c][d] + abs(p - x)); } if (d == 0) { chkMin(f[x][a][b][c][y], g[p][a][b][c][d] + abs(p - x)); } } } } } } for (int a = 9; ~a; a--) { for (int b = 9; ~b; b--) { for (int c = 9; ~c; c--) { for (int d = 9; ~d; d--) { for (int p = 1; p <= 9; p++) { if (a) chkMin(f[a][0][b][c][d], f[p][a][b][c][d] + abs(p - a)); if (b) chkMin(f[b][a][0][c][d], f[p][a][b][c][d] + abs(p - b)); if (c) chkMin(f[c][a][b][0][d], f[p][a][b][c][d] + abs(p - c)); if (d) chkMin(f[d][a][b][c][0], f[p][a][b][c][d] + abs(p - d)); } } } } } } for (int i = 1; i <= 9; i++) chkMin(ans, f[i][0][0][0][0]); printf( %d n , ans + 2 * n); return 0; }
|
// Copyright (c) 2000 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
/*
* This module implements what essentially amounts to an array of DFF
* devices with output enable. This test checks the operation of the
* bufif0 and bufif1 devices.
*/
module grayGap (ad, clk, read, write);
output [31:0] ad;
input clk, read, write;
reg [15:0] regff;
bufif0 ad_drv [31:0] (ad, {16'b0, regff}, read);
always @(posedge clk)
if (write) regff = ad[15:0];
endmodule
module main;
wire [31:0] ad;
reg clk, read, write;
reg [31:0] ad_val;
reg ad_en;
bufif1 ad_drv[31:0] (ad, ad_val, ad_en);
grayGap test (ad, clk, read, write);
always #10 clk = ~clk;
initial begin
clk = 1;
read = 1;
write = 0;
$monitor($time, "ad=%b", ad);
// Set up to write a value into the grayGap register.
@(negedge clk)
ad_val = 32'haaaa_aaaa;
read = 1;
write = 1;
ad_en = 1;
// The posedge has passed, now set up to read that value
// out. Turn all the drivers off for a moment, to see that the
// line becomes tri-state...
@(negedge clk)
ad_en = 0;
write = 0;
// Now read the value.
#1 read = 0;
#1 $display("Wrote %h, got %h", ad_val, ad);
if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin
$display("FAILED -- ad is %b", ad);
$finish;
end
#2 read = 1;
$display("PASSED");
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int dot = -1; for (int i = 0; i < (int)(s).size(); ++i) { if (s[i] == . ) { dot = i; } } int deg = 0; if (dot == -1) { deg = (int)(s).size(); string t = 0. + s; s = t; } else { deg = dot; string t = 0. ; for (int i = 0; i < (int)(s).size(); ++i) { if (s[i] != . ) { t += s[i]; } } s = t; } int lst = (int)(s).size() - 1; while (s[lst] == 0 ) { --lst; } s = s.substr(0, lst + 1); if (s == 0. ) { cout << 0 n ; return 0; } int fst = 2; while (s[fst] == 0 ) { ++fst; } s = s.substr(fst); deg -= fst - 1; cout << s[0]; if ((int)(s).size() > 1) { cout << . ; for (int i = 1; i < (int)(s).size(); ++i) { cout << s[i]; } } if (deg) { cout << E << deg; } cout << n ; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= 1'b1;
else
TxCtrlEndFrm <= 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= 1'b1;
else
if(TxDoneIn)
CtrlMux <= 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= 1'b0;
else
TxUsedDataIn_q <= TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= ControlEnd;
TxCtrlStartFrm_q <= TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= DlyCrcCnt + 4'd1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= 6'h0;
else
if(ResetByteCnt)
ByteCnt <= 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= MuxedCtrlData[7:0];
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:51:58 06/19/2016
// Design Name:
// Module Name: BM_dut
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BM_dut( clk, reset,u0,u1,x0,x1
);
input [47:0] u0;
input [15:0] u1;
input clk,reset;
output reg signed [15:0] x0,x1;
//logarithmic values
wire signed [30:0]e;
//square-root values
wire signed [16:0] f;
//sin cos values
wire signed [15:0] g0;
wire signed [15:0] g1;
logarithmic l2( .u0(u0),.e(e));
sqrt s2( .e(e) , .f(f));
sincos c2(.u1(u1), .g0(g0),.g1(g1));
initial
begin
x0=0;
x1=0;
end
always@(posedge clk)
begin
if(reset==1)
begin
x0=0;
x1=0;
end
else
begin
x0=f*g0;
x1=f*g1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[9] = {1, 0, -1, 0, 1, 1, -1, -1}; int dy[9] = {0, 1, 0, -1, 1, -1, 1, -1}; struct edge { int st, ed; char col; edge() { this->st = 0; this->ed = 0; this->col = 0; } edge(int st, int ed, char col) { this->st = st; this->ed = ed; this->col = col; } }; long long n, m; long long a[2000001], b[2000001]; int main() { std::ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; for (int test_case = 0; test_case < t; ++test_case) { cin >> n >> m; string input; cin >> input; string s2 = ; for (int i = 0; i < n; ++i) { a[i] = 1000000000; } for (int i = 0; i < n; ++i) { if (a[i % m] == 1000000000) a[i % m] = (long long)input[i] - 0 ; s2 += input[i % m]; } bool flg = 0; if (s2 < input) flg = 1; if (flg) { int i; for (i = 0; i < n; ++i) { if (a[i] == 1000000000) break; } i--; while (a[i] == 9) { a[i] = 0; i--; } a[i]++; } cout << n << n ; for (int i = 0; i < n; ++i) { cout << a[i % m]; } cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1e9 + 7; const long long int MAXN = 100010; long long int par[MAXN], nxt[MAXN]; int find_root(int a) { if (par[a] == a) { return a; } int f = par[a]; par[a] = find_root(par[a]); nxt[a] = (nxt[a] + nxt[f]) % MOD; if (nxt[a] < 0) nxt[a] += MOD; return par[a]; } int main() { long long int n; cin >> n; for (int i = 1; i <= n; i++) { par[i] = i; } long long int answer = 0; for (int i = 1; i <= n; i++) { long long int k; cin >> k; for (int j = 0; j < k; j++) { long long int v, x; cin >> v >> x; long long int root = find_root(v); par[root] = i; answer = (answer + ((nxt[v] + x) % MOD)) % MOD; while (answer < 0) answer += MOD; if (x < 0) x += MOD; nxt[root] = ((nxt[v] + x) % MOD); if (nxt[root] < 0) { nxt[root] += MOD; } } } cout << answer % MOD << endl; }
|
#include <bits/stdc++.h> using namespace std; long long ans = 0; long long mod = 1e9 + 7; int cnt[100005], Tcnt[100005], arr[100005]; vector<int> pri; void era() { pri.push_back(2); for (int i = 3; i <= 100000; i += 2) { if (!arr[i]) for (long long j = (long long)i * i; j <= 100000; j += i) { arr[j] = 1; } } for (int i = 3; i <= 100000; i += 2) { if (arr[i] == 0) pri.push_back(i); } } int GGG(int p) { int ret = 0; for (int i = 0; i < pri.size(); i++) { if (pri[i] > p) break; int cnt = 0; while (p % pri[i] == 0) { p /= pri[i]; ++cnt; } if (cnt >= 2) return -1; if (cnt != 0) ret++; } return ret; } long long po(int k) { if (k == 0) return 1; if (k == 1) return 2; long long ret = po(k / 2); ret = ret * ret % mod; if (k & 1) ret = ret * 2 % mod; return ret; } int main() { era(); int n; scanf( %d , &n); for (int t, i = 1; i <= n; i++) { scanf( %d , &t); cnt[t]++; } for (int i = 2; i <= 100000; i++) { for (int j = i; j <= 100000; j += i) { Tcnt[i] += cnt[j]; } } ans += po(n) - 1; for (int i = 2; i <= 100000; i++) { if (Tcnt[i] == 0) continue; int Gcnt = GGG(i); if (Gcnt == -1) continue; if (Gcnt % 2 == 0) { ans += po(Tcnt[i]) - 1; ans %= mod; } else { ans -= po(Tcnt[i]) - 1; while (ans < 0) ans += mod; } } printf( %I64d , ans); }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_cpu_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
mi_nios_cpu_jtag_debug_module_tck the_mi_nios_cpu_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
mi_nios_cpu_jtag_debug_module_sysclk the_mi_nios_cpu_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic mi_nios_cpu_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam mi_nios_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// mi_nios_cpu_jtag_debug_module_phy.sld_instance_index = 0,
// mi_nios_cpu_jtag_debug_module_phy.sld_ir_width = 2,
// mi_nios_cpu_jtag_debug_module_phy.sld_mfg_id = 70,
// mi_nios_cpu_jtag_debug_module_phy.sld_sim_action = "",
// mi_nios_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0,
// mi_nios_cpu_jtag_debug_module_phy.sld_sim_total_length = 0,
// mi_nios_cpu_jtag_debug_module_phy.sld_type_id = 34,
// mi_nios_cpu_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e8; const int N = 300100; int n, m, ans, nans; string mat[N], ansmat[N], nmat[N]; void upd() { if (nans >= ans) return; ans = nans; for (int i = 0; i < n; ++i) ansmat[i] = nmat[i]; } int main() { cin.tie(NULL); ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < n; ++i) cin >> mat[i]; for (int i = 0; i < n; ++i) ansmat[i] = nmat[i] = mat[i]; vector<char> v = { A , C , G , T }; ans = INF; do { nans = 0; for (int j = 0; j < m; ++j) { int op1 = 0, op2 = 0; for (int i = 0; i < n; ++i) { op1 += v[2 * (j & 1) + (i & 1)] != mat[i][j]; op2 += v[2 * (j & 1) + !(i & 1)] != mat[i][j]; } nans += min(op1, op2); bool f = op1 > op2; for (int i = 0; i < n; ++i) nmat[i][j] = v[2 * (j & 1) + (f ^ (i & 1))]; } upd(); nans = 0; for (int i = 0; i < n; ++i) { int op1 = 0, op2 = 0; for (int j = 0; j < m; ++j) { op1 += v[2 * (i & 1) + (j & 1)] != mat[i][j]; op2 += v[2 * (i & 1) + !(j & 1)] != mat[i][j]; } nans += min(op1, op2); bool f = op1 > op2; for (int j = 0; j < m; ++j) nmat[i][j] = v[2 * (i & 1) + (f ^ (j & 1))]; } upd(); } while (next_permutation(v.begin(), v.end())); for (int i = 0; i < n; ++i) cout << ansmat[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[1000010]; int c[20]; int main() { int k; scanf( %d , &k); scanf( %s , s + 1); int n = strlen(s + 1); int sum = 0; int i; memset(c, 0, sizeof c); int ans = 0; for (i = 1; i <= n; i++) { c[s[i] - 0 ]++; sum += s[i] - 0 ; } sum = k - sum; for (i = 0; i <= 9; i++) while (sum > 0 && c[i]) { sum -= 9 - i; ans++; c[i]--; } printf( %d n , ans); return 0; }
|
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