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#include <bits/stdc++.h> using namespace std; long long n, a[100069], dv; int main() { long long i, j, z = 1; scanf( %lld%lld , &n, &dv); if (n > dv) { printf( 0 n ); return 0; } for (i = 1; i <= n; i++) { scanf( %lld , a + i); for (j = 1; j < i; j++) { z = z * abs(a[i] - a[j]) % dv; } } printf( %lld n , z); }
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#include <bits/stdc++.h> using namespace std; int main() { unsigned long long n; cin >> n; if (n % 2 == 0) { cout << n - (n / 2) << endl; } else { cout << - << (n + 1) / 2 << endl; } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_TB_V
`define SKY130_FD_SC_HS__DLXBN_TB_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxbn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hs__dlxbn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_TB_V
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#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 100; int n, k; char str[N]; bool f[N]; int main() { scanf( %s , str + 1), n = strlen(str + 1); while (1 << k < n) ++k; if (1 << k > n) --k; memset(f, 1, sizeof(f)); for (int i = 1; i <= n - (1 << k) + 1; ++i) { char ch = z ; for (int s = 0; s < 1 << k; ++s) if (f[s]) for (int t = 0; t < k; ++t) f[s | (1 << t)] = 1; for (int s = 0; s < 1 << k; ++s) if (f[s]) ch = min(str[i + s], ch); for (int s = 0; s < 1 << k; ++s) if (str[i + s] != ch) f[s] = 0; putchar(ch); } return 0; }
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#include <bits/stdc++.h> int main() { int a, b, c, d, e, f, L; scanf( %d%d%d%d%d%d , &a, &b, &c, &d, &e, &f); L = a + b + c; printf( %d n , L * L - a * a - c * c - e * e); }
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#include <bits/stdc++.h> using namespace std; vector<int> scs(const string& s) { int n = s.size(); vector<int> p(n), c(s.begin(), s.end()); vector<vector<int>> g(max(n, 256)); for (int i = 0; i < n; i++) g[c[i]].push_back(i); int b = 0; for (auto& gr : g) { for (int x : gr) p[b++] = x; gr.clear(); } for (int h = 1; h < n; h <<= 1) { vector<int> p2(n), c2(n); for (int j : p) { int jp = (j + n - h) % n; g[c[jp]].push_back(jp); } b = 0; for (auto& gr : g) { for (int x : gr) p2[b++] = x; gr.clear(); } b = 0; c2[p2[0]] = 0; for (int i = 1; i < n; i++) { int x = p2[i]; int y = p2[i - 1]; if (c[x] == c[y] && c[(x + h) % n] == c[(y + h) % n]) c2[x] = b; else c2[x] = ++b; } swap(c, c2); swap(p, p2); } return p; } struct stvar { int a, b; stvar(int x = 0) : a(x), b(min(0, x)) {} stvar(int p, int q) : a(p), b(q) {} stvar operator+(const stvar& o) const { return stvar(a + o.a, min(b, a + o.b)); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); string s; cin >> s; int n = s.size(); vector<int> p = scs(s); vector<stvar> pref(n + 1), suff(n + 1); for (int i = 0; i < n; i++) pref[i + 1] = pref[i] + stvar(s[i] == ( ? 1 : -1); for (int i = n - 1; i >= 0; i--) suff[i] = stvar(s[i] == ( ? 1 : -1) + suff[i + 1]; for (int j : p) { auto t = suff[j] + pref[j]; if (t.a < 0) { if (t.a == t.b) { cout << string(-t.a, ( ) << s.substr(j) << s.substr(0, j) << n ; return 0; } } else { if (t.b == 0) { cout << s.substr(j) << s.substr(0, j) << string(t.a, ) ) << n ; return 0; } } } }
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#include <bits/stdc++.h> using namespace std; struct block { string str; int pos; }; static bool compare(block b1, block b2) { int n = b1.str.length(); for (int i = 0; i < n; i++) { if (b1.str[i] != b2.str[i]) { if ((i + 1) % 2) { return (b1.str[i] < b2.str[i]); } else { return (b1.str[i] > b2.str[i]); } } } } int main() { int n, m; cin >> n >> m; vector<block> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i].str; arr[i].pos = i + 1; } sort(arr.begin(), arr.end(), compare); for (int i = 0; i < n; i++) { cout << arr[i].pos << ; } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__EINVN_PP_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_4_V
`define SKY130_FD_SC_LP__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_4_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const int maxn = 1e6 + 2; const int base = 31; const int mod = 1e9 + 7; ll t; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> t; while (t--) { ll n, x = 0; cin >> n; vector<ll> a(n); for (ll i = 0; i < n; i++) { cin >> a[i]; x ^= a[i]; } if (x == 0) cout << DRAW n ; else { ll bit = 30; while (!(x & (1 << bit))) { --bit; } ll k0 = 0, k1 = 0; for (auto k : a) { if (k & (1 << bit)) { k1++; } else k0++; } assert(k1 % 2 == 1); if (k0 % 2 == 0 && k1 % 4 == 3) { cout << LOSE << n ; } else cout << WIN << n ; } } }
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [8-1:0] cmd_repeat,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [8-1:0] repeat_cnt_pre;
reg [8-1:0] repeat_cnt;
wire [8-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 8'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 2'b01;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 8'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = cmd_id;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A211O_PP_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a211o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); string s; cin >> s; string v = aeiou ; string c = bcdfghjklmnpqrstvwxyz ; map<char, int> cnt; map<char, int> mp; for (auto i : v) mp[i] = 1; for (auto i : c) mp[i] = 0; string temp = ; int vc = 0; int cc = 0; int dc = 0; vector<string> ans; for (int i = 0; i < s.size(); i++) { if (mp[s[i]] == 1) { cc = 0; dc = 0; for (auto j : c) cnt[j] = 0; } else { if (cnt[s[i]] == 0) { cnt[s[i]]++; dc++; cc++; } else { cnt[s[i]]++; cc++; } } if (cc > 2 && dc > 1) { ans.push_back(temp); for (auto j : c) cnt[j] = 0; cnt[s[i]] = 1; cc = 1; dc = 1; temp = s[i]; } else temp += s[i]; } ans.push_back(temp); for (auto i : ans) cout << i << ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long blk = 300; struct data { long long l, r, i; data() { l = r = i = 0; } data(long long v1, long long v2, long long v3) { l = v1; r = v2; i = v3; } bool operator<(const data &x) const { if (l / blk != x.l / blk) return (l / blk < x.l / blk); else return (r < x.r); } }; long long num[100005], num2[100005]; data query[100005]; long long freq[1048600], freq2[1048600]; long long output[100005]; int main() { long long a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t; scanf( %lld %lld %lld , &a, &b, &c); num[0] = 0; for (i = 1; i <= a; i++) { scanf( %lld , &num[i]); num2[i] = num[i]; num[i] ^= num[i - 1]; } for (i = a - 1; i >= 1; i--) num2[i] ^= num2[i + 1]; for (i = 1; i <= b; i++) { scanf( %lld %lld , &d, &e); query[i] = data(d, e, i); } sort(query + 1, query + b + 1); memset(freq, 0, sizeof(freq)); l = 1; r = 0; long long ans = 0; num[a + 1] = 0; freq[0]++; freq2[num2[1]]++; for (i = 1; i <= b; i++) { freq2[num2[r + 1]]--; while (r < query[i].r) { r++; ans += freq[c ^ num[r]]; freq[num[r]]++; freq2[num2[r]]++; } while (r > query[i].r) { freq[num[r]]--; freq2[num2[r]]--; ans -= freq[c ^ num[r]]; r--; } freq2[num2[r + 1]]++; freq[num[l - 1]]--; while (l < query[i].l) { freq2[num2[l]]--; freq[num[l]]--; ans -= freq2[c ^ num2[l]]; l++; } while (l > query[i].l) { l--; ans += freq2[c ^ num2[l]]; freq2[num2[l]]++; freq[num[l]]++; } freq[num[l - 1]]++; output[query[i].i] = ans; } for (i = 1; i <= b; i++) { printf( %lld n , output[i]); } return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 16:36:06 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul17_16_stub.v
// Design : mul17_16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[16:0],B[15:0],P[16:0]" */;
input CLK;
input [16:0]A;
input [15:0]B;
output [16:0]P;
endmodule
|
`timescale 1ns/1ps
module dv_elink_tb();
parameter AW=32;
parameter DW=32;
parameter PW=104;
parameter CW=2; //number of clocks to send int
parameter MW=104;
parameter MAW=10;
parameter MD=1<<MAW;//limit test to 1K transactions
//TODO:generealize
/* verilator lint_off STMTDLY */
/* verilator lint_off UNOPTFLAT */
//REGS
reg clk;
reg reset;
reg go;
reg [1:0] datamode;
reg ext_access;
reg ext_write;
reg [1:0] ext_datamode;
reg [3:0] ext_ctrlmode;
reg [31:0] ext_dstaddr;
reg [31:0] ext_data;
reg [31:0] ext_srcaddr;
reg ext_wr_wait;
reg ext_rd_wait;
wire [PW-1:0] ext_packet;
reg init;
reg [MW-1:0] stimarray[MD-1:0];
reg [MW-1:0] transaction;
reg [MAW-1:0] stim_addr;
reg [1:0] state;
reg [31:0] count;
reg start;
integer i;
`ifdef MANUAL
//TODO: make test name a parameter, fancify,...
initial
begin
for(i=0;i<MD;i++)
stimarray[i]='d0;
//$readmemh(`TESTNAME,stimarray,0,`TRANS-1);//How to?
$readmemh("test.memh",stimarray,0,`TRANS-1);
end
`endif
//Forever clock
always
#5 clk = ~clk; //system clock (100MHz)
wire clkstim = clk;
//Reset
initial
begin
#0
reset = 1'b1; // reset is active
start = 1'b0;
clk = 1'b0;
#1000
`ifdef AUTO
//clock config (fast /2)
dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0113;
//tx config (enable)
dv_elink.elink.ecfg.ecfg_tx_reg[8:0] = 9'h001;
//rx config (enable)
dv_elink.elink.ecfg.ecfg_rx_reg[4:0] = 5'h01;
`endif
reset = 1'b0; // at time 100 release reset
#4000
start = 1'b1;
#10000
$finish;
end
`define IDLE 2'b00
`define DONE 2'b10
`define GO 2'b01
always @ (posedge clk or posedge reset)
if(reset)
state[1:0] <= `IDLE;//not started
else if(start & (state[1:0]==`IDLE))
state[1:0] <= `GO;//going
else if( ~(|count) & (state[1:0]==`GO))
state[1:0] <= `DONE;//gone
//Notes:The testbench
// connects a 64 bit master to a 32 bit slave
//To make this work, we limit the addresses to 64 bit aligned
//Stimulus Driver
always @ (posedge clkstim)
if(reset)
begin
ext_access <= 1'b0; //empty
ext_write <= 1'b0;
ext_datamode[1:0] <= 2'b0;
ext_ctrlmode[3:0] <= 4'b0;
ext_data[31:0] <= 32'b0;
ext_dstaddr[31:0] <= 32'b0;
ext_srcaddr[31:0] <= 32'b0;
ext_rd_wait <= 1'b0;
ext_wr_wait <= 1'b0;
stim_addr[MAW-1:0] <= 'd0;
transaction[MW-1:0] <= 'd0;
count <= `TRANS;
end
else if ((state[1:0]==`GO) & ~(dut_wr_wait|dut_rd_wait))
begin
transaction[MW-1:0] <= stimarray[stim_addr];
ext_access <= transaction[0];
ext_write <= transaction[1];
ext_datamode[1:0] <= transaction[3:2];
ext_ctrlmode[3:0] <= transaction[7:4];
ext_dstaddr[31:0] <= transaction[39:8];
ext_data[31:0] <= transaction[71:40];
ext_srcaddr[31:0] <= transaction[103:72];
stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1;
count <= count - 1'b1;
end
else
ext_access <= 1'b0;
//Waveform dump
`ifndef TARGET_VERILATOR
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, dv_elink_tb);
end
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dut_access; // From dv_elink of dv_elink.v
wire dut_failed; // From dv_elink of dv_elink.v
wire [PW-1:0] dut_packet; // From dv_elink of dv_elink.v
wire dut_passed; // From dv_elink of dv_elink.v
wire dut_rd_wait; // From dv_elink of dv_elink.v
wire dut_wr_wait; // From dv_elink of dv_elink.v
// End of automatics
emesh2packet e2p (
// Outputs
.packet_out (ext_packet[PW-1:0]),
// Inputs
.access_in (ext_access),
.write_in (ext_write),
.datamode_in (ext_datamode[1:0]),
.ctrlmode_in (ext_ctrlmode[3:0]),
.dstaddr_in (ext_dstaddr[AW-1:0]),
.data_in (ext_data[DW-1:0]),
.srcaddr_in (ext_srcaddr[AW-1:0]));
//dut
dv_elink dv_elink(/*AUTOINST*/
// Outputs
.dut_passed (dut_passed),
.dut_failed (dut_failed),
.dut_rd_wait (dut_rd_wait),
.dut_wr_wait (dut_wr_wait),
.dut_access (dut_access),
.dut_packet (dut_packet[PW-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.ext_access (ext_access),
.ext_packet (ext_packet[PW-1:0]),
.ext_rd_wait (ext_rd_wait),
.ext_wr_wait (ext_wr_wait));
endmodule // dv_elink_tb
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000 * 1000 * 1000 + 7; const int INF = 1e9 + 100; const long long LINF = 1e18 + 100; long long x, k; const int n = 1e5; vector<long long> divs; vector<long long> ddv[7010]; vector<long long> fk[7010]; void getnxt(const vector<long long> &cur, vector<long long> &res) { res.clear(); for (int ptr = 0; ptr < (int)cur.size() && (int)res.size() < n; ptr++) { int p = lower_bound((divs).begin(), (divs).end(), cur[ptr]) - divs.begin(); for (int i = 0; i < (int)ddv[p].size() && (int)res.size() < n; i++) res.push_back(ddv[p][i]); } } void get2i(const vector<long long> &cur, vector<long long> &res) { res.clear(); for (int i = (0); i < (7010); i++) fk[i].clear(); int cnum = 0; for (long long u : cur) { int p = lower_bound((divs).begin(), (divs).end(), u) - divs.begin(); fk[cnum].push_back(u); if (p == cnum) cnum++; } for (int ptr = 0; ptr < (int)cur.size() && (int)res.size() < n; ptr++) { int p = lower_bound((divs).begin(), (divs).end(), cur[ptr]) - divs.begin(); for (int i = 0; i < (int)fk[p].size() && (int)res.size() < n; i++) res.push_back(fk[p][i]); } vector<long long> cop; cop.swap(res); getnxt(cop, res); } void getkth(vector<long long> &res, int k) { if (k == 1) { res = divs; return; } getkth(res, k / 2); vector<long long> cop; cop.swap(res); get2i(cop, res); if (k % 2 == 0) return; cop.clear(); cop.swap(res); getnxt(cop, res); } int32_t main(void) { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> x >> k; if (k == 0) return cout << x << n , 0; if (x == 1) { return cout << 1 n , 0; } if (k > n) { for (int i = (0); i < (n); i++) cout << 1 ; cout << n ; return 0; } for (long long i = 1; i * i <= x; i++) { if (x % i == 0) { divs.push_back(i); if (i * i != x) divs.push_back(x / i); } } sort((divs).begin(), (divs).end()); for (int i = (0); i < ((int)divs.size()); i++) { for (int j = (0); j < (i + 1); j++) { if (divs[i] % divs[j] == 0) ddv[i].push_back(divs[j]); } } vector<long long> ans; getkth(ans, k); for (long long u : ans) cout << u << ; cout << n ; return 0; }
|
module transmit_test_entity_tb ;
//input
reg clk_in ;
reg reset_n ;
//output
wire Sample_Gate ;
wire [15:0] P ;
wire [15:0] N ;
wire HV_SW_CLR ;
wire HV_SW_LE ;
wire HV_SW_CLK ;
wire HV_SW_DOUT;
wire [3:0] AX ;
wire [2:0] AY ;
wire MT_CS ;
wire MT_Strobe;
wire MT_Data ;
transmit_test_entity transmit_test_entity (
//input
.clk_in (clk_in) ,
.reset_n (reset_n) ,
//output
.Sample_Gate (Sample_Gate), //
.P (P),
.N (N ),
.HV_SW_CLR (HV_SW_CLR),
.HV_SW_LE (HV_SW_LE),
.HV_SW_CLK (HV_SW_CLK),
.HV_SW_DOUT (HV_SW_DOUT),
.AX (AX ),
.AY (AY),
.MT_CS (MT_CS) ,
.MT_Strobe (MT_Strobe),
.MT_Data (MT_Data)
);
initial
clk_in = 1'b0;
always
clk_in = #5 ~clk_in;
initial
begin
reset_n = 1'b0;
#400;
reset_n = 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; long long fn(string a, string b) { long long n = a.size(), m = b.size(), j = 0; for (long long i = 0; i < m; i++) { if (b[i] == a[j]) { j++; if (j >= n) { return m - n; } } } if (j >= n) { return m - n; } return m - j + n - j; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long ttt; cin >> ttt; vector<string> v; long long x = 1; while (x <= inf) { string s = ; long long z = x; while (z) { s += (char)( 0 + z % 10); z /= 10; } reverse(s.begin(), s.end()); v.push_back(s); x *= 2; } while (ttt--) { string s; cin >> s; long long n = s.size(); long long ans = inf; for (auto x : v) { ans = min(ans, fn(x, s)); } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; double n, m, k; int main() { while (scanf( %lf %lf %lf , &n, &m, &k) != EOF) { if (m > n + k) { printf( %.6lf n , 0.0); continue; } double resp = 1.0; for (int i = 0; i <= k; i++) { resp *= ((m - i) / (n + k + 1 - i)); } printf( %.6lf n , 1.0 - resp); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O311AI_BEHAVIORAL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> long long T, n, k; long long a, sum, num; int main() { scanf( %I64d%I64d , &n, &k); for (long long i = 1; i <= n; i++) { scanf( %I64d , &a); if (sum - (i - 1 - num) * (n - i) * a >= k) sum += a * (i - 1 - num); else { printf( %I64d n , i); num++; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool options(long a, long b) { return a > b; } int main() { long n, i, *arr, *arrSort, *index; map<long, long> res; cin >> n; arr = new long[n]; arrSort = new long[n]; index = new long[n]; for (i = 0; i < n; i++) { cin >> arr[i]; arrSort[i] = arr[i]; } sort(arrSort, arrSort + n, options); for (i = 0; i < n; i++) { index[i] = i + 1; } for (i = 1; i < n; i++) { if (arrSort[i] == arrSort[i - 1]) { index[i] = index[i - 1]; } } for (i = 0; i < n; i++) { res[arrSort[i]] = index[i]; } for (i = 0; i < n; i++) { cout << res[arr[i]] << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_TB_V
`define SKY130_FD_SC_HS__MUX2I_TB_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A0 = 1'b1;
#140 A1 = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A0 = 1'b0;
#240 A1 = 1'b0;
#260 S = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 S = 1'b1;
#380 A1 = 1'b1;
#400 A0 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 S = 1'bx;
#480 A1 = 1'bx;
#500 A0 = 1'bx;
end
sky130_fd_sc_hs__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_TB_V
|
/*
Servo motor control demo module
Causes connected servos to swing back and forth with
different periods, individually adjustable.
*/
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//outputs to the servos
output [3:0] servo_out
);
wire rst = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
//set the onboard LEDs to a pattern for debugging.
assign led = 8'b01010101;
localparam NUM_SERVOS = 4;
//Pos is a 32 bit array (8 bits per servo)
//It would probably be better to use a 2d array.
wire [(NUM_SERVOS*8)-1:0] pos;
genvar i;
//Generate a serparate up/down counter for each servo
//Each one moves at a different speed (different CTR_LEN)
generate
for (i = 0; i < NUM_SERVOS; i=i+1) begin: counter_gen_loop
counter #(.CTR_LEN(26+i)) pos_counter (
.clk(clk),
.rst(rst),
.value(pos[(i+1)*8-1:i*8])
);
end
endgenerate
//loop to generate the servo controllers, 1 per servo.
//each one has its position connected to the corresponding
// up/down counter generated above.
generate
for (i = 0; i < NUM_SERVOS; i=i+1) begin: servo_gen_loop
servo_controller servo_sweep (
.clk(clk),
.rst(rst),
.position(pos[(i+1)*8-1:i*8]),
.servo(servo_out[i])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int mat[6][7] = { {0, 0, 0, 1, 1, 1, 1}, {0, 1, 1, 0, 0, 1, 1}, {1, 0, 1, 0, 1, 0, 1}, {0, 1, 1, 1, 1, 0, 0}, {1, 0, 1, 1, 0, 1, 0}, {1, 1, 0, 0, 1, 1, 0}, }; int aux[6][7]; int res[7]; bool solve() { int p, div; for (int i = 0; i < 6; ++i) { p = i; for (int j = i + 1; j < 6; ++j) if (abs(aux[j][i]) > abs(aux[p][i])) p = j; for (int j = 0; j <= 6; ++j) swap(aux[i][j], aux[p][j]); div = aux[i][i]; for (int k = i; k <= 6; ++k) { if (aux[i][k] % div != 0) return 0; aux[i][k] /= div; } for (int j = i + 1; j < 6; ++j) { div = aux[j][i]; for (int k = i; k <= 6; ++k) aux[j][k] -= div * aux[i][k]; } } for (int i = 6 - 1; i >= 0; --i) { res[i] = aux[i][6]; for (int k = 6 - 1; k > i; --k) res[i] -= res[k] * aux[i][k]; } return 1; } int main() { int big = 0; for (int i = 0; i < 6; ++i) scanf( %d , &mat[i][6]), big = max(big, mat[i][6]); bool g = 0; for (int i = 0; i <= big && !g; ++i) { memcpy(aux, mat, sizeof aux); for (int j = 0; j < 3; ++j) aux[j][6] -= i; g = solve(); for (int j = 0; j < 6 && g; ++j) if (res[j] < 0) g = 0; res[6] = i; int a = 0; for (int i = 0; i < 7; ++i) a += res[i]; if (!g) continue; printf( %d n , a); for (int j = 3; j >= 0; --j) { for (int i = 0; i < 7; ++i) { char b = a ; if ((i + 1) & 1 << j) b = b ; for (int k = 0; k < res[i]; ++k) printf( %c , b); } printf( n ); } } if (!g) printf( -1 n ); return 0; }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_addsub.v
// Title : PMI adder/subtractor.
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_addsub (
// ----- Inputs -------
DataA,
DataB,
Cin,
Add_Sub,
// ----- Outputs -------
Result,
Cout
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [31:0] DataA;
input [31:0] DataB;
input Cin;
input Add_Sub;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [31:0] Result;
wire [31:0] Result;
output Cout;
wire Cout;
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
generate
if (`LATTICE_FAMILY == "SC" || `LATTICE_FAMILY == "SCM") begin
wire [32:0] tmp_addResult = DataA + DataB + Cin;
wire [32:0] tmp_subResult = DataA - DataB - !Cin;
assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
end else begin
pmi_addsub #(// ----- Parameters -------
.pmi_data_width (32),
.pmi_result_width (32),
.pmi_sign ("off"),
.pmi_family (`LATTICE_FAMILY),
.module_type ("pmi_addsub"))
addsub (// ----- Inputs -------
.DataA (DataA),
.DataB (DataB),
.Cin (Cin),
.Add_Sub (Add_Sub),
// ----- Outputs -------
.Result (Result),
.Cout (Cout),
.Overflow ());
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; std::cin >> n >> m; getchar(); int a[n][m], nums[m]; for (int i = 0; i < m; i++) { nums[i] = 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { a[i][j] = getchar() - 0 ; nums[j] += a[i][j]; } getchar(); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j]) { if (nums[j] == 1) goto A; } } std::cout << YES ; return 0; A:; } printf( NO ); return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_uart
#(parameter TXDEPTH = 1,
parameter RXDEPTH = 1,
parameter CLKDIV_DEFAULT = 16'd0)
(input clk_i, input rst_i,
input we_i, input stb_i, input cyc_i, output reg ack_o,
input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
// Register Map
localparam SUART_CLKDIV = 0;
localparam SUART_TXLEVEL = 1;
localparam SUART_RXLEVEL = 2;
localparam SUART_TXCHAR = 3;
localparam SUART_RXCHAR = 4;
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
reg [15:0] clkdiv;
wire [7:0] rx_char;
wire tx_fifo_full, rx_fifo_empty;
wire [7:0] tx_fifo_level, rx_fifo_level;
always @(posedge clk_i)
if (rst_i)
ack_o <= 1'b0;
else
ack_o <= wb_acc & ~ack_o;
always @(posedge clk_i)
if (rst_i)
clkdiv <= CLKDIV_DEFAULT;
else if (wb_wr)
case(adr_i)
SUART_CLKDIV : clkdiv <= dat_i[15:0];
endcase // case(adr_i)
always @(posedge clk_i)
case (adr_i)
SUART_TXLEVEL : dat_o <= tx_fifo_level;
SUART_RXLEVEL : dat_o <= rx_fifo_level;
SUART_RXCHAR : dat_o <= rx_char;
endcase // case(adr_i)
simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
(.clk(clk_i),.rst(rst_i),
.fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == SUART_TXCHAR)),
.fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
.clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
(.clk(clk_i),.rst(rst_i),
.fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == SUART_RXCHAR)),
.fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty),
.clkdiv(clkdiv),.rx(rx_i));
assign tx_int_o = ~tx_fifo_full;
assign rx_int_o = ~rx_fifo_empty;
endmodule // simple_uart
|
// DESCRIPTION: Verilator: Dedupe optimization test.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// Contributed 2012 by Varun Koyyalagunta, Centaur Technology.
//
// Test consists of the follow logic tree, which has many obvious
// places for dedupe:
/*
output
+
--------------/ \--------------
/ \
+ +
----/ \----- ----/ \----
/ + / +
+ / \ + / \
-/ \- a b -/ \- a b
/ \ / \
+ + + +
/ \ / \ / \ / \
a b c d a b c d
*/
module t(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left,right;
add add(sum,left,right,clk);
l l(left,a,b,c,d,clk);
r r(right,a,b,c,d,clk);
endmodule
module l(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
ll ll(left,a,b,c,d,clk);
lr lr(right,a,b,c,d,clk);
endmodule
module ll(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
lll lll(left,a,b,c,d,clk);
llr llr(right,a,b,c,d,clk);
endmodule
module lll(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,a,b,clk);
endmodule
module llr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,c,d,clk);
endmodule
module lr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,a,b,clk);
endmodule
module r(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
rl rl(left,a,b,c,d,clk);
rr rr(right,a,b,c,d,clk);
endmodule
module rr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,a,b,clk);
endmodule
module rl(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
rll rll(left,a,b,c,d,clk);
rlr rlr(right,a,b,c,d,clk);
endmodule
module rll(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add2 add(sum,a,b,clk);
endmodule
module rlr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add2 add(sum,c,d,clk);
endmodule
module add(sum,x,y,clk);
output sum;
input x,y,clk;
reg t1,t2;
always @(posedge clk) begin
sum <= x + y;
end
endmodule
module add2(sum,x,y,clk);
output sum;
input x,y,clk;
reg t1,t2;
always @(posedge clk) begin
sum <= x + y;
end
endmodule
|
`ifndef DIVIDER_V
`define DIVIDER_V
`ifndef WIDTH
`define WIDTH 32
`endif
module divider(
input start,
input clk,
input [`WIDTH-1:0] dividend,
input [`WIDTH-1:0] divisor,
output reg [`WIDTH-1:0] quotient,
output [`WIDTH-1:0] remainder,
output ready);
reg [`WIDTH+`WIDTH-1:0] dividend_copy, divisor_copy, diff;
assign remainder = dividend_copy[`WIDTH-1:0];
reg [4:0] bits;
assign ready = !bits;
initial begin
bits = 0;
end
// Division by repeated subtraction
always @ (posedge clk) begin
if (ready & start) begin
bits = `WIDTH;
quotient = 0;
dividend_copy = {`WIDTH'd0, dividend};
divisor_copy = {1'b0, divisor, 31'd0};
end
else if (bits) begin
diff = dividend_copy - divisor_copy;
quotient = quotient << 1;
if (!diff[`WIDTH+`WIDTH-1]) begin
dividend_copy = diff;
quotient[0] = 1'd1;
end
divisor_copy = divisor_copy >> 1;
bits = bits - 1;
end
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int ans, tot, head[N], ver[N], Next[N], val[N], n, m, deg[N]; queue<int> q[2]; bool vis[N]; inline void add(int x, int y) { ver[++tot] = y; Next[tot] = head[x]; head[x] = tot; deg[y]++; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) scanf( %d , &val[i]); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); x++; y++; add(y, x); } for (int i = 1; i <= n; i++) if (!deg[i]) q[val[i]].push(i); while ((!q[0].empty()) || (!q[1].empty())) { while (!q[0].empty()) { int x = q[0].front(); q[0].pop(); vis[x] = true; for (int i = head[x]; i; i = Next[i]) { int y = ver[i]; if (vis[y]) continue; if (!(--deg[y])) q[val[y]].push(y); } } if (!q[1].empty()) { ans++; while (!q[1].empty()) { int x = q[1].front(); q[1].pop(); vis[x] = true; for (int i = head[x]; i; i = Next[i]) { int y = ver[i]; if (vis[y]) continue; if (!(--deg[y])) q[val[y]].push(y); } } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, count = 0; cin >> n; pair<int, int> a[3005]; set<pair<int, int>> s; for (int i = 0; i < n; i++) { cin >> x >> y; a[i] = pair<int, int>(x, y); s.insert(a[i]); } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { x = a[i].first + a[j].first; y = a[i].second + a[j].second; if (x % 2 == 0 && y % 2 == 0) { x /= 2; y /= 2; count += (s.find(pair<int, int>(x, y)) != s.end()); } } } cout << count << endl; return 0; }
|
#include bits/stdc++.h using namespace std; #define ffor(n) for(int i = 0; i < n; i++) #define fffor(n) for(int j = 0; j < n; j++) #define uwu ios_base::sync_with_stdio(false);cin.tie(NULL); #pragma GCC optimize( Ofast ) const int INF = 1e9 + 7; const long long INF2 = 1e15; void solve(void) { } bool valid = true; void verify(int current, vector <vector <int>>& asd, vector <int>& state, vector <int>& res) { if (valid == false) return; if (state[current] == 1) { valid = false; return; } if (state[current] == 2) return; if (state[current] == 0) { state[current] = 1; for (int nextnode: asd[current]) { verify(nextnode, asd, state, res); } state[current] = 2; res.push_back(current); } } int main(void) { uwu int n, k; cin >> n >> k; vector <int> v(n); ffor(n) cin >> v[i]; vector <pair <int, int>> v2(k); ffor(k) cin >> v2[i].first >> v2[i].second; set <pair <int, int>> edges; ffor(n) { if (v[i] != 0) edges.insert({v[i] - 1, i}); } ffor(k) { edges.insert({v2[i].first - 1, v2[i].second - 1}); } // next in chain vector <int> next(n, -1), prev(n, -1); for(int i = 0; i < k; i++) { next[v2[i].first - 1] = v2[i].second - 1; prev[v2[i].second - 1] = v2[i].first - 1; } vector <int> chained(n, -1); for(int i = 0; i < n; i++) { if (chained[i] != -1) continue; auto head = i, tail = i; chained[i] = i; while(prev[head] != -1) { if (chained[prev[head]] != -1) { valid = false; break; } head = prev[head]; chained[head] = i; } while(next[tail] != -1) { if (chained[next[tail]] != -1) { valid = false; break; } tail = next[tail]; chained[tail] = i; } while(tail != head) { if (v[tail] != 0 && chained[v[tail] - 1] != i) { edges.insert({v[tail] - 1, head}); } tail = prev[tail]; } } // adjacency list vector <vector <int>> asd(n); for(auto e: edges) { asd[e.first].push_back(e.second); } // topological sort vector <int> state(n), res; for(int i = 0; i < n; i++) { if (v[i] == 0) { verify(i, asd, state, res); } } vector <bool> visited(n); reverse(res.begin(), res.end()); // reverse reversed topological sort vector <int> ans, order_of(n); for(int e: res) { auto current = e; if (visited[current]) continue; // follow chain while(next[current] != -1 && visited[next[current]] != true) { ans.push_back(current); visited[current] = true; current = next[current]; } ans.push_back(current); visited[current] = true; current = next[current]; } if (valid) { // find position in answer for(int i = 0; i < ans.size(); i++) { order_of[ans[i]] = i; } // verify ordering for(int i = 0; i < v.size(); i++) { if (v[i] == 0) continue; if (order_of[v[i] - 1] > order_of[i]) valid = false; } for(int i = 0; i < k; i++) { if (order_of[v2[i].first - 1] + 1 != order_of[v2[i].second - 1]) valid = false; } if (valid) { for (auto e: ans) cout << e + 1 << ; cout << n ; } else cout << 0 << n ; } else cout << 0 << n ; } /* C: Users User Desktop comp_programming final_straw_after_this_im_switching_to_vs_code finally_switched_to_geany.cpp */
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_jp_sstl_dq_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_jp_sstl_dq_bscan(se ,mode_ctl ,bypass_enable ,clock_dr ,in
,ps_in ,bsr_so ,ps_select ,out ,bypass ,shift_dr ,bsr_si ,
update_dr );
output bsr_so ;
output out ;
output bypass ;
input se ;
input mode_ctl ;
input bypass_enable ;
input clock_dr ;
input in ;
input ps_in ;
input ps_select ;
input shift_dr ;
input bsr_si ;
input update_dr ;
wire net39 ;
wire net47 ;
wire net51 ;
wire net58 ;
wire net60 ;
wire net63 ;
wire net66 ;
bw_u1_inv_2x ps_inv (
.z (bypass ),
.a (net63 ) );
bw_u1_muxi21_2x bs_mux1 (
.z (net51 ),
.d0 (net58 ),
.d1 (ps_in ),
.s (ps_select ) );
bw_u1_muxi21_2x bs_mux2 (
.z (net47 ),
.d0 (in ),
.d1 (net60 ),
.s (net39 ) );
bw_u1_nand2_1x ps_nand2 (
.z (net63 ),
.a (net58 ),
.b (bypass_enable ) );
bw_u1_inv_2x ctl_inv2x (
.z (net39 ),
.a (net66 ) );
bw_io_jp_bs_baseblk bs_baseblk (
.upd_q (net58 ),
.bsr_si (bsr_si ),
.update_dr (update_dr ),
.clock_dr (clock_dr ),
.shift_dr (shift_dr ),
.bsr_so (bsr_so ),
.in (in ) );
bw_u1_inv_5x out_inv5x (
.z (out ),
.a (net47 ) );
bw_u1_inv_1x bs_inv1x (
.z (net60 ),
.a (net51 ) );
bw_u1_nor2_1x ctl_nor1x (
.z (net66 ),
.a (se ),
.b (mode_ctl ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000008; int n, m, k, d, i, j, e; int tmp[N], pos[N], p[N], c[N]; char s[N]; int main() { scanf( %s %d , s, &m); n = strlen(s); while (m--) { scanf( %d%d , &k, &d); for (i = 0; i < n; i++) { c[i] = (i + 1) % n; pos[i] = p[i] = i; } int t = 0; for (i = 0; i < d; i++) for (j = i; j < k; t++, j += d) p[t] = j; for (i = 0; i < n; ++i) { c[i] = p[c[i]]; } for (e = n - k + 1; e; e >>= 1) { for (i = 0; i < n; ++i) tmp[i] = c[i]; if (e & 1) for (i = 0; i < n; ++i) pos[i] = c[pos[i]]; for (i = 0; i < n; ++i) c[i] = tmp[c[i]]; } for (i = 0; i < n; ++i) tmp[(i + n - k + 1) % n] = s[pos[i]]; for (i = 0; i < n; ++i) putchar(s[i] = (char)tmp[i]); putchar( n ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x[100002] = {0}, j, t; cin >> n; t = n; for (int i = 0; i < n; i++) { cin >> j; x[j] = 1; while (t >= 1 && x[t] == 1) { cout << t << ; t--; } cout << endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 25 12:44:01 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_rxn1, srio_rxp1, srio_rxn2, srio_rxp2,
srio_rxn3, srio_rxp3, srio_txn0, srio_txp0, srio_txn1, srio_txp1, srio_txn2, srio_txp2,
srio_txn3, srio_txp3, s_axis_iotx_tvalid, s_axis_iotx_tready, s_axis_iotx_tlast,
s_axis_iotx_tdata, s_axis_iotx_tkeep, s_axis_iotx_tuser, m_axis_iorx_tvalid,
m_axis_iorx_tready, m_axis_iorx_tlast, m_axis_iorx_tdata, m_axis_iorx_tkeep,
m_axis_iorx_tuser, s_axi_maintr_rst, s_axi_maintr_awvalid, s_axi_maintr_awready,
s_axi_maintr_awaddr, s_axi_maintr_wvalid, s_axi_maintr_wready, s_axi_maintr_wdata,
s_axi_maintr_bvalid, s_axi_maintr_bready, s_axi_maintr_bresp, s_axi_maintr_arvalid,
s_axi_maintr_arready, s_axi_maintr_araddr, s_axi_maintr_rvalid, s_axi_maintr_rready,
s_axi_maintr_rdata, s_axi_maintr_rresp, sim_train_en, force_reinit, phy_mce,
phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset, phy_debug, gtrx_disperr_or,
gtrx_notintable_or, port_error, port_timeout, srio_host, port_decode_error, deviceid,
idle2_selected, phy_lcl_master_enable_out, buf_lcl_response_only_out,
buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out, phy_lcl_phy_next_fm_out,
phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out, phy_lcl_phy_rcvd_buf_stat_out,
phy_lcl_maint_only_out, port_initialized, link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_rxn2,srio_rxp2,srio_rxn3,srio_rxp3,srio_txn0,srio_txp0,srio_txn1,srio_txp1,srio_txn2,srio_txp2,srio_txn3,srio_txp3,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
input srio_rxn1;
input srio_rxp1;
input srio_rxn2;
input srio_rxp2;
input srio_rxn3;
input srio_rxp3;
output srio_txn0;
output srio_txp0;
output srio_txn1;
output srio_txp1;
output srio_txn2;
output srio_txp2;
output srio_txn3;
output srio_txp3;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
real foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n, S; scanf( %d , &n); scanf( %d , &S); string st; map<int, int> b, s; for (int i = 0; i < n; i++) { cin >> st; int p, q; scanf( %d , &p); scanf( %d , &q); if (st[0] == B ) { b[p] += q; } else { s[p] += q; } } int ct = max(0, (int)s.size() - S); for (map<int, int>::reverse_iterator it = s.rbegin(); it != s.rend(); it++) { if (ct) { ct--; continue; } cout << S << it->first << << it->second << endl; } ct = 0; for (map<int, int>::reverse_iterator it = b.rbegin(); it != b.rend(); it++) { cout << B << it->first << << it->second << endl; ct++; if (ct == S) break; } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "usb_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, ans; while (cin >> a >> b) { if (a == 0 && b == 0) cout << NO << endl; else { ans = abs(a - b); if (ans <= 1) cout << YES << endl; else cout << NO << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; long long ii = 1; vector<long long> prime; bitset<1000000> bs; void sieve() { bs.set(); bs[0] = bs[1] = 0; prime.push_back(2); for (long long i = 3; i <= 1000000; i += 2) { if (bs[i]) { for (long long j = i * i; j <= 1000000; j += i) bs[j] = 0; prime.push_back(i); } } } void solve() { long long n; cin >> n; long long l = 0; long long r = prime.size() - 1; long long p = sqrt(n); while (l <= r) { long long mid = (l + r) / 2; if (prime[mid] <= p) l = mid + 1; else r = mid - 1; } long long cn = l - 1; l = 0; r = prime.size() - 1; while (l <= r) { long long mid = (l + r) / 2; if (prime[mid] <= n) l = mid + 1; else r = mid - 1; } cout << r - cn + 1 << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long TestCase; sieve(); cin >> TestCase; while (TestCase--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int ent; long long int a, b; cin >> ent; while (ent--) { int div = 0, pls = 0; cin >> a >> b; if (a % b == 0) { cout << 0 << endl; continue; } div = a / b; pls = (div + 1) * b; cout << pls - a << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, l = 0; char a; cin >> n; for (int i = 0; i < n; i++) { cin >> a; if (a - 0 == 1) l++; else l--; } cout << abs(l); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[1000000]; for (int i = 0; i < n; i++) { cin >> a[i]; } int cur = a[n - 1]; long long total = a[n - 1]; for (int i = n - 2; i >= 0; i--) { cur = min(cur - 1, a[i]); cur = max(0, cur); total += cur; } cout << total; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Mx = 1e5 + 5; const long long inf = 1e9 + 1; struct Point { long long x, y; } point[Mx]; int n; long long ans, hmax[Mx], emax[Mx], hmin[Mx], emin[Mx]; template <class T> bool cmp(T a, T b) { return a.x < b.x; } bool judge(long long mid) { int l = 1, r = 1; long long Max, Min; while (r <= n) { while (point[r].x - point[l].x <= mid && r <= n) r++; Max = -inf; Min = inf; if (l != 1) { Max = max(Max, hmax[l - 1]); Min = min(Min, hmin[l - 1]); } if (r <= n) { Max = max(Max, emax[r]); Min = min(Min, emin[r]); } if (Max == -inf) return 1; if (Max - Min <= mid) return 1; l++; } return 0; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { long long x, y; scanf( %lld%lld , &x, &y); point[i].x = x + y; point[i].y = x - y; } sort(point + 1, point + 1 + n, cmp<Point>); hmin[0] = inf; hmax[0] = -inf; emin[n + 1] = inf; emax[n + 1] = -inf; for (int i = 1; i <= n; i++) { hmax[i] = max(hmax[i - 1], point[i].y); hmin[i] = min(hmin[i - 1], point[i].y); } for (int i = n; i >= 1; i--) { emax[i] = max(emax[i + 1], point[i].y); emin[i] = min(emin[i + 1], point[i].y); } long long l = 0, r = 2e9; while (l <= r) { long long mid = (l + r) >> 1; if (judge(mid)) { r = mid - 1; ans = mid; } else { l = mid + 1; } } printf( %lf , 1.0 * ans / 2); }
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; #define rep(a, b) for(ll a = 0; a < (b); ++a) #define pb push_back #define st first #define nd second #define all(a) a.begin(), a.end() #define lg(a) (31-__builtin_clz(a)) void solve() { int n; cin >> n; ll T[n]; rep(i, n) cin >> T[i]; sort(T, T+n); ll ans=0, odejmij=0; rep(i, n-1) ans+=T[i+1]-T[i]; rep(i, n) { ans-=i*T[i]-odejmij; odejmij+=T[i]; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int _=1; cin >> _; while(_--) solve(); }
|
#include <bits/stdc++.h> using namespace std; bool comp(pair<unsigned long long, unsigned long long> a, pair<unsigned long long, unsigned long long> b) { unsigned long long s1, s2, h1, h2; tie(s1, h1) = a; tie(s2, h2) = b; if (s1 * h2 > s2 * h1) return true; return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; unsigned long long ans = 0; string str; vector<pair<unsigned long long, unsigned long long> > arr(n); for (int i = 0; i < n; i++) { cin >> str; unsigned long long s1 = 0, h = 0; for (auto x : str) { if (x == s ) s1++; else if (x == h ) h++, ans += s1; } arr[i] = make_pair(s1, h); } sort((arr).begin(), (arr).end(), comp); unsigned long long s1 = 0; for (auto i : arr) { ans += s1 * 1LL * (i.second); s1 += i.first; } cout << ans << n ; return 0; }
|
/* Author: EndlessK * Time: 2021-05-06 20:40:25 **/ #include<bits/stdc++.h> #define maxn 100010 #define pb push_back #define ll long long #define fast ios::sync_with_stdio(false),cin.tie(0),cout.tie(0) using namespace std; int main() { fast; int t; cin>>t; map<int,int> mp; while(t--) { int n; int ans=0; cin>>n; for(int i=1;i<=min(9,n);i++) { ans++; } for(int i=11;i<=min(99,n);i+=11) { ans++; } for(int i=111;i<=min(999,n);i+=111) { ans++; } for(int i=1111;i<=min(9999,n);i+=1111) { ans++; } for(int i=11111;i<=min(99999,n);i+=11111) { ans++; } for(int i=111111;i<=min(999999,n);i+=111111) { ans++; } for(int i=1111111;i<=min(9999999,n);i+=1111111) { ans++; } for(int i=11111111;i<=min(99999999,n);i+=11111111) { ans++; } for(int i=111111111;i<=min(999999999,n);i+=111111111) { ans++; } cout<<ans<< n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_SYMBOL_V
`define SKY130_FD_SC_HD__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_SYMBOL_V
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
OUTPUTS:
pin 19: 500 kHz clock output
pin 18: same clock signal, lagging phase by ~165 ns
TEST PROCEDURE:
1) Verify pin 19 has a clock waveform with 50% duty cycle and 500 KHz frequency
2) Verify pin 18 has the same waveform, delayed by 150-175 ns
*/
module Delay(clk, clk_delayed);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P19" *)
output wire clk;
(* LOC = "P18" *)
output wire clk_delayed;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Oscillators
//The 2 MHz RC oscillator
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("2M"),
.HARDIP_DIV(1),
.FABRIC_DIV(4)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(),
.CLKOUT_FABRIC(clk)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The delay line
GP_DELAY #(.DELAY_STEPS(1)) delay(
.IN(clk),
.OUT(clk_delayed)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; const int MODD = 1000000007; struct Stop { int s, t; bool operator<(const Stop &ss) const { return t < ss.t; } } bus[MAXN]; int n, m, nn, dp[MAXN], sum[MAXN]; int main() { while (scanf( %d%d , &n, &m) != EOF) { map<int, int> stops; stops[0] = stops[n] = 0; for (int i = 0; i < m; ++i) { scanf( %d%d , &bus[i].s, &bus[i].t); stops[bus[i].s] = stops[bus[i].t] = 0; } nn = 0; for (map<int, int>::iterator it = stops.begin(); it != stops.end(); ++it) it->second = ++nn; sort(bus, bus + m); int bi = 0; dp[1] = sum[1] = 1; for (int i = 2; i <= nn; ++i) { dp[i] = 0; for (; bi < m && stops[bus[bi].t] == i; ++bi) { int ms = stops[bus[bi].s]; int mt = stops[bus[bi].t]; dp[i] = ((long long)dp[i] + sum[mt - 1] - sum[ms - 1] + MODD) % MODD; } sum[i] = ((long long)sum[i - 1] + dp[i]) % MODD; } printf( %d n , dp[nn]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> adj[200001]; long long a[200001]; vector<long long> start; stack<long long> last; long long ans; bool f; void dfs(long long); signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; set<long long> roots; for (long long i = 1; i <= n; i++) roots.insert(i); for (long long i = 1; i <= n; i++) cin >> a[i]; long long x; for (long long i = 1; i <= n; i++) { cin >> x; if (x != -1) { adj[x].push_back(i); roots.erase(i); } } start.clear(); while (!last.empty()) last.pop(); ans = 0; for (auto x : roots) { dfs(x); } cout << ans << n ; for (auto x : start) { cout << x << ; } while (!last.empty()) { cout << last.top() << ; last.pop(); } } void dfs(long long v) { for (auto x : adj[v]) { dfs(x); if (a[x] > 0) a[v] += a[x]; } ans += a[v]; if (a[v] > 0) { start.push_back(v); } else { last.push(v); } }
|
#include <bits/stdc++.h> const int maxn = 200000; using namespace std; int a[maxn], b[maxn]; int l[maxn], r[maxn]; int main() { int n, q; scanf( %d%d , &n, &q); a[0] = 0; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), b[i - 1] = abs(a[i] - a[i - 1]); for (int i = 1; i <= q; i++) { int x, y; long long ans = 0; scanf( %d%d , &x, &y); y--; l[x] = x - 1; r[y] = y + 1; for (int j = x + 1; j <= y; j++) { l[j] = j - 1; while (l[j] >= x && b[l[j]] < b[j]) l[j] = l[l[j]]; } for (int j = y - 1; j >= x; j--) { r[j] = j + 1; while (r[j] <= y && b[r[j]] <= b[j]) r[j] = r[r[j]]; } for (int j = x; j <= y; j++) ans += (long long)(l[j] - j) * (j - r[j]) * b[j]; printf( %I64d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_1_V
`define SKY130_FD_SC_HDLL__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_1_V
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline ostream &operator<<(ostream &os, const pair<T1, T2> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T, size_t N> inline ostream &operator<<(ostream &os, const array<T, N> &a) { os << [ ; int cnt = 0; for (auto &val : a) { if (cnt++) os << , ; os << val; } os << ] ; return os; } template <typename T> inline ostream &operator<<(ostream &os, const vector<T> &v) { os << [ ; int cnt = 0; for (auto &val : v) { if (cnt++) os << , ; os << val; } return os << ] ; } template <typename T> inline ostream &operator<<(ostream &os, const set<T> &v) { os << { ; int cnt = 0; for (auto &val : v) { if (cnt++) os << , ; os << val; } return os << } ; } template <typename T> inline ostream &operator<<(ostream &os, const unordered_set<T> &v) { os << { ; int cnt = 0; for (auto &val : v) { if (cnt++) os << , ; os << val; } return os << } ; } template <typename T> inline ostream &operator<<(ostream &os, const multiset<T> &v) { os << { ; int cnt = 0; for (auto &val : v) { if (cnt++) os << , ; os << val; } return os << } ; } template <typename T1, typename T2> inline ostream &operator<<(ostream &os, const map<T1, T2> &v) { os << [ ; int cnt = 0; for (auto &val : v) { if (cnt++) os << , ; os << val; } return os << ] ; } template <typename Arg1> void __f(const char *name, Arg1 &&arg1) { cerr << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char *names, Arg1 &&arg1, Args &&...args) { const char *comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } using ll = long long; using ull = unsigned long long; using vi = vector<int>; using vll = vector<long long>; using vvi = vector<vector<int>>; using vs = vector<string>; using vb = vector<bool>; using vd = vector<double>; using vvb = vector<vector<bool>>; using vvc = vector<vector<char>>; using vc = vector<char>; using si = set<int>; using mpii = map<int, int>; using pii = pair<int, int>; using pll = pair<ll, ll>; const char nl = n ; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <class T> inline bool umin(T &a, const T b) { return b < a ? a = b, 1 : 0; } template <class T> inline bool umax(T &a, const T b) { return a < b ? a = b, 1 : 0; } ll solve() { int n; cin >> n; vector<pii> t(n); vi a(n + 1, 0), b(n + 1, 0); for (int i = 0; i < (n); i++) { cin >> t[i].first >> t[i].second; a[t[i].first]++; b[t[i].second]++; } ll ans = 1LL * n * (n - 1) * (n - 2) / 6; for (int i = 0; i < (n); i++) { ans -= 1LL * (a[t[i].first] - 1) * (b[t[i].second] - 1); } return ans; } void solve(int _cas) { cout << solve() << endl; } int main() { srand(time(NULL)); ios_base::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL), cout.precision(12); int cas; cin >> cas; for (int i = 0; i < (cas); i++) solve(i + 1); }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 6e6; const long long inf = 1e18; const long long maxv = 2e8 + 100; const int miniinf = 1e9; const long double eps = 1e-6; const long long flowconst = 1e9; void init() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int main() { init(); int n; cin >> n; vector<string> ans1; vector<string> ans2; if (n == 1) { cout << ? 1 1 << endl; string ans; cin >> ans; cout << ! << ans << endl; return 0; } map<string, int> foo; cout << ? 1 << n << endl; for (int i = 0; i < n * (n + 1) / 2; i++) { string x; cin >> x; sort(x.begin(), x.end()); foo[x]++; } cout << ? 1 << n - 1 << endl; for (int i = 0; i < (n - 1) * (n) / 2; i++) { string x; cin >> x; sort(x.begin(), x.end()); foo[x]--; } vector<string> diff; for (auto ev : foo) if (ev.second == 1) diff.push_back(ev.first); sort(diff.begin(), diff.end(), [&](string &a, string &b) { return a.size() < b.size(); }); string ans; for (int i = 0; i < n; i++) { vector<int> cnt(26, 0); for (int j = 0; j < diff[i].size(); j++) { cnt[diff[i][j] - a ]++; } for (int j = 0; j < ans.size(); j++) { cnt[ans[j] - a ]--; } for (int j = 0; j < 26; j++) { if (cnt[j] > 0) { ans += a + j; } } } reverse(ans.begin(), ans.end()); cout << ! ; cout << ans << endl; return 0; }
|
// usb_avalon.v
`timescale 1 ns / 1 ps
module usb_avalon_16bit
(
input clk,
input reset,
// avs_ctrl
input avs_ctrl_address,
input avs_ctrl_write,
input [7:0]avs_ctrl_writedata,
input avs_ctrl_read,
output [7:0]avs_ctrl_readdata,
// asi_uplink
output ready,
input valid,
input [15:0]data,
input startofpacket,
input endofpacket,
input empty,
// tx fifo interface
output tx_write,
output [15:0]tx_data,
output [1:0]tx_mask,
input tx_full,
// rx fifo interface
output rx_read,
input [15:0]rx_data,
input rx_mask,
input rx_empty
);
// === avs_ctrl ===========================================================
wire [7:0]readdata_fifo;
wire [7:0]status = { 7'b0000000, !rx_empty };
wire si_request; // request for send immediate
assign si_request = avs_ctrl_write && avs_ctrl_address && avs_ctrl_writedata[0];
assign avs_ctrl_readdata = avs_ctrl_read ?
(avs_ctrl_address ? status : readdata_fifo) : 8'd0;
// --- data register
reg rx_upper;
assign readdata_fifo = rx_upper ? rx_data[15:8] : rx_data[7:0];
assign rx_read = avs_ctrl_read && !avs_ctrl_address && !rx_empty && (!rx_mask || rx_upper);
always @(posedge clk or posedge reset)
begin
if (reset) rx_upper <= 0;
else if (avs_ctrl_read && !avs_ctrl_address && !rx_empty)
rx_upper <= !rx_upper && rx_mask;
end
// === asi_uplink =========================================================
assign ready = !tx_full;
wire tx_empty = endofpacket && empty;
wire tx_write_dat = valid && ready;
reg si; // send immediate request received
wire si_send = si && ready && !valid;
always @(posedge clk or posedge reset)
begin
if (reset) si <= 0;
else if (si_send) si <= 0;
else if (si_request) si <= 1;
end
assign tx_data = {data[7:0], data[15:8]};
assign tx_mask = si_send ? 2'b00 : {!tx_empty, 1'b1};
assign tx_write = si_send || tx_write_dat;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_FUNCTIONAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_16_V
`define SKY130_FD_SC_HDLL__NAND2_16_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_16 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_16 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_16_V
|
#include <bits/stdc++.h> using namespace std; int n, k, h; struct Node { int m, v; int id; bool operator<(const Node &x) const { if (m != x.m) return m < x.m; return v < x.v; } } q[100005]; bool ok(double times) { int i, j; for (j = 1, i = 0; i < n; i++) { if (q[i].v * times - (double)j * h >= -1e-9) j++; if (j > k) return true; } return false; } int main() { int i, j; cin >> n >> k >> h; for (i = 0; i < n; i++) cin >> q[i].m; for (i = 0; i < n; i++) { cin >> q[i].v; q[i].id = i + 1; } sort(q, q + n); double l, r, mid; l = 0, r = 1e20; for (int i = 0; i < 200; i++) { mid = (l + r) * 0.5; if (!ok(mid)) l = mid; else r = mid; } j = 1; for (i = 0; i < n; i++) { if (q[i].v * r - (double)j * h >= -1e-9) { cout << q[i].id << ; j++; } if (j > k) break; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:04:40 06/02/2013
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Alu(Alu_in1,Alu_in2,Alu_sel,Alu_zero_flg,Alu_out
);
parameter wrd_size = 8,
sel_width= 3;
input [wrd_size-1:0] Alu_in1,Alu_in2;
input [sel_width-1:0] Alu_sel;
output reg [wrd_size-1:0] Alu_out;
output Alu_zero_flg;
localparam NOP = 3'b000,
ADD = 3'b001,
SUB = 3'b010,
AND = 3'b011,
OR = 3'b100,
SLT = 3'b101,
SRT = 3'b110,
NOT = 3'b111;
assign Alu_zero_flg = ~|Alu_out;
always @(*)
case(Alu_sel)
NOP: Alu_out = 0;
AND: Alu_out = Alu_in1&Alu_in2;
OR: Alu_out = Alu_in1|Alu_in2;
ADD: Alu_out = Alu_in1+Alu_in2;
SUB: Alu_out = Alu_in1-Alu_in2;
NOT: Alu_out = ~Alu_in1;
SLT: Alu_out = Alu_in1<<Alu_in2;
SRT: Alu_out = Alu_in1>>Alu_in2;
default: Alu_out = 0;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void dbg(T t) { cerr << t << endl; } template <typename T, typename... Args> void dbg(T t, Args... args) { cerr << t << ; dbg(args...); } int main() { ios::sync_with_stdio(0); cin.tie(0); int n, a, spec = 3; int t[2] = {1, 2}; cin >> n; for (int i = 0; i < n; i++) { cin >> a; if (spec == a) { cout << NO << endl; return 0; } for (int j = 0; j < 2; j++) if (t[j] != a) swap(t[j], spec); } cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long OO = 1e18; vector<int> prs = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29}; long long solve(long long num, int in, int lst) { if (in == prs.size() || lst == 0) return num == 1 ? 1 : -1; long long res = -1; long long cur = 1; long long cp = num; for (int i = 0; i <= lst; i++) { if (num < (i + 1) || cur > OO || (i && cur > OO / prs[in])) break; if (i) cur *= prs[in]; if (num % (i + 1) != 0) continue; long long can = solve(num / (i + 1), in + 1, i); if ((res == -1 && can != -1) || (can != -1 && can < (res + cur - 1) / cur)) res = cur * can; } return res; } int main() { long long n; cin >> n; cout << solve(n, 0, 100); }
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j, k, s, p, x[100001], t[100001], w[100001]; void sort1(int l, int r) { int i, j, y, z; i = l; j = r; y = x[(l + r) / 2]; do { while (x[i] < y) { i++; } while (x[j] > y) { j--; } if (!(i > j)) { z = x[i]; x[i] = x[j]; x[j] = z; z = t[i]; t[i] = t[j]; t[j] = z; i++; j--; } } while (!(i > j)); if (l < j) { sort1(l, j); } if (i < r) { sort1(i, r); } } void sort2(int l, int r) { int i, j, y, z; i = l; j = r; y = t[(l + r) / 2]; do { while (t[i] < y) { i++; } while (t[j] > y) { j--; } if (!(i > j)) { z = x[i]; x[i] = x[j]; x[j] = z; z = t[i]; t[i] = t[j]; t[j] = z; z = w[i]; w[i] = w[j]; w[j] = z; i++; j--; } } while (!(i > j)); if (l < j) { sort2(l, j); } if (i < r) { sort2(i, r); } } int main() { scanf( %d %d n , &n, &m); for (i = 1; i <= n; i++) { scanf( %d %d n , &t[i], &x[i]); } i = m; s = 0; while (i <= n) { s = max(s, t[i]); sort1(i - m + 1, i); p = x[i]; k = 1; w[i - m + 1] = s + x[i - m + 1]; for (j = i - m + 2; j <= i; j++) { if (x[j] == x[j - 1]) { k++; } else { s += 1 + (k / 2); k = 1; } w[j] = s + x[j]; } s += p + 1 + p + (k / 2); i += m; } if (i - m < n) { s = max(s, t[n]); sort1(i - m + 1, n); p = x[n]; k = 1; w[i - m + 1] = s + x[i - m + 1]; for (j = i - m + 2; j <= n; j++) { if (x[j] == x[j - 1]) { k++; } else { s += 1 + k / 2; k = 1; } w[j] = s + x[j]; } s += p + 1 + p + k / 2; } sort2(1, n); for (i = 1; i <= n; i++) { printf( %d , w[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int buf_size = 1e5 + 5; char buf[buf_size], *S, *T; inline char gc() { if (S == T) T = (S = buf) + fread(buf, 1, buf_size, stdin); return S != T ? *(S++) : EOF; } inline int in() { int x = 0, f = 1; char c = gc(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = gc(); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 48, c = gc(); return x * f; } const int N = 2e6 + 5, mod = 1e9 + 7; int q, x, y, n = 2000000, ans; int inv[N], fac[N], finv[N]; int pri[N], pc, c[N]; int p[N]; bool inp[N]; int a[105], ac; inline int add(const int &a, const int &b) { return a + b >= mod ? a + b - mod : a + b; } inline int mul(const int &a, const int &b) { return 1ll * a * b % mod; } inline int C(const int &a, const int &b) { return mul(fac[a], mul(finv[b], finv[a - b])); } int main() { inv[1] = fac[0] = fac[1] = finv[0] = finv[1] = 1; for (int i = 2; i <= n; i++) { inv[i] = mul(mod - mod / i, inv[mod % i]); fac[i] = mul(fac[i - 1], i); finv[i] = mul(finv[i - 1], inv[i]); } for (int i = 2; i <= n; i++) { if (!inp[i]) pri[++pc] = i, c[i] = i; for (int j = 1; j <= pc && i * pri[j] <= n; j++) { inp[i * pri[j]] = 1; c[i * pri[j]] = pri[j]; if (i % pri[j] == 0) break; } } p[0] = 1; for (int i = 1; i <= n; i++) p[i] = mul(p[i - 1], 2); q = in(); while (q--) { x = in(), y = in(); ac = 0, ans = 0; int res = 1; while (x > 1) { a[++ac] = c[x]; x /= c[x]; } for (int i = 1, j; i <= ac; i = j + 1) { j = i; while (j + 1 <= ac && a[j + 1] == a[i]) j++; res = mul(res, C(j - i + y, y - 1)); } ans = mul(res, p[y - 1]); printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_TB_V
`define SKY130_FD_SC_MS__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, x; cin >> n >> x; long long count = 0; if (n >= x) { for (long long i = 1; i < n + 1; i++) { if (x % i == 0) { count++; } } } else { for (long long i = 2; i < n + 1; i++) { if (x % i == 0 && ((x / i) <= n)) { count++; } } } cout << count; }
|
//////////////////////////////////////////////////////////////////
// //
// Arithmetic Logic Unit (ALU) for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Supported functions: 32-bit add and subtract, AND, OR, //
// XOR, NOT, Zero extent 8-bit numbers //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_alu (
input [31:0] i_a_in,
input [31:0] i_b_in,
input i_barrel_shift_carry,
input i_status_bits_carry,
input [8:0] i_function,
output [31:0] o_out,
output [3:0] o_flags // negative, zero, carry, overflow
);
wire [31:0] a, b, b_not;
wire [31:0] and_out, or_out, xor_out;
wire [31:0] sign_ex8_out, sign_ex_16_out;
wire [31:0] zero_ex8_out, zero_ex_16_out;
wire [32:0] fadder_out;
wire swap_sel;
wire not_sel;
wire [1:0] cin_sel;
wire cout_sel;
wire [3:0] out_sel;
wire carry_in;
wire carry_out;
wire overflow_out;
wire fadder_carry_out;
assign { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function;
// ========================================================
// A Select
// ========================================================
assign a = (swap_sel ) ? i_b_in : i_a_in ;
// ========================================================
// B Select
// ========================================================
assign b = (swap_sel ) ? i_a_in : i_b_in ;
// ========================================================
// Not Select
// ========================================================
assign b_not = (not_sel ) ? ~b : b ;
// ========================================================
// Cin Select
// ========================================================
assign carry_in = (cin_sel==2'd0 ) ? 1'd0 :
(cin_sel==2'd1 ) ? 1'd1 :
i_status_bits_carry ; // add with carry
// ========================================================
// Cout Select
// ========================================================
assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out :
i_barrel_shift_carry ;
// For non-addition/subtractions that incorporate a shift
// operation, C is set to the last bit
// shifted out of the value by the shifter.
// ========================================================
// Overflow out
// ========================================================
// Only assert the overflow flag when using the adder
assign overflow_out = out_sel == 4'd1 &&
// overflow if adding two positive numbers and get a negative number
( (!a[31] && !b_not[31] && fadder_out[31]) ||
// or adding two negative numbers and get a positive number
(a[31] && b_not[31] && !fadder_out[31]) );
// ========================================================
// ALU Operations
// ========================================================
`ifdef XILINX_FPGA
// XIlinx Spartan 6 DSP module
`ifdef XILINX_SPARTAN6_FPGA
xs6_addsub_n #(.WIDTH(33))
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_addsub_n #(.WIDTH(33))
`endif
u_xx_addsub_33(
.i_a ( {1'd0,a} ),
.i_b ( {1'd0,b_not} ),
.i_cin ( carry_in ),
.i_sub ( 1'd0 ),
.o_sum ( fadder_out ),
.o_co ( )
);
`else
assign fadder_out = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in};
`endif
assign fadder_carry_out = fadder_out[32];
assign and_out = a & b_not;
assign or_out = a | b_not;
assign xor_out = a ^ b_not;
assign zero_ex8_out = {24'd0, b_not[7:0]};
assign zero_ex_16_out = {16'd0, b_not[15:0]};
assign sign_ex8_out = {{24{b_not[7]}}, b_not[7:0]};
assign sign_ex_16_out = {{16{b_not[15]}}, b_not[15:0]};
// ========================================================
// Out Select
// ========================================================
assign o_out = out_sel == 4'd0 ? b_not :
out_sel == 4'd1 ? fadder_out[31:0] :
out_sel == 4'd2 ? zero_ex_16_out :
out_sel == 4'd3 ? zero_ex8_out :
out_sel == 4'd4 ? sign_ex_16_out :
out_sel == 4'd5 ? sign_ex8_out :
out_sel == 4'd6 ? xor_out :
out_sel == 4'd7 ? or_out :
and_out ;
assign o_flags = { o_out[31], // negative
|o_out == 1'd0, // zero
carry_out, // carry
overflow_out // overflow
};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long first[60]; void do_it(long long n2, long long k2, long long x) { if (n2 == 1) { cout << x + 1; return; } if (n2 == 2) { if (k2 == 1) cout << x + 2 << << x + 1; else cout << x + 1 << << x + 2; return; } if (k2 < first[n2 - 1]) { cout << x + 1 << ; do_it(n2 - 1, k2, x + 1); } else { k2 -= first[n2 - 1]; cout << x + 2 << << x + 1 << ; do_it(n2 - 2, k2, x + 2); } } long long n, k; int main() { first[0] = 1, first[1] = 1; for (long long i = (2); i < (60); i++) first[i] = first[i - 1] + first[i - 2]; cin >> n >> k; k--; do_it(n, k, 0); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long test, i, j, xy, flag = 0, n, u, count, d, o1 = 0, o2 = 0, s, e, l, r, x, y, m, z, max1, x1, y1, k, x2, y2, z1, sum, f, min1; cin >> test; while (test--) { x1 = y1 = 0; string a; cin >> n >> x >> y >> z >> a; for (i = 0; i < n; i++) { if (a[i] == 0 ) { x1++; } else { y1++; } } x2 = (x1 * z) + (x1 * y) + (y1 * y); y2 = (y1 * z) + (y1 * x) + (x1 * x); z1 = x1 * x + y1 * y; cout << min(min(x2, y2), z1) << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_TB_V
`define SKY130_FD_SC_LS__O311A_TB_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_TB_V
|
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : AD7401.v
// MODULE NAME : AD7401
// AUTHOR : Adrian Costina
// AUTHOR'S EMAIL :
// -----------------------------------------------------------------------------
// KEYWORDS : Analog Devices, Motor Control, AD7401
// -----------------------------------------------------------------------------
// PURPOSE : Driver for
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Active high reset signal
// Clock Domains : fpga_clk_i, 100 MHz
// adc_clk_i, up to 20 MHz
// Critical Timing : N/A
// Test Features : N/A
// Asynchronous I/F : N/A
// Instantiations : N/A
// Synthesizable (y/n) : Y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
`timescale 1 ns / 100 ps //Use a timescale that is best for simulation.
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module ad7401
//----------- Ports Declarations -----------------------------------------------
(
//clock and reset signals
input fpga_clk_i, // system clock
input adc_clk_i, // up to 20 MHZ clock
input reset_i, // active high reset signal
//IP control and data interface
output reg [15:0] data_o, // data read from the ADC
output reg data_rd_ready_o, // when set to high the data read from the ADC is available on the data_o bus
output reg adc_status_o,
//AD7401 control and data interface
input adc_mdata_i // AD7401 MDAT pin
);
//------------------------------------------------------------------------------
//----------- Wire Declarations ------------------------------------------------
//------------------------------------------------------------------------------
wire data_rdy_s;
wire [15:0] data_s ;
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
//State machine
reg [3:0] present_state;
reg [3:0] next_state;
reg data_rdy_s_d1;
reg data_rdy_s_d2;
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
//States
localparam WAIT_DATA_RDY_HIGH_STATE = 4'b0001;
localparam ACQUIRE_DATA_STATE = 4'b0010;
localparam TRANSFER_DATA_STATE = 4'b0100;
localparam WAIT_DATA_RDY_LOW_STATE = 4'b1000;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// synchronize data on fpga_clki
always @(posedge fpga_clk_i)
begin
data_rdy_s_d1 <= data_rdy_s;
data_rdy_s_d2 <= data_rdy_s_d1;
end
always @(posedge fpga_clk_i)
begin
if(reset_i == 1'b1)
begin
present_state <= WAIT_DATA_RDY_HIGH_STATE;
adc_status_o <= 1'b0;
end
else
begin
present_state <= next_state;
case (present_state)
WAIT_DATA_RDY_HIGH_STATE:
begin
data_rd_ready_o <= 1'b0;
end
ACQUIRE_DATA_STATE: // Acquire data from the filter
begin
data_o <= data_s;
data_rd_ready_o <= 1'b0;
adc_status_o <= 1'b1;
end
TRANSFER_DATA_STATE: // Transfer data to the upper module to write in memory
begin
data_rd_ready_o <= 1'b1;
end
WAIT_DATA_RDY_LOW_STATE:
begin
data_rd_ready_o <= 1'b0;
end
endcase
end
end
always @(present_state, data_rdy_s_d2)
begin
next_state <= present_state;
case (present_state)
WAIT_DATA_RDY_HIGH_STATE:
begin
if(data_rdy_s_d2 == 1'b1)
begin
next_state <= ACQUIRE_DATA_STATE;
end
end
ACQUIRE_DATA_STATE:
begin
next_state <= TRANSFER_DATA_STATE;
end
TRANSFER_DATA_STATE:
begin
next_state <= WAIT_DATA_RDY_LOW_STATE;
end
WAIT_DATA_RDY_LOW_STATE:
begin
if(data_rdy_s_d2 == 1'b0)
begin
next_state <= WAIT_DATA_RDY_HIGH_STATE;
end
end
default:
begin
next_state <= WAIT_DATA_RDY_HIGH_STATE;
end
endcase
end
dec256sinc24b filter(
.mclkout_i(adc_clk_i),
.reset_i(reset_i),
.mdata_i(adc_mdata_i),
.data_rdy_o(data_rdy_s),
.data_o(data_s));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, mod; long long expsq(long long base, long long exp) { if (exp == 0) return 1ll; if (exp == 1) return base; if (exp & 1) return (base * expsq((base % mod * base % mod) % mod, (exp - 1) / 2)) % mod; return expsq((base % mod * base % mod) % mod, exp / 2) % mod; } int main() { cin >> n >> mod; long long ans = expsq(3ll, n); ans--; while (ans < 0) ans += mod; cout << ans % mod; }
|
module io1_sub(
/*AUTOARG*/);
wire [42:0] bscan_data; // boundary scan stitch
parameter bscan_count = 0;
assign bscan_data[0] = bscan_in;
/*
* Emacs template to auto instaniate MD[31:0] pads
*/
/*
autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@]),
.pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
.pin_out(SDRAM_DQ_out[@]),
.pin_outen(SDRAM_DQ_outen),
.sdrmode(SDRAM_single_rate),
.hw_enb(SDRAM_upper_word_enb),
.ff_rptr(SDRAM_ddr_inff_sel),
.ff_wptr(ddr_inff_enbH),
.clk(data_strobeH),
.bscan_so(bscan_data[@ + 1]),
.bscan_si(bscan_data[@]),
.bscan_shift(BScanShift),
.bscan_clock(BScanClock),
.bscan_mode(BScanMode),
.bscan_update(BScanUpdate),
.bscan_outen(SDRAM_DQ_bscan_outen),
);
*/
autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 1)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 2)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/);
endmodule
|
// zhiyang ong
// andrew mattheisen
module mux(ina, inb, out, sel);
//INPUTS
input [0:127] ina, inb;
input sel;
// OUTPUTS
output [0:127] out;
// REGISTERS
reg [0:127] out;
always @ (ina or inb or sel)
begin
out<= sel ? ina : inb;
end // always @ (ina or inb or sel)
endmodule
`include control.h
`include mux.v
`include alu.v
`include reg
module cpu(Clk,
Reset,
Instruction, // 32 bit instruction
ProgramCounter, // 32 bit program counter
DataIn, // 128 bit data from dmem
DataOut, // 128 bit data to dmem
MemAddr, // 21 bit immediate address, only 8 bits are used
MemWrEn, // dmem write enable
MemEn // dmeme enable (to avoid spurious reads)
);
//INPUTS
input Clk, Reset;
input [0:31] Instruction, // 32 bit instruction
ProgramCounter; // 32 bit program counter
input [0:127] DataIn; // 128 bit data from dmem
//OUTPUTS
output
reg
DataOut, // 128 bit data to dmem
MemAddr, // 21 bit immediate address, only 8 bits are used
MemWrEn, // dmem write enable
MemEn // dmeme enable (to avoid spurious reads)
|
#include <bits/stdc++.h> using namespace std; long long parent[1000001]; long long result[1000005]; map<int, list<int>> g; long long getPoints(int p, int t) { return max((3 * p) / 10, (p - (p / 250) * t)); } struct Score { int p, t; }; bool chc(Score a, Score b) { if (a.p == b.p) { return a.t < b.t; } else { return a.p < b.p; } } void solve() { int n; cin >> n; int tf = 0, fifty = 0; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { int x = a[i]; if (x == 25) { tf++; } else if (x == 50) { if (tf == 0) { cout << NO n ; return; } else { tf--; } fifty++; } else if (x == 100) { if (fifty > 0 && tf > 0) { fifty--; tf--; } else if (tf > 2) { tf = tf - 3; } else { cout << NO n ; return; } } } cout << YES n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, dfsCont, dfs_num[2005], dfs_low[2005], numComp; vector<vector<int> > lista; string ans[2005]; vector<int> pila, comp; map<string, int> names; bool vis[2005]; void tarjan(int u) { dfs_low[u] = dfs_num[u] = dfsCont++; vis[u] = 1; pila.push_back(u); for (int i = 0; i < lista[u].size(); i++) { int v = lista[u][i]; if (dfs_num[v] == -1) tarjan(v); if (vis[v]) dfs_low[u] = min(dfs_low[u], dfs_low[v]); } if (dfs_low[u] == dfs_num[u]) { while (true) { int v = pila.back(); comp.push_back(v); pila.pop_back(); vis[v] = 0; if (u == v) break; } numComp++; } } int main() { scanf( %d , &n); lista.assign(n, vector<int>()); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { int x; scanf( %d , &x); if (x) lista[i].push_back(j); } pila.clear(); memset(dfs_low, 0, sizeof dfs_low); memset(dfs_num, -1, sizeof dfs_num); memset(vis, 0, sizeof vis); dfsCont = 0; numComp = 0; tarjan(0); if (numComp == 1 && comp.size() == n) printf( YES n ); else printf( NO n ); }
|
#include <bits/stdc++.h> using namespace std; inline bool EQ(double num4, double b) { return fabs(num4 - b) < 1e-9; } const int INF = 1 << 29; inline int two(int len) { return 1 << len; } inline int test(int len, int b) { return (len >> b) & 1; } inline void set_bit(int &len, int b) { len |= two(b); } inline void unset_bit(int &len, int b) { len &= ~two(b); } inline int last_bit(int len) { return len & (-len); } inline int ones(int len) { int res = 0; while (len && ++res) len -= len & (-len); return res; } template <class T> void chmax(T &num4, const T &b) { num4 = max(num4, b); } template <class T> void chmin(T &num4, const T &b) { num4 = min(num4, b); } inline void add(int &numx, int y) { numx += y; if (numx >= 1000000007) numx -= 1000000007; if (numx < 0) numx += 1000000007; } inline int mul(int numx, int y) { return ((long long)numx * y) % 1000000007; } int gcd(int num4, int b) { if (b) return gcd(b, num4 % b); return num4; } int power(int num4, int pex) { int ret = 1; while (pex) { if (pex & 1) ret = mul(ret, num4); num4 = mul(num4, num4); pex /= 2; } return ret; } int phi(int len) { int ret = len; int idxx = 2; if (len % idxx == 0) { ret -= ret / idxx; while (len % idxx == 0) len /= idxx; } for (idxx = 3; idxx * idxx <= len; idxx++) if (len % idxx == 0) { ret -= ret / idxx; while (len % idxx == 0) len /= idxx; } if (len > 1) ret -= ret / len; return ret; } using namespace std; int main() { bool flags = true; int num1, num2; cin >> num1 >> num2; int vals1 = num1 - 1, v2s = 0, v3s = 0, v4s = num2 - 1, bbs = 0; for (int i = 0; i < num1; ++i) for (int j = 0; j < num2; ++j) { char chh; cin >> chh; if (chh == B ) { vals1 = min(vals1, i); v2s = max(v2s, i); v4s = min(v4s, j); v3s = max(v3s, j); flags = false; ++bbs; } } if (flags) { cout << 1; return 0; } int weights = v3s - v4s + 1, h = v2s - vals1 + 1; if (weights > num1 || h > num2) { cout << -1; return 0; } int len = max(weights, h); cout << len * len - bbs << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:07:47 01/05/2017
// Design Name:
// Module Name: Counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Counter(
input wire clk, clr,
input wire plus,
output wire [3:0] score0, score1, score2, score3, high_score0, high_score1, high_score2, high_score3
);
reg [9:0] score, high_score;
reg [1:0] filter_plus, filter_rst;
initial
begin
score <= 10'b0;
high_score <= 10'b0;
filter_plus <= 2'b0;
filter_rst <= 2'b0;
end
always @ (posedge clk)
begin
filter_plus <= {filter_plus[0], plus};
filter_rst <= {filter_rst[0], clr};
if (filter_rst == 2'b01)
begin
score <= 10'b0;
end
else
begin
if (filter_plus == 2'b01)
score <= score + 10;
if (high_score < score)
high_score <= score;
end
end
//===========================================================
// Change the score into BCD codes
//===========================================================
assign score0 = score % 10;
assign score1 = (score / 10) % 10;
assign score2 = (score / 100) % 10;
assign score3 = score / 1000;
assign high_score0 = high_score % 10;
assign high_score1 = (high_score / 10) % 10;
assign high_score2 = (high_score / 100) % 10;
assign high_score3 = high_score / 1000;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 102; int t, n, m, r[N], b[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> t; for(int ti = 1; ti <= t; ++ti) { cin >> n; for(int i = 1; i <= n; ++i) { cin >> r[i]; r[i] += r[i - 1]; } cin >> m; for(int i = 1; i <= m; ++i) { cin >> b[i]; b[i] += b[i - 1]; } int fp = 0; for(int i = 0; i <= n; ++i) { for(int j = 0; j <= m; ++j) { fp = max(fp, r[i] + b[j]); } } cout << fp << n ; } return 0; }
|
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/18/2016
Founction: I2C top module
Note:
****************************************************************************/
module I2C_MASTER_SUBAD(clk,rst_n,sda,scl,RD_EN,WR_EN,receive_status
);
input clk;
input rst_n;
input RD_EN;
input WR_EN;
reg WR,RD;
output scl;
output receive_status;
inout sda;
reg scl_clk;
reg receive_status;
reg[7:0] clk_div;
reg[7:0] send_count;
wire[7:0] data;
reg[7:0] data_reg;
wire ack;
reg[7:0] send_memory[33:0];
reg[7:0] receive_memory[33:0];
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
scl_clk <= 1'b0;
clk_div <= 'h0;
send_memory[0] <= 8'd1;
send_memory[1] <= 8'd32;
send_memory[2] <= 8'd0;
send_memory[3] <= 8'd1;
send_memory[4] <= 8'd2;
send_memory[5] <= 8'd3;
send_memory[6] <= 8'd4;
send_memory[7] <= 8'd5;
send_memory[8] <= 8'd6;
send_memory[9] <= 8'd7;
send_memory[10] <= 8'd8;
send_memory[11] <= 8'd9;
send_memory[12] <= 8'd10;
send_memory[13] <= 8'd11;
send_memory[14] <= 8'd12;
send_memory[15] <= 8'd13;
send_memory[16] <= 8'd14;
send_memory[17] <= 8'd15;
send_memory[18] <= 8'd16;
send_memory[19] <= 8'd17;
send_memory[20] <= 8'd18;
send_memory[21] <= 8'd19;
send_memory[22] <= 8'd20;
send_memory[23] <= 8'd21;
send_memory[24] <= 8'd22;
send_memory[25] <= 8'd23;
send_memory[26] <= 8'd24;
send_memory[27] <= 8'd25;
send_memory[28] <= 8'd26;
send_memory[29] <= 8'd27;
send_memory[30] <= 8'd28;
send_memory[31] <= 8'd29;
send_memory[32] <= 8'd30;
send_memory[33] <= 8'd31;
end
else begin
if(clk_div > 'd200)begin
scl_clk <= ~scl_clk;
clk_div <= 'h0;
end
else
clk_div <= clk_div + 1'b1;
end
end
always @(posedge ack or negedge rst_n)begin
if(!rst_n)begin
send_count <= 'h0;
end
else begin
if((send_count < 10'd34) && (ack))begin
send_count <= send_count + 1'b1;
receive_memory[send_count] <= RD_EN ? data : 8'h0;
end
else begin
send_count <= send_count;
end
end
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
receive_status <= 1'b0;
else
receive_status <=(receive_memory[31]== 31) ? 1'b1 : 1'b0;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
WR <= 1'b0;
RD <= 1'b0;
data_reg <= 'h0;
end
else begin
if(send_count == 8'd34)begin
WR <= 1'b0;
RD <= 1'b0;
end
else begin
if(RD_EN)
RD <= 1'b1;
else if(WR_EN)begin
WR <= 1'b1;
data_reg <= send_memory[send_count];
end
end
end
end
assign data = WR_EN ? data_reg : 8'hz;
I2C_wr_subad I2C_wr_subad_instance(
.sda(sda),
.scl(scl),
.ack(ack),
.rst_n(rst_n),
.clk(scl_clk),
.WR(WR),
.RD(RD),
.data(data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long long dp[4]; int a[100005]; string s; int main() { cin >> n; cin >> s; for (int i = 0; i < n; i++) { cin >> a[i]; if (s[i] == h ) dp[0] += a[i]; else if (s[i] == a ) dp[1] = min(dp[0], dp[1] + a[i]); else if (s[i] == r ) dp[2] = min(dp[1], dp[2] + a[i]); else if (s[i] == d ) dp[3] = min(dp[2], dp[3] + a[i]); } cout << dp[3]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T_container, typename T = typename enable_if< !is_same<T_container, string>::value, typename T_container::value_type>::type> ostream &operator<<(ostream &os, const T_container &v) { os << { ; string sep; for (const T &x : v) os << sep << x, sep = , ; return os << } ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } const int INF = 1 << 30; const int MOD = 1e9 + 7; const int MAXN = 2e5 + 5; string asignar(int n) { if (n == 0) return S ; if (n == 1) return M ; if (n == 2) return L ; if (n == 3) return XL ; if (n == 4) return XXL ; if (n == 5) return XXXL ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); vector<int> stock(6); for (long long i = (0); i < (long long)(6); i++) cin >> stock[i]; int n; cin >> n; vector<pair<pair<int, int>, int>> quiero(n); for (long long j = (0); j < (long long)(n); j++) { string s; cin >> s; string curr = ; pair<int, int> x = make_pair(-1, -1); for (long long i = (0); i < (long long)(s.size()); i++) { if (s[i] != , ) { curr += s[i]; } else { if (curr == S ) x.first = 0; if (curr == M ) x.first = 1; if (curr == L ) x.first = 2; if (curr == XL ) x.first = 3; if (curr == XXL ) x.first = 4; if (curr == XXXL ) x.first = 5; curr = ; } } if (curr == S ) x.second = 0; if (curr == M ) x.second = 1; if (curr == L ) x.second = 2; if (curr == XL ) x.second = 3; if (curr == XXL ) x.second = 4; if (curr == XXXL ) x.second = 5; if (x.first == -1) x.first = x.second; if (x.first > x.second) swap(x.first, x.second); quiero[j] = make_pair(x, j); } sort((quiero).begin(), (quiero).end()); ; vector<string> ans(n); for (long long i = (0); i < (long long)(n); i++) { if (stock[quiero[i].first.first] > 0) { ans[quiero[i].second] = asignar(quiero[i].first.first); stock[quiero[i].first.first]--; } else if (stock[quiero[i].first.second] > 0) { ans[quiero[i].second] = asignar(quiero[i].first.second); stock[quiero[i].first.second]--; } else { cout << NO n ; return 0; } } cout << YES n ; for (long long i = (0); i < (long long)(n); i++) cout << ans[i] << n ; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; multiset<int, greater<int>> m1, m2; int n, m; int main() { cin >> n >> m; for (int i = 0; i < n; ++i) { int a; cin >> a; m1.insert(a); } for (int i = 0; i < n; ++i) { int a; cin >> a; m2.insert(a); } vector<int> ans; for (; m1.size();) { auto a = m1.begin(); auto b = m2.begin(); auto bestfora = m2.lower_bound(m - 1 - *a); auto bestforb = m1.lower_bound(m - 1 - *b); if (bestfora == m2.end()) --bestfora; if (bestforb == m1.end()) --bestforb; if ((*a + *b) % m > (*a + *bestfora) % m && (*a + *b) % m > (*b + *bestforb) % m) { ans.push_back((*a + *b) % m); m1.erase(a); m2.erase(b); } else if ((*a + *bestfora) % m >= (*a + *b) % m && (*a + *bestfora) % m >= (*b + *bestforb) % m) { ans.push_back((*a + *bestfora) % m); m1.erase(a); m2.erase(bestfora); } else { ans.push_back((*b + *bestforb) % m); m1.erase(bestforb); m2.erase(b); } } sort(ans.begin(), ans.end(), greater<int>()); for (size_t i = 0; i < ans.size(); ++i) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dirx[] = {1, 0, -1, 0}; int diry[] = {0, 1, 0, -1}; int a; vector<int> graph[100005]; int dist[100005]; bool visit[100005]; int cnt = 0; bool flag = false; int dfs(int u, int par) { visit[u] = true; for (int i = 0; i < graph[u].size(); i++) { if (!visit[graph[u][i]]) dist[u] += dfs(graph[u][i], u); } if (dist[u] != 0 && (dist[u] + 1) % 2 == 0) { cnt++; dist[u] = 0; return 0; } else return 1; } int main() { scanf( %d , &a); int x, y; int start = 0; for (int i = 0; i < a - 1; i++) { scanf( %d %d , &x, &y); start = x; graph[x].push_back(y); graph[y].push_back(x); } if (a % 2 == 1) { cout << -1 << endl; return 0; } dfs(start, 0); cout << cnt - 1 << endl; }
|
module vga(
clk,
reset,
// Horizontal counter
h_counter_next,
// Horizontal sync
h_sync,
// Vertical counter
v_counter_next,
// Veritcal sync
v_sync,
// The next pixel will be displayed.
will_display
);
// Initialize parameters as 640 x 480 @ 60Hz
parameter HORIZONTAL_SYNC_POLARITY = 1'b0;
parameter TIME_HORIZONTAL_VIDEO = 640;
parameter TIME_HORIZONTAL_FRONT_PORCH = 16;
parameter TIME_HORIZONTAL_SYNC_PULSE = 96;
parameter TIME_HORIZONTAL_BACK_PORCH = 48;
parameter TIME_HORIZONTAL =
TIME_HORIZONTAL_VIDEO +
TIME_HORIZONTAL_FRONT_PORCH +
TIME_HORIZONTAL_SYNC_PULSE +
TIME_HORIZONTAL_BACK_PORCH;
parameter VERTICAL_SYNC_POLARITY = 1'b0;
parameter TIME_VERTICAL_VIDEO = 480;
parameter TIME_VERTICAL_FRONT_PORCH = 10;
parameter TIME_VERTICAL_SYNC_PULSE = 2;
parameter TIME_VERTICAL_BACK_PORCH = 33;
parameter TIME_VERTICAL =
TIME_VERTICAL_VIDEO +
TIME_VERTICAL_FRONT_PORCH +
TIME_VERTICAL_SYNC_PULSE +
TIME_VERTICAL_BACK_PORCH;
parameter HORIZONTAL_COUNTER_WIDTH = 10;
parameter VERTICAL_COUNTER_WIDTH = 10;
input clk, reset;
output reg [HORIZONTAL_COUNTER_WIDTH-1:0] h_counter_next;
output h_sync;
output reg [VERTICAL_COUNTER_WIDTH-1:0] v_counter_next;
output v_sync;
output will_display;
reg [HORIZONTAL_COUNTER_WIDTH-1:0] h_counter;
reg [VERTICAL_COUNTER_WIDTH-1:0] v_counter;
assign h_sync =
((h_counter >= (TIME_HORIZONTAL_VIDEO + TIME_HORIZONTAL_FRONT_PORCH)) &&
(h_counter < (TIME_HORIZONTAL_VIDEO + TIME_HORIZONTAL_FRONT_PORCH + TIME_HORIZONTAL_SYNC_PULSE))) ?
HORIZONTAL_SYNC_POLARITY : ~HORIZONTAL_SYNC_POLARITY;
assign v_sync =
((v_counter >= (TIME_VERTICAL_VIDEO + TIME_VERTICAL_FRONT_PORCH)) &&
(v_counter < (TIME_VERTICAL_VIDEO + TIME_VERTICAL_FRONT_PORCH + TIME_VERTICAL_SYNC_PULSE))) ?
VERTICAL_SYNC_POLARITY : ~VERTICAL_SYNC_POLARITY;
assign will_display = h_counter_next < TIME_HORIZONTAL_VIDEO && v_counter_next < TIME_VERTICAL_VIDEO;
always @* begin
if (reset) begin
h_counter_next = 0;
v_counter_next = 0;
end else begin
if (h_counter == TIME_HORIZONTAL - 1) begin
h_counter_next = 0;
if (v_counter == TIME_VERTICAL - 1)
v_counter_next = 0;
else
v_counter_next = v_counter + 1;
end else
h_counter_next = h_counter + 1;
end
end
always @(posedge clk) begin
h_counter <= h_counter_next;
v_counter <= v_counter_next;
end
endmodule
|
#include <bits/stdc++.h> const int MAXN = 3e5 + 10; const double eps = 1e-8; using namespace std; struct edge { int t, v; edge *next; } e[MAXN << 1], *h[MAXN], *o = e; void add(int x, int y, int vul) { o->t = y; o->v = vul; o->next = h[x]; h[x] = o++; } long long read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * f; } int n, m, q; int dirx[] = {-1, 1, 0, 0}; int diry[] = {0, 0, -1, 1}; int del[2000005], pos[2000006]; int a[305][305]; vector<pair<int, int> > q1[2000006], q2[2000005]; int f[MAXN]; int find1(int x) { if (x == f[x]) return x; else return f[x] = find1(f[x]); } void cal_add(int x) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) a[i][j] = 0, f[(i - 1) * m + j] = (i - 1) * m + j; for (int i = 0; i < q1[x].size(); i++) { int x1 = (q1[x][i].first - 1) / m + 1; int x2 = q1[x][i].first - (x1 - 1) * m; a[x1][x2] = 1; int num = 1; for (int j = 0; j < 4; j++) { int xx = x1 + dirx[j]; int yy = x2 + diry[j]; if (xx >= 1 && xx <= n && yy >= 1 && yy <= m && a[xx][yy] == 1) { int y = (xx - 1) * m + yy; int t1 = find1(q1[x][i].first); int t2 = find1(y); if (t1 == t2) continue; f[t1] = t2; num--; } } del[q1[x][i].second] += num; } } void cal_del(int x) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) a[i][j] = 0, f[(i - 1) * m + j] = (i - 1) * m + j; for (int i = 0; i < q2[x].size(); i++) { int x1 = (q2[x][i].first - 1) / m + 1; int x2 = q2[x][i].first - (x1 - 1) * m; a[x1][x2] = 1; int num = 1; for (int j = 0; j < 4; j++) { int xx = x1 + dirx[j]; int yy = x2 + diry[j]; if (xx >= 1 && xx <= n && yy >= 1 && yy <= m && a[xx][yy] == 1) { int y = (xx - 1) * m + yy; int t1 = find1(q2[x][i].first); int t2 = find1(y); if (t1 == t2) continue; f[t1] = t2; num--; } } del[q2[x][i].second] -= num; } } int main() { n = read(); m = read(); q = read(); int num = 0; int x, y, c; for (int i = 1; i <= q; i++) { x = read(); y = read(); c = read(); pos[i] = (x - 1) * m + y; num = c; if (a[x][y] == c) continue; q1[c].push_back(make_pair(pos[i], i)); q2[a[x][y]].push_back(make_pair(pos[i], i)); a[x][y] = c; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) q2[a[i][j]].push_back(make_pair((i - 1) * m + j, q + 1)); for (int i = 0; i <= num; i++) reverse(q2[i].begin(), q2[i].end()); for (int i = 0; i <= num; i++) cal_add(i); for (int i = 0; i <= num; i++) cal_del(i); int ans = 1; for (int i = 1; i <= q; i++) ans += del[i], printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int p, x, ans = 0; bool b; cin >> p; for (int i = 1; i < p; i++) { b = 1; x = 1; for (int j = 1; j < p - 1; j++) { x = (x * i) % p; if ((x - 1) % p == 0) b = 0; } if (((x * i) - 1) % p != 0) b = 0; if (b) ans++; } cout << ans << endl; return 0; }
|
module iir (clk, reset, start, din, params, dout, ready,iir_start,iir_done);
input clk, reset, start;
input [7:0] din;
input [15:0] params;
output [7:0] dout;
reg [7:0] dout;
output ready;
reg ready;
reg temp_ready;
reg [6:0] finite_counter;
wire count0;
input iir_start;
output iir_done;
wire iir_done;
reg del_count0;
reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
reg [7:0] uk, uk1, uk2 ;
reg [28:0] ysum ;
reg [26:0] yk ;
reg [22:0] utmp;
reg [3:0] wait_counter ;
// temporary variable
wire [31:0] yo1, yo2;
//wire [23:0] b0t, b1t, b2t;
wire [22:0] b0t, b1t, b2t;
wire [22:0] b0tpaj, b1tpaj, b2tpaj;
reg [3:0] obf_state, obf_next_state ;
reg [7:0] temp_uk, temp_uk1, temp_uk2 ;
reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2;
reg [28:0] temp_ysum ;
reg [26:0] temp_yk ;
reg [22:0] temp_utmp;
reg [7:0] temp_dout;
reg [3:0] temp_wait_counter ;
parameter
idle = 4'b0001 ,
load_a2 = 4'b0010 ,
load_b0 = 4'b0011 ,
load_b1 = 4'b0100 ,
load_b2 = 4'b0101 ,
wait4_start = 4'b0110 ,
latch_din = 4'b0111 ,
compute_a = 4'b1000 ,
compute_b = 4'b1001 ,
compute_yk = 4'b1010 ,
wait4_count = 4'b1011 ,
latch_dout = 4'b1100 ;
always @(obf_state or start or din or wait_counter or iir_start or count0)
begin
case (obf_state )
idle :
begin
if (iir_start)
obf_next_state = load_a2 ;
else
obf_next_state = idle;
temp_a1 = params ;
end
load_a2 :
begin
obf_next_state = load_b0 ;
temp_a2 = params ;
end
load_b0 :
begin
obf_next_state = load_b1 ;
temp_b0 = params ;
end
load_b1 :
begin
obf_next_state = load_b2 ;
temp_b1 = params ;
end
load_b2 :
begin
obf_next_state = wait4_start ;
temp_b2 = params ;
end
wait4_start :
begin
if (start)
begin
obf_next_state = latch_din ;
temp_uk = din ;
end
else
begin
obf_next_state = wait4_start ;
temp_uk = uk;
end
temp_ready = wait4_start;
end
latch_din :
begin
obf_next_state = compute_a ;
end
compute_a :
begin
obf_next_state = compute_b ;
temp_ysum = yo1[31:3] + yo2[31:3];
end
compute_b :
begin
obf_next_state = compute_yk ;
// temp_utmp = b0t[23:0] + b1t[23:0] + b2t[23:0];
temp_utmp = b0t + b1t + b2t;
end
compute_yk :
begin
obf_next_state = wait4_count ;
temp_uk1 = uk ;
temp_uk2 = uk1 ;
temp_yk = ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
temp_wait_counter = 4 ;
end
wait4_count :
begin
if (wait_counter==0 )
begin
obf_next_state = latch_dout ;
temp_dout = yk[26:19];
temp_yk1 = yk[26:11] ;
temp_yk2 = yk1 ;
end
else
begin
obf_next_state = wait4_count ;
temp_dout = dout;
temp_yk1 = yk1;
//temp_yk2 = yk2;
end
temp_wait_counter = wait_counter - 1;
end
latch_dout :
if (count0)
obf_next_state = idle;
else
obf_next_state = wait4_start ;
endcase
end
//assign yo1 = mul_tc_16_16(yk1, a1, clk);
assign yo1 = yk1 * a1;
//assign yo2 = mul_tc_16_16(yk2, a2, clk);
assign yo2 = yk2*a2;
//assign b0t = mul_tc_8_16(uk, b0, clk);
//assign b1t = mul_tc_8_16(uk1, b1, clk);
//assign b2t = mul_tc_8_16(uk2, b2, clk);
assign b0t = uk*b0;
assign b1t = uk1*b1;
assign b2t = uk2*b2;
// paj added to solve unused high order bit
assign b0tpaj = b0t;
assign b1tpaj = b1t;
assign b2tpaj = b2t;
// A COEFFICENTS
always @(posedge clk or posedge reset) begin
if (reset ) begin
uk <= 0 ;
uk1 <= 0 ;
uk2 <= 0 ;
yk1 <= 0 ;
yk2 <= 0 ;
yk <= 0 ;
ysum <= 0 ;
utmp <= 0 ;
a1 <= 0 ;
a2 <= 0 ;
b0 <= 0 ;
b1 <= 0 ;
b2 <= 0 ;
dout <= 0 ;
obf_state <= idle ;
ready <= 0;
end
else begin
obf_state <= obf_next_state ;
uk1 <= temp_uk1;
uk2 <= temp_uk2;
yk <= temp_yk;
uk <= temp_uk ;
a1 <= temp_a1 ;
a2 <= temp_a2 ;
b0 <= temp_b0 ;
b1 <= temp_b1 ;
b2 <= temp_b2 ;
ysum <= temp_ysum;
utmp <= temp_utmp;
dout <= temp_dout;
yk1 <= temp_yk1;
yk2 <= temp_yk2;
ready <= temp_ready;
end
end
// wait counter, count 4 clock after sum is calculated, to
// time outputs are ready, and filter is ready to accept next
// input
always @(posedge clk or posedge reset ) begin
if (reset )
wait_counter <= 0 ;
else begin
wait_counter <= temp_wait_counter ;
end
end
always @(posedge clk) begin
if (reset)
finite_counter<=100;
else
if (iir_start)
finite_counter<=finite_counter -1;
else
finite_counter<=finite_counter;
end
assign count0=finite_counter==7'b0;
always @(posedge clk) begin
del_count0 <= count0;
end
assign iir_done = (count0 && ~del_count0);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] a = crc[1 +: 2];
wire [1:0] b = crc[3 +: 2];
wire [1:0] c = crc[5 +: 2];
wire [1:0] d = crc[7 +: 2];
wire [1:0] e = crc[9 +: 2];
wire [1:0] f = crc[11+: 2];
wire [1:0] g = crc[13+: 2];
// left () [] :: .
// unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary)
// left **
// left * / %
// left + - (binary)
// left << >> <<< >>>
// left < <= > >= inside dist
// left == != === !== ==? !=?
// left & (binary)
// left ^ ~^ ^~ (binary)
// left | (binary)
// left &&
// left ||
// left ? :
// right ->
// none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <=
// {} {{}} concatenation
wire [1:0] bnz = (b==2'b0) ? 2'b11 : b;
wire [1:0] cnz = (c==2'b0) ? 2'b11 : c;
wire [1:0] dnz = (d==2'b0) ? 2'b11 : d;
wire [1:0] enz = (e==2'b0) ? 2'b11 : e;
// verilator lint_off WIDTH
// Do a few in each group
wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse
wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse
wire [1:0] o3 = a ** b ** c; // Some simulators botch this
wire [1:0] o4 = a * b / cnz % dnz * enz;
wire [1:0] o5 = a + b - c + d;
wire [1:0] o6 = a << b >> c <<< d >>> e <<< f;
wire [1:0] o7 = a < b <= c;
wire [1:0] o8 = a == b != c === d == e;
wire [1:0] o9 = a & b & c;
wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a;
wire [1:0] o11 = a | b | c;
wire [1:0] o12 = a && b && c;
wire [1:0] o13 = a || b || c;
wire [1:0] o14 = a ? b ? c : d : e;
wire [1:0] o15 = a ? b : c ? d : e;
// Now cross each pair of groups
wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this
wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this
wire [1:0] x3 = a + b * c + d;
wire [1:0] x4 = a + b << c + d;
wire [1:0] x5 = a == b << c == d;
wire [1:0] x6 = a & b << c & d;
wire [1:0] x7 = a ^ b & c ^ d;
wire [1:0] x8 = a | b ^ c | d;
wire [1:0] x9 = a && b | c && d;
wire [1:0] x10 = a || b && c || d;
wire [1:0] x11 = a ? b || c : d ? e : f;
// verilator lint_on WIDTH
function [1:0] pow (input [1:0] x, input [1:0] y);
casez ({x,y})
4'b00_??: pow = 2'b00;
4'b01_00: pow = 2'b01;
4'b01_01: pow = 2'b01;
4'b01_10: pow = 2'b01;
4'b01_11: pow = 2'b01;
4'b10_00: pow = 2'b01;
4'b10_01: pow = 2'b10;
4'b10_10: pow = 2'b00;
4'b10_11: pow = 2'b00;
4'b11_00: pow = 2'b01;
4'b11_01: pow = 2'b11;
4'b11_10: pow = 2'b01;
4'b11_11: pow = 2'b11;
endcase
endfunction
// Aggregate outputs into a single result vector
wire [63:0] result = {12'h0,
x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,
o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x ", $time, cyc, crc, result);
$write(" %b",o1);
$write(" %b",o2);
$write(" %b",o3);
$write(" %b",o4);
$write(" %b",o5);
$write(" %b",o6);
$write(" %b",o7);
$write(" %b",o8);
$write(" %b",o9);
$write(" %b",o10);
$write(" %b",o11);
$write(" %b",o12);
$write(" %b",o13);
$write(" %b",o14);
$write(" %b",o15);
// Now cross each pair of groups
$write(" %b",x1);
$write(" %b",x2);
$write(" %b",x3);
$write(" %b",x4);
$write(" %b",x5);
$write(" %b",x6);
$write(" %b",x7);
$write(" %b",x8);
$write(" %b",x9);
$write(" %b",x10);
$write(" %b",x11);
$write("\n");
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h2756ea365ec7520e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_SYMBOL_V
`define SKY130_FD_SC_HVL__PROBEC_P_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__probec_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
/**
* udp_dlatch$PSa_pp$PKG$sN: Positive level sensitive D-type -latch
* with active low
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SET_ASYNC;
reg SLEEP_B;
reg NOTIFIER_REG;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER_REG = 1'bX;
SET_ASYNC = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER_REG = 1'b0;
#80 SET_ASYNC = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER_REG = 1'b1;
#220 SET_ASYNC = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER_REG = 1'b0;
#360 SET_ASYNC = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 SET_ASYNC = 1'b1;
#520 NOTIFIER_REG = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 SET_ASYNC = 1'bx;
#660 NOTIFIER_REG = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$sN dut (.D(D), .SET_ASYNC(SET_ASYNC), .SLEEP_B(SLEEP_B), .NOTIFIER_REG(NOTIFIER_REG), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
|
#include <bits/stdc++.h> long long sum(long long val) { if (val % 2) return (val + 1) / 2 * val; return val / 2 * (val + 1); } int main() { long long n, x, d[200005], i, xx, l, ans = 0, now, tmp; scanf( %lld%lld , &n, &x); for (i = 0; i < n; i++) scanf( %lld , &d[i]); l = n - 1; xx = x; now = 0; for (i = n - 1; i >= 0; i--) { while (xx >= d[l]) { xx -= d[l]; now += sum(d[l]); l--; if (l < 0) l += n; } tmp = now - sum(d[l] - xx) + sum(d[l]); if (tmp > ans) ans = tmp; xx += d[i]; now -= sum(d[i]); } printf( %lld n , ans); return 0; }
|
// Copyright 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module spm(clk, rst, x, y, p);
parameter size = 32;
input clk, rst;
input y;
input[size-1:0] x;
output p;
wire[size-1:1] pp;
wire[size-1:0] xy;
genvar i;
CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
generate for(i=1; i<size-1; i=i+1) begin
CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
end endgenerate
TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));
endmodule
module TCMP(clk, rst, a, s);
input clk, rst;
input a;
output reg s;
reg z;
always @(posedge clk or posedge rst) begin
if (rst) begin
//Reset logic goes here.
s <= 1'b0;
z <= 1'b0;
end
else begin
//Sequential logic goes here.
z <= a | z;
s <= a ^ z;
end
end
endmodule
module CSADD(clk, rst, x, y, sum);
input clk, rst;
input x, y;
output reg sum;
reg sc;
// Half Adders logic
wire hsum1, hco1;
assign hsum1 = y ^ sc;
assign hco1 = y & sc;
wire hsum2, hco2;
assign hsum2 = x ^ hsum1;
assign hco2 = x & hsum1;
always @(posedge clk or posedge rst) begin
if (rst) begin
//Reset logic goes here.
sum <= 1'b0;
sc <= 1'b0;
end
else begin
//Sequential logic goes here.
sum <= hsum2;
sc <= hco1 ^ hco2;
end
end
endmodule
/*
module spm_tb;
//Inputs
reg clk;
reg rst;
reg [7: 0] x;
reg[7:0] Y;
reg[15:0] P;
//Outputs
wire p;
reg[3:0] cnt;
//Instantiation of Unit Under Test
spm #(8) uut (
.clk(clk),
.rst(rst),
.y(Y[0]),
.x(x),
.p(p)
);
always #5 clk = ~clk;
always @ (posedge clk)
if(rst) Y = -50;
else Y <= {1'b0,Y[7:1]};
always @ (posedge clk)
if(rst) P = 0;
else P <= {p, P[15:1]};
always @ (posedge clk)
if(rst) cnt = 0;
else cnt <= cnt + 1;
initial begin
//Inputs initialization
clk = 0;
rst = 0;
x = 50;
//Reset
#20 rst = 1;
#20 rst = 0;
#1000;
$finish;
end
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; vector<int> f[100005]; int n, m, temp, flag = 0; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> temp; f[temp].push_back(i + 1); } int j = 0, ans[100005]; for (int i = 0; i < m; i++) { cin >> temp; if (f[temp].size() == 0) { flag = 2; break; } else if (f[temp].size() > 1 && flag != 2) { flag = 1; } else if (flag == 0) { ans[j++] = f[temp][0]; } } if (flag == 0) { cout << Possible n ; for (int i = 0; i < m; i++) cout << ans[i] << ; cout << endl; } else if (flag == 1) { cout << Ambiguity n ; } else { cout << Impossible n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300005; int n, u, v, x, trie[maxn << 1][26], sz[maxn << 1], tot, cnt[maxn], res; char op[2]; int merge(int a, int b) { if (!a || !b) return a + b; int rt = ++tot; memset(trie[rt], 0, sizeof trie[rt]); sz[rt] = 1; for (int i = 0; i < 26; ++i) { trie[rt][i] = merge(trie[a][i], trie[b][i]); sz[rt] += sz[trie[rt][i]]; } return rt; } void dfs(int u, int dep) { sz[u] = 1; for (int i = 0; i < 26; ++i) if (trie[u][i]) { dfs(trie[u][i], dep + 1); sz[u] += sz[trie[u][i]]; } cnt[dep] += sz[u]; tot = n; int rt = 0; for (int i = 0; i < 26; ++i) rt = merge(rt, trie[u][i]); cnt[dep] -= max(1, sz[rt]); } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; ++i) { scanf( %d%d%s , &u, &v, op); trie[u][op[0] - a ] = v; } dfs(1, 0); res = 0; for (int i = 1; i < n; ++i) if (cnt[i] > cnt[res]) res = i; printf( %d n%d n , sz[1] - cnt[res], res + 1); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTP_PP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_PP_SYMBOL_V
|
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