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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__FAH_PP_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_PP_BLACKBOX_V
|
#include <bits/stdc++.h> int a, n; int main() { scanf( %d %d , &n, &a); int res = 0; if (a % 2 == 1) printf( %d n , a / 2 + a % 2); else printf( %d n , n / 2 - a / 2 + 1); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; unsigned seed = chrono::system_clock::now().time_since_epoch().count(); mt19937 eng(seed); long long random2() { return (1ll << 31ll) * eng() + eng(); } long long n, m, k, q, T; const long long big = 1000000007; const long long big2 = 1000000009; const long long mod = 998244353; const int MAXN = 300001; long long PATH[401][401] = {0}; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long a, b, c, d, e; cin >> k; for (int c1 = 0; c1 < (401); ++c1) { for (int c2 = 0; c2 < (401); ++c2) { if (c1 == 0 && c2 == 1) PATH[c1][c2] = 1; if (c2 == 0) PATH[c1][c2] = 1; } } for (int i = 1; i < (k); ++i) { for (long long r = 1; r < k + 1; r++) { for (int x = 0; x < (r + 2); ++x) { if (x < r) PATH[i][r] += (PATH[i - 1][x] * PATH[i - 1][r - 1 - x]) % big; if (x < r + 1) PATH[i][r] += (1 + 2 * r) * ((PATH[i - 1][x] * PATH[i - 1][r - x]) % big); PATH[i][r] %= big; PATH[i][r] += r * (r + 1) * ((PATH[i - 1][x] * PATH[i - 1][r - x + 1]) % big); PATH[i][r] %= big; } } } cout << PATH[k - 1][1] << n ; return 0; }
|
#include <bits/stdc++.h> template <class T> void read(T &a) { a = 0; char x = getchar(); bool f = 0; for (; x < 0 || x > 9 ; x = getchar()) f |= x == - ; for (; x >= 0 && x <= 9 ; x = getchar()) a = (a << 3) + (a << 1) + x - 0 ; if (f) a = -a; } template <class T, class... Args> void read(T &a, Args &...args) { read(a); read(args...); } using namespace std; const int N = 2e5 + 5; int n; int f[N], lim; pair<int, int> d[N]; bool cmp(pair<int, int> a, pair<int, int> b) { if (a.first ^ b.first) { return a.first < b.first; } return a.second > b.second; } int main() { read(n); for (int i = 1; i <= n; ++i) { read(d[i].first); d[i].second = i; } sort(d + 1, d + n + 1, cmp); int lim = 0; for (int i = 1; i <= n; ++i) { int c = d[i].second - d[i].first; if (c < 0) continue; if (lim == 0) { f[++lim] = c; continue; } if (c >= f[lim]) { f[++lim] = c; continue; } int l = 1, r = lim + 1; while (l < r - 1) { int mid = l + r >> 1; if (f[mid] <= c) { l = mid; } else { r = mid; } } if (f[l] > c) { f[l] = c; } else if (l != lim) { f[l + 1] = c; } } printf( %d n , lim); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e4; bitset<maxn * 25> f[50][25]; int n; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; vector<int> a(n * 2); for (int i = 1; i <= n * 2; i++) cin >> a[i - 1]; sort(a.begin(), a.end()); vector<vector<int>> ans(2); ans[0].push_back(a[0]), ans[1].push_back(a[1]); int sum = 0; for (int i = 2; i <= n * 2 - 1; i++) sum += a[i]; int lim = sum / 2; f[1][0].set(0); for (int i = 2; i <= n * 2 - 1; i++) for (int j = 0; j <= min(i, n - 1); j++) { f[i][j] |= f[i - 1][j]; if (j) f[i][j] |= f[i - 1][j - 1] << a[i]; } int s1 = -1, cnt = n - 1, id = 2 * n - 1; for (int i = lim; i >= 0; i--) { if (f[id][cnt][i]) { s1 = i; break; } } assert(s1 >= 0); for (int i = id; i >= 2; i--) { assert(f[i][cnt][s1]); if (cnt >= 1 && s1 >= a[i] && f[i - 1][cnt - 1][s1 - a[i]]) { ans[0].push_back(a[i]); s1 -= a[i], cnt--; } else ans[1].push_back(a[i]); } sort(ans[0].begin(), ans[0].end()); sort(ans[1].begin(), ans[1].end(), greater<int>()); for (int i = 0; i <= 1; i++) { for (auto x : ans[i]) cout << x << ; cout << n ; } }
|
// vim: ts=4 sw=4 noexpandtab
/*
* SPI bus slave
*
* Copyright (c) 2019 Michael Buesch <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`ifndef SPI_SLAVE_MOD_V_
`define SPI_SLAVE_MOD_V_
`include "sync_signal_mod.v"
module spi_slave #(
parameter WORDSIZE = 8, /* Size of SPI word. Can be anything from 1 to 32. */
parameter CPOL = 0, /* SPI clock polarity. Can be 0 or 1. */
parameter CPHA = 0, /* SPI clock phase. Can be 0 or 1. */
parameter MSB_FIRST = 1, /* MSB transmit first enable. Can be 0 or 1. */
) (
input clk, /* clock */
input mosi, /* SPI bus MOSI signal */
output miso, /* SPI bus MISO signal */
input sck, /* SPI bus clock signal */
input ss, /* SPI bus slave select signal */
output rx_irq, /* Receive interrupt */
output [WORDSIZE - 1 : 0] rx_data, /* Received data */
input [WORDSIZE - 1 : 0] tx_data, /* Transmit data */
);
/* Synchronized input signals. */
wire mosi_s;
wire sck_rising_s;
wire sck_falling_s;
wire ss_s;
sync_signal sync_mosi(.clk(clk), .in(mosi), .out(mosi_s));
sync_signal sync_sck(.clk(clk), .in(sck), .rising(sck_rising_s), .falling(sck_falling_s));
sync_signal sync_ss(.clk(clk), .in(ss), .out(ss_s));
/* SCK sample and setup edges. */
wire sck_sample_edge;
wire sck_setup_edge;
assign sck_sample_edge = (CPOL ^ CPHA) ? sck_falling_s : sck_rising_s;
assign sck_setup_edge = (CPOL ^ CPHA) ? sck_rising_s : sck_falling_s;
/* Output buffers. */
reg miso_r;
reg rx_irq_r;
reg [WORDSIZE - 1 : 0] rx_data_r;
assign miso = miso_r;
assign rx_irq = rx_irq_r;
assign rx_data = rx_data_r;
/* Receive and transmit shift registers. */
reg [WORDSIZE - 1 : 0] rx_shiftreg;
reg [WORDSIZE - 1 : 0] tx_shiftreg;
reg [5:0] bit_count;
initial begin
bit_count <= 0;
rx_shiftreg <= 0;
tx_shiftreg <= 0;
miso_r <= 0;
rx_irq_r <= 0;
rx_data_r <= 0;
end
always @(posedge clk) begin
/* Check if slave select is not active */
if (ss_s) begin
bit_count <= 0;
rx_shiftreg <= 0;
tx_shiftreg <= 0;
miso_r <= 0;
rx_irq_r <= 0;
/* Check if slave select is active */
end else begin
/* Check if we are at the start of a word. */
if (bit_count == 0) begin
if (CPHA) begin
/* Reload the TX shift register. */
tx_shiftreg <= tx_data;
miso_r <= 0;
end else begin
/* Reload the TX shift register and
* put the first bit onto the bus. */
if (MSB_FIRST) begin
tx_shiftreg <= tx_data << 1;
miso_r <= tx_data[WORDSIZE - 1];
end else begin
tx_shiftreg <= tx_data >> 1;
miso_r <= tx_data[0];
end
end
/* Check if we are at a setup edge of SCK. */
end else if (sck_setup_edge) begin
/* Put the next bit onto the bus. */
if (MSB_FIRST) begin
miso_r <= tx_shiftreg[WORDSIZE - 1];
tx_shiftreg <= tx_shiftreg << 1;
end else begin
miso_r <= tx_shiftreg[0];
tx_shiftreg <= tx_shiftreg >> 1;
end
end
/* Check if we are at a sample edge of SCK. */
if (sck_sample_edge && (bit_count < WORDSIZE)) begin
/* Get the next bit from the bus. */
if (MSB_FIRST) begin
rx_shiftreg <= rx_shiftreg << 1;
rx_shiftreg[0] <= mosi_s;
end else begin
rx_shiftreg <= rx_shiftreg >> 1;
rx_shiftreg[WORDSIZE - 1] <= mosi_s;
end
bit_count <= bit_count + 1;
end
/* If we received a full word, trigger the RX interrupt. */
if (bit_count >= WORDSIZE) begin
bit_count <= 0;
rx_data_r <= rx_shiftreg;
rx_irq_r <= 1;
end else begin
rx_irq_r <= 0;
end
end
end
endmodule
`endif /* SPI_SLAVE_MOD_V_ */
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; struct edge { long long a, b, cost; edge(long long x, long long y, long long z) : a(x), b(y), cost(z){}; }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, k, p; cin >> n >> k >> p; vector<long long> v(n), a(k); for (long long i = 0; i < (long long)(n); i++) cin >> v[i]; for (long long i = 0; i < (long long)(k); i++) cin >> a[i]; sort((v).begin(), (v).end()); sort((a).begin(), (a).end()); long long ans = INT_MAX; for (long long i = (long long)(0); i <= (long long)(k - n); i++) { long long res = INT_MIN; for (long long j = (long long)(0); j <= (long long)(n - 1); j++) { res = max(res, abs(v[j] - a[i + j]) + abs(a[i + j] - p)); } ans = min(ans, res); } cout << ans << endl; return 0; }
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
(** * Maps: Total and Partial Maps *)
(** Maps (or dictionaries) are ubiquitous data structures both
generally and in the theory of programming languages in
particular; we're going to need them in many places in the coming
chapters. They also make a nice case study using ideas we've seen
in previous chapters, including building data structures out of
higher-order functions (from [Basics] and [Poly]) and the use of
reflection to streamline proofs (from [IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * The Coq Standard Library *)
(** One small digression before we get to maps.
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Strings.String.
Require Import Coq.Logic.FunctionalExtensionality.
(** Documentation for the standard library can be found at
http://coq.inria.fr/library/.
The [Search] command is a good way to look for theorems involving
objects of specific types. Take a minute now to experiment with it. *)
(* ################################################################# *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. For this purpose, we again use the type [id] from the
[Lists] chapter. To make this chapter self contained, we repeat
its definition here, together with the equality comparison
function for [id]s and its fundamental property. *)
Inductive id : Type :=
| Id : string -> id.
Definition beq_id x y :=
match x,y with
| Id n1, Id n2 => if string_dec n1 n2 then true else false
end.
(** (The function [string_dec] comes from Coq's string library.
If you check its result type, you'll see that it does not actually
return a [bool], but rather a type that looks like [{x = y} + {x
<> y}], called a [sumbool], which can be thought of as an
"evidence-carrying boolean." Formally, an element of [sumbool] is
either a proof that two things are equal or a proof that they are
unequal, together with a tag indicating which. But for present
purposes you can think of it as just a fancy [bool].) *)
Theorem beq_id_refl : forall id, true = beq_id id id.
Proof.
intros [n]. simpl. destruct (string_dec n n).
- reflexivity.
- destruct n0. reflexivity.
Qed.
(** The following useful property of [beq_id] follows from an
analogous lemma about strings: *)
Theorem beq_id_true_iff : forall x y : id,
beq_id x y = true <-> x = y.
Proof.
intros [n1] [n2].
unfold beq_id.
destruct (string_dec n1 n2).
- subst. split. reflexivity. reflexivity.
- split.
+ intros contra. inversion contra.
+ intros H. inversion H. subst. destruct n. reflexivity.
Qed.
(** Similarly: *)
Theorem beq_id_false_iff : forall x y : id,
beq_id x y = false
<-> x <> y.
Proof.
intros x y. rewrite <- beq_id_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This useful variant follows just by rewriting: *)
Theorem false_beq_id : forall x y : id,
x <> y
-> beq_id x y = false.
Proof.
intros x y. rewrite beq_id_false_iff.
intros H. apply H. Qed.
(* ################################################################# *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about its behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the very same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps.
We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A:Type) := id -> A.
(** Intuitively, a total map over an element type [A] is just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A:Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A:Type} (m : total_map A)
(x : id) (v : A) :=
fun x' => if beq_id x x' then v else m x'.
(** This definition is a nice example of higher-order programming:
[t_update] takes a _function_ [m] and yields a new function
[fun x' => ...] that behaves like the desired map.
For example, we can build a map taking [id]s to [bool]s, where [Id
3] is mapped to [true] and every other key is mapped to [false],
like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) (Id "foo") false)
(Id "bar") true.
(** This completes the definition of total maps. Note that we don't
need to define a [find] operation because it is just function
application! *)
Example update_example1 : examplemap (Id "baz") = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap (Id "foo") = false.
Proof. reflexivity. Qed.
Example update_example3 : examplemap (Id "quux") = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap (Id "bar") = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. Even if you don't work the following
exercises, make sure you thoroughly understand the statements of
the lemmas! (Some of the proofs require the functional
extensionality axiom, which is discussed in the [Logic]
chapter.) *)
(** **** Exercise: 1 star, optional (t_apply_empty) *)
(** First, the empty map returns its default element for all keys: *)
Lemma t_apply_empty: forall A x v, @t_empty A v x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_eq) *)
(** Next, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m: total_map A) x v,
(t_update m x v) x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_neq) *)
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X:Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_shadow) *)
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on [id]s with the boolean function [beq_id]. *)
(** **** Exercise: 2 stars, optional (beq_idP) *)
(** Use the proof of [beq_natP] in chapter [IndProp] as a template to
prove the following: *)
Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP
x1 x2)] to simultaneously perform case analysis on the result of
[beq_id x1 x2] and generate hypotheses about the equality (in the
sense of [=]) of [x1] and [x2]. *)
(** **** Exercise: 2 stars (t_update_same) *)
(** With the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (t_update_permute) *)
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A:Type) := total_map (option A).
Definition empty {A:Type} : partial_map A :=
t_empty None.
Definition update {A:Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** We now straightforwardly lift all of the basic lemmas about total
maps to partial maps. *)
Lemma apply_empty : forall A x, @empty A x = None.
Proof.
intros. unfold empty. rewrite t_apply_empty.
reflexivity.
Qed.
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
(** $Date: 2017-03-05 16:25:50 -0500 (Sun, 05 Mar 2017) $ *)
|
#include <bits/stdc++.h> using std::abs; using std::bitset; using std::cerr; using std::cin; using std::cout; using std::deque; using std::map; using std::max; using std::min; using std::pair; using std::queue; using std::set; using std::sort; using std::string; using std::swap; using std::unordered_map; using std::unordered_set; using std::vector; void init() { std::iostream::sync_with_stdio(0); cout << std::fixed; cout.precision(10); cerr << std::fixed; cerr.precision(10); srand(time(0)); } const int MAXN = 1e6 + 1; long long arr[MAXN]; long long dp[MAXN][3]; int n; long long a, b; const long long INF = 1e18; vector<int> fact(int x) { vector<int> res; int k = x; for (int i = 2; i * i <= k; ++i) if (!(x % i)) { x /= i; res.push_back(i); } if (x > 1) res.push_back(x); return res; } long long solve(int p) { for (int i = 0; i <= n; ++i) for (int j = 0; j < 3; ++j) dp[i][j] = INF; for (int i = 0; i < 3; ++i) dp[0][i] = 0; for (int i = 1; i <= n; ++i) { dp[i][1] = min(dp[i - 1][0], dp[i - 1][1]) + a; if (arr[i] % p == 0) { dp[i][0] = dp[i - 1][0]; dp[i][2] = min(dp[i - 1][2], dp[i - 1][1]); } else if ((arr[i] + 1) % p == 0 || (arr[i] - 1) % p == 0) { dp[i][0] = dp[i - 1][0] + b; dp[i][2] = min(dp[i - 1][2], dp[i - 1][1]) + b; } } long long ans = INF; for (int i = 0; i < 3; ++i) ans = min(ans, dp[n][i]); return ans; } int main() { init(); cin >> n >> a >> b; for (int i = 1; i <= n; ++i) cin >> arr[i]; set<int> ma; for (int i = -1; i <= 1; ++i) { vector<int> tmp; tmp = fact(arr[1] + i); for (auto j : tmp) ma.insert(j); tmp = fact(arr[n] + i); for (auto j : tmp) ma.insert(j); } long long ans = INF; for (auto i : ma) ans = min(ans, solve(i)); cout << ans << n ; return 0; }
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This module tests the basic behavior of a tri0 register. We use a ?:
* to turn on/off the driver to the tri0 net and watch its value.
* A tri0 net should pull to 0 when undriven, and follow the driver
* otherwise.
*/
module main;
reg enable, val;
tri0 t0 = (~enable) ? 1'bz : val;
initial begin
enable = 0;
val = 0;
#1 if (t0 !== 1'b0) begin
$display("FAILED -- undriven t0 == %b", t0);
$finish;
end
enable = 1;
#1 if (t0 !== 1'b0) begin
$display("FAILED -- driven-0 t0 == %b", t0);
$finish;
end
val = 1;
#1 if (t0 !== 1'b1) begin
$display("FAILED -- driven-1 t0 == %b", t0);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; cout << min(a + a + b + b, min(a + b + c, min(a + a + c + c, b + b + c + c))) << endl; return 0; }
|
#include <bits/stdc++.h> int gcd(int x, int y) { if (y == 0) return x; else return gcd(y, x % y); } int main() { int n, a; scanf( %d , &n); for (int i = 1; i <= n / 2; i++) { if (gcd(i, n - i) == 1) a = i; } printf( %d %d , a, n - a); }
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) #pragma GCC optimize( -fgcse ) #pragma GCC optimize( -fgcse-lm ) #pragma GCC optimize( -fipa-sra ) #pragma GCC optimize( -ftree-pre ) #pragma GCC optimize( -ftree-vrp ) #pragma GCC optimize( -fpeephole2 ) #pragma GCC optimize( -ffast-math ) #pragma GCC optimize( -fsched-spec ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -falign-jumps ) #pragma GCC optimize( -falign-loops ) #pragma GCC optimize( -falign-labels ) #pragma GCC optimize( -fdevirtualize ) #pragma GCC optimize( -fcaller-saves ) #pragma GCC optimize( -fcrossjumping ) #pragma GCC optimize( -fthread-jumps ) #pragma GCC optimize( -funroll-loops ) #pragma GCC optimize( -fwhole-program ) #pragma GCC optimize( -freorder-blocks ) #pragma GCC optimize( -fschedule-insns ) #pragma GCC optimize( inline-functions ) #pragma GCC optimize( -ftree-tail-merge ) #pragma GCC optimize( -fschedule-insns2 ) #pragma GCC optimize( -fstrict-aliasing ) #pragma GCC optimize( -fstrict-overflow ) #pragma GCC optimize( -falign-functions ) #pragma GCC optimize( -fcse-skip-blocks ) #pragma GCC optimize( -fcse-follow-jumps ) #pragma GCC optimize( -fsched-interblock ) #pragma GCC optimize( -fpartial-inlining ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( -freorder-functions ) #pragma GCC optimize( -findirect-inlining ) #pragma GCC optimize( -frerun-cse-after-loop ) #pragma GCC optimize( inline-small-functions ) #pragma GCC optimize( -finline-small-functions ) #pragma GCC optimize( -ftree-switch-conversion ) #pragma GCC optimize( -foptimize-sibling-calls ) #pragma GCC optimize( -fexpensive-optimizations ) #pragma GCC optimize( -funsafe-loop-optimizations ) #pragma GCC optimize( inline-functions-called-once ) #pragma GCC optimize( -fdelete-null-pointer-checks ) using namespace std; inline long long read() { long long x = 0, y = 0, c = getchar(); while (!isdigit(c)) y = c, c = getchar(); while (isdigit(c)) x = (x << 1) + (x << 3) + (c ^ 0 ), c = getchar(); return y == - ? -x : x; } inline void print(long long q) { if (q < 0) putchar( - ), q = -q; if (q >= 10) print(q / 10); putchar(q % 10 + 0 ); } long long s1 = 19260817, s2 = 23333333, s3 = 998244353, srd; inline long long rd() { return srd = (srd * s1 + s2 + rand()) % s3; } void file() { freopen( lis.in , r , stdin); freopen( lis.out , w , stdout); } int n, m; set<int> s; int t[2][800010]; void ins(int op, int q, int l, int r, int ax, int x) { if (l == r) { t[op][q] = x; return; } int mid = l + r >> 1; if (mid >= ax) ins(op, q << 1, l, mid, ax, x); else ins(op, q << 1 | 1, mid + 1, r, ax, x); t[op][q] = max(t[op][q << 1], t[op][q << 1 | 1]); } int qy(int op, int q, int l, int r, int al, int ar) { if (l >= al && r <= ar) return t[op][q]; int mid = l + r >> 1; int as = 0; if (mid >= al) as = qy(op, q << 1, l, mid, al, ar); if (mid < ar) as = max(as, qy(op, q << 1 | 1, mid + 1, r, al, ar)); return as; } int gx(int op, int q) { int tmp = qy(op, 1, 0, (!op ? n : m + 10), 0, q - 1) + 1; ins(op, 1, 0, (!op ? n : m + 10), q, tmp); return tmp; } int gd[200010], wz[200010]; int main() { srand(time(0)); rd(); int i, j, op, x, y; n = read(); m = read(); for (i = 1; i <= m; ++i) { op = read(); x = read(); if (op == 1) { y = read(); x = n - x + 1; y = i - y + 10; gd[x] = y; wz[y] = x; s.insert(x); for (j = y + 1; j <= y + 9; ++j) if (wz[j]) ins(0, 1, 0, n, wz[j], 0); for (j = y; j <= y + 9; ++j) if (wz[j]) { int nxt = gx(0, wz[j]); ins(1, 1, 0, m + 10, j, nxt); } } else { set<int>::iterator it = s.end(), tp; while (x--) { --it; ins(1, 1, 0, m + 10, gd[*it], 0); } tp = it; ins(0, 1, 0, n, *it, 0); wz[gd[*it]] = 0; gd[*it] = 0; for (++it; it != s.end(); ++it) { int nxt = gx(1, gd[*it]); ins(0, 1, 0, n, *it, nxt); } s.erase(tp); } print(t[0][1]); putchar( n ); } return 0; }
|
/*###########################################################################
# Function: Dual port memory wrapper (one read/ one write port)
# To run without hardware platform dependancy, `define:
# "TARGET_CLEAN"
############################################################################
*/
module memory_dp(/*AUTOARG*/
// Outputs
rd_data,
// Inputs
wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_en, rd_addr
);
parameter AW = 14;
parameter DW = 32;
parameter WED = DW/8; //one per byte
parameter MD = 1<<AW;//memory depth
//write-port
input wr_clk; //write clock
input [WED-1:0] wr_en; //write enable vector
input [AW-1:0] wr_addr;//write address
input [DW-1:0] wr_data;//write data
//read-port
input rd_clk; //read clock
input rd_en; //read enable
input [AW-1:0] rd_addr;//read address
output[DW-1:0] rd_data;//read output data
//////////////////////
//SIMPLE MEMORY MODEL
//////////////////////
`ifdef TARGET_CLEAN
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
//read port
always @ (posedge rd_clk)
if(rd_en)
rd_data[DW-1:0] <= ram[rd_addr[AW-1:0]];
//write port
generate
genvar i;
for (i = 0; i < WED; i = i+1) begin: gen_ram
always @(posedge wr_clk)
begin
if (wr_en[i])
ram[wr_addr[AW-1:0]][(i+1)*8-1:i*8] <= wr_data[(i+1)*8-1:i*8];
end
end
endgenerate
`elsif TARGET_XILINX
//instantiate XILINX BRAM (based on parameter size)
`elsif TARGET_ALTERA
`endif
endmodule // memory_dp
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_rx_core
#(
parameter ABUSWIDTH = 16,
parameter [1:0] ADC_ID = 0,
parameter [0:0] HEADER_ID = 0
)
(
input wire ADC_ENC,
input wire [13:0] ADC_IN,
input wire ADC_SYNC,
input wire ADC_TRIGGER,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
output wire LOST_ERROR
);
localparam VERSION = 1;
// 0 - soft reset
// 1 - start/status
//TODO:
// - external trigger /rising falling
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs [15:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000; // CONF_START_WITH_SYNC = TRUE
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 0;
status_regs[6] <= 1;
status_regs[7] <= 0;
status_regs[8] <= 0;
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
wire START;
assign START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_WITH_SYNC;
assign CONF_START_WITH_SYNC = status_regs[2][0];
wire CONF_EN_EX_TRIGGER;
assign CONF_EN_EX_TRIGGER = status_regs[2][1];
wire CONF_SINGLE_DATA;
assign CONF_SINGLE_DATA = status_regs[2][2];
wire [23:0] CONF_DATA_CNT;
assign CONF_DATA_CNT = {status_regs[5], status_regs[4], status_regs[3]};
wire [7:0] CONF_SAMPLE_SKIP = status_regs[6];
wire [7:0] CONF_SAMPEL_DLY = status_regs[7];
reg [7:0] CONF_ERROR_LOST;
assign LOST_ERROR = CONF_ERROR_LOST != 0;
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_ERROR_LOST;
else if(BUS_ADD < 16)
BUS_DATA_OUT <= BUS_STATUS_OUT;
end
end
wire rst_adc_sync;
cdc_reset_sync isync_rst (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(ADC_ENC), .pulse_out(rst_adc_sync));
wire start_adc_sync;
cdc_pulse_sync istart_rst (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(ADC_ENC), .pulse_out(start_adc_sync));
wire adc_sync_pulse;
pulse_gen_rising pulse_adc_sync (.clk_in(ADC_ENC), .in(ADC_SYNC), .out(adc_sync_pulse));
//long reset is needed
reg [7:0] sync_cnt;
always@(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
/*
reg [7:0] align_cnt;
always@(posedge ADC_ENC) begin
if(adc_sync_pulse)
align_cnt <= 0;
else if(align_cnt == (CONF_SAMPLE_SKIP - 1))
align_cnt <= 0;
else
align_cnt <= align_cnt + 1;
end
*/
reg adc_sync_wait;
always@(posedge ADC_ENC) begin
if(rst_adc_sync)
adc_sync_wait <= 0;
else if(start_adc_sync)
adc_sync_wait <= 1;
else if (adc_sync_pulse)
adc_sync_wait <= 0;
end
wire start_data_count;
assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER);
reg [23:0] rec_cnt;
always@(posedge ADC_ENC) begin
if(rst_adc_sync)
rec_cnt <= 0;
else if(start_data_count && (rec_cnt > CONF_DATA_CNT || rec_cnt == 0))
rec_cnt <= 1;
else if(rec_cnt != -1 && rec_cnt>0 && CONF_DATA_CNT!=0 )
rec_cnt <= rec_cnt + 1;
end
wire DONE;
assign DONE = rec_cnt > CONF_DATA_CNT;
reg cdc_fifo_write_single;
always@(*) begin
if(CONF_DATA_CNT==0 && rec_cnt>=1) //forever
cdc_fifo_write_single = 1;
else if(rec_cnt>=1 && rec_cnt <= CONF_DATA_CNT) //to CONF_DATA_CNT
cdc_fifo_write_single = 1;
else
cdc_fifo_write_single = 0;
end
reg [13:0] prev_data;
reg prev_sync;
reg prev_ready;
always@(posedge ADC_ENC) begin
if(rst_adc_sync || start_adc_sync)
prev_ready <= 0;
else
prev_ready <= !prev_ready;
end
//
reg [13:0] ADC_IN_DLY, adc_dly_mem;
reg [13:0] dly_mem [255:0];
reg [7:0] dly_addr_read, dly_addr_write;
always@(posedge ADC_ENC)
if(rst_adc_sync)
dly_addr_write <= 0;
else
dly_addr_write <= dly_addr_write + 1;
always@(posedge ADC_ENC)
dly_mem[dly_addr_write] <= ADC_IN;
always@(posedge ADC_ENC)
adc_dly_mem <= dly_mem[dly_addr_read];
always@(*) begin
dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY;
ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem;
end
//
always@(posedge ADC_ENC) begin
prev_data <= ADC_IN_DLY;
prev_sync <= ADC_SYNC;
end
wire fifo_full, cdc_fifo_empty, cdc_fifo_write_double;
assign cdc_fifo_write_double = cdc_fifo_write_single && prev_ready; //write every second
wire wfull;
reg cdc_fifo_write;
always@(posedge ADC_ENC) begin
if(rst_adc_sync)
CONF_ERROR_LOST <= 0;
else if (CONF_ERROR_LOST!=8'hff && wfull && cdc_fifo_write)
CONF_ERROR_LOST <= CONF_ERROR_LOST +1;
end
reg [31:0] data_to_fifo;
always@(*) begin
if(CONF_SINGLE_DATA)
data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};
else
data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY};
if(CONF_SINGLE_DATA)
cdc_fifo_write = cdc_fifo_write_single;
else
cdc_fifo_write = cdc_fifo_write_double;
end
wire [31:0] cdc_data_out;
cdc_syncfifo #(.DSIZE(32), .ASIZE(3)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(data_to_fifo), //.wdata({ADC_SYNC,2'd0,ADC_SYNC,14'd0,adc_des}),
.winc(cdc_fifo_write), .wclk(ADC_ENC), .wrst(RST_LONG),
.rinc(!fifo_full), .rclk(BUS_CLK), .rrst(RST_LONG)
);
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]), .size());
//assign FIFO_DATA[31:30] = 0;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(ADC_ENC), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_printf_buffer_address_generator
(
// Standard global signals
input clock,
input resetn,
input enable,
// Upstream interface
output o_stall,
input i_valid,
input i_predicate,
input [31:0] i_globalid0,
input [31:0] i_increment,
// Downstream interface
input i_stall,
output reg o_valid,
output reg [31:0] o_result,
// Avalon interface
output avm_read,
output avm_write,
output [5:0] avm_burstcount,
output [31:0] avm_address,
output [255:0] avm_writedata,
output [31:0] avm_byteenable,
input avm_waitrequest,
input [255:0] avm_readdata,
input avm_readdatavalid,
input avm_writeack
);
reg busy; // sent a request, waiting for response
wire predicated_read;
wire down_stall;
// stalled from down-stream when output is valid and stall is high
assign down_stall = ( o_valid & i_stall );
/**************
* AVM Signals *
**************/
// send a interconnect request if not stalled down-stream, not busy, nor predicated
assign avm_read = ( i_valid & ~down_stall & ~busy & ~i_predicate);
assign avm_address = i_increment;
assign avm_write = 1'b0;
assign avm_writedata = 256'b0;
assign avm_byteenable = 32'b1;
assign avm_burstcount = 1;
/****************
* Other signals *
****************/
// act on predicated inputs (o_valid is high next cycle, result does not matter)
// if not stalled down-stream, not busy and predicate is high
assign predicated_read = ( i_valid & ~down_stall & ~busy & i_predicate );
/*******************
* Valid/Stall Logic *
********************/
always @( posedge clock or negedge resetn ) begin
if( ~resetn ) begin
o_valid <= 1'b0;
busy <= 1'b0;
o_result <= 32'dx;
end
else begin
// busy when read signal is sent, not-busy after readdatavalid is received
busy <= (busy & ~avm_readdatavalid) | (~busy & avm_read & ~avm_waitrequest);
// dont change the output, if I get stalled by down-stream
if( ~down_stall )
begin
// readdatavalid stays high only one cycle
o_valid <= avm_readdatavalid | predicated_read;
if( predicated_read ) begin
o_result <= 32'b0; // assign 0 so I can see change when debugging
end
else begin
o_result <= avm_readdata[31:0];
end
end
end
end
// stall up-stream if I get stalled by down-stream, or by the IC, or just busy servicing a request
assign o_stall = ( down_stall | ( avm_read & avm_waitrequest ) | busy );
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(3, Ofast , inline ) using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); const long long maxn = (long long)1e6 + 5; const long long mod = 998244353; const long long inf = 0x3f3f3f3f; long long T = 1; vector<long long> v[maxn], vec[maxn]; long long dep[maxn], pre[maxn]; long long maxx; void dfs(long long now) { maxx = max(maxx, dep[now]); vec[dep[now]].push_back(now); for (auto &to : v[now]) { if (dep[to]) continue; pre[to] = now; dep[to] = dep[now] + 1; dfs(to); } } void solve() { long long n, m; cin >> n >> m; maxx = 1; for (long long i = 1; i <= n; ++i) v[i].clear(), vec[i].clear(), dep[i] = 0; for (long long i = 1; i <= m; ++i) { long long x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } dep[1] = 1; dfs(1); if (maxx > (n + 1) / 2) { cout << PATH n ; stack<long long> s; long long now = vec[maxx][0]; while (now) { s.push(now); now = pre[now]; } cout << s.size() << n ; while (!s.empty()) { cout << s.top() << ; s.pop(); } cout << n ; return; } cout << PAIRING n ; long long ans = 0; for (long long i = 1; i <= maxx; ++i) { ans += vec[i].size() / 2; } cout << ans << n ; for (long long i = 1; i <= maxx; ++i) { for (long long j = 0; j + 1 < vec[i].size(); j += 2) { cout << vec[i][j] << << vec[i][j + 1] << n ; } } } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> T; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); long long n, R = 0, L = 0; cin >> n; long long l[n], r[n]; for (int x = 0; x < n; x++) { cin >> l[x] >> r[x]; L += l[x]; R += r[x]; } int val = abs(R - L); int ans = 0; for (int x = 0; x < n; x++) { int tL = L - (l[x] - r[x]); int tR = R - (r[x] - l[x]); int i = abs(tL - tR); if (i > val) { ans = x + 1; val = i; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, h, m, data[55]; int main() { cin >> n >> h >> m; for (int i = 1; i <= n; i++) { data[i] = h; } for (int i = 1; i <= m; i++) { long long l, r, x; cin >> l >> r >> x; for (int j = l; j <= r; j++) { data[j] = min(data[j], x); } } long long ans = 0; for (int i = 1; i <= n; i++) ans += data[i] * data[i]; cout << ans << endl; return 0; }
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
switches control module
2.23.2010
*/
/*
There are 4 switches on the Spartan3E board, and they are addressable as the last nibble of the returned word
*/
module mod_switches(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout, switches);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
input [7:0] switches;
/* by spec, the iout and dout signals must go hiZ when we're not using them */
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
assign idata = 32'h00000000;
assign ddata = {24'h000000,switches};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_SYMBOL_V
`define SKY130_FD_SC_MS__O21BA_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx, Inc
// Engineer: Parimal Patel
// Create Date: 04/17/2017 12:44:43 PM
// Modified Date: 08/19/2017 to support PYNQ-Z2 board's Raspberry Pi and
// and Arduino interfaces
// Module Name: input_mux
//////////////////////////////////////////////////////////////////////////////////
module input_mux # (parameter C_BOOLEAN_GENERATOR_NUM = 24) (
input [4:0] sel,
input [C_BOOLEAN_GENERATOR_NUM-1:0] in_pin,
output reg out_int
);
always @(sel, in_pin)
case(sel)
5'h00 : out_int = in_pin[0];
5'h01 : out_int = in_pin[1];
5'h02 : out_int = in_pin[2];
5'h03 : out_int = in_pin[3];
5'h04 : out_int = in_pin[4];
5'h05 : out_int = in_pin[5];
5'h06 : out_int = in_pin[6];
5'h07 : out_int = in_pin[7];
5'h08 : out_int = in_pin[8];
5'h09 : out_int = in_pin[9];
5'h0A : out_int = in_pin[10];
5'h0B : out_int = in_pin[11];
5'h0C : out_int = in_pin[12];
5'h0D : out_int = in_pin[13];
5'h0E : out_int = in_pin[14];
5'h0F : out_int = in_pin[15];
5'h10 : out_int = in_pin[16];
5'h11 : out_int = in_pin[17];
5'h12 : out_int = in_pin[18];
5'h13 : out_int = in_pin[19];
5'h14 : out_int = in_pin[20];
5'h15 : out_int = in_pin[21];
5'h16 : out_int = in_pin[22];
5'h17 : out_int = in_pin[23];
5'h18 : out_int = in_pin[24];
5'h19 : out_int = in_pin[25];
5'h1A : out_int = in_pin[26];
5'h1B : out_int = in_pin[27];
5'h1C : out_int = in_pin[28];
5'h1D : out_int = in_pin[29];
default : out_int = 1'b0;
endcase
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file inside CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of register file memories ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_rf.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed, coding style changed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_rf(
// Clock and reset
clk, rst,
// Write i/f
cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
// Read i/f
id_freeze, addra, addrb, dataa, datab, rda, rdb,
// Debug
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
, sp_attack_enable, gpr_written_to, gpr_written_addr, gpr_written_data, sp_exception_comb
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Write i/f
//
input cy_we_i;
output cy_we_o;
input supv;
input wb_freeze;
input [aw-1:0] addrw;
input [dw-1:0] dataw;
input we;
input flushpipe;
//
// Read i/f
//
input id_freeze;
input [aw-1:0] addra;
input [aw-1:0] addrb;
output [dw-1:0] dataa;
output [dw-1:0] datab;
input rda;
input rdb;
//
// SPR access for debugging purposes
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
input du_read;
input [31:0] sp_attack_enable;
output [aw-1:0] gpr_written_addr;
output [dw-1:0] gpr_written_data;
output gpr_written_to;
input sp_exception_comb;
//
// Internal wires and regs
//
wire [dw-1:0] from_rfa;
wire [dw-1:0] from_rfb;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrw;
wire [dw-1:0] rf_dataw;
wire rf_we;
wire spr_valid;
wire rf_ena;
wire rf_enb;
reg rf_we_allow;
// Logic to restore output on RFA after debug unit has read out via SPR if.
// Problem was that the incorrect output would be on RFA after debug unit
// had read out - this is bad if that output is relied upon by execute
// stage for next instruction. We simply save the last address for rf A and
// and re-read it whenever the SPR select goes low, so we must remember
// the last address and generate a signal for falling edge of SPR cs.
// -- Julius
// Detect falling edge of SPR select
reg spr_du_cs;
wire spr_cs_fe;
// Track RF A's address each time it's enabled
reg [aw-1:0] addra_last;
always @(posedge clk)
if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
addra_last <= addra;
always @(posedge clk)
spr_du_cs <= spr_cs & du_read;
assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
//
// Operand A comes from RF or from saved A register
//
assign dataa = from_rfa;
//
// Operand B comes from RF or from saved B register
//
assign datab = from_rfb;
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
spr_cs_fe ? addra_last : addra;
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
assign gpr_written_addr = rf_addrw;
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (rf_addrw == 0) ? 32'b0 : (spr_valid & spr_write) ? spr_dat_i : dataw;
assign gpr_written_data = rf_dataw;
//
// RF write enable is either from SPRS or normal from CPU control
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
rf_we_allow <= 1'b1;
else if (~wb_freeze)
rf_we_allow <= ~flushpipe;
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
assign gpr_written_to = rf_we;
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze;
`ifdef OR1200_RFRAM_TWOPORT
//
// Instantiation of register file two-port RAM A
//
or1200_tpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(rf_addra),
.di_a(32'h0000_0000),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
//
// Instantiation of register file two-port RAM B
//
or1200_tpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),
.di_a(32'h0000_0000),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
`else
`ifdef OR1200_RFRAM_DUALPORT
//
// Instantiation of register file two-port RAM A
//
or1200_dpram #
(
.aw(5),
.dw(32)
)
rf_a
(
// Port A
.clk_a(clk),
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
//
// Instantiation of register file two-port RAM B
//
or1200_dpram #
(
.aw(5),
.dw(32)
)
rf_b
(
// Port A
.clk_a(clk),
.ce_a(rf_enb),
.addr_a(addrb),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
`else
`ifdef OR1200_RFRAM_GENERIC
//
// Instantiation of generic (flip-flop based) register file
//
or1200_rfram_generic rf_a(
// Clock and reset
.clk(clk),
.rst(rst),
// Port A
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.ce_b(rf_enb),
.addr_b(addrb),
.do_b(from_rfb),
// Port W
.ce_w(rf_we & ~sp_exception_comb),
.we_w(rf_we & ~sp_exception_comb),
.addr_w(rf_addrw),
.di_w(rf_dataw)
);
`else
//
// RFRAM type not specified
//
initial begin
$display("Define RFRAM type.");
$finish;
end
`endif
`endif
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; long long second; long long a1[1231], a2[2131]; long long b[1231]; long long sum[1231]; int main() { int n; cin >> n; for (int i = 2; i <= n; i++) cin >> a1[i]; for (int i = 1; i <= n - 1; i++) cin >> a2[i]; for (int i = 1; i <= n; i++) { cin >> b[i]; second += a1[i]; sum[i] = b[i] + second; } second = 0; for (int i = n; i >= 1; i--) { second += a2[i]; sum[i] += second; } sort(sum, sum + n + 1); cout << sum[1] + sum[2]; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_log.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc, ////
//// - Tadej Markovic, ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, ////
//// Tadej Markovic, ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
module uart_log;
parameter testcase_name = "";
integer report_log_file_desc;
integer verbose_log_file_desc;
reg free;
integer tests_ok;
integer tests_failed;
initial free = 1;
initial tests_ok = 0;
initial tests_failed = 0;
task start_log;
output ok_o;
begin
report_log_file_desc = $fopen({"../log/", testcase_name, "_report.log"});
verbose_log_file_desc = $fopen({"../log/", testcase_name, "_verbose.log"});
if ((report_log_file_desc == 0) || (verbose_log_file_desc == 0))
ok_o = 1'b0;
else
ok_o = 1'b1;
end
endtask // start_log
task end_log;
begin
report_add_delimiter;
$fdisplay(report_log_file_desc, "TEST CASE execution summary:");
$fdisplay(report_log_file_desc, "Number of tests PASSED=%0d", tests_ok);
$fdisplay(report_log_file_desc, "Number of tests FAILED=%0d", tests_failed);
$fdisplay(report_log_file_desc, " Simulation End Time: %t", $time);
report_add_delimiter;
$fclose(report_log_file_desc);
$fclose(verbose_log_file_desc);
end
endtask // end_log
task report_test_name;
input [1599:0] test_i;
begin
report_add_delimiter;
$fdisplay(report_log_file_desc, "%0s", test_i);
end
endtask // report_test_name
task report_test_failed;
input [7999:0] message_i;
begin
$fdisplay(report_log_file_desc, " FAILED!");
$fdisplay(report_log_file_desc, " Failure message: %0s.", message_i);
$fdisplay(report_log_file_desc, " Simulation Time: %t", $time);
end
endtask // report_test_failed
task report_test_ok;
begin
$fdisplay(report_log_file_desc, " PASSED!");
$fdisplay(report_log_file_desc, " Simulation Time: %t", $time);
end
endtask // report_test_ok
task report_add_delimiter;
begin
$fdisplay(report_log_file_desc, "");
$fdisplay(report_log_file_desc, "%0s", {75{"-"}});
$fdisplay(report_log_file_desc, "");
end
endtask // report_add_delimiter
task report_add_text;
input [7999:0] text_i;
begin
$fdisplay(report_log_file_desc, " %0s", text_i);
end
endtask // report_add_text
task verbose_test_name;
input [1599:0] test_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "");
$fdisplay(verbose_log_file_desc, "%0s", {75{"-"}});
$fdisplay(verbose_log_file_desc, "- %0s", test_i);
$fdisplay(verbose_log_file_desc, "%0s", {75{"-"}});
$fdisplay(verbose_log_file_desc, "");
free = 1;
end
endtask // verbose_test_name
task verbose_severe_err;
input [7999:0] time_i;
input [7999:0] severe_error_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*E, Reporting severe error:");
$fdisplay(verbose_log_file_desc, " %0s", severe_error_i);
free = 1;
end
endtask // verbose_severe_err
task verbose_err;
input [7999:0] time_i;
input [7999:0] error_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*E, %0s", error_i);
free = 1;
end
endtask // verbose_err
task verbose_wrn;
input [7999:0] time_i;
input [7999:0] warning_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*W, %0s", warning_i);
free = 1;
end
endtask // verbose_wrn
task verbose_msg;
input [7999:0] time_i;
input [7999:0] message_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*N, %0s", message_i);
free = 1;
end
endtask // verbose_msg
task verbose_val;
input [7999:0] time_i;
input [7999:0] message_i;
input [31:0] value_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*N, %0s %0h.", message_i, value_i);
free = 1;
end
endtask // verbose_val
endmodule // uart_log
|
#include <bits/stdc++.h> using namespace std; int main() { int d[100008] = {0}; int n = 0, f = 0; cin >> n; for (f = 0; f < n; f++) cin >> d[f]; sort(d, d + n); if (d[n - 1] >= d[n - 2] + d[n - 3]) cout << NO ; else { cout << YES n ; for (f = n - 1; f >= 0; f -= 2) cout << d[f] << ; f = n % 2; for (; f < n; f += 2) { cout << d[f]; if (f != n - 2) cout << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; template <class T> inline void checkmin(T& a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T& a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline T lsb(T n) { return (n & (-n)); } template <class T> inline int countbit(T n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } template <class T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } bool isequal(vector<int> a, vector<int> b) { for (int i = 0; i < (a.size()); i++) if (a[i] != b[i]) return false; return true; } template <class T> bool allequal(vector<T> a) { sort(a.begin(), a.end()); return a[0] == a[a.size() - 1]; } template <class T> void printarray(vector<T> a) { for (int i = 0; i < (a.size()); i++) cout << a[i] << ; cout << endl; } template <class T> void printsubarray(vector<T> a, int start, int end) { if (start < 0 or end > a.size() - 1) cout << Out of bounds << endl; for (int i = start; i <= end; i++) cout << a[i] << ; cout << endl; } bool isprime(int n) { if (n < 2) return false; if (n == 2) return true; for (int i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } void split(const string& s, char c, vector<string>& result) { stringstream ss(s); string x; while (getline(ss, x, c)) result.push_back(x); } void err(vector<string>::iterator it) {} template <typename T, typename... Args> void err(vector<string>::iterator it, T a, Args... args) { cerr << it->substr((*it)[0] == , it->length()) << = << a << n ; err(++it, args...); } void readarray(vector<int>& a, int size) { int tmp; a.clear(); for (int i = 0; i < (size); i++) { cin >> tmp; a.push_back(tmp); } } bool invalid(int n, int k) { int nbits = countbit(n); if (k < nbits or k > n) return true; return false; } vector<int> res; void split(int n, int k) { if (k == 1) { res.push_back(n); } else { int nbits = countbit(n); if (nbits == 1) { split(n >> 1, ((k >> 1) + k % 2)); split(n >> 1, (k >> 1)); } else { int a, b; int msb = (int)log2(n); a = (1 << msb); b = n ^ a; int excess = k - nbits + 1; int first = min(excess, a); { vector<string> _v; split( a, b, excess, nbits, k, first , , , _v); err(_v.begin(), a, b, excess, nbits, k, first); }; split(a, first); split(b, k - first); } } } void solvecase() { int n, k; cin >> n >> k; if (invalid(n, k)) { cout << NO << endl; return; } split(n, k); cout << YES << endl; printarray(res); } int main() { int cases = 1; while (cases--) { solvecase(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { char c; bool nega = 0; while ((!isdigit(c = getchar())) && (c != - )) ; if (c == - ) { nega = 1; c = getchar(); } x = c - 48; while (isdigit(c = getchar())) x = x * 10 + c - 48; if (nega) x = -x; } template <typename T> inline void writep(T x) { if (x > 9) writep(x / 10); putchar(x % 10 + 48); } template <typename T> inline void write(T x) { if (x < 0) { putchar( - ); x = -x; } writep(x); } template <typename T> inline void writeln(T x) { write(x); putchar( n ); } int n, m; int f[5001][5001]; char c[5001][5001]; inline int sum(int x, int y, int u, int v) { return f[u][v] - f[u][y - 1] - f[x - 1][v] + f[x - 1][y - 1]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> c[i][j]; c[i][j] -= 0 ; } for (int i = 1; i <= 5000; i++) for (int j = 1; j <= 5000; j++) f[i][j] = f[i - 1][j] + f[i][j - 1] - f[i - 1][j - 1] + c[i][j]; int ans = m * n; for (int k = 2500; k >= 2; k--) { int i = 1; int res = 0; int sq = k * k; int t = 0; do { int j = 1; do { t = sum(i, j, i + k - 1, j + k - 1); res += min(t, sq - t); j += k; } while (j <= m); i += k; } while (i <= n); ans = min(ans, res); } writeln(ans); }
|
#include <bits/stdc++.h> using namespace std; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; int inp[100005]; int main() { int n, a, b; cin >> n; int flag = 0; string str; for (int i = 0; i < n; i++) { cin >> str; int a, b; cin >> a >> b; if (a >= 2400 && b > 2400 && b - a > 0) { flag = 1; } } if (flag) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 50; char s[N], t[N]; int n, a[N], b[N], c[N]; int main(void) { scanf( %d , &n); scanf( %s , s); scanf( %s , t); for (int i = 0; i < n; i++) { a[i] = s[i] - a ; b[i] = t[i] - a ; } for (int i = 0; i < n; i++) { c[i] += (a[i] + b[i]) / 2; if ((a[i] + b[i]) % 2) { c[i + 1] += 13; } } for (int i = n - 1; i >= 0; i--) { c[i - 1] += c[i] / 26; c[i] %= 26; } for (int i = 0; i < n; i++) { printf( %c , (char)( a + c[i])); } printf( n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_4_V
`define SKY130_FD_SC_LP__ISOBUFSRC_4_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__isobufsrc_4 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__isobufsrc_4 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_S_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_S_TB_V
/**
* udp_dlatch$P_pp$PKG$s: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 KAPWR = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 KAPWR = 1'b0;
#260 SLEEP_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SLEEP_B = 1'b1;
#380 KAPWR = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SLEEP_B = 1'bx;
#480 KAPWR = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$s dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_S_TB_V
|
#include <bits/stdc++.h> using namespace std; struct matrix { int a[25][25]; }; struct matrix g, b, e; int l, r, mod = 1000000007; int ans; void init() { int i, j; g.a[7][2] = 1; g.a[10][3] = 1; g.a[11][3] = 1; g.a[8][5] = 1; g.a[10][6] = 1; g.a[11][6] = 1; g.a[2][7] = 1; g.a[3][7] = 1; g.a[5][8] = 1; g.a[6][8] = 1; g.a[2][10] = 1; g.a[3][10] = 1; g.a[5][11] = 1; g.a[6][11] = 1; for (i = 1; i <= 12; i++) for (j = 13; j <= 24; j++) g.a[i][j] = g.a[i][j - 12]; for (i = 13; i <= 24; i++) g.a[i][i] = 1; b.a[1][2] = 1; b.a[1][3] = 1; b.a[1][5] = 1; b.a[1][6] = 1; b.a[1][7] = 1; b.a[1][8] = 1; b.a[1][10] = 1; b.a[1][11] = 1; b.a[1][14] = 1; b.a[1][15] = 1; b.a[1][17] = 1; b.a[1][18] = 1; b.a[1][19] = 1; b.a[1][20] = 1; b.a[1][22] = 1; b.a[1][23] = 1; for (i = 1; i <= 24; i++) e.a[i][i] = 1; } matrix operator*(matrix aa, matrix bb) { int i, j, k; matrix ret; for (i = 1; i <= 24; i++) for (j = 1; j <= 24; j++) ret.a[i][j] = 0; for (i = 1; i <= 24; i++) for (k = 1; k <= 24; k++) if (aa.a[i][k]) { for (j = 1; j <= 24; j++) ret.a[i][j] = (ret.a[i][j] + (long long)aa.a[i][k] * bb.a[k][j] % mod) % mod; } return ret; } matrix fpow(int j) { matrix d, ret; ret = e; d = g; while (j != 0) { if (j & 1) ret = ret * d; d = d * d; j = j / 2; } return ret; } int calc(int n) { matrix s; int i, ret = 0; if (n == 0) return 0; if (n == 1) return 4; s = b * fpow(n - 2); for (i = 13; i <= 24; i++) ret = (ret + s.a[1][i]) % mod; return ret + 4; } int main() { int i, j; init(); scanf( %d%d , &l, &r); ans = (((long long)calc(r) + calc((r + 1) / 2)) % mod - ((long long)calc(l - 1) + calc(l / 2)) % mod) % mod; if (ans % 2 != 0) ans += mod; ans /= 2; ans = (ans + mod) % mod; cout << ans << endl; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_dma(
input sys_rst,
input sys_clk,
output reg [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output reg wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o,
output reg down_en,
input down_next_frame,
output reg down_pcmleft_valid,
output reg [19:0] down_pcmleft,
output reg down_pcmright_valid,
output reg [19:0] down_pcmright,
output reg up_en,
input up_next_frame,
input up_frame_valid,
input up_pcmleft_valid,
input [19:0] up_pcmleft,
input up_pcmright_valid,
input [19:0] up_pcmright,
/* in 32-bit words */
input dmar_en,
input [29:0] dmar_addr,
input [15:0] dmar_remaining,
output reg dmar_next,
input dmaw_en,
input [29:0] dmaw_addr,
input [15:0] dmaw_remaining,
output reg dmaw_next
);
assign wbm_cti_o = 3'd0;
reg wbm_strobe;
assign wbm_cyc_o = wbm_strobe;
assign wbm_stb_o = wbm_strobe;
reg load_read_addr;
reg load_write_addr;
always @(posedge sys_clk) begin
if(load_read_addr)
wbm_adr_o <= {dmar_addr, 2'b00};
else if(load_write_addr)
wbm_adr_o <= {dmaw_addr, 2'b00};
end
reg load_downpcm;
always @(posedge sys_clk) begin
if(load_downpcm) begin
down_pcmleft_valid <= dmar_en;
down_pcmright_valid <= dmar_en;
down_pcmleft <= {20{dmar_en}} & {{wbm_dat_i[31:16], wbm_dat_i[30:27]}};
down_pcmright <= {20{dmar_en}} & {{wbm_dat_i[15:0], wbm_dat_i[14:11]}};
end
end
assign wbm_dat_o = {up_pcmleft[19:4], up_pcmright[19:4]};
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter DMAR = 3'd1;
parameter DMAW = 3'd2;
parameter NEXTDFRAME = 3'd3;
parameter NEXTUFRAME = 3'd4;
wire dmar_finished = dmar_remaining == 16'd0;
wire dmaw_finished = dmaw_remaining == 16'd0;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
//$display("state:%d->%d %b %b %b", state, next_state, down_next_frame, dmar_en, ~dmar_finished);
end
always @(*) begin
next_state = state;
wbm_strobe = 1'b0;
load_read_addr = 1'b0;
load_write_addr = 1'b0;
wbm_we_o = 1'b0;
down_en = 1'b0;
up_en = 1'b0;
dmar_next = 1'b0;
dmaw_next = 1'b0;
load_downpcm = 1'b0;
case(state)
IDLE: begin
down_en = 1'b1;
up_en = 1'b1;
if(down_next_frame) begin
if(dmar_en)
down_en = 1'b0;
else
load_downpcm = 1'b1;
end
if(up_next_frame) begin
if(dmaw_en)
up_en = 1'b0;
end
if(down_next_frame & dmar_en & ~dmar_finished) begin
load_read_addr = 1'b1;
next_state = DMAR;
end else if(up_next_frame & dmaw_en & ~dmaw_finished) begin
load_write_addr = 1'b1;
next_state = DMAW;
end
end
DMAR: begin
wbm_strobe = 1'b1;
load_downpcm = 1'b1;
if(wbm_ack_i) begin
dmar_next = 1'b1;
next_state = NEXTDFRAME;
end
end
DMAW: begin
wbm_strobe = 1'b1;
wbm_we_o = 1'b1;
if(wbm_ack_i) begin
dmaw_next = 1'b1;
next_state = NEXTUFRAME;
end
end
NEXTDFRAME: begin
down_en = 1'b1;
next_state = IDLE;
end
NEXTUFRAME: begin
up_en = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
#include<bits/stdc++.h> using namespace std; #define int long long #define fast_io ios_base::sync_with_stdio(0);cin.tie(0) #define mod 1e9 + 7 #define pb push_back #define vi vector<int> int32_t main(){ fast_io; int t;cin>>t; while(t--){ int n;cin>>n; set<int> s; vi arr(n); for(int i=0;i<n;i++){ int x;cin>>x; arr[i] = x; s.insert(x); } sort(arr.rbegin(),arr.rend()); int z = arr[n-1]; int ans = 0; for(int i=0;i<n;i++){ if(arr[i]!=z){ ans++; } } cout<<ans<<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool arr[3001]; int main() { int n, i, input; cin >> n; for (i = 1; i <= n; i++) { cin >> input; arr[input] = true; } for (i = 1; i <= 3000; i++) { if (!arr[i]) { cout << i << endl; return 0; } } cout << 3001 << endl; return 0; }
|
/* ctrl_rst.v */
`ifdef SOC_SIM
`define RST_CNT 16'h00ff // reset counter length used in simulations
`else
`define RST_CNT 16'hffff // reset counter length
`endif
module ctrl_rst (
// system
input wire clk,
// PLL lock input
input wire pll_lock,
// external reset input
input wire rst_ext,
// register reset input
input wire rst_reg,
// reset signal output
output reg rst
);
////////////////////////////////////////
// internal signals //
////////////////////////////////////////
// reset counter
reg [16-1:0] rst_cnt;
// input signal registers
reg pll_lock_n_t=0, rst_ext_t=0, rst_reg_t=0;
reg pll_lock_n_r=0, rst_ext_r=0, rst_reg_r=0;
// reset wire
wire rst_wire;
////////////////////////////////////////
// register initial settings //
////////////////////////////////////////
initial begin
pll_lock_n_t = 1'b1;
rst_ext_t = 1'b1;
rst_reg_t = 1'b1;
pll_lock_n_r = 1'b1;
rst_ext_r = 1'b1;
rst_reg_r = 1'b1;
rst_cnt = `RST_CNT;
rst = 1'b1;
end
////////////////////////////////////////
// logic //
////////////////////////////////////////
// register & synchronize inputs
always @ (posedge clk)
begin
pll_lock_n_t <= #1 !pll_lock;
rst_ext_t <= #1 rst_ext;
rst_reg_t <= #1 rst_reg;
pll_lock_n_r <= #1 pll_lock_n_t;
rst_ext_r <= #1 rst_ext_t;
rst_reg_r <= #1 rst_reg_t;
end
// reset counter
always @ (posedge clk)
begin
if (rst_reg_r || rst_ext_r || pll_lock_n_r) rst_cnt <= #1 `RST_CNT;
else if (|rst_cnt) rst_cnt <= #1 rst_cnt - 1'd1;
end
// reset wire
assign rst_wire = (|rst_cnt);
// output reset registers
always @ (posedge clk)
begin
rst <= #1 rst_wire;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; int main() { long long int n, m, i, j, x, y, l = INF, u = 0; cin >> n >> m; if (m == 0) cout << n - 1 << endl; else { for (i = 0; i < m; i++) { cin >> x >> y; if (y < x) swap(x, y); u = max(u, x); l = min(l, y); } if (l - u > 0) cout << l - u << endl; else cout << 0 << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, m; int dp[303030][30]; int u, v; int in[303030]; vector<int> adj[303030]; char s[303030]; int main() { scanf( %d %d , &n, &m); scanf( %s , s); for (int i = 0; i < m; ++i) { scanf( %d %d , &u, &v); --u; --v; adj[u].push_back(v); in[v]++; } queue<int> q; for (int i = 0; i < n; ++i) { if (in[i] == 0) { q.push(i); } } int cnt = 0; while (!q.empty()) { int u = q.front(); q.pop(); ++cnt; dp[u][s[u] - a ]++; for (int v : adj[u]) { if (--in[v] == 0) { q.push(v); } for (int i = 0; i < 26; ++i) { dp[v][i] = max(dp[v][i], dp[u][i]); } } } if (cnt == n) { int ans = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < 26; ++j) { ans = max(ans, dp[i][j]); } } printf( %d n , ans); } else { printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[1000005]; int main() { int n, q, a, b, x = 0, xPar = 0; scanf( %d %d , &n, &q); while (q--) { scanf( %d , &a); if (a == 1) { scanf( %d , &b); x += b; if (x >= n) { x = x % n; } else if (x < 0) { x = n - ((x * -1) % n); } } else { if ((x + xPar) % 2 == 1) { xPar = ((xPar + 1) % n); } else { if (--xPar < 0) { xPar += n; } } } } for (int i = 1; i <= n; i++) { int nTemp = i + x; if (i % 2) { nTemp -= xPar; } else { nTemp += xPar; } while (nTemp <= 0) { nTemp += n; } while (nTemp > n) { nTemp -= n; } arr[nTemp] = i; } for (int i = 1; i <= n; i++) { cout << arr[i]; if (i != n) { cout << ; } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_BEHAVIORAL_PP_V
|
module testbench_CLA();
parameter bits = 8;
reg [bits-1:0] operand1;
reg [bits-1:0] operand2;
reg carryIn;
wire [bits-1:0] result;
wire carryOut;
wire p;
wire g;
integer i;
integer j;
integer k;
reg errorFlag = 0;
reg expectG;
reg expectP;
reg expectCOut;
reg [bits-1:0] expectResult;
initial begin
carryIn = 0;
for(k = 0;k < 2;k = k+1) begin
carryIn = ~carryIn;
for(i = 0;i < (1 << bits);i = i+1) begin
operand1 = i;
for(j = 0;j < (1 << bits);j = j+1) begin
operand2 = j;
{expectG,expectResult[bits-1:0]} = operand1 + operand2;
{expectCOut,expectResult[bits-1:0]} = operand1 + operand2 + carryIn;
expectP = &(operand1|operand2);
#1;
if (expectG !== g) begin
errorFlag = 1;
$display("singal G fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
if(expectP !== p) begin
errorFlag = 1;
$display("singal P fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
if(expectResult !== result) begin
errorFlag = 1;
$display("result fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
if(expectCOut !== carryOut) begin
errorFlag = 1;
$display("carry out fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
end
end
end
if(errorFlag == 0) begin
$display("Result test pass");
end
else begin
$display("Result test fail");
end
end
CLA #bits cla(.operand1(operand1), .operand2(operand2), .carryIn(carryIn), .carryOut(carryOut), .result(result), .p(p), .g(g));
endmodule
|
#include <bits/stdc++.h> using namespace std; double r[1000]; double p = atan(1.) * 4.; int main() { double rez = 0; int n; cin >> n; for (int i = 0; i < n; i++) cin >> r[i]; sort(r, r + n); bool t = true; for (int i = n - 1; i >= 0; i--) { if (t) rez += r[i] * r[i] * p; else rez -= r[i] * r[i] * p; t = !t; } printf( %.6f , rez); cin >> n; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long T, n, s, sum; inline int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int main() { cin >> T; while (T--) { cin >> n; sum = 0; long long a[100010] = {0}; for (int i = 1; i <= n; i++) { cin >> s; a[i] += s; if (a[i] > 0) a[i + 1] += a[i]; if (a[i] < 0) sum -= a[i]; } cout << sum << endl; } }
|
module etx_fifo(/*AUTOARG*/
// Outputs
txrd_wait, txwr_wait, txrr_wait, txrd_fifo_access,
txrd_fifo_packet, txrr_fifo_access, txrr_fifo_packet,
txwr_fifo_access, txwr_fifo_packet,
// Inputs
sys_nreset, sys_clk, tx_lclk_div4, txrd_access, txrd_packet,
txwr_access, txwr_packet, txrr_access, txrr_packet, txrd_fifo_wait,
txrr_fifo_wait, txwr_fifo_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter TARGET = "GENERIC";
//Clocks,reset,config
input sys_nreset;
input sys_clk;
input tx_lclk_div4; // slow speed parallel clock
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Read request for pins
output txrd_fifo_access;
output [PW-1:0] txrd_fifo_packet;
input txrd_fifo_wait;
//Read response for pins
output txrr_fifo_access;
output [PW-1:0] txrr_fifo_packet;
input txrr_fifo_wait;
//Write for pins
output txwr_fifo_access;
output [PW-1:0] txwr_fifo_packet;
input txwr_fifo_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
/************************************************************/
/*FIFOs */
/************************************************************/
//TODO: Minimize depth and width
/*fifo_cdc AUTO_TEMPLATE (
// Outputs
.access_out (@"(substring vl-cell-name 0 4)"_fifo_access),
.packet_out (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
.wait_out (@"(substring vl-cell-name 0 4)"_wait),
.wait_in (@"(substring vl-cell-name 0 4)"_fifo_wait),
.clk_out (tx_lclk_div4),
.clk_in (sys_clk),
.access_in (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.nreset (sys_nreset),
.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
);
*/
//Write fifo (from slave)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
txwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txwr_wait), // Templated
.access_out (txwr_fifo_access), // Templated
.packet_out (txwr_fifo_packet[PW-1:0]), // Templated
// Inputs
.nreset (sys_nreset), // Templated
.clk_in (sys_clk), // Templated
.access_in (txwr_access), // Templated
.packet_in (txwr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.wait_in (txwr_fifo_wait)); // Templated
//Read request fifo (from slave)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
txrd_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrd_wait), // Templated
.access_out (txrd_fifo_access), // Templated
.packet_out (txrd_fifo_packet[PW-1:0]), // Templated
// Inputs
.nreset (sys_nreset), // Templated
.clk_in (sys_clk), // Templated
.access_in (txrd_access), // Templated
.packet_in (txrd_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.wait_in (txrd_fifo_wait)); // Templated
//Read response fifo (from master)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
txrr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrr_wait), // Templated
.access_out (txrr_fifo_access), // Templated
.packet_out (txrr_fifo_packet[PW-1:0]), // Templated
// Inputs
.nreset (sys_nreset), // Templated
.clk_in (sys_clk), // Templated
.access_in (txrr_access), // Templated
.packet_in (txrr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.wait_in (txrr_fifo_wait)); // Templated
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<pair<int, int> > a(n); for (int i = (0); i < ((n)); ++i) cin >> a[i].first >> a[i].second; sort(a.begin(), a.end()); long long best = -1; vector<long long> dp(n, 0); for (int i = n - 1; i >= 0; --i) { dp[i] = -1; long long prev = 0; for (int j = i; j < n; ++j) { prev += a[j].first - a[i].first; long long cost = a[i].second + prev + (j == n - 1 ? 0 : dp[j + 1]); if (dp[i] == -1 || dp[i] > cost) { dp[i] = cost; } } if (dp[i] == -1) dp[i] = a[i].second; } cout << dp[0] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.sync_with_stdio(false); cin.tie(nullptr); long long int n; cin >> n; bool prime = true; for (long long int i = 2; i < n && i < 101010; ++i) { if (n % i == 0) { prime = false; } } if (prime) { cout << 1 n ; return 0; } if (n % 2 == 0) { cout << 2 n ; return 0; } bool prime2 = true; long long int n2 = n - 2; for (long long int i = 2; i < n2 && i < 101010; ++i) { if (n2 % i == 0) { prime2 = false; } } if (prime2) { cout << 2 n ; return 0; } cout << 3 n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 500; const int MAXM = (int)1e5; vector<int> g[MAXN + 1]; int x[MAXM + 1], y[MAXM + 1]; int ok[MAXN + 1]; bool flag; vector<int> edge; void dfs(int nod) { ok[nod] = 1; edge.push_back(nod); for (auto it : g[nod]) { if (flag == 0) { if (ok[it] == 0) { dfs(it); } else if (ok[it] == 1) { flag = 1; edge.push_back(it); } } } ok[nod] = 2; if (flag == 0) edge.pop_back(); } int a, b; void dfs1(int nod) { ok[nod] = 1; for (auto it : g[nod]) { if (flag == 0 && !(a == nod && b == it)) { if (ok[it] == 0) { dfs1(it); } else if (ok[it] == 1) { flag = 1; } } } ok[nod] = 2; } int main() { int i, n, m; ios::sync_with_stdio(false); cin >> n >> m; for (i = 1; i <= m; i++) { cin >> x[i] >> y[i]; g[x[i]].push_back(y[i]); } for (i = 1; i <= n && flag == 0; i++) { if (ok[i] == 0) { dfs(i); } } if (flag == 0) { cout << YES ; return 0; } int sz = edge.size(); for (i = sz - 2; i >= 0; i--) { a = edge[i], b = edge[i + 1]; if (i == sz - 2 || b != edge.back()) { memset(ok, 0, sizeof(ok)); flag = 0; for (int j = 1; j <= n && flag == 0; j++) { if (ok[j] == 0) dfs1(j); } if (flag == 0) { cout << YES ; return 0; } } else break; } cout << NO ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Copyright (C) 2005 Rice University - Rice Open License Fill
`include "spi_defines.v"
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = reg_ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[`SPI_CTRL_CHAR_LEN];
assign lsb = reg_ctrl[`SPI_CTRL_LSB];
assign ie = reg_ctrl[`SPI_CTRL_IE];
assign ass = reg_ctrl[`SPI_CTRL_ASS];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {`SPI_SS_NB{tip & ass}}) | (reg_ss & {`SPI_SS_NB{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module alu(
input [31:0] A,
input [31:0] B,
input [2:0] ALU_operation,
output [31:0] res,
output zero,
output reg overflow
);
wire [31:0] res_and,res_or,res_add,res_sub,res_nor,res_slt;
reg [31:0] res_op;
parameter one = 32'h00000001,zero_0=32'h00000000;
assign res_and = A&B;
assign res_or = A|B;
assign res_add = A+B;
assign res_sub = A-B;
assign res_slt = (A<B)?one:zero_0;
assign res = res_op[31:0];
always @(*) begin
overflow = 0;
case(ALU_operation)
3'b000: res_op = res_and;
3'b001: res_op = res_or;
3'b010: begin
res_op = res_add;
if ((A[31:31]&B[31:31]&~res[31:31]) | (~A[31:31]&~B[31:31]&res[31:31]))
overflow = 1;
end
3'b110: begin
res_op = res_sub;
if ((A[31:31]&~B[31:31]&~res[31:31]) | (~A[31:31]&B[31:31]&res[31:31]))
overflow = 1;
end
3'b100: res_op = ~(A|B);
3'b111: res_op = res_slt;
3'b101: res_op = A >> 1;
3'b011: res_op = (~A&B) | (A&~B);
default: res_op=32'hxxxxxxxx;
endcase
end
assign zero = (res==0)?1:0;
endmodule
|
//====================================================================
// bsg_imul_iterative.v
// 11/15/2016,
//====================================================================
//
// An 32bit integer iterative multiplier, capable of signed & unsigned division
// a3 a2 a1 a0
// b3 b2 b1 b0
// ------------------------------------------------------------------
// | a3b0 a2b0 a1b0 a0b0
// a3b1 | a2b1 a1b1 a0b1
// a3b2 a2b2 | a1b2 a0b2
// a3b3 a2b3 a1b3 | a0b3
// ------------------------------------------------------------------
// High Part | Low Part
//
// 1. for LOW part output:
// def imul( a, b ):
// result = 0
// for i in range(32):
// if b & 0x1 == 1:
// result += a
// a = a << 1
// b = b >> 1
// return result
//
// 2. for HIGH part output
// def imul( a, b ):
// result = 0
// for i in range(31):
// if b & 0x1 == 1:
// result = ( {1'b0,result} + {1'b0,a}) >> 1
// else:
// result = result >> 1
//
// b = b >> 1
// return result
// 3. for negtive high part output, we have to check if the low part of the
// abs(result) are all zeros. If it is all zero, we have to add 1 to the
// neg high part, otherwise we onely have to neg the high part
// -(4'b10_00) = ~(4'b10 00) + 1 = 4'b01_11 + 1= 4'b10_00
// -(4'b10_10) = ~(4'b10_10) + 1 = 4'b01_01 + 1= 4'b01_10
//
// We add a one bit register to track whether the shifted out LSB of the result
// are all zeros
//
`include "bsg_defines.v"
module bsg_imul_iterative #( width_p = 32)
(input clk_i
,input reset_i
,input v_i //there is a request
,output ready_o //idiv is idle
,input [width_p-1: 0] opA_i
,input signed_opA_i
,input [width_p-1: 0] opB_i
,input signed_opB_i
//needs the high part result or low part result
,input gets_high_part_i
,output v_o //result is valid
,output [width_p-1: 0] result_o
,input yumi_i
);
localparam lg_width_lp = `BSG_SAFE_CLOG2( width_p + 1);
///////////////////////////////////////////////////////////////////////////////
// counter for the shift operation
logic[lg_width_lp-1:0] shift_counter_r;
logic gets_high_part_r;
wire shift_counter_full = gets_high_part_r
? ( shift_counter_r == (width_p-1) )
: ( shift_counter_r == width_p );
///////////////////////////////////////////////////////////////////////////////
// The state machine
typedef enum logic[2:0] {IDLE, NEG_A, NEG_B, CALC, NEG_R, DONE } imul_ctrl_stat;
imul_ctrl_stat curr_state_r, next_state;
// state machine register
always_ff@( posedge clk_i ) begin
if( reset_i ) curr_state_r <= IDLE;
else curr_state_r <= next_state;
end
//determing next state
always_comb begin
unique case(curr_state_r )
IDLE: begin
if( v_i ) next_state = NEG_A;
else next_state = IDLE;
end
NEG_A: next_state = NEG_B;
NEG_B: next_state = CALC ;
CALC: begin
if( !shift_counter_full ) next_state = CALC;
else next_state = NEG_R;
end
NEG_R: next_state = DONE;
DONE: begin
if( yumi_i ) next_state = IDLE;
else next_state = DONE;
end
default: next_state = IDLE;
endcase
end
///////////////////////////////////////////////////////////////////////////////
// update the shift_counter_r
always_ff@( posedge clk_i ) begin
if ( reset_i ) shift_counter_r <= 'b0; //reset
else if( curr_state_r != CALC && next_state == CALC )
shift_counter_r <= 'b0; //new request
else if( curr_state_r == CALC)
shift_counter_r <= shift_counter_r + 1;
end
///////////////////////////////////////////////////////////////////////////////
// the computation logic
logic [width_p-1:0] opA_r, opB_r, result_r;
logic [width_p-1:0] adder_a, adder_b;
logic [width_p :0] adder_result,shifted_adder_result;
// -opA_r = ~opA_r + 1, reunsing the adder here
assign adder_a = (curr_state_r == NEG_A) ? ~opA_r :
(curr_state_r == NEG_B) ? ~opB_r :
(curr_state_r == NEG_R) ? ~result_r : result_r;
wire adder_neg_op = (curr_state_r == NEG_A
|| curr_state_r == NEG_B
|| curr_state_r == NEG_R);
assign adder_b = adder_neg_op ? { {(width_p-1){1'b0}}, 1'b1}
: opA_r ;
assign adder_result = {1'b0, adder_a} + {1'b0, adder_b};
assign shifted_adder_result = adder_result >> 1;
///////////////////////////////////////////////////////////////////////////////
// control register update logic
wire latch_input = v_i & ready_o;
logic signed_opA_r, signed_opB_r, need_neg_result_r;
wire signed_opA = signed_opA_i & opA_i[width_p-1];
wire signed_opB = signed_opB_i & opB_i[width_p-1];
always_ff@(posedge clk_i ) begin
if( reset_i ) signed_opA_r <= 1'b0;
else if( latch_input ) signed_opA_r <= signed_opA;
end
always_ff@(posedge clk_i ) begin
if( reset_i ) signed_opB_r <= 1'b0;
else if( latch_input ) signed_opB_r <= signed_opB;
end
always_ff@(posedge clk_i ) begin
if( reset_i ) need_neg_result_r <= 1'b0;
else if( latch_input ) need_neg_result_r <= signed_opA ^ signed_opB ;
end
always_ff@(posedge clk_i ) begin
if( reset_i ) gets_high_part_r <= 1'b0;
else if( latch_input ) gets_high_part_r <= gets_high_part_i;
end
///////////////////////////////////////////////////////////////////////////////
// operands update logic
always_ff@(posedge clk_i) begin
if( reset_i ) opA_r <= 'b0;
else if( latch_input ) opA_r <= opA_i;
//opA only shifts when we want low part result
else if(curr_state_r == CALC && (!gets_high_part_r ) )
opA_r <= opA_r << 1 ;
else if(curr_state_r == NEG_A && signed_opA_r) //get the abs(opA)
opA_r <= adder_result[width_p-1:0];
end
always_ff@(posedge clk_i) begin
if( reset_i ) opB_r <= 'b0;
else if( latch_input ) opB_r <= opB_i;
else if(curr_state_r == CALC) opB_r <= opB_r >> 1 ;
else if(curr_state_r == NEG_B && signed_opB_r) //get the abs(opB)
opB_r <= adder_result[width_p-1:0];
end
///////////////////////////////////////////////////////////////////////////////
// track the LSB of the result which is shifted out for high part computation
wire shifted_lsb = opB_r[0] ? adder_result[0] : result_r[0];
logic all_sh_lsb_zero_r;
always_ff@(posedge clk_i ) begin
if( reset_i ) all_sh_lsb_zero_r <= 1'b0;
else if( latch_input ) all_sh_lsb_zero_r <= 1'b1;
else if( curr_state_r == CALC ) all_sh_lsb_zero_r <= all_sh_lsb_zero_r
& (~shifted_lsb);
end
///////////////////////////////////////////////////////////////////////////////
// update the result register
// synopsys sync_set_reset "reset_i, latch_input"
always_ff@(posedge clk_i) begin
if( reset_i ) result_r <= 'b0;
else if( latch_input ) result_r <= 'b0;
else if(curr_state_r == NEG_R && need_neg_result_r) //get the signed result
//1. High part Neg in case Low part are not all zeros
if( gets_high_part_r && !all_sh_lsb_zero_r ) //No cin, just reverse
result_r <= ~result_r;
//1. Low part Neg
//2. High part Neg in case Low part are all zeros, ~(result_r) +1
else
result_r <= adder_result[width_p-1:0];
else if(curr_state_r == CALC && opB_r[0]) begin //get the accumulated result
if( gets_high_part_r ) result_r <= shifted_adder_result[width_p-1:0];
else result_r <= adder_result [width_p-1:0];
end
else if(curr_state_r == CALC && !opB_r[0])begin //No addition
if( gets_high_part_r ) result_r <= result_r >>1 ;
end
end
///////////////////////////////////////////////////////////////////////////////
// the output logic
assign ready_o = ( curr_state_r == IDLE );
assign result_o = result_r;
assign v_o = ( curr_state_r == DONE );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_XRES4V2_BLACKBOX_V
`define SKY130_FD_IO__TOP_XRES4V2_BLACKBOX_V
/**
* top_xres4v2: XRES (Input buffer with Glitch filter).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_xres4v2 (
XRES_H_N ,
AMUXBUS_A ,
AMUXBUS_B ,
PAD ,
DISABLE_PULLUP_H,
ENABLE_H ,
EN_VDDIO_SIG_H ,
INP_SEL_H ,
FILT_IN_H ,
PULLUP_H ,
ENABLE_VDDIO ,
PAD_A_ESD_H ,
TIE_HI_ESD ,
TIE_LO_ESD ,
TIE_WEAK_HI_H
);
output XRES_H_N ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout PAD ;
input DISABLE_PULLUP_H;
input ENABLE_H ;
input EN_VDDIO_SIG_H ;
input INP_SEL_H ;
input FILT_IN_H ;
inout PULLUP_H ;
input ENABLE_VDDIO ;
inout PAD_A_ESD_H ;
output TIE_HI_ESD ;
output TIE_LO_ESD ;
inout TIE_WEAK_HI_H ;
// Voltage supply signals
supply1 VCCD ;
supply1 VCCHIB ;
supply1 VDDA ;
supply1 VDDIO ;
supply1 VDDIO_Q;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO ;
supply0 VSSIO_Q;
supply1 VSWITCH;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_XRES4V2_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`include "verilated.v"
module t;
// Note $sscanf already tested elsewhere
reg [3:0] n;
reg [63:0] q;
reg [16*8:1] wide;
reg [8:1] char;
reg [48*8:1] str;
reg [48*8:1] str2;
real r;
initial begin
n = 4'b1100;
q = 64'h1234_5678_abcd_0123;
wide = "hello-there12345";
$sformat(str, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
q = {q[62:0],1'b1};
$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
$swrite(str2, "e=%e", r);
$swrite(str2, "e=%f", r);
$swrite(str2, "e=%g", r);
r = 0.01;
$swrite(str2, "e=%e f=%f g=%g", r, r, r);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop;
$swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
`ifdef verilator
if (str2 !== "mod=top.v") $stop;
`else
if (str2 !== "mod=top.t") $stop;
`endif
$sformat(char,"%s","c");
if (char != "c") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_revision.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_revision
// Generates revision numbers for JTAGID and SPARC V9 VERSION register.
// The JTAGID and minor mask revisions are mask programmable and can be
// incremented with a single metal layer change. The major mask revision
// is a constant for the life of a given mask set and is only incremented
// when a new full mask set is generated.
`include "ctu.h"
module ctu_revision (/*AUTOARG*/
// Outputs
jtag_id, mask_major_id, mask_minor_id
);
output [3:0] jtag_id;
output [3:0] mask_major_id;
output [3:0] mask_minor_id;
assign mask_major_id = `MASK_MAJOR;
ctu_jtag_id #`JTAGID jtag_id_cell(jtag_id);
ctu_mask_id #`MASK_MINOR mask_minor_id_cell(mask_minor_id);
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
//====================================================
// This is FSM demo program using single always
// for both seq and combo logic
// Design Name : fsm_using_single_always
// File Name : fsm_using_single_always.v
//=====================================================
module fsm_using_single_always (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//=============Input Ports=============================
input clock,reset,req_0,req_1;
//=============Output Ports===========================
output gnt_0,gnt_1;
//=============Input ports Data Type===================
wire clock,reset,req_0,req_1;
//=============Output Ports Data Type==================
reg gnt_0,gnt_1;
//=============Internal Constants======================
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//=============Internal Variables======================
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//==========Code startes Here==========================
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT1;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT1;
end else begin
gnt_1 <= 0;
state <= #1 IDLE;
end
default : state <= #1 IDLE;
endcase
end
endmodule // End of Module arbiter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_4_V
`define SKY130_FD_SC_HDLL__AND3_4_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_4_V
|
/* ring32b_bidir.v
Philip Watts
6th April 2010
Chip-to-chip module for the BEE3 based on the microsoft DDR2 code
This version hides the clock inversion control from the top level
Transmission is DDR => 64 bits over 32 wires
*/
`timescale 1ns / 1ps
module ring32b_bidir(
// Clocks and resets
input CLK, // Main interface clock
input swClk0, // Unbuffered calibration clock
input swClk180, // Unbuffered cal clock, 180 deg out of phase
input Reset,
// Data interface with fabric
input [63:0] din,
output[63:0] dout,
//Pin signals
output [31:0] RING_OUT,
input [31:0] RING_IN,
//Control signals
input lock_in,
output lock_out,
//input partner_ready,
output [31:0] test_sigs
);
//Each CLK, we send four 32-bit words.
//The testing requires Chipscope.
reg Equalx;
reg Equal;
reg Zerox;
reg Zero;
reg [63:0] TxD;
reg [63:0] RxD;
wire [31:0] outData;
wire [31:0] bankData; //data from the input pin
wire [31:0] bankDataDly; //data from the IDELAY
wire [63:0] isData; //data out of the ISERDES
reg [63:0] nextPoly; //the next received value we expect
(* KEEP = "TRUE" *) reg incDelay;
(* KEEP = "TRUE" *) reg resetDelay;
reg[6:0] currentTap;
reg[5:0] candWS; //candidate window start
reg candSW;
reg[5:0] candWW; //candidate window width
reg[5:0] WW; //window width
reg[5:0] WS; //window start
reg realSW;
reg[2:0] ringState;
//wire [35:0] control0;
//wire [255:0] cscope_sigs;
reg lock_out_int;
reg [63:0] dout_int;
wire switchClock;
wire swClock;
localparam Unlocked = 0;
localparam DecWS = 1;
localparam DecWW = 3;
localparam Locked = 2;
localparam NormOp = 6;
assign test_sigs = {26'b0, Equal, Zero, ringState, switchClock};
// Generate clocks for C2C phase alignment
// Switchable between 0 and 180 degrees phase
BUFGMUX_CTRL swClkbuf1 (
.O(swClock), // Clock MUX output
.I0(swClk0), // Clock0 input
.I1(swClk180), // Clock1 input
.S(switchClock)); // Clock select input
// Hold in reset until communicating partner is ready. Then send a test pattern
// until calibration has finished
always @(posedge CLK) begin
if(Reset)
TxD <= 63'h1;
else if (ringState==NormOp)
TxD <= din;
else
TxD <= {TxD[62:0], (TxD[63] ^ TxD[62] ^ TxD[60] ^ TxD[59])};
end
// The transmit pins
genvar pin;
generate
for(pin = 0; pin < 32; pin = pin + 1)
begin: makePin
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) dataPin (
.Q (outData[pin] ),
.C (CLK ),
.CE (1'b1 ),
.D1 (TxD[2*pin + 1]),
.D2 (TxD[2*pin] ),
.R (1'b0 ),
.S (1'b0 )
);
OBUF pinBuf(
.I(outData[pin]),
.O(RING_OUT[pin])
);
end
endgenerate
//The receiver pins
genvar inPin;
generate
for(inPin = 0; inPin < 32; inPin = inPin + 1)
begin: makeInPin
IBUF rPinBuf(.I(RING_IN[inPin]), .O(bankData[inPin]));
IDELAY #(
.IOBDELAY_TYPE("VARIABLE"), // "DEFAULT", "FIXED" or "VARIABLE"
.IOBDELAY_VALUE(0) // Any value from 0 to 63
) rPinDly (
.O(bankDataDly[inPin]), // 1-bit output
.C(CLK), // 1-bit clock input
.CE(incDelay), // 1-bit clock enable input
.I(bankData[inPin]), // 1-bit data input
.INC(incDelay), // 1-bit increment input
.RST(resetDelay) // 1-bit reset input
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE"
.INIT_Q1(1'b0), // Initial value of Q1: 1?b0 or 1?b1
.INIT_Q2(1'b0), // Initial value of Q2: 1?b0 or 1?b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) rcvIddr (
.Q1(isData[2 * inPin + 1]), // 1-bit output for positive edge of clock
.Q2(isData[2 * inPin]), // 1-bit output for negative edge of clock
.C(swClock), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(bankDataDly[inPin]), // 1-bit DDR data input
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
end
endgenerate
// Calibration process
// Finds the maximum-width window (sequence of taps for which Equal is true).
always @(posedge CLK) begin
if(Reset) begin
ringState <= Unlocked;
WS <= 0;
WW <= 0;
realSW <= 0;
candWS <= 0;
candWW <= 0;
candSW <= 0;
currentTap <= 0;
resetDelay <= 1;
incDelay <= 0;
lock_out_int <= 0;
end
else begin case(ringState)
Unlocked: begin
resetDelay <= 0;
incDelay <= 1;
currentTap <= currentTap + 1;
if( (currentTap == 127) & ({1'b0, WW} > 8)) begin // IDELAY has 64 taps x 2 phase states = 128 'taps'
resetDelay <= 1;
ringState <= DecWS;
end
else if(Equal & ~Zero & currentTap[5:0] != 31) candWW <= candWW + 1;
else begin
if({1'b0,candWW} >= {1'b0,WW}) begin
WW <= candWW;
realSW <= candSW;
WS <= candWS;
end
candWS <= currentTap[5:0];
candSW <= currentTap[6];
candWW <= 0;
end
end
DecWS: begin
resetDelay <= 0;
if(WS == 0) begin
ringState <= DecWW;
WW <= WW/2;
end
else WS <= WS - 1;
end
DecWW: begin
if(WW == 0) begin
ringState <= Locked;
incDelay <= 0;
end
else WW <= WW - 1;
end
Locked: begin
lock_out_int <= 1;
if (lock_in == 1) ringState <= NormOp;
// if(~Equal | Zero) begin
// ringState <= Unlocked;
// WS <= 0;
// WW <= 0;
// realSW <= 0;
// candWS <= 0;
// candWW <= 0;
// candSW <= 0;
// currentTap <= 0;
// resetDelay <= 1;
// incDelay <= 0;
// end
end
NormOp: begin
if (lock_in == 0) ringState <= Locked;
end
endcase
end
end
assign switchClock = ringState == Unlocked ? currentTap[6]: realSW;
always @(posedge swClock) RxD <= isData;
always @(posedge swClock) nextPoly <= {RxD[62:0], (RxD[63] ^ RxD[62] ^RxD[60] ^ RxD[59])};
always @(posedge swClock) Equalx <= nextPoly == RxD;
always @(posedge swClock) Zerox <= RxD == 0;
always @(posedge CLK) Equal <= Equalx;
always @(posedge CLK) Zero <= Zerox;
always @(posedge CLK) dout_int <= RxD;
assign dout = dout_int;
assign lock_out = lock_out_int;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Gigabit Transceiver Buffer
// /___/ /\ Filename : IBUFDS_GTE4.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/27/2015 - Initial version from E3
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_GTE4 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)(
output O,
output ODIV2,
input CEB,
input I,
input IB
);
// define constants
localparam MODULE_NAME = "IBUFDS_GTE4";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_GTE4_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL;
reg [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
// wire CEB_in;
// wire IB_in;
// wire I_in;
// assign CEB_in = (CEB !== 1'bz) && CEB; // rv 0
// assign IB_in = IB;
// assign I_in = I;
reg ODIV2_out = 1'b0;
assign ODIV2 = ODIV2_out;
reg [2:0] ce_count = 3'b001;
reg [2:0] edge_count = 3'b000;
reg allEqual = 1'b0;
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if (allEqual)
edge_count <= 3'b000;
else
if ((CEB === 1'b0) || (CEB === 1'bz)) // rv = 0
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(*) begin
case (REFCLK_HROW_CK_SEL_REG)
2'b00: ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
2'b01: ODIV2_out <= allEqual;
2'b10: ODIV2_out <= 1'b0;
2'b11: ODIV2_out <= 1'b0;
default : ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
endcase
end
// =====================
// Generate O
// =====================
assign O = ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
`ifndef XIL_XECLIB
//`ifdef XIL_TIMING
// "I" is actually a CLK so need I -> O/ODIV2 delays in functional as well.
// IB to O/ODIV2 delay added because this was creating confusion in some tools
// even though IB input behavior is not modeled.
specify
(I => O) = (100:100:100, 100:100:100);
(I => ODIV2) = (100:100:100, 100:100:100);
(IB => O) = (100:100:100, 100:100:100);
(IB => ODIV2) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
//`endif
`endif
endmodule
`endcelldefine
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX_test.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { , } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
//// and Physical Medium Attachment (PMA) sublayer, type ////
//// 1000BASE-X"; see : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section3.pdf, Clause/Section 36. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module ge_1000baseX_test
(
// --- Resets ---
input reset_pin,
// --- GE 125MHz reference clock ---
input GE_125MHz_ref_ckpin,
// --- FO TBI 125MHz Rx clk ---
input tbi_rx_ckpin,
// --- Fibre-Optic (fo) GE TBI Interface ---
input [9:0] tbi_rxd,
output [9:0] tbi_txd,
// --- GMII interface ---
output [7:0] gmii_rxd,
output gmii_rx_dv,
output gmii_rx_er,
output gmii_col,
output gmii_cs,
input [7:0] gmii_txd,
input gmii_tx_en,
input gmii_tx_er,
// --- Fibre-Optic (fo) ctrl signals ---
output sync_en,
output loop_en,
output prbs_en,
input signal_detect,
input sync,
// --- MDIO interface
inout mdio,
input mdio_ckpin
);
assign sync_en = 1'b0;
assign loop_en = 1'b0;
assign prbs_en = 1'b0;
//----------------------------------------------------------------------------
// MDIO/MDC clock buffering
//----------------------------------------------------------------------------
IBUFG mdio_ckpin_bufi(.I(mdio_ckpin), .O(mdio_ckpin_buf));
BUFG mdio_ck_bufi(.I(mdio_ckpin_buf), .O(mdc));
//----------------------------------------------------------------------------
// GE 125MHz reference clock
//----------------------------------------------------------------------------
IBUFG GE_125MHz_ref_ckpin_bufi(.I(GE_125MHz_ref_ckpin), .O(GE_125MHz_ref_ckpin_buf));
wire GE_125MHz_ref_ck_locked;
DCM #(
.CLKIN_PERIOD(8.0), // Specify period of input clock in ns
.CLKFX_MULTIPLY(5),
.CLKFX_DIVIDE(8)
) GE_125MHz_ref_ck_DCMi(
.CLK0(GE_125MHz_ref_ck_unbuf),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(GE_125MHz_ref_ck_locked),
.PSDONE(),
.STATUS(),
.CLKFB(GE_125MHz_ref_ck),
.CLKIN(GE_125MHz_ref_ckpin_buf),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(reset_pin)
);
//----------------------------------------------------------------------------
// 125MHz refence clock
//----------------------------------------------------------------------------
`ifdef MODEL_TECH
BUFG GE_125MHz_ref_ck_bufi(.I(GE_125MHz_ref_ck_unbuf), .O(GE_125MHz_ref_ck));
`else
BUFGMUX GE_125MHz_ref_ck_bufi(.I1(GE_125MHz_ref_ck_unbuf), .O(GE_125MHz_ref_ck), .S(1'b1));
`endif
//----------------------------------------------------------------------------
// Fibre-Optic (FO) TBI RX clock.
//----------------------------------------------------------------------------
IBUFG tbi_rx_ckpin_bufi(.I(tbi_rx_ckpin), .O(tbi_rx_ckpin_buf));
DCM #(
.CLKIN_PERIOD(8.0)
) tbi_rx_ck_DCMi(
.CLK0(tbi_rx_ck_unbuf),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(tbi_rx_ck_locked),
.PSDONE(),
.STATUS(),
.CLKFB(tbi_rx_ck),
.CLKIN(tbi_rx_ckpin_buf),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(reset_pin)
);
// FO TBI 125MHz rx clock
BUFG tbi_rx_ck_bufi( .I(tbi_rx_ck_unbuf), .O(tbi_rx_ck));
//----------------------------------------------------------------------------
// Reset Cleaners
//----------------------------------------------------------------------------
wire main_clocks_locked = GE_125MHz_ref_ck_locked;
wire tbi_rxck_reset_in = reset_pin | ~main_clocks_locked;
wire GE_125MHz_reset_in = reset_pin | ~main_clocks_locked;
wire mdc_reset_in = reset_pin | ~main_clocks_locked;
wire GE_125MHz_reset, tbi_rx_reset;
clean_rst GE_125MHz_reset_cleaneri(.clk(GE_125MHz_ref_ck), .rsti(GE_125MHz_reset_in), .rsto(GE_125MHz_reset));
clean_rst tbi_rx_reset_cleaneri( .clk(tbi_rx_ck), .rsti(tbi_rxck_reset_in), .rsto(tbi_rx_reset));
clean_rst mdc_reset_cleaneri( .clk(mdc), .rsti(mdc_reset_in), .rsto(mdc_reset));
//-------------------------------------------------------------------------------
// --- IEEE 802.3-2008 1000baseX PCS ---
//-------------------------------------------------------------------------------
ge_1000baseX ge_1000baseX_i(
// --- Clocks ---
.rx_ck(tbi_rx_ck), .tx_ck(GE_125MHz_ref_ck),
// --- resets ---
.tx_reset(GE_125MHz_reset), .rx_reset(tbi_rx_reset),
// --- Startup interface. ---
.startup_enable(~GE_125MHz_reset),
// --- Signal detect from FO transceiver
.signal_detect(signal_detect),
// --- Receive GMII bus ---
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_col(gmii_col),
.gmii_cs(gmii_cs),
// --- Transmit GMII bus ---
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.gmii_txd(gmii_txd),
// --- Receive 8B10B bus ---
.tbi_rxd(tbi_rxd),
// --- Transmit 8B10B bus ---
.tbi_txd(tbi_txd),
// --- Mode of operation ---
.repeater_mode(1'b0),
// --- MDIO interface ---
.mdc_reset(mdc_reset),
.mdc(mdc),
.mdio(mdio)/* synthesis xc_pullup = 1 */
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; int n, k, x, y; set<pair<int, int> > s; vector<pair<int, int> > a[MAXN]; vector<int> ans; inline void start() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &y); a[x].push_back({y, i}); } } inline void solve() { for (int i = 1; i <= 2e5 + 1; i++) { for (int j = 0; j < a[i].size(); j++) s.insert(a[i][j]); while (s.size() > k) { ans.push_back((--s.end())->second); s.erase(--s.end()); } while (!s.empty() && s.begin()->first == i) s.erase(s.begin()); } sort(ans.begin(), ans.end()); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]); puts( ); } int main() { start(); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int N, M; int Candidates[100]; int main() { cin >> N >> M; for (int i = 0; i < M; i++) { int MaxVotesNum = -1; int idx = -1; for (int j = 0; j < N; j++) { int Temp; cin >> Temp; if (MaxVotesNum < Temp) { MaxVotesNum = Temp; idx = j; } } Candidates[idx]++; } cout << (max_element(Candidates, Candidates + 100) - Candidates) + 1 << endl; }
|
module rgb_led
(
pclk,
nreset,
bus_write_en,
bus_read_en,
bus_addr,
bus_write_data,
bus_read_data,
pwm_r, pwm_g, pwm_b
);
`define HZ_PER_COLOR_DIVISION 16'd3921
// 100Hz pwm
`define PWM_PERIOD 32'd1000000
// bus lines
input pclk, nreset, bus_write_en, bus_read_en;
input [7:0] bus_addr;
input [31:0] bus_write_data;
output reg [31:0] bus_read_data;
output reg pwm_r, pwm_g, pwm_b;
// counts to PWM_PERIOD
reg [31:0] duty_cycle_counter;
reg [31:0] brightness;
reg [31:0] brightness_factor;
reg [7:0] delta_brightness;
// led state registers
// the led toggles between state 1 and state 2
reg [31:0] led_control;
// 0x En (Enabled bit) P (pulse_rate) RR GG BB
reg [31:0] pending_led_state_1;
reg [31:0] pending_led_state_2;
reg [31:0] led_state_1;
reg [31:0] led_state_2;
// which led state are we in?
reg [31:0] current_state;
reg enabled;
reg pulse;
reg red;
reg green;
reg blue;
always@(posedge pclk)
if(~nreset)
begin
pending_led_state_1 <= 32'h00000000;
pending_led_state_2 <= 32'h00000000;
end
else begin
if(bus_write_en) begin : WRITE
case(bus_addr[3:2])
2'b00: // led_control
begin
led_control <= bus_write_data;
end
2'b01: // pending_led_state_1
begin
pending_led_state_1 <= bus_write_data;
end
2'b10: // pending_led_state_2
begin
pending_led_state_2 <= bus_write_data;
end
endcase
end
else if(bus_read_en) begin : READ
case(bus_addr[3:2])
2'b00: // led_control
begin
bus_read_data <= led_control;
end
2'b01: // pending_led_state_1
begin
bus_read_data <= pending_led_state_1;
end
2'b10: // pending_led_state_2
begin
bus_read_data <= pending_led_state_2;
end
endcase
end
end
always@(posedge pclk) begin
enabled <= current_state[31];
pulse <= current_state[30:24];
red <= current_state[23:16];
green <= current_state[15:8];
blue <= current_state[7:0];
end
// changing global brightness
always@(posedge pclk) begin
if(brightness == 32'd100000000) begin
delta_brightness = -1;
end
else begin
if(brightness == 32'd0) begin
delta_brightness = 1;
end
else begin
brightness = brightness + delta_brightness;
end
end
brightness_factor <= ((`HZ_PER_COLOR_DIVISION * brightness) / 32'd100000000);
end
// pulsing colors based on global brightness
always@(posedge pclk) begin
if(~nreset)begin
led_state_1 <= 32'h00000000;
led_state_2 <= 32'h00000000;
pwm_r <= 0;
pwm_g <= 0;
pwm_b <= 0;
end
else begin
duty_cycle_counter <= duty_cycle_counter + 1;
if(duty_cycle_counter == `PWM_PERIOD) begin
duty_cycle_counter <= 0;
end
else begin
//turn off signals that have reached their duty cycle
if(red * brightness_factor == duty_cycle_counter) begin
pwm_r <= 0;
end
if(blue * brightness_factor == duty_cycle_counter) begin
pwm_b <= 0;
end
if(green * brightness_factor == duty_cycle_counter) begin
pwm_g <= 0;
end
end
// "overflow" of the pwm counter, so start a new duty cycle
if(duty_cycle_counter == 0)begin
// toggle state
if(current_state == led_state_1)begin
current_state <= led_state_2;
end
else begin
current_state <= led_state_1;
end
led_state_1 <= pending_led_state_1;
led_state_2 <= pending_led_state_2;
//turn on all pwm signals
//TODO only if they are non-zero values
pwm_r <= 1;
pwm_g <= 1;
pwm_b <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; bool impr = false; bool taken[n + 1]; for (int i = 0; i <= n; i++) { taken[i] = false; } int notTaken = -1; for (int i = 0; i < n; i++) { int k; cin >> k; bool done = false; for (int i = 0; i < k; i++) { int next; cin >> next; if (!done && !taken[next]) { taken[next] = true; done = true; } } if (!done) { impr = true; notTaken = i + 1; } } if (impr) { cout << IMPROVE << endl; int good = 0; for (int i = 1; i <= n; i++) { if (taken[i] == false) { good = i; } } cout << notTaken << << good << endl; } else { cout << OPTIMAL << endl; } } }
|
//#############################################################################
//# Function: 4:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux4 #(parameter DW = 1 ) // width of mux
(
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0]);
`ifdef TARGET_SIM
wire error;
assign error = (sel0 | sel1 | sel2 | sel3) &
~(sel0 ^ sel1 ^ sel2 ^ sel3);
always @ (posedge error)
begin
#1 if(error)
$display ("ERROR at in oh_mux4 %m at ",$time);
end
`endif
endmodule // oh_mux4
|
#include <bits/stdc++.h> using namespace std; int n, k; char playLog[1111]; char posLet[3] = { W , D , L }; int delta[3] = {1, 0, -1}; int val[256]; char dp[1111][2222]; void clearArray() { for (int i = 0; i <= n + 1; i++) { for (int j = -k; j <= k; j++) dp[i][j + k] = X ; } } void printAnswer() { int currentState = 0; for (int i = 0; i < n; i++) { char thisOne = dp[i][currentState + k]; printf( %c , thisOne); currentState += val[thisOne]; } printf( n ); } int main() { val[ W ] = 1; val[ D ] = 0; val[ L ] = -1; scanf( %d%d , &n, &k); scanf( %s , playLog); clearArray(); dp[n][k + k] = P ; for (int i = n - 1; i >= 0; i--) { for (int j = -(k - 1); j <= (k - 1); j++) { for (int q = 0; q < 3; q++) { if (playLog[i] != ? && (playLog[i] != posLet[q])) continue; int target = j + delta[q]; if (dp[i + 1][target + k] == X ) continue; dp[i][j + k] = posLet[q]; break; } } } if (dp[0][0 + k] != X ) { printAnswer(); return 0; } clearArray(); dp[n][0] = P ; for (int i = n - 1; i >= 0; i--) { for (int j = -(k - 1); j <= (k - 1); j++) { for (int q = 0; q < 3; q++) { if (playLog[i] != ? && (playLog[i] != posLet[q])) continue; int target = j + delta[q]; if (dp[i + 1][target + k] == X ) continue; dp[i][j + k] = posLet[q]; break; } } } if (dp[0][0 + k] != X ) { printAnswer(); return 0; } printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int INF = 0x3f3f3f3f; const int inf = -INF; const int mod = 1e9 + 7; const double pi = acos(-1.0); string s; int pre[N]; int dp[N][2]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int T; cin >> T; while (T--) { int n, k; cin >> n >> k; cin >> s; pre[0] = 0; for (int i = 0; i <= n; i++) { dp[i][0] = dp[i][1] = 0; } s = + s; for (int i = 1; i <= n; i++) pre[i] = pre[i - 1] + s[i] - 0 ; for (int i = 1; i <= n; i++) { int t = max(0, i - k); dp[i][0] = min(dp[i - 1][0], dp[i - 1][1]) + (s[i] == 1 ); dp[i][1] = min(pre[i - 1], dp[t][1] + pre[i - 1] - pre[t]) + (s[i] == 0 ); } int ans = min(dp[n][0], dp[n][1]); cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[3500]; int main(void) { int c; scanf( %d n , &c); for (int t = 0; t < c; t++) { int n, m, k; scanf( %d %d %d n , &n, &m, &k); for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); } scanf( n ); vector<int> v; for (int i = 0; i < m; i++) { v.push_back(max(arr[i], arr[i + n - m])); } if (k >= m) { k = m - 1; } int ret = 0; for (int i = 0; i <= k; i++) { int mini = 2e9; for (int j = i; j < i + m - k; j++) { mini = min(v[j], mini); } ret = max(ret, mini); } printf( %d n , ret); } }
|
#include <bits/stdc++.h> using namespace std; char str[1000]; int main() { int n, k; while (scanf( %d %d , &n, &k) == 2) { scanf( %s , str + 1); int left = k - 1; int right = n - k; int di; if (right >= left) { di = 1; for (int i = k; i > 1; i--) printf( LEFT n ); } else { di = 2; for (int i = k; i < n; i++) printf( RIGHT n ); } if (di == 1) { for (int i = 1; i <= n; i++) { printf( PRINT %c n , str[i]); if (i != n) printf( RIGHT n ); } } else { for (int i = n; i >= 1; i--) { printf( PRINT %c n , str[i]); if (i != 1) printf( LEFT n ); } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); if (a < b) { if (c < d) { if (d * a > b * c) printf( %d/%d n , (a * d - b * c) / gcd(a * d - b * c, a * d), a * d / gcd(a * d - b * c, a * d)); else printf( %d/%d n , (b * c - a * d) / gcd(b * c - a * d, b * c), b * c / gcd(b * c - a * d, b * c)); } else { printf( %d/%d n , (b * c - a * d) / gcd(b * c - a * d, b * c), b * c / gcd(b * c - a * d, b * c)); } } else { if (c < d) { printf( %d/%d n , (a * d - b * c) / gcd(a * d - b * c, a * d), a * d / gcd(a * d - b * c, a * d)); ; } else { if (d * a > b * c) printf( %d/%d n , (a * d - b * c) / gcd(a * d - b * c, a * d), a * d / gcd(a * d - b * c, a * d)); else printf( %d/%d n , (b * c - a * d) / gcd(b * c - a * d, b * c), b * c / gcd(b * c - a * d, b * c)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n + 2]; vector<int> s; s.push_back(n); for (int i = 2; i < n + 1; i++) cin >> arr[i]; arr[1] = 0; int k = n; while (k > 0) { s.push_back(arr[k]); k = arr[k]; } for (int i = s.size() - 2; i > -1; i--) { cout << s[i] << ; } return 0; }
|
#include <bits/stdc++.h> struct { inline operator int() { int x; return scanf( %d , &x), x; } inline operator long long() { long long x; return scanf( %lld , &x), x; } template <class T> inline void operator()(T &x) { x = *this; } template <class T, class... A> inline void operator()(T &x, A &...a) { x = *this; this->operator()(a...); } } read; const int maxn = 120005; long long his[maxn << 2]; int min[maxn << 2], tot[maxn << 2], mot[maxn << 2], pat[maxn << 2]; void modi(int now, int x) { min[now] += x; mot[now] += x; } void pass(int now, int x) { his[now] += 1ll * tot[now] * x; pat[now] += x; } void push(int now) { if (mot[now]) { modi((now << 1), mot[now]); modi((now << 1 | 1), mot[now]); mot[now] = 0; } if (pat[now]) { if (min[(now << 1)] == min[now]) pass((now << 1), pat[now]); if (min[(now << 1 | 1)] == min[now]) pass((now << 1 | 1), pat[now]); pat[now] = 0; } } void modify(int now, int L, int R, int l, int r, int x) { if (r < L or l > R) return; if (l <= L and R <= r) return modi(now, x); push(now); int M = (L + R) >> 1; modify((now << 1), L, M, l, r, x); modify((now << 1 | 1), M + 1, R, l, r, x); his[now] = his[(now << 1)] + his[(now << 1 | 1)]; min[now] = std::min(min[(now << 1)], min[(now << 1 | 1)]); tot[now] = 0; if (min[(now << 1)] == min[now]) tot[now] += tot[(now << 1)]; if (min[(now << 1 | 1)] == min[now]) tot[now] += tot[(now << 1 | 1)]; } long long query(int now, int L, int R, int l, int r) { if (r < L or l > R) return 0; if (l <= L and R <= r) return his[now]; push(now); int M = (L + R) >> 1; return query((now << 1), L, M, l, r) + query((now << 1 | 1), M + 1, R, l, r); } void build(int now, int L, int R) { min[now] = L; tot[now] = 1; if (L == R) return; int M = (L + R) >> 1; build((now << 1), L, M); build((now << 1 | 1), M + 1, R); } void test(int now, int L, int R) { if (L == R) { fprintf(stderr, %d , min[now]); return; } push(now); int M = (L + R) >> 1; test((now << 1), L, M); test((now << 1 | 1), M + 1, R); if (now == 1) fprintf(stderr, n ); } int a[maxn]; long long ans[maxn]; int st1[maxn], sp1; int st2[maxn], sp2; std::vector<std::pair<int, int> > v[maxn]; int main() { int n = read; for (int i = 1; i <= n; i++) read(a[i]); int q = read; for (int i = 1; i <= q; i++) { int l = read, r = read; v[r].push_back(std::pair<int, int>(l, i)); } build(1, 1, n); for (int r = 1; r <= n; r++) { while (sp2 and a[st2[sp2]] > a[r]) modify(1, 1, n, st2[sp2 - 1] + 1, st2[sp2], a[st2[sp2]]), --sp2; st2[++sp2] = r; modify(1, 1, n, st2[sp2 - 1] + 1, st2[sp2], -a[st2[sp2]]); while (sp1 and a[st1[sp1]] < a[r]) modify(1, 1, n, st1[sp1 - 1] + 1, st1[sp1], -a[st1[sp1]]), --sp1; st1[++sp1] = r; modify(1, 1, n, st1[sp1 - 1] + 1, st1[sp1], a[st1[sp1]]); modi(1, -1); pass(1, 1); for (std::pair<int, int> p : v[r]) ans[p.second] = query(1, 1, n, p.first, r); } for (int i = 1; i <= q; i++) printf( %lld n , ans[i]); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2e18 + 9; const long long MAXN = 1e6 + 7; const long long MAXN1 = 5e2 + 7; const long long MOD = 1e9 + 7; const long long ST = 157; const long long ST1 = 199; const long double EPS = 1e-9; const long long BLOCK = 138; void solve(); signed main() { srand( a + l + e + x + X + 5 + 1 + 2 ); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } void solve() { int n; cin >> n; vector<pair<long long, int>> v; for (int i = 0; i < n; i++) { long long l, r; cin >> l >> r; v.emplace_back(l, -1); v.emplace_back(r, 1); } sort(v.begin(), v.end()); vector<long long> ans(n + 1); int b = -1; for (int i = 1; i < 2 * n; i++) { if (v[i].second == -1) { if (v[i - 1].second == 1) { ans[-b] += v[i].first - v[i - 1].first - 1; } else { ans[-b] += v[i].first - v[i - 1].first; } } else { if (v[i].first != v[i - 1].first || v[i - 1].second == -1) { if (v[i - 1].second == 1) ans[-b] += v[i].first - v[i - 1].first; else ans[-b] += v[i].first - v[i - 1].first + 1; } } b += v[i].second; } for (int i = 1; i <= n; i++) { cout << ans[i] << ; } }
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string ss[100]; int n, ans = 0, cur; cin >> n; for (int i = 0; i < n; i++) cin >> ss[i]; for (char a = a ; a <= z ; a++) for (char b = a ; b <= z ; b++) { cur = 0; for (int i = 0; i < n; i++) { int l = ss[i].length(); bool ok = true; while (l--) { if (ss[i][l] != a && ss[i][l] != b) ok = false; } if (ok) cur += ss[i].length(); } ans = max(ans, cur); } cout << ans; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_in (
// data interface
rx_clk,
rx_data_in_p,
rx_data_in_n,
rx_data_p,
rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter BUFTYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input rx_clk;
input rx_data_in_p;
input rx_data_in_n;
output rx_data_p;
output rx_data_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg rx_data_n;
// internal signals
wire rx_data_n_s;
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
// delay controller
generate
if (IODELAY_CTRL == 1) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
if (BUFTYPE == VIRTEX6) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("ASYNC"))
i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n_s));
always @(posedge rx_clk) begin
rx_data_n <= rx_data_n_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> const int maxn = 400000 + 5; int f[maxn]; int n, m, q; int ans; inline int Read() { register int ret; register char r; register bool f = false; while (r = getchar(), r < 0 || r > 9 ) if (r == - ) f = true; ret = r - 48; while (r = getchar(), r >= 0 && r <= 9 ) ret = (ret << 3) + (ret << 1) + r - 48; return f ? ~ret + 1 : ret; } inline int Find(int x) { return x == f[x] ? x : f[x] = Find(f[x]); } int main() { n = Read(); m = Read(); q = Read(); for (register int i = n + m; i; i--) f[i] = i; for (register int i = 1; i <= q; i++) { int x = Find(Read()), y = Find(Read() + n); if (x != y) f[x] = y; } for (register int i = n + m; i; i--) ans += (Find(i) == i); printf( %d n , ans - 1); return 0; }
|
module top;
parameter seeq1 = 6'sb111000 === 4'sb1000;
parameter seeqx = 6'sbxxx000 === 4'sbx000;
parameter seeqz = 6'sbzzz000 === 4'sbz000;
parameter seq1 = 6'sb111000 == 4'sb1000;
parameter seqx = 6'sbxxx000 == 4'sbx000;
parameter seqz = 6'sbzzz000 == 4'sbz000;
reg pass;
initial begin
pass = 1'b1;
if (seeq1 !== 1'b1) begin
$display("FAILED: signed === (1), got %b", seeq1);
pass = 1'b0;
end
if (seeqx !== 1'b1) begin
$display("FAILED: signed === (x), got %b", seeqx);
pass = 1'b0;
end
if (seeqz !== 1'b1) begin
$display("FAILED: signed === (z), got %b", seeqz);
pass = 1'b0;
end
if (seq1 !== 1'b1) begin
$display("FAILED: signed == (1), got %b", seq1);
pass = 1'b0;
end
if (seqx !== 1'bx) begin
$display("FAILED: signed == (x), got %b", seqx);
pass = 1'b0;
end
if (seqz !== 1'bx) begin
$display("FAILED: signed == (z), got %b", seqz);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 7; int clr[MAX] = {0}, vis[MAX] = {0}, res = 0; vector<int> adj[MAX]; void dfs(int u, int p, int clr_p) { int f = 0; if (!vis[clr[u]]) { f = 1; vis[clr[u]] = 1; res++; } else if (p != -1 && clr_p != clr[u]) res++; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (p == v) continue; dfs(v, u, clr[u]); } if (f) vis[clr[u]] = 0; } int main(int argc, char const *argv[]) { int n, x; cin >> n; for (int i = 2; i <= n; i++) { cin >> x; adj[i].push_back(x); adj[x].push_back(i); } for (int i = 1; i <= n; i++) cin >> clr[i]; dfs(1, -1, -1); std::cout << res << n ; return 0; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.91
// \ \ Application: MIG
// / / Filename: phy_read.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Top-level module for PHY-layer read logic
// 1. Read clock (capture, resync) generation
// 2. Synchronization of control from MC into resync clock domain
// 3. Synchronization of data/valid into MC clock domain
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_read.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_read.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_read #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name
// when mult IP cores in design
parameter nDQS_COL0 = 4, // # DQS groups in I/O column #1
parameter nDQS_COL1 = 4, // # DQS groups in I/O column #2
parameter nDQS_COL2 = 0, // # DQS groups in I/O column #3
parameter nDQS_COL3 = 0, // # DQS groups in I/O column #4
parameter DQS_LOC_COL0 = 32'h03020100, // DQS grps in col #1
parameter DQS_LOC_COL1 = 32'h07060504, // DQS grps in col #2
parameter DQS_LOC_COL2 = 0, // DQS grps in col #3
parameter DQS_LOC_COL3 = 0 // DQS grps in col #4
)
(
input clk_mem,
input clk,
input clk_rd_base,
input rst,
// Read clock generation/distribution signals
input dlyrst_cpt,
input [DQS_WIDTH-1:0] dlyce_cpt,
input [DQS_WIDTH-1:0] dlyinc_cpt,
input dlyrst_rsync,
input [3:0] dlyce_rsync,
input [3:0] dlyinc_rsync,
output [DQS_WIDTH-1:0] clk_cpt,
output [3:0] clk_rsync,
output [3:0] rst_rsync,
output rdpath_rdy,
// Control for command sync logic
input mc_data_sel,
input [4:0] rd_active_dly,
// Captured data in resync clock domain
input [DQ_WIDTH-1:0] rd_data_rise0,
input [DQ_WIDTH-1:0] rd_data_fall0,
input [DQ_WIDTH-1:0] rd_data_rise1,
input [DQ_WIDTH-1:0] rd_data_fall1,
input [DQS_WIDTH-1:0] rd_dqs_rise0,
input [DQS_WIDTH-1:0] rd_dqs_fall0,
input [DQS_WIDTH-1:0] rd_dqs_rise1,
input [DQS_WIDTH-1:0] rd_dqs_fall1,
// DFI signals from MC/PHY rdlvl logic
input dfi_rddata_en,
input phy_rddata_en,
// Synchronized data/valid back to MC/PHY rdlvl logic
output dfi_rddata_valid,
output dfi_rddata_valid_phy,
output [4*DQ_WIDTH-1:0] dfi_rddata,
output [4*DQS_WIDTH-1:0] dfi_rd_dqs,
// Debug bus
output [5*DQS_WIDTH-1:0] dbg_cpt_tap_cnt, // CPT IODELAY tap count
output [19:0] dbg_rsync_tap_cnt, // RSYNC IODELAY tap count
output [255:0] dbg_phy_read //general purpose debug
);
//***************************************************************************
// Assign signals for Debug Port
//***************************************************************************
// Currently no assignments - add as needed
assign dbg_phy_read = 'b0;
//***************************************************************************
// Read clocks (capture, resynchronization) generation
//***************************************************************************
phy_rdclk_gen #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQS_WIDTH (DQS_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3)
)
u_phy_rdclk_gen
(
.clk_mem (clk_mem),
.clk (clk),
.clk_rd_base (clk_rd_base),
.rst (rst),
.dlyrst_cpt (dlyrst_cpt),
.dlyce_cpt (dlyce_cpt),
.dlyinc_cpt (dlyinc_cpt),
.dlyrst_rsync (dlyrst_rsync),
.dlyce_rsync (dlyce_rsync),
.dlyinc_rsync (dlyinc_rsync),
.clk_cpt (clk_cpt),
.clk_rsync (clk_rsync),
.rst_rsync (rst_rsync),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_rsync_tap_cnt (dbg_rsync_tap_cnt)
);
//***************************************************************************
// Synchronization of read enable signal from MC/PHY rdlvl logic
//***************************************************************************
phy_rdctrl_sync #
(
.TCQ (TCQ)
)
u_phy_rdctrl_sync
(
.clk (clk),
.rst_rsync (rst_rsync[0]),
.mc_data_sel (mc_data_sel),
.rd_active_dly (rd_active_dly),
.dfi_rddata_en (dfi_rddata_en),
.phy_rddata_en (phy_rddata_en),
.dfi_rddata_valid (dfi_rddata_valid),
.dfi_rddata_valid_phy (dfi_rddata_valid_phy),
.rdpath_rdy (rdpath_rdy)
);
//***************************************************************************
// Synchronization of read data and accompanying valid signal back to MC/
// PHY rdlvl logic
//***************************************************************************
phy_rddata_sync #
(
.TCQ (TCQ),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3)
)
u_phy_rddata_sync
(
.clk (clk),
.clk_rsync (clk_rsync),
.rst_rsync (rst_rsync),
.rd_data_rise0 (rd_data_rise0),
.rd_data_fall0 (rd_data_fall0),
.rd_data_rise1 (rd_data_rise1),
.rd_data_fall1 (rd_data_fall1),
.rd_dqs_rise0 (rd_dqs_rise0),
.rd_dqs_fall0 (rd_dqs_fall0),
.rd_dqs_rise1 (rd_dqs_rise1),
.rd_dqs_fall1 (rd_dqs_fall1),
.dfi_rddata (dfi_rddata),
.dfi_rd_dqs (dfi_rd_dqs)
);
endmodule
|
// Single-Port BRAM with Byte-wide Write Enable
// Read-First mode
// Single-process description
// Compact description of the write with a generate-for
// statement
// Column width and number of columns easily configurable
//
// bytewrite_ram_32bits.v
//
// `timescale 1ns/1ps
module bytewrite_ram_32bits (clk, we, addr, din, dout);
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] din;
output [NB_COL*COL_WIDTH-1:0] dout;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
integer _i;
wire [ADDR_WIDTH-1:0] addr_dly;
reg [NB_COL*COL_WIDTH-1:0] dout_int;
initial begin
`ifndef NO_RAM_INIT
$readmemh(filename,RAM);
`endif
// #10;
// // Just for debugging readmemh in case it does not work as expected
// for(_i=0;_i<6;_i=_i+1) begin
// $display("idx : %d data : %x",_i,RAM[_i]);
// end
// $display("======================");
end
always @(posedge clk)
begin
dout_int <= RAM[addr];
// $display("%t -D- reading code rom : addr %x ",$realtime,addr);
end
// assign #60 dout = dout_int;
assign dout = dout_int;
// Remove the original generate statement to ease Xilinx memory bitstream patching
always @(posedge clk) begin
if (we[0]) begin
// $display("-I Write to address %x , data %x (%t)",addr,din,$realtime);
RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];
end
end
always @(posedge clk) begin
if (we[1])
RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];
end
always @(posedge clk) begin
if (we[2])
RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];
end
always @(posedge clk) begin
if (we[3])
RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];
end
endmodule
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module spi_ctrl
(
// General
clk_i,
rst_i,
// Memory interface
mem_address_o,
mem_data_o,
mem_data_i,
mem_rd_o,
mem_wr_o,
// SPI Access
spi_start_o,
spi_done_i,
spi_busy_i,
spi_data_i,
spi_data_o,
// Control
xfer_count_i,
xfer_address_i,
xfer_start_i,
xfer_rx_only_i,
xfer_done_o,
xfer_busy_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] MEM_ADDR_WIDTH = 18;
parameter [31:0] XFER_COUNT_WIDTH = 32;
parameter [31:0] TRANSFER_WIDTH = 8;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
output [(MEM_ADDR_WIDTH - 1):0] mem_address_o /*verilator public*/;
output [(TRANSFER_WIDTH - 1):0] mem_data_o /*verilator public*/;
input [(TRANSFER_WIDTH - 1):0] mem_data_i /*verilator public*/;
output mem_rd_o /*verilator public*/;
output mem_wr_o /*verilator public*/;
output spi_start_o /*verilator public*/;
input spi_done_i /*verilator public*/;
input spi_busy_i /*verilator public*/;
input [(TRANSFER_WIDTH - 1):0] spi_data_i /*verilator public*/;
output [(TRANSFER_WIDTH - 1):0] spi_data_o /*verilator public*/;
input [(XFER_COUNT_WIDTH - 1):0]xfer_count_i /*verilator public*/;
input [(MEM_ADDR_WIDTH - 1):0] xfer_address_i /*verilator public*/;
input xfer_start_i /*verilator public*/;
input xfer_rx_only_i /*verilator public*/;
output xfer_done_o /*verilator public*/;
output xfer_busy_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
parameter STATE_IDLE = 3'd0;
parameter STATE_READ = 3'd1;
parameter STATE_READWAIT = 3'd2;
parameter STATE_XFER = 3'd3;
parameter STATE_WRITE = 3'd4;
reg [2:0] reg_state;
reg [(XFER_COUNT_WIDTH - 1):0] reg_count;
reg [(XFER_COUNT_WIDTH - 1):0] reg_current;
reg [(MEM_ADDR_WIDTH - 1):0] reg_address;
reg reg_rx_only;
reg [(MEM_ADDR_WIDTH - 1):0] mem_address_o;
reg [(TRANSFER_WIDTH - 1):0] mem_data_o;
reg mem_rd_o;
reg mem_wr_o;
reg spi_start_o;
reg [(TRANSFER_WIDTH - 1):0] spi_data_o;
reg xfer_done_o;
reg xfer_busy_o;
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
mem_rd_o <= 1'b0;
mem_wr_o <= 1'b0;
mem_address_o <= {(MEM_ADDR_WIDTH - 0){1'b0}};
mem_data_o <= {(TRANSFER_WIDTH - 0){1'b0}};
xfer_done_o <= 1'b0;
xfer_busy_o <= 1'b0;
spi_start_o <= 1'b0;
spi_data_o <= {(TRANSFER_WIDTH - 0){1'b0}};
reg_count <= {(XFER_COUNT_WIDTH - 0){1'b0}};
reg_current <= {(XFER_COUNT_WIDTH - 0){1'b0}};
reg_address <= {(MEM_ADDR_WIDTH - 0){1'b0}};
reg_rx_only <= 1'b0;
reg_state <= STATE_IDLE;
end
else
begin
xfer_done_o <= 1'b0;
spi_start_o <= 1'b0;
mem_rd_o <= 1'b0;
mem_wr_o <= 1'b0;
case (reg_state)
//-------------------------------
// STATE_IDLE
//-------------------------------
STATE_IDLE :
begin
if ((xfer_start_i == 1'b1) & (xfer_count_i != 0))
begin
xfer_busy_o <= 1'b1;
reg_count <= xfer_count_i;
reg_current <= 32'h00000001;
reg_address <= xfer_address_i;
reg_rx_only <= xfer_rx_only_i;
reg_state <= STATE_READ;
end
else
xfer_busy_o <= 1'b0;
end
//-------------------------------
// STATE_READ
//-------------------------------
STATE_READ :
begin
mem_address_o <= reg_address;
mem_rd_o <= 1'b1;
reg_state <= STATE_READWAIT;
end
//-------------------------------
// STATE_READWAIT
//-------------------------------
STATE_READWAIT :
reg_state <= STATE_XFER;
//-------------------------------
// STATE_XFER
//-------------------------------
STATE_XFER :
begin
if (reg_rx_only == 1'b0)
spi_data_o <= mem_data_i;
else
spi_data_o <= {((TRANSFER_WIDTH - 1)-0+1- 0){1'b1}};
spi_start_o <= 1'b1;
reg_state <= STATE_WRITE;
end
//-------------------------------
// STATE_WRITE
//-------------------------------
STATE_WRITE :
begin
if (spi_done_i == 1'b1)
begin
mem_address_o <= reg_address;
mem_data_o <= spi_data_i;
mem_wr_o <= 1'b1;
if (reg_current == reg_count)
begin
xfer_done_o <= 1'b1;
reg_state <= STATE_IDLE;
end
else
begin
reg_address <= (reg_address + 1'b1);
reg_current <= (reg_current + 1'b1);
reg_state <= STATE_READ;
end
end
end
default :
;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> inline long long MAX2(long long a, long long int b) { return (a) > (b) ? (a) : (b); } inline long long MAX3(long long a, long long b, long long c) { return (a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)); } inline long long MIN2(long long a, long long b) { return (a) < (b) ? (a) : (b); } inline long long MIN3(long long a, long long b, long long c) { return (a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c)); } using namespace std; int n, a, b; int p[1000006]; pair<int, int> compute() { if (n % b == 0) return pair<int, int>(0, n / b); if (n % a == 0) return pair<int, int>(n / a, 0); int div = (n / b); int rem = (n % b); int ch; while (div > 0) { ch = rem % a; if (ch == 0) break; div--; rem += b; } if (div == 0) return pair<int, int>(-1, -1); return pair<int, int>((rem / a), div); } void make(int i, int j) { int k; for (k = i; k < j; k++) { p[k] = k + 1; } p[j] = i; } int main() { cin >> n >> a >> b; if (a > b) { int temp = a; a = b; b = temp; } pair<int, int> cycles = compute(); if (cycles.first == -1) { cout << -1; return 0; } int i = 1; while (i <= n) { if (cycles.first > 0) { make(i, i + a - 1); cycles.first--; i += a; } else { make(i, i + b - 1); cycles.second--; i += b; } } for (i = 1; i < n + 1; i++) { cout << p[i] << ; } }
|
`timescale 1ns/1ps
module test_spi;
reg clk;
reg spi_rd_slave_rst_b2b;
reg ss_rd_sck_b2b;
reg ss_rd_mosi_b2b;
wire ss_rd_miso_b2b;
reg ss_rd_ssel_b2b;
wire recived_status;
integer i;
spi_slave_b2b_reduced spi_slave_b2b_instance_reduced(
.clk(clk),
.sck(ss_rd_sck_b2b),
.mosi(ss_rd_mosi_b2b),
.miso(ss_rd_miso_b2b),
.ssel(ss_rd_ssel_b2b),
.rst_n(spi_rd_slave_rst_b2b),
.recived_status(recived_status)
);
initial
begin
spi_rd_slave_rst_b2b = 0;
clk = 0;
ss_rd_mosi_b2b = 0;
ss_rd_ssel_b2b = 1;
ss_rd_sck_b2b = 0;
#10 spi_rd_slave_rst_b2b = 1;
//chip select active low
#10 ss_rd_ssel_b2b = 1'b0;
for (i=0; i< 32; i=i+1) begin
//bit 0
#25 ss_rd_mosi_b2b = 1'b1;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
//bit 1
#25 ss_rd_mosi_b2b = 1'b0;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
//bit 2
#25 ss_rd_mosi_b2b = 1'b1;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
//bit 3
#25 ss_rd_mosi_b2b = 1'b0;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
//bit 4
#25 ss_rd_mosi_b2b = 1'b1;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
//bit 5
#25 ss_rd_mosi_b2b = 1'b0;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
// bit 6
#25 ss_rd_mosi_b2b = 1'b1;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
//bit 7
#25 ss_rd_mosi_b2b = 1'b0;
#25 ss_rd_sck_b2b = 1'b1;
#50 ss_rd_sck_b2b = 1'b0;
end
$stop;
end
always begin
//50M HZ about 20ns one cycle
#10 clk = ! clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200010]; int base; int n, tmp; int main() { cin >> n; cin >> base; a[100000]++; for (int i = 1; i <= n - 1; i++) { cin >> tmp; int offset = tmp - base; if (abs(offset) > 100000) { cout << NO << endl; return 0; } a[offset + 100000]++; } int ub = 100000, lb = 100000; int cnt = n + a[100000]; while (a[ub]) { cnt -= a[ub]; ub++; } while (a[lb]) { cnt -= a[lb]; lb--; } lb++; ub--; if (cnt != 0) { cout << NO ; return 0; } for (int i = lb + 1; i <= ub - 1; i++) { if (a[i] < 2) { cout << NO ; return 0; } a[i] -= 2; } a[lb]--; a[ub]--; for (int i = lb; i <= ub; i++) { if (a[i + 1] < a[i]) { cout << NO ; return 0; } a[i + 1] -= a[i]; } cout << YES ; }
|
// $Id: c_mat_mult.v 1854 2010-03-24 03:12:03Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// matrix multiplication in GF(2)
module c_mat_mult
(input_a, input_b, result);
// matrix dimensions
parameter dim1_width = 1;
parameter dim2_width = 1;
parameter dim3_width = 1;
// first input matrix
input [0:dim1_width*dim2_width-1] input_a;
// second input matrix
input [0:dim2_width*dim3_width-1] input_b;
output [0:dim1_width*dim3_width-1] result;
wire [0:dim1_width*dim3_width-1] result;
generate
genvar row;
for(row = 0; row < dim1_width; row = row + 1)
begin:rows
genvar col;
for(col = 0; col < dim3_width; col = col + 1)
begin:cols
wire [0:dim2_width-1] products;
genvar idx;
for(idx = 0; idx < dim2_width; idx = idx + 1)
begin:idxs
assign products[idx]
= input_a[row*dim2_width+idx] &
input_b[idx*dim3_width+col];
end
assign result[row*dim3_width+col] = ^products;
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MXN = 2000010; int N, M; int A[MXN], B[MXN], T[32] = {}; void init() { scanf( %d%d , &N, &M); for (int i = 1; i <= N; i++) scanf( %d , A + i); for (int i = 1; i <= M; i++) scanf( %d , B + i), T[B[i]]++; } namespace solve { long long answer = 0; int sat[MXN], m = 0, p = 1; void solve() { for (int b = 30; b >= 0; b--) { for (int i = 1; i <= N; i++) { int x = min(T[b], A[i] >> b); A[i] -= x << b; T[b] -= x; for (int i = 0; i < x; i++) sat[++m] = b; } while (T[b] && p <= m && sat[p] > b) { A[++N] = 1 << sat[p++]; int x = min(T[b], A[N] >> b); A[N] -= x << b; T[b] -= x; for (int i = 0; i < x; i++) sat[++m] = b; } } cout << m - p + 1 << endl; } } // namespace solve int main() { init(); solve::solve(); return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_iobuf16 (
input [15:0] T,
input [15:0] I,
output [15:0] O,
inout [15:0] IO
);
IOBUF iobuf0(
.T(T[0]),
.I(I[0]),
.O(O[0]),
.IO(IO[0])
);
IOBUF iobuf1(
.T(T[1]),
.I(I[1]),
.O(O[1]),
.IO(IO[1])
);
IOBUF iobuf2(
.T(T[2]),
.I(I[2]),
.O(O[2]),
.IO(IO[2])
);
IOBUF iobuf3(
.T(T[3]),
.I(I[3]),
.O(O[3]),
.IO(IO[3])
);
IOBUF iobuf4(
.T(T[4]),
.I(I[4]),
.O(O[4]),
.IO(IO[4])
);
IOBUF iobuf5(
.T(T[5]),
.I(I[5]),
.O(O[5]),
.IO(IO[5])
);
IOBUF iobuf6(
.T(T[6]),
.I(I[6]),
.O(O[6]),
.IO(IO[6])
);
IOBUF iobuf7(
.T(T[7]),
.I(I[7]),
.O(O[7]),
.IO(IO[7])
);
IOBUF iobuf8(
.T(T[8]),
.I(I[8]),
.O(O[8]),
.IO(IO[8])
);
IOBUF iobuf9(
.T(T[9]),
.I(I[9]),
.O(O[9]),
.IO(IO[9])
);
IOBUF iobuf10(
.T(T[10]),
.I(I[10]),
.O(O[10]),
.IO(IO[10])
);
IOBUF iobuf11(
.T(T[11]),
.I(I[11]),
.O(O[11]),
.IO(IO[11])
);
IOBUF iobuf12(
.T(T[12]),
.I(I[12]),
.O(O[12]),
.IO(IO[12])
);
IOBUF iobuf13(
.T(T[13]),
.I(I[13]),
.O(O[13]),
.IO(IO[13])
);
IOBUF iobuf14(
.T(T[14]),
.I(I[14]),
.O(O[14]),
.IO(IO[14])
);
IOBUF iobuf15(
.T(T[15]),
.I(I[15]),
.O(O[15]),
.IO(IO[15])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[6]; int m[6]; int w[6]; int h, uh; int main() { x[0] = 500; for (int i = 0; i < 5; i++) { cin >> m[i]; if (i) x[i] = x[i - 1] + 500; } for (int i = 0; i < 5; i++) cin >> w[i]; cin >> h >> uh; int score = 0; for (int i = 0; i < 5; i++) { int bla = 3 * x[i] / 10; score += max(bla, (x[i] * (250 - m[i])) / 250 - 50 * w[i]); } cout << score + 100 * h - 50 * uh << endl; return 0; }
|
#include <iostream> #include <cmath> using namespace std; int t, n, a[105]; int main(){ cin>>t; while(t--){ cin>>n; int suc = 0; for(int i=0; i<n; i++) cin>>a[i]; for(int i=0; i<n; i++){ int k = (int)sqrt((double)a[i]); if(k*k != a[i]){ suc = 1; break; } } if(suc) cout<< YES <<endl; else cout<< NO <<endl; } return 0; }
|
`timescale 1ns / 1ps
/**************************************************************/
/* _____ _ _ */
/* | ____|_ __ ___ _ __ __ _ _ _| | __ _| |__ ___ */
/* | _| | '_ \ / _ \ '__/ _` | | | | | / _` | '_ \/ __| */
/* | |___| | | | __/ | | (_| | |_| | |__| (_| | |_) \__ \ */
/* |_____|_| |_|\___|_| \__, |\__, |_____\__,_|_.__/|___/ */
/* |___/ |___/ */
/**************************************************************/
/* Por: Lucas Teske - lucas at teske dot com dot br */
/* See link below for more info */
/* https://github.com/racerxdl/SuperINT */
/**************************************************************/
module FrequencyCounter(
input clk,
input freqin,
output [23:0] frequency
);
parameter SecondCount = ; // Number of cycles of clk to 1 second
reg [23:0] counter = 0; // Counter for input freqin
reg [23:0] freq = 0; // Last frequency value
reg [23:0] secondcounter = 0; // Counter to one second
reg stopin = 0; // Stop Input Counter
reg inreseted = 0; // Reset Input Counter
always @(posedge clk)
begin
if(secondcounter == SecondCount)
begin
secondcounter <= 0;
stopin <= 1;
freq <= counter*2;
end
else
if(~stopin)
secondcounter <= secondcounter + 1;
if(inreseted)
stopin <= 0;
end
always @(negedge freqin)
begin
if(~stopin)
begin
counter <= counter + 1;
inreseted <= 0;
end
else
begin
counter <= 0;
inreseted <= 1;
end
end
assign frequency = freq;
endmodule
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//COPY ME, CUSTOMIZE ME...
//The following module effects the IO of the DUC chain.
//By default, this entire module is a simple pass-through.
//To implement DSP logic before the DUC:
//Implement custom DSP between baseband and duc input.
//To implement DSP logic after the DUC:
//Implement custom DSP between duc output and frontend.
//To bypass the DUC with custom logic:
//Implement custom DSP between baseband and frontend.
module custom_dsp_tx
#(
//frontend bus width
parameter WIDTH = 24
)
(
//control signals
input clock, //dsp clock
input reset, //active high synchronous reset
input clear, //active high on packet control init
input enable, //active high when streaming enabled
//user settings bus, controlled through user setting regs API
input set_stb, input [7:0] set_addr, input [31:0] set_data,
//full rate outputs directly to the TX frontend
output [WIDTH-1:0] frontend_i,
output [WIDTH-1:0] frontend_q,
//full rate outputs directly from the DUC chain
input [WIDTH-1:0] duc_out_i,
input [WIDTH-1:0] duc_out_q,
//strobed samples {I16,Q16} to the TX DUC chain
output [31:0] duc_in_sample,
input duc_in_strobe, //this is a backpressure signal
output duc_in_enable, //enables DUC module
//strobbed baseband samples {I16,Q16} to this module
input [31:0] bb_sample,
output bb_strobe //this is a backpressure signal
);
assign frontend_i = duc_out_i;
assign frontend_q = duc_out_q;
assign duc_in_sample = bb_sample;
assign bb_strobe = duc_in_strobe;
assign duc_in_enable = enable;
endmodule //custom_dsp_tx
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR3_FUNCTIONAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_FUNCTIONAL_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Wed Apr 13 17:20:49 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FiFo/FiFo_stub.v
// Design : FiFo
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
module FiFo(clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,din[7:0],wr_en,rd_en,dout[7:0],full,empty" */;
input clk;
input [7:0]din;
input wr_en;
input rd_en;
output [7:0]dout;
output full;
output empty;
endmodule
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#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int x, i = 1; while (i <= n) { scanf( %d , &x); printf( n%d %d , 1, x - 1); i++; } }
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