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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, cnt = 0; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a.rbegin(), a.rend()); for (int i = 0; i < n; i++) { if (cnt < a[i]) { cnt++; } else { break; } } cout << cnt << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100 + 20; const int LG = 15; int a[N], cnt[N]; map<vector<int>, int> mp; int main() { ios::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; cnt[i] = __builtin_popcount(a[i]); } for (int mask = 0; mask < (1 << LG); mask++) { vector<int> vec(n + 20, 0); for (int i = 0; i < n; i++) { for (int j = 0; j < LG; j++) { if (!((mask >> j) & 1)) continue; vec[i] += (((a[i] >> j) & 1) ? -1 : 1); } vec[i] += cnt[i]; } mp[vec] = mask; } for (int mask = 0; mask < (1 << 30); mask += (1 << LG)) { vector<int> vec(n + 20, 0); for (int i = 0; i < n; i++) { for (int j = LG; j < 30; j++) { if (!((mask >> j) & 1)) continue; vec[i] += (((a[i] >> j) & 1) ? -1 : 1); } vec[i] *= -1; } for (int i = 0; i <= 30; i++) { auto it = mp.find(vec); if (it != mp.end()) return cout << (mask | it->second) << endl, 0; for (int j = 0; j < n; j++) vec[j]++; } } cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long arr[n + 2]; for (int i = 1; i <= n; i++) cin >> arr[i]; long long cume[n + 2], cumo[n + 2], rcume[n + 2], rcumo[n + 2]; cume[0] = 0; cumo[0] = 0; for (int i = 1; i <= n; i++) { if (i % 2) { cumo[i] = cumo[i - 1] + arr[i]; cume[i] = cume[i - 1]; } else { cume[i] = cume[i - 1] + arr[i]; cumo[i] = cumo[i - 1]; } } rcume[n + 1] = 0; rcumo[n + 1] = 0; for (int i = n; i >= 1; i--) { if (i % 2) { rcumo[i] = rcumo[i + 1] + arr[i]; rcume[i] = rcume[i + 1]; } else { rcume[i] = rcume[i + 1] + arr[i]; rcumo[i] = rcumo[i + 1]; } } long long ans = 0; for (int i = 1; i <= n; i++) { long long o = cumo[i - 1] + rcume[i + 1]; long long e = cume[i - 1] + rcumo[i + 1]; if (o == e) ans++; } cout << ans; return 0; }
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module tcm_mem_ram
(
// Inputs
input clk0_i
,input rst0_i
,input [ 13:0] addr0_i
,input [ 31:0] data0_i
,input [ 3:0] wr0_i
,input clk1_i
,input rst1_i
,input [ 13:0] addr1_i
,input [ 31:0] data1_i
,input [ 3:0] wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
//-----------------------------------------------------------------
// Dual Port RAM 64KB
// Mode: Read First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [16383:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i[0])
ram[addr0_i][7:0] <= data0_i[7:0];
if (wr0_i[1])
ram[addr0_i][15:8] <= data0_i[15:8];
if (wr0_i[2])
ram[addr0_i][23:16] <= data0_i[23:16];
if (wr0_i[3])
ram[addr0_i][31:24] <= data0_i[31:24];
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i[0])
ram[addr1_i][7:0] <= data1_i[7:0];
if (wr1_i[1])
ram[addr1_i][15:8] <= data1_i[15:8];
if (wr1_i[2])
ram[addr1_i][23:16] <= data1_i[23:16];
if (wr1_i[3])
ram[addr1_i][31:24] <= data1_i[31:24];
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long long T; cin >> T; while (T--) { long long n; cin >> n; long long i, j = 1; cout << 2 ; for (i = 1; i < n; i++) { j += 2; cout << j << ; } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int r, c, d[1020][1020], used[1020][1020]; string s[1020]; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; long long ans = 0; bool ok(int x, int y) { return x >= 0 && x < r && y >= 0 && y < c && s[x][y] != T ; } void bfs(int x, int y) { used[x][y] = 1; queue<pair<int, int> > q; q.push(make_pair(x, y)); d[x][y] = 0; while (q.empty() == false) { int xk = q.front().first, yk = q.front().second; q.pop(); for (int i = 0; i < 4; i++) { int xx = xk + dx[i]; int yy = yk + dy[i]; if (ok(xx, yy) == true && used[xx][yy] == 0) { used[xx][yy] = 1; d[xx][yy] = d[xk][yk] + 1; q.push(make_pair(xx, yy)); } } } } int main() { scanf( %d %d , &r, &c); int sx, sy, ex, ey; for (int i = 0; i < r; i++) { cin >> s[i]; for (int j = 0; j < c; j++) { if (s[i][j] == S ) { sx = i; sy = j; s[i][j] = 0 ; } else if (s[i][j] == E ) { ex = i; ey = j; s[i][j] = 0 ; } } } bfs(ex, ey); int need = d[sx][sy]; for (int i = 0; i < r; i++) { for (int j = 0; j < c; j++) { if (s[i][j] == T && i == sx && j == sy) continue; int add = (int)(s[i][j] - 0 ); if (d[i][j] <= need && d[i][j] != 0) { ans += add; } } } printf( %lld , ans); return 0; }
|
`default_nettype none
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [15:0] dout,
input wire [15:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn_from_memory,
input wire interrupt_request
);
reg interrupt_enable = 0;
wire interrupt = interrupt_request & interrupt_enable;
reg [4:0] rsp, rspN; // Return stack pointer
reg [4:0] dsp, dspN; // Data stack pointer
reg [15:0] st0, st0N; // Top of data stack
reg dstkW; // Data stack write
reg [13:0] pc, pcN; // Program Counter
wire [15:0] insn = interrupt ? 16'h5FFF : insn_from_memory; // Interrupt: Execute "Call 3FFE".
wire [13:0] pc_plus_1 = interrupt ? pc : pc + 14'd1; // Do not increment PC for interrupts to continue later at the same location.
wire fetch = pc[13] & ~interrupt; // Memory fetch data on pc[13] only valid if this is no interrupt entry.
reg rstkW; // Return stack write
wire [15:0] rstkD; // Return stack write value
reg notreboot = 0;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [15:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(32)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
stack2 #(.DEPTH(32)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
// wire [31:0] umstar = 0; // 43.51 MHz
wire [31:0] umstar = st0 * st1; // 36.00 MHz
// wire [31:0] umstar = st1 * st0; // 34.53 MHz
always @*
begin
// Compute the new value of st0
casez ({fetch, insn[15:8]})
9'b1_???_?????: st0N = insn_from_memory; // Memory fetch
9'b0_1??_?????: st0N = { 1'b0, insn[14:0] }; // Literal
9'b0_000_?????: st0N = st0; // Jump
9'b0_010_?????: st0N = st0; // Call
9'b0_001_?????: st0N = st1; // Conditional jump
9'b0_011_00000: st0N = st0; // TOS
9'b0_011_00001: st0N = st1; // NOS
9'b0_011_00010: st0N = st0 + st1; // +
9'b0_011_00011: st0N = st0 & st1; // and
9'b0_011_00100: st0N = st0 | st1; // or
9'b0_011_00101: st0N = st0 ^ st1; // xor
9'b0_011_00110: st0N = ~st0; // invert
9'b0_011_00111: st0N = {16{(minus == 0)}}; // =
9'b0_011_01000: st0N = {16{signedless}}; // <
9'b0_011_01001: st0N = {st0[15], st0[15:1]}; // 1 arshift
9'b0_011_01010: st0N = {st0[14:0], 1'b0}; // 1 lshift
9'b0_011_01011: st0N = rst0; // r@
9'b0_011_01100: st0N = minus[15:0]; // -
9'b0_011_01101: st0N = io_din; // Read IO
9'b0_011_01110: st0N = {11'b0, dsp}; // depth
9'b0_011_01111: st0N = {16{(minus[16])}}; // u<
// Specials available on HX8K:
9'b0_011_10000: st0N = st1 << st0; // lshift
9'b0_011_10001: st0N = st1 >> st0; // rshift
9'b0_011_10010: st0N = $signed(st1) >>> st0; // arshift
9'b0_011_10011: st0N = {11'b0, rsp}; // rdepth
9'b0_011_10100: st0N = umstar[15:0]; // Low um*
9'b0_011_10101: st0N = umstar[31:16]; // High um*
9'b0_011_10110: st0N = st0 + 1; // 1+
9'b0_011_10111: st0N = st0 - 1; // 1-
default: st0N = {16{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire func_dint = (insn[6:4] == 6);
wire func_eint = (insn[6:4] == 7);
wire is_alu = !fetch & (insn[15:13] == 3'b011);
assign mem_wr = notreboot & is_alu & func_write;
assign io_wr = notreboot & is_alu & func_iow;
assign io_rd = notreboot & is_alu & func_ior;
assign dout = st1;
wire eint = notreboot & is_alu & func_eint;
wire dint = notreboot & is_alu & func_dint;
wire interrupt_enableN = (interrupt_enable | eint) & ~dint;
// Value which could be written to return stack: Either return address in case of a call or TOS.
assign rstkD = (insn[13] == 1'b0) ? {1'b0, pc_plus_1, interrupt_enable} : st0;
always @*
begin
casez ({fetch, insn[15:13]}) // Calculate new data stack pointer
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01}; // Memory Fetch & Literal
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11}; // Conditional jump
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}}; // ALU
default: {dstkW, dspI} = {1'b0, 2'b00}; // Default: Unchanged
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({fetch, insn[15:13]}) // Calculate new return stack pointer
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11}; // Memory Fetch, triggered by high address bit set
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01}; // Call
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]}; // ALU
default: {rstkW, rspI} = {1'b0, 2'b00}; // Default: Unchanged
endcase
rspN = rsp + {rspI[1], rspI[1], rspI[1], rspI};
casez ({notreboot, fetch, insn[15:13], insn[7], |st0}) // New address for PC
7'b0_0_???_?_?: pcN = 0; // Boot: Start at address zero
7'b1_0_000_?_?,
7'b1_0_010_?_?,
7'b1_0_001_?_0: pcN = {1'b0, insn[12:0]}; // Jumps & Calls: Destination address
7'b1_1_???_?_?,
7'b1_0_011_1_?: pcN = rst0[14:1]; // Memory Fetch & ALU+exit: Return
default: pcN = pc_plus_1; // Default: Increment PC to next opcode
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
notreboot <= 0;
{ pc, dsp, rsp, st0, interrupt_enable} <= 0;
end else begin
notreboot <= 1;
{ pc, dsp, rsp, st0, interrupt_enable} <= { pcN, dspN, rspN, st0N, interrupt_enableN };
end
end
endmodule
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#include <bits/stdc++.h> const int N = 100010; int n; int head[N], to[2 * N], next[2 * N], graphmr; double ans; inline void add(int x, int y) { int p = graphmr++; to[p] = y; next[p] = head[x]; head[x] = p; } inline void dfs(int x, int fa, int dis) { ans += 1.0 / dis; for (int i = head[x]; ~i; i = next[i]) if (to[i] != fa) dfs(to[i], x, dis + 1); } int main() { scanf( %d , &n); memset(head, -1, sizeof head); for (int i = 1, x, y; i < n; i++) { scanf( %d%d , &x, &y); add(x, y); add(y, x); } dfs(1, 0, 1); printf( %lf n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int SCALE = 101; int g[SCALE * 2][SCALE * 2]; int tx, ty; int stepr[4] = {0, -1, 0, 1}; int stepc[4] = {-1, 0, 1, 0}; string s; bool BuildMap(const string& s) { int x = 0; int y = 0; memset(g, 0, sizeof(g)); g[(x + SCALE)][(y + SCALE)] = 1; for (int i = 0; i < s.size(); ++i) { int d = 0; switch (s[i]) { case L : d = 0; break; case U : d = 1; break; case R : d = 2; break; case D : d = 3; break; } x += stepr[d]; y += stepc[d]; if (g[(x + SCALE)][(y + SCALE)] == 1) { return false; } else { g[(x + SCALE)][(y + SCALE)] = 1; } } tx = x; ty = y; return true; } int Dfs(int x, int y, int cost) { if (x == tx && y == ty) return cost; int v = 10000; for (int i = 0; i < 4; ++i) { int tmpx = x + stepr[i]; int tmpy = y + stepc[i]; int& tmpg = g[(tmpx + SCALE)][(tmpy + SCALE)]; if (tmpg == 1) { tmpg = -1; int tv = Dfs(tmpx, tmpy, cost + 1); v = min(tv, v); tmpg = 1; } } return v; } bool CheckShort() { g[(0 + SCALE)][(0 + SCALE)] = -1; int cost = Dfs(0, 0, 0); if (cost < s.size() - 1) { return false; } return true; } int main() { while (cin >> s) { bool b = BuildMap(s); if (b == false) { cout << BUG << endl; continue; } b = CheckShort(); if (b == false) { cout << BUG << endl; continue; } cout << OK << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; string itoa(int x) { string s = ; char c; if (x < 0) x *= -1, s += - ; while (x) { c = x % 10 + 48; s += c; x /= 10; } if (s[0] == - ) reverse(s.begin() + 1, s.end()); else reverse(s.begin(), s.end()); if (s == ) s += 0 ; return s; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); priority_queue<int, vector<int>, greater<int> > pq; int n; cin >> n; string s, t, c; int x; vector<string> ans; while (n--) { cin >> s; if (s != removeMin ) { cin >> x; if (s == insert ) { pq.push(x); t = insert , c = itoa(x), t += c; ans.push_back(t); } else { while (!pq.empty() && pq.top() < x) { t = removeMin ; ans.push_back(t); pq.pop(); } if (pq.empty() || pq.top() > x) t = insert , c = itoa(x), t += c, ans.push_back(t), pq.push(x); t = getMin , c = itoa(x), t += c; ans.push_back(t); } } else { if (pq.empty()) t = insert 0 , ans.push_back(t), pq.push(0); t = removeMin , ans.push_back(t), pq.pop(); } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) cout << ans[i] << n ; }
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/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Terasic DE0 Nano SoC (Cyclone V SoC) Development Board
//
module de0_nano_soc
(
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
input [1:0] BUTTON,
input [3:0] SW,
output [7:0] LED,
output UART_TX,
input UART_RX,
output SPDR_TX,
input SPDR_RX
);
wire clk_50 = FPGA_CLK1_50;
wire clk_slow = FPGA_CLK2_50;
wire fpga_reset_n = BUTTON[0]; // NOTE: Debounced on board
wire irom_cs;
wire [23:0] irom_addr;
wire [31:0] irom_data;
irom irom
(
.clk(clk_50),
.addr(irom_addr),
.cs(irom_cs),
.dout(irom_data)
);
wire [31:0] dram_addr;
wire dram_cs;
wire dram_wr;
wire [3:0] dram_mask;
wire [31:0] dram_din;
wire [31:0] dram_dout;
dram dram
(
.clk(clk_50),
.addr(dram_addr),
.cs(dram_cs),
.wr(dram_wr),
.mask(dram_mask),
.din(dram_din),
.dout(dram_dout)
);
wire [68:0] rcn_00;
wire [68:0] rcn_01;
wire [68:0] rcn_02;
wire [68:0] rcn_03;
wire [68:0] rcn_04;
tawas #(.MASTER_ID(0)) tawas
(
.clk(clk_50),
.rst(!fpga_reset_n),
.ics(irom_cs),
.iaddr(irom_addr),
.idata(irom_data),
.dcs(dram_cs),
.dwr(dram_wr),
.daddr(dram_addr),
.dmask(dram_mask),
.dout(dram_din),
.din(dram_dout),
.rcn_in(rcn_00),
.rcn_out(rcn_01)
);
wire [31:0] test_progress;
wire [31:0] test_fail;
wire [31:0] test_pass;
rcn_testregs #(.ADDR_BASE(24'hFFFFF0)) testregs
(
.clk(clk_50),
.rst(!fpga_reset_n),
.test_progress(),
.test_progress(),
.test_pass(),
.rcn_in(rcn_01),
.rcn_out(rcn_02)
);
rcn_ram #(.ADDR_BASE(24'hFE0000)) sram_0
(
.clk(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_02),
.rcn_out(rcn_03)
);
wire uart_tx_req;
wire uart_rx_req;
rcn_uart #(.ADDR_BASE(24'hFFFFB8)) uart
(
.clk(clk_50),
.clk_50(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_03),
.rcn_out(rcn_04),
.tx_req(uart_tx_req),
.rx_req(uart_rx_req),
.uart_tx(UART_TX),
.uart_rx(UART_RX)
);
wire [68:0] rcn_20;
wire [68:0] rcn_21;
wire [68:0] rcn_22;
rcn_bridge_async #(.ID_MASK(6'h3C), .ID_BASE(6'h08),
.ADDR_MASK(24'hF00000), .ADDR_BASE(24'h100000)) bridge
(
.main_clk(clk_50),
.main_rst(!fpga_reset_n),
.sub_clk(clk_slow),
.main_rcn_in(rcn_04),
.main_rcn_out(rcn_00),
.sub_rcn_in(rcn_20),
.sub_rcn_out(rcn_21)
);
wire [31:0] spdr_gpo;
assign LED[7:0] = spdr_gpo[7:0];
rcn_spdr #(.MASTER_ID(9)) spdr
(
.clk(clk_slow),
.clk_50(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_21),
.rcn_out(rcn_22),
.gpi({28'd0, SW[3:0]}),
.gpi_strobe(),
.gpo(spdr_gpo),
.gpo_strobe(),
.uart_tx(SPDR_TX),
.uart_rx(SPDR_RX)
);
rcn_dma #(.ADDR_BASE(24'h1FFFC0), .MASTER_ID(8)) dma
(
.clk(clk_slow),
.rst(!fpga_reset_n),
.rcn_in(rcn_22),
.rcn_out(rcn_20),
.req({uart_rx_req, uart_tx_req, 14'd1}),
.done()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int cur = 1; long long num = 1; while (cur != n + 1) { if (cur != 1) cout << cur * 1ll * cur * 1ll * cur + 2 * cur * cur + 1; else cout << 2; cout << endl; cur++; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 10 <= 5) { cout << (n / 10) * 10; } else { cout << ((n / 10) + 1) * 10; } }
|
#include <bits/stdc++.h> using namespace std; int n; int a[101]; int dp[101][1 << 17]; int M[61]; vector<int> prime; bool isprime(int num) { int i; for (i = 2; i < num; ++i) { if (num % i == 0) return 0; } return 1; } void pre() { int i, j; for (i = 2; i < 60; ++i) { if (isprime(i)) prime.push_back(i); } memset(M, 0, sizeof(M)); for (i = 2; i <= 60; ++i) { for (j = 0; j < prime.size(); ++j) { if (i % prime[j] == 0) M[i] = M[i] + (1 << j); } } } vector<int> ans; int f(int pos, int mask) { int i; if (pos == n) return 0; else if (dp[pos][mask] != -1) return dp[pos][mask]; else { int tmp = INT_MAX; for (i = 1; i <= 2 * a[pos]; ++i) { if ((mask & M[i]) == 0) tmp = min(tmp, abs(a[pos] - i) + f(pos + 1, mask | M[i])); } return dp[pos][mask] = tmp; } } void rec(int pos, int mask) { int i; if (pos == n) return; else { for (i = 1; i <= 2 * a[pos]; ++i) { if ((mask & M[i]) != 0) continue; if (f(pos, mask) == (abs(a[pos] - i) + f(pos + 1, mask | M[i]))) { ans.push_back(i); rec(pos + 1, mask | M[i]); return; } } } } int main() { int i; pre(); cin >> n; for (i = 0; i < n; ++i) cin >> a[i]; memset(dp, -1, sizeof(dp)); rec(0, 0); for (i = 0; i < n; ++i) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n, greater<int>()); deque<int> d; d.push_front(arr[0]); int i; for (i = 1; i < n; i++) { if (arr[i] != arr[0]) break; } while (i < n) { int a = arr[i]; d.push_back(a); if (arr[i] == arr[i + 1]) d.push_front(a); for (; i < n; i++) { if (arr[i] != a) break; } } cout << d.size() << endl; while (d.size() > 0) { cout << d.front() << ; d.pop_front(); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5, maxm = 100010; int n, m, h[maxm][maxn], v[maxm][maxn]; long long f[maxm][1 << maxn]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m - 1; i++) for (int j = 0; j < n; j++) scanf( %d , &h[i][j]); for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) scanf( %d , &v[i][j]); for (int i = 1; i < 1 << n; i++) f[0][i] = 1LL << 60LL; f[0][0] = 0; for (int i = 1; i < m; i++) for (int opt = 0; opt < 1 << n; opt++) { f[i][opt] = 1LL << 60LL; long long s = 0; for (int j = 0; j < n; j++) s += ((opt & (1 << ((j + 1) % n))) > 0 != (opt & (1 << j)) > 0) * v[i][j]; for (int opt0 = 0; opt0 < 1 << n; opt0++) { long long ss = 0; for (int j = 0; j < n; j++) ss += ((opt & (1 << j)) != (opt0 & (1 << j))) * h[i - 1][j]; f[i][opt] = min(f[i][opt], f[i - 1][opt0] + s + ss); } } printf( %I64d n , f[m - 1][(1 << n) - 1]); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:30:00 10/31/2016
// Module Name: D_MEM
// Project Name: MIPS
// Description: The MIPS Data Memory (D_MEM) module in the MEMORY (MEM) stage.
//
// Dependencies: None.
//
////////////////////////////////////////////////////////////////////////////////
module D_MEM(input clk, MemWrite, MemRead, input [31:0] Address, Write_data,
output reg [31:0] Read_data);
reg [31:0] MEM [128:0];
initial
begin
MEM[0] <= 32'b0000_0000_0000_0000_0000_0000_0000_0000; // Data 0
MEM[1] <= 32'b0000_0000_0000_0000_0000_0000_0000_0001; // Data 1
MEM[2] <= 32'b0000_0000_0000_0000_0000_0000_0000_0010; // Data 2
MEM[3] <= 32'b0000_0000_0000_0000_0000_0000_0000_0011; // Data 3
MEM[4] <= 32'b0000_0000_0000_0000_0000_0000_0000_0100; // Data 4
MEM[5] <= 32'b0000_0000_0000_0000_0000_0000_0000_0101; // Data 5
end
// Get data from the specified address.
always @ *//(MemRead)
begin
Read_data <= MEM[Address];
end
// Write data to the specified address.
always @ (posedge clk && MemWrite)
begin
MEM[Address] <= Write_data;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class BigInt { public: int sign; string s; BigInt() : s( ) {} BigInt(string x) { *this = x; } BigInt(int x) { *this = to_string(x); } BigInt negative() { BigInt x = *this; x.sign *= -1; return x; } BigInt normalize(int newSign) { for (int a = s.size() - 1; a > 0 && s[a] == 0 ; a--) s.erase(s.begin() + a); sign = (s.size() == 1 && s[0] == 0 ? 1 : newSign); return *this; } void operator=(string x) { int newSign = (x[0] == - ? -1 : 1); s = (newSign == -1 ? x.substr(1) : x); reverse(s.begin(), s.end()); this->normalize(newSign); } bool operator==(const BigInt& x) const { return (s == x.s && sign == x.sign); } bool operator<(const BigInt& x) const { if (sign != x.sign) return sign < x.sign; if (s.size() != x.s.size()) return (sign == 1 ? s.size() < x.s.size() : s.size() > x.s.size()); for (int a = s.size() - 1; a >= 0; a--) if (s[a] != x.s[a]) return (sign == 1 ? s[a] < x.s[a] : s[a] > x.s[a]); return false; } bool operator<=(const BigInt& x) const { return (*this < x || *this == x); } bool operator>(const BigInt& x) const { return (!(*this < x) && !(*this == x)); } bool operator>=(const BigInt& x) const { return (*this > x || *this == x); } BigInt operator+(BigInt x) { BigInt curr = *this; if (curr.sign != x.sign) return curr - x.negative(); BigInt res; for (int a = 0, carry = 0; a < s.size() || a < x.s.size() || carry; a++) { carry += (a < curr.s.size() ? curr.s[a] - 0 : 0) + (a < x.s.size() ? x.s[a] - 0 : 0); res.s += (carry % 10 + 0 ); carry /= 10; } return res.normalize(sign); } BigInt operator-(BigInt x) { BigInt curr = *this; if (curr.sign != x.sign) return curr + x.negative(); int realSign = curr.sign; curr.sign = x.sign = 1; if (curr < x) return ((x - curr).negative()).normalize(-realSign); BigInt res; for (int a = 0, borrow = 0; a < s.size(); a++) { borrow = (curr.s[a] - borrow - (a < x.s.size() ? x.s[a] : 0 )); res.s += (borrow >= 0 ? borrow + 0 : borrow + 0 + 10); borrow = (borrow >= 0 ? 0 : 1); } return res.normalize(realSign); } BigInt operator*(BigInt x) { BigInt res( 0 ); for (int a = 0, b = s[a] - 0 ; a < s.size(); a++, b = s[a] - 0 ) { while (b--) res = (res + x); x.s.insert(x.s.begin(), 0 ); } return res.normalize(sign * x.sign); } BigInt operator/(BigInt x) { if (x.s.size() == 1 && x.s[0] == 0 ) x.s[0] /= (x.s[0] - 0 ); BigInt temp( 0 ), res; for (int a = 0; a < s.size(); a++) res.s += 0 ; int newSign = sign * x.sign; x.sign = 1; for (int a = s.size() - 1; a >= 0; a--) { temp.s.insert(temp.s.begin(), 0 ); temp = temp + s.substr(a, 1); while (!(temp < x)) { temp = temp - x; res.s[a]++; } } return res.normalize(newSign); } BigInt operator%(BigInt x) { if (x.s.size() == 1 && x.s[0] == 0 ) x.s[0] /= (x.s[0] - 0 ); BigInt res( 0 ); x.sign = 1; for (int a = s.size() - 1; a >= 0; a--) { res.s.insert(res.s.begin(), 0 ); res = res + s.substr(a, 1); while (!(res < x)) res = res - x; } return res.normalize(sign); } string toString() const { string ret = s; reverse(ret.begin(), ret.end()); return (sign == -1 ? - : ) + ret; } BigInt toBase10(int base) { BigInt exp(1), res( 0 ), BASE(base); for (int a = 0; a < s.size(); a++) { int curr = (s[a] < 0 || s[a] > 9 ? (toupper(s[a]) - A + 10) : (s[a] - 0 )); res = res + (exp * BigInt(curr)); exp = exp * BASE; } return res.normalize(sign); } BigInt toBase10(int base, BigInt mod) { BigInt exp(1), res( 0 ), BASE(base); for (int a = 0; a < s.size(); a++) { int curr = (s[a] < 0 || s[a] > 9 ? (toupper(s[a]) - A + 10) : (s[a] - 0 )); res = (res + ((exp * BigInt(curr) % mod)) % mod); exp = ((exp * BASE) % mod); } return res.normalize(sign); } string convertToBase(int base) { BigInt ZERO(0), BASE(base), x = *this; string modes = 0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ ; if (x == ZERO) return 0 ; string res = ; while (x > ZERO) { BigInt mod = x % BASE; x = x - mod; if (x > ZERO) x = x / BASE; res = modes[stoi(mod.toString())] + res; } return res; } BigInt toBase(int base) { return BigInt(this->convertToBase(base)); } friend ostream& operator<<(ostream& os, const BigInt& x) { os << x.toString(); return os; } }; const double EPS = (1e-5); int dcmp(double a, double b) { return fabs(a - b) <= EPS ? 0 : a < b ? -1 : 1; } struct line { double a, b, c; }; long long binpowmod(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } int findXOR(int n) { switch (n % 4) { case 0: return n; case 1: return 1; case 2: return n + 1; case 3: return 0; } } int rangeXOR(int l, int r) { return (findXOR(l - 1) ^ findXOR(r)); } int getbit(int mask, int bit) { return (mask & (1 << bit)); } void setbit(int& mask, int bit, int val) { if (val) mask |= (1 << bit); else mask &= ~(1 << bit); } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int N = 1e5 + 10; const int M = 500 + 10; const int MOD = 998244353; const long long INF = 1e15 + 100; void solve() { int n; cin >> n; vector<int> cnt(1e5 + 1); for (int i = 0; i < n; ++i) { int x; cin >> x; vector<int> divisors; int mx = 0; for (int i = 1; i * i <= x; ++i) { if (x % i == 0) { if (i != 1) { mx = max(mx, cnt[i] + 1); divisors.push_back(i); } if (x / i != i) { mx = max(mx, cnt[x / i] + 1); divisors.push_back(x / i); } } } for (int i = 0; i < (int)divisors.size(); ++i) cnt[divisors[i]] = mx; } int ans = *max_element(cnt.begin(), cnt.end()); cout << max(1, ans) << n ; } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc = 1; while (tc--) { solve(); } }
|
module IBUF(input I, output O);
assign O = I;
endmodule
module IOBUFE(input I, input E, output O, inout IO);
assign O = IO;
assign IO = E ? I : 1'bz;
endmodule
module ANDTERM(IN, IN_B, OUT);
parameter TRUE_INP = 0;
parameter COMP_INP = 0;
input [TRUE_INP-1:0] IN;
input [COMP_INP-1:0] IN_B;
output reg OUT;
integer i;
always @(*) begin
OUT = 1;
for (i = 0; i < TRUE_INP; i=i+1)
OUT = OUT & IN[i];
for (i = 0; i < COMP_INP; i=i+1)
OUT = OUT & ~IN_B[i];
end
endmodule
module ORTERM(IN, OUT);
parameter WIDTH = 0;
input [WIDTH-1:0] IN;
output reg OUT;
integer i;
always @(*) begin
OUT = 0;
for (i = 0; i < WIDTH; i=i+1) begin
OUT = OUT | IN[i];
end
end
endmodule
module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
parameter INVERT_OUT = 0;
input IN_PTC;
input IN_ORTERM;
output wire OUT;
wire xor_intermed;
assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
assign xor_intermed = IN_ORTERM ^ IN_PTC;
endmodule
module FDCP (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module FDCP_N (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module LDCP (G, PRE, CLR, D, Q);
parameter INIT = 0;
input G, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @* begin
if (CLR == 1)
Q <= 0;
else if (G == 1)
Q <= D;
else if (PRE == 1)
Q <= 1;
end
endmodule
module LDCP_N (G, PRE, CLR, D, Q);
parameter INIT = 0;
input G, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @* begin
if (CLR == 1)
Q <= 0;
else if (G == 0)
Q <= D;
else if (PRE == 1)
Q <= 1;
end
endmodule
module BUFG(I, O);
input I;
output O;
assign O = I;
endmodule
module BUFGSR(I, O);
parameter INVERT = 0;
input I;
output O;
assign O = INVERT ? ~I : I;
endmodule
module BUFGTS(I, O);
parameter INVERT = 0;
input I;
output O;
assign O = INVERT ? ~I : I;
endmodule
module FDDCP (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module FTCP (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FTCP_N (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FTDCP (C, PRE, CLR, T, Q);
parameter INIT = 0;
input C, PRE, CLR, T;
output wire Q;
reg Q_;
initial begin
Q_ <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q_ <= 0;
else if (PRE == 1)
Q_ <= 1;
else if (T == 1)
Q_ <= ~Q_;
end
assign Q = Q_;
endmodule
module FDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDCPE_N (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e6 + 10; const long long mod = 998244353; long long power(long long x, long long y) { x = x % mod, y = y % (mod - 1); long long ans = 1; while (y > 0) { if (y & 1) { ans = (1ll * x * ans) % mod; } y >>= 1; x = (1ll * x * x) % mod; } return ans; } long long add(long long a, long long b) { return (a % mod + b % mod) % mod; } long long mul(long long a, long long b) { return (a % mod * b % mod) % mod; } long long n, k; const long long K = 210; vector<long long> a(N); vector<long long> b(N); multiset<long long> st; long long pow2[N]; void power_2() { pow2[0] = 1; long long x = 1; long long cnt = 1; while (cnt < 3e5) { pow2[cnt] = mul(pow2[cnt - 1], 2); cnt++; } } int32_t main() { long long nx, mx; cin >> nx >> mx; string s, t; cin >> s >> t; power_2(); long long temp = 0, ans = 0; long long n = min(s.size(), t.size()); for (long long i = 0; i < mx; i++) { if (i < nx and s[nx - i - 1] == 1 ) temp = add(temp, pow2[i]); if (t[mx - i - 1] == 1 ) ans = add(ans, temp); } cout << ans; return 0; }
|
// MBT: This module has a broken interface because it uses bypass_i as a live input, which could use glitching
// MBT: This module should never be used in actual synthesized RTL; it must be hardened.
// For this reason, I am guarding it with an ifndef SYNTHESIS and we can fix it later.
`include "bsg_defines.v"
`ifndef SYNTHESIS
// This is an integrated clock cell using a negative latch and an AND gate
// This logic may be susceptible bug if en_i changes multiple times within a clk cyle
module bsg_clkgate_optional (input clk_i
,input en_i
,input bypass_i
,output gated_clock_o
);
//wire en_latch;
//assign en_latch = (reset_i) ? 1'b0 :
// (~clk_i) ? en_i : en_latch;
wire latched_en_lo;
bsg_dlatch #(.width_p(1), .i_know_this_is_a_bad_idea_p(1))
en_latch
( .clk_i ( ~clk_i )
, .data_i ( en_i )
, .data_o ( latched_en_lo )
);
assign gated_clock_o = (latched_en_lo|bypass_i) & clk_i;
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; inline void read(long long &x) { long long f = 1; x = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } long long fa[200005][21], lg[2 * 200005], deep[200005], dis[200005], w[200005], t[200005], h[200005], head, n, ans[200005]; struct yyy { long long to, z, w; inline void add(long long x, long long y, long long W) { to = y; z = h[x]; h[x] = head; w = W; } } a[200005 * 2]; inline void dfs2(long long x, long long pre) { register long long i; deep[x] = deep[pre] + 1; fa[x][0] = pre; for (i = 1; i <= lg[deep[x]]; i++) fa[x][i] = fa[fa[x][i - 1]][i - 1]; for (i = h[x]; i; i = a[i].z) if (a[i].to != pre) dis[a[i].to] = dis[x] + a[i].w, dfs2(a[i].to, x); } inline void dfs(long long x, long long pre) { register long long i; for (i = h[x]; i; i = a[i].z) if (a[i].to ^ pre) { dfs(a[i].to, x); t[x] += t[a[i].to]; } } inline void init() { register long long i, j, k; for (j = 1, k = 1; j <= n; j <<= 1, k++) for (i = j; i < j * 2; i++) lg[i] = k; dfs2(1, 0); } signed main() { register long long i, j, x, y; read(n); for (i = 1; i <= n; i++) read(w[i]); for (i = 2; i <= n; i++) { read(x); read(y); a[++head].add(i, x, y); a[++head].add(x, i, y); } init(); for (i = 2; i <= n; i++) { x = i; for (j = lg[deep[i]]; j >= 0; j--) if (fa[x][j] && dis[i] - dis[fa[x][j]] <= w[i]) x = fa[x][j]; t[fa[x][0]]--; t[fa[i][0]]++; } dfs(1, 0); for (i = 1; i <= n; i++) printf( %lld , t[i]); return 0; }
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: MBUS Reset Detector (Active Low)
// Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module rstdtctr
(
//Power Domain
//Always On
//Input
//Output
RESETn
);
output reg RESETn; //Active Low
initial begin
RESETn <= 1'b0;
`RESET_TIME;
RESETn <= 1'b1;
end
endmodule // rstdtctr
|
#include <bits/stdc++.h> using namespace std; const int N = 1000005; const int MAXN = 1e5 + 5; const int LG = 22; int dp[51][51][51][51]; int n; int a[55][55]; int get(int tli, int tlj, int rbi, int rbj) { int res = a[rbi][rbj]; if (tli > 0) res = res - a[tli - 1][rbj]; if (tlj > 0) res = res - a[rbi][tlj - 1]; if (tli > 0 && tlj > 0) res = res + a[tli - 1][tlj - 1]; return res; } int foo(int r1, int r2, int c1, int c2) { if (r1 > r2 or c1 > c2) return 0; if (dp[r1][r2][c1][c2] != -1) return dp[r1][r2][c1][c2]; int ans = (get(r1, c1, r2, c2) > 0) * max(r2 - r1 + 1, c2 - c1 + 1); for (int i = r1; i < r2; i++) { ans = min(ans, foo(r1, i, c1, c2) + foo(i + 1, r2, c1, c2)); } for (int i = c1; i < c2; i++) { ans = min(ans, foo(r1, r2, c1, i) + foo(r1, r2, i + 1, c2)); } return dp[r1][r2][c1][c2] = ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; string s[n]; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (s[i][j] == # ) { a[i][j] = 1; } } } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int ii = 0; ii < n; ii++) for (int jj = 0; jj < n; jj++) dp[i][ii][j][jj] = -1; for (int i = 0; i < n; i++) { for (int j = 1; j < n; j++) { a[i][j] += a[i][j - 1]; } } for (int i = 1; i < n; i++) { for (int j = 0; j < n; j++) { a[i][j] += a[i - 1][j]; } } int ans = foo(0, n - 1, 0, n - 1); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 1000; const long long INF64 = 1e18; const int N = 1001000; const int MOD = 1e9 + 7; const double EPS = 1E-9; long long gcd(long long a, long long b) { return a == 0 ? b : gcd(b % a, a); } int add(int first, int second, int m) { first += second; while (first >= m) first -= m; while (first < 0) first += m; return first; } int sub(int first, int second, int m) { return add(first, -second, m); } int mul(int first, int second, int m) { return (first * 1ll * second) % m; } int binpow(int first, int second, int m) { int z = 1; while (second) { if (second & 1) z = mul(z, first, m); first = mul(first, first, m); second >>= 1; } return z; } int divide(int first, int second, int m) { return mul(first, binpow(second, m - 2, m), m); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int first, t, a, b, da, db; cin >> first >> t >> a >> b >> da >> db; if (first == 0) { cout << YES n ; return 0; } for (int ta = 0; ta < t; ++ta) { for (int tb = 0; tb < t; ++tb) { if (a - da * ta + b - db * tb == first || a - da * ta == first || b - db * tb == first) { cout << YES n ; return 0; } } } cout << NO n ; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 10005; const int Maxb = 31; struct linker { int x, y, id; linker(int x = 0, int y = 0, int id = 0) : x(x), y(y), id(id) {} bool operator<(const linker &b) const { if (y != b.y) return y > b.y; if (x != b.x) return x > b.x; return id < b.id; } }; int n; linker L[Maxn]; int xbas[Maxb]; int rval[Maxb], masktaken[Maxn]; vector<pair<int, int> > res; int getBit(int x) { if (x == 0) return -1; for (int i = Maxb - 1; i >= 0; i--) if (x & 1 << i) return i; } void Swap(int a, int b) { if (a == b) return; res.push_back(pair<int, int>(L[a].id, L[b].id)); res.push_back(pair<int, int>(L[b].id, L[a].id)); res.push_back(pair<int, int>(L[a].id, L[b].id)); swap(L[a].x, L[b].x); int ab = getBit(L[a].x), bb = getBit(L[b].x); if (ab != -1) xbas[ab] = a; if (bb != -1) xbas[bb] = b; } void writeMask(int x) { for (int i = 0; i < Maxb; i++) if (masktaken[L[x].id] & 1 << i) res.push_back(pair<int, int>(L[x].id, rval[i])); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &L[i].x); L[i].id = i; for (int b = Maxb - 1; b >= 0; b--) if (L[i].x & 1 << b) if (xbas[b]) { res.push_back(pair<int, int>(i, xbas[b])); L[i].x ^= L[xbas[b]].x; } else { xbas[b] = i; break; } } for (int i = 1; i <= n; i++) { scanf( %d , &L[i].y); int num = L[i].y; L[i].y = 0; for (int b = Maxb - 1; b >= 0; b--) if (num & 1 << b) if (xbas[b]) { num ^= L[xbas[b]].x; L[i].y |= 1 << b; } else { printf( -1 n ); return 0; } } int cur = 1; while (true) { sort(L + cur, L + n + 1); for (int i = cur; i <= n; i++) { int b = getBit(L[i].x); if (b != -1) xbas[b] = i; } int b = getBit(L[cur].y); if (b == -1) { for (int i = cur; i <= n; i++) { if (L[i].x) res.push_back(pair<int, int>(L[i].id, L[i].id)); writeMask(i); } break; } else { Swap(cur, xbas[b]); writeMask(cur); for (int i = b - 1; i >= 0; i--) if (L[cur].y & 1 << i) res.push_back(pair<int, int>(L[cur].id, L[xbas[i]].id)); rval[b] = L[cur].id; masktaken[L[cur].id] ^= 1 << b; for (int i = cur + 1; i <= n; i++) if (L[i].y & 1 << b) { L[i].y ^= L[cur].y; masktaken[L[i].id] ^= masktaken[L[cur].id]; } } cur++; } printf( %d n , res.size()); for (int i = 0; i < res.size(); i++) printf( %d %d n , res[i].first, res[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, sum, mod1, mod, mod2; cin >> a >> b >> c; sum = (a + b); if ((a >= b || a <= b) && (c <= sum)) { if (c == a) { cout << YES << endl; } else if (c == sum) { cout << YES << endl; } else { cout << NO << endl; } } else if (c > sum) { mod = sum % b; sum = sum + 1; mod1 = sum % b; mod2 = c % b; if (mod2 == mod1 || mod2 == mod) { cout << YES << endl; } else { cout << NO << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; bool cmax(int &a, int b) { return (a < b) ? a = b, 1 : 0; } bool cmin(int &a, int b) { return (a > b) ? a = b, 1 : 0; } template <typename T> T read() { T ans = 0, f = 1; char ch = getchar(); while (!isdigit(ch) && ch != - ) ch = getchar(); if (ch == - ) f = -1, ch = getchar(); while (isdigit(ch)) ans = (ans << 3) + (ans << 1) + (ch - 0 ), ch = getchar(); return ans * f; } void file() {} int n, dep[N]; int same; void input() { n = read<int>(); for (register int i = (int)1; i <= (int)n + 1; ++i) { dep[i] = read<int>(); if (dep[i] > 1 && dep[i - 1] > 1) same = i; } } void work() { int old = 0, now = 0; if (!same) { puts( perfect ); return; } puts( ambiguous ); for (register int i = (int)1; i <= (int)n + 1; ++i) { for (register int j = (int)1; j <= (int)dep[i]; ++j) { now++; printf( %d , old); } old = now; } printf( n ); old = now = 0; for (register int i = (int)1; i <= (int)n + 1; ++i) { for (register int j = (int)1; j <= (int)dep[i]; ++j) { now++; if (i == same) { printf( %d , old - 1); same = 0; } else printf( %d , old); } old = now; } } int main() { file(); input(); work(); return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream frame joiner
*/
module axis_frame_join #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Prepend data with tag
parameter TAG_ENABLE = 1,
// Tag field width
parameter TAG_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
/*
* Status signals
*/
output wire busy
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter TAG_WORD_WIDTH = (TAG_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH;
parameter CL_TAG_WORD_WIDTH = $clog2(TAG_WORD_WIDTH);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_WRITE_TAG = 2'd1,
STATE_TRANSFER = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [CL_TAG_WORD_WIDTH-1:0] frame_ptr_reg = {CL_TAG_WORD_WIDTH{1'b0}}, frame_ptr_next;
reg [CL_S_COUNT-1:0] port_sel_reg = {CL_S_COUNT{1'b0}}, port_sel_next;
reg busy_reg = 1'b0, busy_next;
reg output_tuser_reg = 1'b0, output_tuser_next;
reg [S_COUNT-1:0] s_axis_tready_reg = {S_COUNT{1'b0}}, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
wire [DATA_WIDTH-1:0] input_tdata = s_axis_tdata[port_sel_reg*DATA_WIDTH +: DATA_WIDTH];
wire input_tvalid = s_axis_tvalid[port_sel_reg];
wire input_tlast = s_axis_tlast[port_sel_reg];
wire input_tuser = s_axis_tuser[port_sel_reg];
always @* begin
state_next = STATE_IDLE;
frame_ptr_next = frame_ptr_reg;
port_sel_next = port_sel_reg;
s_axis_tready_next = {S_COUNT{1'b0}};
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
output_tuser_next = output_tuser_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = {CL_TAG_WORD_WIDTH{1'b0}};
port_sel_next = {CL_S_COUNT{1'b0}};
output_tuser_next = 1'b0;
if (TAG_ENABLE) begin
// next cycle if started will send tag, so do not enable input
s_axis_tready_next = 1'b0;
end else begin
// next cycle if started will send data, so enable input
s_axis_tready_next = m_axis_tready_int_early;
end
if (s_axis_tvalid) begin
// input 0 valid; start transferring data
if (TAG_ENABLE) begin
// tag enabled, so transmit it
if (m_axis_tready_int_reg) begin
// output is ready, so short-circuit first tag word
frame_ptr_next = 1;
m_axis_tdata_int = tag;
m_axis_tvalid_int = 1'b1;
end
state_next = STATE_WRITE_TAG;
end else begin
// tag disabled, so transmit data
if (m_axis_tready_int_reg) begin
// output is ready, so short-circuit first data word
m_axis_tdata_int = s_axis_tdata;
m_axis_tvalid_int = 1'b1;
end
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_TAG: begin
// write tag data
if (m_axis_tready_int_reg) begin
// output ready, so send tag word
state_next = STATE_WRITE_TAG;
frame_ptr_next = frame_ptr_reg + 1;
m_axis_tvalid_int = 1'b1;
m_axis_tdata_int = tag >> frame_ptr_reg*DATA_WIDTH;
if (frame_ptr_reg == TAG_WORD_WIDTH-1) begin
s_axis_tready_next = m_axis_tready_int_early << 0;
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WRITE_TAG;
end
end
STATE_TRANSFER: begin
// transfer input data
// set ready for current input
s_axis_tready_next = m_axis_tready_int_early << port_sel_reg;
if (input_tvalid && m_axis_tready_int_reg) begin
// output ready, transfer byte
state_next = STATE_TRANSFER;
m_axis_tdata_int = input_tdata;
m_axis_tvalid_int = input_tvalid;
if (input_tlast) begin
// last flag received, switch to next port
port_sel_next = port_sel_reg + 1;
// save tuser - assert tuser out if ANY tuser asserts received
output_tuser_next = output_tuser_next | input_tuser;
// disable input
s_axis_tready_next = {S_COUNT{1'b0}};
if (S_COUNT == 1 || port_sel_reg == S_COUNT-1) begin
// last port - send tlast and tuser and revert to idle
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = output_tuser_next;
state_next = STATE_IDLE;
end else begin
// otherwise, disable enable next port
s_axis_tready_next = m_axis_tready_int_early << port_sel_next;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= {CL_TAG_WORD_WIDTH{1'b0}};
port_sel_reg <= {CL_S_COUNT{1'b0}};
s_axis_tready_reg <= {S_COUNT{1'b0}};
output_tuser_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
port_sel_reg <= port_sel_next;
s_axis_tready_reg <= s_axis_tready_next;
output_tuser_reg <= output_tuser_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
`resetall
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`ifdef verilator
`define stop $stop
`else
`define stop
`endif
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
class Cls;
bit b;
int i;
bit [15:0] carray4 [4];
bit [64:0] cwide[2];
string name;
task debug();
$display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message");
endtask
endclass
module t (/*AUTOARG*/);
initial begin
Cls c;
c = new;
c.b = '1;
c.i = 42;
c.name = "object_name";
c.carray4[0] = 16'h11;
c.carray4[1] = 16'h22;
c.carray4[2] = 16'h33;
c.carray4[3] = 16'h44;
$display("'%p'", c);
c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944};
$display("'%p'", c);
c.debug();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int buffer_size = 1 << 20; int rd_char() { static char buf[buffer_size]; static int l = buffer_size, r = buffer_size; if (l == r && r == buffer_size) { r = fread(buf, sizeof(char), 1 << 20, stdin); l = 0; } if (l == r) return EOF; return buf[l++]; } unsigned int rd_uint() { int c; unsigned int x = 0; while ( 0 <= (c = rd_char())) x = x * 10 + c - 0 ; return x; } int rd_int() { bool neg = false; int c = rd_char(); long long x = 0; if (c == - ) neg = true; else x = c - 0 ; while ( 0 <= (c = rd_char())) x = x * 10 + c - 0 ; return neg ? -x : x; } unsigned long long rd_ull() { int c; unsigned long long x = 0; while ( 0 <= (c = rd_char())) x = x * 10 + c - 0 ; return x; } long long rd_ll() { bool neg = false; int c = rd_char(); long long x = 0; if (c == - ) neg = true; else x = c - 0 ; while ( 0 <= (c = rd_char())) x = x * 10 + c - 0 ; return neg ? -x : x; } string rd_str() { string ret; int c; while ((c = rd_char()) != n && c != && c != EOF) ret += c; return ret; } struct writer_struct { char buf[buffer_size]; int l = 0; ~writer_struct() { fwrite(buf, sizeof(char), l, stdout); } } writer; void flush() { fwrite(writer.buf, sizeof(char), writer.l, stdout); fflush(stdout); writer.l = 0; } void wt(char c) { if (writer.l == buffer_size) { fwrite(writer.buf, sizeof(char), buffer_size, stdout); writer.l = 0; } writer.buf[writer.l++] = c; } void wt(unsigned int x) { if (x == 0) wt( 0 ); else { char f[10]; int sz = 0; while (x) { f[sz++] = x % 10 + 0 ; x /= 10; } while (sz) wt(f[--sz]); } } void wt(int x) { if (x < 0) wt( - ), x = -x; wt((unsigned int)x); } void wt(unsigned long long x) { if (x == 0) wt( 0 ); else { char f[20]; int sz = 0; while (x) { f[sz++] = x % 10 + 0 ; x /= 10; } while (sz) wt(f[--sz]); } } void wt(long long x) { if (x < 0) wt( - ), x = -x; wt((unsigned long long)x); } void wt(const char* s) { while (*s != 0 ) wt(*s++); } void wt(const string& s) { for (char c : s) wt(c); } const int LIM = 3e6; int N, C[LIM + 1]; long long cnt[LIM + 1]; int main() { N = rd_uint(); for (int i = 0; i < N; i++) C[rd_uint()]++; for (int i = 1; i <= LIM; i++) { if ((long long)i * i <= LIM) cnt[i * i] += (long long)C[i] * (C[i] - 1); else cnt[LIM] += (long long)C[i] * (C[i] - 1); int rest = N - C[i]; for (int j = 1; (long long)i * j <= LIM; j++) { if (i != j) cnt[i * j] += (long long)C[i] * C[j], rest -= C[j]; } cnt[LIM] += (long long)C[i] * rest; } for (int i = LIM; i >= 1; i--) cnt[i - 1] += cnt[i]; int M = rd_uint(); for (; M--;) { int p = rd_uint(); wt(cnt[p]); wt( n ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string sub; for (int i = 0; i < k; i++) { sub.push_back( k ); } long long int count = 0; set<string> arra; for (int i = 0; i < n; i++) { string a; cin >> a; arra.insert(a); } set<string>::iterator it1, it2; for (it1 = arra.begin(); it1 != arra.end(); it1++) { for (it2 = arra.begin(); it2 != arra.end(); it2++) { string a = *it1; string b = *it2; if (a != b) { for (int i = 0; i < k; i++) { if (a[i] == b[i]) { sub[i] = a[i]; } else if ((a[i] == S && b[i] == T ) || (a[i] == T && b[i] == S )) { sub[i] = E ; } else if ((a[i] == S && b[i] == E ) || (a[i] == E && b[i] == S )) { sub[i] = T ; } else if ((a[i] == E && b[i] == T ) || (a[i] == T && b[i] == E )) { sub[i] = S ; } } if (arra.find(sub) != arra.end()) { count++; } } } } cout << count / 6 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const double pi = 3.14159265358979323846264338327950288419716939937510582097494459230781640628620899862; void gn(int &x) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; if (c == - ) sg = -1, x = 0; else x = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= sg; } void gn(long long &x) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; if (c == - ) sg = -1, x = 0; else x = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= sg; } int mo = 1000000007; int inf = 1061109567; double eps = 1e-6; int qp(int a, long long b) { int ans = 1; do { if (b & 1) ans = 1ll * ans * a % mo; a = 1ll * a * a % mo; } while (b >>= 1); return ans; } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; int a[333]; int n; void out(int i, int t) { for (int j = 0; j < t; j++) putchar(i - 1 + a ); } int ord[333]; int main() { gn(n); for (int i = 1; i <= n; i++) gn(a[i]); int su = 0; int numodd = 0; for (int i = 1; i <= n; i++) numodd += a[i] & 1, su += a[i]; if (numodd > 1) { printf( 0 n ); for (int i = 1; i <= n; i++) out(i, a[i]); putchar( n ); return 0; } int d = 0; for (int i = 1; i <= n; i++) d = gcd(d, a[i]); int no1 = 0; for (int i = 1; i <= n; i++) no1 += (a[i] / d) & 1; if (no1 > 1 && d % 2 == 0) d /= 2, no1 = 0; for (int i = 1; i <= n; i++) a[i] /= d; for (int i = 1; i <= n; i++) ord[i] = i; for (int i = 1; i <= n; i++) if (a[i] & 1) swap(ord[i], ord[n]); if (no1) { printf( %d n , d); } else printf( %d n , d * 2); for (int tt = 1; tt <= d; tt++) { for (int i = 1; i <= n - 1; i++) { out(ord[i], a[ord[i]] / 2); } out(ord[n], a[ord[n]]); for (int i = n - 1; i >= 1; i--) { out(ord[i], a[ord[i]] / 2); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__OR3B_FUNCTIONAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3b (
VPWR,
VGND,
X ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; using DB = double; using LL = long long; using PII = pair<int, int>; void err() { puts( ); } template <template <typename...> class T, typename t, typename... Args> void err(T<t> a, Args... args) { for (auto x : a) cout << x << ; err(args...); } template <typename T, typename... Args> void err(T a, Args... args) { cout << a << ; err(args...); } const int N = 2e5 + 10; char s[N], t[N]; void work() { int n, m; scanf( %d%d%s%s , &n, &m, s, t); int id = -1; for (int i = 0; i < n; i++) if (s[i] == * ) id = i; if (id == -1) { printf( %s n , strcmp(s, t) == 0 ? YES : NO ); } else { bool flag = 0; if (n - 1 <= m) { flag = 1; for (int i = 0; i < id; i++) { if (s[i] != t[i]) flag = 0; } for (int i = n - 1, j = m - 1; i > id; i--, j--) { if (s[i] != t[j]) flag = 0; } } printf( %s n , flag ? YES : NO ); } } int main() { work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, x; vector<int> a; cin >> n >> k; vector<int> w(k); for (int i = 0; i < n; i++) { cin >> x; a.push_back(x); } for (int i = 0; i < k; i++) { for (int j = i; j < n; j += k) { w[i] += a[j]; } } int menor = w[0]; int z = 0; for (int i = 0; i < k; i++) if (menor > w[i]) { menor = w[i]; z = i; } cout << z + 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f *= -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = (x << 1) + (x << 3) + s - 0 ; s = getchar(); } return x * f; } int n = read(), w[5], dp[1005][630], s[15], c[15] = {0, 125, 25, 5, 1, 300, 60, 12, 465, 93, 624}; bool p[6][1005]; int main() { for (int i = 1; i < 5; i++) w[i] = read(); char ss = getchar(); for (int i = 1; i < 5; i++) for (int j = 1; j <= n; j++) { while (ss != . && ss != * ) ss = getchar(); p[i][j] = (ss == * ); ss = getchar(); } memset(dp, 0x3f3f3f3f, sizeof(dp)); dp[1][0] = 0; int b[5] = {0, 125, 25, 5, 1}; for (int i = 1; i < 11; i++) { if (i < 5) s[i] = w[1]; else if (i > 4 && i < 8) s[i] = w[2]; else if (i > 7 && i < 10) s[i] = w[3]; else s[i] = w[4]; } for (int i = 1; i <= n; i++) { for (int j = 0; j < 625; j++) { int a[5] = {0, j / 125, j / 25 % 5, j / 5 % 5, j % 5}; if (max(max(a[1], a[2]), max(a[3], a[4])) > n - i + 1) continue; for (int o = 1; o < 5; o++) if (a[o] > 0 && !p[o][i + a[o] - 1]) dp[i][j] = min(dp[i][j], dp[i][j - b[o]]); if (min(min(a[1], a[2]), min(a[3], a[4])) > 0) dp[i + 1][j - 156] = min(dp[i + 1][j - 156], dp[i][j]); for (int k = 1; k < 11; k++) { int b[5] = {0, c[k] / 125, c[k] / 25 % 5, c[k] / 5 % 5, c[k] % 5}, l = 0; for (int o = 1; o < 5; o++) l = l * 5 + max(a[o], b[o]); dp[i][l] = min(dp[i][l], dp[i][j] + s[k]); } } } printf( %d n , dp[n + 1][0]); return 0; }
|
module npc (iaddr, branch, jump, ins, jiaddr, imm16, imm26, riaddr, niaddr);
input branch, jump;
input [31:0] ins;
input [31:0] jiaddr;// Jump to instruction address.
input [31:0] iaddr;// Instruction Address.
input [15:0] imm16;
input [25:0] imm26;
output [31:0] riaddr;// Return instruction address;
output reg [31:0] niaddr;// Next Instruction Address;
wire [5:0] op;
wire [5:0] func;
assign op = ins[31:26];
assign func = ins[5:0];
// Operation code.
parameter R = 6'b000000,
J = 6'b000010,
JAL = 6'b000011,
ERET = 6'b010000;
// Function code.
parameter JR = 6'b001000,
JALR = 6'b001001,
SYSCALL = 6'b001100;
wire [31:0] pc4;
assign pc4 = iaddr + 3'b100;
assign riaddr = pc4 + 3'b100;
always @ ( * ) begin
if (branch) begin// Branch;
// Arithmetic extend.
niaddr = {{14{imm16[15]}}, imm16[15:0], 2'b00} + pc4;
end else if (jump) begin// Jump.
case (op)
J: begin// Jump.
niaddr = {iaddr[31:28], imm26[25:0], 2'b00};
end
JAL: begin// Jump and link.
// riaddr <= pc4 + 3'b100;
niaddr <= {iaddr[31:28], imm26[25:0], 2'b00};
end
R: begin
case (func)
JR: begin// Jump register.
niaddr = jiaddr[31:0];
end
JALR: begin// Jump and link register.
// riaddr <= pc4 + 3'b100;
niaddr <= jiaddr[31:0];
end
SYSCALL: begin
niaddr <= jiaddr[31:0];
end
endcase
end
ERET: begin
niaddr <= jiaddr[31:0];
end
endcase
end else begin// PC + 4;
niaddr = pc4;
end
end
endmodule // Next Program Counter;
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
// See xapp052.pdf from Xilinx
module jt51_noise_lfsr #(parameter init=14220 )(
input rst,
input clk,
input cen,
input base,
output out
);
reg [16:0] bb;
assign out = bb[16];
always @(posedge clk, posedge rst) begin : base_counter
if( rst ) begin
bb <= init[16:0];
end
else if(cen) begin
if( base ) begin
bb[16:1] <= bb[15:0];
bb[0] <= ~(bb[16]^bb[13]);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; int n, m; vector<int> g[MAXN]; int max1[MAXN], max2[MAXN]; bool vis[MAXN]; void dfs(int v) { vis[v] = true; for (auto to : g[v]) { if (!vis[to]) { dfs(to); if (max1[v] <= max1[to] + 1) { max2[v] = max1[v]; max1[v] = max1[to] + 1; } else if (max2[v] < max1[to] + 1) { max2[v] = max1[to] + 1; } } } } int ans; int main() { cin >> n >> m; while (m--) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i); for (int i = 1; i <= n; i++) ans = max(ans, max1[i] + max2[i]); cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> #define mp make_pair #define fi first #define se second #define pb push_back #define eb emplace_back #define all(x) (x).begin(), (x).end() #define rall(x) (x).rbegin(), (x).rend() #define forn(i, n) for (int i = 0; i < (int)(n); ++i) #define for1(i, n) for (int i = 1; i <= (int)(n); ++i) #define ms(x, y) memset(x, y, sizeof(x)) #define SZ(x) int(x.size()) #define fk cout<< fk <<endl #define db(x) cout<<(#x)<< = <<(x)<<endl #define db2(x,y) cout<<(#x)<< = <<(x)<< <<(#y)<< = <<(y)<<endl using namespace std; typedef pair<int, int> pii; typedef vector<int> vi; typedef long long i64; template<class T> bool uin(T &a, T b) { return a > b ? (a = b, true) : false; } template<class T> bool uax(T &a, T b) { return a < b ? (a = b, true) : false; } void fastio(){ios::sync_with_stdio(false); cin.tie(0); cout.precision(10); cout<<fixed;} //1.integer overflow (1e5 * 1e5) (2e9 + 2e9) //2.runtime error //3.boundary condition int tc,n,k,cnt[30],need[30]; string s; int main() { fastio(); cin>>tc; while(tc--){ cin>>n>>k; cin>>s; ms(cnt,0); for(int i=0; i<n; ++i){ int num=int(s[i])-int( a ); ++cnt[num]; } bool ok=true; for(int i=0; i<26; ++i){ if(cnt[i]%k!=0) ok=false; } if(ok){ cout<<s<< n ; continue; } bool have=false; string ans= ; for(int i=n-1; i>=0; --i){ string res= ; int cur=int(s[i])-int( a ); --cnt[cur]; if(cur==25) continue; int all_need=0; ms(need,0); for(int j=0; j<26; ++j){ int goal=(cnt[j]+k-1)/k*k; need[j]=goal-cnt[j]; all_need+=goal-cnt[j]; } if(all_need<=n-i){ if(all_need==n-i){ int find=-1; for(int j=cur+1; j<26; ++j){ if(need[j]>0){ find=j; break; } } if(find!=-1){ have=true; for(int j=0; j<i; ++j) res+=s[j]; char ch=char(int( a )+find); res+=ch; --need[find]; for(int j=0; j<26; ++j){ while(need[j]>0){ char ch_temp=char(int( a )+j); res+=ch_temp; need[j]--; } } ans=res; break; } } else{ if(((n-i)-all_need)%k==0){ int find=-1; for(int j=cur+1; j<26; ++j){ if(need[j]>0){ find=j; break; } } if(find==cur+1){ need[0]+=(n-i)-all_need; have=true; for(int j=0; j<i; ++j) res+=s[j]; res+=char(int( a )+cur+1); --need[cur+1]; for(int j=0; j<26; ++j){ while(need[j]>0){ res+=char(int( a )+j); --need[j]; } } ans=res; break; } else{ need[cur+1]+=k; need[0]+=(n-i)-all_need-k; have=true; for(int j=0; j<i; ++j) res+=s[j]; res+=char(int( a )+cur+1); --need[cur+1]; for(int j=0; j<26; ++j){ while(need[j]>0){ res+=char(int( a )+j); --need[j]; } } ans=res; break; } } } } } // if(have) assert(SZ(ans)==n); if(have) cout<<ans<< n ; else cout<<-1<< n ; } return 0; }
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// Directive indicates that 1ns is the time period used when specifying delays
// (i.e., #10 means 10ns); 100ps is the smallest unit of time precision that
// will be simulated (100ps = .1ns; thus #.1 is meaningful, #.00001 is equivalent
// to #0)
`timescale 1ns / 100ps
module testbench ();
reg clk;
reg reset_;
reg up_;
reg down_;
reg left_;
reg right_;
wire [6:0] segment_;
wire [3:0] digit_enable_;
// Create an instance of the circuit under test
konamiacceptor uut (
.clk(clk),
.reset_(reset_),
.up_(up_),
.down_(down_),
.left_(left_),
.right_(right_),
.segment_(segment_),
.digit_enable_(digit_enable_)
);
always@ (uut.state)
$display("Konami state changed to %d (%s)", uut.state,
uut.state == 4'd0 ? "START" :
uut.state == 4'd1 ? "UP_1" :
uut.state == 4'd2 ? "UP_2" :
uut.state == 4'd3 ? "DOWN_1" :
uut.state == 4'd4 ? "DOWN_2" :
uut.state == 4'd5 ? "LEFT_1" :
uut.state == 4'd6 ? "RIGHT_1" :
uut.state == 4'd7 ? "LEFT_2" :
uut.state == 4'd9 ? "ACCEPT" :
uut.state == 4'd10 ? "REJECT" : "(BUG!)"
);
// Initialize the clock signal to zero; drive reset_ active (low) for the
// first 100ns of the simulation.
initial begin
clk = 1'b0;
reset_ = 1'b0;
up_ = 1'b1;
down_ = 1'b1;
left_ = 1'b1;
right_ = 1'b1;
#100 reset_ = 1'b1;
end
// Stop the simulation after 400ms; note that simulations can run indefinitely
// (with waveforms loaded incrementally in the viewer.) Press ctrl-c to break
// iverilog, then enter '$finish' to stop the simulation.
initial begin
#400000000 $finish; // 400ms
end
// Toggle the clock every 31.25ns (32 MHz frequency)
initial begin forever
#31.25 clk = ~clk;
end
initial begin
#500;
press_up();
press_up();
press_down();
press_down();
press_left();
press_right();
press_left();
press_right();
#100000;
$finish;
end
// Produce a waveform output of this simulation
initial begin
$dumpfile("waveform.vcd");
$dumpvars();
end
task press_up;
begin
up_ <= 1'b0;
@(posedge uut.up_debounced);
up_ <= 1'b1;
@(negedge uut.up_debounced);
end
endtask
task press_down;
begin
down_ <= 1'b0;
@(posedge uut.down_debounced);
down_ <= 1'b1;
@(negedge uut.down_debounced);
end
endtask
task press_left;
begin
left_ <= 1'b0;
@(posedge uut.left_debounced);
left_ <= 1'b1;
@(negedge uut.left_debounced);
end
endtask
task press_right;
begin
right_ <= 1'b0;
@(posedge uut.right_debounced);
right_ <= 1'b1;
@(negedge uut.right_debounced);
end
endtask
endmodule
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#include <bits/stdc++.h> using namespace std; int k[5] = {100, 20, 10, 5, 1}; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; while (cin >> n) { long long ans = 0; for (int i = 0; i < 5; i++) { ans += n / k[i]; n %= k[i]; } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> v[1000005]; int ok[2][1000005]; int main() { int q; cin >> q; while (q--) { int n; cin >> n; for (int i = 0; i < n; i++) ok[0][i] = 0; set<int> s; for (int i = 0; i < n; i++) s.insert(i); int cnt = 0; for (int i = 0; i < n; i++) { int x; cin >> x; v[i].clear(); for (int j = 0; j < x; j++) { int a; cin >> a; v[i].push_back(a - 1); } for (int j = 0; j < v[i].size(); j++) { if (s.count(v[i][j])) { ok[0][i] = ok[1][v[i][j]] = 1; s.erase(v[i][j]); cnt++; break; } } } if (cnt == n) cout << OPTIMAL << endl; else { cout << IMPROVE << endl; for (int i = n - 1; i >= 0; i--) { if (ok[0][i] == 0) { cout << (i + 1) << << (*s.rbegin() + 1) << endl; ; break; } } } } return 0; }
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#include <bits/stdc++.h> int x[30]; template <class T> inline void read(T &num) { num = 0; char c = getchar(); T sign = 1; while (c < 0 || c > 9 ) { if (c == - ) sign = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { num = (num << 1) + (num << 3) + (c ^ 48); c = getchar(); } num *= sign; } int main() { int t, a; read(t); while (t--) { read(a); int tag = a, cnt = 0, ok = 0, ans = 0; while (tag) { x[++cnt] = tag & 1; if (!x[cnt]) ok = 1; tag >>= 1; } if (ok) { for (register int i = cnt; i; --i) { ans <<= 1; if (!x[i]) ++ans; } printf( %d n , ans ^ a); } else { for (register int i = 2; i * i <= a; ++i) if (a % i == 0) { printf( %d n , a / i); ok = 1; break; } if (!ok) puts( 1 ); } } return 0; }
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream statistics counter
*/
module axis_stat_counter #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16,
parameter TICK_COUNT_ENABLE = 1,
parameter TICK_COUNT_WIDTH = 32,
parameter BYTE_COUNT_ENABLE = 1,
parameter BYTE_COUNT_WIDTH = 32,
parameter FRAME_COUNT_ENABLE = 1,
parameter FRAME_COUNT_WIDTH = 32
)
(
input wire clk,
input wire rst,
/*
* AXI monitor
*/
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
/*
* AXI status data output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
input wire trigger,
/*
* Status
*/
output wire busy
);
localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
localparam TICK_COUNT_BYTE_WIDTH = (TICK_COUNT_WIDTH + 7) / 8;
localparam BYTE_COUNT_BYTE_WIDTH = (BYTE_COUNT_WIDTH + 7) / 8;
localparam FRAME_COUNT_BYTE_WIDTH = (FRAME_COUNT_WIDTH + 7) / 8;
localparam TOTAL_LENGTH = TAG_BYTE_WIDTH + TICK_COUNT_BYTE_WIDTH + BYTE_COUNT_BYTE_WIDTH + FRAME_COUNT_BYTE_WIDTH;
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_OUTPUT_DATA = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [TICK_COUNT_WIDTH-1:0] tick_count_reg = 0, tick_count_next;
reg [BYTE_COUNT_WIDTH-1:0] byte_count_reg = 0, byte_count_next;
reg [FRAME_COUNT_WIDTH-1:0] frame_count_reg = 0, frame_count_next;
reg frame_reg = 0, frame_next;
reg store_output;
reg [$clog2(TOTAL_LENGTH)-1:0] frame_ptr_reg = 0, frame_ptr_next;
reg [TICK_COUNT_WIDTH-1:0] tick_count_output_reg = 0;
reg [BYTE_COUNT_WIDTH-1:0] byte_count_output_reg = 0;
reg [FRAME_COUNT_WIDTH-1:0] frame_count_output_reg = 0;
reg busy_reg = 0;
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign busy = busy_reg;
integer offset, i, bit_cnt;
always @* begin
state_next = 2'bz;
tick_count_next = tick_count_reg;
byte_count_next = byte_count_reg;
frame_count_next = frame_count_reg;
frame_next = frame_reg;
output_axis_tdata_int = 0;
output_axis_tvalid_int = 0;
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
store_output = 0;
frame_ptr_next = frame_ptr_reg;
// data readout
case (state_reg)
STATE_IDLE: begin
if (trigger) begin
store_output = 1;
tick_count_next = 0;
byte_count_next = 0;
frame_count_next = 0;
frame_ptr_next = 0;
if (output_axis_tready_int) begin
frame_ptr_next = 1;
if (TAG_ENABLE) begin
output_axis_tdata_int = tag[(TAG_BYTE_WIDTH-1)*8 +: 8];
end else if (TICK_COUNT_ENABLE) begin
output_axis_tdata_int = tick_count_reg[(TICK_COUNT_BYTE_WIDTH-1)*8 +: 8];
end else if (BYTE_COUNT_ENABLE) begin
output_axis_tdata_int = byte_count_reg[(BYTE_COUNT_BYTE_WIDTH-1)*8 +: 8];
end else if (FRAME_COUNT_ENABLE) begin
output_axis_tdata_int = frame_count_reg[(FRAME_COUNT_BYTE_WIDTH-1)*8 +: 8];
end
output_axis_tvalid_int = 1;
end
state_next = STATE_OUTPUT_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_OUTPUT_DATA: begin
if (output_axis_tready_int) begin
state_next = STATE_OUTPUT_DATA;
frame_ptr_next = frame_ptr_reg + 1;
output_axis_tvalid_int = 1;
offset = 0;
if (TAG_ENABLE) begin
for (i = TAG_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tag[i*8 +: 8];
end
offset = offset + 1;
end
end
if (TICK_COUNT_ENABLE) begin
for (i = TICK_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tick_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (BYTE_COUNT_ENABLE) begin
for (i = BYTE_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = byte_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (FRAME_COUNT_ENABLE) begin
for (i = FRAME_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = frame_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (frame_ptr_reg == offset-1) begin
output_axis_tlast_int = 1;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_OUTPUT_DATA;
end
end
endcase
// stats collection
// increment tick count by number of words that can be transferred per cycle
tick_count_next = tick_count_next + KEEP_WIDTH;
if (monitor_axis_tready & monitor_axis_tvalid) begin
// valid transfer cycle
// increment byte count by number of words transferred
bit_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
byte_count_next = byte_count_next + bit_cnt;
// count frames
if (monitor_axis_tlast) begin
// end of frame
frame_next = 0;
end else if (~frame_reg) begin
// first word after end of frame
frame_count_next = frame_count_next + 1;
frame_next = 1;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
tick_count_reg <= 0;
byte_count_reg <= 0;
frame_count_reg <= 0;
frame_reg <= 0;
frame_ptr_reg <= 0;
busy_reg <= 0;
tick_count_output_reg <= 0;
byte_count_output_reg <= 0;
frame_count_output_reg <= 0;
end else begin
state_reg <= state_next;
tick_count_reg <= tick_count_next;
byte_count_reg <= byte_count_next;
frame_count_reg <= frame_count_next;
frame_reg <= frame_next;
frame_ptr_reg <= frame_ptr_next;
busy_reg <= state_next != STATE_IDLE;
if (store_output) begin
tick_count_output_reg <= tick_count_reg;
byte_count_output_reg <= byte_count_reg;
frame_count_output_reg <= frame_count_reg;
end
end
end
// output datapath logic
reg [7:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [7:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { long long n, side = 0, ans = 0; cin >> n; int i = (n + 1) % 4; if (i == 0) ans = n + 1; else if (i == 1 || i == 3) ans = 4 * n + 1; else ans = 2 * n + 1; cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int a, b, t, c, j, k, T, i, A[1028], B[1028], C[1028]; int main() { cin >> a >> b; while (a > 0) { a--; t++; if (t == b) { t = 0; a++; } j++; } cout << j; }
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`timescale 1ns / 1ps
module ym_sync(
input rst,
input clk,
// YM2151 pins
input ym_p1,
input ym_so,
input ym_sh1,
input ym_sh2,
input ym_irq_n,
input [7:0] ym_data,
//
output reg ym_p1_sync,
output reg ym_so_sync,
output reg ym_sh1_sync,
output reg ym_sh2_sync,
output reg ym_irq_n_sync,
output reg [7:0] ym_data_sync
);
reg p1_0, so_0, sh1_0, sh2_0, irq_0;
reg [7:0] data0;
always @(posedge ym_p1 or posedge rst ) begin : first_sync
if( rst ) begin
p1_0 <= 1'b0;
so_0 <= 1'b0;
sh1_0 <= 1'b0;
sh2_0 <= 1'b0;
irq_0 <= 1'b1;
data0 <= 8'h0;
end
else begin
p1_0 <= ym_p1;
so_0 <= ym_so;
sh1_0 <= ym_sh1;
sh2_0 <= ym_sh2;
irq_0 <= ym_irq_n;
data0 <= ym_data;
end
end
always @(posedge clk or posedge rst ) begin : second_sync
if( rst ) begin
ym_p1_sync <= 1'b0;
ym_so_sync <= 1'b0;
ym_sh1_sync <= 1'b0;
ym_sh2_sync <= 1'b0;
ym_irq_n_sync <= 1'b1;
ym_data_sync <= 8'h0;
end
else begin
ym_p1_sync <= p1_0;
ym_so_sync <= so_0;
ym_sh1_sync <= sh1_0;
ym_sh2_sync <= sh2_0;
ym_irq_n_sync <= irq_0;
ym_data_sync <= data0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long calc2(long long a, long long b, long long c, long long ab, long long ac, long long bc, long long abc) { long long parts[] = {a - ab - ac + abc, b - ab - bc + abc, c - ac - bc + abc, ab - abc, ac - abc, bc - abc, abc}; int masks[3] = {1 + 8 + 16 + 64, 2 + 8 + 32 + 64, 4 + 16 + 32 + 64}; static int mark[64 * 8] = {0}; static int id = 0; ++id; long long res = 0; for (int i = 0; i < 7; ++i) if ((masks[0] >> i) & 1) for (int j = 0; j < 7; ++j) if ((masks[1] >> j) & 1) for (int k = 0; k < 7; ++k) if ((masks[2] >> k) & 1) { int a1 = min(i, min(j, k)); int a3 = max(i, max(j, k)); int a2 = i + j + k - a1 - a3; if (mark[64 * a1 + 8 * a2 + a3] == id) continue; mark[64 * a1 + 8 * a2 + a3] = id; if (i == j && j == k) { long long x = parts[i]; res += +x * (x - 1) * (x - 2) / 6 + x * (x - 1) + x; } else if (i == j || j == k || i == k) { long long x = parts[i]; long long y = parts[j]; if (i == j) y = parts[k]; else if (j == k) swap(x, y); res += x * (x + 1) / 2 * y; } else { res += parts[i] * parts[j] * parts[k]; } } return res; } int get_common_num(vector<int> &a, vector<int> &b) { int ia = 0, ib = 0; int res = 0; while (ia < a.size() && ib < b.size()) { if (a[ia] == b[ib]) { ++res; ++ia, ++ib; } else if (a[ia] < b[ib]) ++ia; else ++ib; } return res; } int get_common_num(vector<int> &a, vector<int> &b, vector<int> &c) { int ia = 0, ib = 0, ic = 0; int res = 0; while (ia < a.size() && ib < b.size() && ic < c.size()) { if (a[ia] == b[ib] && b[ib] == c[ic]) { ++res; ++ia, ++ib, ++ic; } else if (a[ia] <= min(b[ib], c[ic])) ++ia; else if (b[ib] <= min(a[ia], c[ic])) ++ib; else ++ic; } return res; } vector<int> dividers[100111]; int main() { ios::sync_with_stdio(false); dividers[1].push_back(1); vector<int> smallest_fact(100111 + 1, 0); for (int i = 2; i < 100111; ++i) { if (!smallest_fact[i]) { smallest_fact[i] = i; for (long long j = i * (long long)i; j < 100111; j += i) { if (!smallest_fact[j]) smallest_fact[j] = i; } } int p = smallest_fact[i]; int x = i; while (x % p == 0) x /= p; int y = i; int pp = p; dividers[i] = dividers[x]; while (y % p == 0) { for (int d : dividers[x]) dividers[i].push_back(pp * d); pp *= p; y /= p; } sort(dividers[i].begin(), dividers[i].end()); } int t; cin >> t; while (t--) { int a, b, c; cin >> a >> b >> c; int x = dividers[a].size(); int y = dividers[b].size(); int z = dividers[c].size(); int xy = get_common_num(dividers[a], dividers[b]); int xz = get_common_num(dividers[a], dividers[c]); int yz = get_common_num(dividers[b], dividers[c]); int xyz = get_common_num(dividers[a], dividers[b], dividers[c]); long long ans = calc2(x, y, z, xy, xz, yz, xyz); cout << ans << n ; } return 0; }
|
module reset_and_status
#(
parameter PIO_WIDTH=32
)
(
input clk,
input resetn,
output reg [PIO_WIDTH-1 : 0 ] pio_in,
input [PIO_WIDTH-1 : 0 ] pio_out,
input lock_kernel_pll,
input fixedclk_locked, // pcie fixedclk lock
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
output reg [1:0] mem_organization,
output [1:0] mem_organization_export,
output pll_reset,
output reg sw_reset_n_out
);
reg [1:0] pio_out_ddr_mode;
reg pio_out_pll_reset;
reg pio_out_sw_reset;
reg [9:0] reset_count;
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= 10'b0;
else if (pio_out_sw_reset)
reset_count <= 10'b0;
else if (!reset_count[9])
reset_count <= reset_count + 2'b01;
// false paths set for pio_out_*
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_out_*]\"" *)
always@(posedge clk)
begin
pio_out_ddr_mode = pio_out[9:8];
pio_out_pll_reset = pio_out[30];
pio_out_sw_reset = pio_out[31];
end
// false paths for pio_in - these are asynchronous
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *pio_in*]\"" *)
always@(posedge clk)
begin
pio_in = {
lock_kernel_pll,
fixedclk_locked,
1'b0,
1'b0,
mem1_local_cal_fail,
mem0_local_cal_fail,
mem1_local_cal_success,
mem1_local_init_done,
mem0_local_cal_success,
mem0_local_init_done};
end
(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -from [get_registers *mem_organization*]\"" *)
always@(posedge clk)
mem_organization = pio_out_ddr_mode;
assign mem_organization_export = mem_organization;
assign pll_reset = pio_out_pll_reset;
// Export sw kernel reset out of iface to connect to kernel
always@(posedge clk)
sw_reset_n_out = !(!reset_count[9] && (reset_count[8:0] != 0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_1_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_1_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog wrapper for schmittbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__schmittbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_1_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file program_memory.v when simulating
// the core, program_memory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module program_memory(
clka,
addra,
douta
);
input clka;
input [8 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("program_memory.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
module spdif_dai_varclk #(
parameter MIN_CLK_PER_HALFBIT = 4,
parameter MAX_CLK_PER_HALFBIT = 31,
parameter MAX_CLK_PER_HALFBIT_LOG2 = 5, // 32 max
parameter NUM_RATE = 5
)(
input wire clk,
input wire rst,
input wire signal_i,
output wire [23:0] data_o,
output wire ack_o,
output wire locked_o,
output wire rst_o,
output wire lrck_o,
output wire [191:0] udata_o,
output wire [191:0] cdata_o,
output wire [(NUM_RATE-1):0] rate_o);
wire [(MAX_CLK_PER_HALFBIT_LOG2-1):0] clk_per_halfbit;
wire locked;
spdif_dai #(
.MAX_CLK_PER_HALFBIT_LOG2(MAX_CLK_PER_HALFBIT_LOG2)
) dai_fixedclk(
.clk(clk),
.rst(rst),
.clk_per_halfbit(clk_per_halfbit),
.signal_i(signal_i),
.data_o(data_o),
.ack_o(ack_o),
.locked_o(locked),
.lrck_o(lrck_o),
.udata_o(udata_o),
.cdata_o(cdata_o));
assign locked_o = locked;
reg last_locked_ff;
always @(posedge clk)
last_locked_ff <= locked;
assign rst_o = !last_locked_ff && locked;
reg [13:0] unlocked_duration_counter;
wire unlocked_for_longtime = unlocked_duration_counter == 14'h3fff;
always @(posedge clk) begin
if(rst || locked)
unlocked_duration_counter <= 0;
else if(!locked)
unlocked_duration_counter <= unlocked_duration_counter + 1;
end
reg [(NUM_RATE-1):0] rate_ff;
parameter RATE_32 = 0;
parameter RATE_441 = 1;
parameter RATE_48 = 2;
parameter RATE_96 = 3;
parameter RATE_192 = 4;
always @(posedge clk) begin
if (rst)
rate_ff <= 5'd1 << RATE_192;
else if(unlocked_for_longtime || (last_locked_ff && !locked)) begin
if(rate_ff == (5'd1 << RATE_32))
rate_ff <= 5'd1 << RATE_192;
else
rate_ff <= {1'b0, rate_ff[(NUM_RATE-1):1]}; // shr
end
end
assign rate_o = rate_ff;
reg [(MAX_CLK_PER_HALFBIT_LOG2-1):0] clk_per_halfbit_ff;
always @(posedge clk) begin
// sampling rate -> clk_per_halfbit
case (rate_ff)
5'd1 << RATE_32:
clk_per_halfbit_ff <= 5'd24;
5'd1 << RATE_441:
clk_per_halfbit_ff <= 5'd18; // or d18???
5'd1 << RATE_48:
clk_per_halfbit_ff <= 5'd16;
5'd1 << RATE_96:
clk_per_halfbit_ff <= 5'd8;
5'd1 << RATE_192:
clk_per_halfbit_ff <= 5'd4;
default:
clk_per_halfbit_ff <= 5'd4;
endcase
end
assign clk_per_halfbit = clk_per_halfbit_ff;
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (a % b != 0) return gcd(b, a % b); return b; } int main() { int n, x = 0, y = 0; cin >> n; string a, b; cin >> a >> b; int k = a.size() * b.size() / gcd(a.size(), b.size()); for (int i = 0; i < k; i++) { int t1 = i % a.size(), t2 = i % b.size(); if (a[t1] != b[t2]) { if ((a[t1] > b[t2] && a[t1] - b[t2] != 3) || b[t2] - a[t1] == 3) x++; else y++; } } x *= n / k; y *= n / k; n %= k; for (int i = 0; i < n; i++) { int t1 = i % a.size(), t2 = i % b.size(); if (a[t1] != b[t2]) { if ((a[t1] > b[t2] && a[t1] - b[t2] != 3) || b[t2] - a[t1] == 3) x++; else y++; } } cout << x << << y; }
|
#include <bits/stdc++.h> using namespace std; long long n, q, x, y, ans; int main() { cin >> n >> q; while (q--) { cin >> x >> y; ans = 0; if ((x & 1) == (y & 1)) { ans += (x - 1) / 2 * n; x = x % 2; if (x) ans += (y + 1) / 2; else ans += (y / 2) + (n / 2) + (n & 1); } else { ans += (n * n / 2) + (n & 1) + (x - 1) / 2 * n; x = x % 2; if (x) ans += y / 2; else ans += (n / 2) + (y + 1) / 2; } cout << ans << endl; } return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_pulse.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU noise channel.
***************************************************************************************************/
module apu_pulse
#(
parameter [0:0] CHANNEL = 1'b0 // Pulse channel 0 or 1
)
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] pulse_out, // pulse channel output
output wire active_out // pulse channel active (length counter > 0)
);
//
// Envelope
//
wire envelope_generator_wr;
wire envelope_generator_restart;
wire [3:0] envelope_generator_out;
apu_envelope_generator envelope_generator(
.clk_in(clk_in),
.rst_in(rst_in),
.eg_pulse_in(eg_pulse_in),
.env_in(d_in[5:0]),
.env_wr_in(envelope_generator_wr),
.env_restart(envelope_generator_restart),
.env_out(envelope_generator_out)
);
assign envelope_generator_wr = wr_in && (a_in == 2'b00);
assign envelope_generator_restart = wr_in && (a_in == 2'b11);
//
// Timer
//
reg [10:0] q_timer_period, d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(12)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in({ q_timer_period, 1'b0 }),
.pulse_out(timer_pulse)
);
//
// Sequencer
//
wire [3:0] sequencer_out;
reg [1:0] q_duty;
wire [1:0] d_duty;
reg [2:0] q_sequencer_cnt;
wire [2:0] d_sequencer_cnt;
wire seq_bit;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_duty <= 2'h0;
q_sequencer_cnt <= 3'h0;
end
else
begin
q_duty <= d_duty;
q_sequencer_cnt <= d_sequencer_cnt;
end
end
assign d_duty = (wr_in && (a_in == 2'b00)) ? d_in[7:6] : q_duty;
assign d_sequencer_cnt = (timer_pulse) ? q_sequencer_cnt - 3'h1 : q_sequencer_cnt;
assign seq_bit = (q_duty == 2'h0) ? &q_sequencer_cnt[2:0] :
(q_duty == 2'h1) ? &q_sequencer_cnt[2:1] :
(q_duty == 2'h2) ? q_sequencer_cnt[2] : ~&q_sequencer_cnt[2:1];
assign sequencer_out = (seq_bit) ? envelope_generator_out : 4'h0;
//
// Sweep
//
reg q_sweep_reload;
wire d_sweep_reload;
reg [7:0] q_sweep_reg;
wire [7:0] d_sweep_reg;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_sweep_reg <= 8'h00;
q_sweep_reload <= 1'b0;
end
else
begin
q_sweep_reg <= d_sweep_reg;
q_sweep_reload <= d_sweep_reload;
end
end
assign d_sweep_reg = (wr_in && (a_in == 2'b01)) ? d_in : q_sweep_reg;
assign d_sweep_reload = (wr_in && (a_in == 2'b01)) ? 1'b1 :
(lc_pulse_in) ? 1'b0 : q_sweep_reload;
wire sweep_divider_reload;
wire sweep_divider_pulse;
reg sweep_silence;
reg [11:0] sweep_target_period;
apu_div #(.PERIOD_BITS(3)) sweep_divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(lc_pulse_in),
.reload_in(sweep_divider_reload),
.period_in(q_sweep_reg[6:4]),
.pulse_out(sweep_divider_pulse)
);
assign sweep_divider_reload = lc_pulse_in & q_sweep_reload;
always @*
begin
sweep_target_period =
(!q_sweep_reg[3]) ? q_timer_period + (q_timer_period >> q_sweep_reg[2:0]) :
q_timer_period + ~(q_timer_period >> q_sweep_reg[2:0]) + CHANNEL;
sweep_silence = (q_timer_period[10:3] == 8'h00) || sweep_target_period[11];
if (wr_in && (a_in == 2'b10))
d_timer_period = { q_timer_period[10:8], d_in };
else if (wr_in && (a_in == 2'b11))
d_timer_period = { d_in[2:0], q_timer_period[7:0] };
else if (sweep_divider_pulse && q_sweep_reg[7] && !sweep_silence && (q_sweep_reg[2:0] != 3'h0))
d_timer_period = sweep_target_period[10:0];
else
d_timer_period = q_timer_period;
end
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_length_counter_halt <= 1'b0;
end
else
begin
q_length_counter_halt <= d_length_counter_halt;
end
end
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[5] : q_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign length_counter_wr = wr_in && (a_in == 2'b11);
assign pulse_out = (length_counter_en && !sweep_silence) ? sequencer_out : 4'h0;
assign active_out = length_counter_en;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 205; int n, siz[N], s[N][N], ori[N][N], tot[N], pos[N]; vector<int> ans; int read() { int x = 0, f = 1; char s; while ((s = getchar()) > 9 || s < 0 ) if (s == - ) f = -1; while (s >= 0 && s <= 9 ) x = (x << 1) + (x << 3) + (s ^ 48), s = getchar(); return x * f; } bool ok() { for (int i = 1; i <= n; ++i) if (tot[i]) return 0; return 1; } bool check() { int maxx; for (int i = 1; i <= n; ++i) pos[ans[n - i]] = i; for (int i = 1; i < n; ++i) { maxx = 0; for (int j = 1; j <= n; ++j) tot[j] = 0; for (int j = 1; j <= siz[i]; ++j) maxx = max(maxx, pos[ori[i][j]]), ++tot[ori[i][j]]; if (maxx - siz[i] + 1 < 1) return 0; for (int j = maxx; j >= maxx - siz[i] + 1; --j) if (!tot[ans[n - j]]) return 0; } return 1; } int main() { int x, sum; bool flag; for (int T = read(); T; --T) { n = read(); for (int i = 1; i < n; ++i) { siz[i] = read(); for (int j = 1; j <= siz[i]; ++j) ori[i][j] = read(); } for (int num = 1; num <= n; ++num) { ans.clear(); flag = 0; for (int i = 1; i < n; ++i) { for (int j = 1; j <= siz[i]; ++j) { s[i][j] = ori[i][j]; if (s[i][j] == num) s[i][j] = 0; } } while (233) { sum = 0; for (int i = 0; i <= n; ++i) tot[i] = 0; for (int i = 1; i < n; ++i) for (int j = 1; j <= siz[i]; ++j) ++tot[s[i][j]]; for (int i = 1; i <= n; ++i) if (tot[i] == 1) ++sum, x = i; if (ok()) break; if (sum != 1) { flag = 1; break; } ans.push_back(x); bool f; for (int i = 1; i < n; ++i) { f = 0; for (int j = 1; j <= siz[i]; ++j) if (s[i][j] == x) { f = 1; break; } if (f) for (int j = 1; j <= siz[i]; ++j) s[i][j] = 0; } } if (!flag) { ans.push_back(num); if (check()) break; } } for (int i = ans.size() - 1; ~i; --i) printf( %d , ans[i]); puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool fl, vis[200005]; int en, d[200005], head[200005]; struct edge { int u, v, w, nxt; } e[200005 * 4], e0[200005]; void dfs(int); void adde(int, int, int); int calc(int x) { int ans = 0; while (x) { ans ^= x & 1; x >>= 1; } return ans; } int main() { int i, k, t, n, m, u, v, w; scanf( %d , &t); while (t--) { scanf( %d %d , &n, &m); fl = 0; en = 0; memset(vis, 0, n + 1); memset(head, 0, 4 * (n + 1)); for (i = 1; i < n; ++i) { scanf( %d %d %d , &u, &v, &w); e0[i].u = u; e0[i].v = v; e0[i].w = w; if (w != -1) { k = calc(w); adde(u, v, k); adde(v, u, k); } } for (i = 1; i <= m; ++i) { scanf( %d %d %d , &u, &v, &w); adde(u, v, w); adde(v, u, w); } for (i = 1; i <= n; ++i) if (!vis[i]) { d[i] = 0; dfs(i); } if (fl) { puts( NO ); continue; } for (i = 1; i < n; ++i) if (e0[i].w == -1) { u = e0[i].u; v = e0[i].v; if (d[u] == d[v]) e0[i].w = 0; else e0[i].w = 1; } puts( YES ); for (i = 1; i < n; ++i) printf( %d %d %d n , e0[i].u, e0[i].v, e0[i].w); } return 0; } void dfs(int u) { int i, v; vis[u] = 1; for (i = head[u]; i; i = e[i].nxt) if (!vis[v = e[i].v]) { d[v] = (d[u] ^ e[i].w); dfs(v); } else fl |= d[v] != (d[u] ^ e[i].w); } void adde(int u, int v, int w) { e[++en].v = v; e[en].w = w; e[en].nxt = head[u]; head[u] = en; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
typedef enum int {
PADTYPE_DEFAULT = 32'd0,
PADTYPE_GPIO,
PADTYPE_VDD,
PADTYPE_GND
} t_padtype;
localparam int STR_PINID [0:15]
= '{
"DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR",
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7"
};
typedef struct packed {
t_padtype padtype;
int aux;
} t_pin_descriptor;
localparam t_pin_descriptor
PINOUT[ 1: 6]
= '{
'{default:0, padtype:PADTYPE_GPIO, aux:1},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_VDD},
'{default:0, padtype:PADTYPE_GND}
};
localparam int PINOUT_SIZE = 6;
localparam int PINOUT_WA[1:PINOUT_SIZE][3]
= '{
'{0, PADTYPE_GPIO, 0},
'{1, PADTYPE_GPIO, 0},
'{2, PADTYPE_GPIO, 0},
'{5, PADTYPE_GPIO, 0},
'{6, PADTYPE_VDD, 0},
'{8, PADTYPE_GND , 0}
};
const int pinout_static_const[1:PINOUT_SIZE][3]
= '{
'{0, PADTYPE_GPIO, 0},
'{1, PADTYPE_GPIO, 0},
'{2, PADTYPE_GPIO, 0},
'{5, PADTYPE_GPIO, 0},
'{6, PADTYPE_VDD, 0},
'{8, PADTYPE_GND , 0}
};
// Make sure consants propagate
checkstr #(.PINID(STR_PINID[1]),
.EXP("ERR"))
substr1 ();
checkstr #(.PINID(STR_PINID[8]),
.EXP("PA0"))
substr8 ();
initial begin
$display("PINID1 %s", STR_PINID[1]);
$display("PINID8 %s", STR_PINID[8]);
if (STR_PINID[1] != "ERR") $stop;
if (STR_PINID[8] != "PA0") $stop;
if (pinout_static_const[1][0] != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module checkstr;
parameter int PINID = " ";
parameter int EXP = " ";
initial begin
$display("PID %s EXP %s", PINID, EXP);
if (EXP != "ERR" && EXP != "PA0") $stop;
if (PINID != EXP) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mmax = 1e6 + 10; const int eps = 1e-9; struct node { string name; } s[105]; long long cmp(node a, node b) { if (a.name == b.name) return a.name < b.name; return a.name < b.name; } int main() { long long n; while (cin >> n) { for (int i = 0; i < n; i++) { cin >> s[i].name; } sort(s, s + n, cmp); long long ans = 0, sum = 0; for (int i = 0; i < n; i++) { if (s[i].name[0] == s[i + 1].name[0]) ans++; else { long long num0 = (ans + 1) / 2; long long num1 = ans + 1 - num0; long long sum0 = 0, sum1 = 0; for (int i = 1; i < num0; i++) sum0 += i; for (int i = 1; i < num1; i++) sum1 += i; sum += (sum0 + sum1); ans = 0; } } cout << sum << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long double PI = 3.14159265359; long long inf = 1000000000000000007; long long mod = 1000000007; long long mod1 = 998244353; const bool multi = 0; long long DP[500007]; long long s[500007]; vector<long long> G[500007]; long long ans = inf, n; void dfs(long long v, long long o) { s[v] = 1; vector<pair<pair<long long, long long>, long long>> DPs; DP[v] = inf; if ((long long)(G[v]).size() == 1) DP[v] = 0; long long sum = 0; for (auto u : G[v]) { if (u == o) continue; dfs(u, v); s[v] += s[u]; DPs.push_back({{-2 * s[u], 2 * DP[u] + s[u] * (s[u] + 1)}, u}); } sort(DPs.begin(), DPs.end()); vector<pair<long long, long long>> CHT; for (auto x : DPs) { long long l = 0, r = (long long)(CHT).size() - 1, sr; long long S = n - s[x.second]; ans = min(ans, 2 * DP[x.second] + (n - s[x.second]) * (n - s[x.second] - 1)); while (l <= r) { sr = (l + r) / 2; long long L = 2 * DP[x.second] + S * (S - 1) + S * CHT[sr].first + CHT[sr].second; ans = min(ans, L); if (sr + 1 == (long long)(CHT).size()) break; long long R = 2 * DP[x.second] + S * (S - 1) + S * CHT[sr + 1].first + CHT[sr + 1].second; ans = min(ans, R); if (L <= R) r = sr - 1; else l = sr + 1; } if ((long long)(CHT).size() == 0 || x.first.first != CHT.back().first) CHT.push_back({x.first.first, x.first.second}); DP[v] = min(DP[v], DP[x.second] + (s[v] - s[x.second]) * (s[v] - s[x.second] - 1) / 2); } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long tt; if (multi) cin >> tt; else tt = 1; while (tt--) { long long a, b; cin >> n; for (long long i = 1; i < n; i++) { cin >> a >> b; G[a].push_back(b); G[b].push_back(a); } dfs(1, -1); ans /= 2; cout << ans + 2 * (n * (n - 1) / 2 - ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[10][10], b[10][10]; struct per { int x, y; }; int k; queue<per> q, q2; void bf2() { while (!q2.empty()) { per aux; aux = q2.front(); q2.pop(); int xx = aux.x - 1, yy = aux.y - 1; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x - 1, yy = aux.y; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x - 1, yy = aux.y + 1; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x, yy = aux.y - 1; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x, yy = aux.y + 1; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x + 1, yy = aux.y - 1; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x + 1, yy = aux.y + 1; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } xx = aux.x + 1, yy = aux.y; if (b[xx][yy] == 0) { b[xx][yy] = b[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; q2.push(nou); } } } void bf1() { while (!q.empty()) { per aux; aux = q.front(); q.pop(); int xx = aux.x - 1, yy = aux.y - 1; while (a[xx][yy] == 0) { a[xx][yy] = a[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; xx--; yy--; q.push(nou); } xx = aux.x - 1, yy = aux.y + 1; while (a[xx][yy] == 0) { a[xx][yy] = a[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; xx--; yy++; q.push(nou); } xx = aux.x + 1, yy = aux.y + 1; while (a[xx][yy] == 0) { a[xx][yy] = a[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; xx++; yy++; q.push(nou); } xx = aux.x + 1, yy = aux.y - 1; while (a[xx][yy] == 0) { a[xx][yy] = a[aux.x][aux.y] + 1; per nou; nou.x = xx; nou.y = yy; xx++; yy--; q.push(nou); } } } int main() { int x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; if (x1 == x2 || y1 == y2) cout << 1 << ; else cout << 2 << ; int i; for (i = 0; i <= 9; i++) { a[i][0] = -1; a[i][9] = -1; a[0][i] = -1; a[9][i] = -1; b[i][0] = -1; b[i][9] = -1; b[0][i] = -1; b[9][i] = -1; } per st; st.x = x1; st.y = y1; q.push(st); a[x1][y1] = 1; bf1(); if (a[x2][y2]) cout << a[x2][y2] - 1; else cout << 0; cout << ; int j; b[x1][y1] = 1; q2.push(st); bf2(); if (b[x2][y2]) cout << b[x2][y2] - 1; else cout << 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool alph[26] = {1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0}; bool check(string s) { for (int i = 0; i < s.length(); i++) if (!alph[s[i] - A ]) return false; return true; } int main() { string s; cin >> s; string t = s; reverse(s.begin(), s.end()); if (s == t && check(s)) cout << YES ; else cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR4_PP_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, p, k; int a[333333]; long long ans; map<int, int> mp, mpb; int main() { scanf( %d%d%d , &n, &p, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { mp[a[i]]++; } for (map<int, int>::iterator it = mp.begin(); it != mp.end(); it++) { if (1ll * ((it->first) + (it->first)) * (2ll * (it->first) * (it->first) % p) % p != k) ans -= (1ll * (it->second) * ((it->second) - 1)); } for (int i = 1; i <= n; i++) { mpb[((1ll * a[i] * a[i] % p * a[i] % p * a[i] - 1ll * k * a[i]) % p + p) % p]++; } for (map<int, int>::iterator it = mpb.begin(); it != mpb.end(); it++) { ans += (1ll * (it->second) * ((it->second) - 1)); } printf( %lld n , ans / 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; std::mt19937 rnd( (int)std::chrono::steady_clock::now().time_since_epoch().count()); long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int NDIG = 6; const int MAXQ = 100000; const int MAXSUM = 999999; int nvals; int gain[NDIG]; int nq; int q[MAXQ]; long long qans[MAXQ]; long long dp[NDIG + 1][MAXSUM + 1]; long long tmp[MAXSUM + 1]; pair<long long, int> qq[MAXSUM + 1]; int qhead, qtail; void solve() { for (int ndig = (0); ndig <= (NDIG); ++ndig) for (int sum = (0); sum <= (MAXSUM); ++sum) dp[ndig][sum] = ndig == 0 && sum == 0 ? 0 : LLONG_MIN; for (int ndig = (1); ndig <= (NDIG); ++ndig) { int curgain = gain[NDIG - ndig]; long long vargain = (long long)10 * curgain; for (int sum = (0); sum <= (MAXSUM); ++sum) tmp[sum] = dp[ndig - 1][sum] == LLONG_MIN ? LLONG_MIN : dp[ndig - 1][sum] - (sum / 3) * vargain; for (int mod = (0); mod < (30); ++mod) if (mod <= 9 * nvals) { long long fixedgain = (long long)(mod / 3) * curgain; qhead = qtail = 0; for (int sum = mod; sum <= MAXSUM; sum += 10) { int fst = (sum - mod) / 10; int qmx = min((sum - mod) / 30, (9 * nvals - mod) / 30); long long now = tmp[fst]; while (qtail < qhead && now >= qq[qhead - 1].first) --qhead; qq[qhead++] = make_pair(now, fst); while (qtail < qhead && qq[qtail].second < fst - (qmx - 10)) ++qtail; long long best = qtail < qhead ? qq[qtail].first : LLONG_MIN; if (best != LLONG_MIN) { dp[ndig][sum] = max(dp[ndig][sum], best + fixedgain + (fst / 3) * vargain); } for (int q = (max(0, qmx - 10)); q <= (qmx); ++q) { long long opt = dp[ndig - 1][fst - 3 * q]; if (opt == LLONG_MIN) continue; int nthree = mod / 3 + 10 * q; opt += fixedgain + q * vargain; if (nthree >= 3 * (nvals - 1) && mod % 3 != 0) opt -= (long long)(nthree - 3 * (nvals - 1)) * curgain; dp[ndig][sum] = max(dp[ndig][sum], opt); } } } } for (int i = (0); i < (nq); ++i) qans[i] = dp[NDIG][q[i]]; } void run() { scanf( %d , &nvals); for (int i = (0); i < (NDIG); ++i) scanf( %d , &gain[i]); scanf( %d , &nq); for (int i = (0); i < (nq); ++i) scanf( %d , &q[i]); solve(); for (int i = (0); i < (nq); ++i) printf( %lld n , qans[i]); } long long qansstupid[MAXQ]; void solvestupid() { auto calc = [&](int x) { long long ret = 0; for (int i = 0; x > 0; ++i, x /= 10) if (x % 10 % 3 == 0) ret += (long long)(x % 10 / 3) * gain[i]; return ret; }; for (int i = (0); i < (nq); ++i) { int sum = q[i]; qansstupid[i] = LLONG_MIN; if (nvals == 4) { for (int a = (0); a <= (sum); ++a) for (int b = (0); b <= (sum - a); ++b) for (int c = (0); c <= (sum - a - b); ++c) { int d = sum - a - b - c; long long cur = calc(a) + calc(b) + calc(c) + calc(d); qansstupid[i] = max(qansstupid[i], cur); } } else if (nvals == 3) { for (int a = (0); a <= (sum); ++a) for (int b = (0); b <= (sum - a); ++b) { int c = sum - a - b; long long cur = calc(a) + calc(b) + calc(c); qansstupid[i] = max(qansstupid[i], cur); } } else if (nvals == 2) { for (int a = (0); a <= (sum); ++a) { int b = sum - a; long long cur = calc(a) + calc(b); qansstupid[i] = max(qansstupid[i], cur); } } else if (nvals == 1) { int a = sum; long long cur = calc(a); qansstupid[i] = max(qansstupid[i], cur); } else { assert(false); } } } void stress() { for (int rep = (0); rep < (1000); ++rep) { nvals = rnd() % 4 + 1; int sum = rnd() % (nvals == 4 ? 100 : 10000) + 1; for (int i = (0); i < (NDIG); ++i) gain[i] = rnd() % 1000 + 1; nq = 1, q[0] = sum; solve(); solvestupid(); bool ok = true; for (int i = (0); i < (nq); ++i) if (qans[i] != qansstupid[i]) ok = false; if (ok) { printf( . ); continue; } printf( err have=%lld want=%lld n , qans[0], qansstupid[0]); printf( %d n , nvals); for (int i = (0); i < (NDIG); ++i) { if (i != 0) printf( ); printf( %d , gain[i]); } puts( ); printf( %d n , nq); for (int i = (0); i < (nq); ++i) printf( %d n , q[i]); } } int main() { run(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; long long int a[n + 1]; for (long long int i = 1; i <= n; i++) { cin >> a[i]; } long long int f = 0; for (long long int i = 1; i <= n; i++) { for (long long int j = 1; j <= n; j++) { if (j != i) { for (long long int k = 1; k <= n; k++) { if (k != j) { if (a[i] == a[j] + a[k]) { f = 1; cout << i << << j << << k << endl; break; } } } if (f) { break; } } } if (f) { break; } } if (f == 0) { cout << -1; } return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:48:32 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_0_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_0_V
`define SKY130_FD_SC_LP__A211O_0_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211o_0 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211o_0 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_0_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, i, min1, min2, max1, max2, a[10000], b[10000]; cin >> n; t = n; while (n--) { cin >> a[i] >> b[i]; i++; } max1 = a[0]; max2 = b[0]; min1 = a[0]; min2 = b[0]; for (i = 0; i < t; i++) { if (a[i] > max1) max1 = a[i]; if (b[i] > max2) max2 = b[i]; if (a[i] <= min1) min1 = a[i]; if (b[i] <= min2) min2 = b[i]; } max1 = max1 - min1; max2 = max2 - min2; if (max1 >= max2) cout << max1 * max1; else cout << max2 * max2; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; int minn[MAX], maxx[MAX], h[MAX]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> h[i]; int block = 1; minn[1] = h[1]; maxx[1] = h[1]; for (int i = 2; i <= n; ++i) { if (maxx[block] <= h[i]) { block++; minn[block] = h[i]; maxx[block] = h[i]; } else { minn[block] = min(minn[block], h[i]); maxx[block] = max(maxx[block], h[i]); while (block > 1 && maxx[block - 1] > minn[block]) { --block; minn[block] = min(minn[block], minn[block + 1]); maxx[block] = max(maxx[block], maxx[block + 1]); } } } cout << block; return 0; }
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: datamux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module datamux (
aclr,
clock,
data0x,
data1x,
data2x,
data3x,
sel,
result);
input aclr;
input clock;
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire5 = data3x[7:0];
wire [7:0] sub_wire4 = data2x[7:0];
wire [7:0] sub_wire3 = data1x[7:0];
wire [7:0] result = sub_wire0[7:0];
wire [7:0] sub_wire1 = data0x[7:0];
wire [31:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
lpm_mux LPM_MUX_component (
.aclr (aclr),
.clock (clock),
.data (sub_wire2),
.sel (sel),
.result (sub_wire0)
// synopsys translate_off
,
.clken ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_pipeline = 1,
LPM_MUX_component.lpm_size = 4,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 8,
LPM_MUX_component.lpm_widths = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
// Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
// Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
// Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data0x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 8 data1x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 16 data2x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 24 data3x 0 0 8 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; template <typename T> void deb(T v[], long long n) { if (false) cerr << ARRAY : ; long long i; for (i = 0; i < n; i++) if (false) cerr << v[i] << ; if (false) cerr << endl; } template <typename T> void deb(set<T> s) { if (false) cerr << SET : ; for (auto it : s) if (false) cerr << it << ; if (false) cerr << endl; } template <typename T> void deb(vector<T> v) { if (false) cerr << VECTOR : ; long long i; for (i = 0; i < v.size(); i++) if (false) cerr << v[i] << ; if (false) cerr << endl; } template <typename T> void deb(stack<T> s) { if (false) cerr << STACK : ; stack<T> st = s; while (st.size()) { if (false) cerr << st.top() << ; st.pop(); }; if (false) cerr << endl; } template <typename T> void deb(queue<T> q) { if (false) cerr << Queue : ; queue<T> qq = q; while (qq.size()) { if (false) cerr << qq.front() << ; qq.pop(); }; if (false) cerr << endl; } void deb(map<long long, long long> m) { if (false) cerr << MAP : ; for (auto it : m) if (false) cerr << it.first << : << it.second << endl; } void deb(unordered_map<long long, long long> m) { if (false) cerr << MAP : ; for (auto it : m) if (false) cerr << it.first << : << it.second << endl; } template <typename T> T abs(T a) { return a < 0 ? a * -1 : a; } void swap(long long &x, long long &y); bool isPrime(long long n); long long power(long long x, long long y, long long p); long long gcdExtended(long long a, long long b, long long *x, long long *y); long long modInverse(long long b, long long m); long long modDivide(long long a, long long b, long long m); void simpleSieve(long long N, bool[]); void PrimeDivisorSieve(long long N, long long prime[]); class nCrModPClass { public: vector<long long> f, fi; long long N; long long MOD; long long poww(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans; } long long modinvv(long long k) { return poww(k, MOD - 2, MOD); } nCrModPClass(long long size, long long mod) { MOD = mod; N = size + 10; f.resize(N); fi.resize(N); f[0] = f[1] = 1; for (long long i = 2; i < N; i++) f[i] = (f[i - 1] * i) % MOD; fi[N - 1] = modinvv(f[N - 1]); for (long long i = N - 2; i >= 0; i--) fi[i] = (fi[i + 1] * (i + 1)) % MOD; } long long nCrModPfromClass(long long n, long long r) { if (r > n) return 0; long long ret = f[n]; ret %= MOD; ret *= fi[r]; ret %= MOD; ret *= fi[n - r]; ret %= MOD; return ret; } }; long long testCases; long long minTocs(string a, char c) { if (a.length() == 1) { return a[0] != c; } string lef, rig; long long dlef, drig; dlef = drig = 0; for (long long i = 0; i < a.length() / 2; i++) { dlef += a[i] != c; lef += a[i]; } for (long long i = a.length() / 2; i < a.length(); i++) { drig += a[i] != c; rig += a[i]; } return min(dlef + minTocs(rig, (char)c + 1), minTocs(lef, (char)c + 1) + drig); } int main() { testCases = 1; cin >> testCases; while (testCases--) { long long n; cin >> n; string s; cin >> s; cout << minTocs(s, a ) << endl; } return 0; } void simpleSieve(long long N, bool prime[]) { long long i, j; for (i = 0; i < N + 1; i++) prime[i] = true; for (i = 2; i * i <= N; i++) { if (prime[i]) { for (j = i * i; j <= N; j += i) { prime[j] = false; } } } } void PrimeDivisorSieve(long long N, long long prime[]) { long long i, j; for (i = 0; i < N + 1; i++) prime[i] = i; for (i = 2; i * i <= N; i++) { if (prime[i] == i) { for (j = i; j <= N; j += i) { if (prime[j] == j) prime[j] = i; } } } } void swap(long long &x, long long &y) { x ^= y; y ^= x; x ^= y; } bool isPrime(long long n) { if (n <= 1) return false; for (long long i = 2; i < n; i++) if (n % i == 0) return false; return true; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long modInverse(long long b, long long m) { long long x, y; long long g = gcdExtended(b, m, &x, &y); if (g != 1) return -1; return (x % m + m) % m; } long long modDivide(long long a, long long b, long long m) { a = a % m; long long inv = modInverse(b, m); if (inv == -1) return -1; else return (inv * a) % m; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 7; const int M = 2e6 + 7; const int lim = 1e6; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; long long ksm(long long a, long long b, long long p) { long long ret = 1; while (b) { if (b & 1) (ret *= a) %= p; (a *= a) %= p; b >>= 1; } return ret; } long long inv(long long x) { return ksm(x, mod - 2, mod); } int main() { long long k, x, a = 1, b = 1, f1 = 0, f2 = 0; scanf( %lld , &k); for (int i = 1; i <= k; i++) { scanf( %lld , &x); if (x % 2 == 0) f1 = 1; if (x == 0) f2 = 1; (b *= x % (mod - 1)) %= mod - 1; (a *= x % 2) %= 2; } b = (b - 1 + mod - 1) % (mod - 1); long long bb = ksm(2, b, mod); if (f1 == 0) f1 = -1; long long aa = (bb + f1 + mod) % mod, t = ksm(2, (a - 1 + 2) % 2, 3); t = (t + f1 + 3) % 3; if (t == 0) aa = aa * inv(3) % mod; else bb *= 3; printf( %lld/%lld n , aa, bb); return 0; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//
//-------------------------------------------------------------------
//
// Filename : fme_pred.v
// Author : Yufeng Bai
// Email :
// Created On : 2014-12-24
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_pred (
clk ,
rstn ,
ip_start_i ,
end_ip_i ,
imv_x_i ,
imv_y_i ,
fmv_x_i ,
fmv_y_i ,
block_idx_i ,
candi0_valid_i ,
candi1_valid_i ,
candi2_valid_i ,
candi3_valid_i ,
candi4_valid_i ,
candi5_valid_i ,
candi6_valid_i ,
candi7_valid_i ,
candi8_valid_i ,
candi0_pixles_i ,
candi1_pixles_i ,
candi2_pixles_i ,
candi3_pixles_i ,
candi4_pixles_i ,
candi5_pixles_i ,
candi6_pixles_i ,
candi7_pixles_i ,
candi8_pixles_i ,
pred_pixel_o ,
pred_wren_o ,
pred_addr_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] ip_start_i ; // 8x8 block ip start signal
input [1-1:0] end_ip_i ; // 8x8 block ip done
input [`FMV_WIDTH-1:0] imv_x_i ; // imv x
input [`FMV_WIDTH-1:0] imv_y_i ; // imv y
input [`FMV_WIDTH-1:0] fmv_x_i ; // fmv x
input [`FMV_WIDTH-1:0] fmv_y_i ; // fmv y
input [6-1:0] block_idx_i ; // processing block index
input [1-1:0] candi0_valid_i ; // candidate 0 row pixels valid
input [1-1:0] candi1_valid_i ; // candidate 1 row pixels valid
input [1-1:0] candi2_valid_i ; // candidate 2 row pixels valid
input [1-1:0] candi3_valid_i ; // candidate 3 row pixels valid
input [1-1:0] candi4_valid_i ; // candidate 4 row pixels valid
input [1-1:0] candi5_valid_i ; // candidate 5 row pixels valid
input [1-1:0] candi6_valid_i ; // candidate 6 row pixels valid
input [1-1:0] candi7_valid_i ; // candidate 7 row pixels valid
input [1-1:0] candi8_valid_i ; // candidate 8 row pixels valid
input [`PIXEL_WIDTH*8-1:0] candi0_pixles_i ; // candidate 0 row pixels
input [`PIXEL_WIDTH*8-1:0] candi1_pixles_i ; // candidate 1 row pixels
input [`PIXEL_WIDTH*8-1:0] candi2_pixles_i ; // candidate 2 row pixels
input [`PIXEL_WIDTH*8-1:0] candi3_pixles_i ; // candidate 3 row pixels
input [`PIXEL_WIDTH*8-1:0] candi4_pixles_i ; // candidate 4 row pixels
input [`PIXEL_WIDTH*8-1:0] candi5_pixles_i ; // candidate 5 row pixels
input [`PIXEL_WIDTH*8-1:0] candi6_pixles_i ; // candidate 6 row pixels
input [`PIXEL_WIDTH*8-1:0] candi7_pixles_i ; // candidate 7 row pixels
input [`PIXEL_WIDTH*8-1:0] candi8_pixles_i ; // candidate 8 row pixels
output [`PIXEL_WIDTH*32-1:0] pred_pixel_o ; // fme predicted pixels data
output [4-1:0] pred_wren_o ; // predicted pixels valid
output [7-1:0] pred_addr_o ; // 8x8 block y position in lcu
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
wire signed [3-1 :0] dmv_x, dmv_y;
wire signed [3-1 :0] frac_x, frac_y;
wire [4-1 :0] best_candi;
reg [4-1 :0] best_r0, best_r1;
reg [6-1 :0] idx_r0, idx_r1;
wire [4-1 :0] best;
reg flag,flag_out;
wire [2-1 :0] cnt32, cnt16, cnt08;
reg [8*`PIXEL_WIDTH-1:0] predicted_pixel_o;
reg [1-1 :0] predicted_valid_o;
reg [3-1:0] predicted_cnt_o ; // predicted pixels counter
reg [4-1:0] pred_wren_o ; // predicted pixels valid
reg [`PIXEL_WIDTH*32-1:0] pred_pixel_o ; // fme predicted pixels data
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign dmv_x = fmv_x_i - imv_x_i;
assign dmv_y = fmv_y_i - imv_y_i;
assign frac_x = (dmv_x == 0) ? 3'b000 : ((dmv_x < 0 ) ? 3'b110 : 3'b010); // frac < 0: -2 ; frac > 0 : +2 ; frac == 0: 0
assign frac_y = (dmv_y == 0) ? 3'b000 : ((dmv_y < 0 ) ? 3'b110 : 3'b010); // frac < 0: -2 ; frac > 0 : +2 ; frac == 0: 0
assign best_candi = (dmv_y - frac_y + 1) * 3 + (dmv_x - frac_x) + 1;
assign best = (flag_out) ? best_r1 : best_r0;
assign {cnt32,cnt16,cnt08} = (flag_out) ? idx_r1: idx_r0;
always @ (*) begin
case(best)
4'd0 : begin predicted_pixel_o = candi0_pixles_i; predicted_valid_o = candi0_valid_i; end
4'd1 : begin predicted_pixel_o = candi1_pixles_i; predicted_valid_o = candi1_valid_i; end
4'd2 : begin predicted_pixel_o = candi2_pixles_i; predicted_valid_o = candi2_valid_i; end
4'd3 : begin predicted_pixel_o = candi3_pixles_i; predicted_valid_o = candi3_valid_i; end
4'd4 : begin predicted_pixel_o = candi4_pixles_i; predicted_valid_o = candi4_valid_i; end
4'd5 : begin predicted_pixel_o = candi5_pixles_i; predicted_valid_o = candi5_valid_i; end
4'd6 : begin predicted_pixel_o = candi6_pixles_i; predicted_valid_o = candi6_valid_i; end
4'd7 : begin predicted_pixel_o = candi7_pixles_i; predicted_valid_o = candi7_valid_i; end
4'd8 : begin predicted_pixel_o = candi8_pixles_i; predicted_valid_o = candi8_valid_i; end
default: begin predicted_pixel_o = candi4_pixles_i; predicted_valid_o = candi4_valid_i; end
endcase
end
//assign pre_lcu_x_o = {cnt32[0], cnt16[0], cnt08[0]};
//assign pre_lcu_y_o = {cnt32[1], cnt16[1], cnt08[1]};
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
best_r0 <= 'd0;
best_r1 <= 'd0;
idx_r0 <= 'd0;
idx_r1 <= 'd0;
flag <= 'd0;
end
else if(ip_start_i) begin
flag <= ~flag;
if(~flag) begin
best_r0 <= best_candi;
idx_r0 <= block_idx_i;
end
else begin
best_r1 <= best_candi;
idx_r1 <= block_idx_i;
end
end
end
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
flag_out <= 1'b0;
end
else if (end_ip_i) begin
flag_out <= ~flag_out;
end
end
always @(posedge clk or negedge rstn) begin
if(~rstn) begin
predicted_cnt_o <= 'd0;
end
else if (predicted_valid_o) begin
predicted_cnt_o <= predicted_cnt_o + 'd1;
end
end
assign pred_addr_o = {cnt32[1], cnt32[0], cnt16[1], cnt08[1], predicted_cnt_o};
always @ (*) begin
case({cnt16[0],cnt08[0]})
2'b00: begin pred_pixel_o = { predicted_pixel_o , 64'b0, 64'b0, 64'b0 }; pred_wren_o = 4'b1000 & {4{predicted_valid_o}}; end
2'b01: begin pred_pixel_o = { 64'b0, predicted_pixel_o , 64'b0, 64'b0 }; pred_wren_o = 4'b0100 & {4{predicted_valid_o}}; end
2'b10: begin pred_pixel_o = { 64'b0, 64'b0, predicted_pixel_o , 64'b0 }; pred_wren_o = 4'b0010 & {4{predicted_valid_o}}; end
2'b11: begin pred_pixel_o = { 64'b0, 64'b0, 64'b0, predicted_pixel_o }; pred_wren_o = 4'b0001 & {4{predicted_valid_o}}; end
endcase
end
endmodule
|
module node_router(clk, rst, Data_in_N, Data_in_S, Data_in_W, Data_in_E, Data_in_ready_N, Data_in_ready_S, Data_in_ready_W,
Data_in_ready_E, Data_out_N, Data_out_S, Data_out_W, Data_out_E,
Data_out_ready_N, Data_out_ready_S, Data_out_ready_W, Data_out_ready_E,
Data_in_valid_N, Data_in_valid_E, Data_in_valid_S, Data_in_valid_W,
Data_out_valid_N, Data_out_valid_S, Data_out_valid_W, Data_out_valid_E,
noc_locationx, noc_locationy);
parameter WIDTH=36;
parameter DEPTH=8;
parameter ADDR=4;
parameter lhsCount=5;
parameter rhsCount=5;
input clk;
input rst;
input [1:0] noc_locationx;
input [1:0] noc_locationy;
input [WIDTH-1:0] Data_in_N;
input [WIDTH-1:0] Data_in_S;
input [WIDTH-1:0] Data_in_W;
input [WIDTH-1:0] Data_in_E;
//input [WIDTH-1:0] Data_in_L;
input Data_in_ready_N;
input Data_in_ready_S;
input Data_in_ready_W;
input Data_in_ready_E;
//input Data_in_ready_L;
output [WIDTH-1:0] Data_out_N;
output [WIDTH-1:0] Data_out_S;
output [WIDTH-1:0] Data_out_W;
output [WIDTH-1:0] Data_out_E;
//output [WIDTH-1:0] Data_out_L;
output Data_out_ready_N;
output Data_out_ready_E;
output Data_out_ready_S;
output Data_out_ready_W;
//output Data_out_ready_L;
input Data_in_valid_N;
input Data_in_valid_E;
input Data_in_valid_S;
input Data_in_valid_W;
output Data_out_valid_N;
output Data_out_valid_E;
output Data_out_valid_S;
output Data_out_valid_W;
wire [4:0] Data_out_valid;
wire Valid_router2node;
assign Data_out_valid_N = Data_out_valid[0];
assign Data_out_valid_E = Data_out_valid[1] ;
assign Data_out_valid_S = Data_out_valid[2] ;
assign Data_out_valid_W = Data_out_valid[3] ;
assign Valid_router2node = Data_out_valid[4];
// Data_out_valid[4] should connect to the enbalein of PE
wire [31:0] Data_router2node;
wire [WIDTH-1:0] Data_router2node_36;
wire [31:0] Data_node2router;
wire [WIDTH-1:0] Data_node2router_36;
wire Ready_router2node;
wire Ready_node2router;
wire Valid_node2router;
wire [5*WIDTH-1:0] Data_out;
assign Data_out_N = Data_out[WIDTH-1:0];
assign Data_out_E = Data_out[2*WIDTH-1:WIDTH];
assign Data_out_S = Data_out[3*WIDTH-1:2*WIDTH];
assign Data_out_W = Data_out[4*WIDTH-1:3*WIDTH];
assign Data_router2node_36 = Data_out[5*WIDTH-1:4*WIDTH];
assign Data_router2node = Data_router2node_36[35:4];
wire [4:0] Data_out_ready;
assign Data_out_ready[0] = Data_out_ready_N;
assign Data_out_ready[1] = Data_out_ready_E;
assign Data_out_ready[2] = Data_out_ready_S;
assign Data_out_ready[3] = Data_out_ready_W;
assign Data_out_ready[4] = Ready_router2node;
wire [5*WIDTH-1:0] Data_in;
assign Data_in[WIDTH-1:0] = Data_in_N;
assign Data_in[2*WIDTH-1:WIDTH] = Data_in_E;
assign Data_in[3*WIDTH-1:2*WIDTH] = Data_in_S;
assign Data_in[4*WIDTH-1:3*WIDTH] = Data_in_W;
assign Data_in[5*WIDTH-1:4*WIDTH] = Data_node2router_36;
assign Data_node2router_36[35:4] = Data_node2router;
// Reducer location: 1101
assign Data_node2router_36[3:0] = (Valid_node2router==1 && (Data_node2router!=0))?4'b1101:4'b0000;
wire [4:0] Data_in_valid;
//assign Data_in_valid[4]
assign Data_in_valid[0] = Data_in_valid_N;
assign Data_in_valid[1] = Data_in_valid_E;
assign Data_in_valid[2] = Data_in_valid_S;
assign Data_in_valid[3] = Data_in_valid_W;
// Attention
assign Data_in_valid[4] = Valid_node2router;
//Connect to 'bustorouter_ready' of router
wire [4:0] Data_in_ready;
assign Data_in_ready[0] = Data_in_ready_N;
assign Data_in_ready[1] = Data_in_ready_E;
assign Data_in_ready[2] = Data_in_ready_S;
assign Data_in_ready[3] = Data_in_ready_W;
assign Data_in_ready[4] = Ready_node2router;
// Attention
//assign Ready_mapper2router = !Valid_mapper2router;
assign Ready_node2router = 1'bz;
router router0(
.clk(clk),
.reset_b(rst),
.bustorouter_data(Data_in),
.bustorouter_ready(Data_in_ready),
.bustorouter_valid(Data_in_valid),
.X(noc_locationx),
.Y(noc_locationy),
.routertobus_data(Data_out),
.routertobus_ready(),
.routertobus_valid(Data_out_valid)
);
node_noc node_noc0(
.clk(clk),
.rst(rst),
.data_in(Data_router2node),
.data_in_ready(Data_in_valid_W),
.fifo_in_ready(1'b1),
.data_out(Data_node2router),
.data_out_ready(data_out_ready)
);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA Top-level for the Xilinx synthesis.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 37 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------
`include "arch.v"
`include "timescale.v"
`include "openMSP430_defines.v"
module openMSP430_fpga (
// OUTPUTs
aclk_en, // ACLK enable
dbg_freeze, // Freeze peripherals
dbg_uart_txd, // Debug interface: UART TXD
irq_acc, // Interrupt request accepted (one-hot signal)
per_addr, // Peripheral address
per_din, // Peripheral data input
per_wen, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
smclk_en, // SMCLK enable
// INPUTs
dbg_uart_rxd, // Debug interface: UART RXD
dco_clk, // Fast oscillator (fast clock)
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
reset_n // Reset Pin (low active)
);
// OUTPUTs
//=========
output aclk_en; // ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_uart_txd; // Debug interface: UART TXD
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [7:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_wen; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output smclk_en; // SMCLK enable
// INPUTs
//=========
input dbg_uart_rxd; // Debug interface: UART RXD
input dco_clk; // Fast oscillator (fast clock)
input [13:0] irq; // Maskable interrupts
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input nmi; // Non-maskable interrupt (asynchronous)
input [15:0] per_dout; // Peripheral data output
input reset_n; // Reset Pin (active low)
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
wire mclk;
wire puc;
//=============================================================================
// 2) PROGRAM AND DATA MEMORIES
//=============================================================================
`ifdef CYCLONE_II
cyclone2_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
cyclone2_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef CYCLONE_III
cyclone3_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
cyclone3_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef CYCLONE_IV_GX
cyclone4gx_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
cyclone4gx_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef ARRIA_GX
arriagx_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
arriagx_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef ARRIA_II_GX
arria2gx_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
arria2gx_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef STRATIX
stratix_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
stratix_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef STRATIX_II
stratix2_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
stratix2_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
`ifdef STRATIX_III
stratix3_pmem pmem (.clock(mclk), .clken(~pmem_cen), .wren(~(&pmem_wen)), .byteena(~pmem_wen), .address(pmem_addr), .data(pmem_din), .q(pmem_dout));
stratix3_dmem dmem (.clock(mclk), .clken(~dmem_cen), .wren(~(&dmem_wen)), .byteena(~dmem_wen), .address(dmem_addr), .data(dmem_din), .q(dmem_dout));
`endif
//=============================================================================
// 3) OPENMSP430
//=============================================================================
openMSP430 openMSP430_0 (
// OUTPUTs
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc (puc), // Main system reset
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n) // Reset Pin (low active)
);
endmodule // openMSP430_fpga
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr ();
// Module supplies
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_LP_V
`define SKY130_FD_SC_LP__DFSTP_LP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_lp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_lp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_LP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1]) begin
byte_data_received <= {byte_data_received[6:0], MOSI};
end
if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive) begin
byte_cnt_r <= 16'h0000;
end else if(byte_received_sync) begin
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int lazy[maxn << 2]; int a[maxn], c[maxn]; void pushup(int l, int r, int rt) { lazy[rt << 1] = lazy[rt << 1 | 1] = lazy[rt]; lazy[rt] = 0; } void update(int L, int R, int c, int l, int r, int rt) { if (L <= l && R >= r) { lazy[rt] = c; return; } if (lazy[rt]) pushup(l, r, rt); if (L <= ((l + r) >> 1)) update(L, R, c, l, ((l + r) >> 1), rt << 1); if (R > ((l + r) >> 1)) update(L, R, c, ((l + r) >> 1) + 1, r, rt << 1 | 1); } void query(int l, int r, int rt) { if (l == r) { c[l] = lazy[rt]; return; } if (lazy[rt]) pushup(l, r, rt); query(l, ((l + r) >> 1), rt << 1); query(((l + r) >> 1) + 1, r, rt << 1 | 1); } struct T { int l, r; } b[maxn]; int main() { map<int, int> mp; int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { if (a[i] == 0) continue; if (mp[a[i]]) b[a[i]].r = i; else mp[a[i]] = 1, b[a[i]].l = i, b[a[i]].r = i; } for (int i = 1; i <= k; i++) { if (mp[i]) { update(b[i].l, b[i].r, i, 1, n, 1); } } query(1, n, 1); bool d = true; for (int i = 1; i <= n; i++) { if (c[i] != a[i] && a[i] != 0) d = false; } if (!d) { cout << NO << endl; return 0; } bool ff = true; for (int i = 1; i <= n; i++) { if (a[i] == k) ff = false; } if (ff) { bool dd = false; for (int i = 1; i <= n; i++) if (a[i] == 0) { dd = true; c[i] = k; break; } if (!dd) { cout << NO << endl; return 0; } } cout << YES << endl; for (int i = 1; i <= n; i++) { if (a[i] == 0 && c[i] == 0) { c[i] = 1; } cout << c[i] << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; struct fastIO { inline fastIO operator>>(int& num) { num = 0; char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); bool foo = 0; if (c == - ) { foo = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } if (foo) num = -num; return *this; } inline fastIO operator>>(long long& num) { num = 0; char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); bool foo = 0; if (c == - ) { foo = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { num = (num << 3) + (num << 1) + c - 0 ; c = getchar(); } if (foo) num = -num; return *this; } inline fastIO operator>>(float& num) { scanf( %f , &num); return *this; } inline fastIO operator>>(double& num) { scanf( %lf , &num); return *this; } inline fastIO operator>>(long double& num) { scanf( %Lf , &num); return *this; } inline fastIO operator>>(char& num) { num = getchar(); while (num == || num == n ) num = getchar(); return *this; } inline fastIO operator>>(char* num) { int cnt = 0; char c = getchar(); while (c == || c == n ) c = getchar(); while (c != && c != n ) { num[cnt++] = c; c = getchar(); } num[cnt] = 0; return *this; } inline fastIO operator>>(string& num) { cin >> num; return *this; } inline void printInt(const int& num) { if (num < 10) { putchar(num + 0 ); return; } printInt(num / 10); putchar((num % 10) + 0 ); } inline void printINT(const long long& num) { if (num < 10) { putchar(num + 0 ); return; } printINT(num / 10); putchar((num % 10) + 0 ); } inline fastIO operator<<(const int& num) { if (num < 0) putchar( - ), printInt(-num); else printInt(num); return *this; } inline fastIO operator<<(const long long& num) { if (num < 0) putchar( - ), printINT(-num); else printINT(num); return *this; } inline fastIO operator<<(const float& num) { printf( %.10f , num); return *this; } inline fastIO operator<<(const double& num) { printf( %.16lf , num); return *this; } inline fastIO operator<<(const long double& num) { printf( %.20Lf , num); return *this; } inline fastIO operator<<(const char& num) { putchar(num); return *this; } inline fastIO operator<<(const char* num) { for (int i = 0; num[i]; i++) putchar(num[i]); return *this; } inline fastIO operator<<(const string& num) { cout << num; return *this; } } fio; char s[1000005]; int fail[1000005]; int bz[1000005][25]; int n, k; int main() { fio >> n >> k; fio >> (s + 1); int fu = 0; fail[1] = 0; for (int i = 2; i <= n; i++) { while (fu && s[i] != s[fu + 1]) { fu = fail[fu]; } if (s[i] == s[fu + 1]) { fu++; } fail[i] = fu; } fail[0] = 0; for (int i = 0; i <= n; i++) { bz[i][0] = fail[i]; } for (int i = 1; i <= 20; i++) { for (int j = 0; j <= n; j++) { bz[j][i] = bz[bz[j][i - 1]][i - 1]; } } for (int i = 1; i <= n; i++) { int frm = (1LL * (k - 1) * i + k - 1) / k; int to = 1LL * k * i / (k + 1); int xx = i; for (int j = 20; j >= 0; j--) { if (bz[xx][j] > to) { xx = bz[xx][j]; } } xx = bz[xx][0]; if (frm <= xx && to >= xx) { fio << 1; } else { fio << 0; } } fio << n ; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: book.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module book (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/book.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/book.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/book.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL book.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_bit_synchronizer # (
parameter INITIALIZE = 5'b00000,
parameter FREQUENCY = 512
)(
input wire clk_in,
input wire i_in,
output wire o_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable clustering. Their GSR default values are provided by the INITIALIZE parameter.
(* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0];
(* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1];
(* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2];
(* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3];
reg i_in_out = INITIALIZE[4];
always @(posedge clk_in) begin
i_in_meta <= i_in;
i_in_sync1 <= i_in_meta;
i_in_sync2 <= i_in_sync1;
i_in_sync3 <= i_in_sync2;
i_in_out <= i_in_sync3;
end
assign o_out = i_in_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[] = {0, 1, 2, 9, 64, 625, 7776, 117649, 2097152}; const long long M = 1000000007ll; int main(void) { std::ios::sync_with_stdio(false); long long k, n, m, t; while (cin >> n >> m) { n -= m; t = 1; k = n; while (k) { if (k & 1) t = t * n % M; n = n * n % M; k >>= 1; } cout << a[m] * t % M << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O2BB2A_PP_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O21BA_PP_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); int q; cin >> q; while (q--) { int a, b, n, S; cin >> a >> b >> n >> S; int x = min(a, S / n); cout << (S - x * n <= b ? YES : NO ) << n ; } return 0; }
|
// This is the Avalon slave for the motor controller
// Registers 0-5 store the direction and on/off switch for each motor
// Registers 8-13 store the respective duty cycle
// The output should be fed to GPIO pins in the SOPC configuration
`include "defines.v"
module slave_controller(input clk, input chipselect, input write, input [3:0]addr, input [31:0] writedata, output [23:0] GPIO_out);
reg [11:0] in = 12'd0;
reg [6*`PERIOD_LENGTH-1:0] duty_cycle = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (chipselect & write)
casex (addr)
4'b0000:
in[1:0] <= writedata[1:0];
4'b0001:
in[3:2] <= writedata[1:0];
4'b0010:
in[5:4] <= writedata[1:0];
4'b0011:
in[7:6] <= writedata[1:0];
4'b0100:
in[9:8] <= writedata[1:0];
4'b0101:
in[11:10] <= writedata[1:0];
4'b1000:
duty_cycle[`PERIOD_LENGTH-1:0] <= writedata[`PERIOD_LENGTH-1:0];
4'b1001:
duty_cycle[2*`PERIOD_LENGTH-1:`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1010:
duty_cycle[3*`PERIOD_LENGTH-1:2*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1011:
duty_cycle[4*`PERIOD_LENGTH-1:3*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH-1:0];
4'b1100:
duty_cycle[5*`PERIOD_LENGTH-1:4*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1101:
duty_cycle[6*`PERIOD_LENGTH-1:5*`PERIOD_LENGTH] <= writedata[`PERIOD_LENGTH:0];
4'b1110:
period <= writedata[15:0];
default:
; // do nothing
endcase
generate
genvar i;
for (i=0; i<6; i=i+1)
begin : motor_control_loop
motor_controller mc(clk, in[i*2 + 1], in[i*2], period, duty_cycle[(i+1)*`PERIOD_LENGTH-1:i*`PERIOD_LENGTH], GPIO_out[i*4+3:i*4]);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> V, L, Q; vector<string> P; map<int, int> M; set<char> S; set<char>::iterator it; long long n, m, a, b, c, d, e, f, cnt, x, y, z, t; string s, p, ans, temp; long long arr[1001]; bool xy = 0; char bd; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; cin >> s; for (int i = 0; i < n; i++) if (s[i] == G or s[i] == T ) { for (int j = i + m; j < n; j += m) { if (s[j] == # ) { cout << NO ; return 0; ; } if (s[j] == G or s[j] == T ) { cout << YES ; return 0; ; } } } cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3000 + 10; int sum, d[maxn], dp[maxn][2]; vector<pair<int, int> > edge[maxn]; int min(int a, int b) { return a < b ? a : b; } void dfs(int u, int f, int w) { if (f == -1) { sum = 0; d[u] = 0; dp[u][0] = dp[u][1] = 0; } else { dp[u][1] = dp[f][1] + w; dp[u][0] = min(dp[f][0], dp[f][1]) + !w; d[u] = d[f] + w; } for (vector<pair<int, int> >::iterator it = edge[u].begin(); it != edge[u].end(); it++) { int to = it->first; int wt = it->second; if (to == f) continue; sum += wt; dfs(to, u, wt); } } int main() { int n, u, v, ret = maxn; cin >> n; for (int i = 0; i < n - 1; i++) { cin >> u >> v; edge[u].push_back(make_pair(v, 0)); edge[v].push_back(make_pair(u, 1)); } for (int i = 1; i <= n; i++) { dfs(i, -1, 0); for (int j = 1; j <= n; j++) { ret = min(ret, sum + min(dp[j][0], dp[j][1]) - d[j]); } } cout << ret << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; struct ad { int l, r, i; bool operator<(const ad a) const { if (l != a.l) return l < a.l; return r > a.r; } }; const int INF = 1000000000; const int MAXN = 200005; const int SZ = 1 << 18; int N, M, A, B; long long res, resi, resj, C; pair<int, int> arr[2 * SZ]; ad S[MAXN]; vector<ad> T; set<pair<int, int> > Q, R; void build() { for (int i = SZ - 1; i > 0; i--) { arr[i] = max(arr[2 * i], arr[2 * i + 1]); } } inline pair<int, int> rmq(int l, int r) { l += SZ, r += SZ + 1; pair<int, int> res(0, 0); for (; l < r; l /= 2, r /= 2) { if (l & 1) res = max(res, arr[l++]); if (r & 1) res = max(res, arr[--r]); } return res; } inline long long calc(ad &a, int A, int B) { if (a.l > B || a.r < A) return 0; return min(a.r, B) - max(a.l, A); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> N >> M; for (int i = 0; i < N; i++) { cin >> S[i].l >> S[i].r; S[i].i = i; } sort(S, S + N); for (int i = 0; i < N; i++) { if (i > 0 && T.back().r >= S[i].r) continue; else T.push_back(S[i]); } for (int i = 0; i < T.size(); i++) { arr[SZ + i] = pair<int, int>(T[i].r - T[i].l, i); Q.insert(pair<int, int>(T[i].l, i)); R.insert(pair<int, int>(T[i].r, i)); } build(); for (int i = 0; i < M; i++) { cin >> A >> B >> C; set<pair<int, int> >::iterator it, jt; it = Q.upper_bound(pair<int, int>(A, INF)); jt = R.lower_bound(pair<int, int>(B, -INF)); if (it != Q.begin()) { it--; long long k = calc(T[it->second], A, B) * C; if (k > res) { res = k; resi = T[it->second].i + 1; resj = i + 1; } } if (jt != R.end()) { long long k = calc(T[jt->second], A, B) * C; if (k > res) { res = k; resi = T[jt->second].i + 1; resj = i + 1; } } it = Q.lower_bound(pair<int, int>(A, -INF)); jt = R.upper_bound(pair<int, int>(B, INF)); if (it != Q.end() && jt != R.begin()) { jt--; if (it->second <= jt->second) { pair<int, int> p = rmq(it->second, jt->second); if (p.first * C > res) { res = p.first * C; resi = T[p.second].i + 1; resj = i + 1; } } } } cout << res << n ; if (res > 0) { cout << resi << << resj << n ; } }
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#include <bits/stdc++.h> using namespace std; const long long int inf = (long long int)1e18 + 19; const long long int mod = (long long int)1e9 + 7; void cazz() { long long int t = 1, i; long double j, n; cin >> t; while (t--) { cin >> n; i = 3, j = -1; while (j < n) { j = (((long double)180 * (i - 2)) / i); i++; } if (j == n) { cout << YES n ; continue; } cout << NO n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cazz(); return 0; }
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