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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_2_V
`define SKY130_FD_SC_HD__DFSTP_2_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_2 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_2 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_2_V
|
#include <bits/stdc++.h> using namespace std; template <class T> T Max(const T &a, const T &b) { return a > b ? a : b; } const int SN = 100000 + 10; long long w[SN], f[SN][2], down[SN], g[SN], h[SN], head[SN]; long long u, v, n, num; bool vis[SN]; struct Edge { int from, to, next; } E[SN << 2]; void Read(long long &x) { long long in = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch = - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { in = in * 10 + ch - 0 ; ch = getchar(); } x = in * f; } void Add(int u, int v) { E[++num].from = u; E[num].to = v; E[num].next = head[u]; head[u] = num; } void dfs(int u) { vis[u] = 1; g[u] = f[u][0] = f[u][1] = down[u] = w[u]; for (int i = head[u]; i; i = E[i].next) { int to = E[i].to; if (vis[to]) continue; dfs(to); f[u][0] = Max(f[u][0], f[to][0]); f[u][0] = Max(f[u][0], f[u][1] + f[to][1]); f[u][0] = Max(f[u][0], g[to] + down[u]); f[u][0] = Max(f[u][0], down[to] + g[u]); f[u][1] = Max(f[u][1], f[to][1]); f[u][1] = Max(f[u][1], down[u] + down[to]); g[u] = Max(g[u], g[to] + w[u]); g[u] = Max(g[u], down[u] + f[to][1]); g[u] = Max(g[u], down[to] + w[u] + h[u]); h[u] = Max(h[u], f[to][1]); down[u] = Max(down[u], down[to] + w[u]); } } int main() { Read(n); for (int i = 1; i <= n; i++) Read(w[i]); for (int i = 1; i < n; i++) { Read(u), Read(v); Add(u, v), Add(v, u); } dfs(1); printf( %lld n , f[1][0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int i; int main() { cin >> s; i = s.find( 0 ); if (i > -1) s.erase(i, 1); else s.erase(0, 1); cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int h, cen; long long n, num; while (scanf( %d%I64d , &h, &n) != EOF) { num = (long long)pow(2.0, h) - 1 + n; int flag; long long ans = 0; if (num % 2 == 0) flag = 0; else flag = 1; cen = h - 1; while (1) { ans++; num /= (long long)2; if (num % 2 == 0) { if (flag == 0) ans += (long long)pow(2.0, h - cen) - (long long)1.0; flag = 0; } else { if (flag == 1) ans += (long long)pow(2.0, h - cen) - (long long)1.0; flag = 1; } if (num == 1) break; cen--; } printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long int> v; vector<long long int> v1; vector<long long int> v2; const long long int inf = 100000000000005; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; for (int i = 1; i < n; i++) cout << i + 1 << ; cout << 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int const maxn = 1e5 + 5; int n, m, k, p[105], second[105], mx[105]; int ans; int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; ++i) scanf( %d , &p[i]); for (int i = 1; i <= n; ++i) { scanf( %d , &second[i]); if (mx[second[i]] < p[i]) mx[second[i]] = p[i]; } for (int i = 1; i <= k; ++i) { int v; scanf( %d , &v); if (mx[second[v]] > p[v]) ans++; } printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O41A_FUNCTIONAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_FUNCTIONAL_V
|
module RotaryLed(clock0,clock180,reset,rotary,leds,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock0;
input wire clock180;
input wire reset;
input wire [1:0] rotary;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [7:0] alu_result;
wire mrotary_rotary_left_status;
wire mrotary_rotary_right_status;
wire [7:0] ledbank_leds;
assign leds = ledbank_leds;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0,mrotary_rotary_left_status}),
.ireg_2({7'h0,mrotary_rotary_right_status}),
.ireg_3({8'h00}),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
RotaryLedRom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
RotaryLedRomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
Alu
alu (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result));
Rotary
mrotary (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.rotary(rotary),
.rotary_left_status(mrotary_rotary_left_status),
.rotary_right_status(mrotary_rotary_right_status));
LedBank
ledbank (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.leds(ledbank_leds));
VGA1
vga (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[3]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // RotaryLed
|
#include <bits/stdc++.h> using namespace std; const int inf = 2e9; const long double eps = 0.000001; const long long mod = 1e9 + 7; const long double PI = 3.14159265359; template <class T> struct MyVector : vector<T> { MyVector() : vector<T>() {} MyVector(int n) : vector<T>(n) {} T &operator[](size_t i) { return vector<T>::at(i); } }; string t; string p; vector<int> a; bool check(int m) { vector<int> u((int)t.size(), false); for (int i = 0; i < m; i++) { u[a[i]] = true; } string ns; for (int i = 0; i < (int)t.size(); i++) { if (u[i]) continue; ns.push_back(t[i]); } int idx = 0; for (int i = 0; i < (int)p.size(); i++) { bool fl = false; for (; idx < (int)ns.size(); idx++) { if (ns[idx] == p[i]) { idx++; fl = true; break; } } if (!fl) return false; } return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> t >> p; a.resize((int)t.size()); for (int i = 0; i < (int)t.size(); i++) { cin >> a[i]; a[i]--; } int l = -1, r = (int)t.size() + 1; while (r - l > 1) { int m = (l + r) / 2; if (check(m)) l = m; else r = m; } cout << l; return 0; }
|
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: JTAG_Probe.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module JTAG_Probe (
probe,
source);
input [15:0] probe;
output source;
wire sub_wire0;
wire source = sub_wire0;
altsource_probe altsource_probe_component (
.probe (probe),
.source (sub_wire0)
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "NO",
altsource_probe_component.instance_id = "NONE",
altsource_probe_component.probe_width = 16,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "NONE"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "0"
// Retrieval info: USED_PORT: probe 0 0 16 0 INPUT NODEFVAL "probe[15..0]"
// Retrieval info: USED_PORT: source 0 0 0 0 OUTPUT NODEFVAL "source"
// Retrieval info: CONNECT: @probe 0 0 16 0 probe 0 0 16 0
// Retrieval info: CONNECT: source 0 0 0 0 @source 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:57:44 07/13/2015
// Design Name:
// Module Name: SPI
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI
( input Clk,
// SPI Host interface
output reg MOSI,
input MISO,
output reg SCLK,
output reg SCE,
// Controller interface
input Enable,
input Speed, // 0:LowSpeed 1:HighSpeed
input [7:0] SendData,
input SendReq,
output reg SendAck,
output reg [7:0] RecvData,
output reg RecvAdv,
input RecvAck
);
// ClkPeriod = Clk period in ns, default 20ns = 50MHz
parameter real ClkPeriod = 20.0;
// Low Speed = 400KHz
`define LO_SPEED_TICKS_UP $rtoi(((1.00 / 400000.00) / (ClkPeriod * 1.0E-9)) / 2.00)
`define LO_SPEED_TICKS_DW ($rtoi((1.00 / 400000.00) / (ClkPeriod * 1.0E-9)) - `LO_SPEED_TICKS_UP)
// High Speed = 5MHz
`define HI_SPEED_TICKS_UP $rtoi(((1.00 / .00) / (ClkPeriod * 1.0E-9)) / 2.00)
`define HI_SPEED_TICKS_DW ($rtoi((1.00 / .00) / (ClkPeriod * 1.0E-9)) - `HI_SPEED_TICKS_UP)
integer ClkCounter;
integer ClkStatus;
integer Counter;
reg [7:0] ShiftReg;
initial
begin
ClkCounter = 0;
ClkStatus = 0;
MOSI = 1;
SCLK = 0;
SCE = 1;
SendAck = 0;
ShiftReg = 8'hFF;
end
always @(posedge Clk)
begin
if (SendReq == 1) SendAck = 1; else begin end
if (RecvAck == 1) RecvAdv = 0; else begin end
if (Enable == 0) SCE = 1; else begin end
case(ClkStatus)
0: begin
ClkCounter = 0;
SCLK = 0;
ClkStatus = 2;
end
1: begin
if (ClkCounter > 1) ClkCounter = ClkCounter - 1;
else begin
ClkCounter = (Speed == 0) ? `LO_SPEED_TICKS_DW : `HI_SPEED_TICKS_DW;
SCLK = 0;
ClkStatus = 2;
// SCLK negedge -- SPI Shift
if (Enable == 1)
begin
if (SCE == 1)
begin
SCE = 0;
if (SendAck == 1)
begin
ShiftReg = {SendData[6:0],1'b0};
MOSI = SendData[7];
SendAck = 0;
end
else
begin
ShiftReg = 8'b11111111;
MOSI = 1;
end
Counter = 7;
end
else
begin
if (Counter > 0)
begin
Counter = Counter - 1;
MOSI = ShiftReg[7];
ShiftReg = {ShiftReg[6:0],1'b0};
end
else
begin
if (SendAck == 1)
begin
ShiftReg = {SendData[6:0],1'b0};
MOSI = SendData[7];
SendAck = 0;
end
else
begin
ShiftReg = 8'b11111111;
MOSI = 1;
end
Counter = 7;
end
end
end
else MOSI = 1;
end
end
2: begin
if (ClkCounter > 1) ClkCounter = ClkCounter - 1;
else begin
ClkCounter = (Speed == 0) ? `LO_SPEED_TICKS_UP : `HI_SPEED_TICKS_UP;
SCLK = 1;
ClkStatus = 1;
// SCLK posedge -- SPI Latch
if (SCE == 0)
begin
ShiftReg[0] = MISO;
if (Counter == 0)
begin
RecvData = ShiftReg;
RecvAdv = 1;
end
else begin
end
end
else begin
end
end
end
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 1100000; const int M = 21; vector<int> adj[N]; int par[N][M]; int vis[N]; void dfs(int u, int p) { par[u][0] = p; for (int v : adj[u]) { if (v == p) continue; dfs(v, u); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(n, 0); for (int i = 1; i < M; i++) for (int j = 1; j <= n; j++) par[j][i] = par[par[j][i - 1]][i - 1]; vis[n] = 1; int rest = n - k - 1; for (int i = n - 1; i >= 0; i--) { if (vis[i]) continue; int now = i; int cnt = 0; for (int j = M - 1; j >= 0; j--) { int cur = par[now][j]; if (cur == 0 || vis[cur]) continue; cnt += 1 << j; now = cur; } if (cnt + 1 > rest) continue; rest -= cnt + 1; vis[i] = 1; now = i; for (int times = 0; times < cnt; times++) { now = par[now][0]; vis[now] = 1; } } for (int i = 1; i <= n; i++) if (!vis[i]) cout << i << ; return 0; }
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#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return (b == 0 ? a : gcd(b, a % b)); } struct key { string name; int t, p, g; }; int main() { int n, s, mt = 0, mg = 0, mp = 0; string x; cin >> n; vector<key> vec(n); for (int i = 0; i < n; i++) { cin >> s >> vec[i].name; vec[i].t = vec[i].p = vec[i].g = 0; for (int j = 0; j < s; j++) { cin >> x; if (x[0] == x[1] && x[1] == x[3] && x[3] == x[4] && x[4] == x[6] && x[6] == x[7]) vec[i].t++; else if (x[1] < x[0] && x[3] < x[1] && x[4] < x[3] && x[6] < x[4] && x[7] < x[6]) vec[i].p++; else vec[i].g++; } mt = max(mt, vec[i].t); mg = max(mg, vec[i].g); mp = max(mp, vec[i].p); } int f = 0; cout << If you want to call a taxi, you should call: ; for (int i = 0; i < n; i++) if (vec[i].t == mt) { if (f) cout << , ; cout << << vec[i].name; f = 1; } f = 0; cout << . << endl << If you want to order a pizza, you should call: ; for (int i = 0; i < n; i++) if (vec[i].p == mp) { if (f) cout << , ; cout << << vec[i].name; f = 1; } f = 0; cout << . << endl << If you want to go to a cafe with a wonderful girl, you should call: ; for (int i = 0; i < n; i++) if (vec[i].g == mg) { if (f) cout << , ; cout << << vec[i].name; f = 1; } cout << . ; }
|
`timescale 1 ns / 1 ps
module axis_variable #
(
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg;
reg int_tvalid_reg, int_tvalid_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_reg <= 1'b0;
end
else
begin
int_tdata_reg <= cfg_data;
int_tvalid_reg <= int_tvalid_next;
end
end
always @*
begin
int_tvalid_next = int_tvalid_reg;
if(int_tdata_reg != cfg_data)
begin
int_tvalid_next = 1'b1;
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tvalid_next = 1'b0;
end
end
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long Fib[100]; long long Path[100]; pair<long long, long long> get(long long N, long long X, bool f) { assert(Fib[N] >= X); if (N <= 0) { return {0, 0}; } if (N == 1) { if (X == 1) { return {0, 1}; } else { return {1, 0}; } } pair<long long, long long> res = {}; if (X <= Fib[N - 1]) { res = get(N - 1, X, true); res.second = min(res.first, res.second) + 1ll + Path[N - 2]; if (f) { res.second = min(res.second, res.first + 2ll); res.first = min(res.first, res.second + 2ll); } } else { res = get(N - 2, X - Fib[N - 1], false); res.first++; if (f) { res.second = min(res.second, res.first + 2ll); res.first = min(res.first, res.second + 2ll); } } return res; } long long solve(long long N, long long X, long long Y) { int f = 0; if (N > 90) { N = 90; f = 1; } assert(Fib[N] >= X && Fib[N] >= Y); if (X > Y) swap(X, Y); while (true) { if (Y <= Fib[N - 1]) { f = 1; N--; } else if (X > Fib[N - 1]) { if (f) { f++; } X -= Fib[N - 1]; Y -= Fib[N - 1]; N -= 2; } else { break; } } if (N == 1) { return 1; } auto res1 = get(N - 1, X, true); auto res2 = get(N - 2, Y - Fib[N - 1], false); long long res = res2.first + 1ll + min(res1.first, res1.second); if (f) { res = min(res, res2.second + 2ll + res1.first + f - 1ll); } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); Fib[0] = 1; Path[0] = 0; Fib[1] = 2; Path[1] = 1; for (int i = 2; i < 100; i++) { Fib[i] = Fib[i - 1] + Fib[i - 2]; Path[i] = Path[i - 2] + 1; } long long T, N, X, Y; cin >> T >> N; while (T--) { cin >> X >> Y; cout << solve(N, X, Y) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace std; long long a[200005]; struct poi { long long val; int pos; } tp; bool operator<(const poi &a, const poi &b) { return (a.val > b.val) || (a.val == b.val and a.pos > b.pos); } priority_queue<poi> q; int main() { int n; int cnt = 0; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); tp.val = a[i]; tp.pos = i; q.push(tp); } while (!q.empty()) { poi a1 = q.top(); q.pop(); poi b1 = q.top(); q.pop(); while (!q.empty() && a1.val != b1.val) { a1 = b1; b1 = q.top(); q.pop(); } if (a1.val == b1.val and a1.pos != b1.pos) { a[b1.pos] = b1.val * 2; b1.val = b1.val * 2; a[a1.pos] = -1; cnt++; if (q.empty()) break; q.push(b1); } } printf( %d n , n - cnt); for (int i = 0; i < n; i++) { if (a[i] != -1) printf( %lld , a[i]); } printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {-1, 1, 0, 0}; int dy[] = {0, 0, -1, 1}; long long int sizes[100001]; long long int arr[100001]; bool ok = true; long long int A[100001]; pair<long long int, long long int> B[100001]; long long int root(long long int i) { while (i != arr[i]) i = arr[i]; return (i); } void Union(long long int i, long long int j) { long long int root_i = root(i), root_j = root(j); if (root_i == root_j) return; if (sizes[root_i] > sizes[root_j]) swap(root_i, root_j); sizes[root_j] += sizes[root_i]; arr[root_i] = arr[root_j]; return; } long long int Arr[100001]; bool solve(long long int n) { if (n == 1) return (true); set<long long int> st; for (long long int i = 0; i < n; i++) { long long int m = (Arr[i] + i) % n; if (m < 0) m += n; if (st.count(m)) return (false); st.insert(m); } return (true); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { string s; cin >> s; set<pair<pair<long long int, long long int>, pair<long long int, long long int> > > st; long long int ans = 0, x = 0, y = 0; for (long long int i = 0; i < s.size(); i++) { long long int a, b, c, d; if (s[i] == N ) { a = x; b = y + 1; c = 0; d = 1; } else if (s[i] == S ) { a = x; b = y - 1; c = 0; d = -1; } else if (s[i] == W ) { a = x + 1; b = y; c = 1; d = 0; } else if (s[i] == E ) { a = x - 1; b = y; c = -1; d = 0; } if (st.count(pair<pair<long long int, long long int>, pair<long long int, long long int> >( pair<long long int, long long int>(x, y), pair<long long int, long long int>(a, b)))) ans++; else if (st.count(pair<pair<long long int, long long int>, pair<long long int, long long int> >( pair<long long int, long long int>(a, b), pair<long long int, long long int>(x, y)))) ans++; else ans += 5; st.insert(pair<pair<long long int, long long int>, pair<long long int, long long int> >( pair<long long int, long long int>(x, y), pair<long long int, long long int>(a, b))); x += c; y += d; } cout << ans << n ; } return (0); }
|
/* Top level that just instantiates a UART in loopback mode in an icestick.
* Assumtions: 12M clock. 115200 bps. 8N1 format.
* Note: Needs retesting on hardware after code reorganization.
*/
/*
MIT License
Copyright (c) 2016 Baard Nossum
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* LogicCells:
* 38 for uart proper
* 1 for metastability removal rxpin
* 1 for generation of constant 1'b1.
* -------
* 40 logicCells in total
*
*/
/*
PIO3_08 _ _ _
[x] ----| |- rxpinmeta1 -| |--| |-- rxpin -> UART
>_| |_| >_|
_
UART -- txpin ->| |--|>o--[x] PIO03_07
>_|
*/
module top
// ( inout PIO3_08,PIO3_07,PIO1_14,PIO1_02,GBIN6
// );
( input PIO3_08, GBIN6,
output PIO3_07, PIO1_14, PIO1_02
);
wire [7:0] d;
wire clk,cte1,rxpinmeta1,c_rxpinmeta1,rxpin;
reg [4:0] bitxcecnt;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bytercvd; // From uart of uartICE40.v
wire [7:0] q; // From uart of uartICE40.v
wire [1:0] rxst; // From uart of uartICE40.v
wire txbusy; // From uart of uartICE40.v
wire txpin; // From uart of uartICE40.v
// End of automatics
assign cte1 = 1'b1;
// Clock pin
SB_GB_IO clockpin
( .PACKAGE_PIN(GBIN6), .GLOBAL_BUFFER_OUTPUT(clk));
// Transmit pin
SB_IO #( .PIN_TYPE(6'b011111)) // OUTPUT_REGISTERED_INVERTED/INPUT_LATCH
IO_tx ( .PACKAGE_PIN(PIO3_07), .OUTPUT_CLK(clk), .D_OUT_0(txpin) );
// txbusy to LED0
SB_IO #( .PIN_TYPE(6'b010111)) // OUTPUT_REGISTERED/INPUT_LATCH
IO_txbusy ( .PACKAGE_PIN(PIO1_14), .OUTPUT_CLK(clk), .D_OUT_0(txbusy) );
// bitxce to J2 pin 1 for debugging
SB_IO #( .PIN_TYPE(6'b010111)) // OUTPUT_REGISTERED/INPUT_LATCH
IO_bitxce ( .PACKAGE_PIN(PIO1_02), .OUTPUT_CLK(clk), .D_OUT_0(bitxce) );
// Receive pin
SB_IO #( .PIN_TYPE(6'b000000)) // NO_OUTPUT/INPUT_REGISTERED
IO_rx ( .PACKAGE_PIN(PIO3_08), .INPUT_CLK(clk), .D_IN_0(rxpinmeta1) );
SB_LUT4 #( .LUT_INIT(16'haaaa))
cmb( .O(c_rxpinmeta1), .I3(1'b0), .I2(1'b0), .I1(1'b0), .I0(rxpinmeta1));
SB_DFF metareg( .Q(rxpin), .C(clk), .D(c_rxpinmeta1));
always @(posedge clk)
bitxcecnt <= bitxcecnt[4] ? 5'h4 : bitxcecnt+5'h1;
assign bitxce = bitxcecnt[4];
// The module proper
uartICE40 uart
(/*AUTOINST*/
// Outputs
.txpin (txpin),
.txbusy (txbusy),
.bytercvd (bytercvd),
.rxst (rxst[1:0]),
.q (q[7:0]),
// Inputs
.clk (clk),
.bitxce (bitxce),
.load (load),
.d (d[7:0]),
.rxpin (rxpin));
// Connect the uart in loopback:
assign load = bytercvd;
assign d = q;
endmodule
// Local Variables:
// verilog-library-directories:("." "./fromrefdesign/" )
// verilog-library-files:("../../../PROJ/iCE_simlib/iCE_simlib.v" "uart.v" )
// verilog-library-extensions:(".v" )
// End:
|
module VGAController(
input iClk,
input inRst,
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
output [7:0] oR,
output [7:0] oG,
output [7:0] oB,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid
);
/*****************************************************************
* H timings
****************************************************************/
parameter H_SYNC_PULSE = 96;
parameter H_SYNC_BACK = 48;
parameter H_SYNC_DATA = 640;
parameter H_SYNC_FRONT = 16;
parameter H_SYNC_TOTAL = H_SYNC_FRONT + H_SYNC_PULSE + H_SYNC_BACK + H_SYNC_DATA;
/*****************************************************************
* V timings
****************************************************************/
parameter V_SYNC_PULSE = 2;
parameter V_SYNC_BACK = 36;
parameter V_SYNC_DATA = 480;
parameter V_SYNC_FRONT = 7;
parameter V_SYNC_TOTAL = V_SYNC_FRONT + V_SYNC_PULSE + V_SYNC_BACK + V_SYNC_DATA;
/*****************************************************************
* Data offsets
****************************************************************/
parameter H_START_DATA = H_SYNC_BACK + H_SYNC_PULSE + H_SYNC_FRONT;
parameter V_START_DATA = V_SYNC_BACK + V_SYNC_PULSE + V_SYNC_FRONT;
parameter H_STOP_DATA = H_START_DATA + H_SYNC_DATA;
parameter V_STOP_DATA = V_START_DATA + V_SYNC_DATA;
/*****************************************************************
* Sync pulses offsets
****************************************************************/
parameter H_START_PULSE = H_SYNC_FRONT;
parameter V_START_PULSE = V_SYNC_FRONT;
parameter H_STOP_PULSE = H_SYNC_FRONT + H_SYNC_PULSE;
parameter V_STOP_PULSE = V_SYNC_FRONT + V_SYNC_PULSE;
/*****************************************************************
* Internal schedule counters
****************************************************************/
reg [12:0] mHCounter = 0;
reg [12:0] mVCounter = 0;
/*****************************************************************
* Async assignments
****************************************************************/
assign oVSync = (mVCounter >= V_START_PULSE && mVCounter < V_STOP_PULSE && inRst ) ? 0 : 1;
assign oHSync = (mHCounter >= H_START_PULSE && mHCounter < H_STOP_PULSE && inRst ) ? 0 : 1;
assign oFrameValid = (mVCounter >= V_START_DATA && mVCounter < V_STOP_DATA && inRst ) ? 1 : 0;
assign oLineValid = (mHCounter >= H_START_DATA && mHCounter < H_STOP_DATA && oFrameValid) ? 1 : 0;
assign oR = (oLineValid && oFrameValid && inRst) ? iR : 0;
assign oG = (oLineValid && oFrameValid && inRst) ? iG : 0;
assign oB = (oLineValid && oFrameValid && inRst) ? iB : 0;
/*****************************************************************
* Pixel counter generator
****************************************************************/
always@(posedge iClk or negedge inRst)
begin
if(~inRst) mHCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1)) mHCounter <= 0;
else mHCounter <= mHCounter + 1;
end
end
/*****************************************************************
* Line counter generator
****************************************************************/
always@(posedge iClk or negedge inRst)
begin
if(~inRst) mVCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1))
begin
if(mVCounter == (V_SYNC_TOTAL - 1)) mVCounter <= 0;
else mVCounter <= mVCounter + 1;
end
else mVCounter <= mVCounter;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[100005], s[100005]; int main() { int n, k, inp; scanf( %d %d , &n, &k); for (int i = 1; i < k + 1; i++) { scanf( %d , &inp); s[inp] = i; if (!f[inp]) f[inp] = i; } int ans = 0; for (int i = 1; i < n + 1; i++) { if (!f[i]) { ans += 3; if (i == 1 || i == n) ans--; continue; } int b = i - 1; if (b >= 1 && s[b] < f[i]) ans++; b = i + 1; if (b <= n && s[b] < f[i]) ans++; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int r1, c1, r2, c2; cin >> r1 >> c1 >> r2 >> c2; if (r1 == r2 || c1 == c2) cout << 1; else cout << 2; cout << ; if ((r1 + c1) % 2 != (r2 + c2) % 2) cout << 0; else { if (r1 + c1 == r2 + c2 || r1 - c1 == r2 - c2) cout << 1; else { cout << 2; } } cout << ; cout << max(abs(r1 - r2), abs(c1 - c2)) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; while (cin >> t) { string a; cin >> a; int s = 0; for (int i = 0; i < t - 1;) { if (a.at(i) == a.at(i + 1)) { if (a.at(i) == a ) a.at(i) = b ; else a.at(i) = a ; s++; } i += 2; if (i >= a.size()) break; } cout << s << endl << a << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Inf = (int)1e9 + 7; const long long LongInf = (long long)1e18 + 7; namespace { const int N = 1007; const int MOD = (int)1e9 + 7; int k, pa, pb; long long dp[N][N]; long long pw(long long x, int m) { if (m == 0) return 1; long long y = pw(x, m / 2); y = (y * y) % MOD; if (m % 2) y = (y * x) % MOD; return y; } long long inv(int x) { return pw(x, MOD - 2); } void solve() { cin >> k >> pa >> pb; long long s = inv(pa + pb); pa = (pa * s) % MOD; pb = (pb * s) % MOD; long long res = 0; dp[1][0] = 1; long long rem = (pa * inv(pb)) % MOD; for (int i = 1; i <= k; i++) { for (int j = 0; j <= k; j++) { if (i + j >= k) { res += (dp[i][j] * (i + j + rem)) % MOD; res %= MOD; } else { (dp[i + 1][j] += (dp[i][j] * pa) % MOD) %= MOD; (dp[i][i + j] += (dp[i][j] * pb) % MOD) %= MOD; } } } cout << res << n ; } } // namespace int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(9); cout << fixed; solve(); return 0; }
|
#include <bits/stdc++.h> char s[200010]; int tree[26][200010 << 2]; bool vis[200010]; inline void PushUp(int t, int rt) { tree[t][rt] = tree[t][rt << 1] + tree[t][rt << 1 | 1]; } void Update(int t, int x, int L, int R, int rt) { if (L == R) tree[t][rt] = 1; else { int mid = (L + R) >> 1; if (mid >= x) Update(t, x, L, mid, rt << 1); else Update(t, x, mid + 1, R, rt << 1 | 1); PushUp(t, rt); } } int Find(int t, int x, int L, int R, int rt) { if (L == R) { tree[t][rt] = 0; return L; } int ans, mid = (L + R) >> 1; if (tree[t][rt << 1] >= x) ans = Find(t, x, L, mid, rt << 1); else { x -= tree[t][rt << 1]; ans = Find(t, x, mid + 1, R, rt << 1 | 1); } PushUp(t, rt); return ans; } int main() { char ch; int k, i, j, q, len, n; while (~scanf( %d %s%d , &k, s + 1, &q)) { memset(vis, false, sizeof(vis)); memset(tree, 0, sizeof(tree)); len = strlen(s + 1); n = len * k; for (j = len + 1; --k;) { for (i = 1; i <= len; i++) s[j++] = s[i]; } s[j] = 0; for (i = 1; s[i]; i++) Update(s[i] - a , i, 1, n, 1); while (q--) { scanf( %d %c , &i, &ch); k = Find(ch - a , i, 1, n, 1); vis[k] = true; } for (i = 1; s[i]; i++) { if (!vis[i]) putchar(s[i]); } putchar( n ); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/17/2017 08:53:01 PM
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb();
reg CLOCK_50;
reg rst;
wire vsync;
wire[11:0] color_out;
wire[7:0] seg_out;
wire[3:0] sel;
wire hsync;
//integer file_output;
initial begin
//file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = 1'b1;
#195 rst= 1'b0;
# $stop;
end
top_greedy_snake top_greedy_snake1(
.clk(CLOCK_50),
.rst(rst),
.left(0),
.right(0),
.up(0),
.down(0),
.hsync(hsync),
.vsync(vsync),
.color_out(color_out),
.seg_out(seg_out),
.sel(sel)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[222222], b[222222], c[222222], d[222222]; set<long long> st; set<long long>::iterator it; map<long long, long long> sp2; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m, k, x, s, i; cin >> n >> m >> k; cin >> x >> s; for (i = 1; i <= m; i++) { cin >> a[i]; } for (i = 1; i <= m; i++) { cin >> b[i]; } for (i = 1; i <= k; i++) { cin >> c[i]; } for (i = 1; i <= k; i++) { cin >> d[i]; st.insert(d[i]); sp2[d[i]] = c[i]; } long long ans = n * x; long long rem; long long temp; for (i = 1; i <= m; i++) { if (b[i] <= s) { temp = 0; rem = s - b[i]; it = st.upper_bound(rem); if (it != st.begin()) { it--; temp += sp2[*it]; } if (temp >= n) ans = 0; else ans = min(ans, (n - temp) * a[i]); } } temp = 0; it = st.upper_bound(s); if (it != st.begin()) { it--; temp += sp2[*it]; } if (temp >= n) ans = 0; else ans = min(ans, (n - temp) * x); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } int main() { int n, m; cin >> n >> m; int a0, b0, x; for (int i = 0; i < n + 1; i++) { cin >> x; if (!i) a0 = x; } for (int i = 0; i < m + 1; i++) { cin >> x; if (!i) b0 = x; } if (n > m) { int sign; if (a0 < 0 && b0 > 0 || a0 > 0 && b0 < 0) cout << - ; cout << Infinity n ; } else if (n < m) { cout << 0/1 n ; } else { int sign; if (a0 < 0 && b0 < 0 || a0 > 0 && b0 > 0) sign = 1; else sign = -1; a0 = abs(a0); b0 = abs(b0); int g = gcd(a0, b0); a0 /= g; b0 /= g; a0 *= sign; cout << a0 << / << b0 << n ; } }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'push' primitive
//
// Upstream are signals that go to the feedback (snk node is a acl_pop),
// downstream are signals that continue into our "normal" pipeline.
//
// dir indicates if you want to push it to the feedback
// 1 - push to feedback
// 0 - bypass, just push out to downstream
//===----------------------------------------------------------------------===//
// altera message_off 10036
module acl_push (
clock,
resetn,
// interface from kernel pipeline, input stream
dir,
data_in,
valid_in,
stall_out,
predicate,
// interface to kernel pipeline, downstream
valid_out,
stall_in,
data_out,
// interface to pipeline feedback, upstream
feedback_out,
feedback_valid_out,
feedback_stall_in
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 1;
parameter MIN_FIFO_LATENCY = 0;
// style can be "REGULAR", for a regular push
// or "TOKEN" for a special fifo that hands out tokens
parameter string STYLE = "REGULAR"; // "REGULAR"/"TOKEN"
parameter STALLFREE = 0;
parameter ENABLED = 0;
input clock, resetn, stall_in, valid_in, feedback_stall_in;
output stall_out, valid_out, feedback_valid_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out, feedback_out;
wire [DATA_WIDTH-1:0] feedback;
wire data_downstream, data_upstream;
wire push_upstream;
assign push_upstream = dir & ~predicate;
assign data_upstream = valid_in & push_upstream;
assign data_downstream = valid_in;
wire feedback_stall, feedback_valid;
reg consumed_downstream, consumed_upstream;
assign valid_out = data_downstream & !consumed_downstream;
assign feedback_valid = data_upstream & !consumed_upstream & (ENABLED ? ~stall_in : 1'b1);
assign data_out = data_in;
assign feedback = data_in;
//assign stall_out = valid_in & ( ~(data_downstream & ~stall_in) & ~(data_upstream & ~feedback_stall));
// assign stall_out = valid_in & ( ~(data_downstream & ~stall_in) | ~(data_upstream & ~feedback_stall));
assign stall_out = stall_in | (feedback_stall & push_upstream );
generate
if (ENABLED) begin
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
consumed_downstream <= 1'b0;
consumed_upstream <= 1'b0;
end else begin
if (~stall_in) begin
if (consumed_downstream)
consumed_downstream <= stall_out;
else
consumed_downstream <= stall_out & data_downstream;
consumed_upstream <= 1'b0;
end
end
end
end else begin
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
consumed_downstream <= 1'b0;
consumed_upstream <= 1'b0;
end else begin
if (consumed_downstream)
consumed_downstream <= stall_out;
else
consumed_downstream <= stall_out & (data_downstream & ~stall_in);
if (consumed_upstream)
consumed_upstream <= stall_out;
else
consumed_upstream <= stall_out & (data_upstream & ~feedback_stall);
end
end
end
endgenerate
localparam TYPE = MIN_FIFO_LATENCY < 1 ? (FIFO_DEPTH < 8 ? "zl_reg" : "zl_ram") : (MIN_FIFO_LATENCY < 3 ? (FIFO_DEPTH < 8 ? "ll_reg" : "ll_ram") : (FIFO_DEPTH < 8 ? "ll_reg" : "ram"));
generate
if ( STYLE == "TOKEN" )
begin
acl_token_fifo_counter
#(
.DEPTH(FIFO_DEPTH)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_out(feedback_out),
.valid_in(feedback_valid),
.valid_out(feedback_valid_out),
.stall_in(feedback_stall_in),
.stall_out(feedback_stall)
);
end
else if (FIFO_DEPTH == 0) begin
// if no FIFO depth is requested, just connect
// feedback directly to output
assign feedback_out = feedback;
assign feedback_valid_out = feedback_valid;
assign feedback_stall = feedback_stall_in;
end
else if (FIFO_DEPTH == 1 && MIN_FIFO_LATENCY == 0) begin
// simply add a staging register if the requested depth is 1
// and the latency must be 0
acl_staging_reg #(
.WIDTH(DATA_WIDTH)
) staging_reg (
.clk(clock),
.reset(~resetn),
.i_data(feedback),
.i_valid(feedback_valid),
.o_stall(feedback_stall),
.o_data(feedback_out),
.o_valid(feedback_valid_out),
.i_stall(feedback_stall_in)
);
end
else
begin
// only allow full write in stall free clusters if you're an ll_reg
// otherwise, comb cycles can form, since stall_out depends on
// stall_in the acl_data_fifo. To make up for the last space, we
// add a capacity of 1 to the FIFO
localparam OFFSET = ( (TYPE == "ll_reg") && !STALLFREE ) ? 1 : 0;
localparam ALLOW_FULL_WRITE = ( (TYPE == "ll_reg") && !STALLFREE ) ? 0 : 1;
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(((TYPE == "ram") || (TYPE == "ll_ram") || (TYPE == "zl_ram")) ? FIFO_DEPTH + 1 : FIFO_DEPTH + OFFSET),
.IMPL(TYPE),
.ALLOW_FULL_WRITE(ALLOW_FULL_WRITE)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_in(feedback),
.data_out(feedback_out),
.valid_in(feedback_valid),
.valid_out(feedback_valid_out),
.stall_in(feedback_stall_in),
.stall_out(feedback_stall)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105][105][105]; int ans[105][105]; int main() { int n, m, h, x; cin >> n >> m >> h; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) for (int k = 1; k <= h; k++) a[i][j][k] = 1; for (int i = 1; i <= m; i++) { cin >> x; for (int j = x + 1; j <= h; j++) for (int k = 1; k <= n; k++) a[k][i][j] = 0; } for (int i = 1; i <= n; i++) { cin >> x; for (int j = x + 1; j <= h; j++) for (int k = 1; k <= m; k++) a[i][k][j] = 0; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> x; if (x == 0) for (int k = 1; k <= h; k++) a[i][j][k] = 0; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { ans[i][j] = 0; for (int k = 1; k <= h; k++) if (a[i][j][k]) ans[i][j]++; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cout << ans[i][j]; if (j == m) cout << endl; else cout << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_1_V
`define SKY130_FD_SC_HD__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_1_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<double, double> > vec; double x[10], y[10]; int cross(pair<double, double> a, pair<double, double> b, pair<double, double> c) { double re = (a.first - c.first) * (b.second - c.second); re -= (a.second - c.second) * (b.first - c.first); if (fabs(re) < 1e-8) return 0; return re > 0 ? 1 : -1; } bool work() { double x0, y0, d, xb, yb, xc, yc, xa, ya, xd, yd; int i; x0 = x[1] * 2 - x[2]; y0 = y[1] * 2 - y[2]; d = x0 * (y[1] - y[3]) + x[1] * (y[3] - y0) + x[3] * (y0 - y[1]); d *= 2; xb = (x0 * x0 + y0 * y0) * (y[1] - y[3]); xb += (x[1] * x[1] + y[1] * y[1]) * (y[3] - y0); xb += (x[3] * x[3] + y[3] * y[3]) * (y0 - y[1]); xb /= d; yb = (x0 * x0 + y0 * y0) * (x[3] - x[1]); yb += (x[1] * x[1] + y[1] * y[1]) * (x0 - x[3]); yb += (x[3] * x[3] + y[3] * y[3]) * (x[1] - x0); yb /= d; xc = 2 * x[1] - xb; yc = 2 * y[1] - yb; xa = 2 * x[3] - xb; ya = 2 * y[3] - yb; xd = 2 * x[2] - xc; yd = 2 * y[2] - yc; vec.clear(); vec.push_back(make_pair(xa, ya)); vec.push_back(make_pair(xd, yd)); vec.push_back(make_pair(xc, yc)); vec.push_back(make_pair(xb, yb)); for (i = 0; i < 4; i++) if (cross(vec[i], vec[(i + 1) % 4], vec[(i + 2) % 4]) * cross(vec[i], vec[(i + 1) % 4], vec[(i + 3) % 4]) <= 0) return false; printf( YES n ); for (i = 0; i < 4; i++) printf( %.10f %.10f , vec[i].first, vec[i].second); printf( n ); return true; } int main() { int T, i; scanf( %d , &T); while (T--) { for (i = 1; i <= 3; i++) scanf( %lf%lf , &x[i], &y[i]); if ((x[1] - x[3]) * (y[2] - y[3]) == (y[1] - y[3]) * (x[2] - x[3])) { printf( NO n n ); continue; } if (work()) continue; swap(x[1], x[2]); swap(y[1], y[2]); if (work()) continue; swap(x[1], x[3]); swap(y[1], y[3]); if (work()) continue; printf( NO n n ); } }
|
module tb_fpga();
parameter wire_width = 7;
parameter lb_cfg_size = 18;
parameter fpga_width = 5;
parameter fpga_height = 5;
// Test ports
reg A, B;
reg carryin;
wire out;
wire carryout;
// Configuration ports
reg [fpga_height*fpga_width*wire_width*12-1:0] brbselect;
reg [(fpga_height-1)*(fpga_width-1)*(wire_width*wire_width*12)-1:0] bsbselect;
reg [fpga_width*fpga_height*lb_cfg_size-1:0] lbselect;
reg [2*wire_width*fpga_height-1:0] leftioselect;
reg [2*wire_width*fpga_height-1:0] rightioselect;
reg [2*wire_width*fpga_height-1:0] topioselect;
reg [2*wire_width*fpga_height-1:0] bottomioselect;
wire [4:0] left, right, top, bottom;
assign bottom[0] = A;
// assign bottom[2] = B;
// assign bottom[4] = carryin;
// // assign out = top[0];
assign out = left[0];
// assign carryout = top[4];
fpga_top #(
.wire_width(wire_width),
.lb_cfg_size(lb_cfg_size),
.fpga_width(fpga_width),
.fpga_height(fpga_width)
) f1(
clk,
brbselect, bsbselect, lbselect,
leftioselect, rightioselect, topioselect, bottomioselect,
left, right, top, bottom
);
reg k;
initial begin
brbselect = 900'b0;
bsbselect = 1728'b0;
lbselect = 80'b0;
leftioselect = 30'b0;
rightioselect = 30'b0;
topioselect = 30'b0;
bottomioselect = 30'b0;
$display("initialized memory");
set_bottom_io_cfg(0, 0, 1); // Bottom left in
// // bottomioselect[1] = 1'b1;
// set_top_io_cfg(0, 0, 1); // Top left out
set_left_io_cfg(0, 0, 2);
// // leftioselect[0] = 1'b1;
set_brb_cfg(0, 0, 0, 2, 1);
// brbselect[4] = 1'b0;
// brbselect[5] = 1'b1;
// // set_brb_cfg(0, 0, 0, 3, 1);
// set_brb_cfg(1, 0, 0, 3, 1);
// set_brb_cfg(2, 0, 0, 3, 1);
// set_brb_cfg(3, 0, 0, 3, 1);
// set_brb_cfg(4, 0, 0, 3, 1);
$display("finished setting bits.");
A = 1'b0; B = 1'b0; carryin = 1'b0;
$monitor("A = %b, B = %b, carryin = %b, out = %b, carryout = %b",
A, B, carryin, out, carryout);
#10 A = 1'b0; B = 1'b0; carryin = 1'b0;
#10 A = 1'b1; B = 1'b0; carryin = 1'b0;
#10 A = 1'b0; B = 1'b1; carryin = 1'b0;
#10 A = 1'b1; B = 1'b1; carryin = 1'b0;
#10 A = 1'b0; B = 1'b0; carryin = 1'b1;
#10 A = 1'b1; B = 1'b0; carryin = 1'b1;
#10 A = 1'b0; B = 1'b1; carryin = 1'b1;
#10 A = 1'b1; B = 1'b1; carryin = 1'b1;
end
task set_top_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
topioselect[io_index*6+io_line*2+0] = 1'b0;
topioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in top", io_index*6+io_line*2+1);
topioselect[io_index*6+io_line*2+0] = 1'b0;
topioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in top", io_index*6+io_line*2+0);
topioselect[io_index*6+io_line*2+0] = 1'b1;
topioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_bottom_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
bottomioselect[io_index*6+io_line*2+0] = 1'b0;
bottomioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in bottom", io_index*6+io_line*2+1);
bottomioselect[io_index*6+io_line*2+0] = 1'b0;
bottomioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in bottom", io_index*6+io_line*2+0);
bottomioselect[io_index*6+io_line*2+0] = 1'b1;
bottomioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_left_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
leftioselect[io_index*6+io_line*2+0] = 1'b0;
leftioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in left", io_index*6+io_line*2+1);
leftioselect[io_index*6+io_line*2+0] = 1'b0;
leftioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in left", io_index*6+io_line*2+0);
leftioselect[io_index*6+io_line*2+0] = 1'b1;
leftioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_right_io_cfg;
input integer io_index, io_line, io_dir;
begin
if (io_dir == 0) begin // Off
rightioselect[io_index*6+io_line*2+0] = 1'b0;
rightioselect[io_index*6+io_line*2+1] = 1'b0;
end else if (io_dir == 1) begin // Out
$display("set bit %d in right", io_index*6+io_line*2+1);
rightioselect[io_index*6+io_line*2+0] = 1'b0;
rightioselect[io_index*6+io_line*2+1] = 1'b1;
end else if (io_dir == 2) begin // In
$display("set bit %d in right", io_index*6+io_line*2+0);
rightioselect[io_index*6+io_line*2+0] = 1'b1;
rightioselect[io_index*6+io_line*2+1] = 1'b0;
end
end
endtask
task set_brb_cfg;
input integer row, col;
// which switch element, which internal switch
input integer s_index, s_sel;
input integer dir;
begin
if (dir == 0) begin // Off
brbselect[col*36 + row*180 + s_index*12 + s_sel*2] = 1'b0;
brbselect[col*36 + row*180 + s_index*12 + s_sel*2 + 1] = 1'b0;
end else if (dir == 1) begin // In
brbselect[col*36 + row*180 + s_index*12 + s_sel*2] = 1'b0;
brbselect[col*36 + row*180 + s_index*12 + s_sel*2 + 1] = 1'b1;
end else if (dir == 2) begin // Out
brbselect[col*36 + row*180 + s_index*12 + s_sel*2] = 1'b1;
brbselect[col*36 + row*180 + s_index*12 + s_sel*2 + 1] = 1'b0;
end
end
endtask
task set_bsb_cfg;
input integer row, col;
// which switch element, which internal switch
input integer s_row, s_col, s_sel;
input integer dir;
begin
if (dir == 0) begin // Off
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2] = 1'b0;
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2 + 1] = 1'b0;
end else if (dir == 1) begin // In
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2] = 1'b0;
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2 + 1] = 1'b1;
end else if (dir == 2) begin // Out
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2] = 1'b1;
bsbselect[col*108 + row*432 + s_col*12 + s_row*36 + s_sel*2 + 1] = 1'b0;
end
end
endtask
task set_lb_cfg;
input integer row, col;
input [3:0] truth_tbl;
input sync;
begin
lbselect[col*5 + row * 20] = truth_tbl[0];
lbselect[col*5 + row * 20 + 1] = truth_tbl[1];
lbselect[col*5 + row * 20 + 2] = truth_tbl[2];
lbselect[col*5 + row * 20 + 3] = truth_tbl[3];
lbselect[col*5 + row * 20 + 4] = sync;
end
endtask
endmodule
|
#include <bits/stdc++.h> int main() { long a, b, c; scanf( %ld%ld%ld , &a, &b, &c); if (b == a) { printf( YES n ); } else if (c > 0) { if (b < a) { printf( NO n ); } else if (((b - a) % c) == 0) { printf( YES n ); } else { printf( NO n ); } } else if (c < 0) { if (b > a) { printf( NO n ); } else if (((a - b) % c) == 0) { printf( YES n ); } else { printf( NO n ); } } else { printf( NO n ); } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// dma interface
dac_div_clk,
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [ 13:0] dac_data_out_a_p;
output [ 13:0] dac_data_out_a_n;
output [ 13:0] dac_data_out_b_p;
output [ 13:0] dac_data_out_b_n;
// dma interface
output dac_div_clk;
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [ 15:0] dac_data_00_s;
wire [ 15:0] dac_data_01_s;
wire [ 15:0] dac_data_02_s;
wire [ 15:0] dac_data_03_s;
wire [ 15:0] dac_data_04_s;
wire [ 15:0] dac_data_05_s;
wire [ 15:0] dac_data_06_s;
wire [ 15:0] dac_data_07_s;
wire [ 15:0] dac_data_08_s;
wire [ 15:0] dac_data_09_s;
wire [ 15:0] dac_data_10_s;
wire [ 15:0] dac_data_11_s;
wire [ 15:0] dac_data_12_s;
wire [ 15:0] dac_data_13_s;
wire [ 15:0] dac_data_14_s;
wire [ 15:0] dac_data_15_s;
wire dac_status_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9739a_if #(.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE)) i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_rst (dac_rst),
.dac_clk (),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_data_00 (dac_data_00_s),
.dac_data_01 (dac_data_01_s),
.dac_data_02 (dac_data_02_s),
.dac_data_03 (dac_data_03_s),
.dac_data_04 (dac_data_04_s),
.dac_data_05 (dac_data_05_s),
.dac_data_06 (dac_data_06_s),
.dac_data_07 (dac_data_07_s),
.dac_data_08 (dac_data_08_s),
.dac_data_09 (dac_data_09_s),
.dac_data_10 (dac_data_10_s),
.dac_data_11 (dac_data_11_s),
.dac_data_12 (dac_data_12_s),
.dac_data_13 (dac_data_13_s),
.dac_data_14 (dac_data_14_s),
.dac_data_15 (dac_data_15_s));
// core
axi_ad9739a_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_data_00 (dac_data_00_s),
.dac_data_01 (dac_data_01_s),
.dac_data_02 (dac_data_02_s),
.dac_data_03 (dac_data_03_s),
.dac_data_04 (dac_data_04_s),
.dac_data_05 (dac_data_05_s),
.dac_data_06 (dac_data_06_s),
.dac_data_07 (dac_data_07_s),
.dac_data_08 (dac_data_08_s),
.dac_data_09 (dac_data_09_s),
.dac_data_10 (dac_data_10_s),
.dac_data_11 (dac_data_11_s),
.dac_data_12 (dac_data_12_s),
.dac_data_13 (dac_data_13_s),
.dac_data_14 (dac_data_14_s),
.dac_data_15 (dac_data_15_s),
.dac_status (dac_status_s),
.dac_valid (dac_valid),
.dac_enable (dac_enable),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name: red_pitaya_iq_fgen_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_lpf_block #(
parameter ALPHABITS = 25,
parameter HIGHESTALPHABIT = 18,
parameter LPFBITS = 18 //,
// parameter HIGHPASS = 0
)
(
input clk_i,
input reset_i ,
input signed [HIGHESTALPHABIT-1:0] alpha_i,
input signed [LPFBITS-1:0] signal_i,
output signed [LPFBITS-1:0] signal_o
);
//reg signed [ALPHABITS-1:0] alpha;
reg signed [LPFBITS+ALPHABITS-1:0] y;
reg signed [LPFBITS+ALPHABITS-1:0] delta; //we need this cumbersome imperfect implementation with a delta buffer to introduce some delay so the code works at 125 MHZ
//reg signed [LPFBITS+1-1:0] delta_out;
wire signed [LPFBITS-1:0] y_out;
assign y_out = y[ALPHABITS+LPFBITS-1:ALPHABITS];
always @(posedge clk_i) begin
// alpha <= $signed(alpha_i);
if (reset_i == 1'b1) begin
y <= {ALPHABITS+LPFBITS{1'b0}};
delta <= {ALPHABITS+LPFBITS{1'b0}};
//delta_out <= {LPFBITS{1'b0}};
end
else begin
//delta <= ($signed(signal_i)-$signed(y_out))*$signed(alpha);
//y <= $signed(y) + $signed(delta);
delta <= (signal_i-y_out)*alpha_i;
//delta_out <= signal_i - y_out;
y <= y + delta;
end
end
assign signal_o = y_out;
//generate
//if (HIGHPASS == 0)
// assign signal_o = y_out;
//else
// if (delta_out[LPFBITS:LPFBITS-1] == 2'b01)
// assign signal_o = {1'b0,{LPFBITS-1{1'b1}}};
// else if (delta_out[LPFBITS:LPFBITS-1] == 2'b10)
// assign signal_o = {1'b1,{LPFBITS-1{1'b0}}};
// else
// assign signal_o = delta_out[LPFBITS-1:0];
//endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; inline const int read() { int r = 0, k = 1; char c = getchar(); for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) k = -1; for (; c >= 0 && c <= 9 ; c = getchar()) r = r * 10 + c - 0 ; return k * r; } long long n; int k, a[110]; bool vis[1000010]; long long dp[110][100000]; long long dfs(int pos, long long n) { if (pos == k + 1) return n; if (n <= 0) return 0; if (n < 100000 && dp[pos][n] != -1) return dp[pos][n]; long long ans = dfs(pos + 1, n) - dfs(pos + 1, n / a[pos]); if (n < 100000) dp[pos][n] = ans; return ans; } void input() { memset(dp, -1, sizeof(dp)); cin >> n >> k; for (int i = (1), _ = (k); i <= _; i++) a[i] = read(); sort(a + 1, a + k + 1, greater<int>()); } void solve() { cout << dfs(1, n) << endl; } int main() { input(), solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXM = 101000; pair<int, int> a[MAXM]; vector<pair<int, int> > b[MAXM << 1]; vector<int> c[MAXM << 1], d[MAXM << 1]; int main() { int n, m, i, j, k, x, y; int f, l, r, top; while (scanf( %d%d , &n, &m) != EOF) { for (i = 0; i < m; i++) { scanf( %d%d , &x, &y); a[i] = make_pair(x, y); } sort(a, a + m); for (i = 0; i + n - 1 < m; i++) if (a[i].first == a[i + n - 1].first) break; if (i + n - 1 < m && a[i].first == a[i + n - 1].first) { puts( -1 ); continue; } if (a[0].first == 1) { b[0].push_back(make_pair(1, a[0].second - 1)); f = 1; top = 0; } else { b[0].push_back(make_pair(1, n)); b[1].push_back(make_pair(1, a[0].second - 1)); f = a[0].first; top = 1; } for (i = 1; i < m; i++) { if (a[i].first > f) { if (a[i - 1].second != n) b[top].push_back(make_pair(a[i - 1].second + 1, n)); top++; if (a[i].first - f > 1) b[top++].push_back(make_pair(1, n)); if (a[i].second > 1) b[top].push_back(make_pair(1, a[i].second - 1)); f = a[i].first; } else { if (a[i].second - a[i - 1].second > 1) b[top].push_back(make_pair(a[i - 1].second + 1, a[i].second - 1)); } } if (a[m - 1].second != n) b[top].push_back(make_pair(a[m - 1].second + 1, n)); top++; if (a[m - 1].first != n) b[top++].push_back(make_pair(1, n)); c[0].push_back(b[0][0].first); d[0].push_back(b[0][0].second); for (i = 1; i < top; i++) { f = b[i].size(); for (j = 0; j < f; j++) { k = lower_bound(d[i - 1].begin(), d[i - 1].end(), b[i][j].first) - d[i - 1].begin(); if (k >= 0 && k < d[i - 1].size() && d[i - 1][k] >= b[i][j].first && c[i - 1][k] <= b[i][j].second) { c[i].push_back(max(b[i][j].first, c[i - 1][k])); d[i].push_back(b[i][j].second); } } if (c[i].size() == 0) break; } if (d[top - 1].size() != 0 && d[top - 1][d[top - 1].size() - 1] == n) printf( %d n , 2 * n - 2); else puts( -1 ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(); void YN(bool b) { if (b) { cout << YES << n ; ; } else { cout << NO << n ; ; } }; void yn(bool b) { if (b) { cout << Yes << n ; ; } else { cout << No << n ; ; } }; void queries() { int n; cin >> n; while (n--) solve(); } const int maxn = 200200; void solve() { int n; cin >> n; vector<int> a(n); vector<int> b; map<int, int> m; for (int i = 0; i < n; i++) { cin >> a[i]; m[a[i]]++; } for (auto i : m) { b.push_back(i.second); } map<int, bool> taken; long long sum = 0; sort(b.begin(), b.end()); for (int i = b.size() - 1; i >= 0; i--) { if (!taken[b[i]]) { sum += b[i]; taken[b[i]] = 1; } else { for (int j = b[i]; j > 0; j--) { if (!taken[j]) { sum += j; taken[j] = 1; break; } } } } cout << sum << n ; ; return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); queries(); ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long inf = 4e18, mod = 1e9 + 7; vector<pair<pair<long long, long long>, pair<long long, long long>>> v; int segt[4 * 6000000 + 5], lazy[4 * 6000000 + 5]; void push(int v, int l, int r) { segt[v] += lazy[v]; if (l != r) { lazy[2 * v] += lazy[v]; lazy[2 * v + 1] += lazy[v]; } lazy[v] = 0; } void update_range(int v, int l, int r, int qs, int qe, int x) { push(v, l, r); if (l > qe || r < qs) return; if (qs <= l && r <= qe) { lazy[v] += x; push(v, l, r); return; } int m = (l + r) / 2; update_range(2 * v, l, m, qs, qe, x); update_range(2 * v + 1, m + 1, r, qs, qe, x); segt[v] = max(segt[2 * v], segt[2 * v + 1]); } int query(int v, int l, int r, int qs, int qe) { push(v, l, r); if (l > qe || r < qs) return 0; if (qs <= l && r <= qe) return segt[v]; int m = (l + r) / 2; int val1 = query(2 * v, l, m, qs, qe); int val2 = query(2 * v + 1, m + 1, r, qs, qe); return max(val1, val2); } void solve() { int n, r; cin >> n >> r; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; int X = x + y, Y = y - x; int lx, ly, ux, uy; lx = X - r, ux = X + r, ly = Y - r, uy = Y + r; lx += 3000000; ux += 3000000; ly += 3000000; uy += 3000000; v.push_back({{ly, 0}, {lx, ux}}); v.push_back({{uy, 1}, {lx, ux}}); } sort(v.begin(), v.end()); int res = 0; for (auto it : v) { if (it.first.second == 0) update_range(1, 0, 6000000, it.second.first, it.second.second, 1); else update_range(1, 0, 6000000, it.second.first, it.second.second, -1); int val = query(1, 0, 6000000, 0, 6000000); res = max(res, val); } cout << res << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q ;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 300010; int n; int maxx; int node[2 * MAX][30]; int cau[MAX]; int site; int other; void in() { scanf( %d , &n); int a, b; char c; for (int i = 1; i < n; i++) { scanf( %d %d %c , &a, &b, &c), node[a][c - a ] = b; } } int w = 1; int mix(int x, int y) { if (x == 0 || y == 0) return x + y; int now = ++other; site++; for (int i = 0; i < 26; i++) node[now][i] = mix(node[x][i], node[y][i]); return now; } void dfs(int x, int deep) { other = n + 1; int now = other; site = 0; for (int i = 0; i < 26; i++) now = mix(now, node[x][i]); cau[deep] += site; for (int i = 0; i < 26; i++) if (node[x][i] > 0) dfs(node[x][i], deep + 1); } void work() { dfs(1, 1); maxx = 1; for (int i = 1; i <= n; i++) if (n - cau[maxx] > n - cau[i]) maxx = i; } void out() { printf( %d n , n - cau[maxx]); printf( %d n , maxx); } int main() { in(); work(); out(); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } string S, P; int dp[2001][2002], dp1[2001][2011], len[2001]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long a, b, c, d = 0, e, f = 0, g, h = 0, x, y, z = 0; cin >> S >> P; a = S.size(), b = P.size(); for (int i = (0); i < (b); ++i) dp1[a][i] = 1000000; for (int i = a - 1; i >= 0; i--) { for (int j = 0; j < b; j++) { if (S[i] == P[j]) { dp1[i][j] = dp1[i + 1][j + 1]; } else dp1[i][j] = 1 + dp1[i + 1][j]; } len[i] = dp1[i][0]; } for (int i = 1; i <= a; i++) dp[a][i] = -100000; for (int i = a - 1; i >= 0; i--) { for (int j = 0; j <= a; j++) { dp[i][j] = -100000; if (j > (a - i)) { continue; } dp[i][j] = max(dp[i][j], dp[i + 1][j]); if (j > 0) dp[i][j] = max(dp[i][j], dp[i + 1][j - 1]); if (len[i] <= j && (i + len[i] + b) <= a) dp[i][j] = max(dp[i][j], 1 + dp[i + len[i] + b][j - len[i]]); } } for (int i = 0; i <= a; i++) cout << dp[0][i] << ; cout << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:34 05/31/2016
// Design Name:
// Module Name: Contador_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_ID(
input rst,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 2;
parameter X = 2;
always @(posedge clk)
if (rst)
Cuenta <= 0;
else if (Cambio == 8'h7A && got_data)
begin
if (Cuenta == X)
Cuenta <= 0;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h69 && got_data)
begin
if (Cuenta == 0)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
endmodule
|
//THINK ALOUD !! #include <bits/stdc++.h> #define debug(x) cout << -> [ << #x << = << x << ] n #define debug2(x, y) cout << -> [ << #x << = << x << , << #y << = << y << ] n #define debug3(x, y, z) cout << -> [ << #x << = << x << , << #y << = << y << , << #z << = << z << ] n ; #define debug4(x, y, z, xx) cout << -> [ << #x << = << x << , << #y << = << y << , << #z << = << z << , << #xx << = << xx << ] n ; using namespace std; using ll=long long int; using lld=long double; #define mp make_pair #define pb push_back #define accu accumulate #define pll pair<ll, ll> #define pii pair<int, int> #define pci pair<char, int> #define pic pair<int, char> #define pls pair<ll, string> #define psl pair<string, ll> #define pis pair<int, string> #define psi paid<string, int> // #define x first // #define y second #define fast ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); #define rep(i, a, n) for (ll i = a; i < n; i++) #define per(i, a, n) for (ll i = n-1; i >= a; i--) #define repp(i, a, n, p) for (ll i = a; i < n; i += p) #define all(c) (c).begin(), (c).end() #define lla(c) (c).rbegin(), (c).rend() #define print_arr(arr, n) for (int i = 0; i < n; i++) std::cout << arr[i] << ; std::cout << n ; #define mod 1000000007 #define primeSize 2000000 #define Size 1e6 template <typename t> inline void print(const t & v) { for (const auto& i : v) { std::cout << i << ; } std::cout << n ; } template <typename t> inline void printt(const t & v) { for (const auto& i : v) { std::cout << i.first << << i.second << n ; } std::cout << n ; } template <typename INT> INT GCD(INT a, INT b) { // if (b == 0) return a; // return gcd(b, a%b); return b ? gcd(b, a%b) : a; } template <typename INT> INT LCM(INT a, INT b) { return a / gcd(a, b) * b; } template <typename INT> std::map<INT, int> factorize(INT n) { map<INT, int> mp; for (INT i = 2; i * i <= n; i++) { while (n % i == 0) { n /= i; mp[i] ++; } } if (n > 1) mp[n] += 1; return mp; } ll bin_pow(ll a, ll b) { if (b == 0) return 1; long long res = bin_pow(a, b / 2); if (b % 2) return res * res * a; else return res * res; } int totalDigits(ll i) { return i > 0 ? (int) log10 ((double) i) + 1 : 1; } vector<bool> isPrime(primeSize, true); vector<int> arePrimes; void make_seive() { isPrime[0] = false; isPrime[1] = false; for (int i = 2; i <= sqrt(primeSize); i++) { if (isPrime[i]) { for (int j = i * 2; j <= primeSize; j += i) { isPrime[j] = false; } } } for (int i = 2; i < primeSize; i++) { if (isPrime[i]) { arePrimes.push_back(i); } } } void solve() { int n; cin >> n; vector<ll> X; vector<ll> Y; for (int i = 0; i < 2 * n; i++) { int a, b; cin >> a >> b; a = abs(a); b = abs(b); if (a == 0) X.push_back(b); else Y.push_back(a); } sort(all(X)); sort(lla(Y)); lld ans = 0; lld ans2 = 0; for (int i = 0; i < n; i++) ans += sqrt(X[i]*X[i] + Y[i]*Y[i]); sort(all(Y)); for (int i = 0; i < n; i++) ans2 += sqrt(X[i]*X[i] + Y[i]*Y[i]); lld final_ans = 0; final_ans = min(ans, ans2); cout << setprecision(20) << final_ans << n ; } int main() { fast; int t = 1; //make_seive(); cin >> t; while (t--) solve(); } /* Tips: -- for queries involving sum using queue or minimum sum of size k, do also consider prefix sum. */ /* Build and running g++ --std=c++17 -Wall -Wextra -Wshadow -fsanitize=undefined -fsanitize=address FILE.cpp && ./a.out < in Naming -for types (class/struct name) UpperCamelCase: Point, Info, SegTree -functions and variable lowerCamelCase: someMethod, someVariable -MACROS and constants all capital letters separated by _ : SOME_MACRO, MAX_N, MOD */
|
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : -x; } int n; int m; int l[100], v[100][100], t[100][100], q[200]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &l[i]); for (int j = 0; j < l[i]; j++) { scanf( %d%d , &v[i][j], &t[i][j]); if (j > 0) t[i][j] += t[i][j - 1]; } } int ans = 0; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) { int k = 0; q[k++] = 0; for (int p = 0; p < l[i]; p++) q[k++] = t[i][p]; for (int p = 0; p < l[j]; p++) q[k++] = t[j][p]; sort(q, q + k); int a = 0, b = 0, ls = 0, x = 0, y = 0; for (int p = 1; p < k; p++) { int d = q[p] - q[p - 1]; while (a + 1 < l[i] && t[i][a] < q[p]) a++; while (b + 1 < l[j] && t[j][b] < q[p]) b++; x += v[i][a] * d; y += v[j][b] * d; int cs = int(x > y) - int(x < y); if (ls == 0) ls = cs; else if (cs != 0 && ls != cs) { ls = cs; ans++; } if (x == m || y == m) break; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const long long inf = 9e18; struct NODE { long long v, id; bool operator<(const NODE& other) const { return v > other.v || (v == other.v && id > other.id); } } node[N]; long long a[N], b[N]; long long n; long long f(long long x, long long y) { return x - 3LL * y * y + 3LL * y - 1; } long long find(long long v, long long x) { long long l, r, mid; l = 0; r = x + 1; while (r - l > 1) { mid = (l + r) >> 1; if (f(x, mid) >= v) l = mid; else r = mid; } return l; } long long solve(long long x) { long long tot = 0, i; for (i = 1; i <= n; i++) { tot += (b[i] = find(x, a[i])); } return tot; } int main() { long long k, i, cnt = 0; long long l = inf, r = -inf, mid, tot; cin >> n >> k; for (i = 1; i <= n; i++) { cin >> a[i]; l = min(l, f(a[i], a[i])); r = max(r, f(a[i], 1)); } while (r - l > 1) { mid = (l + r) >> 1; if (solve(mid) <= k) r = mid; else l = mid; } tot = solve(r); for (i = 1; i <= n; i++) if (b[i] < a[i]) node[++cnt].v = f(a[i], b[i] + 1), node[cnt].id = i; sort(node + 1, node + cnt + 1); for (i = 1; i <= cnt; i++) { if (tot == k) break; b[node[i].id]++; tot++; } for (i = 1; i <= n; i++) cout << b[i] << ; return 0; }
|
// a simple font_module
// a simple font_module
// text is generated from position (translated to ANSI)
// IMPORTANT
// this code can be a little confusing
// since test_on is generated but not outputted
// this is because that the top module of this module do not need to distinguish between different screens
module font_gen
(
input wire clk,
input wire video_on,
input wire [9:0] pixel_x, pixel_y,
output reg [2:0] rgb_text
);
// signal declaration
wire [10:0] rom_addr;
wire [6:0] char_addr;
wire [3:0] row_addr;
wire [2:0] bit_addr;
wire [7:0] font_word;
wire font_bit, text_bit_on;
// body
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// font ROM interface
// character is selected purely by position
assign char_addr = {pixel_y[5:4], pixel_x[7:3]};
assign row_addr = pixel_y[3:0];
assign rom_addr = {char_addr, row_addr};
assign bit_addr = pixel_x[2:0];
// remember, x is increasing from left to right
// but in the rom, x is decreasing from left to right
// so bit_addr must be inverted to get the correct character
assign font_bit = font_word[~bit_addr];
// "on" region limited to top-left corner
assign text_bit_on = (pixel_x[9:8]==0 && pixel_y[9:6]==0) ?
font_bit : 1'b0;
// rgb multiplexing circuit
always @*
if (~video_on)
rgb_text = 3'b001; // blue
// well (this is only about eliminating error)
// can you understand it?
else
if (text_bit_on)
rgb_text = 3'b110; // yellow
else
rgb_text = 3'b000; // black
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_2_V
`define SKY130_FD_SC_HS__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int arr[100]; for (int counter = 0; counter < n; counter++) { cin >> arr[counter]; } sort(arr, arr + n); int sum = 0; for (int counter = n - 1; counter >= 0; counter--) { sum += arr[counter]; if (sum >= m) { cout << n - counter; break; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int s = 0; for (int i = 0; i < 5; i++) { int x; cin >> x; s += x; } if (s % 5 || !s) cout << -1 ; else cout << s / 5; }
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T x) { return x * x; } template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } template <class T> inline T bigmod(T p, T e, T M) { if (e == 0) return 1; if (e % 2 == 0) { long long int t = bigmod(p, e / 2, M); return (T)((t * t) % M); } return (T)((long long int)bigmod(p, e - 1, M) * (long long int)p) % M; } template <class T> inline T bigexp(T p, T e) { if (e == 0) return 1; if (e % 2 == 0) { long long int t = bigexp(p, e / 2); return (T)((t * t)); } return (T)((long long int)bigexp(p, e - 1) * (long long int)p); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } int dx4[] = {1, 0, -1, 0}; int dy4[] = {0, 1, 0, -1}; int dx8[] = {1, 1, 0, -1, -1, -1, 0, 1}; int dy8[] = {0, 1, 1, 1, 0, -1, -1, -1}; int nx8[] = {1, 1, -1, -1, 2, 2, -2, -2}; int ny8[] = {2, -2, 2, -2, 1, -1, 1, -1}; int month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int n, a[100005], b[100005], c, com; vector<int> v[100005]; map<int, int> m; bool bl[100005]; void dfs(int p) { if (bl[p]) return; bl[p] = true; v[com].push_back(p); dfs(b[p]); } int main() { scanf( %d , &n); for (__typeof(n) i = (1); i <= (n); i++) scanf( %d , &a[i]); for (__typeof(n) i = (1); i <= (n); i++) b[i] = a[i]; sort(b + 1, b + n + 1); for (__typeof(n) i = (1); i <= (n); i++) m[b[i]] = ++c; for (__typeof(n) i = (1); i <= (n); i++) b[i] = m[a[i]]; for (int i = 1; i <= n; i++) { if (bl[i] == false) { ++com; dfs(i); } } cout << com, printf( n ); for (__typeof(com) i = (1); i <= (com); i++) { printf( %d , (int)v[i].size()); for (int j = 0; j < (int)v[i].size(); j++) printf( %d , v[i][j]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const double eps = 1e-6; const int mod = 1000000007; inline string getstr(string &s, int l, int r) { string ret = ; for (int i = l; i <= r; i++) ret.push_back(s[i]); return ret; } int modpow(int x, int y, int md = mod) { if (y == 0) return 1; int ret = modpow(x, y >> 1, md); ret = (long long)ret * ret % md; if (y & 1) ret = (long long)ret * x % md; return ret; } string s, t; int n; int main() { cin >> n >> s >> t; int l, r; for (l = 0;; l++) { if (s[l] != t[l]) { break; } } for (r = n - 1;; r--) { if (s[r] != t[r]) { break; } } int lft = 1, rgt = 1; for (int i = l; i < r; i++) { if (s[i] != t[i + 1]) lft = 0; if (s[i + 1] != t[i]) rgt = 0; } cout << lft + rgt << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_PP_SYMBOL_V
/**
* sleep_pargate_plv: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_pargate_plv (
//# {{power|Power}}
input SLEEP ,
output VIRTPWR,
input VPB ,
input VPWR ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int tim; int t[maxn]; int sum[maxn], sum2[maxn]; int in[maxn], ou[maxn], dfn[maxn]; vector<int> G[maxn]; void dfs(int rt, int fa) { in[rt] = ++tim; dfn[tim] = rt; for (int i = 0; i < G[rt].size(); i++) { int to = G[rt][i]; if (to == fa) continue; dfs(to, rt); } ou[rt] = tim; } struct T { int l, r, mid; int add, sum; } tree[maxn << 2]; void push_up(int rt) { tree[rt].sum = tree[rt << 1].sum + tree[rt << 1 | 1].sum; } void push_down(int rt) { if (tree[rt].add) { tree[rt << 1].add ^= 1; tree[rt << 1].sum = (tree[rt << 1].r - tree[rt << 1].l + 1) - tree[rt << 1].sum; tree[rt << 1 | 1].add ^= 1; tree[rt << 1 | 1].sum = (tree[rt << 1 | 1].r - tree[rt << 1 | 1].l + 1) - tree[rt << 1 | 1].sum; tree[rt].add = 0; } } void build(int rt, int l, int r) { tree[rt].add = 0; tree[rt].l = l; tree[rt].r = r; if (l == r) { tree[rt].sum = t[dfn[l]]; return; } int mid = tree[rt].mid = l + r >> 1; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); push_up(rt); } void update(int rt, int l, int r) { if (tree[rt].r < l || tree[rt].l > r) return; if (tree[rt].l >= l && tree[rt].r <= r) { tree[rt].sum = (tree[rt].r - tree[rt].l + 1) - tree[rt].sum; tree[rt].add ^= 1; return; } push_down(rt); if (tree[rt].mid >= l) update(rt << 1, l, r); if (tree[rt].mid < r) update(rt << 1 | 1, l, r); push_up(rt); } int query(int rt, int l, int r) { if (tree[rt].r < l || tree[rt].l > r) return 0; if (tree[rt].l >= l && tree[rt].r <= r) return tree[rt].sum; push_down(rt); int ans = 0; if (tree[rt].mid >= l) ans += query(rt << 1, l, r); if (tree[rt].mid < r) ans += query(rt << 1 | 1, l, r); push_up(rt); return ans; } int main() { int n, x; scanf( %d , &n); for (int i = 2; i <= n; i++) { scanf( %d , &x); G[x].push_back(i); G[i].push_back(x); } for (int i = 1; i <= n; i++) scanf( %d , &t[i]); dfs(1, -1); build(1, 1, n); int q; scanf( %d , &q); while (q--) { char op[4]; int v; scanf( %s%d , op, &v); if (op[0] == p ) update(1, in[v], ou[v]); else printf( %d n , query(1, in[v], ou[v])); } return 0; }
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_pll (
input rx_clk,
output tx_mining_clk
);
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign tx_mining_clk = sub_wire1;
wire sub_wire2 = rx_clk;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int n, m, k, par[maxn], ans[maxn]; bool arr[maxn]; pair<int, pair<int, int>> e[maxn]; int get_path(int v) { return par[v] < 0 ? v : (par[v] = get_path(par[v])); } void merge(int v, int u) { if ((v = get_path(v)) == (u = get_path(u))) return; if (par[v] < par[u]) swap(v, u); par[u] += par[v]; par[v] = u; arr[u] = arr[u] || arr[v]; } int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i < k; i++) { int x; cin >> x; arr[x] = 1; } for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; e[i] = {w, {u, v}}; } sort(e, e + m); int ind; memset(par, -1, sizeof(par)); for (int i = 0; i < m; i++) { int u = e[i].second.first, v = e[i].second.second; if ((u = get_path(u)) != (v = get_path(v)) && arr[u] && arr[v]) { ind = i; } merge(u, v); } for (int i = 0; i < k; i++) { cout << e[ind].first << ; } return 0; }
|
// Copyright (c) 2000 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// This tests DFF-like behavior. The clocked always block acts like a
// DFF, and if the -Fsynth flag to ivl is used, actually generates an
// LPM_FF device.
module main () ;
reg clk;
reg D, Q;
always #10 clk = ~clk;
always @(posedge clk) Q = D;
initial begin
clk = 0;
D = 0;
@(negedge clk)
if (Q !== 1'b0)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
D = 1;
@(negedge clk)
if (Q !== 1'b1)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
D = 'bx;
@(negedge clk)
if (Q !== 1'bx)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
D = 'bz;
@(negedge clk)
if (Q !== 1'bz)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|
/*
This block handles the autoincrement needed for bursting and detects
read responses
*/
`include "elink_regmap.v"
module erx_protocol (/*AUTOARG*/
// Outputs
erx_test_access, erx_test_data, erx_rdwr_access, erx_rr_access,
erx_packet,
// Inputs
clk, test_mode, rx_packet, rx_burst, rx_access
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h800; //link id
// System reset input
input clk;
//test mode
input test_mode; //block all traffic in test mode
output erx_test_access;
output [31:0] erx_test_data;
// Parallel interface, 8 eLink bytes at a time
input [PW-1:0] rx_packet;
input rx_burst;
input rx_access;
// Output to MMU / filter
output erx_rdwr_access;
output erx_rr_access;
output [PW-1:0] erx_packet;
//wires
reg [31:0] dstaddr_reg;
wire [31:0] dstaddr_next;
wire [31:0] dstaddr_mux;
reg erx_rdwr_access;
reg erx_rr_access;
reg [PW-1:0] erx_packet;
wire [11:0] myid;
wire [31:0] rx_addr;
wire read_response;
reg erx_test_access;
//parsing inputs
assign myid[11:0] = ID;
assign rx_addr[31:0] = rx_packet[39:8];
//Address generator for bursting
always @ (posedge clk)
if(rx_access)
dstaddr_reg[31:0] <= dstaddr_mux[31:0];
assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4'b1000;
assign dstaddr_mux[31:0] = rx_burst ? dstaddr_next[31:0] :
rx_addr[31:0];
//Read response detector
assign read_response = (rx_addr[31:20] == myid[11:0]) &
(rx_addr[19:16] == `EGROUP_RR);
//Pipeline stage and decode
always @ (posedge clk)
begin
//Write/read request
erx_rdwr_access <= ~test_mode & rx_access & ~read_response;
//Read response
erx_rr_access <= ~test_mode & rx_access & read_response;
//Test packet
erx_test_access <= test_mode & rx_access & ~read_response;
//Common packet
erx_packet[PW-1:0] <= {rx_packet[PW-1:40],
dstaddr_mux[31:0],
rx_packet[7:0]
};
end
//Testdata to write
assign erx_test_data[31:0] = erx_packet[71:40];
endmodule // erx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: pipeline.v (tranlate from pipeline.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from pipeline.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Pipeline
// AUTHOR: Steve Rhoads ()
// DATE CREATED: 6/24/02
// FILENAME: pipeline.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Controls the three stage pipeline by delaying the signals:
// a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
//-------------------------------------------------------------------
//Note: sigD <= sig after rising_edge(clk)
module pipeline (clk, reset, a_bus, a_busD, b_bus, b_busD, alu_func, alu_funcD,
shift_func, shift_funcD, mult_func, mult_funcD, reg_dest,
reg_destD, rd_index, rd_indexD, rs_index, rt_index, pc_source,
mem_source, a_source, b_source, c_source, c_bus, pause_any,
pause_pipeline);
input clk;
input reset;
input [31:0] a_bus;
input [31:0] b_bus;
input [ 3:0] alu_func;
input [ 1:0] shift_func;
input [ 3:0] mult_func;
input [31:0] reg_dest;
input [ 5:0] rd_index;
input [ 5:0] rs_index;
input [ 5:0] rt_index;
input [ 1:0] pc_source;
input [ 3:0] mem_source;
input [ 1:0] a_source;
input [ 1:0] b_source;
input [ 2:0] c_source;
input [31:0] c_bus;
input pause_any;
output [31:0] a_busD;
output [31:0] b_busD;
output [ 3:0] alu_funcD;
output [ 1:0] shift_funcD;
output [ 3:0] mult_funcD;
output [31:0] reg_destD;
output [ 5:0] rd_indexD;
output pause_pipeline;
reg [31:0] a_busD;
reg [31:0] b_busD;
reg [ 3:0] alu_funcD;
reg [ 1:0] shift_funcD;
reg [ 3:0] mult_funcD;
reg [ 5:0] rd_index_reg;
reg [31:0] reg_dest_reg;
reg [31:0] reg_dest_delay;
reg [ 2:0] c_source_reg;
reg pause_mult_clock;
reg pause_enable_reg;
wire [31:0] reg_destD = reg_dest_delay ;
wire [ 5:0] rd_indexD = rd_index_reg ;
wire pause_pipeline = pause_mult_clock & pause_enable_reg ;
wire freeze_pipeline = ~(pause_mult_clock & pause_enable_reg) &
pause_any;
//When operating in three stage pipeline mode, the following signals
//are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
//c_source, and rd_index.
always @(posedge clk or posedge reset) begin
if (reset) begin
pause_enable_reg <= 1'b1 ;
rd_index_reg <= 6'b000000 ;
a_busD <= `ZERO;
b_busD <= `ZERO;
alu_funcD <= 4'b0000;
shift_funcD <= 2'b00;
mult_funcD <= 4'b0000;
reg_dest_reg <= `ZERO;
c_source_reg <= 3'b000;
end else begin
if (~freeze_pipeline)
begin
if ((rs_index == 6'b000000 | rs_index != rd_index_reg) |
(a_source != `a_from_reg_source | ~pause_enable_reg))
a_busD <= a_bus ;
else
a_busD <= reg_dest_delay ; //rs from previous operation (bypass stage)
if ((rt_index == 6'b000000 | rt_index != rd_index_reg) |
(b_source != `b_from_reg_target | ~pause_enable_reg))
b_busD <= b_bus ;
else
b_busD <= reg_dest_delay ; //rt from previous operation
alu_funcD <= alu_func ;
shift_funcD <= shift_func;
mult_funcD <= mult_func ;
reg_dest_reg <= reg_dest ;
c_source_reg <= c_source ;
rd_index_reg <= rd_index ;
end
if (~pause_enable_reg & ~pause_any)
pause_enable_reg <= 1'b1 ; //enable pause_pipeline
else if (pause_mult_clock)
pause_enable_reg <= 1'b0 ; //disable pause_pipeline
end
end
always @(pc_source or mem_source or mult_func or c_source_reg or
c_bus or reg_dest_reg) begin
if ((pc_source != `from_inc4 & pc_source != `from_opcode25_0) |
mem_source != `mem_fetch |
(mult_func == `mult_read_lo | mult_func == `mult_read_hi))
pause_mult_clock = 1'b1;
else
pause_mult_clock = 1'b0;
if (c_source_reg == `c_from_alu)
reg_dest_delay = c_bus; //delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay = reg_dest_reg; //need to delay 1 clock cycle from reg_dest
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 11:52:43 AM
// Design Name:
// Module Name: Oper_Start_In
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Oper_Start_In
# (parameter W = 32 ) // This parameter could be adjust based
//on the desire precision format
//W = 64 indicates the double precision format
//W = 32 indicates the single precision format
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//The ctrl_x signals are used to load certain registers within the module
input wire load_b_i,
input wire add_subt_i, //This signal selects if the operations is an add o subtract operation
input wire [W-1:0] Data_X_i, //Data_X and Data_y are both operands of the module
//they are expected in ieee 754 format
input wire [W-1:0] Data_Y_i,
//////////////////////////////////////////////////////////////////////
output wire [W-2:0] DMP_o, //Because the algorithm these outputs contain the largest and smallest operand
output wire [W-2:0] DmP_o,
output wire zero_flag_o, //Flag for FSM when the subt result is zero
output wire real_op_o, //bit for real add/subt operation in case for -DataY
output wire sign_final_result_o //bit for sign result
);
//Wire Signals useful to interconnect the components of the module
wire [W-1:0] intDX; //Output of register DATA_X
wire [W-1:0] intDY; //Output of register DATA_Y
wire intAS; //Output of register add_subt
wire gtXY; //Output for magntiude_comparator (X>Y)
wire eqXY; //Output for magntiude_comparator (X=Y)
wire [W-2:0] intM; //Output of MuxXY for bigger value
wire [W-2:0] intm; //Output of MuxXY for small value
///////////////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) XRegister ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Data_X_i),
.Q(intDX)
);
RegisterAdd #(.W(W)) YRegister ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Data_Y_i),
.Q(intDY)
);
RegisterAdd #(.W(1)) ASRegister ( //Data Add_Subtract input register
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(add_subt_i),
.Q(intAS)
);
Comparator #(.W(W-1)) Magnitude_Comparator ( //Compare between magnitude for DATA_X and DATA_Y and select whos bigger and if there's a equality
.Data_X_i(intDX[W-2:0]),
.Data_Y_i(intDY[W-2:0]),
.gtXY_o(gtXY),
.eqXY_o(eqXY)
);
xor_tri #(.W(W)) Op_verification ( //Operation between the DATA_X & Y's sign bit and the operation bit to find the real operation for ADDER/SUBTRACT
.A_i(intDX[W-1]),
.B_i(intDY[W-1]),
.C_i(intAS),
.Z_o(real_op_o)
);
sgn_result result_sign_bit (//Calculate the sign bit for the final result
.Add_Subt_i(intAS),
.sgn_X_i(intDX[W-1]),
.sgn_Y_i(intDY[W-1]),
.gtXY_i(gtXY),
.eqXY_i(eqXY),
.sgn_result_o(sign_result)
);
MultiplexTxT #(.W(W-1)) MuxXY (//Classify in the registers the bigger value (M) and the smaller value (m)
.select(gtXY),
.D0_i(intDX[W-2:0]),
.D1_i(intDY[W-2:0]),
.S0_o(intM),
.S1_o(intm)
);
RegisterAdd #(.W(W-1)) MRegister ( //Data_M register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(intM),
.Q(DMP_o)
);
RegisterAdd #(.W(W-1)) mRegister ( //Data_m register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(intm),
.Q(DmP_o)
);
RegisterAdd #(.W(1)) SignRegister (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(sign_result),
.Q(sign_final_result_o)
);
assign zero_flag_o = real_op_o & eqXY;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int BASE = 27; const int N = 200000 + 2; const int LOGN = 20; const long long oo = 1e18; const double EPS = 1e-9; int n, q, a[N], mn[N], mx[N], freq[N], dsu[N], bst[N], sum[N]; int find(int i) { return dsu[i] == i ? i : dsu[i] = find(dsu[i]); } struct seg { int l, r, val; seg(int _l, int _r, int _val) { l = _l, r = _r, val = _val; } bool operator<(const seg& sg) const { return l < sg.l; } }; vector<seg> cln; vector<seg> sg; int main() { memset(mn, -1, sizeof mn); cin >> n >> q; for (int i = 1; i <= 200000; ++i) dsu[i] = i; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); freq[a[i]]++; if (mn[a[i]] == -1) { mn[a[i]] = mx[a[i]] = i; } mx[a[i]] = max(mx[a[i]], i); mn[a[i]] = min(mn[a[i]], i); } for (int i = 1; i <= 200000; ++i) { if (mn[i] == -1) continue; sg.push_back(seg(mn[i], mx[i], i)); } sort(sg.begin(), sg.end()); for (int i = 0; i < sg.size(); ++i) { if (cln.size() && cln.back().r >= sg[i].l) { dsu[find(cln.back().val)] = find(sg[i].val); cln.back().r = max(cln.back().r, sg[i].r); continue; } cln.push_back(sg[i]); } for (int i = 1; i <= 200000; ++i) { if (mn[i] == -1) continue; bst[find(i)] = max(bst[find(i)], freq[i]); sum[find(i)] += freq[i]; } int ans = 0; for (int i = 1; i <= 200000; ++i) { if (find(i) == i) { ans += sum[i] - bst[i]; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int nax = 1e5 + 10; vector<int> tree(4 * nax); long long i, j, x, y, k; bool sortbysec(const pair<long long, long long> &a, const pair<long long, long long> &b) { return (a.second < b.second); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, cnt = 0; cin >> n; vector<vector<long long>> a(n + 1); for (i = 0; i < n - 1; i++) { cin >> x >> y; a[x].push_back(y); a[y].push_back(x); } for (i = 1; i <= n; i++) { if (a[i].size() == 1) cnt++; } cout << cnt << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:28:42 11/06/2013
// Design Name:
// Module Name: FrequencyDivider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//-------------------------DIVISOR DE FRECUENCIA-----------------------------------
/* Descripción: Se entrega una frecuencia de salida clk_out a partir de una frecuencia
de entrada clk. El usuario debe ingresar los valores correspondientes a las variables
Ts(periodo de salida) y Te(periodo de entrada)en base a la frecuencias con las que se va a
trabajar.
Funcionamiento: Se define el parametro n = (periodo de salida)/(2*periodo de entrada)-1
la variable counter va contando desde 0 hasta el valor de n veces el reloj de
la frecuencia de entrada. Cada vez que counter alcanza el valor de n se modifica
el estado de clk_out(1 o 0).
IMPORTANTE: valores de Ts y Te deben estar en las mismas unidades, para este ejemplo se emplean nano segundos.
en este codigo se desea una frecuencia de salida de 12,5MHz(es decir un periodo de 80ns) a partir de una frecuencia
de entrada de 50MHz(es de cir un periodo de 20ns), si se desea efectuar la operacion con otra frecuencia de salida o
de entrada se deben modificar los valores de las variables Ts y Te como se menciono anteriormente.
*/
module FrequencyDivider(clk,clk_out);
input clk;
output reg clk_out;
reg rst;
/* el parametro n es la razon entre el periodo de salida sobre
dos veces el periodo de entrada menos uno ya que cuenta desde 0, en este caso */
parameter Ts = 80;
parameter Te = 20;
parameter n = ((Ts/(2*Te))-1);//si las unidades de Ts y Te son iguales se desprecian ya que en la division se cancelan.
/* El parametro BitCount es el numero de bits necesarios para representar el paramtro n en binario, con
el fin de reducir calculos se le asigna a bitcount un valor grande en este caso 31 para no tener que efectuar la
convercion a binario de cada parametron, si en algun caso el numero para representar el valor de n en
binario es mayor a 31 este debe modificarse */
parameter bitCount = 31;
reg [bitCount:0] counter;// vector de bitCount bits de tipo reg cuyo bit mas significante es el que ocupa
// la posición bitCounter-1
initial
rst=0;// la variable rst se usa para poner las condiciones iniciales para empezar el conteo
always @(posedge clk or negedge rst)//el proceso se evalua cada vez que se produce un flanco de subida en clk(0 a 1)
//o un flanco de bajada es rst(1 a 0)
// se ponen los valores iniciales para dar paso al conteo
begin
if(!rst)// si rst = 0
begin
rst<=1;
counter<=32'd0;
clk_out <= 1'b0;//el reloj de baja frecuencia empieza en cero
end
// cuando rst = 1 es decir se inicia el conteo
else
//si counter alcanzo el valor de n se cambia el estado de clk_out,se pone counter en 0 para que vuelva a contar
// y se modifica el valor de clk_out
if(counter==n)
begin
counter<=32'd0;
clk_out <= ~clk_out;
end
// empieza a contar la variable counter si counter<divisor y rst=1
else
begin
counter<=counter+1;
end
end
endmodule
|
//#############################################################################
//# Function: Phase Locked Loop #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pll #(parameter N = 8) // number of clocks
( input clkin, // primary clock input
input nreset, // async active low reset
input clkfb, // feedback clock
input pll_en, // enable pll
input [N*8-1:0] clkdiv, // clock divider settings (per clock)
input [N*16-1:0] clkphase, // clock phase setting (rise/fall edge)
input [7:0] clkmult, // feedback clock multiplier
output [N-1:0] clkout, // output clocks
output locked // PLL locked status
);
`ifdef TARGET_SIM
//insert PLL simulation model
`endif
endmodule // oh_pll
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : pdl_puf
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
//
// This is probably what you are looking for.
//
// This module takes 2 signals and pdl configuration bits for 2 lines as inputs.
// Instantiates 64 pdl_switches and sends the received 2 signals along the switches
// Also assigns the configuration bits to switches.
// Final output signal is passed through arbiter and response is evaluated.
// The evaluated response will be sent back to higher modules.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module pdl_puf (s_tp, s_btm, s1, s2, reset, o);
// s: The challenge vector of size PUFlength
// q: The input trigger signal to the PUF (launch signal)
// reset: Resets the PUF output to zero and prepares it for the next round
// o: The output of the arbiters (response)
// s1: a sum bit from adder1;
// s2: a sum bit from adder2
parameter PUFlength = 63;
input [PUFlength:0] s_tp, s_btm;
input s1, s2, reset;
output o;
wire [PUFlength:0] i1,i2;
wire puf_out;
(* KEEP_HIERARCHY="TRUE" *)
pdl_switch sarray [PUFlength:0] (
.i1({s1,i1[PUFlength:1]}),
.i2({s2,i2[PUFlength:1]}),
.select_tp(s_tp[PUFlength:0]),
.select_btm(s_btm[PUFlength:0]),
.o1(i1[PUFlength:0]),
.o2(i2[PUFlength:0])
);
// Arbiter to decide which signal reached first.
FDC FDC1 (.Q (puf_out),
.C (i2[0]),
.CLR (reset),
.D (i1[0]));
(* BEL ="D6LUT" *) (* LOCK_PINS = "all" *)
LUT1 #(
.INIT(2'b10) // Specify LUT Contents
) LUT1_inst_2 (
.O(o), // LUT general output
.I0(puf_out) // LUT input
);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Maintain_Range_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Maintain_Range
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Maintain_Range_block
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En33
output signed [17:0] Out1; // sfix18_En15
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En15
// <S19>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Maintain_Range_block
|
// Copyright (C) 2012
// Ashwin A. Mendon
//
// This file is part of SATA2 core.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////////////
// ENTITY: scrambler
// Version: 1.0
// Author: Ashwin Mendon
// Description: This sub/module implements the Scrambler Circuit for the SATA Protocol
// The code provides a parallel implementation of the following
// generator polynomial
// 16 15 13 4
// G(x) = x + x + x + x + 1
// The output of this scrambler is then XORed with the input data DWORD
// The scrambler is initialized to a value of 0xF0F6.
// The first DWORD output of the implementation is equal to 0xC2D2768D
// PORTS:
/////////////////////////////////////////////////////////////////////////////////////////
module scrambler (
clk,
rst,
en,
prim_scrambler,
din,
dout
);
input clk;
input rst;
input en;
input prim_scrambler;
input [31:0] din;
output [31:0] dout;
//Parameters
parameter SCRAMBLER_INIT = 16'hF0F6;
//Registers/Wires
reg [15:0] context;
wire [31:0] context_next;
reg [31:0] context_reg;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
context <= SCRAMBLER_INIT;
context_reg <= 32'h0;
end
else begin
if (en) begin
context <= context_next[31:16];
context_reg <= context_next;
end
end
end
assign dout = (prim_scrambler) ? context_reg : context_reg ^ din;
//Aysnchronous Logic
assign context_next[31] = context[12] ^
context[10] ^
context[7] ^
context[3] ^
context[1] ^
context[0];
assign context_next[30] = context[15] ^
context[14] ^
context[12] ^
context[11] ^
context[9] ^
context[6] ^
context[3] ^
context[2] ^
context[0];
assign context_next[29] = context[15] ^
context[13] ^
context[12] ^
context[11] ^
context[10] ^
context[8] ^
context[5] ^
context[3] ^
context[2] ^
context[1];
assign context_next[28] = context[14] ^
context[12] ^
context[11] ^
context[10] ^
context[9] ^
context[7] ^
context[4] ^
context[2] ^
context[1] ^
context[0];
assign context_next[27] = context[15] ^
context[14] ^
context[13] ^
context[12] ^
context[11] ^
context[10] ^
context[9] ^
context[8] ^
context[6] ^
context[1] ^
context[0];
assign context_next[26] = context[15] ^
context[13] ^
context[11] ^
context[10] ^
context[9] ^
context[8] ^
context[7] ^
context[5] ^
context[3] ^
context[0];
assign context_next[25] = context[15] ^
context[10] ^
context[9] ^
context[8] ^
context[7] ^
context[6] ^
context[4] ^
context[3] ^
context[2];
assign context_next[24] = context[14] ^
context[9] ^
context[8] ^
context[7] ^
context[6] ^
context[5] ^
context[3] ^
context[2] ^
context[1];
assign context_next[23] = context[13] ^
context[8] ^
context[7] ^
context[6] ^
context[5] ^
context[4] ^
context[2] ^
context[1] ^
context[0];
assign context_next[22] = context[15] ^
context[14] ^
context[7] ^
context[6] ^
context[5] ^
context[4] ^
context[1] ^
context[0];
assign context_next[21] = context[15] ^
context[13] ^
context[12] ^
context[6] ^
context[5] ^
context[4] ^
context[0];
assign context_next[20] = context[15] ^
context[11] ^
context[5] ^
context[4];
assign context_next[19] = context[14] ^
context[10] ^
context[4] ^
context[3];
assign context_next[18] = context[13] ^
context[9] ^
context[3] ^
context[2];
assign context_next[17] = context[12] ^
context[8] ^
context[2] ^
context[1];
assign context_next[16] = context[11] ^
context[7] ^
context[1] ^
context[0];
assign context_next[15] = context[15] ^
context[14] ^
context[12] ^
context[10] ^
context[6] ^
context[3] ^
context[0];
assign context_next[14] = context[15] ^
context[13] ^
context[12] ^
context[11] ^
context[9] ^
context[5] ^
context[3] ^
context[2];
assign context_next[13] = context[14] ^
context[12] ^
context[11] ^
context[10] ^
context[8] ^
context[4] ^
context[2] ^
context[1];
assign context_next[12] = context[13] ^
context[11] ^
context[10] ^
context[9] ^
context[7] ^
context[3] ^
context[1] ^
context[0];
assign context_next[11] = context[15] ^
context[14] ^
context[10] ^
context[9] ^
context[8] ^
context[6] ^
context[3] ^
context[2] ^
context[0];
assign context_next[10] = context[15] ^
context[13] ^
context[12] ^
context[9] ^
context[8] ^
context[7] ^
context[5] ^
context[3] ^
context[2] ^
context[1];
assign context_next[9] = context[14] ^
context[12] ^
context[11] ^
context[8] ^
context[7] ^
context[6] ^
context[4] ^
context[2] ^
context[1] ^
context[0];
assign context_next[8] = context[15] ^
context[14] ^
context[13] ^
context[12] ^
context[11] ^
context[10] ^
context[7] ^
context[6] ^
context[5] ^
context[1] ^
context[0];
assign context_next[7] = context[15] ^
context[13] ^
context[11] ^
context[10] ^
context[9] ^
context[6] ^
context[5] ^
context[4] ^
context[3] ^
context[0];
assign context_next[6] = context[15] ^
context[10] ^
context[9] ^
context[8] ^
context[5] ^
context[4] ^
context[2];
assign context_next[5] = context[14] ^
context[9] ^
context[8] ^
context[7] ^
context[4] ^
context[3] ^
context[1];
assign context_next[4] = context[13] ^
context[8] ^
context[7] ^
context[6] ^
context[3] ^
context[2] ^
context[0];
assign context_next[3] = context[15] ^
context[14] ^
context[7] ^
context[6] ^
context[5] ^
context[3] ^
context[2] ^
context[1];
assign context_next[2] = context[14] ^
context[13] ^
context[6] ^
context[5] ^
context[4] ^
context[2] ^
context[1] ^
context[0];
assign context_next[1] = context[15] ^
context[14] ^
context[13] ^
context[5] ^
context[4] ^
context[1] ^
context[0];
assign context_next[0] = context[15] ^
context[13] ^
context[4] ^
context[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1200005; const int OO = 0x3f3f3f3; int vis[maxn]; vector<int> p; int N = 1200000; void find_prime() { p.clear(); memset(vis, 0, sizeof(vis)); for (int i = 2; i <= N; i++) if (!vis[i]) for (int j = i * 2; j <= N; j += i) vis[j] = 1; for (int i = 2; i <= N; i++) if (!vis[i]) p.push_back(i); } vector<int> palin; void find_palin() { palin.clear(); for (int i = 1; i <= 9; i++) { palin.push_back(i); palin.push_back(i * 11); } for (int i = 1; i <= 9; i++) for (int j = 0; j <= 9; j++) { palin.push_back(i * 101 + j * 10); palin.push_back(i * 1001 + j * 110); } for (int i = 1; i <= 9; i++) for (int j = 0; j <= 9; j++) for (int k = 0; k <= 9; k++) { palin.push_back(i * 10001 + j * 1010 + k * 100); palin.push_back(i * 100001 + j * 10010 + k * 1100); } for (int i = 0; i <= 1; i++) for (int j = 0; j <= 9; j++) for (int k = 0; k <= 9; k++) { palin.push_back(1000001 + i * 100010 + j * 10100 + k * 1000); } sort(palin.begin(), palin.end()); } int cnt_prime[maxn], cnt_palin[maxn]; int main() { find_prime(); find_palin(); memset(cnt_palin, 0, sizeof(cnt_palin)); memset(cnt_prime, 0, sizeof(cnt_prime)); for (int i = 2; i <= N; i++) cnt_prime[i] = cnt_prime[i - 1] + 1 - vis[i]; memset(vis, 0, sizeof(vis)); for (int i = 0; i < palin.size(); i++) vis[palin[i]] = 1; for (int i = 1; i <= N; i++) cnt_palin[i] = cnt_palin[i - 1] + vis[i]; int sz = palin.size(); int ans = -1; int x, y; scanf( %d%d , &x, &y); for (int i = sz - 1; i >= 0; i--) if (cnt_prime[palin[i]] * y <= cnt_palin[palin[i]] * x) { ans = palin[i]; break; } sz = p.size(); for (int i = sz - 1; i >= 0; i--) if (cnt_prime[p[i] - 1] * y <= cnt_palin[p[i] - 1] * x) { if (p[i] - 1 > ans) ans = p[i] - 1; break; } if (ans == -1) printf( Palindromic tree is better than splay tree n ); else printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[222][105]; int dp2[105]; char cc[555]; char c[111]; char a[111]; int alen, clen; int main() { int b, d; scanf( %d %d n , &b, &d); gets(a); gets(c); alen = strlen(a); clen = strlen(c); for (int i = 0; i < clen; i++) { cc[i] = cc[i + clen] = c[i]; } for (int i = 0; i < clen; i++) { int p = i; for (int j = 0; j < alen; j++) { if (a[j] == c[p]) { p++; dp2[i]++; } if (p == clen) p = 0; } } int len = 0; int curr = 0; for (int i = 0; i < b; i++) { len += dp2[curr]; curr = dp2[curr] + curr; curr %= clen; } int ans = len / (clen * d); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int arr[500005], sum[500005]; bool vis[100005]; map<long long int, long long int> hola; map<pair<long long int, long long int>, long long int> con; vector<pair<long long int, long long int>> conn; int main() { long long int n, maxi = INT_MIN; cin >> n; for (long long int i = 0; i < n; i++) { cin >> arr[i]; hola[arr[i]]++; } for (long long int i = 0; i < n; i++) { if (hola[arr[i]] > maxi) maxi = hola[arr[i]]; } cout << maxi; return 0; }
|
/* a lpc decoder
* lpc signals:
* lpc_ad: 4 data lines
* lpc_frame: frame to start a new transaction. active low
* lpc_reset: reset line. active low
* output signals:
* out_cyctype_dir: type and direction. same as in LPC Spec 1.1
* out_addr: 16-bit address
* out_data: data read or written (1byte)
* out_clock_enable: on rising edge all data must read.
*/
module lpc(
input [3:0] lpc_ad,
input lpc_clock,
input lpc_frame,
input lpc_reset,
input reset,
output [3:0] out_cyctype_dir,
output [31:0] out_addr,
output [7:0] out_data,
output out_sync_timeout,
output reg out_clock_enable);
/* type and direction. same as in LPC Spec 1.1 */
/* addr + data written or read */
/* state machine */
reg [3:0] state = 0;
localparam idle = 0, start = 1, cycle_dir = 2, address = 3, tar = 4, sync = 5, read_data = 6, abort = 7;
/* counter used by some states */
reg [3:0] counter;
/* mode + direction. same as in LPC Spec 1.1 */
reg [3:0] cyctype_dir;
reg [31:0] addr;
reg [7:0] data;
always @(negedge lpc_clock or negedge lpc_reset) begin
if (~lpc_reset) begin
state <= idle;
counter <= 1;
end
else begin
if (~lpc_frame) begin
counter <= 1;
if (lpc_ad == 4'b0000) /* start condition */
state <= cycle_dir;
else
state <= idle; /* abort */
end else begin
counter <= counter - 1;
case (state)
cycle_dir:
cyctype_dir <= lpc_ad;
address: begin
addr[31:4] <= addr[27:0];
addr[3:0] <= lpc_ad;
end
read_data: begin
data[7:4] <= lpc_ad;
data[3:0] <= data[7:4];
end
sync: begin
if (lpc_ad == 4'b0000)
if (cyctype_dir[3] == 0) begin /* i/o or memory */
state <= read_data;
data <= 0;
counter <= 2;
end else
state <= idle; /* unsupported dma or reserved */
end
default:
begin end
endcase
if (counter == 1) begin
case (state)
idle: begin end
cycle_dir: begin
out_clock_enable <= 0;
out_sync_timeout <= 0;
if (lpc_ad[3:2] == 2'b00) begin /* i/o */
state <= address;
counter <= 4;
addr <= 0;
end
else if (lpc_ad[3:2] == 2'b01) begin /* memory */
state <= address;
counter <= 8;
addr <= 0;
end else begin /* dma or reserved not yet supported */
state <= idle;
end
end
address: begin
if (cyctype_dir[1]) /* write memory or i/o */
state <= read_data;
else /* read memory or i/o */
state <= tar;
counter <= 2;
end
tar: begin
state <= sync;
counter <= 1;
end
sync: begin
if (lpc_ad == 4'b1111) begin
out_sync_timeout <= 1;
out_clock_enable <= 1;
state <= idle;
end
end
read_data: begin
out_clock_enable <= 1;
state <= idle;
end
/* todo: missing TAR after read_data */
abort: counter <= 2;
endcase
end
end
end
end
assign out_cyctype_dir = cyctype_dir;
assign out_data = data;
assign out_addr = addr;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s1[200005], s2[200005]; int len; bool judge(int p, char *s1, char *s2) { for (int i = 0; i < p; i++) { if (s1[i] != s2[i]) return 0; } return 1; } int check(int p, char *s1, char *s2) { if (p == 1) { if (s1[0] != s2[0]) return 0; return 1; } if (judge(p, s1, s2)) return 1; int len = p; if (len & 1) return 0; return (check(len / 2, s1, s2) && check(len / 2, s1 + len / 2, s2 + len / 2)) || (check(len / 2, s1 + len / 2, s2) && check(len / 2, s1, s2 + len / 2)); } int main(void) { int i, j; while (~scanf( %s%s , s1, s2)) { int len = strlen(s1); if (check(len, s1, s2)) puts( YES ); else puts( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; long long a[10010]; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); sort(a + 1, a + 1 + n); long long sum = 0; for (int i = 1; i <= k; i++) sum += a[i]; printf( %lld n , sum); return 0; }
|
`timescale 1ns / 1ps
//-----------------------------------------------------------------------------
// Title : JTAG VPI virtual interface
// Project : KPU
//-----------------------------------------------------------------------------
// File : v_jtag_vpi.v
// Author : acorallo <>
// Created : 03.06.2017
//-----------------------------------------------------------------------------
// Description :
// Execution stage implementation file for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2017 by Authors.
//------------------------------------------------------------------------------
// Derived from SoC/OpenRISC Development Interface
// Orignal Authors Author(s):
// Igor Mohor ()
// Gyorgy Jeney ()
// Nathan Yawn ()
//-----------------------------------------------------------------------------
`ifndef _v_jtag
`define _v_jtag
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many clk_o ticks. Must be less than 6 bits.
// `define JTAG_INPUT_FILE "tap_input_test_data.txt"
// `define JTAG_OUTPUT_FILE "tap_output_test_data.txt"
module v_jtag (
input wire clk_i,
output wire tms_o,
output wire tck_o,
output wire trst_o,
output wire tdi_o,
input wire tdo_i,
input wire tdo_oe_i
);
reg [4:0] memory;
reg [3:0] in_word_r;
reg [5:0] clk_count;
`ifdef JTAG_INPUT_FILE
reg [8:0] c;
integer t;
integer fd_in;
integer fd_out;
integer read_count;
`endif
// Handle commands from the upper level
initial begin
in_word_r = 5'b0;
memory = 5'b0;
`ifndef JTAG_INPUT_FILE
$jp_init(`JP_PORT);
`else
fd_in = $fopen(`JTAG_INPUT_FILE, "r");
if (fd_in == 0)
$display ("JTAG: stimulus file wasn't found");
fd_out = $fopen(`JTAG_OUTPUT_FILE, "w");
`endif
#5500; // Wait until reset is complete
while(1) begin
#1;
`ifndef JTAG_INPUT_FILE
$jp_in(memory); // This will not change memory if no command has been sent from jp
`else
memory[4] = 1;
if (fd_in)
read_count = $fscanf (fd_in, "%b", memory[3:0]);
if (!read_count) begin
c = $fgetc(fd_in);
if (c == "\#") begin
// Comment
while ($fgetc(fd_in) != "\n")
#0;
end
else if (c == "\S") begin
// Sleep
read_count = $fscanf (fd_in, "%b", t);
while(t) begin
t = t - 1;
#1;
end
end
end // if (!read_count)
#100; // jtag is supposed to be much slower then the cpu
`endif
if(memory[4]) begin
in_word_r = memory[3:0];
memory = memory & 4'b1111;
clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
end
end
end
// Send the output bit to the upper layer
`ifndef JTAG_INPUT_FILE
always @ (tdo_i)
$jp_out(tdo_i);
`else
always @ (posedge tck_o)
if (tdo_oe_i)
$fwrite(fd_out, "%b", tdo_i);
`endif
assign tck_o = in_word_r[0];
assign trst_o = in_word_r[1];
assign tdi_o = in_word_r[2];
assign tms_o = in_word_r[3];
// Send timeouts / wait periods to the upper layer
always @ (posedge clk_i) begin
if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
else if(clk_count == `TIMEOUT_COUNT) begin //
`ifndef JTAG_INPUT_FILE
$jp_wait_time(); //
`endif
clk_count[5:0] = clk_count[5:0] + 1;
end //
// else it's already timed out, don't do anything
end
endmodule
`endif
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_Onchip_Memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../video_sys_Onchip_Memory.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "video_sys_Onchip_Memory.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<ll, ll>; const ll MOD = 1e9 + 7, N = 1e5 + 10; const ll LG = log2(N) + 1; struct LCA { vector<vector<ll>> G, parent; vector<ll> tin, tout, depth; ll timer; ll n; ll LG; LCA(vector<vector<ll>> G, ll R = 1) { this->G = G; this->n = G.size(); this->LG = log2(n) + 1; this->timer = 0; tin.assign(n, 0); tout.assign(n, 0); depth.assign(n, 0); tin[0] = ++timer; parent = vector<vector<ll>>(n, vector<ll>(LG)); dfs(R); tout[0] = ++timer; compute(); } void dfs(ll u, ll p = 0, ll d = 0) { parent[u][0] = p; tin[u] = ++timer; depth[u] = d; for (auto &v : G[u]) { if (v != p) { dfs(v, u, d + 1); } } tout[u] = ++timer; } void compute() { for (ll j = 1; j < LG; j++) { for (ll i = 1; i < n; i++) { if (parent[i][j - 1]) { parent[i][j] = parent[parent[i][j - 1]][j - 1]; } } } } bool is_anc(ll u, ll v) { return tin[u] <= tin[v] and tout[v] <= tout[u]; } ll lca(ll u, ll v) { if (is_anc(u, v)) return u; if (is_anc(v, u)) return v; for (ll i = LG - 1; i >= 0; i--) { if (!is_anc(parent[u][i], v)) { u = parent[u][i]; } } u = parent[u][0]; return u; } ll dist(ll u, ll v) { return depth[u] + depth[v] - 2 * depth[lca(u, v)]; } }; int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); ll n, q; cin >> n >> q; vector<vector<ll>> G(n + 1); for (ll i = 2; i < n + 1; i++) { ll p; cin >> p; G[i].push_back(p); G[p].push_back(i); } LCA lc(G); while (q--) { ll a, b, c; cin >> a >> b >> c; vector<ll> A = {a, b, c}; sort(A.begin(), A.end()); ll ans = 0; ll cn = 0; do { cn++; ll s = A[0], f = A[1], t = A[2]; if (lc.lca(s, t) == lc.lca(f, t)) { if (lc.depth[lc.lca(s, t)] <= lc.depth[t]) { ans = max(ans, lc.depth[t] + lc.depth[lc.lca(s, f)] - 2 * lc.depth[lc.lca(s, t)]); } } else { if (lc.depth[lc.lca(s, t)] < lc.depth[t] and lc.depth[lc.lca(f, t)] < lc.depth[t]) { ans = max(ans, lc.depth[t] - max(lc.depth[lc.lca(s, t)], lc.depth[lc.lca(f, t)])); } } } while (next_permutation(A.begin(), A.end())); cout << ans + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string myNumber; cin >> myNumber; int temp; int fhalf = 0, shalf = 0; for (int i = 0; i < n / 2; ++i) { temp = myNumber[i] - 0 ; if (temp != 4 && temp != 7) { cout << NO ; goto exit; } shalf += temp; } for (int i = n / 2; i < n; ++i) { temp = myNumber[i] - 0 ; if (temp != 4 && temp != 7) { cout << NO ; goto exit; } fhalf += temp; } if (fhalf == shalf) cout << YES ; else cout << NO ; exit: return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 4; int a[4]; for (int i = 0; i < 4; i++) { cin >> a[i]; } sort(a, a + n); for (int i = 0; i < 3; i++) { cout << a[3] - a[i] << ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_1_V
`define SKY130_FD_SC_LP__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_1_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_stub.v
// Design : zynq_design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zynq_design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int d = 5; const int MAX = 1 << d; const int TOTAL = 374; inline int bit(unsigned int mask, int k) { return (mask >> k) & 1; } int __builtin_fnz(unsigned int x) { return 31 - __builtin_clz(x); } void printm(unsigned int mask, int k = d) { for (int i = 0; i < k; ++i) printf( %d , bit(mask, i)); printf( n ); } int dim(unsigned int V) { int res = 0; for (; V != 1; ++res) V &= (1U << (1 << __builtin_fnz(__builtin_fnz(V)))) - 1; return res; } unsigned int join_v(unsigned int U, int x) { unsigned int X = U; for (int v = 0; v < MAX; ++v) if (bit(U, v)) X |= 1U << (v ^ x); return X; } unsigned int join(unsigned int U, unsigned int V) { unsigned int X = U; int x; while (V != 1) { x = __builtin_fnz(V); X |= join_v(X, x); V &= (1U << (1U << __builtin_fnz(x))) - 1; } return X; } void show(unsigned int V) { printf( %d n , dim(V)); printf( %u n , V); printm(V, MAX); for (int v = 0; v < MAX; ++v) if (bit(V, v)) printm(v, d); printf( n ); } const int MOD = (int)1e9 + 7; void add(int& a, int b) { a += b; if (a >= MOD) a -= MOD; } void mult(int& a, int b) { a = (a * 1LL * b) % MOD; } int prod(int a, int b) { return (a * 1LL * b) % MOD; } const int N = (int)1e5; vector<pair<int, int> > g[N]; int pref[N]; int tab[TOTAL][TOTAL]; int dp[2][TOTAL + 1]; int main() { vector<unsigned int> subspaces; subspaces.push_back(1); for (int i = 0; i < d; ++i) { vector<unsigned int> nsubspaces; for (unsigned int U : subspaces) { nsubspaces.push_back(U); for (int v = (1 << i); v < (1 << (i + 1)); ++v) nsubspaces.push_back(join_v(U, v)); } sort((nsubspaces).begin(), (nsubspaces).end()); nsubspaces.erase(unique((nsubspaces).begin(), (nsubspaces).end()), nsubspaces.end()); subspaces = nsubspaces; } assert(TOTAL == (int)(subspaces).size()); function<int(unsigned int)> id = [&](unsigned int V) { int i = lower_bound((subspaces).begin(), (subspaces).end(), V) - subspaces.begin(); return i; }; for (int i = 0; i < TOTAL; ++i) for (int j = 0; j < TOTAL; ++j) { if ((subspaces[i] & subspaces[j]) != 1) tab[i][j] = TOTAL; else tab[i][j] = id(join(subspaces[i], subspaces[j])); } int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) { int u, v, w; scanf( %d %d %d , &u, &v, &w); --u; --v; g[u].push_back({v, w}); g[v].push_back({u, w}); } int t = 0, nt = 1; memset(dp[t], 0, sizeof dp[t]); dp[t][id(1)] = 1; memset(pref, -1, sizeof pref); pref[0] = 0; for (auto& [start, weight] : g[0]) { if (pref[start] != -1) continue; int vec = -1; unsigned int V = 1; function<void(int, int, bool&)> dfs = [&](int v, int par, bool& ok) { for (auto& [u, w] : g[v]) { if (pref[u] == -1) { pref[u] = pref[v] ^ w; dfs(u, v, ok); } else { if (u > v || u == par) continue; int add = pref[u] ^ pref[v] ^ w; if (u == 0) { vec = add; } else { if (bit(V, add)) ok = false; V = join_v(V, add); } } } }; pref[start] = weight; bool ok = true; dfs(start, 0, ok); if (!ok) continue; memcpy(dp[nt], dp[t], sizeof dp[t]); int i = id(V); if (vec == -1) { for (int j = 0; j < TOTAL; ++j) { add(dp[nt][tab[i][j]], dp[t][j]); } } else { for (int j = 0; j < TOTAL; ++j) { add(dp[nt][tab[i][j]], dp[t][j]); add(dp[nt][tab[i][j]], dp[t][j]); } int with = id(join_v(V, vec)); if (i != with) { V = subspaces[with]; for (int j = 0; j < TOTAL; ++j) { add(dp[nt][tab[with][j]], dp[t][j]); } } } swap(t, nt); } int ans = 0; for (int i = 0; i < TOTAL; ++i) add(ans, dp[t][i]); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; int toNumber(string s) { int Number; if (!(istringstream(s) >> Number)) Number = 0; return Number; } string toString(int number) { ostringstream ostr; ostr << number; return ostr.str(); } int main() { int n, m, k; while (cin >> n >> m >> k) { long long lo = 0; long long hi = m + 1; while (hi - lo > 1) { long long mi = (lo + hi) / 2; long long voy; if (k >= mi) { voy = (mi - 1) * mi / 2 + (k - mi); } else { voy = (mi - 1) * mi / 2 - (mi - k) * (mi - k + 1) / 2; } if (n - k + 1 >= mi) { voy += (mi + 1) * mi / 2 + (n - k + 1 - mi); } else { voy += (mi + 1) * mi / 2 - (mi - (n - k + 1) + 1) * (mi - (n - k + 1)) / 2; } if (voy <= m) { lo = mi; } else { hi = mi; } } cout << lo << endl; } }
|
#include <bits/stdc++.h> using namespace std; int A, B, q; long long l, t, m; bool check(long long len) { long long ind_left = l; long long ind_righ = ind_left + len - 1; long long num_left = A + (ind_left - 1) * B; long long num_righ = A + (ind_righ - 1) * B; long long need_time; if (len > m) need_time = ((num_left + num_righ) * len / 2 + m - 1) / m; else need_time = num_righ; return need_time <= t && num_righ <= t; } void work() { scanf( %d %d %d , &A, &B, &q); while (q--) { scanf( %lld %lld %lld , &l, &t, &m); long long lpt = 0, rpt = 1e6; while (lpt < rpt) { long long mid = (lpt + rpt + 1) >> 1; if (check(mid)) { lpt = mid; } else { rpt = mid - 1; } } if (lpt == 0) { puts( -1 ); } else { printf( %lld n , l + rpt - 1); } } } int main() { work(); return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: adc_data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> child; int n, k; scanf( %d %d , &n, &k); int *A = new int[k]; for (int i = 0; i < k; ++i) { scanf( %d , &A[i]); } for (int i = 0; i < n; ++i) { child.push_back(i + 1); } int count = 0; for (int i = 0; i < k; ++i) { count += A[i]; count = count % (n - i); printf( %d , child[count]); child.erase(child.begin() + count); if (count >= child.size()) count = 0; } return 0; }
|
//---------------------------------------------------------------------//
// Name: addrgen.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Generates addresses.
//---------------------------------------------------------------------//
module addrgen(
clk,
nrst,
start,
readout,
n,
wraddr,
wren,
rdaddr,
vexaddr
);
input clk;
input nrst;
input start;
input readout;
input [15:0]n;
output [9:0]wraddr;
output [9:0]rdaddr;
output [12:0]vexaddr;
output wren;
reg [15:0]counter1;
reg [15:0]counter2;
reg [15:0]counter3;
reg [15:0]counter4;
reg [15:0]timer1;
reg [15:0]timer2;
reg [15:0]timer3;
reg [29:0]t1_exp_dly;
reg [29:0]t2_exp_dly;
reg [29:0]start_dly;
wire t1_expire = timer1[15];
wire t2_expire = timer2[15];
wire t3_expire = timer3[15];
assign rdaddr = counter1[9:0];
assign vexaddr = counter3[12:0];
assign wraddr = counter4[9:0];
//---------------------------------------------------------------------//
// Timers
//---------------------------------------------------------------------//
// Timer T1
// - Loads 'n' on start.
// - Stops counting when it reaches -1.
// - Decrements on t2_expire;
always @(posedge clk)
if (~nrst) timer1 <= -1;
else if(start) timer1 <= {1'b0,n[14:0]};
else if(!t1_expire && t2_expire) timer1 <= timer1 - 1;
// Timer T2
// - Counts down from T1 divided by 4.
// - Resets when it hits -1.
// - Stops decrementing the initial input once t3 expires.
wire [15:0] t2_startval = {3'b0, n[15:2]} - 1;
wire [15:0] t1_minus = timer1 - 5;
always @(posedge clk)
if (~nrst) timer2 <= -1;
else if(start) timer2 <= t2_startval;
else if(!t1_expire && t2_expire && !t3_expire) timer2 <= {3'b0, t1_minus[15:2]};
else if(!t1_expire && t2_expire && t3_expire) timer2 <= 30;
else if(!t1_expire && !t2_expire) timer2 <= timer2 - 1;
// Timer T3
always @(posedge clk)
if(~nrst) timer3 <= -1;
else if(start) timer3 <= n-128; // For a 30 cycle pipeline.
else if(!t3_expire && t2_expire) timer3 <= timer3 - 1;
// Shift registers for delayed counting.
always@(posedge clk)
if (~nrst) t1_exp_dly <= 0;
else t1_exp_dly <= {t1_exp_dly[28:0], t1_expire};
always@(posedge clk)
if(~nrst) t2_exp_dly <= 0;
else t2_exp_dly <= {t2_exp_dly[28:0], t2_expire};
always@(posedge clk)
if(~nrst) start_dly <= 0;
else start_dly <= {start_dly[28:0], start};
wire sig_a = t1_exp_dly[24];
wire sig_b = t2_exp_dly[24];
wire sig_c = start_dly[24];
wire sig_d = t1_exp_dly[29];
wire sig_e = t2_exp_dly[29];
wire sig_f = start_dly[29];
assign wren = !sig_d;
//---------------------------------------------------------------------//
// Logic for generating rdaddr.
//---------------------------------------------------------------------//
// Counter C1
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter1 <= -1;
else if(start) counter1 <= 0;
else if(readout) counter1 <= 10'b1000000000;
else if(!t1_expire && t2_expire) counter1 <= 0;
else if(!t1_expire && !t2_expire) counter1 <= counter1 + 1;
//---------------------------------------------------------------------//
// Logic for generating vex_addr.
//---------------------------------------------------------------------//
// Counter C2
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t4 expires.
always @(posedge clk)
if(~nrst) counter2 <= -1;
else if(sig_c) counter2 <= 0;
else if(!sig_a && sig_b) counter2 <= counter2 + 1;
// Counter C3
// - Counts up from 0.
// - Resets at start.
// - Stops counting when t1 expires.
always @(posedge clk)
if(~nrst) counter3 <= -1;
else if(sig_c) counter3 <= 0;
else if(!sig_a && sig_b) counter3 <= counter2 + 1;
else if(!sig_a && !sig_b) counter3 <= counter3 + 8;
//---------------------------------------------------------------------//
// Logic for generating wraddr.
//---------------------------------------------------------------------//
// Counter C4
// - Counts up from 0.
// - Resets when t2 expires.
// - Stops when t1 expires.
always @(posedge clk)
if (~nrst) counter4 <= -1;
else if(sig_f) counter4 <= 0;
else if(!sig_d && sig_e) counter4 <= 0;
else if(!sig_d && !sig_e) counter4 <= counter4 + 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v; long long int arr[100001], operation[100001][3], kitnibaar1[100002], kitnibaar[100002], update1[100002], update[100002]; int main() { int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> arr[i]; } for (int i = 1; i <= m; i++) { cin >> operation[i][0]; cin >> operation[i][1]; cin >> operation[i][2]; } for (int i = 1; i <= k; i++) { int start, end; cin >> start >> end; kitnibaar1[start]++; kitnibaar1[end + 1]--; } long long int up = 0; for (int i = 1; i <= m; i++) { up += kitnibaar1[i]; kitnibaar[i] += up; } up = 0; for (int i = 1; i <= m; i++) { operation[i][2] *= kitnibaar[i]; update[operation[i][0]] += operation[i][2]; update[operation[i][1] + 1] -= operation[i][2]; } up = 0; for (int i = 1; i <= n; i++) { up += update[i]; arr[i] += up; cout << arr[i] << ; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
passed,
// Inputs
clk, fastclk, reset_l
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
input reset_l;
output passed;
// Combine passed signals from each sub signal
// verilator lint_off MULTIDRIVEN
wire [20:0] passedv;
// verilator lint_on MULTIDRIVEN
wire passed = &passedv;
assign passedv[0] = 1'b1;
assign passedv[1] = 1'b1;
assign passedv[2] = 1'b1;
assign passedv[3] = 1'b1;
assign passedv[4] = 1'b1;
assign passedv[5] = 1'b1;
t_inst tinst
(.passed (passedv[6]),
/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk));
t_param tparam
(.passed (passedv[7]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[8] = 1'b1;
assign passedv[9] = 1'b1;
assign passedv[10] = 1'b1;
t_clk tclk
(.passed (passedv[11]),
/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.clk (clk),
.reset_l (reset_l));
assign passedv[12] = 1'b1;
assign passedv[13] = 1'b1;
t_chg tchg
(.passed (passedv[14]),
/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk));
assign passedv[15] = 1'b1;
assign passedv[16] = 1'b1;
assign passedv[17] = 1'b1;
assign passedv[18] = 1'b1;
assign passedv[19] = 1'b1;
t_netlist tnetlist
(.passed (passedv[20]),
.also_fastclk (fastclk),
/*AUTOINST*/
// Inputs
.fastclk (fastclk));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; vector<char> a(str.begin(), str.end()); cin >> str; vector<char> b(str.begin(), str.end()); int res = 0; for (int i = 0; i < a.size(); i++) { if (a[i] >= a ) a[i] += - a + A ; if (b[i] >= a ) b[i] += - a + A ; if (a[i] > b[i]) { res = 1; break; } else if (a[i] < b[i]) { res = -1; break; } } printf( %d n , res); }
|
#include <bits/stdc++.h> using namespace std; long long k, d, t, cnt = 0; bool f(double T) { long long interval = ((long long)ceil(k / (d * 1.0))) * d; long long no_of_interval = T / interval; double t_on = no_of_interval * k, t_off = (interval - k) * no_of_interval; double rem = T - no_of_interval * interval; if (rem <= (double)k) t_on += rem; else { t_on += k; t_off += rem - k; } return t_on + t_off / 2 >= t; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> k >> d >> t; double s = t, e = 2 * t, mid; while (cnt++ <= 10000) { mid = (s + e) / 2; if (f(mid)) e = mid; else s = mid; } cout << setprecision(20) << mid; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:51:00 02/21/2015
// Design Name: mfmDecode
// Module Name: C:/Users/ChrisP/Documents/RL02Controller/RL02Controller/mfmDecode_tb.v
// Project Name: RL02Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mfmDecode
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mfmDecode_tb;
// Inputs
reg clk;
reg rst;
reg mfmIn;
wire mfmEdge;
// Outputs
wire currentRealBit;
wire currentRealBitValid;
wire mfmSynced;
//Edge detector is required for this test
inputSync is (
.clk(clk),
.rst(rst),
.async_in(mfmIn),
.sync_out(mfmSynced)
);
edgeDetect edgey (
.clk(clk),
.rst(rst),
.data(mfmSynced),
.strobe(mfmEdge)
);
// Instantiate the Unit Under Test (UUT)
mfmDecode uut (
.clk(clk),
.rst(rst),
.mfmIn(mfmSynced),
.mfmEdge(mfmEdge),
.currentRealBit(currentRealBit),
.currentRealBitValid(currentRealBitValid)
);
initial begin
// Initialize Inputs
clk = 0;
mfmIn = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 1;
toggle_clk;
rst = 0;
mfmIn = 0;
toggle_clk;
repeat (46) begin
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
end
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
//INTENTIONAL ERROR!!!
//mfmIn=1;
//toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
mfmIn=1;
toggle_clk;
mfmIn=0;
toggle_clk;
// Add stimulus here
end
task toggle_clk;
begin
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
endtask
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_channel_gate.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Provides cross domain synchronization for the CHNL_RX*
// signals between the CHNL_CLK and CLK domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_channel_gate #(
parameter C_DATA_WIDTH = 9'd64
)
(
input RST,
input CLK,
input RX, // Channel read signal (CLK)
output RX_RECVD, // Channel read received signal (CLK)
output RX_ACK_RECVD, // Channel read acknowledgment received signal (CLK)
input RX_LAST, // Channel last read (CLK)
input [31:0] RX_LEN, // Channel read length (CLK)
input [30:0] RX_OFF, // Channel read offset (CLK)
output [31:0] RX_CONSUMED, // Channel words consumed (CLK)
input [C_DATA_WIDTH-1:0] RD_DATA, // FIFO read data (CHNL_CLK)
input RD_EMPTY, // FIFO is empty (CHNL_CLK)
output RD_EN, // FIFO read enable (CHNL_CLK)
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal (CHNL_CLK)
input CHNL_RX_ACK, // Channle read received signal (CHNL_CLK)
output CHNL_RX_LAST, // Channel last read (CHNL_CLK)
output [31:0] CHNL_RX_LEN, // Channel read length (CHNL_CLK)
output [30:0] CHNL_RX_OFF, // Channel read offset (CHNL_CLK)
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data (CHNL_CLK)
output CHNL_RX_DATA_VALID, // Channel read data valid (CHNL_CLK)
input CHNL_RX_DATA_REN // Channel read data has been recieved (CHNL_CLK)
);
reg rAckd=0, _rAckd=0;
reg rChnlRxAck=0, _rChnlRxAck=0;
reg [31:0] rConsumed=0, _rConsumed=0;
reg [31:0] rConsumedStable=0, _rConsumedStable=0;
reg [31:0] rConsumedSample=0, _rConsumedSample=0;
reg rCountRead=0, _rCountRead=0;
wire wCountRead;
wire wCountStable;
wire wDataRead = (CHNL_RX_DATA_REN & CHNL_RX_DATA_VALID);
assign RX_CONSUMED = rConsumedSample;
assign RD_EN = CHNL_RX_DATA_REN;
assign CHNL_RX_LAST = RX_LAST;
assign CHNL_RX_LEN = RX_LEN;
assign CHNL_RX_OFF = RX_OFF;
assign CHNL_RX_DATA = RD_DATA;
assign CHNL_RX_DATA_VALID = !RD_EMPTY;
// Buffer the input signals that come from outside the rx_port.
always @ (posedge CHNL_CLK) begin
rChnlRxAck <= #1 (RST ? 1'd0 : _rChnlRxAck);
end
always @ (*) begin
_rChnlRxAck = CHNL_RX_ACK;
end
// Signal receive into the channel domain.
cross_domain_signal rxSig (
.CLK_A(CLK),
.CLK_A_SEND(RX),
.CLK_A_RECV(RX_RECVD),
.CLK_B(CHNL_CLK),
.CLK_B_RECV(CHNL_RX),
.CLK_B_SEND(CHNL_RX)
);
// Signal acknowledgment of receive into the CLK domain.
syncff rxAckSig (.CLK(CLK), .IN_ASYNC(rAckd), .OUT_SYNC(RX_ACK_RECVD));
// Capture CHNL_RX_ACK and reset only after the CHNL_RX drops.
always @ (posedge CHNL_CLK) begin
rAckd <= #1 (RST ? 1'd0 : _rAckd);
end
always @ (*) begin
_rAckd = (CHNL_RX & (rAckd | rChnlRxAck));
end
// Count the words consumed by the channel and pass it into the CLK domain.
always @ (posedge CHNL_CLK) begin
rConsumed <= #1 _rConsumed;
rConsumedStable <= #1 _rConsumedStable;
rCountRead <= #1 (RST ? 1'd0 : _rCountRead);
end
always @ (*) begin
_rConsumed = (!CHNL_RX ? 0 : rConsumed + (wDataRead*(C_DATA_WIDTH/32)));
_rConsumedStable = (wCountRead | rCountRead ? rConsumedStable : rConsumed);
_rCountRead = !wCountRead;
end
always @ (posedge CLK) begin
rConsumedSample <= #1 _rConsumedSample;
end
always @ (*) begin
_rConsumedSample = (wCountStable ? rConsumedStable : rConsumedSample);
end
// Determine when it's safe to update the count in the CLK domain.
cross_domain_signal countSync (
.CLK_A(CHNL_CLK),
.CLK_A_SEND(rCountRead),
.CLK_A_RECV(wCountRead),
.CLK_B(CLK),
.CLK_B_RECV(wCountStable),
.CLK_B_SEND(wCountStable)
);
endmodule
|
/*
** Copyright (C) 2009 Onno Kortmann <>
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
**
*/
/* SPI slave Verilog example code. */
`timescale 1ns / 1ns
module test;
reg CLK;
wire nCS, SCK, MOSI;
wire MISO;
wire [7:0] pb;
wire [7:0] pc;
wire [7:0] pd;
assign MISO=pb[4];
assign MOSI=pb[3];
assign SCK=pb[5];
assign nCS=pb[2];
defparam avr.progfile="spi-waveforms.elf";
ATmega8 avr(CLK, pb, pc, pd);
initial begin
$avr_trace("spi-waveforms.trace");
$dumpfile("spi-waveforms.vcd");
$dumpvars(0, test);
# 100000 $finish;
end // initial begin
always begin
#100 CLK<=0;
#100 CLK<=1;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: result_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module result_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [33:0] data;
input rdreq;
input wrreq;
output [33:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire [33:0] sub_wire1;
wire [9:0] usedw = sub_wire0[9:0];
wire [33:0] q = sub_wire1[33:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.empty (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 34,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "34"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "34"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "34"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 34 0 INPUT NODEFVAL data[33..0]
// Retrieval info: USED_PORT: q 0 0 34 0 OUTPUT NODEFVAL q[33..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 34 0 data 0 0 34 0
// Retrieval info: CONNECT: q 0 0 34 0 @q 0 0 34 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL result_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_fib.list"
`include "top.v"
module top_test_fibonacci;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
wire uart_tx;
reg [WIDTH-1 : 0] i, j, k, l;
initial begin
j = 1;
k = 1;
l = 0;
for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
expected_output[i] = k;
l = k;
k = k + j;
j = l;
end
i = 0;
end
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
$dumpfile("top_test_fibonacci.vcd");
$dumpvars;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (i >= OUTPUT_CNT) begin
$display("Fibonacci test passed, computed results match the expected output!\n");
$finish;
end
if (serial_data != expected_output[i]) begin
$display("Fibonacci test failed!\n");
$display("Serial output:%d doesn't match expected_output[%d]:%d\n",
serial_data, i, expected_output[i]);
$finish;
end
i <= i + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 5; vector<long long> g[N]; map<long long, long long> cnt; long long n, c, a[N], pref[N]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> c; for (long long i = 1; i <= n; i++) { cin >> a[i]; cnt[a[i]]++; g[a[i]].push_back(i); pref[i] = pref[i - 1] + (a[i] == c); } long long ans = cnt[c]; for (long long i = 1; i < N; i++) { if (!g[i].size() || i == c) continue; long long prev = g[i][0]; long long cur = 0, max_so_far = 0; for (auto it : g[i]) { cur = cur + 1 - (pref[it] - pref[prev]); prev = it; if (cur <= 0) cur = 1; max_so_far = max(max_so_far, cur); } ans = max(ans, pref[n] + max_so_far); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void c_p_c() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int32_t main() { c_p_c(); long long t; cin >> t; while (t--) { long long n, r; cin >> n >> r; long long k = r; r = min(n - 1, r); long long ans = r * (r + 1) / 2; if (k > r) ans++; cout << ans << endl; } return 0; }
|
`default_nettype none
module async (
input wire clk,
input wire reset,
input wire [3:0] async_data,
output reg async_ack,
output reg [1:0] sync_data,
output reg sync_en
);
reg [3:0] async_data_d1, async_data_d2;
wire async_req_d0, async_sp_d0;
reg async_req_d1, async_sp_d1;
wire async_req_edge, async_sp_edge;
always @(posedge clk) begin
if (reset == 1'b1) begin
async_data_d1 <= 4'b0;
async_data_d2 <= 4'b0;
end else begin
async_data_d1 <= async_data;
async_data_d2 <= async_data_d1;
end
end
assign async_req_d0 = (async_data_d2[0] | async_data_d2[1]) & (async_data_d2[2] | async_data_d2[3]);
assign async_sp_d0 = ~(async_data_d2[0] | async_data_d2[1]) & ~(async_data_d2[2] | async_data_d2[3]);
always @(posedge clk) begin
if (reset == 1'b1) begin
async_req_d1 <= 1'b0;
async_sp_d1 <= 1'b0;
end else begin
async_req_d1 <= async_req_d0;
async_sp_d1 <= async_sp_d0;
end
end
assign async_req_edge = ~async_req_d1 & async_req_d0;
assign async_sp_edge = ~async_sp_d1 & async_sp_d0;
always @(posedge clk) begin
if (reset == 1'b1) begin
async_ack <= 1'b0;
sync_data <= 2'b0;
sync_en <= 1'b0;
end else begin
if (async_req_edge == 1'b1) begin
async_ack <= 1'b1;
sync_data <= {async_data_d2[3], async_data_d2[1]};
sync_en <= 1'b1;
end else if (async_sp_edge == 1'b1) begin
async_ack <= 1'b0;
sync_data <= 2'b0;
sync_en <= 1'b0;
end else begin
sync_en <= 1'b0;
end
end
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int c[5555], ans[5555]; int main() { int n; cin >> n; int a[n + 1]; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { memset(c, 0, sizeof(c)); int bc = 0, bt = -1; for (int j = i; j <= n; j++) { int s = ++c[a[j]]; if (s > bc || (s == bc && a[j] < bt)) bc = s, bt = a[j]; ++ans[bt]; } } for (int i = 1; i <= n; i++) cout << ans[i] << ; }
|
#include <bits/stdc++.h> long long MOD = 1e9 + 7; using namespace std; int main() { long long n, t; cin >> n >> t; long long a[200010], x[200010], b[200010]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { cin >> x[i]; x[i]--; if ((i > 0 && x[i] < x[i - 1]) || x[i] < i) { cout << No ; return 0; } } int c[200010] = {}; for (int i = 0; i < n; i++) { long long temp = x[i]; c[x[i]] = 1; if (temp == i) { if (i > 0) b[i] = max(a[i] + t, b[i - 1] + 1); else b[i] = a[i] + t; if (i < n - 1 && b[i] >= a[i + 1] + t) { cout << No ; return 0; } } else { if (i > 0) b[i] = max(a[i + 1] + t, b[i - 1] + 1); else b[i] = a[i + 1] + t; } if (i < n - 1 && c[i] && b[i] >= a[i + 1] + t) { cout << No ; return 0; } } cout << Yes << endl; for (int i = 0; i < n; i++) { printf( %lld , b[i]); } return 0; }
|
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