text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; void solve(istream& in, ostream& out) { int n; in >> n; int res = n % 2 ? 0 : 1LL << (n / 2); out << res << endl; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); std::istream& in(std::cin); std::ostream& out(std::cout); solve(in, out); }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "DE0_NANO_SOC_QSYS_onchip_memory2.hex";
output [ 31: 0] readdata;
input [ 15: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 40000,
the_altsyncram.numwords_a = 40000,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; long long num_to_sig(long long x) { vector<int> v; while (x > 0) { v.push_back((x % 10) % 2); x /= 10; } int n = v.size(); long long ret = 0; for (int i = n - 1; i >= 0; i--) { ret *= 10; ret += v[i]; } return ret; } int main() { int Q; scanf( %d , &Q); map<long long, int> cnt; while (Q--) { char c; scanf( %c , &c); long long x; if (c == + ) { scanf( %lld , &x); cnt[num_to_sig(x)]++; } else if (c == - ) { scanf( %lld , &x); cnt[num_to_sig(x)]--; } else { scanf( %lld , &x); printf( %d n , cnt[num_to_sig(x)]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long getint() { long long summ = 0, f = 1; char ch; for (ch = getchar(); !isdigit(ch) && ch != - ; ch = getchar()) ; if (ch == - ) { f = -1; ch = getchar(); } for (; isdigit(ch); ch = getchar()) summ = (summ << 3) + (summ << 1) + ch - 48; return summ * f; } long long n, m, a[200005], ans, k, s[200004]; priority_queue<long long> q; signed main() { cin >> n >> m; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = n; i; i--) { if (a[i] < 0) q.push(a[i]); else { while (!q.empty() && a[i] >= 0) { a[i] += q.top(); q.pop(); } if (a[i] < 0) q.push(a[i]); } } long long tot = 0; while (!q.empty()) { s[++tot] = q.top(); q.pop(); } for (long long i = 1; i <= tot; i++) { s[i] = -s[i] + s[i - 1]; } for (long long i = 1, x; i <= m; i++) { x = getint(); cout << tot + 1 - (upper_bound(s + 1, s + 1 + tot, x) - s) << endl; } return 0; }
|
/*********************************************************/
// MODULE: Synchronous FIFO
//
// FILE NAME: sfifo_rtl.v
// VERSION: 1.0
// DATE: January 1, 1999
// AUTHOR: Bob Zeidman, Zeidman Consulting
//
// CODE TYPE: Register Transfer Level
//
// DESCRIPTION: This module defines a Synchronous FIFO. The
// FIFO memory is implemented as a ring buffer. The read
// pointer points to the beginning of the buffer, while the
// write pointer points to the end of the buffer. Note that
// in this RTL version, the memory has one more location than
// the FIFO needs in order to calculate the FIFO count
// correctly.
//
/*********************************************************/
// DEFINES
`define FIFO_DEPTH 15 // Depth of FIFO (number of bytes)
`define FIFO_HALF 8 // Half depth of FIFO
// (this avoids rounding errors)
`define FIFO_BITS 4 // Number of bits required to
// represent the FIFO size
`define FIFO_WIDTH 8 // Width of FIFO data
// TOP MODULE
module bm_sfifo_rtl(
clock,
reset_n,
data_in,
read_n,
write_n,
data_out,
full,
empty,
half);
// INPUTS
input clock; // Clock input
input reset_n; // Active low reset
input [`FIFO_WIDTH-1:0] data_in; // Data input to FIFO
input read_n; // Read FIFO (active low)
input write_n; // Write FIFO (active low)
// OUTPUTS
output [`FIFO_WIDTH-1:0] data_out; // FIFO output data
output full; // FIFO is full
output empty; // FIFO is empty
output half; // FIFO is half full
// or more
// INOUTS
// SIGNAL DECLARATIONS
wire clock;
wire reset_n;
wire [`FIFO_WIDTH-1:0] data_in;
wire read_n;
wire write_n;
reg [`FIFO_WIDTH-1:0] data_out;
wire full;
wire empty;
wire half;
// The FIFO memory.
reg [`FIFO_WIDTH-1:0] fifo_mem[`FIFO_DEPTH-1:0];
// How many locations in the FIFO
// are occupied?
reg [`FIFO_BITS-1:0] counter;
// FIFO read pointer points to
// the location in the FIFO to
// read from next
reg [`FIFO_BITS-1:0] rd_pointer;
// FIFO write pointer points to
// the location in the FIFO to
// write to next
reg [`FIFO_BITS-1:0] wr_pointer;
// PARAMETERS
// ASSIGN STATEMENTS
assign full = (counter == `FIFO_DEPTH) ? 1'b1 : 1'b0;
assign empty = (counter == 0) ? 1'b1 : 1'b0;
assign half = (counter >= `FIFO_HALF) ? 1'b1 : 1'b0;
// MAIN CODE
// This block contains all devices affected by the clock
// and reset inputs
always @(posedge clock) begin
if (~reset_n) begin
// Reset the FIFO pointer
rd_pointer <= 0;
wr_pointer <= 0;
counter <= 0;
end
else begin
// If we are doing a simultaneous read and write,
// there is no change to the counter
if (~read_n && write_n) begin
// Decrement the FIFO counter
counter <= counter - 1;
end
else if (~write_n && read_n) begin
// Increment the FIFO counter
counter <= counter + 1;
end
if (~read_n) begin
// Increment the read pointer
// Check if the read pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (rd_pointer == `FIFO_DEPTH-1)
rd_pointer <= 0;
else
rd_pointer <= rd_pointer + 1;
end
if (~write_n) begin
// Increment the write pointer
// Check if the write pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (wr_pointer == `FIFO_DEPTH-1)
wr_pointer <= 0;
else
wr_pointer <= wr_pointer + 1;
end
end
end
// This block contains all devices affected by the clock
// but not reset
always @(posedge clock) begin
if (~read_n) begin
// Output the data
data_out <= fifo_mem[rd_pointer];
end
if (~write_n) begin
// Store the data
fifo_mem[wr_pointer] <= data_in;
end
end
endmodule // Sfifo
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module CHOPLIFTER (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("CHOPLIFTER.mif"),
.C_INIT_FILE("CHOPLIFTER.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[105][105], s[105], res[105], letter, letter2, help[105]; int i, j, k, N, lens, lena[105]; int main() { scanf( %d , &N); gets(a[103]); for (i = 0; i < N; i++) { gets(a[i]); lena[i] = strlen(a[i]); for (j = 0; j < lena[i]; j++) if (a[i][j] >= a && a[i][j] <= z ) a[i][j] -= 32; } gets(s); lens = strlen(s); for (i = 0; i < lens; i++) { if (s[i] >= a && s[i] <= z ) help[i] = s[i] - 32; else help[i] = s[i]; } scanf( %c , &letter); if (letter >= A && letter <= Z ) letter2 = letter + 32; else letter2 = letter - 32; if (letter < letter2) swap(letter, letter2); for (i = 0; i < lens; i++) { for (j = 0; j < N; j++) { if (memcmp(help + i, a[j], lena[j]) == 0) { for (k = i; k < i + lena[j]; k++) { if (s[k] != letter && s[k] != letter2) { if (s[k] >= a && s[k] <= z ) res[k] = letter; else res[k] = letter2; } else { if (s[k] >= a && s[k] <= z ) res[k] = letter == a ? b : a ; else res[k] = letter2 == A ? B : A ; } } } } } for (i = 0; i < lens; i++) if (res[i] == 0) res[i] = s[i]; puts(res); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize ( O3 ) #pragma GCC optimize ( Ofast ) using namespace std; #define int int64_t #define SQ(a) (a)*(a) const int INF = 1e15; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<vector<pair<int, int>>> g(n); for (int i = 0, a, b, c; i < m; i++) { cin >> a >> b >> c; a--, b--; g[a].push_back({b, c}); g[b].push_back({a, c}); } vector<int> deven(n, INF); vector<vector<int>> dodd(51, vector<int> (n, INF)); deven[0] = 0; priority_queue<array<int, 3>> Q; // {dist, v, (-1 OR w_last)} Q.push({0, 0, -1}); vector<vector<bool>> vis(52, vector<bool> (n)); while (!Q.empty()) { int d = -Q.top()[0]; int v = Q.top()[1]; int lw= Q.top()[2]; Q.pop(); if (vis[lw + 1][v]) continue; vis[lw + 1][v] = true; if (lw == -1) { // even steps for (auto [u, w] : g[v]) { if (dodd[w][u] > d) { dodd[w][u] = d; Q.push({-d, u, w}); } } } else { for (auto [u, w] : g[v]) { if (deven[u] > d + SQ(lw + w)) { deven[u] = d + SQ(lw + w); Q.push({-deven[u], u, -1}); } } } } for (int i = 0; i < n; i++) cout << (deven[i] == INF ? -1 : deven[i]) << ; cout << n ; }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n; cin >> n; vector<long long> apr(n + 1), arr(n); long long now = 1, next = 2; for (long long i = 0; i < n - 1; i++, next++) { long long a = 0, b = 0; cout << ? << now << << next << n ; cout.flush(); cin >> a; cout << ? << next << << now << n ; cout.flush(); cin >> b; if (a > b) { arr[now - 1] = a; apr[a] = 1; now = next; } else { arr[next - 1] = b; apr[b] = 1; } } for (long long i = 1; i <= n; i++) { if (apr[i] == false) { arr[now - 1] = i; break; } } cout << ! ; for (long long i = 0; i < n; i++) { cout << arr[i] << ; } cout << n ; cout.flush(); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e3 + 7; const int mod = 998244353; int col[maxn]; namespace DSU { int far[maxn]; void init() { for (int i = 0; i < maxn; i++) far[i] = i; } int Find(int x) { return x == far[x] ? x : far[x] = Find(far[x]); } void Union(int x, int y) { x = Find(x), y = Find(y); if (x < y) swap(x, y); far[y] = x; } }; // namespace DSU string s; int var, w, b; bool isp[maxn]; vector<int> G[maxn]; bool dfs(int u) { for (auto &v : G[u]) { if (col[v] == -1) { col[v] = col[u] ^ 1; if (!dfs(v)) return false; } else { if (col[v] == col[u]) return false; } } return true; } long long solve(int len) { for (int i = 0; i <= b; i++) G[i].clear(); memset(isp, 0, sizeof(isp)); DSU::init(); for (int i = 0; i < s.length() / 2; i++) DSU::Union(i, s.length() - i - 1); for (int i = 0; i < len / 2; i++) DSU::Union(var + i, var + len - 1 - i); isp[w] = isp[b] = 1; DSU::Union(var + len - 1, b); for (int i = 0; i < s.length(); i++) isp[i] = 1; for (int i = 0; i < len; i++) isp[i + var] = 1; for (int i = 0; i < len; i++) if (s[i] == 0 ) DSU::Union(i, var + i); for (int i = len; i < s.length(); i++) { if (s[i] == 1 ) DSU::Union(i, b); else if (s[i] == 0 ) DSU::Union(i, w); } DSU::Union(s.length() - 1, b); if (DSU::Find(b) == DSU::Find(w)) return 0; for (int i = 0; i < len; i++) { if (s[i] == 1 ) { G[DSU::Find(i)].push_back(DSU::Find(var + i)); G[DSU::Find(var + i)].push_back(DSU::Find(i)); } } G[DSU::Find(w)].push_back(DSU::Find(b)); G[DSU::Find(b)].push_back(DSU::Find(w)); long long ret = 1; memset(col, -1, sizeof(col)); for (int i = b; i >= 0; i--) { if (isp[i]) { int cur = DSU::Find(i); if (col[cur] == -1) { if (cur == b) col[cur] = 1; else col[cur] = 0; if (!dfs(cur)) return 0; else { if (cur != b && cur != w) ret = ret * 2 % mod; } } } } return ret; } int main() { cin >> s; var = s.length(); reverse(s.begin(), s.end()); w = var * 2 + 1, b = var * 2 + 2; long long ans = 0; for (int i = 1; i < s.length(); i++) ans = (ans + solve(i)) % mod; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; constexpr long long INF = numeric_limits<long long>::max() / 4; constexpr long long n_max = 2e5 + 10; template <typename A, typename B> string to_string(pair<A, B> p); string to_string(const string &s) { return + s + ; } string to_string(const char c) { return to_string((string)&c); } string to_string(bool b) { return (b ? true : false ); } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) res += static_cast<char>( 0 + v[i]); return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) res += , ; first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <class T> bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } signed main() { cin.tie(nullptr); ios::sync_with_stdio(false); long long t; cin >> t; for (long long _ = 0; _ < (long long)(t); _++) { long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < (long long)(n); i++) cin >> a[i]; vector<long long> dp(n + 1); for (long long i = 1; i < (long long)(n) + 1; i++) { dp[i]++; for (long long j = i * 2; j <= n; j += i) { if (a[j - 1] > a[i - 1]) chmax(dp[j], dp[i]); } } long long ans = 0; for (long long i = 0; i < (long long)(n + 1); i++) chmax(ans, dp[i]); cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans = 0, sch = 0, nm = -100000, pnm = 10000; vector<int> v; scanf( %d , &n); for (int i = 0; i < n; i++) { int t; scanf( %d , &t); if ((t % 2 == 1) && (t > 0)) { pnm = ((pnm) < (t)) ? (pnm) : (t); ans += t; } else if (t % 2 == -1) { nm = ((nm) > (t)) ? (nm) : (t); } else if (t > 0) { sch += t; } } if (ans == 0) ans += nm; ans += sch; if (ans % 2 == 0) ans = ((ans - pnm) > (ans + nm)) ? (ans - pnm) : (ans + nm); printf( %d , ans); return 0; }
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
This module infers the RAM block necessary to hold the neural network
weights between the nodes in the current layer and the nodes in the previous
layer.
The DEPTH of the RAM is constrained due to limited FPGA memory resources.
To get around holding only portions of the weights at a time, the RAM will
reload itself with new weights from the SDRAM every time it cycles through
its entire memory range.
If all the weights can be held on the FPGA, the RAM is only loaded
once.
*/
`include "DeepGATE_include.v"
module weight_RAM #(
parameter SIZE = 4,
parameter MAX_DEPTH = SIZE,
parameter DIVIDER = 1,
parameter WEIGHT_WIDTH = 3,
parameter NUM_BYTES = $rtoi($ceil($itor(SIZE*WEIGHT_WIDTH)/8))
)(
input clk_i,
input rd_i,
input wr_i,
input [7:0] data_i,
output reg pipeline_lock_o = 1'b1,
output reg [SIZE*WEIGHT_WIDTH - 1'b1:0] data_o = 0
);
localparam DEPTH = MAX_DEPTH/DIVIDER;
localparam LAST_BIT_INDEX = (SIZE*WEIGHT_WIDTH) % 8 == 0 ? 7 : ((SIZE*WEIGHT_WIDTH) % 8) - 1;
reg [DEPTH == 1 ? 0 : $clog2(DEPTH - 1'b1) - 1'b1 : 0] rd_addr = 0;
reg [DEPTH == 1 ? 0 : $clog2(DEPTH - 1'b1) - 1'b1 : 0] wr_addr = 0;
reg [SIZE*WEIGHT_WIDTH - 1'b1 : 0] buffer = 0;
reg [SIZE*WEIGHT_WIDTH - 1'b1 : 0] RAM [DEPTH - 1'b1:0];
reg [NUM_BYTES == 1 ? 0 : $clog2(NUM_BYTES - 1) : 0] wr_cnt = 0;
reg wr_flag = 0;
initial begin
/*
case(FILE_INDEX) //because Verilog sucks.
0: $readmemb("C:/Users/cedric/Documents/Visual Studio 2015/Projects/FeedForwardNN/FeedForwardNN/weights12.txt", RAM);
1: $readmemb("C:/Users/cedric/Documents/Visual Studio 2015/Projects/FeedForwardNN/FeedForwardNN/weights23.txt", RAM);
2: $readmemb("C:/Users/cedric/Documents/UCF/C Programs/DeepGATE/weights2.txt", RAM);
3: $readmemb("C:/Users/cedric/Documents/UCF/C Programs/DeepGATE/weights3.txt", RAM);
4: $readmemb("C:/Users/cedric/Documents/UCF/C Programs/DeepGATE/weights4.txt", RAM);
5: $readmemb("C:/Users/cedric/Documents/UCF/C Programs/DeepGATE/weights5.txt", RAM);
6: $readmemb("C:/Users/cedric/Documents/UCF/C Programs/DeepGATE/weights6.txt", RAM);
7: $readmemb("C:/Users/cedric/Documents/UCF/C Programs/DeepGATE/weights7.txt", RAM);
endcase
*/
end
always@(posedge clk_i) begin
wr_flag <= 0;
if(rd_i) begin
rd_addr <= rd_addr + 1'b1;
data_o <= RAM[rd_addr];
if(rd_addr == DEPTH - 1'b1) begin
rd_addr <= 0;
if(DIVIDER != 1)
pipeline_lock_o <= 1;
end
end
if(wr_i) begin
wr_cnt <= wr_cnt + 1'b1;
if(wr_cnt == NUM_BYTES - 1) begin
wr_cnt <= 0;
wr_flag <= 1;
if(NUM_BYTES != 1)
buffer <= {data_i[LAST_BIT_INDEX : 0], buffer[SIZE*WEIGHT_WIDTH - 1'b1: 8 - (7 - LAST_BIT_INDEX)]};
else
buffer <= data_i[LAST_BIT_INDEX: 0];
end
else begin
if(NUM_BYTES != 1)
buffer <= {data_i, buffer[SIZE*WEIGHT_WIDTH - 1'b1: 8]};
end
end
if(wr_flag) begin
wr_addr <= wr_addr + 1'b1;
RAM[wr_addr] <= buffer;
if(wr_addr == DEPTH - 1'b1) begin
wr_addr <= 0;
pipeline_lock_o <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mxn = 1e6 + 7; const long long mod = 1e9 + 7; const long long inf = 1e18 + 7; int dx[] = {+1, -1, 0, 0}; int dy[] = {0, 0, -1, +1}; pair<int, int> p[mxn]; map<long long, long long> f, s; int n; int a[mxn], ls[mxn]; long long ans; void upd1(int x, int val) { while (x <= (int)1e8) { f[x] += val; x = (x | (x + 1)); } } void upd2(int x) { while (x <= (int)1e8) { s[x]++; x = (x | (x + 1)); } } long long sum1(int x) { long long res = 0; while (x > 0) { res += f[x]; x = (x & (x + 1)) - 1; } return res; } int sum2(int x) { int res = 0; while (x > 0) { res += s[x]; x = (x & (x + 1)) - 1; } return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> p[i].first; } for (int i = 1; i <= n; i++) { cin >> p[i].second; ls[i] = p[i].second; } sort(p + 1, p + n + 1); sort(ls + 1, ls + n + 1); for (int i = 1; i <= n; i++) { p[i].second = lower_bound(ls + 1, ls + n + 1, p[i].second) - ls; } for (int i = 1; i <= n; i++) { ans += (1LL * p[i].first * sum2(p[i].second)) - sum1(p[i].second); upd1(p[i].second, p[i].first); upd2(p[i].second); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, x, m, tmp, ans, sum, t; int a[N], b[N], h[N]; string s, p; map<string, int> pol; vector<int> nei[N]; bool mark[N]; void read_input() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] > 1 && tmp == 0) tmp = i; sum += a[i]; } if (sum == n) { cout << (n % 2 ? First n : Second n ); return; } cout << (tmp % 2 ? First n : Second n ); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> t; while (t--) { sum = 0; tmp = 0; read_input(); } return 0; }
|
`timescale 1ps/1ps
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80s (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
di_reg <= #1 0;
end
else
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= #1 ~ intcycle_n;
mreq_n <= #1 ~ intcycle_n;
iorq_n <= #1 intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= #1 1'b0;
`endif
end // if (mcycle[0])
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
endmodule // t80s
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 9; long long n, a, b, val[MAX], incc[MAX], decc[MAX]; vector<int> g[MAX]; void dfs(int v, int p) { for (auto u : g[v]) if (u != p) dfs(u, v), decc[v] = max(decc[v], decc[u]), incc[v] = max(incc[v], incc[u]); long long meg = val[v] + incc[v] - decc[v]; if (meg < 0) incc[v] += -meg; else decc[v] += meg; } int main() { cin >> n; for (int i = 0; i < n - 1; i++) cin >> a >> b, a--, b--, g[a].push_back(b), g[b].push_back(a); for (int i = 0; i < n; i++) cin >> val[i]; dfs(0, -1); cout << incc[0] + decc[0]; }
|
#include <bits/stdc++.h> using namespace std; int m, n, k; pair<long long, long long> ptsx[100005]; pair<long long, long long> ptsy[100005]; bool removed[100005]; long long get(int l, int r, int u, int d, int dep) { while (removed[ptsx[l].second]) l++; while (removed[ptsx[r].second]) r--; while (removed[ptsy[u].second]) u++; while (removed[ptsy[d].second]) d--; if (dep == k) { long long xd = ptsx[r].first - ptsx[l].first; long long yd = ptsy[d].first - ptsy[u].first; if (xd == 0) xd++; if (yd == 0) yd++; return ((xd + 1) / 2) * ((yd + 1) / 2); } long long ans = (1LL) << 62; removed[ptsx[l].second] = true; ans = min(ans, get(l + 1, r, u, d, dep + 1)); removed[ptsx[l].second] = false; removed[ptsx[r].second] = true; ans = min(ans, get(l, r - 1, u, d, dep + 1)); removed[ptsx[r].second] = false; removed[ptsy[u].second] = true; ans = min(ans, get(l, r, u + 1, d, dep + 1)); removed[ptsy[u].second] = false; removed[ptsy[d].second] = true; ans = min(ans, get(l, r, u, d - 1, dep + 1)); removed[ptsy[d].second] = false; return ans; } int main() { ios_base::sync_with_stdio(0); cout << fixed << setprecision(12); cin >> n >> k; for (int i = 0, _i = (n); i < _i; ++i) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; ptsx[i] = make_pair(x1 + x2, i); ptsy[i] = make_pair(y1 + y2, i); } sort(ptsx, ptsx + n); sort(ptsy, ptsy + n); cout << get(0, n - 1, 0, n - 1, 0) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_LP__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_SYMBOL_V
|
module rca(a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7);
input a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7;
output car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7;
assign s0=a0^b0^0;
assign car1=(a0&b0)|(0&(a0^b0));
assign s1=a1^b1^car1;
assign car2=(a1&b1)|(car1&(a1^b1));
assign s2=a2^b2^car2;
assign car3=(a2&b2)|(car2&(a2^b2));
assign s3=a3^b3^car3;
assign car4=(a3&b3)|(car3&(a3^b3));
assign s4=a4^b4^car4;
assign car5=(a4&b4)|(car4&(a4^b4));
assign s5=a5^b5^car5;
assign car6=(a5&b5)|(car5&(a5^b5));
assign s6=a6^b6^car6;
assign car7=(a6&b6)|(car6&(a6^b6));
assign s7=a7^b7^car7;
assign car8=(a7&b7)|(car7&(a7^b7));
endmodule
module rca1(a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7);
output reg a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7;
input car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7;
initial begin
$dumpfile("rca8.vcd");
$dumpvars(0,a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7);
a0=1'b0;
a1=1'b0;
a2=1'b0;
a3=1'b0;
a4=1'b0;
a5=1'b0;
a6=1'b0;
a7=1'b0;
b0=1'b0;
b1=1'b0;
b2=1'b0;
b3=1'b0;
b4=1'b0;
b5=1'b0;
b6=1'b0;
b7=1'b0;
$monitor($time,,,"addend=%b %b %b %b %b %b %b %b, augend=%b %b %b %b %b %b %b %b, sum=%b %b %b %b %b %b %b %b %b",b7,b6,b5,b4,b3,b2,b1,b0,a7,a6,a5,a4,a3,a2,a1,a0,car8,s7,s6,s5,s4,s3,s2,s1,s0);
#5 a7=1'b1;a6=1'b0;a5=1'b1;a4=1'b1;a3=1'b1;a2=1'b0;a1=1'b1;a0=1'b1;
b7=1'b0;b6=1'b0;b5=1'b1;b4=1'b1;b3=1'b0;b2=1'b0;b1=1'b1;b0=1'b1;
#5 a7=1'b0;a6=1'b1;a5=1'b1;a4=1'b1;a3=1'b0;a2=1'b1;a1=1'b1;a0=1'b1;
b7=1'b1;b6=1'b1;b5=1'b0;b4=1'b0;b3=1'b1;b2=1'b1;b1=1'b0;b0=1'b0;
#10 $finish;
end
endmodule
module wb6;
wire a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7;
rca obj(a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7);
rca1 obj1(a0,a1,a2,a3,a4,a5,a6,a7,b0,b1,b2,b3,b4,b5,b6,b7,car1,car2,car3,car4,car5,car6,car7,car8,s0,s1,s2,s3,s4,s5,s6,s7);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_2_V
`define SKY130_FD_SC_MS__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_2_V
|
// Copyright (c) 2015 The Connectal Project
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module PutInverter(CLK,
RST,
put,
EN_put,
RDY_put,
get,
EN_get,
RDY_get
);
parameter DATA_WIDTH = 1;
input CLK;
input RST;
output [DATA_WIDTH-1 : 0] get;
input [DATA_WIDTH-1 : 0] put;
input EN_get;
input EN_put;
output RDY_get;
output RDY_put;
// will this work?
assign get = put;
assign RDY_get = EN_put;
assign RDY_put = EN_get;
endmodule // PutInverter
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_barrier(clock, resetn, i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
i_datac, i_datac_valid, o_datac_stall, i_datad, i_datad_valid, o_datad_stall,
o_dataout, o_dataout_valid, i_dataout_stall, i_start, i_counter_value, i_settings);
parameter DATA_WIDTH = 1;
parameter CONFIG_WIDTH = 4;
parameter FIFO_DEPTH = 64;
parameter BARRIER_MAX_SIMULTANEOUS_WORKGROUPS = 4;
parameter BARRIER_WORKGROUP_SIZE_BITS = 10;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input [DATA_WIDTH-1:0] i_datac;
input [DATA_WIDTH-1:0] i_datad;
input i_dataa_valid, i_datab_valid, i_datac_valid, i_datad_valid;
output o_dataa_stall, o_datab_stall, o_datac_stall, o_datad_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
input i_start;
input [31:0] i_counter_value;
input [CONFIG_WIDTH-1:0] i_settings;
wire data_to_count_valid;
wire fifo_a_valid, fifo_b_valid, fifo_c_valid, fifo_d_valid;
wire is_fifo_a_valid, is_fifo_b_valid, is_fifo_c_valid, is_fifo_d_valid;
wire is_fifo_stalled;
vfabric_counter_fifo fifo_a( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_dataa_valid), .o_datain_stall(o_dataa_stall),
.o_dataout_valid(fifo_a_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_b( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datab_valid), .o_datain_stall(o_datab_stall),
.o_dataout_valid(fifo_b_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_c( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datac_valid), .o_datain_stall(o_datac_stall),
.o_dataout_valid(fifo_c_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_d( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datad_valid), .o_datain_stall(o_datad_stall),
.o_dataout_valid(fifo_d_valid), .i_dataout_stall(is_fifo_stalled));
assign is_fifo_a_valid = fifo_a_valid | ~i_settings[0];
assign is_fifo_b_valid = fifo_b_valid | ~i_settings[1];
assign is_fifo_c_valid = fifo_c_valid | ~i_settings[2];
assign is_fifo_d_valid = fifo_d_valid | ~i_settings[3];
assign is_fifo_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid
& is_fifo_d_valid);
assign data_to_count_valid = i_start &
is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid;
acl_barrier_simple barrier0(
.clock(clock),
.resetn(resetn),
.valid_entry(data_to_count_valid),
.data_entry(),
.stall_entry(1'b0),
.valid_exit(o_dataout_valid),
.data_exit(),
.stall_exit(i_dataout_stall),
.num_live_workitems(),
.workgroup_size(i_counter_value));
defparam barrier0.DATA_WIDTH = DATA_WIDTH;
defparam barrier0.MAX_SIMULTANEOUS_WORKGROUPS = BARRIER_MAX_SIMULTANEOUS_WORKGROUPS;
defparam barrier0.WORKGROUP_SIZE_BITS = BARRIER_WORKGROUP_SIZE_BITS;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[4005], t[4005], ax[4005]; int main() { scanf( %s%s , s, t); int n = strlen(s), m = strlen(t), ret = m; for (int i = n - 1; i >= 0; i--) s[i + m] = s[i], s[i] = 0; n += m; for (int i = 0; i < n; i++) { int ct = 0; for (int j = 0; j < m; j++) { if (i + j >= n || s[i + j] != t[j]) ct++; } ret = min(ret, ct); ct = 0; for (int j = 0; j < m; j++) { if (i - j < 0 || s[i - j] != t[m - 1 - j]) ct++; } ret = min(ret, ct); } printf( %d n , ret); return 0; }
|
/*
* Copyright (c) 2014, Aleksander Osman
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module simple_ram
#(parameter width = 1,
parameter widthad = 1
)
(
input clk,
input [widthad-1:0] wraddress,
input wren,
input [width-1:0] data,
input [widthad-1:0] rdaddress,
output reg [width-1:0] q
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren) mem[wraddress] <= data;
q <= mem[rdaddress];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[400500], b[400500], n, tot; long long read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int main() { n = read(); tot = 0; for (int i = 1; i <= n; i++) { int x = read(); if (x) a[++tot] = x; } tot = 0; for (int i = 1; i <= n; i++) { int x = read(); if (x) b[++tot] = x; } for (int i = n; i <= 2 * n - 2; i++) b[i] = b[i - (n - 1)]; n--; int loc = 0; for (int i = 1; i <= n; i++) if (a[1] == b[i]) loc = i; int flag = 0; for (int i = loc, j = 1; j <= n; i++, j++) if (b[i] != a[j]) { flag = 1; break; } if (!flag) puts( YES ); else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 5; int grid[maxn][maxn]; int main() { int n, ans = 0; scanf( %d , &n); for (int i = 0, x1, x2, y1, y2; i < n; i++) { scanf( %d%d%d%d , &x1, &y1, &x2, &y2); ans += (x2 - x1 + 1) * (y2 - y1 + 1); } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; long long a[500005]; long long add[500005]; int main() { int i, j, n, x, y, z, m; long long sum; scanf( %d , &n); sum = 0; a[0] = 0; m = 1; for (i = 0; i < n; i++) { scanf( %d , &x); if (x == 1) { scanf( %d%d , &y, &z); sum += y * z; add[y - 1] += z; printf( %lf n , sum * 1.0 / m); } if (x == 2) { scanf( %d , &y); a[m++] = y; add[m - 1] = 0; sum += y; printf( %lf n , sum * 1.0 / m); } if (x == 3) { sum -= a[m - 1]; sum -= add[m - 1]; a[m - 1] = 0; add[m - 2] += add[m - 1]; add[m - 1] = 0; m--; printf( %lf n , sum * 1.0 / m); } } return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) #pragma comment(linker, /STACK:336777216 ) using namespace std; int IT_MAX = 1 << 17; const long long MOD = 1000000009; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1); const double ERR = 1e-8; vector<pair<long long, long long> > Vu; int main() { int N, K, M, i, j; scanf( %d %d %d , &N, &K, &M); for (i = 1; i <= N; i++) { int t; scanf( %d , &t); if (!Vu.empty() && Vu.back().first == t) { Vu.back().second++; if (Vu.back().second == K) Vu.pop_back(); } else Vu.emplace_back(t, 1); } long long s = 0; for (auto it : Vu) s += it.second; if (M == 1 || s == 0) return !printf( %lld n , s); s *= M; int st = 0, en = (int)Vu.size() - 1; while (st < en) { if (Vu[st].first != Vu[en].first) return !printf( %lld n , s); if (Vu[st].second + Vu[en].second == K) { s -= (long long)(M - 1) * K; st++, en--; continue; } if (Vu[st].second + Vu[en].second > K) s -= (long long)(M - 1) * K; return !printf( %lld n , s); } long long x = Vu[st].second * M; if (x % K == 0) { return !printf( 0 n ); } else { return !printf( %lld n , s - (x / K) * K); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_BLACKBOX_V
`define SKY130_FD_SC_LS__DECAPHE_BLACKBOX_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphe ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_1_V
`define SKY130_FD_SC_HS__A21BOI_1_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long v1, v2, v3, vm; long long u1, u2, u3; cin >> v1 >> v2 >> v3 >> vm; for (u1 = v1; u1 <= 2 * v1; u1++) { for (u2 = v2; u2 <= 2 * v2; u2++) { for (u3 = v3; u3 <= 2 * v3; u3++) { if (vm <= u3 && vm <= u2 && vm <= u1 && 2 * vm >= u3 && 2 * vm < u2 && 2 * vm < u1 && u1 > u2 && u2 > u3 && u1 > u3) { cout << u1 << n << u2 << n << u3; return 0; } } } } cout << -1 ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_V
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; using ld = long double; template <class T> using Table = vector<vector<T>>; const ld eps = 1e-9; template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> v) { os << ( << v.first << , << v.second << ) ; return os; } template <class T> ostream &operator<<(ostream &os, const vector<T> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << ; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const vector<vector<T>> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << endl; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const vector<set<T>> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << endl; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const map<T, T> &v) { int i = 0; for (auto it : v) { if (i > 0) { os << ; } os << it.first << << it.second; i++; } return os; } using ll = long long; const int mod = 998244353; struct Mod { public: int num; Mod() : Mod(0) { ; } Mod(long long int n) : num((n % mod + mod) % mod) { static_assert(mod < INT_MAX / 2, mod is too big, please make num long long int from int ); } Mod(int n) : Mod(static_cast<long long int>(n)) { ; } operator int() { return num; } }; Mod operator+(const Mod a, const Mod b) { return Mod((a.num + b.num) % mod); } Mod operator+(const long long int a, const Mod b) { return Mod(a) + b; } Mod operator+(const Mod a, const long long int b) { return b + a; } Mod operator++(Mod &a) { return a + Mod(1); } Mod operator-(const Mod a, const Mod b) { return Mod((mod + a.num - b.num) % mod); } Mod operator-(const long long int a, const Mod b) { return Mod(a) - b; } Mod operator--(Mod &a) { return a - Mod(1); } Mod operator*(const Mod a, const Mod b) { return Mod(((long long)a.num * b.num) % mod); } Mod operator*(const long long int a, const Mod b) { return Mod(a) * b; } Mod operator*(const Mod a, const long long int b) { return Mod(b) * a; } Mod operator*(const Mod a, const int b) { return Mod(b) * a; } Mod operator+=(Mod &a, const Mod b) { return a = a + b; } Mod operator+=(long long int &a, const Mod b) { return a = a + b; } Mod operator-=(Mod &a, const Mod b) { return a = a - b; } Mod operator-=(long long int &a, const Mod b) { return a = a - b; } Mod operator*=(Mod &a, const Mod b) { return a = a * b; } Mod operator*=(long long int &a, const Mod b) { return a = a * b; } Mod operator*=(Mod &a, const long long int &b) { return a = a * b; } Mod operator^(const Mod a, const int n) { if (n == 0) return Mod(1); Mod res = (a * a) ^ (n / 2); if (n % 2) res = res * a; return res; } Mod mod_pow(const Mod a, const long long n) { if (n == 0) return Mod(1); Mod res = mod_pow((a * a), (n / 2)); if (n % 2) res = res * a; return res; } Mod inv(const Mod a) { return a ^ (mod - 2); } Mod operator/(const Mod a, const Mod b) { assert(b.num != 0); return a * inv(b); } Mod operator/(const long long int a, const Mod b) { return Mod(a) / b; } Mod operator/=(Mod &a, const Mod b) { return a = a / b; } Mod fact[1024000], factinv[1024000]; void init(const int amax = 1024000) { fact[0] = Mod(1); factinv[0] = 1; for (int i = 0; i < amax - 1; ++i) { fact[i + 1] = fact[i] * Mod(i + 1); factinv[i + 1] = factinv[i] / Mod(i + 1); } } Mod comb(const int a, const int b) { return fact[a] * factinv[b] * factinv[a - b]; } using Value = pair<Mod, Mod>; const Value ini = make_pair(Mod(1), Mod(0)); Value connect(Value al, const Value ar) { return make_pair(al.first * ar.first, al.second * ar.first + ar.second); } Value dat[800001]; struct segtree { int N; segtree() {} segtree(int n) { N = 1; while (N < n) N *= 2; for (int x = 0; x < N; ++x) { { dat[x + N - 1] = ini; } } for (int x = N - 2; x >= 0; --x) { dat[x] = connect(dat[x * 2 + 1], dat[x * 2 + 2]); } } void update(int k, const Value &a) { k += N - 1; dat[k] = a; while (k > 0) { k = (k - 1) >> 1; dat[k] = connect(dat[k * 2 + 1], dat[k * 2 + 2]); } } Value query(int a, int b) { return query(a, b, 0, 0, N); } Value query(int a, int b, int k, int l, int r) { if (r <= a or b <= l) return ini; if (a <= l and r <= b) return dat[k]; const int m = (l + r) / 2; return connect(query(a, b, k * 2 + 1, l, m), query(a, b, k * 2 + 2, m, r)); } }; pair<Mod, Mod> dp[2010][2010]; int flag[2010][2010]; string st; pair<Mod, Mod> solve(int l, int r) { if (flag[l][r]) { return dp[l][r]; } flag[l][r] = true; if (l == r) { return dp[l][r] = make_pair(Mod(st[l] == ? ? 2 : 1), Mod(0)); } else if (l - 1 == r) { return dp[l][r] = make_pair(Mod(1), Mod(0)); } if (st[l] == ( ) { if (st[r] == ( ) { dp[l][r] = solve(l, r - 1); } else if (st[r] == ? ) { auto ap = solve(l + 1, r - 1); auto bp = solve(l, r - 1); dp[l][r] = make_pair(ap.first + bp.first, ap.second + bp.second + ap.first); } else { auto ap = solve(l + 1, r - 1); dp[l][r] = make_pair(ap.first, ap.second + ap.first); } } else if (st[l] == ) ) { dp[l][r] = solve(l + 1, r); } else { if (st[r] == ( ) { dp[l][r] = solve(l, r - 1); } else if (st[r] == ? ) { auto ap = solve(l + 1, r - 1); auto bp = solve(l, r - 1); auto cp = solve(l + 1, r); auto ep = solve(l + 1, r - 1); ap.second += ap.first; dp[l][r].first += ap.first + bp.first + cp.first - ep.first; dp[l][r].second += ap.second + bp.second + cp.second - ep.second; } else { auto ap = solve(l + 1, r - 1); ap.second += ap.first; auto bp = solve(l + 1, r); dp[l][r] = make_pair(ap.first + bp.first, ap.second + bp.second); } } return dp[l][r]; } int main() { ios::sync_with_stdio(false); cin >> st; auto answer = solve(0, int(st.size()) - 1); cout << answer.second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; default_random_engine generator; uniform_int_distribution<int> distribution(1, INT_MAX); vector<vector<long long> > one(int sz) { vector<vector<long long> > ret; ret.resize(sz); for (int i = 0; i < ret.size(); i++) { ret[i].resize(sz); for (int j = 0; j < ret.size(); j++) { ret[i][j] = (i == j); } } return ret; } vector<vector<long long> > mult(vector<vector<long long> > a, vector<vector<long long> > b) { vector<vector<long long> > ret; ret.resize(a.size()); for (int i = 0; i < ret.size(); i++) { ret[i].resize(a.size()); for (int j = 0; j < ret.size(); j++) { ret[i][j] = 0; } } for (int k = 0; k < ret.size(); k++) { for (int i = 0; i < a.size(); i++) { for (int j = 0; j < b.size(); j++) { ret[i][j] = (ret[i][j] + a[i][k] * b[k][j]); ret[i][j] %= 998244353; } } } return ret; } vector<vector<long long> > pw(vector<vector<long long> > a, long long b) { if (b == 0) return one((int)a.size()); if (b % 2) return mult(a, pw(a, b - 1)); return pw(mult(a, a), b / 2); } long long my_rand(long long a = 0, long long b = INT_MAX) { return a + distribution(generator) % b; } inline int mul(int a, int b) { return int(a * 1ll * b % 998244353); } inline int norm(int a) { if (a >= 998244353) a -= 998244353; if (a < 0) a += 998244353; return a; } inline int binPow(int a, int k) { int ans = 1; while (k > 0) { if (k & 1) ans = mul(ans, a); a = mul(a, a); k >>= 1; } return ans; } inline int subtract(int a, int b) { return norm(a - b); } inline int inv(int a) { return binPow(a, 998244353 - 2); } long long ceil_int(long long a, long long b) { return a / b + (a % b != 0); } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } int main() { generator.seed(chrono::system_clock::now().time_since_epoch().count()); cin.sync_with_stdio(false); cin.tie(0); int x; cin >> x; int cnt = 0; vector<int> op; int ok = 0; do { int k = x; int pos = -1; int j = 0; while (k > 0) { if ((k & 1) == 0) { pos = j; } j++; k >>= 1; } if (pos == -1) break; else if (cnt % 2 == 0) op.push_back(pos + 1); if (cnt % 2 == 0) { x = x ^ ((1 << (pos + 1)) - 1); } else { x++; } cnt++; } while (1); cout << cnt << endl; for (int i = 0; i < op.size(); i++) { cout << op[i] << ; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Lookup Table Multiplexer with General Output
// /___/ /\ Filename : MUXF7.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXF7 (O, I0, I1, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, S;
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR3_PP_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
// Decoder for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: Decoder
// Module Name: Decoder
// File Name: Decoder.v
//
// Version: v1.0.0
//
// Description: General purpose decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module Decoder
#
(
parameter OutputWidth = 4
)
(
I,
O
);
input [$clog2(OutputWidth) - 1:0] I;
output [OutputWidth - 1:0] O;
reg [OutputWidth - 1:0] rO;
genvar c;
generate
for (c = 0; c < OutputWidth; c = c + 1)
begin: DecodeBits
always @ (*)
begin
if (I == c)
rO[c] <= 1'b1;
else
rO[c] <= 1'b0;
end
end
endgenerate
assign O = rO;
endmodule
|
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
// always be low.
assign pwr_hi = 1'b0;
assign pwr_lo = 1'b0;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1;
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
end
// Divide 13.56 MHz by 32 to produce the SSP_CLK
// The register is bigger to allow higher division factors of up to /128
reg [6:0] ssp_clk_divider;
always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
assign ssp_clk = ssp_clk_divider[4];
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
// this is arbitrary, because it's just a bitstream.
// One nasty issue, though: I can't make it work with both rx and tx at
// once. The phase wrt ssp_clk must be changed. TODO to find out why
// that is and make a better fix.
reg [2:0] ssp_frame_divider_to_arm;
always @(posedge ssp_clk)
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
reg [2:0] ssp_frame_divider_from_arm;
always @(negedge ssp_clk)
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
reg ssp_frame;
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
if(mod_type == 3'b000) // not modulating, so listening, to ARM
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
else
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
reg modulating_carrier;
always @(mod_type or ssp_clk or ssp_dout)
if(mod_type == 3'b000)
modulating_carrier <= 1'b0; // no modulation
else if(mod_type == 3'b001)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == 3'b010)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else if(mod_type == 3'b100)
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
else
modulating_carrier <= 1'b0; // yet unused
// This one is all LF, so doesn't matter
assign pwr_oe2 = modulating_carrier;
// Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_oe1 = modulating_carrier;
assign pwr_oe4 = modulating_carrier;
// This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0;
assign dbg = after_hysteresis;
//reg dbg;
//always @(ssp_dout)
// dbg <= ssp_dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; long long int x = a[0]; for (long long int i = n - 1; i > 0; i--) { a[i] -= a[i - 1]; if (a[i] < 0) x += a[i]; } if (x >= 0) cout << YES << endl; else { cout << NO << endl; } } }
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_ram_switch
*/
module test_axis_ram_switch_4x4_64_64;
// Parameters
parameter FIFO_DEPTH = 512;
parameter SPEEDUP = 0;
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT+1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
parameter RAM_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
wire [S_COUNT-1:0] status_overflow;
wire [S_COUNT-1:0] status_bad_frame;
wire [S_COUNT-1:0] status_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
status_overflow,
status_bad_frame,
status_good_frame
);
// dump file
$dumpfile("test_axis_ram_switch_4x4_64_64.lxt");
$dumpvars(0, test_axis_ram_switch_4x4_64_64);
end
axis_ram_switch #(
.FIFO_DEPTH(FIFO_DEPTH),
.SPEEDUP(SPEEDUP),
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_PP_SYMBOL_V
`define SKY130_FD_SC_LP__FAH_PP_SYMBOL_V
/**
* fah: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_PP_SYMBOL_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = (int)2E5 + 5; const long long mdls = (long long)1E9 + 7; vector<int> Adj[maxN]; vector<long long> suff[maxN], pref[maxN]; long long f[maxN], g[maxN], h[maxN]; int n; void DFS(int u) { f[u] = 1; for (int i = 0, sz = Adj[u].size(); i < sz; ++i) { int v = Adj[u][i]; DFS(v); f[u] = (f[u] * (f[v] + 1)) % mdls; } int sz = Adj[u].size(); suff[u].resize(sz); pref[u].resize(sz); long long temp = 1; for (int i = 0; i < sz; ++i) { temp = (temp * (f[Adj[u][i]] + 1)) % mdls; pref[u][i] = temp; } temp = 1; for (int i = sz - 1; i >= 0; --i) { temp = (temp * (f[Adj[u][i]] + 1)) % mdls; suff[u][i] = temp; } } void DFS2(int u) { for (int i = 0, sz = Adj[u].size(); i < sz; ++i) { int v = Adj[u][i]; h[v] = h[u]; if (i > 0) h[v] = (h[v] * pref[u][i - 1]) % mdls; if (i < sz - 1) h[v] = (h[v] * suff[u][i + 1]) % mdls; h[v] = (h[v] + 1) % mdls; g[v] = (f[v] * h[v]) % mdls; DFS2(v); } } int main() { scanf( %d , &n); for (int u = 1; u <= n; ++u) Adj[u].clear(); for (int v = 2; v <= n; ++v) { int u; scanf( %d , &u); Adj[u].push_back(v); } DFS(1); h[1] = 1; g[1] = f[1]; DFS2(1); for (int u = 1; u <= n; ++u) printf( %I64d , g[u]); printf( n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A211OI_FUNCTIONAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_FUNCTIONAL_PP_V
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
/*
* serial with inversion
* Berlekamp–Massey algorithm
*
* sigma_i^(r) = sigma_i^(r-1) + d_rp * beta_i^(r) (i = 1 to t-1)
* d_r = summation sigma_i^(r) * S_(2 * r - i + 1) from i = 0 to t
* d_rp = d_p^-1 * d_r
*
* combine above equations:
* d_r = summation (simga_i^(r-1) + d_rp * beta_i^(r)) * S_(2 * r - i + 1) from i = 0 to t
*/
module bch_sigma_bma_serial #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input clk,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
input ack_done,
output reg done = 0,
output ready,
output [`BCH_SIGMA_SZ(P)-1:0] sigma,
output reg [`BCH_ERR_SZ(P)-1:0] err_count = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
wire [M-1:0] d_r;
wire [M-1:0] d_rp_dual;
wire [T:0] cin;
wire [T:0] sigma_serial; /* 0 bits of each sigma */
wire [M-1:0] syn1 = syndromes[0+:M];
wire [T*M-1:0] _sigma;
wire [M-1:0] sigma_1;
/* because of inversion, sigma0 is always 1 */
assign sigma = {_sigma, {M-1{1'b0}}, 1'b1};
reg [(T+1)*M-1:0] beta = 0;
reg [(T-1)*M-1:0] sigma_last = 0; /* Last sigma values */
reg first_cycle = 0;
reg second_cycle = 0;
reg penult2_cycle = 0;
reg penult1_cycle = 0;
reg last_cycle = 0;
reg first_calc = 0; /* bch_n == 0 */
reg final_calc = 0; /* bch_n == T - 1 */
reg counting = 0;
reg busy = 0;
/* beta(1)(x) = syn1 ? x^2 : x^3 */
wire [M*4-1:0] beta0; /* Initial beta */
assign beta0 = {{{M-1{1'b0}}, !syn1}, {{M-1{1'b0}}, |syn1}, {(M*2){1'b0}}};
/* d_r(0) = 1 + S_1 * x */
wire [(T+1)*M-1:0] d_r0; /* Initial dr */
assign d_r0 = {syn1, {(M-1){1'b0}}, 1'b1};
wire [`BCH_ERR_SZ(P)-1:0] bch_n;
counter #(T+1) u_bch_n_counter(
.clk(clk),
.reset(start),
.ce(last_cycle),
.count(bch_n)
);
wire [log2(M-4)-1:0] count;
counter #(M-4) u_counter(
.clk(clk),
.reset(second_cycle),
.ce(counting),
.count(count)
);
wire [(2*T-1)*M-1:0] syn_shuffled;
bch_syndrome_shuffle #(P) u_bch_syndrome_shuffle(
.clk(clk),
.start(start),
.ce(last_cycle),
.syndromes(syndromes),
.syn_shuffled(syn_shuffled)
);
reg d_r_nonzero = 0;
wire bsel;
assign bsel = d_r_nonzero && bch_n >= err_count;
reg bsel_last = 0;
assign ready = !busy && (!done || ack_done);
always @(posedge clk) begin
if (start)
busy <= #TCQ 1;
else if (penult2_cycle && final_calc)
busy <= #TCQ 0;
if (penult2_cycle && final_calc)
done <= #TCQ 1;
else if (ack_done)
done <= #TCQ 0;
if (last_cycle || start)
final_calc <= #TCQ T == 2 ? first_calc : (bch_n == T - 2);
if (start)
first_calc <= #TCQ 1;
else if (last_cycle)
first_calc <= #TCQ 0;
if (start) begin
beta <= #TCQ beta0;
sigma_last <= #TCQ beta0[2*M+:2*M]; /* beta(1) */
err_count <= #TCQ {{`BCH_ERR_SZ(P)-1{1'b0}}, |syn1};
bsel_last <= #TCQ 1'b1;
end else if (first_cycle) begin
if (bsel)
err_count <= #TCQ 2 * bch_n - err_count + 1;
bsel_last <= #TCQ bsel;
end else if (last_cycle) begin
d_r_nonzero <= #TCQ |d_r;
sigma_last <= #TCQ sigma[0+:(T-1)*M];
/* b^(r+1)(x) = x^2 * (bsel ? sigmal^(r-1)(x) : b_(r)(x)) */
beta[2*M+:(T-1)*M] <= #TCQ bsel_last ?
sigma_last[0*M+:(T-1)*M] :
beta[0*M+:(T-1)*M];
end
penult2_cycle <= #TCQ counting && count == M - 4;
penult1_cycle <= #TCQ penult2_cycle && !final_calc;
last_cycle <= #TCQ penult1_cycle;
first_cycle <= #TCQ last_cycle;
second_cycle <= #TCQ first_cycle || start;
if (second_cycle)
counting <= #TCQ 1;
else if (count == M - 4)
counting <= #TCQ 0;
end
wire [M-1:0] d_p0 = syn1 ? syn1 : 1;
/* d_rp = d_p^-1 * d_r */
finite_divider #(M) u_dinv(
.clk(clk),
.start(start || (first_cycle && bsel && !final_calc)),
.busy(),
.standard_numer(d_r),
/* d_p = S_1 ? S_1 : 1 */
.standard_denom(start ? d_p0 : d_r), /* syn1 is d_p initial value */
.dual_out(d_rp_dual)
);
/* mbN SDBM d_rp * beta_i(r) */
serial_mixed_multiplier_dss #(M, T + 1) u_serial_mixed_multiplier(
.clk(clk),
.start(last_cycle),
.dual_in(d_rp_dual),
.standard_in(beta),
.standard_out(cin)
);
/* Add Beta * drp to sigma (Summation) */
/* sigma_i^(r-1) + d_rp * beta_i^(r) */
wire [T:0] _cin = first_calc ? {T+1{1'b0}} : cin;
finite_serial_adder #(M) u_cN [T:0] (
.clk(clk),
.start(start),
.ce(!last_cycle && !penult1_cycle),
.parallel_in(d_r0),
.serial_in(_cin), /* First time through, we just shift out d_r0 */
.parallel_out({_sigma, sigma_1}),
.serial_out(sigma_serial)
);
/* d_r = summation (sigma_i^(r-1) + d_rp * beta_i^(r)) * S_(2 * r - i + 1) from i = 0 to t */
serial_standard_multiplier #(M, T+1) msm_serial_standard_multiplier(
.clk(clk),
.reset(start || first_cycle),
.ce(!last_cycle),
.parallel_in(syn_shuffled[0+:M*(T+1)]),
.serial_in(sigma_serial),
.out(d_r)
);
endmodule
|
// 3rd party code: from Swapforth [1]
//
// Copyright (c) 2015 James Bowman
//
// [1] https://github.com/jamesbowman/swapforth
//
/*
Copyright (c) 2015, James Bowman
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of swapforth nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`define CLKFREQ 25000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
module inpin(
input clk,
input pin,
output rd);
SB_IO #(.PIN_TYPE(6'b0000_00)) _io (
.PACKAGE_PIN(pin),
.INPUT_CLK(clk),
.D_IN_0(rd));
endmodule
module outpin(
input clk,
output pin,
input we,
input wd,
output rd);
SB_IO #(.PIN_TYPE(6'b0101_01)) _io (
.PACKAGE_PIN(pin),
.CLOCK_ENABLE(we),
.OUTPUT_CLK(clk),
.D_OUT_0(wd),
.D_IN_0(rd));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long l, r; cin >> l >> r; long long x = r, y = 0; while (x > 0) { ++y; x /= 10; } x = 5; long long k = y; for (int i = 0; i < k - 1; ++i) { x *= 10; } if (r < x) x = r; else if (l > x) x = l; k = x; vector<long long> ans; while (k > 0) { ans.push_back(k % 10); k /= 10; } reverse(ans.begin(), ans.end()); y = 0; for (auto& i : ans) { y *= 10; y += 9 - i; } cout << x * y; return 0; }
|
#include <bits/stdc++.h> using namespace std; string inp[100005]; int num[100005]; int tl; int ch[1200005][27]; int fail[1200005], len[1200005], elen[1200005]; long long cost[1200005]; int rt = 1, tot = 1, last = 1; void add(int x, int c, int _elen) { int p = last; int np = ++tot; len[np] = len[p] + 1; cost[np] = c; elen[np] = _elen; last = np; while (p && !ch[p][x]) { ch[p][x] = np; p = fail[p]; } if (!p) { fail[np] = rt; } else { int q = ch[p][x]; if (len[q] == len[p] + 1) { fail[np] = q; } else { int nq = ++tot; memcpy(ch[nq], ch[q], sizeof(ch[q])); len[nq] = len[p] + 1; fail[nq] = fail[q]; fail[np] = fail[q] = nq; while (p && ch[p][x] == q) { ch[p][x] = nq; p = fail[p]; } } } } int freq[600005], tpsort[1200005]; void TopoSort() { for (int i = (1); i <= (tot); i += (1)) freq[len[i]]++; for (int i = (1); i <= (tl); i += (1)) freq[i] += freq[i - 1]; for (int i = (tot); i >= (1); i -= (1)) tpsort[--freq[len[i]]] = i; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = (1); i <= (n); i += (1)) cin >> inp[i]; for (int i = (1); i <= (n); i += (1)) cin >> num[i]; for (int i = (0); i <= (1200005 - 1); i += (1)) elen[i] = 1000000000; tl = 0; for (int i = (1); i <= (n); i += (1)) { int t = inp[i].length(); for (int j = (0); j <= (t - 1); j += (1)) { add(inp[i][j] - a , num[i], j + 1); } add(26, 0, 0); tl += t + 1; } TopoSort(); long long mx = 0; for (int i = (tot); i >= (1); i -= (1)) { int u = tpsort[i]; cost[fail[u]] += cost[u]; elen[fail[u]] = min(elen[fail[u]], elen[u]); if (elen[u] > len[fail[u]]) { mx = max(mx, cost[u] * min(elen[u], len[u])); } } printf( %lld n , mx); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10, maxm = 2e6 + 10; const long long INF = 0x3f3f3f3f, mod = 1e9 + 7; int casn, n, m, k; namespace graph { vector<int> g[maxn]; int all, sz[maxn], root, maxt; bool vis[maxn]; int dfs_root(int now, int fa) { int cnt = 1; for (auto to : g[now]) { if (to == fa || vis[to]) continue; cnt += dfs_root(to, now); } int tmp = max(cnt - 1, all - cnt); if (maxt > tmp) maxt = tmp, root = now; return sz[now] = cnt; } int ans[maxn]; void dfs_col(int now, int fa, int c) { ans[now] = c; for (auto to : g[now]) if (to != fa && !vis[to]) dfs_col(to, now, c); } void dfs_dv(int now, int d = 0) { vis[now] = 1; dfs_col(now, now, d); for (auto to : g[now]) { if (vis[to]) continue; maxt = root = n + 1; all = sz[to]; dfs_root(to, now); dfs_dv(root, d + 1); } } void solve(int n) { all = maxt = root = n + 1; dfs_root(1, 1); dfs_dv(root); } } // namespace graph using namespace graph; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 2; i <= n; ++i) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } solve(n); for (int i = 1; i <= n; ++i) cout << char(ans[i] + A ) << ; }
|
#include <bits/stdc++.h> using namespace std; int byk[3][3]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; string s; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == B ) byk[i % 3][0]++; if (s[i] == G ) byk[i % 3][1]++; if (s[i] == R ) byk[i % 3][2]++; } int mini = 10000000; vector<int> jwb; vector<int> V; V.push_back(0); V.push_back(1); V.push_back(2); do { int x = byk[0][0] + byk[0][1] + byk[0][2]; x -= byk[0][V[0]]; int y = byk[1][0] + byk[1][1] + byk[1][2]; y -= byk[1][V[1]]; int z = byk[2][0] + byk[2][1] + byk[2][2]; z -= byk[2][V[2]]; if (x + y + z < mini) { mini = x + y + z; jwb.clear(); jwb.push_back(V[0]); jwb.push_back(V[1]); jwb.push_back(V[2]); } } while (next_permutation(V.begin(), V.end())); cout << mini << endl; for (int i = 0; i < n; i++) { if (i % 3 == 0) { if (jwb[0] == 0) cout << B ; if (jwb[0] == 1) cout << G ; if (jwb[0] == 2) cout << R ; } if (i % 3 == 1) { if (jwb[1] == 0) cout << B ; if (jwb[1] == 1) cout << G ; if (jwb[1] == 2) cout << R ; } if (i % 3 == 2) { if (jwb[2] == 0) cout << B ; if (jwb[2] == 1) cout << G ; if (jwb[2] == 2) cout << R ; } } cout << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:47:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire resetn;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.resetn(resetn));
endmodule
(* ORIG_REF_NAME = "system_clk_wiz_0_0_clk_wiz" *)
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(36.500000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(8.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(36.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int cnt = 0; while (n > 0) { if (n >= 100) { n -= 100; cnt++; } else if (n >= 20) { n -= 20; cnt++; } else if (n >= 10) { n -= 10; cnt++; } else if (n >= 5) { n -= 5; cnt++; } else if (n >= 1) { n -= 1; cnt++; } } cout << cnt; }
|
#include <bits/stdc++.h> using std::map; const int MAXN = 1000 + 3; int table[MAXN][MAXN]; int n, m, k; map<int, int> r, c; int main(int argc, char *argv[]) { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; ++i) { r[i] = i; for (int j = 1; j <= m; ++j) { if (i == 1) c[j] = j; scanf( %d , &table[i][j]); } } char cmd; int tmp, x, y; while (k--) { scanf( %s%d%d , &cmd, &x, &y); if (cmd == r ) { tmp = r[x]; r[x] = r[y]; r[y] = tmp; } else if (cmd == c ) { tmp = c[x]; c[x] = c[y]; c[y] = tmp; } else printf( %d n , table[r[x]][c[y]]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int a[1000001]; long long int b[1000001]; bool marked[1000001]; int main() { long long int n, i, j, k, x, y, fin_ans = 0, sum = 0; cin >> n >> k; a[0] = 0; for (i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; fin_ans += a[i - 1] * a[i]; } fin_ans += a[n] * a[1]; for (i = 0; i < k; i++) { cin >> x; b[i] = x; } long long val = 0; for (j = 0; j < k; j++) { marked[b[j]] = 1; val += a[b[j]]; long long to_mul = 0; if (b[j] != 1 && b[j] != n) { to_mul = sum - val - a[b[j] + 1]; if (!marked[b[j] - 1]) { to_mul -= a[b[j] - 1]; } } if (b[j] == 1) { to_mul = sum - val - a[b[j] + 1]; to_mul -= a[n]; } if (b[j] == n) { to_mul = sum - val; if (!marked[b[j] - 1]) to_mul -= a[b[j] - 1]; if (!marked[1]) to_mul -= a[1]; } fin_ans += (a[b[j]] * to_mul); } cout << fin_ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, K; int gru0[] = {0, 1, 2}; int gru1[] = {0, 1, 0, 1, 2}; int grundy(int x) { if (K) { if (x < 5) { return gru1[x]; } else if (x & 1) { return 0; } else { return grundy(x / 2) == 1 ? 2 : 1; } } else { return x <= 2 ? x : !(x & 1); } } int main() { if (fopen( input.txt , r )) { freopen( input.txt , r , stdin); } ios::sync_with_stdio(false); cin >> N >> K; K %= 2; int ans = 0; for (int i = 0, x; i < N; i++) { cin >> x; ans ^= grundy(x); } cout << (ans ? Kevin : Nicky ) << endl; }
|
#include <bits/stdc++.h> using namespace std; long long res, d, e, k; int N; int h[2020]; long long dp[2020][2020]; long long pw(long long a, long long n) { long long ret = 1; while (n) { if (n % 2) ret *= a, ret %= 998244353; a *= a, a %= 998244353; n >>= 1; } return ret; } long long C(long long n, long long r) { if (r == 0 || r == n) return 1; if (dp[n][r]) return dp[n][r]; return dp[n][r] = (C(n - 1, r - 1) + C(n - 1, r)) % 998244353; } int main() { scanf( %d %d , &N, &k); if (k == 1) return !printf( 0 ); for (int i = 0; i < N; i++) scanf( %d , &h[i]); for (int i = 0; i < N; i++) { if (h[i] == h[(i + 1) % N]) e++; else d++; } for (long long s = 0; s < d; s++) { long long mul = 1; mul *= pw(k - 2, s); mul %= 998244353; mul *= C(d, s); mul %= 998244353; long long sum = 0; for (long long m = 0; m <= (d - s - 1) / 2; m++) { sum += C(d - s, m); sum %= 998244353; } mul *= sum; mul %= 998244353; res += mul; res %= 998244353; } res *= pw(k, e); res %= 998244353; printf( %lld , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 123456789; template <class T> void scanint(T& x) { register int c = getchar(); x = 0; int m = 0; if (c == - ) { m = 1; } for (; (c < 48 || c > 57); c = getchar()) ; for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (m == 1) { x *= -1; } } template <typename T> void cinall(T& t) { cin >> t; } template <typename T, typename... Args> void cinall(T& t, Args&... args) { cin >> t; cinall(args...); } int main() { ios_base::sync_with_stdio(false); int n; cinall(n); ; vector<int> v(n); vector<int> xv(n + 1); long long sol = 0; for (int i = 0; i < n; ++i) { cin >> v[i]; sol ^= v[i]; xv[i + 1] = xv[i] ^ i; } for (int i = 2; i <= n; ++i) { sol ^= xv[((n / i) % 2) * i] ^ xv[(n % i) + 1]; } cout << sol; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_BEHAVIORAL_V
|
// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Julien Margetts.
module t (/*AUTOARG*/ out, out2, in );
input [9:0] in;
output reg [3:0] out;
output reg [3:0] out2;
// Should be no latch here since the input space is fully covered
always @* begin
casez (in)
10'b0000000000 : out = 4'h0;
10'b?????????1 : out = 4'h0;
10'b????????10 : out = 4'h1;
10'b???????100 : out = 4'h2;
10'b??????1000 : out = 4'h3;
10'b?????10000 : out = 4'h4;
10'b????100000 : out = 4'h5;
10'b??? : out = 4'h6;
10'b??10000000 : out = 4'h7;
10'b?100000000 : out = 4'h8;
10'b1000000000 : out = 4'h9;
endcase
end
// Should detect a latch here since not all paths assign
// BUT we don't because warnOff(LATCH) is set for any always containing a
// complex case statement
always @* begin
casez (in)
10'b0000000000 : out2 = 4'h0;
10'b?????????1 : out2 = 4'h0;
10'b????????10 : out2 = 4'h1;
10'b???????100 : out2 = 4'h2;
10'b??????1000 : out2 = 4'h3;
10'b?????10000 : /* No assignement */ ;
10'b????100000 : out2 = 4'h5;
10'b??? : out2 = 4'h6;
10'b??10000000 : out2 = 4'h7;
10'b?100000000 : out2 = 4'h8;
10'b1000000000 : out2 = 4'h9;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 10; struct Node { int a, b, d; } p[MAXN]; int n, k; bool cmp(Node aa, Node bb) { return aa.d < bb.d; } bool cmp2(Node aa, Node bb) { return aa.d > bb.d; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &p[i].a); for (int i = 1; i <= n; i++) { scanf( %d , &p[i].b); p[i].d = p[i].a - p[i].b; } long long ans = 0; sort(p + 1, p + 1 + n, cmp); if (p[1].d >= 0) { for (int i = 1; i <= k; i++) ans += (long long)p[i].a; for (int i = k + 1; i <= n; i++) ans += (long long)p[i].b; } else if (p[n].d <= 0) { sort(p + 1, p + 1 + n, cmp2); for (int i = 1; i <= n; i++) { ans += (long long)p[i].a; } } else { if (p[k].d <= 0) { for (int i = 1; i <= n; i++) { if (p[i].d <= 0) ans += (long long)p[i].a; else ans += (long long)p[i].b; } } else { int tmp = 0; for (int i = 1; i <= n; i++) { if (p[i].d <= 0) { ans += (long long)p[i].a; } else { tmp = i; break; } } sort(p + tmp, p + 1 + k, cmp2); for (int i = tmp; i <= k; i++) { ans += (long long)p[i].a; } for (int i = k + 1; i <= n; i++) { ans += (long long)p[i].b; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, m, k, fri = 0; cin >> n >> m >> k; vector<int> v; for (int i = 0; i < m + 1; i++) { int t; cin >> t; v.push_back(t); } int la = v[m]; vector<int> labit; for (int i = 0; i < 32; i++) { if ((1 << i) & la) labit.push_back(1); else labit.push_back(0); } for (int i = 0; i < m; i++) { int cnt = 0; for (int j = 0; j < 32; j++) { int tembit; if ((1 << j) & v[i]) tembit = 1; else tembit = 0; if (tembit != labit[j]) cnt++; } if (cnt <= k) fri++; } cout << fri; } int main() { int t = 1; for (int i = 0; i < t; i++) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_1_V
`define SKY130_FD_SC_LP__DLRTP_1_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_1_V
|
#include <bits/stdc++.h> using namespace std; int n; string c[int(20)]; int r[int(20)], b[int(20)]; int count(int mask, char color) { int ans = 0; for (int s = 0, __R = n - 1; s <= __R; s++) if (!((mask >> s) & 1) && c[s][0] == color) ans++; return ans; } int f(int i, int j, int k) { if (!i) return 0; static int dp[1 << 16][2][(1 << 8) + 1]; static bool mark[1 << 16][2][(1 << 8) + 1]; auto& ans = dp[i][j][k]; if (mark[i][j][k]) return ans; mark[i][j][k] = true; ; int R = count(i, R ), B = count(i, B ); int rs = j ? k : 0, bs = j ? 0 : k; ans = 0x3f3f3f3f3f3f3f3fLL; for (int s = 0, __R = n - 1; s <= __R; s++) if ((i >> s) & 1) { int cr = max(0, r[s] - R), cb = max(0, b[s] - B); int fr = max(0, cr - rs), fb = max(0, cb - bs); int turns = max(fr, fb); int rs_ = rs + turns - cr, bs_ = bs + turns - cb; ans = min(ans, f(i & ~(1 << s), rs_ ? 1 : 0, max(rs_, bs_)) + turns); } return ans; } int main() { int B = 0, R = 0; cin >> n; for (int i = 0, __R = n - 1; i <= __R; i++) { cin >> c[i] >> r[i] >> b[i]; B += max(0, b[i] - n); R += max(0, r[i] - n); b[i] = min(b[i], n); r[i] = min(r[i], n); } cout << f((1 << n) - 1, B > R ? 1 : 0, min(n * n, max(B, R) - min(B, R))) + max(B, R) + n << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 2, maxm = 1e7 + 5; struct node { int bg, ed, id; } a[maxn]; int n, ans[maxn]; bool vis[maxm]; bool cmp(node a, node b) { return a.ed < b.ed; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &a[i].bg, &a[i].ed); a[i].id = i; } sort(a, a + n, cmp); for (int i = 0; i < n; i++) { int y = a[i].bg; while (vis[y]) y++; vis[y] = true; ans[a[i].id] = y; } for (int i = 0; i < n; i++) printf( %d , ans[i]); return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo (
clock,
data,
rdreq,
wrreq,
empty,
q);
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output empty;
output [7:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_TB_V
`define SKY130_FD_SC_LP__INPUTISO0P_TB_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso0p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__inputiso0p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_TB_V
|
#include <bits/stdc++.h> using namespace std; double alto, ancho, altomesa, anchomesa, ancho1, alto1, x_1, x_2, y_1, y_2; double abajo() { if (altomesa <= y_1) return 0; return altomesa - y_1; } double arriba() { if (altomesa <= alto - y_2) return 0; return altomesa - (alto - y_2); } double izquierda() { if (anchomesa <= x_1) return 0; return anchomesa - x_1; } double derecha() { if (anchomesa <= ancho - x_2) return 0; return anchomesa - (ancho - x_2); } void solve() { cin >> ancho >> alto; cin >> x_1 >> y_1 >> x_2 >> y_2; cin >> anchomesa >> altomesa; ancho1 = x_2 - x_1, alto1 = y_2 - y_1; if (ancho1 + anchomesa > ancho && alto1 + altomesa > alto) { cout << -1; return; } double ans = 100000000; if (ancho1 + anchomesa <= ancho) { ans = min(ans, izquierda()); ans = min(ans, derecha()); } if (alto1 + altomesa <= alto) { ans = min(ans, arriba()); ans = min(ans, abajo()); } printf( %.6f , ans); } int main() { int T = 1; cin >> T; cout << n ; while (T--) solve(), cout << n ; return 0; }
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: helloworld.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To create a *very* simple UART test program, which can be used
// as the top level design file of any FPGA program.
//
// With some modifications (discussed below), this RTL should be able to
// run as a top-level testing file, requiring only the UART and clock pin
// to work.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
// }}}
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
// {{{
//
// Two versions of the UART can be found in the rtl directory: a full featured
// UART, and a LITE UART that only handles 8N1 -- no break sending, break
// detection, parity error detection, etc. If we set USE_LITE_UART here, those
// simplified UART modules will be used.
// }}}
// `define USE_LITE_UART
//
`default_nettype none
//
module helloworld #(
// {{{
// Here we set i_setup to something appropriate to create a
// 115200 Baud UART system from a 100MHz clock. This also sets
// us to an 8-bit data word, 1-stop bit, and no parity. This
// will be overwritten by i_setup, but at least it gives us
// something to start with/from.
// Verilator lint_off UNUSED
parameter INITIAL_UART_SETUP = 31'd868
// Verilator lint_on UNUSED
// }}}
) (
// {{{
input wire i_clk,
`ifndef OPT_STANDALONE
input wire [30:0] i_setup,
`endif
output wire o_uart_tx
// }}}
);
// Signal declarations
// {{{
reg [7:0] message [0:15];
reg pwr_reset;
reg [27:0] counter;
wire tx_break, tx_busy;
reg tx_stb;
reg [3:0] tx_index;
reg [7:0] tx_data;
wire cts_n;
// }}}
// i_setup
// {{{
`ifdef OPT_STANDALONE
// The i_setup wires are input when run under Verilator, but need to
// be set internally if this is going to run as a standalone top level
// test configuration.
assign i_setup = INITIAL_UART_SETUP;
`endif
// }}}
// pwr_reset
// {{{
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset <= 1'b0;
// }}}
// Initialize the message
// {{{
initial begin
message[ 0] = "H";
message[ 1] = "e";
message[ 2] = "l";
message[ 3] = "l";
message[ 4] = "o";
message[ 5] = ",";
message[ 6] = " ";
message[ 7] = "W";
message[ 8] = "o";
message[ 9] = "r";
message[10] = "l";
message[11] = "d";
message[12] = "!";
message[13] = " ";
message[14] = "\r";
message[15] = "\n";
end
// }}}
// Send a Hello World message to the transmitter
// {{{
initial counter = 28'hffffff0;
always @(posedge i_clk)
counter <= counter + 1'b1;
assign tx_break = 1'b0;
initial tx_index = 4'h0;
always @(posedge i_clk)
if ((tx_stb)&&(!tx_busy))
tx_index <= tx_index + 1'b1;
always @(posedge i_clk)
tx_data <= message[tx_index];
initial tx_stb = 1'b0;
always @(posedge i_clk)
if (&counter)
tx_stb <= 1'b1;
else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
tx_stb <= 1'b0;
// }}}
// The UART transmitter
// {{{
// Bypass any hardware flow control
assign cts_n = 1'b0;
`ifdef USE_LITE_UART
txuartlite
#(24'd868)
transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
`else
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
`endif
// }}}
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; int i, count = 0; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 1; i < n - 1; i++) { if (a[i] == 0 && a[i - 1] == 1 && a[i + 1] == 1) { count++; i += 2; } } printf( %d , count); return 0; }
|
#include <bits/stdc++.h> using namespace std; int M, K, i, st, ed, ans[2], arr[100005]; int main() { cin >> M >> K; for (i = st = ed = 0; i < M; i++) cin >> arr[i]; sort(arr, arr + M, greater<int>()); while (1) { while ((ed + 1) < M && (arr[st] - arr[ed + 1]) <= K) K -= (arr[st] - arr[++ed]); if ((ed - st + 1) >= ans[0]) { ans[0] = (ed - st + 1); ans[1] = arr[st]; } if (ed == M - 1 || st == M - 1) break; K += ((arr[st] - arr[st + 1]) * (ed - st)); st++; } cout << ans[0] << << ans[1] << endl; }
|
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module fjmem_jtag (
output jtag_tck,
output jtag_rst,
output jtag_update,
output jtag_shift,
output jtag_tdi,
input jtag_tdo
);
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(1)
) bscan (
.CAPTURE(),
.DRCK(jtag_tck),
.RESET(jtag_rst),
.RUNTEST(),
.SEL(),
.SHIFT(jtag_shift),
.TCK(),
.TDI(jtag_tdi),
.TMS(),
.UPDATE(jtag_update),
.TDO(jtag_tdo)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int vis[10100]; int dist[10100]; int pre[10100], cntt[30]; char str[10100]; struct Edge { int u, v, c, cost, next; } edge[1000100]; int anss, head[10100], cnt; void init() { cnt = 0; memset(head, -1, sizeof(head)); } void addedge(int u, int v, int c, int cost) { edge[cnt].u = u; edge[cnt].v = v; edge[cnt].cost = cost; edge[cnt].c = c; edge[cnt].next = head[u]; head[u] = cnt++; edge[cnt].u = v; edge[cnt].v = u; edge[cnt].cost = -cost; edge[cnt].c = 0; edge[cnt].next = head[v]; head[v] = cnt++; } bool spfa(int begin, int end) { int u, v; queue<int> q; for (int i = 0; i <= end + 2; i++) { pre[i] = -1; vis[i] = 0; dist[i] = 99999999; } vis[begin] = 1; dist[begin] = 0; q.push(begin); while (!q.empty()) { u = q.front(); q.pop(); vis[u] = 0; for (int i = head[u]; i != -1; i = edge[i].next) { if (edge[i].c > 0) { v = edge[i].v; if (dist[v] > dist[u] + edge[i].cost) { dist[v] = dist[u] + edge[i].cost; pre[v] = i; if (!vis[v]) { vis[v] = true; q.push(v); } } } } } return dist[end] != 99999999; } int MCMF(int begin, int end) { int ans = 0, flow; int flow_sum = 0; while (spfa(begin, end)) { flow = 99999999; for (int i = pre[end]; i != -1; i = pre[edge[i].u]) if (edge[i].c < flow) flow = edge[i].c; for (int i = pre[end]; i != -1; i = pre[edge[i].u]) { edge[i].c -= flow; edge[i ^ 1].c += flow; } ans += dist[end] * flow; flow_sum += flow; } anss = flow_sum; return ans; } int main() { int n, m, a, b, c, cost, i, j, cc, len; scanf( %s , str); len = strlen(str); init(); for (i = 0; i < strlen(str); i++) cntt[str[i] - 97]++; scanf( %d , &n); for (i = n + 1; i <= n + 26; i++) addedge(i, n + 27, cntt[i - n - 1], 0); for (i = 1; i <= n; i++) { scanf( %s%d , str, &cc); addedge(0, i, cc, i); memset(cntt, 0, sizeof(cntt)); for (j = 0; j < strlen(str); j++) cntt[str[j] - 97]++; for (j = 0; j < 26; j++) addedge(i, n + 1 + j, cntt[j], 0); } int z = MCMF(0, n + 27); if (anss == len) printf( %d n , z); else printf( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long linf = 1e18 + 5; const int mod = (int)1e9 + 7; const int logN = 17; const int inf = 1e9; const int N = 2e5 + 5; int main() { int n, t; vector<pair<int, int> > ans; scanf( %d , &n); queue<int> q; for (int i = 1; i <= n; i++) { scanf( %d , &t); while (q.size() > t) { ans.push_back(make_pair(q.front(), i - 1)); q.pop(); } while (q.size() < t) q.push(i); } while (q.size()) { ans.push_back(make_pair(q.front(), n)); q.pop(); } cout << ans.size() << n ; for (__typeof(ans.begin()) it = ans.begin(); it != ans.end(); it++) cout << it->first << << it->second << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_20_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_20_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog wrapper for busdrivernovlpsleep with size of 20 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlpsleep.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep_20 (
Z ,
A ,
TE_B ,
SLEEP,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B ;
input SLEEP;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busdrivernovlpsleep base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep_20 (
Z ,
A ,
TE_B ,
SLEEP
);
output Z ;
input A ;
input TE_B ;
input SLEEP;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busdrivernovlpsleep base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_20_V
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int n) { if (n == 0) return 1; else if (n % 2 == 0) return power(x * x, n / 2); else return x * power(x * x, (n - 1) / 2); } long long int highestPowerof2(long long int n) { long long int p = (long long int)log2(n); return (long long int)pow(2, p); } long long int powermod(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m, i, j, k, count; bool ok = false; cin >> n >> m; long long int a[n][m]; long long int arr[n][m]; memset(arr, -1, sizeof(arr)); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) cin >> a[i][j]; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (a[i][j] == 0) { for (k = 0; k < n; k++) arr[k][j] = 0; for (k = 0; k < m; k++) arr[i][k] = 0; } } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (arr[i][j] == -1) arr[i][j] = 1; } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { count = 0; if (a[i][j] == 1) { for (k = 0; k < n; k++) if (arr[k][j] == 1) count++; for (k = 0; k < m; k++) if (arr[i][k] == 1) count++; if (count == 0) { ok = true; break; } } else if (a[i][j] == 0) { for (k = 0; k < n; k++) if (arr[k][j] == 1) count++; for (k = 0; k < m; k++) if (arr[i][k] == 1) count++; if (count != 0) { ok = true; break; } } } if (ok) break; } if (ok) cout << NO << endl; else { cout << YES << endl; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cout << arr[i][j] << ; } cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[300003]; vector<int> adje[300003]; int d[300003]; int pickd[300003]; bool vis[300003]; int n, m; int x; int dfs1(int u) { int ans = 0; if (d[u] == -1) x = u; else if (d[u] == 1) ++ans; vis[u] = true; for (int v : adj[u]) { if (!vis[v]) { ans += dfs1(v); } } return ans; } int dfs2(int u) { int ans = 0; if (d[u] == 1) ++ans; vis[u] = true; for (int i = 0; i < ((int)(adj[u].size())); ++i) { int v = adj[u][i]; if (!vis[v]) { int c = dfs2(v); if (c % 2) pickd[adje[u][i]] = 1; ans += c; } } return ans; } bool solve() { memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; ++i) { if (!vis[i]) { x = -1; int c = dfs1(i); if (c % 2) { if (x == -1) return false; else { d[x] = 1; } } } } memset(vis, 0, sizeof(vis)); memset(pickd, 0, sizeof(pickd)); for (int i = 1; i <= n; ++i) { if (!vis[i]) { dfs2(i); } } int k = accumulate(pickd + 1, pickd + m + 1, 0); cout << k << n ; for (int i = 1; i <= m; ++i) { if (pickd[i]) { cout << i << n [(--k) == 0]; } } return true; } int main() { ios ::sync_with_stdio(0); while (cin >> n >> m) { for (int i = 1; i <= n; ++i) { cin >> d[i]; } for (int i = 1; i <= m; ++i) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); adje[u].push_back(i); adje[v].push_back(i); } if (!solve()) cout << -1 n ; for (int i = 1; i <= n; ++i) { adj[i].clear(); adje[i].clear(); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, t, t1 = 0; cin >> n >> k; cin >> t1; for (int i = 2; i <= n; i++) { cin >> t; t1 += t + 1; } if (t1 == k) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10, INF = 1e9; vector<int> g[N], r[N], out; int cnt[N], ans = INF, sum = 0; int dfs(int v, int par) { for (int i = 0; i < g[v].size(); i++) if (g[v][i] != par) cnt[v] += dfs(g[v][i], v); for (int i = 0; i < r[v].size(); i++) if (r[v][i] != par) cnt[v] += 1 + dfs(r[v][i], v); return cnt[v]; } void dfs2(int v, int par, int a, int b) { for (int i = 0; i < g[v].size(); i++) if (g[v][i] != par) dfs2(g[v][i], v, a + 1, b); for (int i = 0; i < r[v].size(); i++) if (r[v][i] != par) dfs2(r[v][i], v, a, b + 1); int cur = sum - b + a; if (cur < ans) { ans = cur; out.clear(); out.push_back(v + 1); } else if (cur == ans) out.push_back(v + 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--; b--; g[a].push_back(b); r[b].push_back(a); } dfs(0, -1); sum = cnt[0]; dfs2(0, -1, 0, 0); cout << ans << n ; sort(out.begin(), out.end()); for (int i = 0; i < out.size(); i++) cout << out[i] << n [i == out.size() - 1]; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR3B_BEHAVIORAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; int x = 0, y = 0; int n = b.length(); while (x < n && a[x] == b[x]) x++; while (y < n && a[n - y] == b[n - 1 - y]) y++; int res = x + y + 2 - (n + 1); res = max(0, min(res, n + 1)); cout << res << endl; int start = n - y + 1; for (int i = 0; i < res; i++) cout << (start + i) << ; cout << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:45:30 01/30/2016
// Design Name:
// Module Name: third_step
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module third_step(
/*Control signals input*/
input wire aluSrc,
input wire [5:0] ALUOp,
input wire regDst,
input wire [1:0] ForwardAE,
input wire [1:0] ForwardBE,
/*Data signals input*/
//input wire [31:0] pcPlusFour,
input wire [31:0] reg1,
input wire [31:0] reg2,
input wire [31:0] signExtend,
input wire [4:0] regDst1,
input wire [4:0] regDst2,
input wire [31:0] reg_muxes_b,
input wire [31:0] reg_muxes_d,
/*Signal output*/
//output wire [31:0] addResult,
//output wire zero,
output wire [31:0] aluResult,
output wire [31:0] reg2Out,
output wire [4:0] muxRegDstOut
);
mux #(5) muxRegDst (
.select(regDst),
.item_a(regDst1),
.item_b(regDst2),
.signal(muxRegDstOut)
);
//For hazards
wire [31:0] ALUoperator1;
mux4 mux_reg1
(
.sel(ForwardAE),
.item_a(reg1),
.item_b(reg_muxes_b),
.item_c(reg_muxes_d),
.item_d(),
.signal(ALUoperator1)
);
wire [31:0] ALUoperator2;
mux4 mux_reg2
(
.sel(ForwardBE),
.item_a(reg2),
.item_b(reg_muxes_b),
.item_c(reg_muxes_d),
.item_d(),
.signal(ALUoperator2)
);
wire [31:0] muxAluSrc2Out;
mux muxAluSrc2 (
.select(aluSrc),
.item_a(ALUoperator2),
.item_b(signExtend),
.signal(muxAluSrc2Out)
);
wire [3:0] ALUcontrolOut;
alu_control aluControl (
.ALUOp(ALUOp), //TODO: conectar la seal de control correspondiente de la unidad de control
.funct(signExtend[5:0]),
.ALUcontrolOut(ALUcontrolOut)
);
alu aluModule (
.op1(ALUoperator1),
.op2(muxAluSrc2Out),
.alu_control(ALUcontrolOut),
.result(aluResult),
.zero()
);
wire [31:0] shiftLeftOut;
/*
shift_left shiftModule(
.shift_in(signExtend),
.shift_out(shiftLeftOut)
);
adder #(32) adderModule(
.value1(pcPlusFour),
.value2(shiftLeftOut),
.result(addResult)
);
*/
assign reg2Out = ALUoperator2;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
`timescale 1ns / 1ps
//Control Unit.
module CUnit(
input wire clk,
input wire reset,
output reg rw,
output reg [31:0] wD,
input wire [31:0] rD,
output reg e,
output reg [9:0] MAR,
input wire le,
input wire eq,
input wire gt,
input wire [31:0] c,
output reg [31:0] a,
output reg [31:0] b,
output reg [3:0] s
);
//Opcodes.
localparam NOP = 5'd0;
localparam SUM = 5'd1;
localparam SUS = 5'd2;
localparam MUL = 5'd3;
localparam DIV = 5'd4;
localparam AND = 5'd5;
localparam OR = 5'd6;
localparam NOT = 5'd7;
localparam LE = 5'd8;
localparam EQ = 5'd9;
localparam GT = 5'd10;
localparam LW = 5'd11;
localparam SW = 5'd12;
localparam J = 5'd13;
localparam BEQ = 5'd14;
localparam BLE = 5'd15;
localparam BGT = 5'd16;
//1111_b
localparam FIN = 4'd31;
//Internal registers
reg [9:0] PC;
reg [31:0] R [15:0];
reg [31:0] IR;
reg [31:0] MBR;
reg [31:0] alu_c;
reg [3:0] T;
integer i;
always @(posedge clk) begin
if (reset) begin
//All registers in 0's
PC = 10'b0;
for (i = 0; i < 16; i = i + 1) begin
R[i] = 32'b0;
end
IR = 32'b0;
MBR = 32'b0;
alu_c = 32'b0;
T = 4'b0;
e = 1;
end
else begin
case (T)
//Fetch
4'h0: begin
rw = 0; //Read
MAR = PC;
end
//Wait 1 time for memory answer.
4'h2: begin
MBR = rD;
PC = PC + 1;
end
4'h3: IR = MBR;
endcase
case (IR[31:27]) //Opcode
NOP: begin
T = FIN;
end
SUM: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd0;
end
4'h6: alu_c = c;
4'h7: R[IR[18:15]] = alu_c;
4'h8: T = FIN;
endcase
end
SUS: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd1;
4'h6: alu_c = c;
4'h7: R[IR[18:15]] = alu_c;
4'h8: T = FIN;
endcase
end
MUL: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd2;
end
4'h6: alu_c = c;
4'h7: R[IR[18:15]] = alu_c;
4'h8: T = FIN;
endcase
end
DIV: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd3;
end
4'h6: alu_c = c;
4'h7: R[IR[18:15]] = alu_c;
4'h8: T = FIN;
endcase
end
AND: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd7;
end
4'h6: alu_c = c;
4'h7: R[IR[18:15]] = alu_c;
4'h8: T = FIN;
endcase
end
OR: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd8;
end
4'h6: alu_c = c;
4'h7: R[IR[18:15]] = alu_c;
4'h8: T = FIN;
endcase
end
NOT: begin
case (T)
4'h4: begin
a = R[IR[26:23]];
s = 4'd9;
end
4'h5: alu_c = c;
4'h6: R[IR[22:19]] = alu_c;
4'h7: T = FIN;
endcase
end
LE: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd4;
end
4'h6: if (le) R[IR[18:15]] = 32'b1;
else R[IR[18:15]] = 32'b0;
4'h7: T = FIN;
endcase
end
EQ: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd5;
end
4'h6: if (eq) R[IR[18:15]] = 32'b1;
else R[IR[18:15]] = 32'b0;
4'h7: T = FIN;
endcase
end
GT: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd6;
end
4'h6: if (gt) R[IR[18:15]] = 32'b1;
else R[IR[18:15]] = 32'b0;
4'h7: T = FIN;
endcase
end
LW: begin
case (T)
4'h6: MAR = begin
IR[22:13];
rw = 0; //Read.
end
4'h7: MBR = rD;
//Wait 1 time for memory answer.
4'h9: R[IR[26:23]] = MBR;
4'h10: T = FIN;
endcase
end
SW: begin
case (T)
4'h6: begin
MAR = IR[22:13];
rw = 1; //Write.
end
4'h7: R[IR[26:23]] = MBR;
4'h8: wD = MBR;
//Wait 1 time for memory to end.
4'h10: T = FIN;
endcase
end
J: begin
case (T)
4'h4: PC = IR[26:17];
4'h5: T = FIN;
endcase
end
BEQ: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd5;
end
4'h6: if (eq) PC = IR[18:9];
else T = FIN;
4'h7: T = FIN;
endcase
end
BLE: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd4;
end
4'h6: if (le) PC = IR[18:9];
else T = FIN;
4'h7: T = FIN;
endcase
end
BGT: begin
case (T)
4'h4: a = R[IR[26:23]];
4'h5: begin
b = R[IR[22:19]];
s = 4'd6;
end
4'h6: if (gt) PC = IR[18:9];
else T = FIN;
4'h7: T = FIN;
endcase
end
endcase
//Increase the Timer.
T = T + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxlen = 2e5 + 2; long long ans; long long lt[Maxlen], ls[2 * Maxlen]; int n, m, dpt[Maxlen], dps[Maxlen]; char ct[Maxlen], cs[2 * Maxlen]; long long cmp(int pos) { if (cs[0] != ct[pos] || ls[0] > lt[pos]) return 0; if (m == 1) return lt[pos] - ls[0] + 1; pos++; int p1 = 1; while (p1 < m && pos < n && cs[p1] == ct[pos] && ls[p1] == lt[pos]) { pos++; p1++; } if (p1 < m && pos < n && cs[p1] == ct[pos] && ls[p1] < lt[pos]) p1++; if (p1 == m) return 1; return 0; } int kmp() { int res = 0; for (int i = 1; i < n + m; i++) { int j = dps[i - 1]; if (j == m - 2 && cs[i] == cs[j] && ls[i] >= ls[j]) res++; while (j > 0 && (cs[i] != cs[j] || ls[i] != ls[j])) j = dps[j - 1]; if (cs[j] == cs[i]) if (ls[j] == ls[i] || (j == 0 && ls[i] >= ls[j])) ++j; dps[i] = j; } return res; } int main() { scanf( %d%d , &n, &m); scanf( %d-%c , <[0], &ct[0]); for (int i = 1; i < n; i++) { scanf( %d-%c , <[i], &ct[i]); if (ct[i] == ct[i - 1]) { lt[i - 1] += lt[i]; n--; i--; } } scanf( %d-%c , &ls[0], &cs[0]); for (int i = 1; i < m; i++) { scanf( %d-%c , &ls[i], &cs[i]); if (cs[i] == cs[i - 1]) { ls[i - 1] += ls[i]; m--; i--; } } if (m == 1) { for (int i = 0; i < n; i++) ans = ans + cmp(i); } else { cs[m++] = # ; for (int i = 0; i < n; i++) { cs[m + i] = ct[i]; ls[m + i] = lt[i]; } ans = kmp(); } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string s; while (n--) cin >> s; bool wall = false; int segments = 0, i = 0; while (i < s.size()) { if (!wall && s[i] == B ) { segments++; wall = true; } else if (wall && s[i] == . ) { wall = false; } i++; } cout << segments << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, k1 = 0, k2 = 0; cin >> a; string h; cin >> h; string *s = new string[a]; for (int i = 0; i < a; i++) { cin >> s[i]; if (s[i].substr(s[i].size() - 3, 3) == h) k1++; else k2++; } if (k1 == k2) cout << home ; else cout << contest ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; const int maxn = 1001000; const int mod = 1000000007; int a[maxn], f[maxn], r[maxn]; int main() { int n; scanf( %d , &n); for (int e = 1; e <= n; e++) scanf( %d , a + e); auto mul = [](int x, int y) { return 1ll * x * y % mod; }; f[0] = 1; for (int e = 1; e <= n; e++) f[e] = mul(e, f[e - 1]); r[n + 1] = 1; for (int e = n; e >= 1; e--) r[e] = mul(e, r[e + 1]); sort(a + 1, a + 1 + n); int small = 0; int i = 1, j = 1; int ans = 0; while (i <= n) { while (j <= n && a[i] == a[j]) j++; if (j == n + 1) break; ans += mul(j - i, mul(a[i], mul(f[n - small - 1], r[n - small + 1]))); small += j - i; if (ans >= mod) ans -= mod; i = j; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1; const long long MOD = 1; long long _gcd(long long a, long long b) { if (b == 0) return a; return _gcd(b, a % b); } long long gcd(long long a, long long b) { a = abs(a), b = abs(b); if (a < b) swap(a, b); return _gcd(a, b); } long long qpow(long long a, long long n) { long long rt = 1; while (n) { if (n & 1) rt = (rt * a) % MOD; a = a * a % MOD; n >>= 1; } return rt; } long long factor[MAXN]; long long inv[MAXN]; void cal_factor() { factor[0] = 1; for (int u = 1; u < MAXN; u++) { factor[u] = (factor[u - 1] * u) % MOD; } } void cal_factor_inv() { inv[0] = 1; inv[MAXN - 1] = qpow(factor[MAXN - 1], MOD - 2); for (int u = MAXN - 2; u >= 1; u--) { inv[u] = inv[u + 1] * (u + 1) % MOD; } } void init_factor() { cal_factor(); cal_factor_inv(); } long long C(long long n, long long k) { if (n < k) return 0; return factor[n] * qpow(factor[n - k], MOD - 2) % MOD * qpow(factor[k], MOD - 2) % MOD; } void solve() { int n; cin >> n; int mx = 0; int g = -1; for (int u = 0; u < n; u++) { int t; cin >> t; if (g == -1) g = t; else g = gcd(g, t); mx = max(t, mx); } if ((mx / g - n) % 2) { cout << Alice n ; } else { cout << Bob n ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); }
|
module stimulus (output reg A, B);
initial begin
// both inputs are x
#0 {A, B} = 2'bxx;
// both inputs are z
#10 {A, B} = 2'bzz;
// one input is a zero
#10 {A, B} = 2'b0x;
#10 {A, B} = 2'bx0;
#10 {A, B} = 2'b0z;
#10 {A, B} = 2'bz0;
// one input is a one
#10 {A, B} = 2'b1x;
#10 {A, B} = 2'bx1;
#10 {A, B} = 2'b1z;
#10 {A, B} = 2'bz1;
// one input x, other z
#10 {A, B} = 2'bxz;
#10 {A, B} = 2'bzx;
// normal bit operands
#10 {A, B} = 2'b00;
#10 {A, B} = 2'b01;
#10 {A, B} = 2'b10;
#10 {A, B} = 2'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
// both inputs are x
2'bxx: gate_output = 1'bx;
// both inputs are z
2'bzz: gate_output = 1'bx;
// output should be x (one input is a one)
2'b1x: gate_output = 1'bx;
2'bx1: gate_output = 1'bx;
2'b1z: gate_output = 1'bx;
2'bz1: gate_output = 1'bx;
// output is x (one input is a zero)
2'b0x: gate_output = 1'bx;
2'bx0: gate_output = 1'bx;
2'b0z: gate_output = 1'bx;
2'bz0: gate_output = 1'bx;
// inputs x, z
2'bxz: gate_output = 1'bx;
2'bzx: gate_output = 1'bx;
// normal operation on bit
2'b00: gate_output = 1;
2'b01: gate_output = 0;
2'b10: gate_output = 0;
2'b11: gate_output = 1;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in XNOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
xnor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#200;
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct yts { long long dp[210][210]; } a, ans, t; int ch[210][26], fail[210], q[210], root = 1; long long w[210], b[210]; int n, m, tot = 1; char s[210]; long long L; void insert(int id) { int x = root, len = strlen(s + 1); for (int i = 1; i <= len; i++) { int t = s[i] - a ; if (!ch[x][t]) ch[x][t] = ++tot; x = ch[x][t]; } w[x] += b[id]; } void build_fail() { int l = 0, r = 0; for (int i = 0; i < 26; i++) if (ch[root][i]) fail[ch[root][i]] = root, q[++r] = ch[root][i]; else ch[root][i] = root; while (l < r) { int x = q[++l]; w[x] += w[fail[x]]; for (int i = 0; i < 26; i++) if (ch[x][i]) fail[ch[x][i]] = ch[fail[x]][i], q[++r] = ch[x][i]; else ch[x][i] = ch[fail[x]][i]; } } void mul(yts &c, yts &a, yts &b) { memset(t.dp, -1, sizeof(t.dp)); for (int k = 1; k <= tot; k++) for (int i = 1; i <= tot; i++) for (int j = 1; j <= tot; j++) if (a.dp[i][k] != -1 && b.dp[k][j] != -1) t.dp[i][j] = max(t.dp[i][j], a.dp[i][k] + b.dp[k][j]); for (int i = 1; i <= tot; i++) for (int j = 1; j <= tot; j++) c.dp[i][j] = t.dp[i][j]; } void power() { memset(ans.dp, -1, sizeof(ans.dp)); for (int i = 1; i <= tot; i++) ans.dp[i][i] = 0; while (L) { if (L & 1) mul(ans, ans, a); mul(a, a, a); L >>= 1; } } void build_a() { memset(a.dp, -1, sizeof(a.dp)); for (int i = 1; i <= tot; i++) for (int c = 0; c < 26; c++) { if (a.dp[i][ch[i][c]] == -1) a.dp[i][ch[i][c]] = 0; a.dp[i][ch[i][c]] += w[ch[i][c]]; } } int main() { scanf( %d%I64d , &n, &L); for (int i = 1; i <= n; i++) scanf( %I64d , &b[i]); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); insert(i); } build_fail(); build_a(); power(); long long ANS = 0; for (int i = 1; i <= tot; i++) if (ans.dp[root][i] != -1) ANS = max(ANS, ans.dp[root][i]); printf( %I64d n , ANS); return 0; }
|
#include <bits/stdc++.h> using namespace std; int nos; void split(int n) { if (nos == 0 || n == 1) cout << n << ; else { --nos; split(n / 2); split(n / 2); } } int main() { ios::sync_with_stdio(false); int n, k; cin >> k >> n; if (n > k) cout << NO << endl; else { vector<int> nums; for (int i = 0; k; k /= 2, ++i) { if (k % 2) nums.push_back(pow(2, i)); } nos = n - nums.size(); if (nos < 0) cout << NO << endl; else { cout << YES << endl; for (auto &i : nums) split(i); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; struct node { int c, f, l, i; } a[maxn], b[maxn]; bool cmp1(node a, node b) { return a.f < b.f; } bool cmp2(node a, node b) { return a.c > b.c; } int main() { int n, d, s; scanf( %d%d%d , &n, &d, &s); int nn = n; int m = 0; int ss = s; for (int i = 1; i <= n; i++) { scanf( %d%d%d , &a[i].c, &a[i].f, &a[i].l); a[i].i = i; b[i] = a[i]; if (a[i].c != 0 && a[i].l >= d) { if (m == 0 || a[m].f > a[i].f) m = i; } } int ansf = 0; int ansc = 0; if (m != 0 && a[m].f <= s) { s = s - a[m].f; sort(a + 1, a + 1 + n, cmp2); int sumc = a[1].c; int sum = 1; for (int i = 2; i <= n; i++) { sum++; sumc = sumc - 1 + a[i].c; if (sumc == 0) break; } int j = 0; for (int i = 1; i <= n; i++) if (a[i].l >= d && a[i].i != m) { a[++j] = a[i]; } n = j; sort(a + 1, a + 1 + n, cmp1); for (int i = 1; i <= n; i++) { if (sum == nn) break; if (s >= a[i].f) { sum++; s -= a[i].f; } else break; } ansf = ss - s; ansc = sum; } n = nn; for (int i = 1; i <= n; i++) a[i] = b[i]; s = ss; int sumc = 0; int j = 0; for (int i = 1; i <= n; i++) if (a[i].c == 0 && a[i].l >= d) { a[++j] = a[i]; } n = j; sort(a + 1, a + 1 + n, cmp1); for (int i = 1; i <= n; i++) { if (s >= a[i].f) { sumc++; s -= a[i].f; } else break; } if (ansc < sumc) { ansf = ss - s; ansc = sumc; } else if (ansc == sumc && ansf > ss - s) { ansf = ss - s; ansc = sumc; } printf( %d %d n , ansc, ansf); return 0; }
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 66,
parameter inUsePackets = 0,
parameter inDataWidth = 66,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 66,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [65:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [65:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
* Copyright (c) 2015, Arch Labolatory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module GEN( input wire CLK_IN,
input wire RST_X_IN,
output wire CLK_OUT,
output wire VGA_CLK_OUT,
output wire RST_X_OUT
);
wire LOCKED, VLOCKED, CLK_IBUF;
wire RST_X_BUF;
clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule
module RSTGEN(CLK, RST_X_I, RST_X_O);
input CLK, RST_X_I;
output RST_X_O;
reg [7:0] cnt;
assign RST_X_O = cnt[7];
always @(posedge CLK or negedge RST_X_I) begin
if (!RST_X_I) cnt <= 0;
else if (~RST_X_O) cnt <= (cnt + 1'b1);
end
endmodule
|
// File : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v
// Generated : 11/10/06 05:37:24
// From : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// usbTxWireArbiter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbConstants_h.v"
`include "usbSerialInterfaceEngine_h.v"
module USBTxWireArbiter (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
input SIETxCtrl;
input [1:0] SIETxData;
input SIETxFSRate;
input SIETxReq;
input SIETxWEn;
input USBWireRdyIn;
input clk;
input prcTxByteCtrl;
input [1:0] prcTxByteData;
input prcTxByteFSRate;
input prcTxByteReq;
input prcTxByteWEn;
input rst;
output SIETxGnt;
output [1:0] TxBits;
output TxCtl;
output TxFSRate;
output USBWireRdyOut;
output USBWireWEn;
output prcTxByteGnt;
wire SIETxCtrl;
wire [1:0] SIETxData;
wire SIETxFSRate;
reg SIETxGnt, next_SIETxGnt;
wire SIETxReq;
wire SIETxWEn;
reg [1:0] TxBits, next_TxBits;
reg TxCtl, next_TxCtl;
reg TxFSRate, next_TxFSRate;
wire USBWireRdyIn;
reg USBWireRdyOut, next_USBWireRdyOut;
reg USBWireWEn, next_USBWireWEn;
wire clk;
wire prcTxByteCtrl;
wire [1:0] prcTxByteData;
wire prcTxByteFSRate;
reg prcTxByteGnt, next_prcTxByteGnt;
wire prcTxByteReq;
wire prcTxByteWEn;
wire rst;
// diagram signals declarations
reg muxSIENotPTXB, next_muxSIENotPTXB;
// BINARY ENCODED state machine: txWireArb
// State codes definitions:
`define START_TARB 2'b00
`define TARB_WAIT_REQ 2'b01
`define PTXB_ACT 2'b10
`define SIE_TX_ACT 2'b11
reg [1:0] CurrState_txWireArb;
reg [1:0] NextState_txWireArb;
// Diagram actions (continuous assignments allowed only: assign ...)
// processTxByte/SIETransmitter mux
always @(USBWireRdyIn)
begin
USBWireRdyOut <= USBWireRdyIn;
end
always @(muxSIENotPTXB or SIETxWEn or SIETxData or
SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
SIETxFSRate or prcTxByteFSRate)
begin
if (muxSIENotPTXB == 1'b1)
begin
USBWireWEn <= SIETxWEn;
TxBits <= SIETxData;
TxCtl <= SIETxCtrl;
TxFSRate <= SIETxFSRate;
end
else
begin
USBWireWEn <= prcTxByteWEn;
TxBits <= prcTxByteData;
TxCtl <= prcTxByteCtrl;
TxFSRate <= prcTxByteFSRate;
end
end
//--------------------------------------------------------------------
// Machine: txWireArb
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
begin : txWireArb_NextState
NextState_txWireArb <= CurrState_txWireArb;
// Set default values for outputs and signals
next_prcTxByteGnt <= prcTxByteGnt;
next_muxSIENotPTXB <= muxSIENotPTXB;
next_SIETxGnt <= SIETxGnt;
case (CurrState_txWireArb)
`START_TARB:
NextState_txWireArb <= `TARB_WAIT_REQ;
`TARB_WAIT_REQ:
if (prcTxByteReq == 1'b1)
begin
NextState_txWireArb <= `PTXB_ACT;
next_prcTxByteGnt <= 1'b1;
next_muxSIENotPTXB <= 1'b0;
end
else if (SIETxReq == 1'b1)
begin
NextState_txWireArb <= `SIE_TX_ACT;
next_SIETxGnt <= 1'b1;
next_muxSIENotPTXB <= 1'b1;
end
`PTXB_ACT:
if (prcTxByteReq == 1'b0)
begin
NextState_txWireArb <= `TARB_WAIT_REQ;
next_prcTxByteGnt <= 1'b0;
end
`SIE_TX_ACT:
if (SIETxReq == 1'b0)
begin
NextState_txWireArb <= `TARB_WAIT_REQ;
next_SIETxGnt <= 1'b0;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : txWireArb_CurrentState
if (rst)
CurrState_txWireArb <= `START_TARB;
else
CurrState_txWireArb <= NextState_txWireArb;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : txWireArb_RegOutput
if (rst)
begin
muxSIENotPTXB <= 1'b0;
prcTxByteGnt <= 1'b0;
SIETxGnt <= 1'b0;
end
else
begin
muxSIENotPTXB <= next_muxSIENotPTXB;
prcTxByteGnt <= next_prcTxByteGnt;
SIETxGnt <= next_SIETxGnt;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 450007; int read() { int ans = 0, f = 1, c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { ans = ans * 10 + (c - 0 ); c = getchar(); } return ans * f; } int n, k, sum1, sum2; int x[M], y[M], f[M]; int main() { n = read(); for (int i = 1; i <= n; i++) { k = read(); if (k) x[sum1++] = k; } for (int i = 1; i <= n; i++) { k = read(); if (k) y[sum2++] = k; } int now = sum1 - 1; for (int i = 0; i < now; i++) x[sum1++] = x[i]; for (int i = 1; i < sum2; i++) { int j = f[i]; while (j && y[i] != y[j]) j = f[j]; f[i + 1] = (y[i] == y[j]) ? f[j] + 1 : 0; } int j = 0; for (int i = 0; i < sum1; i++) { while (j && x[i] != y[j]) j = f[j]; if (x[i] == y[j]) j++; if (j == sum2) break; } if (j == sum2) printf( YES n ); else printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long LLINF = 9223372036854775807LL; const int INF = 2147483647; const int MOD = 1000000007; const double eps = 1e-7; const double PI = acos(-1.0); int dr[] = {1, 0, -1, 0, -1, 1, 1, -1}; int dc[] = {0, -1, 0, 1, 1, 1, -1, -1}; int m; pair<int, int> arr[100005]; vector<int> v; bool done[100005]; bool cf(pair<int, int> a, pair<int, int> b) { return a.first > b.first; } int main() { scanf( %d , &m); for (int(i) = (1); (i) <= (m); (i)++) scanf( %d , &arr[i].first), arr[i].second = i; sort(arr + 1, arr + 1 + m); int cur = arr[1].first; done[arr[1].second] = true; v.push_back(cur); for (int(i) = (2); (i) <= (m); (i)++) { if (arr[i].first > cur) { cur = arr[i].first; done[arr[i].second] = true; v.push_back(cur); } } sort(arr + 1, arr + 1 + m, cf); for (int(i) = (1); (i) <= (m); (i)++) { if (arr[i].first < cur && !done[arr[i].second]) { cur = arr[i].first; v.push_back(cur); } } cout << (int)(v.size()) << endl; for (int(i) = (0); (i) < ((int)(v.size())); (i)++) printf( %d , v[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long t[505]; long long p[505][505]; long long dp[505][505]; const long long oo = 4557430888798830399LL; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n, m, k; cin >> n >> m >> k; vector<string> s(n); for (auto &i : s) cin >> i; memset(p, 63, sizeof p); memset(dp, 63, sizeof dp); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) t[j + 1] = t[j] + s[i][j] - 0 ; for (int j = 1; j <= m; ++j) if (s[i][j - 1] == 1 ) for (int l = j; l <= m; ++l) if (s[i][l - 1] == 1 ) p[i][t[m] - t[l] + t[j - 1]] = min(p[i][t[m] - t[l] + t[j - 1]], (long long)l - j + 1); p[i][t[m]] = 0; } dp[0][0] = 0; for (int i = 0; i < n; ++i) for (int j = 0; j <= k; ++j) if (dp[i][j] != oo) for (int l = k - j; l >= 0; --l) if (p[i][l] != oo) dp[i + 1][j + l] = min(dp[i + 1][j + l], dp[i][j] + p[i][l]); long long ans = oo; for (int i = 0; i <= k; ++i) ans = min(ans, dp[n][i]); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7; const long long mod = 998244353; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); int n, m, k; vector<int> a; int f(int off) { int q = 0; int left = m - 1; int at_w = k; for (int i = off; i < n; i++) { if (at_w - a[i] >= 0) { at_w -= a[i]; q++; } else { if (left == 0) break; at_w = k - a[i]; q++; left--; } } return q == (n - off); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> k; a.resize(n); { for (auto &_re : a) cin >> _re; }; int l = 0, r = n, mid; int ans = 0; while (l <= r) { mid = l + r >> 1; if (f(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } cout << n - ans << n ; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.