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`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Ethernet CRC-32 (derived from easics.com generator)
Original license:
Copyright (C) 1999-2008 Easics NV.
This source file may be used and distributed without restriction
provided that this copyright statement is not removed from the file
and that any derivative work contains the original copyright notice
and the associated disclaimer.
THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Purpose : synthesizable CRC function
* polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
* data width: 8
Info :
http://www.easics.com
*/
module CRC32_Ethernet(
input wire clk,
input wire reset,
input wire update,
input wire[7:0] din,
output wire[31:0] crc_flipped);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O shuffling
reg[31:0] crc = 0;
wire[31:0] crc_not = ~crc;
assign crc_flipped =
{
crc_not[24], crc_not[25], crc_not[26], crc_not[27],
crc_not[28], crc_not[29], crc_not[30], crc_not[31],
crc_not[16], crc_not[17], crc_not[18], crc_not[19],
crc_not[20], crc_not[21], crc_not[22], crc_not[23],
crc_not[8], crc_not[9], crc_not[10], crc_not[11],
crc_not[12], crc_not[13], crc_not[14], crc_not[15],
crc_not[0], crc_not[1], crc_not[2], crc_not[3],
crc_not[4], crc_not[5], crc_not[6], crc_not[7]
};
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual CRC function
wire[7:0] din_flipped =
{
din[0], din[1], din[2], din[3],
din[4], din[5], din[6], din[7]
};
always @(posedge clk) begin
if(reset)
crc <= 'hffffffff;
if(update) begin
crc[0] <= din_flipped[6] ^ din_flipped[0] ^ crc[24] ^ crc[30];
crc[1] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[1] ^ din_flipped[0] ^ crc[24] ^ crc[25] ^ crc[30] ^ crc[31];
crc[2] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[2] ^ din_flipped[1] ^ din_flipped[0] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[30] ^ crc[31];
crc[3] <= din_flipped[7] ^ din_flipped[3] ^ din_flipped[2] ^ din_flipped[1] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[31];
crc[4] <= din_flipped[6] ^ din_flipped[4] ^ din_flipped[3] ^ din_flipped[2] ^ din_flipped[0] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30];
crc[5] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[5] ^ din_flipped[4] ^ din_flipped[3] ^ din_flipped[1] ^ din_flipped[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31];
crc[6] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[5] ^ din_flipped[4] ^ din_flipped[2] ^ din_flipped[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30] ^ crc[31];
crc[7] <= din_flipped[7] ^ din_flipped[5] ^ din_flipped[3] ^ din_flipped[2] ^ din_flipped[0] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[31];
crc[8] <= din_flipped[4] ^ din_flipped[3] ^ din_flipped[1] ^ din_flipped[0] ^ crc[0] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28];
crc[9] <= din_flipped[5] ^ din_flipped[4] ^ din_flipped[2] ^ din_flipped[1] ^ crc[1] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29];
crc[10] <= din_flipped[5] ^ din_flipped[3] ^ din_flipped[2] ^ din_flipped[0] ^ crc[2] ^ crc[24] ^ crc[26] ^ crc[27] ^ crc[29];
crc[11] <= din_flipped[4] ^ din_flipped[3] ^ din_flipped[1] ^ din_flipped[0] ^ crc[3] ^ crc[24] ^ crc[25] ^ crc[27] ^ crc[28];
crc[12] <= din_flipped[6] ^ din_flipped[5] ^ din_flipped[4] ^ din_flipped[2] ^ din_flipped[1] ^ din_flipped[0] ^ crc[4] ^ crc[24] ^ crc[25] ^ crc[26] ^ crc[28] ^ crc[29] ^ crc[30];
crc[13] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[5] ^ din_flipped[3] ^ din_flipped[2] ^ din_flipped[1] ^ crc[5] ^ crc[25] ^ crc[26] ^ crc[27] ^ crc[29] ^ crc[30] ^ crc[31];
crc[14] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[4] ^ din_flipped[3] ^ din_flipped[2] ^ crc[6] ^ crc[26] ^ crc[27] ^ crc[28] ^ crc[30] ^ crc[31];
crc[15] <= din_flipped[7] ^ din_flipped[5] ^ din_flipped[4] ^ din_flipped[3] ^ crc[7] ^ crc[27] ^ crc[28] ^ crc[29] ^ crc[31];
crc[16] <= din_flipped[5] ^ din_flipped[4] ^ din_flipped[0] ^ crc[8] ^ crc[24] ^ crc[28] ^ crc[29];
crc[17] <= din_flipped[6] ^ din_flipped[5] ^ din_flipped[1] ^ crc[9] ^ crc[25] ^ crc[29] ^ crc[30];
crc[18] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[2] ^ crc[10] ^ crc[26] ^ crc[30] ^ crc[31];
crc[19] <= din_flipped[7] ^ din_flipped[3] ^ crc[11] ^ crc[27] ^ crc[31];
crc[20] <= din_flipped[4] ^ crc[12] ^ crc[28];
crc[21] <= din_flipped[5] ^ crc[13] ^ crc[29];
crc[22] <= din_flipped[0] ^ crc[14] ^ crc[24];
crc[23] <= din_flipped[6] ^ din_flipped[1] ^ din_flipped[0] ^ crc[15] ^ crc[24] ^ crc[25] ^ crc[30];
crc[24] <= din_flipped[7] ^ din_flipped[2] ^ din_flipped[1] ^ crc[16] ^ crc[25] ^ crc[26] ^ crc[31];
crc[25] <= din_flipped[3] ^ din_flipped[2] ^ crc[17] ^ crc[26] ^ crc[27];
crc[26] <= din_flipped[6] ^ din_flipped[4] ^ din_flipped[3] ^ din_flipped[0] ^ crc[18] ^ crc[24] ^ crc[27] ^ crc[28] ^ crc[30];
crc[27] <= din_flipped[7] ^ din_flipped[5] ^ din_flipped[4] ^ din_flipped[1] ^ crc[19] ^ crc[25] ^ crc[28] ^ crc[29] ^ crc[31];
crc[28] <= din_flipped[6] ^ din_flipped[5] ^ din_flipped[2] ^ crc[20] ^ crc[26] ^ crc[29] ^ crc[30];
crc[29] <= din_flipped[7] ^ din_flipped[6] ^ din_flipped[3] ^ crc[21] ^ crc[27] ^ crc[30] ^ crc[31];
crc[30] <= din_flipped[7] ^ din_flipped[4] ^ crc[22] ^ crc[28] ^ crc[31];
crc[31] <= din_flipped[5] ^ crc[23] ^ crc[29];
end
end
endmodule
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_spi_sync (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 100000 + 10; int leaf[M]; vector<int> adj[M]; int childnum[M]; void dfs(int cur, int par) { for (int i = 0; i < adj[cur].size(); i++) { int nxt = adj[cur][i]; if (nxt != par) { childnum[cur]++; dfs(nxt, cur); } } } bool ok = true; long long int coef[M]; long long int thres = 1e16 + 10; void dfs1(int cur, int par) { coef[cur] = childnum[par] * coef[par]; if (coef[cur] > thres) { ok = false; return; } for (int i = 0; i < adj[cur].size(); i++) { int nxt = adj[cur][i]; if (nxt != par) { dfs1(nxt, cur); } } } vector<int> leafnode; long long int gcd(long long int x, long long int y) { return y == 0 ? x : gcd(y, x % y); } int main() { int n; cin >> n; long long int s = 0; for (int i = 1; i <= n; i++) { cin >> leaf[i]; s = s + leaf[i]; } for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } for (int i = 2; i <= n; i++) { if (adj[i].size() == 1) { leafnode.push_back(i); } } dfs(1, 0); coef[0] = 1; childnum[0] = 1; dfs1(1, 0); long long int minv = -1; for (int i = 0; i < leafnode.size(); i++) { int curleaf = leafnode[i]; long long int x = leaf[curleaf]; long long int k = coef[curleaf]; long long int v = k * x; if (minv == -1) { minv = v; } else { minv = min(minv, v); } } if (!ok) { cout << s << endl; } else { long long int lcm = 1; for (int i = 0; i < leafnode.size(); i++) { int curleaf = leafnode[i]; long long int k = coef[curleaf]; long long int d = gcd(lcm, k); lcm = lcm * k / d; if (lcm > minv) { ok = false; break; } } if (!ok) { cout << s << endl; } else { lcm = minv / lcm * lcm; long long int ans = 0; for (int i = 0; i < leafnode.size(); i++) { int curleaf = leafnode[i]; long long int k = coef[curleaf]; long long int x = lcm / k; long long int val = leaf[curleaf] - x; ans = ans + val; } cout << ans << endl; } } return 0; }
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult_21_coeff_26561.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.3 Build 178 02/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_21_coeff_26561 (
clken,
clock,
dataa,
result);
input clken;
input clock;
input [20:0] dataa;
output [41:0] result;
wire [41:0] sub_wire0;
wire [20:0] sub_wire1 = 21'd26561;
wire [41:0] result = sub_wire0[41:0];
lpm_mult lpm_mult_component (
.clock (clock),
.datab (sub_wire1),
.clken (clken),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=NO,INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=1",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 21,
lpm_mult_component.lpm_widthb = 21,
lpm_mult_component.lpm_widthp = 42;
endmodule
|
module BitonicSortX4 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3
);
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
// half-clean
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(a0),
.b(a2),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(a1),
.b(a3),
.sort0(sort1_0),
.sort1(sort1_1)
);
// divide sort
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sort0_0),
.b(sort1_0),
.sort0(sort0),
.sort1(sort1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sort0_1),
.b(sort1_1),
.sort0(sort2),
.sort1(sort3)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005]; int w[100005]; int x[100005]; int main() { int n; scanf( %d , &n); int i; for (i = 0; n > i; i++) { scanf( %d , &a[i]); } w[0] = a[0]; for (i = 1; n > i; i++) { w[i] = w[i - 1] + a[i]; } int k; string s; cin >> s; unsigned int max = 0; unsigned int sum = 0; for (i = 0; n > i; i++) { if (s[i] == 1 ) { sum += a[i]; } x[i] = sum; } int temp; max = sum; for (i = 1; n > i; i++) { if (s[i] == 1 ) { temp = sum - x[i] + w[i - 1]; if (temp > max) { max = temp; } } } printf( %d , max); }
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#include <bits/stdc++.h> using namespace std; long long fact[200005]; long long extgcd(long long a, long long b, long long& x, long long& y) { long long d = a; if (b != 0LL) { d = extgcd(b, a % b, y, x); y -= (a / b) * x; } else { x = 1; y = 0; } return d; } long long mod_inverse(long long a, long long m) { long long x, y; extgcd(a, m, x, y); return (m + x % m) % m; } long long mod_fact(long long n, long long p, long long& e) { e = 0; if (n == 0) return 1; long long res = mod_fact(n / p, p, e); e += n / p; if (n / p % 2 != 0) { return res * (p - fact[n % p]) % p; } return res * fact[n % p] % p; } long long mod_comb(long long n, long long k, long long p) { if (n < 0 || k < 0 || n < k) return 0; long long e1, e2, e3; long long a1 = mod_fact(n, p, e1), a2 = mod_fact(k, p, e2), a3 = mod_fact(n - k, p, e3); if (e1 > e2 + e3) return 0; return a1 * mod_inverse(a2 * a3 % p, p) % p; } long long mod_pow(long long x, long long n) { long long ans = 1; while (n > 0) { if (n & 1) { ans = ans * x % 998244353LL; } x = x * x % 998244353LL; n >>= 1; } return ans; } int n; long long k; int h[200005]; int main(void) { fact[0] = 1; for (long long i = 1; i <= 200000; i++) { fact[i] = fact[i - 1] * i % 998244353LL; } scanf( %d%lld , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &h[i]); } int cur = 0, nxt = 1; long long po = 1; int cnt = 0; for (int i = 0; i < n; i++) { int ans = h[i]; int cans = h[(i + 1) % n]; if (ans == cans) { po = po * k % 998244353LL; } else { cnt++; } } long long ans = 0; long long v1 = 1; for (int i = 0; i < cnt; i++) { int rest = cnt - i; long long v4 = mod_comb(cnt, i, 998244353LL); long long sum = 0; if (rest % 2 == 1) { if (i == cnt) { sum += v1 * mod_pow(2, rest - 1) % 998244353LL; sum %= 998244353LL; } else { sum += v1 * mod_pow(2, rest - 1) % 998244353LL; sum %= 998244353LL; } } else if (rest > 0) { long long v3 = mod_pow(2, rest - 1); long long v5 = mod_comb(rest - 1, rest / 2, 998244353LL); v3 = (v3 - v5 + 998244353LL) % 998244353LL; sum += v1 * v3 % 998244353LL; sum %= 998244353LL; } sum = sum * v4 % 998244353LL; ans += sum; ans %= 998244353LL; v1 = v1 * (k - 2LL) % 998244353LL; } ans = ans * po % 998244353LL; printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; void reset(int& n, int first) { n = n & ~(1 << first); } bool check(int n, int first) { return (bool)(n & (1 << first)); } const int mx = 55; long long inf = 1e18; unsigned long long f[mx], v; int a[mx]; int main() { f[0] = f[1] = 1; int i, j, k, n; for (i = 2; i < mx; i++) f[i] = f[i - 1] + f[i - 2]; while (cin >> n >> v) { int cur = n; for (i = 1; i <= n; i++) a[i] = i; for (i = 1; i <= n; i++) { if (v > f[cur - 1]) { swap(a[i], a[i + 1]); i++; cur -= 2; v -= f[cur + 1]; } else cur--; } for (i = 1; i <= n; i++) printf( %d , a[i]); puts( ); } }
|
// DESCRIPTION: Verilator: System Verilog test of a complete CPU
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
integer clk_count;
testbench testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Drive simulation for 500 clock cycles
// **************************************************************************
initial begin
`ifdef TEST_VERBOSE
$display( "[testbench] - Start of simulation ----------------------- " );
`endif
clk_count = 0;
end
always @( posedge clk ) begin
if (500 == clk_count) begin
$finish ();
end
else begin
clk_count++;
end
end
final begin
`ifdef TEST_VERBOSE
$display( "[testbench] - End of simulation ------------------------- " );
`endif
$write("*-* All Finished *-*\n");
end
endmodule
module testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
// **************************************************************************
// Local parameters
// **************************************************************************
localparam
NUMPADS = $size( pinout );
// **************************************************************************
// Regs and Wires
// **************************************************************************
// **** Pinout ****
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
// **************************************************************************
// Regs and Wires, Automatics
// **************************************************************************
/*AUTOWIRE*/
// **************************************************************************
// Includes (Testbench extensions)
// **************************************************************************
// N/A
// **************************************************************************
// Chip Instance
// **************************************************************************
chip
i_chip
(
/*AUTOINST*/
// Inouts
.pad (pad),
// Inputs
.clk (clk),
.rst (rst));
endmodule // test
// Local Variables:
// verilog-library-directories:("." "t_sv_cpu_code")
// End:
|
`begin_keywords "1364-2005"
module top;
reg passed, in, expect;
integer lp;
wire rand = ∈
wire ror = |in;
wire rxor = ^in;
wire rnand = ~∈
wire rnor = ~|in;
wire rxnor = ~^in;
initial begin
passed = 1'b1;
for (lp=0; lp < 3 ; lp = lp + 1) begin
case (lp)
0: {in,expect} = 2'b00;
1: {in,expect} = 2'b11;
2: {in,expect} = 2'bzx;
3: {in,expect} = 2'bxx;
endcase
#1;
// Check the normal reductions.
if (rand !== expect) begin
$display("FAILED CA reduction & with input %b, expected %b, got %b",
in, expect, rand);
passed = 1'b0;
end
if (ror !== expect) begin
$display("FAILED CA reduction | with input %b, expected %b, got %b",
in, expect, ror);
passed = 1'b0;
end
if (rxor !== expect) begin
$display("FAILED CA reduction ^ with input %b, expected %b, got %b",
in, expect, rxor);
passed = 1'b0;
end
// Check the inverted reductions.
if (rnand !== ~expect) begin
$display("FAILED CA reduction ~& with input %b, expected %b, got %b",
in, ~expect, rnand);
passed = 1'b0;
end
if (rnor !== ~expect) begin
$display("FAILED CA reduction ~| with input %b, expected %b, got %b",
in, ~expect, rnor);
passed = 1'b0;
end
if (rxnor !== ~expect) begin
$display("FAILED CA reduction ~^ with input %b, expected %b, got %b",
in, ~expect, rxnor);
passed = 1'b0;
end
end
if (passed) $display("PASSED");
end
endmodule
`end_keywords
|
#include <bits/stdc++.h> using namespace std; int l[210000], r[210000]; vector<pair<int, int> > v; int n, m, k; int mp[1000]; int lbit[1000]; int dp[210000][300]; int msk[210000]; int main() { for (int i = 0; i < 210000; i++) for (int j = 0; j < 300; j++) dp[i][j] = -0x3f3f3f3f; dp[0][0] = 0; for (int i = 0; i < (1 << 9); i++) { int cnt = 0; for (int j = 0; j < 8; j++) if (i & (1 << j)) { mp[i]++; } else if (lbit[i] == 0) { lbit[i] = (1 << j); } } cin >> n >> m >> k; for (int i = 1; i <= n; i++) { scanf( %d%d , &l[i], &r[i]); v.push_back({l[i] - 1, i}); v.push_back({r[i], -i}); } sort(v.begin(), v.end()); int tim = 0; int posmsk = 0; int ans = 0; int lst = 0; for (auto p : v) { tim++; if (p.second < 0) { for (int j = 0; j < (1 << 8); j++) if (j & msk[-p.second]) dp[tim][j ^ msk[-p.second]] = max(dp[tim][j ^ msk[-p.second]], dp[tim - 1][j] + max(0, p.first - lst) * (mp[j] & 1)); else { dp[tim][j] = max(dp[tim][j], dp[tim - 1][j] + (p.first - lst) * (mp[j] & 1)); } posmsk ^= msk[-p.second]; } else { msk[p.second] = lbit[posmsk]; posmsk ^= msk[p.second]; for (int j = 0; j < (1 << 8); j++) if ((j & msk[p.second]) == 0) { dp[tim][j ^ msk[p.second]] = max(dp[tim][j ^ msk[p.second]], dp[tim - 1][j] + (max(0, p.first - lst)) * (mp[j] & 1)); dp[tim][j] = max(dp[tim][j], dp[tim - 1][j] + (p.first - lst) * (mp[j] & 1)); } } lst = p.first; } cout << dp[2 * n][0]; return ~~(0 ^ 0 ^ 0); }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) #pragma GCC optimize( -ffloat-store ) const long long INF = 9e18; const long long N = 998244353; const double eps = 1e-9; const auto start_time = std::chrono::high_resolution_clock::now(); void zark() {} void solve() { long long n, k; cin >> n >> k; vector<long long> a(n), b(n); for (long long i = (0); i < (n); i++) cin >> a[i]; for (long long i = (0); i < (n); i++) cin >> b[i]; sort((a).begin(), (a).end()); sort((b).begin(), (b).end()); long long s = 0; long long i = 0, j = n - 1, cnt = 0; while (cnt < k && i < n && j >= 0) { if (a[i] < b[j]) s += b[j], cnt++, j--, i++; else break; } for (long long ii = i; ii < n; ii++) s += a[ii]; cout << s << n ; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) solve(); zark(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void read(T& x) { x = 0; T f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) f = (ch == - ? -1 : 1), ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 48, ch = getchar(); x *= f; } template <class T, class... Args> void read(T& x, Args&... args) { read(x), read(args...); } template <class T> void write(T x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } const int MAXN = 2E5 + 5; const int MOD = 1E9 + 7; long long n, num; double p; bool check(long long k) { return (-k * k * k + 3 * k * k + k * (4 + 3 * n * n - 9 * n)) * 10000 >= num * n * (n - 1) * (n - 2) * 2; } signed main() { cin >> n >> p; num = llround(p * 10000); int l = 0, r = n, ans = 0; while (l <= r) { int mid = l + r >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; multiset<int, greater<int> > s1; multiset<int> s2; int bs1, bs2, n, a[500500], b[500500], ct, nomb[500500], cr, noma[500500]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); noma[a[i]] = i; } for (int i = 0; i < n; i++) { scanf( %d , &b[i]); nomb[b[i]] = i; } s1.clear(); s2.clear(); bs1 = 0; bs2 = 0; for (int i = 0; i < n; i++) { ct = nomb[a[i]] - i; if (ct <= 0) s1.insert(ct); else s2.insert(ct); } for (int i = 0; i < n; i++) { cr = 1000000000; if (!s1.empty()) { int qt = *s1.begin(); cr = min(cr, (-(qt - bs1))); } if (!s2.empty()) cr = min(cr, (*s2.begin()) - bs2); printf( %d n , cr); ct = 0 - noma[b[i]] + bs1; s1.erase(s1.find(ct)); ct = n - 1 - noma[b[i]] + bs2 + 1; s2.insert(ct); bs1++; bs2++; while ((!s2.empty()) && (*s2.begin() == bs2)) { s2.erase(s2.begin()); s1.insert(0 + bs1); } } }
|
#include <bits/stdc++.h> using namespace std; int n, k, mod = 1000000007; bool ok[1005]; char a[1005], b[1005]; int cnt[2][1005], tp, tn; int solve() { scanf( %s , a); scanf( %s , b); n = strlen(a); scanf( %d , &k); int cg = 0; for (int i = 0; i < n; i++) { ok[i] = true; for (int j = 0; j < n && ok[i]; j++) if (a[j] != b[(i + j) % n]) ok[i] = false; cg += ok[i]; } if (!cg) return 0; cnt[1][0] = 1; tp = 1; for (int s = 0; s < k; s++) { tn = 0; int p = (s + 1) % 2, c = s % 2; for (int i = 0; i < n; i++) { cnt[c][i] = (tp + mod - cnt[p][i]) % mod; tn = (tn + cnt[c][i]) % mod; } tp = tn; } int re = 0; for (int i = 0; i < n; i++) if (ok[i]) { re = (re + cnt[(k + 1) % 2][i]) % mod; } return re; } int main() { printf( %d n , solve()); }
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* vending machine
*/
// Import the modules that will be tested for in this testbench
`include "ee577bHw2q1a.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q1.f +gui
module tbfsm();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the couunter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire disp_Q,disp_D,disp_N,disp_P,done;
// Declare "reg" signals: inputs to the DUT
reg [6:0] money,price;
reg start,clk,reset;
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
fsmVendingMachine fsm (
// instance_name(signal name),
// Signal name can be the same as the instance name
disp_Q,disp_D,disp_N,disp_P,done,money,price,start,clk,reset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
money = 7'd75;
price = 7'd64;
#60
// @ t=0,
money = 7'd75;
price = 7'd64;
reset = 0;
start = 1;
// @ t=40
#40
start = 0;
// @ t=240;
#200
money = 7'd100;
price = 7'd54;
reset = 0;
start = 1;
// @ t=280
#40
start = 0;
// @ t=380;
wait (done)
#40
money = 7'd50;
price = 7'd27;
reset = 0;
start = 1;
// @ t=420
#40
start = 0;
// @ t=380;
wait (done)
#40
money = 7'd55;
price = 7'd63;
reset = 0;
start = 1;
// @ t=420
#40
start = 0;
// end simulation
#200
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k; vector<int> E[200020], V; int dis[2][200020]; void solve() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= k; i++) { int x; scanf( %d , &x); V.push_back(x); } for (int i = 0; i < (m); i++) { int x, y; scanf( %d%d , &x, &y); E[x].push_back(y); E[y].push_back(x); } for (int v = 0; v < (2); v++) { int st = (v == 0 ? 1 : n); vector<int> q; auto D = dis[v]; for (int i = 1; i <= n; i++) D[i] = -1; D[st] = 0; q.push_back(st); for (int i = 0; i < ((int)(q).size()); i++) { int t = q[i]; for (int e : E[t]) if (D[e] == -1) { D[e] = D[t] + 1; q.push_back(e); } } } sort((V).begin(), (V).end(), [&](int x, int y) { return dis[0][x] > dis[0][y]; }); int mx = -1e9, ans = 0; for (int i = 0; i + 1 < (int)(V).size(); i++) { if (dis[0][V[i]] == dis[0][V[i + 1]]) { printf( %d n , dis[0][n]); return; } } for (int i = 0; i < ((int)(V).size()); i++) { int u = V[i]; int val = min({dis[0][n], dis[0][u] + dis[1][u], dis[0][u] + 1 + mx}); ans = max(ans, val); mx = max(mx, dis[1][u]); } printf( %d n , ans); } int main() { int T = 1; for (int t = 1; t <= T; t++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, cnt; int po[999994], cr[14]; map<int, int> mert; void calc(int L) { int x = 0; for (int i = 1; i <= L; i++) x = x * 10 + cr[i]; if (x == 0) return; else if (!mert.count(x)) { mert[x] = 1; po[++cnt] = x; } } void dfs(int cur, int limit) { if (cur > limit) calc(limit); else for (int i = 0; i <= 1; i++) { cr[cur] = i; dfs(cur + 1, limit); } } int main() { cin >> n; for (int i = 1; i <= 10; i++) dfs(1, i); sort(po + 1, po + cnt + 1); int i = 0; for (i = 1; po[i] <= n; i++) ; cout << i - 1 << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef struct packed {
bit b9;
byte b1;
bit b0;
} pack_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
pack_t in;
always @* in = crc[9:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pack_t out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {54'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input pack_t in,
output pack_t out);
always @* begin
out = in;
out.b1 = in.b1 + 1;
out.b0 = 1'b1;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, a[12], b[20], c[5], u[15], vs, hh; string v[2033333]; void add(int o, int s, int k) { if (s > k) return; if (o == 4) { if (k - s > 2) return; if (k - s && b[s] == 0) return; if (k - s == 2 && b[s] * 100 + b[s + 1] * 10 + b[k] >= 256) return; string st = ; for (int i = 1; i <= c[1]; i++) st += char(b[i] + 48); st += . ; for (int i = c[1] + 1; i <= c[1] + c[2]; i++) st += char(b[i] + 48); st += . ; for (int i = c[1] + c[2] + 1; i < s; i++) st += char(b[i] + 48); st += . ; for (int i = s; i <= k; i++) st += char(b[i] + 48); v[++vs] = st; return; } c[o] = 1; add(o + 1, s + 1, k); if (!b[s]) return; c[o] = 2; add(o + 1, s + 2, k); if (b[s] * 100 + b[s + 1] * 10 + b[s + 2] >= 256) return; c[o] = 3; add(o + 1, s + 3, k); } void cty(int k) { for (int i = 1; i <= n; i++) { b[k] = a[i]; if (!u[i]) hh++; u[i]++; if (k >= 2) { do { if (hh != n) break; for (int j = 1; j <= k; j++) b[(k << 1) - j + 1] = b[j]; add(1, 1, k << 1); if (k != 2) { for (int j = 1; j < k; j++) b[(k << 1) - j] = b[j]; add(1, 1, (k << 1) - 1); } } while (0); } if (k < 6) cty(k + 1); u[i]--; if (!u[i]) hh--; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i); cty(1); sort(v + 1, v + vs + 1); printf( %d n , vs); for (int i = 1; i <= vs; i++) { int l = v[i].size(); for (int j = 0; j < l; j++) printf( %c , v[i][j]); printf( n ); } return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_clz32();
reg [31:0] d;
wire [4:0] clz;
pfpu_clz32 dut(
.d(d),
.clz(clz)
);
reg [5:0] i;
reg [7:0] j;
initial begin
$display("Testing clz32 module");
for (j=0;j<100;j=j+1) begin
for (i=0;i<32;i=i+1) begin
d = (32'h80000000 >> i);
if(i < 31) d = d + ($random % (32'h40000000 >> i));
#1 $display("%b -> %d", d, clz);
if(i[4:0] != clz) begin
$display("***** TEST FAILED *****");
$display("Expected %d, got %d", i, clz);
$finish;
end
end
end
d = 32'h00000000;
#1 $display("%b -> %d", d, clz);
if(5'd31 != clz) begin
$display("***** TEST FAILED *****");
$display("Expected 31, got %d", i, clz);
$finish;
end
$display("***** TEST PASSED *****");
$finish;
end
endmodule
|
// This is a component of pluto_step_spi, a stepper driver for linuxcnc over SPI.
// based on the main.v from Jeff Epler <>
// Copyright 2013 by Matsche <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//**********************************************************************
module rpi_fpga_stepper(clk, SCK, MOSI, MISO, SSEL, nRESET, LED, nConfig, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig = 1'bZ;
output LED;
input [15:0] din;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
reg Spolarity;
reg[13:0] real_dout; output [13:0] dout = do_tristate ? 14'bZ : real_dout;
wire[3:0] real_step; output [3:0] step = do_tristate ? 4'bZ : real_step ^ {4{Spolarity}};
wire[3:0] real_dir; output [3:0] dir = do_tristate ? 4'bZ : real_dir;
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
//**********************************************************************
// SPI zeugs
// synchronizing the handshakes
//
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
wire SCK_high = SCKr[1]; // SCK is high
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
wire MOSI_data = MOSI;
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
reg byte_received; // high when 8 bit has been received
reg [4:0] spibytecnt;
reg [7:0] data_recvd;
reg [7:0] data_sent;
reg [7:0] data_outbuf;
always @(posedge clk) begin
if(SSEL_startmessage) begin
//data_sent <= data_outbuf;
bitcnt <= 3'b000;
spibytecnt <= 5'b00000;
end
if(SSEL_active) begin
if(SCK_risingedge) begin
data_recvd <= {data_recvd[6:0], MOSI_data};
bitcnt <= bitcnt + 3'b001;
if(bitcnt==3'b000)
data_sent <= data_outbuf;
end
else if(SCK_fallingedge) begin
data_sent <= {data_sent[6:0], 1'b0};
if(bitcnt==3'b000) begin
spibytecnt <= spibytecnt + 5'b00001;
end
end
byte_received <= SCK_risingedge && (bitcnt==3'b111);
end
end
assign MISO = data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
reg [7:0] data_inbuf;
always @(posedge clk) begin
if(SSEL_active) begin
//------------------------------------------------- word 0
if(spibytecnt == 5'b00000) begin // 0
data_outbuf <= pos0[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel0[7:0]
end
else if(spibytecnt == 5'b00001) begin // 1
data_outbuf <= pos0[15:8];
if(byte_received)
vel0 <= {data_recvd,data_inbuf}; //vel0
end
else if(spibytecnt == 5'b00010) begin // 2
data_outbuf <= pos0[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel1[7:0]
end
else if(spibytecnt == 5'b00011) begin // 3
data_outbuf <= 8'b0;
if(byte_received)
vel1 <= {data_recvd,data_inbuf}; //vel1
end
//------------------------------------------------- word 1
else if(spibytecnt == 5'b00100) begin // 4
data_outbuf <= pos1[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel2[7:0]
end
else if(spibytecnt == 5'b00101) begin // 5
data_outbuf <= pos1[15:8];
if(byte_received)
vel2 <= {data_recvd,data_inbuf}; //vel2
end
else if(spibytecnt == 5'b00110) begin // 6
data_outbuf <= pos1[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel3[7:0]
end
else if(spibytecnt == 5'b00111) begin // 7
data_outbuf <= 8'b0;
if(byte_received)
vel3 <= {data_recvd,data_inbuf}; //vel3
end
//------------------------------------------------- word 2
else if(spibytecnt == 5'b01000) begin // 8
data_outbuf <= pos2[7:0];
if(byte_received)
data_inbuf <= data_recvd; //real_dout[7:0]
end
else if(spibytecnt == 5'b01001) begin // 9
data_outbuf <= pos2[15:8];
if(byte_received) begin
real_dout <= {data_recvd[5:0],data_inbuf}; //real_dout
end
end
else if(spibytecnt == 5'b01010) begin // 10
data_outbuf <= pos2[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd;
end
else if(spibytecnt == 5'b01011) begin // 11
data_outbuf <= 8'b0;
if(byte_received) begin
tap <= data_recvd[7:6];
steptime <= data_recvd[T-1:0];
Spolarity <= data_inbuf[7];
dirtime <= data_inbuf[T-1:0];
end
end
//------------------------------------------------- word 3
else if(spibytecnt == 5'b01100) data_outbuf <= pos3[7:0];
else if(spibytecnt == 5'b01101) data_outbuf <= pos3[15:8];
else if(spibytecnt == 5'b01110) data_outbuf <= pos3[W+F-1:16];
else if(spibytecnt == 5'b01111) data_outbuf <= 8'b0;
//------------------------------------------------- word 4
else if(spibytecnt == 5'b10000) data_outbuf <= din[7:0];
else if(spibytecnt == 5'b10001) data_outbuf <= din[15:8];
else if(spibytecnt == 5'b10010) data_outbuf <= 8'b0;
else if(spibytecnt == 5'b10011) data_outbuf <= 8'b0;
else data_outbuf <= spibytecnt;
end
end
assign LED = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign do_enable_wdt = data_recvd[6] & (spibytecnt == 5'b01001) & byte_received;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)(2e9); const long long INF = (long long)(5e18); const int N = 305; set<pair<int, int> > st; int n, m; int bl[N * N], a[N][N], vis[N][N]; int ans[N][N]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &a[i][j]); for (int i = 1; i <= n; i++) { int mx = 0; for (int j = 1; j <= m; j++) mx = max(mx, a[i][j]); st.insert(make_pair(mx, 1)); bl[mx] = 1; } for (int j = 1; j <= m; j++) { int mx = 0; for (int i = 1; i <= n; i++) mx = max(mx, a[i][j]); st.insert(make_pair(mx, -1)); bl[mx] = 1; } int hang = 1, lie = 1, now = 1; while (!st.empty()) { pair<int, int> u = *st.begin(); st.erase(u); pair<int, int> tmp = *st.begin(); if (tmp.first == u.first) { st.erase(tmp); u.second = 2; } vector<int> v; ans[hang][lie] = u.first; if (u.second == 1) { v.clear(); for (int i = lie + 1; i <= m; i++) { while (bl[now]) now++; v.push_back(now); now++; } for (int i = m, j = 0; i >= lie + 1; i--) { ans[hang][i] = v[j]; j++; } hang++; } else if (u.second == -1) { v.clear(); for (int i = hang + 1; i <= n; i++) { while (bl[now]) now++; v.push_back(now); now++; } for (int i = n, j = 0; i >= hang + 1; i--) { ans[i][lie] = v[j]; j++; } lie++; } else { v.clear(); for (int i = lie + 1; i <= m; i++) { while (bl[now]) now++; v.push_back(now); now++; } for (int i = m, j = 0; i >= lie + 1; i--) { ans[hang][i] = v[j]; j++; } v.clear(); for (int i = hang + 1; i <= n; i++) { while (bl[now]) now++; v.push_back(now); now++; } for (int i = n, j = 0; i >= hang + 1; i--) { ans[i][lie] = v[j]; j++; } lie++; hang++; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) printf( %d , ans[i][j]); puts( ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool grid[3][10004]; int n; long long dp[10004][8]; long long calc(int i, int mask) { int mask2 = 0; if (grid[0][i]) mask2 |= 1; if (grid[1][i]) mask2 |= 2; if (grid[2][i]) mask2 |= 4; if ((mask & mask2) != 0) { return 0; } mask |= mask2; long long ret = dp[i][mask]; if (ret != -1) { return ret; } if (i == n - 1) { if (mask == 1 || mask == 4 || mask == 7) { return 1; } else return 0; } switch (mask) { case 0: ret = calc(i + 1, 4); ret += calc(i + 1, 1); ret += calc(i + 1, 7); ret %= 1000000007; break; case 1: ret = calc(i + 1, 6); ret += calc(i + 1, 0); ret %= 1000000007; break; case 2: ret = calc(i + 1, 5); break; case 3: ret = calc(i + 1, 4); break; case 4: ret = calc(i + 1, 3); ret += calc(i + 1, 0); ret %= 1000000007; break; case 5: ret = calc(i + 1, 2); break; case 6: ret = calc(i + 1, 1); break; case 7: ret = calc(i + 1, 0); break; default: break; } dp[i][mask] = ret; return ret; } int main() { cin >> n; string a, b, c; cin >> a >> b >> c; memset(grid, true, sizeof grid); memset(dp, -1, sizeof dp); for (int i = 0; i < n; i++) { if (a[i] == . ) { grid[0][i] = false; } } for (int i = 0; i < n; i++) { if (b[i] == . ) { grid[1][i] = false; } } for (int i = 0; i < n; i++) { if (c[i] == . ) { grid[2][i] = false; } } if (a.find( O ) == string::npos && c.find( O ) == string::npos && b.find( O ) != 0 && b.find( O ) != n - 1) { long long x = calc(0, 0); int p = b.find( O ); memset(dp, -1, sizeof dp); grid[1][p - 1] = true; grid[2][p - 1] = true; grid[0][p + 1] = true; grid[1][p + 1] = true; long long y = calc(0, 0); grid[0][p - 1] = true; grid[2][p - 1] = false; grid[0][p + 1] = false; grid[2][p + 1] = true; memset(dp, -1, sizeof(dp)); long long z = calc(0, 0); cout << (x - y - z + 1000000007 + 1000000007) % 1000000007 << endl; } else { cout << calc(0, 0) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, char c) { vector<string> v; stringstream second(s); string x; while (getline(second, x, c)) v.emplace_back(x); return move(v); } template <typename T, typename... Args> inline string arrStr(T arr, int n) { stringstream s; s << [ ; for (int i = 0; i < n - 1; i++) s << arr[i] << , ; s << arr[n - 1] << ] ; return s.str(); } inline void __evars_begin(int line) { cerr << # << line << : ; } template <typename T> inline void __evars_out_var(vector<T> val) { cerr << arrStr(val, val.size()); } template <typename T> inline void __evars_out_var(T* val) { cerr << arrStr(val, 10); } template <typename T> inline void __evars_out_var(T val) { cerr << val; } inline void __evars(vector<string>::iterator it) { cerr << n ; } template <typename T, typename... Args> inline void __evars(vector<string>::iterator it, T a, Args... args) { cerr << it->substr((*it)[0] == , it->length()) << = ; __evars_out_var(a); cerr << ; ; __evars(++it, args...); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int dx[8] = {1, -1, 0, 0, 1, 1, -1, -1}; int dy[8] = {0, 0, -1, 1, 2, -2, 2, -2}; int myrandom(int i) { return std::rand() % i; } const int MAX = 200010; const unsigned long long inf = 1000000007; int ans = 0, maxi = 0; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m; cin >> n >> m; long long x, k, y; cin >> x >> k >> y; vector<long long> v(n), t(m); for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { cin >> v[i]; } for (__typeof(m) j = (0) - ((0) > (m)); j != (m) - ((0) > (m)); j += 1 - 2 * ((0) > (m))) { cin >> t[j]; } vector<long long> vis(n, 0); int i = 0, j = 0, cnt = 0; while (i < n && j < m) { if (v[i] == t[j]) { vis[i] = 1; i++; j++; cnt++; } else { i++; } } if (cnt != m) { cout << -1 << n ; return 0; } i = 0; long long ans = 0; while (i < n) { while (i < n && vis[i] == 1) { i++; } if (i == n) break; int l = i; vector<long long> temp; while (i < n && vis[i] == 0) { temp.push_back(v[i]); i++; } sort((temp).begin(), (temp).end()); if (y * k > x) { if ((int)temp.size() >= k) { ans += ((long long)temp.size() % k) * y; ans += ((long long)temp.size() / k) * x; } else { long long left = l - 1 >= 0 ? v[l - 1] : 0; long long right = i < n ? v[i] : 0; if (temp.back() < max(left, right)) { ans += (long long)temp.size() * y; } else { cout << -1 << n ; return 0; } } } else { long long left = l - 1 >= 0 ? v[l - 1] : 0; long long right = i < n ? v[i] : 0; if ((long long)temp.size() >= k) { if (temp.back() < max(left, right)) { ans += (long long)temp.size() * y; } else { ans += ((long long)temp.size() - k) * y + x; } } else { if (temp.back() < max(left, right)) { ans += (long long)temp.size() * y; } else { cout << -1 << n ; return 0; } } } } cout << ans << n ; }
|
#define _CRT_SECURE_NO_WARNINGS #include <iostream> #include <vector> #include <algorithm> #include <string> #include <fstream> #include <set> #include <deque> #include <math.h> #include <iomanip> #define ll long long #define ld long double using namespace std; int all = 0; int price = 0; void dfs(int u, vector<int>& used, vector<int> &col, vector<vector<int>>& graph) { all++; if (used[u] != col[u]) { price++; } for (int v : graph[u]) { if (used[v] == -1) { used[v] = 1 - used[u]; dfs(v, used, col, graph); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); //freopen( input.txt , r , stdin); //freopen( output.txt , w , stdout); int n; cin >> n; vector<int> col(n); vector<pair<int, int>> arr(n); vector<int> L(2 * n); for (int i = 0; i < 2 * n; ++i) { L[i] = -1; } for (int i = 0; i < n; ++i) { cin >> arr[i].first >> arr[i].second; if (arr[i].first > arr[i].second) { col[i] = 1; swap(arr[i].first, arr[i].second); } arr[i].first--; arr[i].second--; L[arr[i].first] = i; } for (int i = 0; i < n; ++i) { if (L[i] == -1) { cout << -1 n ; return 0; } } vector<int> r(n); for (int i = 0; i < n; ++i) { r[i] = arr[L[i]].second; } vector<int> mn(n); vector<int> mni(n); vector<int> mx(n); vector<int> mxi(n); mn[0] = r[0]; mni[0] = 0; mx[n - 1] = r[n - 1]; mxi[n - 1] = n - 1; for (int i = 1; i < n; ++i) { if (r[i] < mn[i - 1]) mni[i] = i; else mni[i] = mni[i - 1]; mn[i] = min(mn[i - 1], r[i]); } for (int i = n - 2; i >= 0; --i) { if (r[i] > mx[i + 1]) mxi[i] = i; else mxi[i] = mxi[i + 1]; mx[i] = max(mx[i + 1], r[i]); } for (int i = 1; i < n - 1; ++i) { if (mn[i - 1] < r[i] && r[i] < mx[i + 1]) { cout << -1 n ; return 0; } } //cerr << here n ; vector<vector<int>> graph(n); vector<int> st; for (int i = 0; i < n; ++i) { if (i < n - 1 && r[i] < mx[i + 1]) { st.push_back(i); continue; } if (i > 0 && r[i] > mn[i - 1]) { int useful = st.back(); while (!st.empty()){ if (r[st.back()] < r[i]) { graph[L[st.back()]].push_back(L[i]); graph[L[i]].push_back(L[st.back()]); st.pop_back(); continue; } break; } st.push_back(useful); } } vector<int> used(n); int ans = 0; for (int i = 0; i < n; ++i) { used[i] = -1; } for (int i = 0; i < n; ++i) { if (used[i] == -1) { price = 0; all = 0; used[i] = 0; dfs(i, used, col, graph); ans += min(price, all - price); } } cout << ans << n ; } //*/
|
module spi_engine_interconnect (
input clk,
input resetn,
output m_cmd_valid,
input m_cmd_ready,
output [15:0] m_cmd_data,
output m_sdo_valid,
input m_sdo_ready,
output [7:0] m_sdo_data,
input m_sdi_valid,
output m_sdi_ready,
input [7:0] m_sdi_data,
input m_sync_valid,
output m_sync_ready,
input [7:0] m_sync,
input s0_cmd_valid,
output s0_cmd_ready,
input [15:0] s0_cmd_data,
input s0_sdo_valid,
output s0_sdo_ready,
input [7:0] s0_sdo_data,
output s0_sdi_valid,
input s0_sdi_ready,
output [7:0] s0_sdi_data,
output s0_sync_valid,
input s0_sync_ready,
output [7:0] s0_sync,
input s1_cmd_valid,
output s1_cmd_ready,
input [15:0] s1_cmd_data,
input s1_sdo_valid,
output s1_sdo_ready,
input [7:0] s1_sdo_data,
output s1_sdi_valid,
input s1_sdi_ready,
output [7:0] s1_sdi_data,
output s1_sync_valid,
input s1_sync_ready,
output [7:0] s1_sync
);
reg s_active = 1'b0;
reg idle = 1'b1;
`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
assign s0_sdi_data = m_sdi_data;
assign s1_sdi_data = m_sdi_data;
assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
assign s0_sync = m_sync;
assign s1_sync = m_sync;
assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
always @(posedge clk) begin
if (idle == 1'b1) begin
if (s0_cmd_valid)
s_active <= 1'b0;
else if (s1_cmd_valid)
s_active <= 1'b1;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle = 1'b1;
end else begin
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
idle <= 1'b1;
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
idle <= 1'b0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a >> b; cout << a + b << n ; } return 0; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:48:31 MST 2014
// Date : Wed Feb 11 13:39:15 2015
// Host : austin_workstation_1 running 64-bit Fedora release 20 (Heisenbug)
// Command : write_verilog -force -mode synth_stub
// /home/luis/FIRMWARE/git/vhdl/ip_blocks/sip_check_data/src/async_fifo_align_64in_out/async_fifo_align_64in_out_stub.v
// Design : async_fifo_align_64in_out
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1157-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.4" *)
module async_fifo_align_64in_out(clk, rst, din, wr_en, rd_en, dout, full, empty, valid)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty,valid" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output valid;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> a, b; int n, m, k; string s; int main() { cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> s; a.push_back(s); } for (int i = 0; i < m; ++i) { cin >> s; b.push_back(s); } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (a[i] == b[j]) ++k; } } if (k % 2 == 0) { if (n > m) cout << YES ; else cout << NO ; } else { if (n >= m) cout << YES ; else cout << NO ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<pair<int, int> > vneg, vpos; int n, a, b, neg = 0, pos = 0, sum = 0, ans = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; if (a < 0) { neg++; vneg.push_back({a, b}); } else { pos++; vpos.push_back({a, b}); } sum += b; } sort(vneg.begin(), vneg.end()); sort(vpos.begin(), vpos.end()); if (neg == 0) { cout << vpos[0].second << endl; return 0; } else if (pos == 0) { cout << vneg[vneg.size() - 1].second << endl; return 0; } int mn = min(vneg.size(), vpos.size()); int i, j; for (i = vneg.size() - 1, j = 0; j < mn; i--, j++) { ans = ans + vneg[i].second + vpos[j].second; } if (vneg.size() > vpos.size()) ans += vneg[i].second; if (vneg.size() < vpos.size()) ans += vpos[j].second; cout << ans << endl; }
|
`timescale 1ns/1ns
`define DEFAULT_CYCLE_TIMEOUT 10000
`define INPUT_DELAY 0
`define OUTPUT_DELAY 0
`define CLOCK_PERIOD 10
`define THREADS 4
module core_testbench;
// Process command line options.
reg [31:0] max_cycles;
reg [511:0] ispmfile;
reg [511:0] dspmfile;
reg [511:0] vcdplusfile;
reg [31:0] vcdpluson;
reg [15:0] k;
initial begin
// Read command line arguments.
// Maximum number of cycles.
if(!$value$plusargs("maxcycles=%d", max_cycles))
max_cycles = `DEFAULT_CYCLE_TIMEOUT;
// Where to store VPD trace file.
if($value$plusargs("vcd=%s", vcdplusfile))
$vcdplusfile(vcdplusfile);
// When to turn on VCD tracing.
if(!$value$plusargs("vcdstart=%d", vcdpluson))
vcdpluson = 0;
// Enable warnings about comparisons with X's or Z's.
//$xzcheckon;
end
// Clock signal.
reg clk;
initial begin
clk <= 0;
forever #(`CLOCK_PERIOD/2.0) clk = ~clk;
end
// SPM
reg [31:0] ispm_init [4095:0];
reg [31:0] dspm_init [4095:0];
// Reset signal.
reg reset;
initial begin
reset <= 1'b1;
@(posedge clk);
@(negedge clk);
// Module
//$readmemh(ispmfile, core.imem.ispm);
//$readmemh(dspmfile, core.dmem.dspm);
// Blackbox
$readmemh(ispmfile, ispm_init);
$readmemh(dspmfile, dspm_init);
for(k = 0; k < 4096; k = k + 1) begin
core.imem.BRAMS[0].ispm[k] = ispm_init[k][3:0];
core.imem.BRAMS[1].ispm[k] = ispm_init[k][7:4];
core.imem.BRAMS[2].ispm[k] = ispm_init[k][11:8];
core.imem.BRAMS[3].ispm[k] = ispm_init[k][15:12];
core.imem.BRAMS[4].ispm[k] = ispm_init[k][19:16];
core.imem.BRAMS[5].ispm[k] = ispm_init[k][23:20];
core.imem.BRAMS[6].ispm[k] = ispm_init[k][27:24];
core.imem.BRAMS[7].ispm[k] = ispm_init[k][31:28];
core.dmem.BRAMS[0].dspm[k] = dspm_init[k][3:0];
core.dmem.BRAMS[1].dspm[k] = dspm_init[k][7:4];
core.dmem.BRAMS[2].dspm[k] = dspm_init[k][11:8];
core.dmem.BRAMS[3].dspm[k] = dspm_init[k][15:12];
core.dmem.BRAMS[4].dspm[k] = dspm_init[k][19:16];
core.dmem.BRAMS[5].dspm[k] = dspm_init[k][23:20];
core.dmem.BRAMS[6].dspm[k] = dspm_init[k][27:24];
core.dmem.BRAMS[7].dspm[k] = dspm_init[k][31:28];
end
reset = 1'b0;
end
// FlexPRET core.
wire [31:0] tohost;
Core core
(
.clk (clk),
.reset (reset),
.io_imem_addr(12'b0),
.io_imem_enable(1'b0),
.io_imem_write(1'b0),
.io_imem_data_in(32'b0),
.io_dmem_addr(12'b0),
.io_dmem_enable(1'b0),
.io_dmem_byte_write_3(1'b0),
.io_dmem_byte_write_2(1'b0),
.io_dmem_byte_write_1(1'b0),
.io_dmem_byte_write_0(1'b0),
.io_dmem_data_in(32'b0),
.io_bus_data_out(32'b0),
.io_host_to_host (tohost),
.io_gpio_in_3(1'b0),
.io_gpio_in_2(1'b0),
.io_gpio_in_1(1'b0),
.io_gpio_in_0(1'b0),
.io_int_exts_3(1'b0),
.io_int_exts_2(1'b0),
.io_int_exts_1(1'b0),
.io_int_exts_0(1'b0)
);
// Cycle counter.
reg [31:0] cycle_count = 32'd0;
always @(posedge clk)
begin
// Increment cycle.
cycle_count <= cycle_count + 1;
// Turn on vcdplus?
if(cycle_count == vcdpluson)
$vcdpluson(0);
end
// Check for completion.
always @(posedge clk)
begin
// Timeout.
if(cycle_count > max_cycles)
begin
$display("*** FAILED *** (Max cycles timeout)");
$finish;
end
// Test failed.
if(!reset && tohost[31:30] == 2'b0 && tohost > 1)
begin
$display("*** FAILED *** (test #%d)", tohost);
$finish;
end
// Test passed.
if(!reset && tohost == 1)
begin
$display("*** PASSED ***: %d", tohost);
$finish;
end
end
endmodule
|
`timescale 1ns/10ps
module svinterface_at_top_tb_wrapper;
logic clk;
logic rst;
logic [21:0] outOther;
logic [1:0] sig;
logic [1:0] sig_out;
logic flip;
logic [15:0] passThrough;
integer outfile;
logic interfaceInstanceAtTop_setting;
logic [2:0] interfaceInstanceAtTop_other_setting;
logic [1:0] interfaceInstanceAtTop_mysig_out;
logic [15:0] interfaceInstanceAtTop_passThrough;
TopModule u_dut (
.clk(clk),
.rst(rst),
.outOther(outOther),
.sig(sig),
.flip(flip),
.passThrough(passThrough),
.\interfaceInstanceAtTop.setting (interfaceInstanceAtTop_setting),
.\interfaceInstanceAtTop.other_setting (interfaceInstanceAtTop_other_setting),
.\interfaceInstanceAtTop.mysig_out (interfaceInstanceAtTop_mysig_out),
.\interfaceInstanceAtTop.passThrough (interfaceInstanceAtTop_passThrough),
.sig_out(sig_out)
);
initial begin
clk = 0;
while(1) begin
clk = ~clk;
#50;
end
end
initial begin
outfile = $fopen("output.txt");
rst = 1;
sig = 0;
interfaceInstanceAtTop_setting = 0;
flip = 0;
@(posedge clk);
#(2);
rst = 0;
@(posedge clk);
for(int j=0;j<2;j++) begin
for(int i=0;i<20;i++) begin
#(2);
flip = j;
sig = i;
@(posedge clk);
end
end
$finish;
end
always @(negedge clk) begin
$fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 08 01:04:33 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.v
// Design : system_inverter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_0_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const double eps = 1e-9; const double INF = inf; const double EPS = eps; vector<long long> V; int cmp(long long b, long double d, long long a) { if (d > 2e18) return 1; if (b > a) return 1; if (b == a) return 0; return -1; } int calc(long long n, long long p, long long k) { long double d = (2.0 * k + 1.0) * (k + p - 1ll); long long l = (2ll * k + 1) * (k + p - 1ll); return cmp(l, d, n); } void solve(long long n, long long p) { p = (1ll << p); if (p - 1 > n) return; long long l = 0, r = n + 1; while (r - l > 1) { long long m = (l + r) / 2; (calc(n, p, m) <= 0) ? (l = m) : (r = m); } if (calc(n, p, l) == 0) V.push_back(p * (2ll * l + 1ll)); } int main() { long long n; int i; scanf( %I64d , &n); for (i = 0; i < 60; i++) solve(n, i); sort(V.begin(), V.end()); if (!V.size()) { puts( -1 ); return 0; } for (i = 0; i < (int)V.size(); i++) printf( %I64d n , V[i]); ; return 0; }
|
`timescale 1ns / 1ps
/* verilator lint_off STMTDLY */
module jt12_test;
reg rst;
reg clk;
wire s1_enters, s2_enters, s3_enters, s4_enters;
`include "../common/dump.vh"
initial begin
clk = 0;
forever #10 clk=~clk;
end
reg test_eg;
// envelope configuration
wire [4:0] keycode_III = 5'd10;
reg [4:0] arate; // attack rate
reg [4:0] rate1; // decay rate
reg [4:0] rate2; // sustain rate
wire [3:0] rrate = 4'hf; // release rate
wire [3:0] d1l = 4'd8; // sustain level
wire [1:0] ks_III = 2'd0; // key scale
// SSG operation
reg [3:0] ssg_eg_II;
// envelope operation
reg keyon;
reg keyoff;
// envelope number
wire [6:0] am = 7'd0;
reg [6:0] tl_VII=7'd0;
wire [1:0] ams_VII = 2'd0;
wire amsen_VII = 1'b0;
initial begin
rst = 0;
rate1 = 5'd29;
rate2 = 5'd27;
#5 rst = 1;
#20 rst = 0;
#(1*1000*1000) $finish;
end
integer cycles;
reg [4:0] cnt24;
wire zero = cnt24==5'd0;
reg keyon_done;
always @(posedge clk)
if( rst ) begin
keyon <= 1'b1;
keyoff <= 1'b0;
cycles <= 0;
keyon_done <= 1'b0;
ssg_eg_II <= 4'b0;
end else begin
cycles <= cycles + 1;
if( cycles==100 ) keyon<=1'b0;
if( cycles==110 ) keyoff<=1'b1;
if( cycles==134 ) keyoff<=1'b0;
if( cycles > 10000 ) begin
keyon <= cycles==10559;
ssg_eg_II <= 4'b1110;
end
end
always @(posedge clk)
if( rst ) begin
cnt24 <= 0;
end else begin
if( cnt24 == 5'd23 )
cnt24 <= 5'd0;
else
cnt24 <= cnt24 + 1;
end
always @(*)
if( cycles < 104 )
arate = 5'h1f;
else
arate = cnt24==5'd0 ? 5'd31 : 5'd0;
wire [9:0] eg_IX;
wire pg_rst_III;
jt12_eg uut(
// .test_eg(test_eg),
.rst (rst),
.clk (clk),
.clk_en (1'b1),
.zero (zero),
.eg_stop(1'b0),
// envelope configuration
.keycode_III(keycode_III),
.arate_II (arate), // attack rate
.rate1_II (rate1), // decay rate
.rate2_II (rate2), // sustain rate
.rrate_II (rrate), // release rate
.d1l_I (d1l), // sustain level
.ks_III (ks_III), // key scale
// SSG operation
.ssg_en_II ( cnt24==5'd0 ? ssg_eg_II[3] : 1'h0 ),
.ssg_eg_II ( cnt24==5'd1 ? ssg_eg_II[2:0] : 3'h0 ),
// envelope operation
.keyon_II (keyon),
// envelope number
.am (am),
.tl_VII (tl_VII),
.ams_VII (ams_VII),
.amsen_VII (amsen_VII),
.eg_IX (eg_IX),
.pg_rst_III (pg_rst_III)
);
wire [9:0] eg0;
wire [9:0] rest_and, rest_or;
/* verilator lint_off PINMISSING */
sep24 #(.width(10),.pos0(8)) sep(
.clk ( clk ),
.clk_en ( 1'b1 ),
.mixed ( eg_IX ),
.cnt ( cnt24 ),
.ch0s1 ( eg0 ),
.alland ( rest_and ),
.allor ( rest_or ),
.mask ( ~24'b1 )
);
/* verilator lint_on PINMISSING */
`ifdef NCVERILOG
initial $shm_probe(jt12_test,"AS");
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; long double eps = -1e12; inline bool eq(const long double &x, const long double &y) { return abs(x - y) < eps || abs(x - y) < eps * abs(x); } int main() { long double x, y, z; cin >> x >> y >> z; string expression[12] = { x^y^z , x^z^y , (x^y)^z , (x^z)^y , y^x^z , y^z^x , (y^x)^z , (y^z)^x , z^x^y , z^y^x , (z^x)^y , (z^y)^x }; vector<long double> ans(12, 0); long double res = -1000; long double logx = log(x); long double logy = log(y); long double logz = log(z); ans[0] = pow(y, z) * logx; ans[1] = pow(z, y) * logx; ans[2] = logx * y * z; ans[3] = ans[2]; ans[4] = pow(x, z) * logy; ans[5] = pow(z, x) * logy; ans[6] = logy * x * z; ans[7] = ans[6]; ans[8] = pow(x, y) * logz; ans[9] = pow(y, x) * logz; ans[10] = logz * y * x; ans[11] = ans[10]; int index = 0; for (int i = 0; i < 12; ++i) { if (ans[i] > res && !eq(ans[i], res)) { res = ans[i]; index = i; } } cout << expression[index] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n, m, k, ans = 0; cin >> n >> m >> k; vector<int> a(n + 1), b(n + 1), c(k + 1); for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 1; i <= k; i++) cin >> c[i]; for (int i = 1; i <= k; i++) { int curp = a[c[i]], curid = b[c[i]]; for (int j = 1; j <= n; j++) { if (b[j] == curid && curp < a[j]) { ans++; a[c[i]] = 0; b[c[i]] = 0; break; } } } cout << ans << endl; return 0; }
|
module testit;
reg clk;
reg a_i;
reg b_i;
reg a_o;
reg b_o;
reg rst_n;
reg [7:0] shreg;
//== State enumeration
parameter [2:0] // synopsys enum state_info
SM_IDLE = 3'b000,
SM_SEND = 3'b001,
SM_WAIT1 = 3'b010;
//== State variables
reg [2:0] /* synopsys enum state_info */
state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */
state_e1;
//== ASCII state decoding
/*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
// Beginning of automatic ASCII enum decoding
reg [39:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
SM_IDLE: _stateascii_r = "idle ";
SM_SEND: _stateascii_r = "send ";
SM_WAIT1: _stateascii_r = "wait1";
default: _stateascii_r = "%Erro";
endcase
end
// End of automatics
initial begin
clk = 0;
a_i = 0;
b_i = 0;
rst_n = 0;
#20 rst_n = 1;
end
always #5 clk = ~clk;
always @(posedge clk or rst_n) begin
if (~rst_n) begin
a_o <= 0;
b_o <= 0;
shreg <= 8'b00110011;
end
else begin
a_o <= a_i;
b_o <= b_i;
shreg <= {shreg[6:0], shreg[7]};
end
end
task set_a_i;
begin
a_i = shreg[0];
end
endtask // set_a_i
always @(shreg & a_o) begin
set_a_i;
end
initial begin
$vcdpluson;
#500 $finish;
end
endmodule // testit
|
#include <bits/stdc++.h> int main() { int n, m, i; float x, max = 0.0; scanf( %d%d , &n, &m); int s[n][2]; for (i = 0; i < n; i++) { scanf( %d%d , &s[i][0], &s[i][1]); x = (float)(s[i][0]) / s[i][1]; if (max == 0.0) { max = x; } if (max > x) { max = x; } } x = max * m; printf( %.8f n , x); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRBP_FUNCTIONAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZE = 8;
integer cnt = 0;
logic [SIZE-1:0] vld_for;
logic vld_if = 1'b0;
logic vld_else = 1'b0;
genvar i;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if (cnt==SIZE) begin : if_cnt_finish
$write("*-* All Finished *-*\n");
$finish;
end : if_cnt_finish
generate
for (i=0; i<SIZE; i=i+1) begin : generate_for
always @ (posedge clk)
if (cnt == i) vld_for[i] <= 1'b1;
end : generate_for
endgenerate
generate
if (SIZE>0) begin : generate_if_if
always @ (posedge clk)
vld_if <= 1'b1;
end : generate_if_if
else begin : generate_if_else
always @ (posedge clk)
vld_else <= 1'b1;
end : generate_if_else
endgenerate
endmodule : t
|
#include <bits/stdc++.h> using namespace std; long long nCr(int n, int r) { if (r > n - r) r = n - r; long long ans = 1; int i; for (i = 1; i <= r; i++) { ans *= n - r + i; ans /= i; } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long a, b, c, d, e, g, h, n, t, f, k, l, m, f1 = 0, flag = 0, flag1 = 0, co = 0, co1 = 0, co2 = 0, arr1[100001] = {0}, arr[100001] = {0}, sum = 0, sum1 = 0, ma = 0, mi = 1000000000000000001; long long co3 = 0, co4 = 0, co5 = 0, co6 = 0, co7 = 0, co8 = 0; double pi = 2 * acos(0.0); string str, str1, str2, str3; char ch; vector<long long> v; vector<long long> v1; vector<string> vs; vector<string> vs1; map<int, int> mp; set<long long> s; set<long long> s1; set<long long>::iterator it; queue<long long> q; int x[] = {1, 1, 1, 0, 0, -1, -1, -1}; int y[] = {0, 1, -1, 1, -1, 1, -1, 0}; cin >> a >> b; for (int i = 0; i < a; i++) { cin >> c; mp[c] = 1; } for (int i = 1;; i++) { if (mp[i] == 1) continue; else { b -= i; if (b < 0) break; v.push_back(i); } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i] << ; return 0; }
|
// -- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
//-----------------------------------------------------------------------------
//
// File name: cdn_axi_bfm_0.v
//
// Description: Verilog wrapper for Cadence's "cdn_axi_bfm" module.
//
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
//-----------------------------------------------------------------------------
// The AXI4 Streaming Master BFM Top Level Wrapper
//-----------------------------------------------------------------------------
module cdn_axi_bfm_0 (m_axis_aclk, m_axis_aresetn,
m_axis_tvalid, m_axis_tready, m_axis_tdata,
m_axis_tkeep,m_axis_tid,m_axis_tdest,m_axis_tuser, m_axis_tlast);
//-----------------------------------------------------------------------------
parameter C_M_AXIS_NAME = "cdn_axi_bfm_0";
parameter C_M_AXIS_TDATA_WIDTH = 24;
parameter C_M_AXIS_TID_WIDTH = 8;
parameter C_M_AXIS_TDEST_WIDTH = 4;
parameter C_M_AXIS_TUSER_WIDTH = 8;
parameter C_M_AXIS_MAX_PACKET_SIZE = 10;
parameter C_M_AXIS_MAX_OUTSTANDING_TRANSACTIONS = 8;
parameter C_INTERCONNECT_M_AXIS_WRITE_ISSUING = 8;
parameter C_M_AXIS_STROBE_NOT_USED = 1;
parameter C_M_AXIS_KEEP_NOT_USED = 0;
//------------------------------------------------------------------------
// Signal Definitions
//------------------------------------------------------------------------
// Global Clock Input. All signals are sampled on the rising edge.
input wire m_axis_aclk;
// Internal Clock created by delaying the input clock and used for sampling
// and driving input and output signals respectively to avoid race conditions.
//wire bfm_aclk;
// Global Reset Input. Active Low.
input wire m_axis_aresetn;
// Transfer Channel Signals.
output wire m_axis_tvalid; // Master Transfer Valid.
input wire m_axis_tready; // Slave Transfer Ready.
output wire [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata; // Master Transfer Data.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep; // Master Transfer Keep.
output wire m_axis_tlast; // Master Transfer Last Flag.
output wire [C_M_AXIS_TID_WIDTH-1:0] m_axis_tid; // Master Transfer ID Tag.
output wire [C_M_AXIS_TDEST_WIDTH-1:0] m_axis_tdest; // Master Transfer Destination.
output wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser; // Master Transfer User Defined.
cdn_axi4_streaming_master_bfm #(.NAME(C_M_AXIS_NAME),
.DATA_BUS_WIDTH(C_M_AXIS_TDATA_WIDTH),
.ID_BUS_WIDTH(C_M_AXIS_TID_WIDTH),
.DEST_BUS_WIDTH(C_M_AXIS_TDEST_WIDTH),
.USER_BUS_WIDTH(C_M_AXIS_TUSER_WIDTH),
.MAX_PACKET_SIZE(C_M_AXIS_MAX_PACKET_SIZE),
.MAX_OUTSTANDING_TRANSACTIONS(C_M_AXIS_MAX_OUTSTANDING_TRANSACTIONS),
.STROBE_NOT_USED(C_M_AXIS_STROBE_NOT_USED),
.KEEP_NOT_USED(C_M_AXIS_KEEP_NOT_USED)
)
cdn_axi4_streaming_master_bfm_inst(.ACLK(m_axis_aclk),
.ARESETn(m_axis_aresetn),
.TVALID(m_axis_tvalid),
.TREADY(m_axis_tready),
.TDATA(m_axis_tdata),
.TKEEP(m_axis_tkeep),
.TID(m_axis_tid),
.TDEST(m_axis_tdest),
.TUSER(m_axis_tuser),
.TLAST(m_axis_tlast)
);
// These runtime parameters are set based on selection in GUI
// All these parameters can be changed during the runtime in the TB also
initial
begin
cdn_axi4_streaming_master_bfm_inst.set_response_timeout(500);
cdn_axi4_streaming_master_bfm_inst.set_clear_signals_after_handshake(0);
cdn_axi4_streaming_master_bfm_inst.set_stop_on_error(1);
cdn_axi4_streaming_master_bfm_inst.set_channel_level_info(0);
cdn_axi4_streaming_master_bfm_inst.set_packet_transfer_gap(0);
cdn_axi4_streaming_master_bfm_inst.set_task_call_and_reset_handling(0);
cdn_axi4_streaming_master_bfm_inst.set_input_signal_delay(0);
end
endmodule
|
`timescale 1ns / 1ps
module SeparadorNumeros
#(parameter stateA = 'b0001, //idle
parameter stateB = 'b0010, //convert
parameter stateC = 'b0100 //send
)
(input [31:0] alu_in,
input start_conversion,
input tx_done,
input clk,
output reg [7:0] value_to_send = 0,
output reg tx_start = 0
);
reg [3:0] diez;
reg [3:0] nueve;
reg [3:0] ocho;
reg [3:0] siete;
reg [3:0] seis;
reg [3:0] cinco;
reg [3:0] cuatro;
reg [3:0] tres;
reg [3:0] dos;
reg [3:0] uno;
reg done_convert = 0;
reg done_send = 0;
reg [3:0] state = stateA;
reg [3:0] next_state = stateA;
integer enviando_valor = 10;
always@(posedge clk)
begin
state = next_state;
end
always@(posedge clk)
begin
case(state)
stateA:
begin
if(!start_conversion) next_state = stateA;
else next_state = stateB;
end
stateB:
begin
if(!done_convert) next_state = stateB;
else next_state = stateC;
end
stateC:
begin
if(!done_send)next_state = stateC;
else next_state = stateA;
end
endcase
end
integer i;
integer retardo = 0;
always@(posedge clk)
begin
if(state == stateA)
begin
done_send = 0;
done_convert = 0;
tx_start = 0;
enviando_valor = 10;
end
if(state == stateB)
begin
diez = 4'd0;
nueve = 4'd0;
ocho = 4'd0;
siete = 4'd0;
seis = 4'd0;
cinco = 4'd0;
cuatro = 4'd0;
tres = 4'd0;
dos = 4'd0;
uno = 4'd0;
for(i=31;i>=0; i=i-1)
begin
if(diez >= 5)
diez = diez + 3;
if(nueve >= 5)
nueve = nueve + 3;
if(ocho >= 5)
ocho = ocho + 3;
if(siete >= 5)
siete = siete + 3;
if(seis >= 5)
seis = seis + 3;
if(cinco >= 5)
cinco = cinco + 3;
if(cuatro >= 5)
cuatro = cuatro + 3;
if(tres >= 5)
tres = tres + 3;
if(dos >= 5)
dos = dos + 3;
if(uno >= 5)
uno = uno + 3;
diez = diez << 1;
diez[0] = nueve[3];
nueve = nueve << 1;
nueve[0] = ocho[3];
ocho = ocho << 1;
ocho[0] = siete[3];
siete = siete << 1;
siete[0] = seis[3];
seis = seis << 1;
seis[0] = cinco[3];
cinco = cinco << 1;
cinco[0] = cuatro[3];
cuatro = cuatro << 1;
cuatro[0] = tres[3];
tres = tres << 1;
tres[0] = dos[3];
dos = dos << 1;
dos[0] = uno[3];
uno = uno << 1;
uno[0] = alu_in[i];
end
done_convert = 1;
end
if(state == stateC)
begin
if(tx_done)
begin
case(enviando_valor)
10:
begin
if(retardo == 0)
begin
value_to_send <= diez + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo - 1;
end
9:
begin
if(retardo == 0)
begin
value_to_send <= nueve + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
8:
begin
if(retardo == 0)
begin
value_to_send <= ocho + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
7:
begin
if(retardo == 0)
begin
value_to_send <= siete + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
6:
begin
if(retardo == 0)
begin
value_to_send <= seis + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
5:
begin
if(retardo == 0)
begin
value_to_send <= cinco + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
4:
begin
if(retardo == 0)
begin
value_to_send <= cuatro + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
3:
begin
if(retardo == 0)
begin
value_to_send <= tres + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
2:
begin
if(retardo == 0)
begin
value_to_send <= dos + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
1:
begin
if(retardo == 0)
begin
value_to_send <= uno + 48;
tx_start = 1;
enviando_valor = enviando_valor - 1;
retardo = 4;
end
else retardo = retardo -1;
end
default:
begin
tx_start = 0;
enviando_valor = 10;
done_send = 1;
end
endcase
end
else tx_start = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void getint(int &v) { char ch, fu = 0; for (ch = * ; (ch < 0 || ch > 9 ) && ch != - ; ch = getchar()) ; if (ch == - ) fu = 1, ch = getchar(); for (v = 0; ch >= 0 && ch <= 9 ; ch = getchar()) v = v * 10 + ch - 0 ; if (fu) v = -v; } const int MO = 1e9 + 7; long long P[5555], ans, p[5555], T; int n, k, a[5555], f[5010][5010]; long long pw(long long x, long long y) { long long t = 1; for (; y; y >>= 1) { if (y & 1) t = t * x % MO; x = x * x % MO; } return t; } int main() { cin >> n >> k; T = 1; for (int i = 1; i <= n; ++i) getint(a[i]), T = T * a[i] % MO; P[0] = 1; for (int i = 1; i <= n; ++i) P[i] = P[i - 1] * (k - i + 1) % MO; f[0][0] = 1; for (int i = 1; i <= n; ++i) { f[i][0] = 1; for (int j = 1; j <= i; ++j) f[i][j] = (f[i - 1][j] + (long long)f[i - 1][j - 1] * a[i]) % MO; } long long t = MO - pw(n, MO - 2); p[0] = 1; for (int i = 1; i <= n; ++i) p[i] = p[i - 1] * t % MO; for (int i = 0; i <= n; ++i) { if (n - i > k) continue; long long x = f[n][i] * P[n - i] % MO * p[n - i] % MO; (ans += x) %= MO; } cout << (T - ans + MO) % MO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, x[5], a[30], d = 0; long long mod = 1000000007ll, fc[30]; long long C[30][30]; bool vis[30]; long long first(long long s1, long long s2, long long s3, long long ind, long long q, long long t) { if (t == 1) { if (s1 == 0) return (fc[q] * first(0, s2, s3, 0, 0, 2)) % mod; long long r = 0; for (int i = ind + 1; i <= n && a[i] <= s1; i++) { int N = 1; for (int j = i + 1; j <= n && a[j] == a[i]; j++) N++; for (int k = 1; k <= N && a[i] * k <= s1; k++) { vis[i + k - 1] = 1; r = (r + (C[N][k] * first(s1 - k * a[i], s2, s3, i + N - 1, q + k, 1)) % mod) % mod; } for (int j = i; j < i + N; ++j) vis[j] = 0; i += N - 1; } return r; } if (t == 2) { if (s2 == 0) return (fc[q] * first(0, 0, s3, 0, 0, 3)) % mod; long long r = 0; for (int i = ind + 1; i <= n && a[i] <= s2; i++) if (!vis[i]) { vis[i] = 1; r = (r + first(0, s2 - a[i], s3, i, q + 1, 2)) % mod; vis[i] = 0; } return r; } q = 0; for (int i = 1; i <= n; i++) if (!vis[i]) q++; return fc[q]; } int main() { memset(C, 0, sizeof(C)); memset(vis, 0, sizeof(vis)); for (int i = 0; i < 30; i++) C[i][0] = 1; for (int i = 1; i < 30; i++) for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; cin >> n; fc[0] = 1; for (int i = 1; i <= n; ++i) { cin >> a[i]; d += a[i]; fc[i] = (fc[i - 1] * i) % mod; } sort(a + 1, a + n + 1); cin >> k; for (int i = 1; i <= k; i++) cin >> x[i]; if (k == 0) { cout << fc[n]; return 0; } if (k == 1) { fc[n] = (fc[n] - first(x[1], 0, d - x[1], 0, 0, 1) + mod) % mod; cout << fc[n]; return 0; } if (x[1] > x[2]) swap(x[1], x[2]); long long r1 = first(min(x[1], d - x[1]), 0, max(d - x[1], x[1]), 0, 0, 1); memset(vis, 0, sizeof(vis)); long long r2 = first(min(x[2], d - x[2]), 0, max(d - x[2], x[2]), 0, 0, 1); memset(vis, 0, sizeof(vis)); x[3] = d - x[2]; x[2] -= x[1]; sort(x + 1, x + 3); long long r3 = first(x[1], x[2], x[3], 0, 0, 1); long long res = (fc[n] - r1 - r2 + r3 + 2 * mod) % mod; cout << res; return 0; }
|
// zhiyang ong
// andrew mattheisen
// This version includes:
// HZ1 Detection and data forwarding for HZ1
// HZ2 detection was not necessary
// HZ3 Detection and data forwarding for HZ3
// Current bugs (...they're features, actually)
// No none current bugs!
// this statement is for ncverilog only
`include "control.h"
`include "alu.v"
`include "control.v"
`include "mux128.v"
`include "pipe1.v"
`include "pipe2.v"
`include "pipe3.v"
`include "prog_counter2.v"
`include "regfileww.v"
`include "hazard_detect.v"
/*
// Synthesis include statements
`include "~/ee577b/syn/src/control.h"
`include "~/ee577b/syn/src/alu.v"
`include "~/ee577b/syn/src/control.v"
`include "~/ee577b/syn/src/mux128.v"
`include "~/ee577b/syn/src/pipe1.v"
`include "~/ee577b/syn/src/pipe2.v"
`include "~/ee577b/syn/src/pipe3.v"
`include "~/ee577b/syn/src/prog_counter2.v"
`include "~/ee577b/syn/src/regfileww.v"
`include "~/ee577b/syn/src/hazard_detect.v"
*/
//Note that the following two lines were removed because the cpu.tb file integrates datamem
//`include datamem.v
//data_mem datamem1(data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
module cpu(
clk,
reset,
instruction, // 32 bit instruction
pc, // 32 bit program counter
dataIn, // 128 bit data from dmem
dataOut, // 128 bit data to dmem
memAddr, // 21 bit immediate address, only 8 bits are used
memWrEn, // dmem write enable
memEn // dmem enable (to avoid spurious reads)
);
//INPUTS
input clk, reset;
input [0:31] instruction; // 32 bit instruction
input [0:127] dataIn; // 128 bit data from dmem
//OUTPUTS
output [0:31] pc; // 32 bit program counter
output [0:127] dataOut; // 128 bit data to dmem
output [0:21] memAddr; // 21 bit immediate address, only 8 bits are used
output memWrEn, // dmem write enable
memEn; // dmem enable (to avoid spurious reads)
// WIRES
wire [0:31] pc;
wire [0:31] instruction1, instruction2, instruction3;
wire [0:4] aluop, aluop2;
wire [0:1] ww, ww2;
wire [0:1] memop;
wire [0:20] memAddr_pre, memAddr;
wire [0:15] wbyteen, wbyteen2, wbyteen3;
wire [0:2] regop;
wire regwren2, regwren3;
wire [0:4] rrdaddra, rrdaddrb;
wire [0:4] rwraddrd, rwraddrd2, rwraddrd3;
wire [0:127] rd1data;
wire [0:127] rd2data, dataOut, dataIn, dataIn3;
wire reginmuxop, reginmuxop2, reginmuxop3;
wire aluinmuxop;
wire [0:127] immediate, immediate2;
wire [0:127] aluOut, aluOut3, wrdata;
wire memEn_pre, memWrEn_pre;
// Wires for data forwarding
wire hz1_a_or_d, hz1_b, hz3;
wire [0:127] rd2data_immediate, rega, hz1data;
wire hz3_a_or_d, hz3_b;
wire [0:127] regahz1, regbhz1;
// ------------- Stage 1 IF -----------------------
// modules for sturctural verilog
prog_counter2 programcounter(pc, reset, clk);
// imem is integrated in the testbench
pipe1 pipe1_1(instruction, instruction1, clk, reset);
// ------------- Stage 2 ID/RF ---------------------
control control1(instruction1, aluop, ww, memEn_pre, memWrEn_pre, memAddr_pre, wbyteen,
regop, rrdaddra, rrdaddrb, rwraddrd, reginmuxop, aluinmuxop, immediate);
regfileww regfile1(rd1data,rd2data,wrdata,rrdaddra,rrdaddrb,rwraddrd3,
regop[0],regop[1],regwren3,wbyteen3,clk);
mux128 aluinmux(rd2data, immediate2, rd2data_immediate, aluinmuxop2);
// HZ1 Data Forwarding Muxes
mux128 regb_df1_mux(rd2data_immediate, hz1data, regbhz1, hz1_b);
mux128 rega_df1_mux(rd1data, hz1data, regahz1, hz1_a_or_d);
// HZ3 Data Forwarding Muxes
mux128 regb_df3_mux(regbhz1, wrdata, dataOut, hz3_b);
mux128 rega_df3_mux(regahz1, wrdata, rega, hz3_a_or_d);
pipe2 pipe2_1(aluop, aluop2,
ww, ww2,
memEn_pre, memEn,
memWrEn_pre, memWrEn,
memAddr_pre, memAddr,
wbyteen, wbyteen2,
regop[2], regwren2,
rwraddrd, rwraddrd2,
reginmuxop, reginmuxop2,
aluinmuxop, aluinmuxop2,
immediate, immediate2,
wrdata, hz1data,
instruction1, instruction2,
clk,
reset);
// ------------- Stage 3 MEM/EX ---------------------
alu alu1(rega, dataOut, ww2, aluop2, aluOut);
//datamem - seperate module, integrated by testbench
pipe3 pipe3_1( dataIn, dataIn3,
wbyteen2, wbyteen3,
regwren2, regwren3,
rwraddrd2, rwraddrd3,
reginmuxop2, reginmuxop3,
aluOut, aluOut3,
instruction2, instruction3,
clk,
reset);
// ------------- Stage 4 WB ---------------------
mux128 reginmux(aluOut3,
dataIn,
wrdata,
reginmuxop3 );
// WR inputs of previously instantiated regfile used
// ------------- Hazard Detection -----------------
hazard_detect hazard_detect1(instruction1, instruction2, instruction3,
hz1_a_or_d, hz1_b, hz3_a_or_d, hz3_b);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<int> g[n]; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--, v--; g[v].push_back(u); } int l[n]; for (int i = 0; i < n; i++) l[i] = 0; vector<int> a; for (int i = 0; i < n; i++) { for (auto j : g[i]) l[i] = max(l[i], l[j] + 1); if (l[i] == 2) { l[i] = -1; a.push_back(i); } } cout << a.size() << n ; for (auto i : a) cout << i + 1 << ; cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const int M = 1e6 + 10; int n, m, x, y, a[N], f[M]; bitset<N> ans, tmp; int main() { scanf( %d%d%d , &n, &x, &y); for (int i = 1; i <= n + 1; i++) { scanf( %d , &a[i]); tmp.set(a[i]); } for (int i = 1; i <= n + 1; i++) { ans |= tmp >> a[i]; } for (int i = 1; i <= x; i++) if (ans[i]) f[2 * (i + y)] = 2 * (i + y); for (int i = 1; i < M; i++) for (int j = i; j < M; j += i) f[j] = max(f[j], f[i]); scanf( %d , &m); while (m--) { scanf( %d , &x); if (f[x]) printf( %d , f[x]); else printf( -1 ); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_SYMBOL_V
`define SKY130_FD_SC_LS__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O2111A_FUNCTIONAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int mod = (int)1e9 + 7; const int MOD = (int)998244353; const int INF = (int)1e18; bool cmp(const pair<long long, long long>& a, const pair<long long, long long>& b) { if (a.second == b.second) return a.first < b.first; return a.second > b.second; } void solve() { long long a, b, x, y, p, q; cin >> a >> b >> x >> y >> p >> q; vector<long long> v; long long cnt = 0; map<pair<long long, int>, int> m1; long long n, m; n = a + x - p; m = b + y - q; v.push_back(n); v.push_back(m); m1[{n, m}] = 1; cnt++; n = a - x + p; m = b - y + q; if (m1[{n, m}] == 0) { cnt++; m1[{n, m}] = 1; v.push_back(n); v.push_back(m); } n = -a + x + p; m = -b + y + q; if (m1[{n, m}] == 0) { cnt++; m1[{n, m}] = 1; v.push_back(n); v.push_back(m); } cout << cnt << n ; cnt = ((int)(v).size()); for (long long i = 0; i < cnt; i++) { cout << v[i] << ; if (i & 1) cout << n ; } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1, m = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; bool palindrom = true; for (int i = 0; i < ceil(s.length() / 2.0); i++) { if (s[i] != s[s.length() - 1 - i]) palindrom = false; } if (!palindrom) { cout << s.length() << n ; return 0; } char elso = s[0]; bool mind_ugyanaz = true; for (auto c : s) { if (c != elso) mind_ugyanaz = false; } if (mind_ugyanaz) cout << 0 n ; else cout << s.length() - 1 << n ; }
|
// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Mike Popoloski.
// SPDX-License-Identifier: CC0-1.0
interface foo_intf
(
input x
);
endinterface
module foo_subm
(
input x
);
endmodule
module t ();
localparam N = 3;
wire [2:0] X = 3'b110;
// Should not cause LITENDIAN warning, as no harm in array selections.
// verilator lint_on LITENDIAN
foo_intf foo1 [N] (.x(1'b1));
foo_subm sub1 [N] (.x(1'b1));
// Will cause LITENDIAN warning?
// verilator lint_off LITENDIAN
foo_intf foos [N] (.x(X));
foo_intf fool [1:3] (.x(X));
foo_intf foom [3:1] (.x(X));
foo_subm subs [N] (.x(X));
foo_subm subl [1:3] (.x(X));
foo_subm subm [3:1] (.x(X));
initial begin
// Check numbering with 0 first
// NC has a bug here
if (foos[0].x !== 1'b1) $stop;
if (foos[1].x !== 1'b1) $stop;
if (foos[2].x !== 1'b0) $stop;
//
if (fool[1].x !== 1'b1) $stop;
if (fool[2].x !== 1'b1) $stop;
if (fool[3].x !== 1'b0) $stop;
//
if (foom[1].x !== 1'b0) $stop;
if (foom[2].x !== 1'b1) $stop;
if (foom[3].x !== 1'b1) $stop;
//
if (subs[0].x !== 1'b1) $stop;
if (subs[1].x !== 1'b1) $stop;
if (subs[2].x !== 1'b0) $stop;
//
if (subl[1].x !== 1'b1) $stop;
if (subl[2].x !== 1'b1) $stop;
if (subl[3].x !== 1'b0) $stop;
//
if (subm[1].x !== 1'b0) $stop;
if (subm[2].x !== 1'b1) $stop;
if (subm[3].x !== 1'b1) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> int main() { int n; std::cin >> n; if (n > 1) { std::cout << 2 * (n - 1); } else { std::cout << 1; }; std::cout << << 2 << std::endl << 1 << << 2; return NULL; }
|
#include <bits/stdc++.h> using namespace std; struct node { long long x, id; } a[200005]; long long st[200005], top; bool cmp(node a, node b) { return a.x < b.x; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long T; cin >> T; while (T--) { top = 0; long long n, w, sum = 0; cin >> n >> w; for (long long i = 1; i <= n; i++) { cin >> a[i].x; a[i].id = i; } for (long long i = 1; i <= n; i++) { if ((w + 1) / 2 <= a[i].x && a[i].x <= w) { cout << 1 n << i << n ; goto loop; } } sort(a + 1, a + n + 1, cmp); while (a[n].x >= w) { n--; } for (long long i = n; i >= 1; i--) { if (sum + a[i].x <= w) { sum += a[i].x; st[++top] = a[i].id; } if ((w + 1) / 2 <= sum) { cout << top << n ; for (long long i = 1; i <= top; i++) { cout << st[i] << ; } cout << n ; goto loop; } } cout << -1 n ; loop:; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 != 0) { n += 1; } cout << (n / 2) - 1 << endl; return 0; }
|
// Beck Pang
// University of Washington, Seattle
// Apr. 6th, 2015
// EE 471, Lab 1
`include "DFlipFlop.v"
`include "upCounter4Bit.v"
module upCounter4Bit_testBench ();
// connext the two modules
wire clk, rst_n;
wire [3:0] out;
// declare an instance of the AND module
upCounter4Bit myCounter (clk, rst_n, out);
// Running the GUI part of simulation
upCounter4Bit_Tester aTester (clk, rst_n, out);
// file for gtkwave
initial
begin
$dumpfile("upCounter.vcd");
$dumpvars(1, myCounter);
end
endmodule
module upCounter4Bit_Tester (
output reg clk, rst_n,
input [3:0] out
);
parameter stimDelay = 20;
// generate a clock
always #(stimDelay/2) clk = ~clk;
initial // Response
begin
$display("\t\t clk rst_n \t out \t Time ");
$monitor("\t %b ", out, $time);
clk = 'b0;
end
always @(posedge clk) // Stimulus
begin
rst_n = 'b0;
#stimDelay rst_n = 'b1;
#(32*stimDelay) rst_n = 'b0;
#stimDelay clk = 'b1;
#(32*stimDelay) clk = 'b0;
#stimDelay clk = 'b1;
#(2*stimDelay);
$stop;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class Mod { public: int mod; Mod(int mod_ = 1e9 + 7) : mod(mod_) {} int add(int a, int b) { return (a + b) % mod; } int mul(long long a, int b) { return (a * b) % mod; } int pow(long long a, int x) { int ans = 1; while (x) { if (x & 1) { ans = (ans * a) % mod; } x >>= 1; a = (a * a) % mod; } return ans; } }; class IO { public: static void read(int &val) { scanf( %d , &val); } static void read(long long &val) { scanf( %lld , &val); } static void read(char *val) { scanf( %s , val); } static void read(string &val) { const int BUFFER_SIZE = 1e5 + 5; static char buffer[BUFFER_SIZE]; scanf( %s , buffer); val = buffer; } static void read_n(vector<int> &val, int n) { val.resize(n); for (int i = 0; i < n; i++) { scanf( %d , &val[i]); } } static void write(int val) { printf( %d n , val); } static void write(long long val) { printf( %lld n , val); } static void write(const char *val) { printf( %s n , val); } static void write(const string &val) { printf( %s n , val.c_str()); } static void write(const vector<int> &val) { for (int i = 0; i < val.size(); i++) { if (i > 0) { putchar( ); } printf( %d , val[i]); } putchar( n ); } }; long long gcd_ex(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long ans = gcd_ex(b, a % b, y, x); y -= (a / b) * x; return ans; } class Solver { long long x; stringstream ans; int cnt_ans = 0; void print(long long x, long long a) { long long cur = 0; while (a) { if (a & 1) { if (cur > 0) { ans << cur << + << x << endl; cnt_ans++; } cur += x; } a >>= 1; ans << x << + << x << endl; cnt_ans++; x <<= 1; } } public: void read() { IO::read(x); } void solve() { long long e = 1; while ((e << 1) <= x) { e <<= 1; } print(x, e); ans << e * x << ^ << x << endl; cnt_ans++; long long y = ((e * x) ^ x); long long a, b; gcd_ex(x, y, a, b); if (a < 0) { swap(a, b); swap(x, y); } b = -b; if (!(a & 1)) { a += y; b += x; } print(x, a); print(y, b); ans << a * x << ^ << b * y << endl; cnt_ans++; IO::write(cnt_ans); IO::write(ans.str()); } }; void init() { ios::sync_with_stdio(false); } int main() { init(); int t = 1; while (t--) { Solver solver; solver.read(); solver.solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int K = 269; const int MS = 2; const int MOD[MS] = {(int)1e9 + 7, (int)1e9 + 9}; const int MAXN = 1e6 + 69; using hsh = vector<long long>; struct hj { int shift = MS == 1 ? 0 : 32 / (MS - 1); size_t operator()(const hsh& h) const { long long res = 0; for (int M = 0; M < MS; M++) res <<= shift, res ^= h[M]; return res; } }; int t; int n; set<int> a[MAXN]; unordered_map<hsh, int, hj> mp; vector<string> str; int check[MAXN]; int cnt; int ans; void build(hsh& h, char c) { for (int M = 0; M < MS; M++) h[M] = (c + h[M] * K) % MOD[M]; } void init() { for (int i = 1; i <= cnt; i++) { a[i].clear(); check[i] = 0; } mp.clear(); cnt = 0; ans = 0; } bool dfs(int u) { check[u] = 1; int tookChild = 0; for (int v : a[u]) if (!check[v]) tookChild |= dfs(v); ans += tookChild ^ 1; return tookChild ^ 1; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { init(); cin >> n; str.resize(n + 1); for (int i = 1; i <= n; i++) cin >> str[i], str[i] = + str[i]; for (int i = 1; i <= n; i++) { string& s = str[i]; hsh h(MS); for (int j = 1; j < (int)s.size(); j++) { build(h, s[j]); if (!mp.count(h)) mp[h] = ++cnt; } } for (int i = 1; i <= n; i++) { string& s = str[i]; hsh h(MS), h2(MS); for (int j = 1; j < (int)s.size(); j++) { build(h, s[j]); if (j >= 2) { build(h2, s[j]); if (mp.count(h2)) { int u = mp[h], v = mp[h2]; a[u].insert(v); a[v].insert(u); } } } } for (int i = 1; i <= cnt; i++) if (!check[i]) dfs(i); cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110000; const double EPS = 1E-7; struct pt { int x, y; }; int n; pt p[MAXN]; int l[MAXN], r[MAXN]; long long r_sums[MAXN]; inline long long vec(pt a, pt b, pt c) { return (b.x - a.x) * 1ll * (c.y - a.y) - (b.y - a.y) * 1ll * (c.x - a.x); } inline bool between(pt p, pt a, pt b, pt q) { return vec(p, a, q) > 0 && vec(p, q, b) > 0; } inline long long sum_r(int lt, int rt) { long long res = r_sums[rt]; if (lt) res -= r_sums[lt - 1]; return res; } long long solve(pt q) { int j = 0; for (int i = 0; i < n; ++i) { j = max(j, i + 1); while (j + 1 < n && !between(p[i], p[i + 1], p[j + 1], q)) ++j; r[i] = j; l[i] = j + 1; } for (int i = 0; i < n; ++i) { r_sums[i] = 0; if (i) r_sums[i] += r_sums[i - 1]; r_sums[i] += r[i]; } long long ans = 0; j = 0; for (int i = 0; i < n; ++i) { while (j < n && r[j] < l[i]) ++j; if (l[i] < n && j < n) { int left = j, right = r[i]; if (left > right) continue; ans += sum_r(left, right); ans -= (right - left + 1) * 1ll * (l[i] - 1); } } return ans; } bool inside(pt q) { bool res = false; for (int i = 0; i < n; ++i) { pt a = p[i], b = p[(i + 1) % n]; if (min(a.y, b.y) <= q.y && max(a.y, b.y) >= q.y) { if (q.y != a.y && q.y != b.y) { double cx = a.x + (b.x - a.x) * ((q.y - a.y) * 1. / (b.y - a.y)); if (cx >= q.x - EPS) res ^= true; } else { if (a.y == q.y && a.x > q.x || b.y == q.y && b.x > q.x) if (max(a.y, b.y) > q.y) res ^= true; } } } return res; } int main() { cin >> n; for (int i = 0; i < n; ++i) scanf( %d%d , &p[i].x, &p[i].y); reverse(p, p + n); int ts; cin >> ts; for (int tt = 0; tt < ts; ++tt) { pt q; scanf( %d%d , &q.x, &q.y); long long ans = 0; if (inside(q)) ans = solve(q); printf( %I64d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; int a[10005], cnt[305], dp[10005], inf = 1e8; int main() { int n, t; scanf( %d %d , &n, &t); int max_num = 0, len = n * min(n / 2, t); if (len <= 0) len = n; for (int i = 1; i <= n; ++i) { scanf( %d , a + i); max_num = max(max_num, ++cnt[a[i]]); } for (int i = n + 1; i <= len; ++i) { a[i] = a[i - n]; } int ans = 0; for (int i = 1; i <= len; ++i) { dp[i] = 1; for (int j = i - 1; j >= max(i - n, 1); --j) { if (a[i] >= a[j]) { dp[i] = max(dp[i], dp[j] + 1); } } ans = max(ans, dp[i]); } if (n / 2 == 0) n++; if (t <= (n / 2)) { printf( %d n , ans); } else { printf( %d n , ans + max_num * (t - (n / 2))); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char* x) { cerr << << x << ; } void __print(const string& x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V>& x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T& x) { int f = 0; cerr << { ; for (auto& i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void pre() {} const long long mod = (119 << 23) + 1, root = 3; long long modpow(long long a, long long e) { if (e == 0) return 1; long long x = modpow(a * a % mod, e >> 1); return e & 1 ? x * a % mod : x; } void ntt(long long* x, long long* temp, long long* roots, int N, int skip) { if (N == 1) return; int n2 = N / 2; ntt(x, temp, roots, n2, skip * 2); ntt(x + skip, temp, roots, n2, skip * 2); for (int i = 0; i < (N); ++i) temp[i] = x[i * skip]; for (int i = 0; i < (n2); ++i) { long long s = temp[2 * i], t = temp[2 * i + 1] * roots[skip * i]; x[skip * i] = (s + t) % mod; x[skip * (i + n2)] = (s - t) % mod; } } void ntt(vector<long long>& x, bool inv = false) { long long e = modpow(root, (mod - 1) / (int)(x).size()); if (inv) e = modpow(e, mod - 2); vector<long long> roots((int)(x).size(), 1), temp = roots; for (int i = 1; i <= ((int)(x).size() - 1); ++i) roots[i] = roots[i - 1] * e % mod; ntt(&x[0], &temp[0], &roots[0], (int)(x).size(), 1); } vector<long long> conv(vector<long long> a, vector<long long> b) { int s = (int)(a).size() + (int)(b).size() - 1; if (s <= 0) return {}; int L = s > 1 ? 32 - __builtin_clz(s - 1) : 0, n = 1 << L; if (s <= 200) { vector<long long> c(s); for (int i = 0; i < ((int)(a).size()); ++i) for (int j = 0; j < ((int)(b).size()); ++j) c[i + j] = (c[i + j] + a[i] * b[j]) % mod; return c; } a.resize(n); ntt(a); b.resize(n); ntt(b); vector<long long> c(n); long long d = modpow(n, mod - 2); for (int i = 0; i < (n); ++i) c[i] = a[i] * b[i] % mod * d % mod; ntt(c, true); c.resize(s); return c; } vector<vector<long long> > g; vector<long long> solve(int l, int r) { if (l == r) return g[l]; int m = (l + r) / 2; vector<long long> a = solve(l, m); vector<long long> b = solve(m + 1, r); return conv(a, b); } int a[200009]; int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); pre(); int n, k; cin >> n >> k; for (int i = 0; i < (n); ++i) cin >> a[i]; for (int i = 0; i < (n); ++i) { if (a[i] == a[(i + 1) % n]) { g.push_back({0, k, 0}); } else { g.push_back({1, k - 2, 1}); } } vector<long long> ans = solve(0, n - 1); long long fns = 0; for (int i = n + 1; i <= (2 * n); ++i) fns += ans[i]; cout << (fns % mod + mod) % mod; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_2_V
`define SKY130_FD_SC_HDLL__NOR3B_2_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_2_V
|
module TOP (/*AUTOARG*/
// Outputs
SIG_NAMEB, SIG_NAMEA
)
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [223:0] SIG_NAMEA; // From A of A.v, ...
output [FOO*4-2:0] SIG_NAMEB; // From C of C.v
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
A A(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[224*1-1:128*1]));
B B(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[127:0]));
C C(/*AUTOINST*/
// Outputs
.SIG_NAMEB (SIG_NAMEB[FOO*4-2*1:0]));
endmodule
module A(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [224*1-1:128*1] SIG_NAMEA;
//output [223:128] SIG_NAMEA;
endmodule
module B(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [127:0] SIG_NAMEA;
endmodule
module C(/*AUTOARG*/
// Outputs
SIG_NAMEB
);
output [FOO*4-2*1:0] SIG_NAMEB;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, a[150]; scanf( %d , &n); int sum = 0; for (i = 0; i < n; i++) { scanf( %d , &a[i]); sum += a[i]; } int ans = 0; for (i = 0; i < n; i++) (sum % 2) ^ ((a[i] + 1) % 2) ? ans++ : ans = ans; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> const int N = 100010; using ll = long long; int a[N]; int main() { int n, d, m; scanf( %d%d%d , &n, &d, &m); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } std::sort(a, a + n); int last = n; for (int i = 0; i < n; ++i) { if (a[i] > m) { last = i; break; } } std::sort(a, a + last, std::greater<int>()); ll ans = 0, sum = 0; for (int i = 0; i < last; ++i) { sum += a[i]; } for (int i = last - 1, j = n - 1; i >= -1; --i) { while (j >= last) { int num = i + 1 + (n - j) * (d + 1) - d; if (num > n) { break; } sum += a[j--]; } ans = std::max(ans, sum); if (i >= 0) { sum -= a[i]; } } printf( %lld n , ans); return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arp_eth_tx
*/
module test_arp_eth_tx;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_frame_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [15:0] s_arp_htype = 0;
reg [15:0] s_arp_ptype = 0;
reg [15:0] s_arp_oper = 0;
reg [47:0] s_arp_sha = 0;
reg [31:0] s_arp_spa = 0;
reg [47:0] s_arp_tha = 0;
reg [31:0] s_arp_tpa = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_frame_ready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_frame_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_arp_htype,
s_arp_ptype,
s_arp_oper,
s_arp_sha,
s_arp_spa,
s_arp_tha,
s_arp_tpa,
m_eth_hdr_ready,
m_eth_payload_axis_tready
);
$to_myhdl(
s_frame_ready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
busy
);
// dump file
$dumpfile("test_arp_eth_tx.lxt");
$dumpvars(0, test_arp_eth_tx);
end
arp_eth_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// ARP frame input
.s_frame_valid(s_frame_valid),
.s_frame_ready(s_frame_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_arp_htype(s_arp_htype),
.s_arp_ptype(s_arp_ptype),
.s_arp_oper(s_arp_oper),
.s_arp_sha(s_arp_sha),
.s_arp_spa(s_arp_spa),
.s_arp_tha(s_arp_tha),
.s_arp_tpa(s_arp_tpa),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int c[100]; for (int i = 0; i < n; i++) cin >> c[i]; int ans = 0; int min = a > b ? b : a; for (int i = 0; i < n / 2; i++) { if (c[i] == 0 && c[n - 1 - i] == 2 || c[i] == 2 && c[n - 1 - i] == 0) ans += a; else if (c[i] == 1 && c[n - 1 - i] == 2 || c[i] == 2 && c[n - 1 - i] == 1) ans += b; else if (c[i] == 2 && c[n - 1 - i] == 2) ans += min * 2; else if (c[i] == 0 && c[n - 1 - i] == 1 || c[i] == 1 && c[n - 1 - i] == 0) { cout << -1 << endl; return 0; } } if (n % 2 == 1 && c[n / 2] == 2) ans += min; cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_PP_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module ERROR_OUTPUT_LOGIC #(
parameter [7:0] DATA_WIDTH = 1,
parameter [7:0] ADDR_WIDTH = 6
) (
input rst,
input clk,
input loop_complete,
input error_detected,
input [7:0] error_state,
input [ADDR_WIDTH-1:0] error_address,
input [DATA_WIDTH-1:0] expected_data,
input [DATA_WIDTH-1:0] actual_data,
// Output to UART
input tx_data_accepted,
output reg tx_data_ready,
output reg [7:0] tx_data
);
reg reg_error_detected;
reg [7:0] reg_error_state;
reg [ADDR_WIDTH-1:0] reg_error_address;
reg [DATA_WIDTH-1:0] reg_expected_data;
reg [DATA_WIDTH-1:0] reg_actual_data;
reg [7:0] error_count;
reg [7:0] output_shift;
wire [7:0] next_output_shift = output_shift + 8;
wire count_shift_done = next_output_shift >= 8'd16;
wire address_shift_done = next_output_shift >= ADDR_WIDTH;
wire data_shift_done = next_output_shift >= DATA_WIDTH;
reg loop_ready;
reg [7:0] latched_error_count;
reg [7:0] errors;
reg [10:0] state;
reg [15:0] loop_count;
reg [15:0] latched_loop_count;
localparam START = (1 << 0),
ERROR_COUNT_HEADER = (1 << 1),
ERROR_COUNT_COUNT = (1 << 2),
CR = (1 << 3),
LF = (1 << 4),
ERROR_HEADER = (1 << 5),
ERROR_STATE = (1 << 6),
ERROR_ADDRESS = (1 << 7),
ERROR_EXPECTED_DATA = (1 << 8),
ERROR_ACTUAL_DATA = (1 << 9),
LOOP_COUNT = (1 << 10);
initial begin
tx_data_ready <= 1'b0;
tx_data <= 8'b0;
state <= START;
reg_error_detected <= 1'b0;
end
always @(posedge clk) begin
if(rst) begin
state <= START;
error_count <= 0;
reg_error_detected <= 0;
tx_data_ready <= 0;
tx_data <= 8'b0;
loop_count <= 0;
loop_ready <= 0;
end else begin
if(error_detected) begin
if(error_count < 255) begin
error_count <= error_count + 1;
end
if(!reg_error_detected) begin
reg_error_detected <= 1;
reg_error_state <= error_state;
reg_error_address <= error_address;
reg_expected_data <= expected_data;
reg_actual_data <= actual_data;
end
end
if(tx_data_accepted) begin
tx_data_ready <= 0;
end
if(loop_complete) begin
loop_count <= loop_count + 1;
if(!loop_ready) begin
loop_ready <= 1;
latched_error_count <= error_count;
latched_loop_count <= loop_count;
error_count <= 0;
end
end
case(state)
START: begin
if(reg_error_detected) begin
state <= ERROR_HEADER;
end else if(loop_ready) begin
state <= ERROR_COUNT_HEADER;
end
end
ERROR_COUNT_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "L";
tx_data_ready <= 1;
state <= ERROR_COUNT_COUNT;
end
end
ERROR_COUNT_COUNT: begin
if(!tx_data_ready) begin
tx_data <= latched_error_count;
tx_data_ready <= 1;
output_shift <= 0;
state <= LOOP_COUNT;
end
end
LOOP_COUNT: begin
if(!tx_data_ready) begin
tx_data <= (latched_loop_count >> output_shift);
tx_data_ready <= 1;
if(count_shift_done) begin
output_shift <= 0;
loop_ready <= 0;
state <= CR;
end else begin
output_shift <= next_output_shift;
end
end
end
CR: begin
if(!tx_data_ready) begin
tx_data <= 8'h0D; // "\r"
tx_data_ready <= 1;
state <= LF;
end
end
LF: begin
if(!tx_data_ready) begin
tx_data <= 8'h0A; // "\n"
tx_data_ready <= 1;
state <= START;
end
end
ERROR_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "E";
tx_data_ready <= 1;
state <= ERROR_STATE;
end
end
ERROR_STATE: begin
if(!tx_data_ready) begin
tx_data <= reg_error_state;
tx_data_ready <= 1;
output_shift <= 0;
state <= ERROR_ADDRESS;
end
end
ERROR_ADDRESS: begin
if(!tx_data_ready) begin
tx_data <= (reg_error_address >> output_shift);
tx_data_ready <= 1;
if(address_shift_done) begin
output_shift <= 0;
state <= ERROR_EXPECTED_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_EXPECTED_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_expected_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
output_shift <= 0;
state <= ERROR_ACTUAL_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_ACTUAL_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_actual_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
state <= CR;
reg_error_detected <= 0;
end else begin
output_shift <= output_shift + 8;
end
end
end
default: begin
state <= START;
end
endcase
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANNEL_INIT_SM
//
//
// Description: the CHANNEL_INIT_SM module is a state machine for managing channel
// bonding.
//
// The channel init state machine is reset until the lane up signals
// of all the lanes that constitute the channel are asserted. It then
// requests channel bonding until the lanes have been bonded.Channel
// bonding is skipped if there is only one lane in the channel.
// If bonding is unsuccessful, the lanes are reset.
//
// After CHANNEL_UP_TX_IF goes high, the state machine is quiescent, and will
// reset only if one of the lanes goes down, a hard error is detected, or
// a general reset is requested.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_CHANNEL_INIT_SM
(
// GT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
CHAN_BOND_RESET,
// Aurora Lane Interface
GEN_NA_IDLES,
RESET_LANES,
RX_NA_IDLES,
RX_CC,
REMOTE_READY,
RX_CB,
RX_IDLES,
// System Interface
USER_CLK,
RESET,
LANE_UP,
CHANNEL_UP_RX_IF,
CHANNEL_UP_TX_IF
);
`define DLY #1
//***********************************Port Declarations*******************************
// MGT Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
output CHAN_BOND_RESET;
// Aurora Lane Interface
output GEN_NA_IDLES;
output RESET_LANES;
input RX_NA_IDLES;
input RX_CC;
input REMOTE_READY;
input RX_CB;
input RX_IDLES;
// System Interface
input USER_CLK;
input RESET;
input LANE_UP;
output CHANNEL_UP_RX_IF;
output CHANNEL_UP_TX_IF;
//***************************External Register Declarations***************************
reg CHANNEL_UP_RX_IF = 1'b0;
reg CHANNEL_UP_TX_IF = 1'b0;
//***************************Internal Register Declarations***************************
// State registers
reg wait_for_lane_up_r = 1'b0;
reg bond_passed_r = 1'b0;
reg wait_for_remote_r = 1'b0;
reg ready_r = 1'b0;
reg any_na_idles_r = 1'b0;
reg any_idles_r = 1'b0;
reg rx_cc_r = 1'b0;
reg remote_ready_r = 1'b0;
reg [0:5] idle_xmit_cntr = 6'd0;
reg [0:3] rx_na_idles_cntr = 1'b0;
reg channel_bond_q = 1'b0;
reg channel_bond_qq = 1'b0;
reg [8:0] chan_bond_timer = 9'd0;
(* KEEP = "TRUE" *) reg reset_watchdog = 1'b0;
//*********************************Wire Declarations**********************************
wire reset_lanes_c;
wire channel_up_c;
wire channel_up_rx_c;
// Next state signals
wire next_wait_for_remote_c;
wire next_ready_c;
wire txidle_64d_done;
wire rx_na_idles_16d_done;
wire rst_ready_r_state;
wire set_enchansync_pulse;
(* KEEP = "TRUE"*) wire [8:0] chan_bond_timeout_val = 9'd500;
//*********************************Main Body of Code**********************************
//________________Main state machine for bonding and verification________________
always @(posedge USER_CLK)
begin
if(wait_for_remote_r)
rx_na_idles_cntr <= `DLY 4'h0;
else if(ready_r & any_na_idles_r)
rx_na_idles_cntr <= `DLY rx_na_idles_cntr + 1'b1;
else
rx_na_idles_cntr <= `DLY 4'h0;
end
assign rx_na_idles_16d_done = &rx_na_idles_cntr;
assign rst_ready_r_state = (ready_r & !remote_ready_r & bond_passed_r);
always @(posedge USER_CLK)
begin
if(wait_for_lane_up_r)
idle_xmit_cntr <= `DLY 6'h0;
else if(rst_ready_r_state)
idle_xmit_cntr <= `DLY 6'h0;
else if(idle_xmit_cntr == 6'b111111)
idle_xmit_cntr <= `DLY idle_xmit_cntr;
else if(wait_for_remote_r)
begin
if(any_idles_r & (idle_xmit_cntr == 6'h0))
idle_xmit_cntr <= `DLY 6'h1;
else
idle_xmit_cntr <= `DLY (idle_xmit_cntr != 6'h0) ? idle_xmit_cntr + 1'b1 : idle_xmit_cntr;
end
end
assign txidle_64d_done = &idle_xmit_cntr;
// State registers
always @(posedge USER_CLK)
begin
if(RESET|!(&LANE_UP))
begin
wait_for_lane_up_r <= `DLY 1'b1;
wait_for_remote_r <= `DLY 1'b0;
ready_r <= `DLY 1'b0;
end
else
begin
wait_for_lane_up_r <= `DLY 1'b0;
wait_for_remote_r <= `DLY next_wait_for_remote_c;
ready_r <= `DLY next_ready_c;
end
end
// Next state logic
/*
assign next_wait_for_remote_c = (wait_for_lane_up_r) |
(wait_for_remote_r & (any_na_idles_r | rx_cc_r)) |
(wait_for_remote_r & (!remote_ready_r | !txidle_64d_done)) |
(ready_r & rx_na_idles_16d_done);
assign next_ready_c = (wait_for_remote_r & remote_ready_r & txidle_64d_done)|
(ready_r & !rx_na_idles_16d_done ) ;
*/
assign next_wait_for_remote_c = (wait_for_lane_up_r)|
(wait_for_remote_r & (!remote_ready_r | !txidle_64d_done)) |
(ready_r & !remote_ready_r );
assign next_ready_c = (wait_for_remote_r & remote_ready_r & txidle_64d_done )|
(ready_r & remote_ready_r) ;
// Output Logic Channel up is high as long as the Global Logic is in the ready state.
assign channel_up_c = ready_r & !next_wait_for_remote_c ;
assign channel_up_rx_c = channel_up_c | remote_ready_r ;
always @(posedge USER_CLK)
begin
if(RESET)
CHANNEL_UP_TX_IF <= `DLY 1'b0;
else
CHANNEL_UP_TX_IF <= `DLY channel_up_c;
end
always @(posedge USER_CLK)
begin
if(RESET)
CHANNEL_UP_RX_IF <= `DLY 1'b0;
else
CHANNEL_UP_RX_IF <= `DLY channel_up_rx_c;
end
//__________________________Channel Reset _________________________________
// Some problems during channel bonding and verification require the lanes to
// be reset. When this happens, we assert the Reset Lanes signal, which gets
// sent to all Aurora Lanes. When the Aurora Lanes reset, their LANE_UP signals
// go down. This causes the Channel Error Detector to assert the Reset Channel
// signal.
assign reset_lanes_c = (!(&LANE_UP) & !wait_for_lane_up_r)|
RESET;
FD #(
.INIT(1'b1)
) reset_lanes_flop_0_i (
.D(reset_lanes_c),
.C(USER_CLK),
.Q(RESET_LANES)
);
assign EN_CHAN_SYNC = 1'b1;
assign CHAN_BOND_RESET = 1'b0;
//_____________________________Idle Pattern Generation and Reception_______________________________
// Generate NA idles when until channel bonding is complete
assign GEN_NA_IDLES = wait_for_lane_up_r;
// The NA IDles will be coming in on all the lanes. OR them to decide when to go into and out of
// wait_for_remote_r state. This OR gate may need to be pipelined for greater number of lanes
always @(posedge USER_CLK)
begin
rx_cc_r <= `DLY |( RX_CC);
remote_ready_r <= `DLY &( REMOTE_READY);
any_na_idles_r <= `DLY |( RX_NA_IDLES);
any_idles_r <= `DLY |( RX_IDLES);
end
endmodule
|
module wb_ram
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output [dw-1:0] wb_dat_o);
`include "wb_common.v"
reg [aw-1:0] adr_r;
wire [aw-1:0] next_adr;
wire valid = wb_cyc_i & wb_stb_i;
reg valid_r;
reg is_last_r;
always @(posedge wb_clk_i)
is_last_r <= wb_is_last(wb_cti_i);
wire new_cycle = (valid & !valid_r) | is_last_r;
assign next_adr = wb_next_adr(adr_r, wb_cti_i, wb_bte_i, dw);
wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
always@(posedge wb_clk_i) begin
adr_r <= adr;
valid_r <= valid;
//Ack generation
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst_i) begin
adr_r <= {aw{1'b0}};
valid_r <= 1'b0;
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
//TODO:ck for burst address errors
assign wb_err_o = 1'b0;
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (wb_clk_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr(adr_r[aw-1:2]),
.raddr (adr[aw-1:2]),
.dout (wb_dat_o));
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: BC.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module BC (
address,
clock,
q);
input [0:0] address;
input clock;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "BC.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=BC",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 1,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "BC"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "BC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "BC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=BC"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL BC.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL BC_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_1_V
`define SKY130_FD_SC_HD__EDFXTP_1_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog wrapper for edfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__edfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__edfxtp_1 (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__edfxtp_1 (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_LP_V
`define SKY130_FD_SC_LP__MUX2I_LP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_lp (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_lp (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_LP_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_udiv(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataouta, o_dataouta_valid, i_dataouta_stall,
o_dataoutb, o_dataoutb_valid, i_dataoutb_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataouta, o_dataoutb;
output o_dataouta_valid, o_dataoutb_valid;
input i_dataouta_stall, i_dataoutb_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_a_valid & is_fifo_b_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & (i_dataouta_stall | i_dataoutb_stall));
assign is_fifo_stalled = (shift_reg_valid[0] & (i_dataouta_stall | i_dataoutb_stall)) | !(is_fifo_a_valid & is_fifo_b_valid);
acl_int_div32u udiv_unit(
.enable(~is_stalled), .clock(clock), .denom(datab), .numer(dataa), .quotient(o_dataouta),
.remain(o_dataoutb));
assign o_dataouta_valid = shift_reg_valid[0];
assign o_dataoutb_valid = shift_reg_valid[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846; int a[100010], d[100010]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n + 1; i++) d[i] = a[i] - a[i - 1]; stack<int> st; int r = 0; for (int i = 1; i <= n; i++) { if (d[i] > 0) r += d[i]; } cout << r << endl; for (int i = 1; i <= n + 1; i++) { if (d[i] > 0) { for (int j = 0; j < d[i]; j++) { st.push(i); } } if (d[i] < 0) { for (int j = 0; j > d[i]; j--) { printf( %d %d n , st.top(), i - 1); st.pop(); } } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
// Local signals
wire DN not0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_BEHAVIORAL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* use_dsp48 = "yes" *) module matrix_mult_mac_mbkb_DSP48_0(
input clk,
input rst,
input ce,
input [8 - 1:0] in0,
input [8 - 1:0] in1,
input [16 - 1:0] in2,
output [16 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
reg signed [43 - 1:0] m_reg;
reg signed [25 - 1:0] a_reg;
reg signed [18 - 1:0] b_reg;
assign a = $signed(in0);
assign b = $signed(in1);
assign c = $unsigned(in2);
assign m = a_reg * b_reg;
assign p = m_reg + c;
always @(posedge clk) begin
if (ce) begin
m_reg <= m;
a_reg <= a;
b_reg <= b;
end
end
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module matrix_mult_mac_mbkb(
clk,
reset,
ce,
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
matrix_mult_mac_mbkb_DSP48_0 matrix_mult_mac_mbkb_DSP48_0_U(
.clk( clk ),
.rst( reset ),
.ce( ce ),
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 10 + 1e5; const int MOD = 1e9 + 7; int n, m; int a[MAXN], c[MAXN]; void Inout() { freopen( ABC .inp , r , stdin); freopen( ABC .out , w , stdout); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; long long ans = 0; for (int i = 1; i <= n; ++i) { cin >> a[i]; c[i] = max(c[i - 1], a[i] + 1); } for (int i = n - 1; i; --i) c[i] = max(c[i], c[i + 1] - 1); for (int i = 1; i <= n; ++i) { ans += c[i] - a[i] - 1; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, pair<int, int> > > v; int main() { ios_base::sync_with_stdio(false); ; int n; cin >> n; cout << (long long)(n - 2) * (n - 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int com[] = {1, 4, 6, 8, 9}; long long int t; cin >> t; while (t--) { int64_t k; cin >> k; string n; cin >> n; map<int, int> m; for (int i = 0; i < n.size(); i++) { m[n[i] - 0 ]++; } int flag = 1; for (auto it : m) { if (it.first == 1 || it.first == 4 || it.first == 6 || it.first == 8 || it.first == 9) { flag = 0; cout << 1 << endl << it.first << endl; break; } } if (flag) { for (auto it : m) { if (it.second > 1) { cout << 2 << endl << it.first << it.first << endl; flag = 0; break; } } if (n == 32 || n == 35 ) { flag = 0; cout << 2 << endl << n << endl; } } if (flag) { stack<int> s; string temp = ; for (int i = 0; i < n.size(); i++) { if (n[i] != 3 ) { temp += n[i]; } if (temp.size() == 2) { break; } } cout << 2 << endl << temp << endl; } } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) const long long inf = 2147383647; const double pi = 2 * acos(0.0); const double eps = 1e-9; const long long maxint = 2147483647; const long long minint = -2147483648; using namespace std; struct Bigint { string a; int sign; Bigint() {} Bigint(string b) { (*this) = b; } int size() { return a.size(); } Bigint inverseSign() { sign *= -1; return (*this); } Bigint normalize(int newSign) { for (int i = a.size() - 1; i > 0 && a[i] == 0 ; i--) a.erase(a.begin() + i); sign = (a.size() == 1 && a[0] == 0 ) ? 1 : newSign; return (*this); } void operator=(string b) { a = b[0] == - ? b.substr(1) : b; reverse(a.begin(), a.end()); this->normalize(b[0] == - ? -1 : 1); } void operator=(long long num) { char buf[30]; sprintf(buf, %lld , num); *this = buf; } bool operator<(const Bigint &b) const { if (sign != b.sign) return sign < b.sign; if (a.size() != b.a.size()) return sign == 1 ? a.size() < b.a.size() : a.size() > b.a.size(); for (int i = a.size() - 1; i >= 0; i--) if (a[i] != b.a[i]) return sign == 1 ? a[i] < b.a[i] : a[i] > b.a[i]; return false; } bool operator==(const Bigint &b) const { return a == b.a && sign == b.sign; } Bigint operator+(Bigint b) { if (sign != b.sign) return (*this) - b.inverseSign(); Bigint c; for (int i = 0, carry = 0; i < a.size() || i < b.size() || carry; i++) { carry += (i < a.size() ? a[i] - 48 : 0) + (i < b.a.size() ? b.a[i] - 48 : 0); c.a += (carry % 10 + 48); carry /= 10; } return c.normalize(sign); } Bigint operator-(Bigint b) { if (sign != b.sign) return (*this) + b.inverseSign(); int s = sign; sign = b.sign = 1; if ((*this) < b) return ((b - (*this)).inverseSign()).normalize(-s); Bigint c; for (int i = 0, borrow = 0; i < a.size(); i++) { borrow = a[i] - borrow - (i < b.size() ? b.a[i] : 48); c.a += borrow >= 0 ? borrow + 48 : borrow + 58; borrow = borrow >= 0 ? 0 : 1; } return c.normalize(s); } Bigint operator*(Bigint b) { Bigint c( 0 ); for (int i = 0, k = a[i] - 48; i < a.size(); i++, k = a[i] - 48) { while (k--) c = c + b; b.a.insert(b.a.begin(), 0 ); } return c.normalize(sign * b.sign); } Bigint operator/(Bigint b) { if (b.size() == 1 && b.a[0] == 0 ) b.a[0] /= (b.a[0] - 48); Bigint c( 0 ), d; for (int j = 0; j < a.size(); j++) d.a += 0 ; int dSign = sign * b.sign; b.sign = 1; for (int i = a.size() - 1; i >= 0; i--) { c.a.insert(c.a.begin(), 0 ); c = c + a.substr(i, 1); while (!(c < b)) c = c - b, d.a[i]++; } return d.normalize(dSign); } Bigint operator%(Bigint b) { if (b.size() == 1 && b.a[0] == 0 ) b.a[0] /= (b.a[0] - 48); Bigint c( 0 ); b.sign = 1; for (int i = a.size() - 1; i >= 0; i--) { c.a.insert(c.a.begin(), 0 ); c = c + a.substr(i, 1); while (!(c < b)) c = c - b; } return c.normalize(sign); } void print() { if (sign == -1) putchar( - ); for (int i = a.size() - 1; i >= 0; i--) putchar(a[i]); } Bigint operator*(long long b) { long long carry = 0; Bigint c = *this; int bsign; if (b < 0) { bsign = -1; b *= -1; } else bsign = 1; for (int i = 0; i < c.a.size(); i++) { carry += (c.a[i] - 48) * b; c.a[i] = (carry % 10 + 48); carry /= 10; } while (carry) { c.a += (carry % 10 + 48); carry /= 10; } return c.normalize(sign * bsign); } }; Bigint power[2001]; void init() { power[0] = 1 ; int i; for (i = 1; i <= 2000; i++) { power[i] = power[i - 1] * 2; } } struct drive { int value; bool sell; } arr[5010]; Bigint res; void use(int buy, int sell) { if (buy == inf) { if (sell != inf) arr[sell].value = inf - 10; else return; } else { res = res + power[arr[sell].value]; for (int i = buy; i <= sell; i++) arr[i].value = inf; } } int main() { init(); int size; scanf( %d , &size); int i; char buf[200]; for (i = 0; i < size; i++) { scanf( %s %d , buf, &arr[i].value); arr[i].sell = false; if (buf[0] == s ) { arr[i].sell = true; } } res = 0 ; int k = 5000; while (k--) { int sell = inf, buy = inf, mx = -1; for (i = size - 1; i >= 0; i--) { if (arr[i].value == inf) { use(buy, sell); sell = inf; buy = inf; mx = -1; continue; } if (arr[i].sell) { if (arr[i].value == inf - 10) continue; if (arr[i].value >= mx) { mx = arr[i].value; sell = i; buy = inf; } } else { if (arr[i].value == mx && buy == inf) { buy = i; } } } use(buy, sell); } res.print(); puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_SYMBOL_V
`define SKY130_FD_SC_HS__O31AI_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 303; int n, m, d; int a[maxn], b[maxn], t[maxn]; int dt[maxn]; long long que[150001]; int id[150001]; long long dp[150001][2]; int main() { scanf( %d%d%d , &n, &m, &d); for (int i = 1; i <= m; ++i) { scanf( %d%d%d , a + i, b + i, t + i); dt[i] = t[i] - t[i - 1]; } dt[1] = n; for (int ii = 1; ii <= m; ++ii) { int i = ii % 2; int l = 1, r = 1, nl = 1, nr = 1; int lt, rt; for (int j = 1; j <= n; ++j) { lt = max(1ll, 1ll * j - 1ll * dt[ii] * d); rt = min(1ll * n, 1ll * j + 1ll * dt[ii] * d); while (nr <= rt) { while (r > l && dp[nr][1 - i] >= que[r - 1]) r--; que[r] = dp[nr][1 - i]; id[r] = nr; r++; nr++; } while (r > l && id[l] < lt) l++; dp[j][i] = que[l] + 1ll * b[ii] - 1ll * abs(a[ii] - j); } } long long ans = dp[1][m % 2]; for (int i = 2; i <= n; ++i) { ans = max(ans, dp[i][m % 2]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int n; int length; int num[1000]; int main() { scanf( %d , &n); while (n--) { int max = 0; int mark = 0; scanf( %d , &length); for (int i = 1; i <= length; i++) { scanf( %d , &num[i]); if (num[i] > (i + mark)) { mark += num[i] - i - mark; } } printf( %d n , mark); } return 0; }
|
#include <bits/stdc++.h> char s[100005], stack[100005], ss; int main() { long long n, k, now, i, i2, l, plus = 0, kid, pos; scanf( %lld %lld , &n, &k); for (i = 1; i <= k; i++) { scanf( %lld , &now); plus = 0; ss = 0; kid = n; while (kid / 2 + plus + 1 != now) { if (kid / 2 + plus + 1 < now) { stack[++ss] = R ; plus += kid / 2 + 1; kid /= 2; } else { stack[++ss] = L ; kid /= 2; } } now = kid; scanf( %s , s); l = strlen(s); for (i2 = 0; i2 < l; i2++) { if (s[i2] == R ) { if (now == 1) continue; plus += now / 2 + 1; now /= 2; stack[++ss] = R ; } else if (s[i2] == L ) { if (now == 1) continue; now /= 2; stack[++ss] = L ; } else { if (now == n) continue; if (stack[ss] == R ) plus -= now + 1; now = now * 2 + 1; ss--; } } printf( %lld n , plus + now / 2 + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Q = 100100, rt = 223, inf = 1 << 29; int ans[Q], todo[Q]; pair<int, int> look[Q]; int a[Q], b[Q]; string s; unordered_map<int, unordered_set<int>> post; map<pair<int, int>, int> ans2; unordered_map<int, vector<int>> matches; int f(int x, int xs, int y, int ys) { return max(x + xs, y + ys) - min(x, y); } int S[100000][5]; map<string, int> intern; int interned_size[500000]; int cnt = 1; int get(const string& s) { auto it = intern.find(s); if (it == end(intern)) { interned_size[cnt] = s.size(); return intern[s] = cnt++; } return it->second; } int brute(int a, int b) { int res = inf; vector<int>&ma = matches[a], &mb = matches[b]; for (int i = 0; i < ma.size(); ++i) { int j = lower_bound(begin(mb), end(mb), ma[i]) - begin(mb); if (j < mb.size()) res = min(res, f(ma[i], interned_size[a], mb[j], interned_size[b])); } return res; } int main() { cin >> s; for (int i = 0; i < s.size(); ++i) { for (int w = 1; w <= 4; ++w) { S[i][w] = get(s.substr(i, w)); matches[S[i][w]].push_back(i); } } int q; cin >> q; fill(ans, ans + q, inf); for (int i = 0; i < q; ++i) { string as, bs; cin >> as >> bs; int a = get(as), b = get(bs); if (max(matches[a].size(), matches[b].size()) < rt) { ans[i] = min(brute(a, b), brute(b, a)); } else { if (matches[a].size() < matches[b].size()) swap(a, b); post[a].insert(b); look[i] = make_pair(a, b); todo[i] = 1; } } for (auto& it : post) { const int a = it.first; auto& m = it.second; int last = matches[a][0]; for (int i = last; i < s.size(); ++i) { for (int w = 1; w <= 4; ++w) if (S[i][w] == a) last = i; for (int w = 1; w <= 4; ++w) { int b = S[i][w]; if (m.find(b) == end(m)) continue; auto st = make_pair(a, b); int sol = f(last, interned_size[a], i, interned_size[b]); auto fi = ans2.find(st); if (fi == end(ans2) || sol < fi->second) ans2[st] = sol; } } last = matches[a].back(); for (int i = last; i >= 0; --i) { for (int w = 1; w <= 4; ++w) if (S[i][w] == a) last = i; for (int w = 1; w <= 4; ++w) { int b = S[i][w]; if (m.find(b) == end(m)) continue; auto st = make_pair(a, b); int sol = f(last, interned_size[a], i, interned_size[b]); auto fi = ans2.find(st); if (fi == end(ans2) || sol < fi->second) ans2[st] = sol; } } } for (int i = 0; i < q; ++i) { if (todo[i]) ans[i] = ans2.find(look[i]) != end(ans2) ? ans2[look[i]] : inf; cout << (ans[i] == inf ? -1 : ans[i]) << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100100; int N; vector<pair<int, int> > ans; vector<int> E[maxn]; void go(int i, int t) { ans.push_back({i, t}); } void dfs(int i, int p, int t) { go(i, t); int d = (t < E[i].size()); if (!d) t -= E[i].size(), go(i, t); for (auto &j : E[i]) if (j != p) { t++; dfs(j, i, t); go(i, t); if (d && t == E[i].size()) t -= E[i].size(), go(i, t); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> N; int u, v; for (int i = 1; i < N; i++) { cin >> u >> v; E[u].push_back(v); E[v].push_back(u); } go(1, 0); int t = 0; for (auto &i : E[1]) t++, dfs(i, 1, t), go(1, t); cout << ans.size() << n ; for (auto &i : ans) cout << i.first << << i.second << n ; }
|
#include <bits/stdc++.h> int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; const double PI = acos(-1), EPS = 1e-7; const int OO = 0x3f3f3f3f, N = 1e6 + 5, mod = 1e9 + 7; using namespace std; long long gcd(long long x, long long y) { return (!y) ? x : gcd(y, x % y); } long long lcm(long long x, long long y) { return ((x / gcd(x, y)) * y); } void file() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int n, red, blue, cnt; vector<vector<int>> g; vector<int> col; pair<int, int> DFS(int v, int p = -1) { int r = (col[v] == 1), b = (col[v] == 2); for (auto u : g[v]) if (u != p) { auto tmp = DFS(u, v); cnt += (tmp.first == red && tmp.second == 0); cnt += (tmp.first == 0 && tmp.second == blue); r += tmp.first; b += tmp.second; } return make_pair(r, b); } int main() { file(); cin >> n; g = vector<vector<int>>(n + 1); col = vector<int>(n + 1); for (int i = 1; i <= n; i++) { cin >> col[i]; if (col[i] == 1) red++; if (col[i] == 2) blue++; } n--; while (n--) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } DFS(1, -1); cout << cnt; }
|
// Raster_Laser_Projector_X_Axis_Subsystem.v
// Generated using ACDS version 16.1 200
`timescale 1 ps / 1 ps
module Raster_Laser_Projector_X_Axis_Subsystem (
input wire clk_clk, // clk.clk
input wire hsync_reset_reset_n, // hsync_reset.reset_n
input wire hsync_target_clk, // hsync_target.clk
input wire reset_reset_n // reset.reset_n
);
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> PI_Controller_0:reset
PI_Controller pi_controller_0 (
.clk (clk_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.control (), // control_out.ctrl
.error () // error.error
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// bi-directional monaural interface to AC97
//
///////////////////////////////////////////////////////////////////////////////
module lab5audio (
input wire clock_27mhz,
input wire reset,
input wire [4:0] volume,
output wire [7:0] audio_in_data,
input wire [7:0] audio_out_data,
output wire ready,
output reg audio_reset_b, // ac97 interface signals
output wire ac97_sdata_out,
input wire ac97_sdata_in,
output wire ac97_synch,
input wire ac97_bit_clock
);
wire [7:0] command_address;
wire [15:0] command_data;
wire command_valid;
wire [19:0] left_in_data, right_in_data;
wire [19:0] left_out_data, right_out_data;
// wait a little before enabling the AC97 codec
reg [9:0] reset_count;
always @(posedge clock_27mhz) begin
if (reset) begin
audio_reset_b = 1'b0;
reset_count = 0;
end else if (reset_count == 1023)
audio_reset_b = 1'b1;
else
reset_count = reset_count+1;
end
wire ac97_ready;
ac97 ac97(.ready(ac97_ready),
.command_address(command_address),
.command_data(command_data),
.command_valid(command_valid),
.left_data(left_out_data), .left_valid(1'b1),
.right_data(right_out_data), .right_valid(1'b1),
.left_in_data(left_in_data), .right_in_data(right_in_data),
.ac97_sdata_out(ac97_sdata_out),
.ac97_sdata_in(ac97_sdata_in),
.ac97_synch(ac97_synch),
.ac97_bit_clock(ac97_bit_clock));
// ready: one cycle pulse synchronous with clock_27mhz
reg [2:0] ready_sync;
always @ (posedge clock_27mhz) ready_sync <= {ready_sync[1:0], ac97_ready};
assign ready = ready_sync[1] & ~ready_sync[2];
reg [7:0] out_data;
always @ (posedge clock_27mhz)
if (ready) out_data <= audio_out_data;
assign audio_in_data = left_in_data[19:12];
assign left_out_data = {out_data, 12'b000000000000};
assign right_out_data = left_out_data;
// generate repeating sequence of read/writes to AC97 registers
ac97commands cmds(.clock(clock_27mhz), .ready(ready),
.command_address(command_address),
.command_data(command_data),
.command_valid(command_valid),
.volume(volume),
.source(3'b000)); // mic
endmodule
// assemble/disassemble AC97 serial frames
module ac97 (
output reg ready,
input wire [7:0] command_address,
input wire [15:0] command_data,
input wire command_valid,
input wire [19:0] left_data,
input wire left_valid,
input wire [19:0] right_data,
input wire right_valid,
output reg [19:0] left_in_data, right_in_data,
output reg ac97_sdata_out,
input wire ac97_sdata_in,
output reg ac97_synch,
input wire ac97_bit_clock
);
reg [7:0] bit_count;
reg [19:0] l_cmd_addr;
reg [19:0] l_cmd_data;
reg [19:0] l_left_data, l_right_data;
reg l_cmd_v, l_left_v, l_right_v;
initial begin
ready <= 1'b0;
// synthesis attribute init of ready is "0";
ac97_sdata_out <= 1'b0;
// synthesis attribute init of ac97_sdata_out is "0";
ac97_synch <= 1'b0;
// synthesis attribute init of ac97_synch is "0";
bit_count <= 8'h00;
// synthesis attribute init of bit_count is "0000";
l_cmd_v <= 1'b0;
// synthesis attribute init of l_cmd_v is "0";
l_left_v <= 1'b0;
// synthesis attribute init of l_left_v is "0";
l_right_v <= 1'b0;
// synthesis attribute init of l_right_v is "0";
left_in_data <= 20'h00000;
// synthesis attribute init of left_in_data is "00000";
right_in_data <= 20'h00000;
// synthesis attribute init of right_in_data is "00000";
end
always @(posedge ac97_bit_clock) begin
// Generate the sync signal
if (bit_count == 255)
ac97_synch <= 1'b1;
if (bit_count == 15)
ac97_synch <= 1'b0;
// Generate the ready signal
if (bit_count == 128)
ready <= 1'b1;
if (bit_count == 2)
ready <= 1'b0;
// Latch user data at the end of each frame. This ensures that the
// first frame after reset will be empty.
if (bit_count == 255) begin
l_cmd_addr <= {command_address, 12'h000};
l_cmd_data <= {command_data, 4'h0};
l_cmd_v <= command_valid;
l_left_data <= left_data;
l_left_v <= left_valid;
l_right_data <= right_data;
l_right_v <= right_valid;
end
if ((bit_count >= 0) && (bit_count <= 15))
// Slot 0: Tags
case (bit_count[3:0])
4'h0: ac97_sdata_out <= 1'b1; // Frame valid
4'h1: ac97_sdata_out <= l_cmd_v; // Command address valid
4'h2: ac97_sdata_out <= l_cmd_v; // Command data valid
4'h3: ac97_sdata_out <= l_left_v; // Left data valid
4'h4: ac97_sdata_out <= l_right_v; // Right data valid
default: ac97_sdata_out <= 1'b0;
endcase
else if ((bit_count >= 16) && (bit_count <= 35))
// Slot 1: Command address (8-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_addr[35-bit_count] : 1'b0;
else if ((bit_count >= 36) && (bit_count <= 55))
// Slot 2: Command data (16-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_data[55-bit_count] : 1'b0;
else if ((bit_count >= 56) && (bit_count <= 75)) begin
// Slot 3: Left channel
ac97_sdata_out <= l_left_v ? l_left_data[19] : 1'b0;
l_left_data <= { l_left_data[18:0], l_left_data[19] };
end
else if ((bit_count >= 76) && (bit_count <= 95))
// Slot 4: Right channel
ac97_sdata_out <= l_right_v ? l_right_data[95-bit_count] : 1'b0;
else
ac97_sdata_out <= 1'b0;
bit_count <= bit_count+1;
end // always @ (posedge ac97_bit_clock)
always @(negedge ac97_bit_clock) begin
if ((bit_count >= 57) && (bit_count <= 76))
// Slot 3: Left channel
left_in_data <= { left_in_data[18:0], ac97_sdata_in };
else if ((bit_count >= 77) && (bit_count <= 96))
// Slot 4: Right channel
right_in_data <= { right_in_data[18:0], ac97_sdata_in };
end
endmodule
// issue initialization commands to AC97
module ac97commands (
input wire clock,
input wire ready,
output wire [7:0] command_address,
output wire [15:0] command_data,
output reg command_valid,
input wire [4:0] volume,
input wire [2:0] source
);
reg [23:0] command;
reg [3:0] state;
initial begin
command <= 4'h0;
// synthesis attribute init of command is "0";
command_valid <= 1'b0;
// synthesis attribute init of command_valid is "0";
state <= 16'h0000;
// synthesis attribute init of state is "0000";
end
assign command_address = command[23:16];
assign command_data = command[15:0];
wire [4:0] vol;
assign vol = 31-volume; // convert to attenuation
always @(posedge clock) begin
if (ready) state <= state+1;
case (state)
4'h0: // Read ID
begin
command <= 24'h80_0000;
command_valid <= 1'b1;
end
4'h1: // Read ID
command <= 24'h80_0000;
4'h3: // headphone volume
command <= { 8'h04, 3'b000, vol, 3'b000, vol };
4'h5: // PCM volume
command <= 24'h18_0808;
4'h6: // Record source select
command <= { 8'h1A, 5'b00000, source, 5'b00000, source};
4'h7: // Record gain = max
command <= 24'h1C_0F0F;
4'h9: // set +20db mic gain
command <= 24'h0E_8048;
4'hA: // Set beep volume
command <= 24'h0A_0000;
4'hB: // PCM out bypass mix1
command <= 24'h20_8000;
default:
command <= 24'h80_0000;
endcase // case(state)
end // always @ (posedge clock)
endmodule // ac97commands
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