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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_16_V
`define SKY130_FD_SC_MS__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_16_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1000011; const long long INF = (1 << 29) + 123; const long long MOD = 1000000007; const long double PI = 4 * atan((long double)1); int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, w; cin >> n >> w; int l[n]; int x; long long ans[w], pf[w + 1]; for (int i = 0; i < w + 1; i++) ans[i] = pf[i] = 0; for (int i = 0; i < n; i++) { cin >> l[i]; deque<pair<long long, int>> store; int window = w - l[i] + 1; int best = -INF; for (int j = 0; j < w; j++) { if (j < l[i]) { cin >> x; while (!store.empty() && x >= store.back().first) store.pop_back(); store.push_back(make_pair(x, j)); best = max(best, x); } else if (j == l[i] && j < window) { j = window; if (best >= 0) { pf[l[i]] += best; pf[window] -= best; } else { if (window - 1 < w - window + 1) { pf[window - 1] += best; pf[w - window + 1] -= best; } } } if (j == w) break; while (store.front().second <= j - window) store.pop_front(); if (store.front().first > 0 || (j >= window - 1 && j <= w - window)) { ans[j] += 1LL * store.front().first; } } } long long total = 0; for (int i = 0; i < w; i++) { total += pf[i]; cout << ans[i] + total << ; } cout << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:28:58 11/18/2013
// Design Name: top_module
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/tec-drums/top_module_test.v
// Project Name: tec-drums
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_module_test;
// Inputs
reg clock;
reg reset;
// Outputs
wire lrck;
wire mclk;
wire sdin;
wire sclk;
wire [15:0] left_data_o;
wire [15:0] right_data_o;
// Instantiate the Unit Under Test (UUT)
top_module uut (
.clock(clock),
.reset(reset),
.lrck(lrck),
.mclk(mclk),
.sdin(sdin),
.sclk(sclk),
.left_data_o(left_data_o),
.right_data_o(right_data_o)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int v, fr; node(){}; node(int a, int b) { v = a, fr = b; } } C[115 + 115]; long long f[115 + 115][115], K; int ar[115 + 115], n, m, P[115][115]; inline bool cmp(node a, node b) { return a.v < b.v; } inline void pluss(long long &p, long long p1) { p += p1; if (p > 2000000000000000011LL) p = 2000000000000000011LL; } int main() { int i, j, e, t, k; cin >> n >> m >> K; for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) scanf( %d , &P[i][j]); for (i = 1; i < n + m; ++i) C[i] = node((~0U >> 1), i); for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) C[i + j - 1].v = min(C[i + j - 1].v, P[i][j]); sort(C + 1, C + n + m, cmp); for (e = ((n + m) >> 1) + 1, t = 1; t < n + m; ++t) { ar[C[t].fr] = 1; memset(f, 0, sizeof(f)); for (f[0][0] = i = 1; i < n + m; ++i) { if (ar[i]) { k = (ar[i] == 1 ? -1 : 1); for (j = 0; j <= e; ++j) if (j + k > -1) pluss(f[i][j], f[i - 1][j + k]); } else for (j = 0; j <= e; ++j) { if (j > 0) pluss(f[i][j], f[i - 1][j - 1]); pluss(f[i][j], f[i - 1][j + 1]); } } if (f[n + m - 1][0] < K) { ar[C[t].fr] = 2; K -= f[n + m - 1][0]; } } for (i = 1; i <= n; ++i) { for (j = 1; j <= m; ++j) { if (ar[i + j - 1] == 1) printf( ( ); else printf( ) ); } printf( n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int Left[1000010]; int mini[1000010]; int main(void) { cin.tie(0); ios::sync_with_stdio(false); int n; cin >> n; string S; cin >> S; for (int i = 0; i < S.length(); i++) { if (S[i] == ( ) Left[i + 1] = Left[i] + 1; else Left[i + 1] = Left[i] - 1; } for (int i = 0; i < 1000010; i++) mini[i] = 2000000000; int ans = 0; if (Left[n] == 2) { for (int i = n; i >= 0; i--) mini[i] = min(mini[i + 1], Left[i]); for (int i = 0; i < n; i++) { if (i != 0 && Left[i - 1] < 0) break; if (S[i] == ( && mini[i + 1] >= 2 && Left[n] == 2) ans++; } } else if (Left[n] == -2) { for (int i = n; i >= 0; i--) mini[i] = min(mini[i + 1], Left[i]); for (int i = 0; i < n - 1; i++) { if (i != 0 && Left[i - 1] < 0) break; if (S[i] == ) && mini[i] >= -2) ans++; } } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, x, m = 0, sum = 0; cin >> n >> x; int *arr = new int[n]; for (long long i = 0; i < n; i++) cin >> arr[i], sum += arr[i]; if (sum > 0) while (sum > 0) { sum -= x; m++; } else while (sum < 0) { sum += x; m++; } cout << m; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } class dsu { public: vector<int> p; int n; dsu(int _n) : n(_n) { p.resize(n); iota(p.begin(), p.end(), 0); } inline int get(int x) { return (x == p[x] ? x : (p[x] = get(p[x]))); } inline bool unite(int x, int y) { x = get(x); y = get(y); if (x != y) { p[x] = y; return true; } return false; } }; const int MAX = 100010; int bound[MAX]; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; assert(1 <= tt && tt <= 1000); int x = 0; while (tt--) { int n; cin >> n; assert(n >= 1); vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); for (int i = 0; i < n - 1; i++) { assert(v[i] < v[i + 1]); } assert(1 <= v[0]); assert(v[n - 1] <= 100000); { int ptr = -1; for (int val = 0; val < MAX; val++) { if (ptr + 1 < n && v[ptr + 1] == val) { ++ptr; } bound[val] = ptr; } } vector<vector<int>> who(1, vector<int>(n, -1)); vector<dsu> d(1, dsu(n + 1)); vector<bool> seen; for (int i = n - 1; i >= 0; i--) { int start = 0; int j = 0; while (start < i) { if (j == (int)who.size()) { who.emplace_back(n, -1); d.emplace_back(n + 1); } int finish = i - 1; int tmp = who[j][i]; if (tmp != -1) { int val = v[i] - (v[tmp] - v[i]); finish = (val <= 0 ? -1 : bound[val]); } if (start <= finish) { int pos = d[j].get(start); while (pos <= finish) { who[j][pos] = i; d[j].unite(pos, pos + 1); pos = d[j].get(pos); } start = finish + 1; } ++j; } int g = 0; while (g < (int)who.size() && who[g][i] != -1) { ++g; } if (g >= (int)seen.size()) { seen.resize(g + 1); } seen[g] = true; } int g = 0; while (g < (int)seen.size() && seen[g]) { ++g; } x ^= g; 42; } cout << (x > 0 ? YES : NO ) << n ; return 0; }
|
// Double pumped single precision floating point add/sub
// Latency = 9 kernel clocks
//
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_add_sub_dbl_pumped
#(
// Bit width of a single precision float
parameter WIDTH=32
)
(
input clock,
input clock2x,
input enable,
input add_sub,
input [WIDTH-1:0] a1,
input [WIDTH-1:0] b1,
input [WIDTH-1:0] a2,
input [WIDTH-1:0] b2,
output reg [WIDTH-1:0] y1,
output reg [WIDTH-1:0] y2
);
reg [WIDTH-1:0] a1_reg;
reg [WIDTH-1:0] b1_reg;
reg [WIDTH-1:0] a2_reg;
reg [WIDTH-1:0] b2_reg;
reg add_sub_reg;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg clk_90deg, sel2x /* synthesis preserve */;
reg [WIDTH-1:0] fp_add_sub_inp_a;
reg [WIDTH-1:0] fp_add_sub_inp_b;
reg fp_add_sub_inp_add_sub;
wire [WIDTH-1:0] fp_add_sub_res;
reg [WIDTH-1:0] fp_add_sub_res_reg;
reg [WIDTH-1:0] fp_add_sub_res_del1_2x_cycle;
//Register before double pumping
always@(posedge clock)
begin
if (enable) a1_reg <= a1;
if (enable) a2_reg <= a2;
if (enable) b1_reg <= b1;
if (enable) b2_reg <= b2;
if (enable) add_sub_reg <= add_sub;
end
generate
if (WIDTH == 32)
acl_fp_add_sub_fast the_sub(
.add_sub(fp_add_sub_inp_add_sub),
.clk_en(enable),
.clock(clock2x),
.dataa(fp_add_sub_inp_a),
.datab(fp_add_sub_inp_b),
.result(fp_add_sub_res));
else // WIDTH == 64
acl_fp_add_sub_fast_double the_sub(
.add_sub(fp_add_sub_inp_add_sub),
.enable(enable),
.clock(clock2x),
.dataa(fp_add_sub_inp_a),
.datab(fp_add_sub_inp_b),
.result(fp_add_sub_res));
endgenerate
//For testing purposes
//always@(posedge clk2x)
//begin
// fp_sub_res1 <= fp_sub_inp_a + fp_sub_inp_b;
// fp_sub_res <= fp_sub_res1;
//end
always@(posedge clock2x)
begin
if (enable) fp_add_sub_res_del1_2x_cycle <= fp_add_sub_res_reg;
if (enable) fp_add_sub_inp_a <= (!sel2x) ? a1_reg : a2_reg;
if (enable) fp_add_sub_inp_b <= (!sel2x) ? b1_reg : b2_reg;
if (enable) fp_add_sub_inp_add_sub <= add_sub_reg;
if (enable) fp_add_sub_res_reg <= fp_add_sub_res;
end
always@(posedge clock)
begin
if (enable) y1 <= fp_add_sub_res_del1_2x_cycle;
if (enable) y2 <= fp_add_sub_res_reg;
end
//Convert clock to data signal
always@(negedge clock2x)
clk_90deg<=clock;
always@(posedge clock2x)
sel2x<=clk_90deg; //This should give you exactly sel2x=~clock
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_36x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_36x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [35:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [35:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [35:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [35:0] q = sub_wire2[35:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 36,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "36"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "36"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL data[35..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL q[35..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_36x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXH = 1000000; const int MAXW = 1000000; const int MAXN = 100000; const int MOD = 1000000007; typedef struct R { int x1, y1, x2, y2; } R; int h, w, n; int shead[MAXH], snxt[MAXN]; int thead[MAXH], tnxt[MAXN]; R r[MAXN]; int cur[MAXN], ncur; int sval[4 * MAXW]; int slazy[4 * MAXW]; inline void inc(int &a, int b) { if ((a += b) >= MOD) a -= MOD; } void spush(int x) { if (sval[x] != -1) { sval[2 * x + 1] = sval[2 * x + 2] = sval[x]; slazy[2 * x + 1] = slazy[2 * x + 2] = 0; sval[x] = -1; } if (slazy[x] != 0) { inc(slazy[2 * x + 1], slazy[x]), inc(slazy[2 * x + 2], slazy[x]); slazy[x] = 0; } } void sset(int x, int l, int h, int L, int H, int VAL) { if (h < L || l > H) return; if (L <= l && h <= H) { sval[x] = VAL, slazy[x] = 0; return; } spush(x); int m = l + (h - l) / 2; sset(2 * x + 1, l, m, L, H, VAL); sset(2 * x + 2, m + 1, h, L, H, VAL); } void sinc(int x, int l, int h, int L, int H, int BY) { if (h < L || l > H) return; if (L <= l && h <= H) { inc(slazy[x], BY); return; } spush(x); int m = l + (h - l) / 2; sinc(2 * x + 1, l, m, L, H, BY); sinc(2 * x + 2, m + 1, h, L, H, BY); } int sget(int x, int l, int h, int IDX) { if (sval[x] != -1) return sval[x] + slazy[x]; spush(x); int m = l + (h - l) / 2; return IDX <= m ? sget(2 * x + 1, l, m, IDX) : sget(2 * x + 2, m + 1, h, IDX); } void run() { scanf( %d%d%d , &h, &w, &n); for (int x = (0); x < (h); ++x) shead[x] = thead[x] = -1; for (int i = (0); i < (n); ++i) { scanf( %d%d%d%d , &r[i].x1, &r[i].y1, &r[i].x2, &r[i].y2); --r[i].x1, --r[i].y1, --r[i].x2, --r[i].y2; snxt[i] = shead[r[i].x1], shead[r[i].x1] = i; tnxt[i] = thead[r[i].x2], thead[r[i].x2] = i; } multiset<int> have; have.insert(w); sval[0] = slazy[0] = 0; sset(0, 0, w - 1, 0, 0, 1); for (int x = (0); x < (h); ++x) { for (int z = shead[x]; z != -1; z = snxt[z]) sset(0, 0, w - 1, r[z].y1, r[z].y2, 0), have.insert(r[z].y1); ncur = 0; if (x == 0) cur[ncur++] = 0; else for (int z = thead[x - 1]; z != -1; z = tnxt[z]) { if (r[z].y1 != 0) cur[ncur++] = r[z].y1 - 1; multiset<int>::iterator it = have.lower_bound(r[z].y1); have.erase(it); } sort(cur, cur + ncur); ncur = unique(cur, cur + ncur) - cur; for (int i = ncur - 1; i >= 0; --i) { int y = cur[i]; int val = sget(0, 0, w - 1, y); if (val == 0) continue; multiset<int>::iterator it = have.lower_bound(y); int ny = *it - 1; if (y + 1 <= ny) sinc(0, 0, w - 1, y + 1, ny, val); } } int ret = sget(0, 0, w - 1, w - 1); printf( %d n , ret); } int main() { run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { std::cerr << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); std::cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } long long int solve() { long long int n; cin >> n; std::vector<long long int> v; long long int seg = 0; long long int count = 0; for (long long int i = 0; i < n; i++) { long long int a; cin >> a; v.push_back(a); if (a != i + 1) { count++; } else { if (count) { seg++; count = 0; } } } if (count) { seg++; } if (seg == 0) { cout << 0 << n ; } else if (seg == 1) { cout << 1 << n ; } else { cout << 2 << n ; } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int T = 1; cin >> T; while (T--) { solve(); } return 0; }
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_simulate.v"
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga(
spcki, miso, mosi, ncs,
pck0i, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spcki, mosi, ncs;
output miso;
input pck0i, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
//assign pck0 = pck0i;
IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
.O(pck0),
.I(pck0i)
);
//assign spck = spcki;
IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
.O(spck),
.I(spcki)
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0];
4'b0010: divisor <= shift_reg[7:0];
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lo_is_125khz;
assign lo_is_125khz = conf_word[3];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation;
assign hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848;
assign hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop;
assign hi_read_rx_xcorr_snoop = conf_word[1];
// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
wire hi_read_rx_xcorr_quarter;
assign hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
lo_read lr(
pck0, ck_1356meg, ck_1356megb,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
cross_hi, cross_lo,
lr_dbg,
lo_is_125khz, divisor
);
lo_passthru lp(
pck0, ck_1356meg, ck_1356megb,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
adc_d, lp_adc_clk,
lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
cross_hi, cross_lo,
lp_dbg, divisor
);
lo_simulate ls(
pck0, ck_1356meg, ck_1356megb,
ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
adc_d, ls_adc_clk,
ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
cross_hi, cross_lo,
ls_dbg, divisor
);
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF simulated tag (generic)
// 010 -- HF reader, transmitting to tag; modulation depth selectable
// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 100 -- HF simulated tag
// 101 -- HF ISO14443-A
// 110 -- LF passthrough
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/22 19:39:56 lampret
// Fixed parameters in generic sprams.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [7:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [7:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x24_bist artisan_ssp(
`else
art_hssp_64x24 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x24_bist vs_ssp(
`else
vs_hdsp_64x24 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({3'b000, addr}),
.DI({8'h00,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_xlconcat_0_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN\
23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/10 10:07:18
// Design Name:
// Module Name: clock_100kHz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_100kHz(clk,rst_n,out_100kHz);
input clk,rst_n;
output reg out_100kHz;
reg [15:0] counter;
always @ (posedge clk or negedge rst_n)
if (!rst_n)
begin
out_100kHz <= 0;
counter <= 0;
end
else
if (counter == 16'd499) //clk=100MHz
begin
out_100kHz <= !out_100kHz;
counter <= 0;
end
else
begin
out_100kHz <= out_100kHz;
counter <= counter + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000; int main(int argc, char *argv[]) { string s; vector<pair<char, int> > count; int n; cin >> s; n = s.size(); for (int i = 0; i < n;) { int cnt = 0; int prev = s[i]; while (s[i] == prev) { cnt++; i++; } count.push_back(make_pair(prev, cnt)); } for (int i = 0; i < count.size(); i++) { if (count[i].second >= 3) count[i].second = 2; } for (int i = 0; i < count.size() - 1; i++) { if (count[i].second == 2 && count[i + 1].second == 2) count[i + 1].second = 1; } for (int i = 0; i < count.size(); i++) { for (int j = 0; j < count[i].second; j++) cout << count[i].first; } }
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : write_back.v
// KEYWORDS : write-back, multiplexer, combinational, dlx
// -----------------------------------------------------------------------------
// PURPOSE: Selects the data which will be stores in register file.
// -----------------------------------------------------------------------------
module write_back
#(
parameter DATA_WIDTH = 32,
parameter REG_ADDR_WIDTH = 5
)
(
input [DATA_WIDTH-1:0] mem_data_in,
input [DATA_WIDTH-1:0] alu_data_in,
input [DATA_WIDTH-1:0] hi_data_in,
// input reg_wr_en_in,
// input [REG_ADDR_WIDTH-1:0] reg_wr_addr_in,
input [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_in,
input [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_in,
input reg_a_wr_en_in,
input reg_b_wr_en_in,
input write_back_mux_sel,
output [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
output [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
output [DATA_WIDTH-1:0] reg_a_wr_data_out,
output [DATA_WIDTH-1:0] reg_b_wr_data_out,
output reg_a_wr_en_out,
output reg_b_wr_en_out
);
//verificar se vai extender o sinal apenas de uma forma
assign reg_a_wr_data_out = write_back_mux_sel?mem_data_in:alu_data_in;
assign reg_b_wr_data_out = hi_data_in;
assign reg_a_wr_en_out = reg_a_wr_en_in;
assign reg_b_wr_en_out = reg_b_wr_en_in;
assign reg_a_wr_addr_out = reg_a_wr_addr_in;
assign reg_b_wr_addr_out = reg_b_wr_addr_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int N = 2e5 + 7; int n, m, i, j, a, b; int check(int x, int y) { int dis1 = abs(x - i); int dis2 = abs(y - j); if (dis1 % a == 0 && dis2 % b == 0) { int p = dis1 / a; int q = dis2 / b; if (p == q) return q; if ((p + q) & 1) return inf; if (p < q) { if (i + a > n && i - a < 1) return inf; } else { if (j + b > m && j - b < 1) return inf; } return max(p, q); } else return inf; } int main() { scanf( %d , &n); scanf( %d , &m); scanf( %d , &i); scanf( %d , &j); scanf( %d , &a); scanf( %d , &b); int ans = inf; ans = min(ans, check(1, 1)); ans = min(ans, check(n, 1)); ans = min(ans, check(1, m)); ans = min(ans, check(n, m)); if (ans == inf) puts( Poor Inna and pony! ); else printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> long long ans; int F[50000001], n, m, N; char str[10001]; void dfs(int x, int bit, int key) { if (x > 3) { if (bit) F[bit] += key; return; } dfs(x + 1, bit, key); int v = str[x] - a ; dfs(x + 1, bit | (1 << v), -key); } int main() { scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %s , str + 1); dfs(1, 0, -1); } n = 24; N = 1 << n; int res = 0; for (int i = 0; i < N; i++) res += F[i]; for (int i = 1; i < N; i <<= 1) for (int j = 0; j < N; j++) if (i & j) { F[j] += F[j - i]; } for (int i = 0; i < N; i++) ans ^= (long long)F[i] * F[i]; printf( %I64d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 300005, N = 333333; const int D = 1e9 + 7, inv2 = 5e8 + 4; int n, Q, a[MAXN], mul[N + 233], inv[N + 233]; int val[MAXN << 1]; int id[MAXN], w[MAXN]; int tim, len; struct node { int v, id; node() {} node(int vv, int ii) { v = vv, id = ii; } } s[MAXN << 1]; bool operator<(const node &aa, const node &bb) { if (aa.v != bb.v) return aa.v < bb.v; return aa.id < bb.id; } int v0[MAXN << 4], v1[MAXN << 4], sum[MAXN << 4], cnt[MAXN << 4]; void up(int p) { cnt[p] = cnt[p << 1] + cnt[p << 1 | 1]; sum[p] = (sum[p << 1] + sum[p << 1 | 1] + 1ll * v0[p << 1] * v1[p << 1 | 1] % D * inv[cnt[p << 1]]) % D; v0[p] = (v0[p << 1] + 1ll * v0[p << 1 | 1] * mul[cnt[p << 1]]) % D; v1[p] = (v1[p << 1] + 1ll * v1[p << 1 | 1] * inv[cnt[p << 1]]) % D; } void insert(int p, int l, int r, int x) { if (l == r) { cnt[p] = 1, sum[p] = 0; v0[p] = val[x]; v1[p] = 1ll * val[x] * inv[1] % D; return; } int mid = (l + r) >> 1; if (x <= mid) insert(p << 1, l, mid, x); else insert(p << 1 | 1, mid + 1, r, x); up(p); } void remove(int p, int l, int r, int x) { if (l == r) return (void)(cnt[p] = sum[p] = v0[p] = v1[p] = 0); int mid = (l + r) >> 1; if (x <= mid) remove(p << 1, l, mid, x); else remove(p << 1 | 1, mid + 1, r, x); up(p); } int main() { mul[0] = inv[0] = 1; for (int i = 1; i <= N; i++) mul[i] = mul[i - 1] * 2 % D; for (int i = 1; i <= N; i++) inv[i] = 1ll * inv[i - 1] * inv2 % D; scanf( %d , &n); tim = -n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), s[++len] = node(a[i], ++tim); scanf( %d , &Q); for (int i = 1; i <= Q; i++) { scanf( %d%d , &id[i], &w[i]); s[++len] = node(w[i], ++tim); } sort(s + 1, s + len + 1); for (int i = 1; i <= len; i++) { val[i] = s[i].v; if (s[i].id <= 0) a[s[i].id + n] = i; else w[s[i].id] = i; } for (int i = 1; i <= n; i++) insert(1, 1, len, a[i]); printf( %d n , sum[1]); for (int i = 1; i <= Q; i++) { remove(1, 1, len, a[id[i]]); insert(1, 1, len, w[i]); a[id[i]] = w[i]; printf( %d n , sum[1]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Node { int a, b, id; } p[100005]; bool mark[100005]; bool cmp1(const Node &p1, const Node &p2) { if (p1.b != p2.b) return p1.b > p2.b; else return p1.a < p2.a; } bool cmp2(const Node &p1, const Node &p2) { if (p1.a != p2.a) return p1.a > p2.a; else return p1.b > p2.b; } int main() { int n, p1, k; cin >> n >> p1 >> k; for (int i = 0; i < n; i++) { scanf( %d%d , &p[i].a, &p[i].b); p[i].id = i + 1; } sort(p, p + n, cmp1); sort(p, p + n - p1 + k, cmp2); for (int i = 0; i < k; i++) mark[p[i].id] = true; sort(p, p + n - p1 + k, cmp1); p1 -= k; for (int i = 0; i < n; i++) { if (k && mark[p[i].id]) --k; else if (!k && p1) { mark[p[i].id] = true; --p1; } } for (int i = 1; i <= n; i++) if (mark[i]) printf( %d , i); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, tmp; long long A[1005]; long long B[1005]; long long Acost(int q) { q *= 4; long long ret = 0; for (int i = 1; i <= n; i++) { long long tmp2 = i * 4 - 2 - q; ret += A[i] * tmp2 * tmp2; } return ret; } long long Bcost(int q) { q *= 4; long long ret = 0; for (int i = 1; i <= m; i++) { long long tmp2 = i * 4 - 2 - q; ret += B[i] * tmp2 * tmp2; } return ret; } int ansx, ansy; long long sumx = LLONG_MAX, sumy = LLONG_MAX; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> tmp; A[i] += tmp; B[j] += tmp; } } for (int i = 0; i <= n; i++) { long long tmp3 = Acost(i); if (tmp3 < sumx) { ansx = i; sumx = tmp3; } } for (int i = 0; i <= m; i++) { long long tmp3 = Bcost(i); if (tmp3 < sumy) { ansy = i; sumy = tmp3; } } cout << sumx + sumy << endl; cout << ansx << << ansy << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ms__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, x, k = 0; cin >> n; vector<int> a; for (i = 0; i < n; i++) { cin >> x; a.push_back(x); } sort(a.begin(), a.end()); for (i = 0; i < n; i++) { if (a[i] % 2 != 0) k++; } int y = min(k, n - k); cout << y << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); if (n == 1) { printf( a na nb nb n ); } else if (n == 2) { printf( aa nbb ncc ndd n ); } else if (n == 3) { printf( aab n ); printf( ccb n ); printf( baa n ); printf( bcc n ); } else { char a[4][105]; int i, j; if (n % 2 == 0) { a[0][0] = a ; a[0][1] = a ; a[1][0] = b ; a[2][0] = b ; a[3][0] = a ; a[3][1] = a ; a[0][n - 2] = a[0][n - 1] = y ; a[1][n - 1] = a[2][n - 1] = z ; a[3][n - 2] = a[3][n - 1] = y ; for (i = 1;; i += 2) { a[1][i] = a[1][i + 1] = g + ((i / 2) % 2) * 2; a[2][i] = a[2][i + 1] = h + ((i / 2) % 2) * 2; if (i + 1 == n - 2) break; a[0][i + 1] = a[0][i + 2] = m + ((i / 2) % 2) * 2; a[3][i + 1] = a[3][i + 2] = n + ((i / 2) % 2) * 2; } } else { a[0][0] = a[1][0] = a ; a[2][0] = a[2][1] = b ; a[3][0] = a[3][1] = c ; a[0][n - 1] = a[0][n - 2] = z ; a[1][n - 1] = a[1][n - 2] = y ; a[2][n - 1] = a[3][n - 1] = x ; for (i = 1; i < n - 2; i++) a[0][i] = g + (((i - 1) / 2) % 2); for (i = 1; i < n - 2; i++) a[1][i] = i + (((i - 1) / 2) % 2); for (i = 2; i < n - 1; i++) a[2][i] = k + (((i) / 2) % 2); for (i = 2; i < n - 1; i++) a[3][i] = n + (((i) / 2) % 2); } a[0][n] = a[1][n] = a[2][n] = a[3][n] = 0 ; printf( %s n%s n%s n%s n , a[0], a[1], a[2], a[3]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int n, i, j; cin >> n; vector<int> icons(n); for (i = 0; i < n; i++) { cin >> icons[i]; } vector<int> num; sort(icons.begin(), icons.end()); int cnt = 1; for (i = 1; i < icons.size(); i++) { if (icons[i] == icons[i - 1]) { cnt++; } else { num.push_back(cnt); cnt = 1; } } num.push_back(cnt); int x = num[0] + 1; int minNum = 1e9 + 7; for (i = 1; i <= x; i++) { int sum = 0; for (j = 0; j < num.size(); j++) { int q = ceil((float)num[j] / i); if ((i - 1) * q > num[j]) { sum = 1e9 + 7; break; } sum += q; } if (sum < minNum) minNum = sum; } cout << minNum << endl; } return 0; }
|
module Seg7_integer(a_in , s_out);
input [3:0] a_in;
output [7:0] s_out;
reg [7:0] temp;
assign s_out = temp;
always @(a_in) begin
case (a_in)
/*segdp ~ seg a*/
4'b0000: temp = 8'b00111111;
4'b0001: temp = 8'b00000110;
4'b0010: temp = 8'b01011011;
4'b0011: temp = 8'b01001111;
4'b0100: temp = 8'b01100110;
4'b0101: temp = 8'b01101101;
4'b0110: temp = 8'b01111101;
4'b0111: temp = 8'b00100111;
4'b1000: temp = 8'b01111111;
4'b1001: temp = 8'b01101111;
default: temp = 8'b00000000;
endcase
end
endmodule
module Seg7_sign(a_in , s_out);
input a_in;
output [7:0] s_out;
reg [7:0] temp;
assign s_out = temp;
always @(a_in) begin
if(a_in == 1) begin
temp = 8'b01000000;
end
else begin
temp = 8'b00000000;
end
end
endmodule
module Seg7(c_in , s_out);
input [16:0] c_in;
output [39:0] s_out;
Seg7_sign seg7_1(
.a_in(c_in[16]),
.s_out(s_out[39:32])
);
Seg7_integer seg7_2(
.a_in(c_in[15:12]),
.s_out(s_out[31:24])
);
Seg7_integer seg7_3(
.a_in(c_in[11:8]),
.s_out(s_out[23:16])
);
Seg7_integer seg7_4(
.a_in(c_in[7:4]),
.s_out(s_out[15:8])
);
Seg7_integer seg7_5(
.a_in(c_in[3:0]),
.s_out(s_out[7:0])
);
endmodule
|
#include <bits/stdc++.h> #define ll long long #define II pair<int,int> #define fi first #define se second #define task test using namespace std; void Init(){ ios::sync_with_stdio(0); cin.tie(0);cout.tie(0); } int n; int a[200001]; int res; int d(II &a,II &b){ return abs(a.fi-b.fi)+b.se-a.se; } bool Check(int i,int j,int k){ II p={a[i],i}; II q={a[j],j}; II r={a[k],k}; //int s=d( p,q )+d( q,r ),S=d( p,r ); //cout<<i<< <<j<< <<k<< <<s<< <<S<< n ; return( d( p,q )+d( q,r )==d( p,r ) ); } bool Cal(int l,int r){ for(int i=l;i<r;++i) for(int j=i+1;j<r;++j) if(Check(i,j,r))return 1; res++; return 0; } void Solve(){ cin>>n; while(cin>>n){ for(int i=1;i<=n;++i)cin>>a[i]; res=0; for(int i=1;i<=n;++i) for(int j=i+2;j<=n;++j){ if(Cal(i,j))break; //cout<<i<< <<j<< n ; } cout<<res+n+n-1<< n ; } } int main(){ Init(); Solve(); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; const long long mod = 1e9 + 7; struct Matrix { int n, m; long long a[10][10]; Matrix() { memset(this->a, 0, sizeof(this->a)); } Matrix(int n, int m) { this->n = n; this->m = m; memset(this->a, 0, sizeof(this->a)); } }; Matrix operator*(Matrix a, Matrix b) { Matrix out = Matrix(a.n, b.m); for (int i = 0; i < a.n; i++) { for (int j = 0; j < b.m; j++) { for (int p = 0; p < a.m; p++) { out.a[i][j] = (out.a[i][j] + a.a[i][p] * b.a[p][j]) % mod; } } } return out; } Matrix fastPow(Matrix x, long long p) { Matrix answer = Matrix(x.n, x.m), current = x; for (int i = 0; i < x.n; i++) { answer.a[i][i] = 1; } while (p != 0) { if (p % 2 != 0) { answer = answer * current; } p /= 2; current = current * current; } return answer; } string fString[35]; void precalcStrings() { fString[1] = a ; fString[2] = b ; for (int i = 3; i <= 30; i++) { fString[i] = fString[i - 1] + fString[i - 2]; } } int match(string s, string pattern) { vector<int> f; f.assign(pattern.size() + 1, 0); int len = 0; f[0] = 0; for (int i = 1; i < pattern.size(); i++) { if (pattern[len] == pattern[i]) { len++; f[i] = len; } else { while (pattern[len] != pattern[i] && len != 0) len = f[len - 1]; if (pattern[len] == pattern[i]) { len++; f[i] = len; } else { f[i] = 0; } } } len = 0; int answer = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == pattern[len]) { len++; if (len == pattern.size()) { answer++; len = f[pattern.size() - 1]; } } else { while (s[i] != pattern[len] && len != 0) len = f[len - 1]; if (s[i] == pattern[len]) { len++; } else { len = 0; } } } return answer; } string getPrefix(string s, int len) { string out = ; for (int i = 0; i < len; i++) out += s[i]; return out; } string getSuffix(string s, int len) { string out = ; for (int i = s.size() - len; i < s.size(); i++) out += s[i]; return out; } long long k; string s; int val[2]; string prefix; string suffix[2]; long long dp[MAXN]; void solve() { if (k < 30) { cout << match(fString[k], s) << n ; return; } int n = s.size(); int ind; for (int i = 1; i < 30; i++) { if (fString[i].size() > s.size()) { ind = i; break; } } prefix = getPrefix(fString[ind], n - 1); suffix[0] = getSuffix(fString[ind], n - 1); suffix[1] = getSuffix(fString[ind + 1], n - 1); val[0] = match(suffix[0] + prefix, s); val[1] = match(suffix[1] + prefix, s); Matrix A = Matrix(1, 4); A.a[0][0] = match(fString[ind], s); A.a[0][1] = match(fString[ind + 1], s); A.a[0][2] = val[1]; A.a[0][3] = val[0]; Matrix B = Matrix(4, 4); B.a[0][0] = 0; B.a[0][1] = 1; B.a[0][2] = 0; B.a[0][3] = 0; B.a[1][0] = 1; B.a[1][1] = 1; B.a[1][2] = 0; B.a[1][3] = 0; B.a[2][0] = 0; B.a[2][1] = 1; B.a[2][2] = 0; B.a[2][3] = 1; B.a[3][0] = 0; B.a[3][1] = 0; B.a[3][2] = 1; B.a[3][3] = 0; cout << (A * fastPow(B, k - ind - 1)).a[0][1] << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); precalcStrings(); int T; cin >> k >> T; while (T--) { cin >> s; solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { char no[20]; cin >> no; int len = strlen(no); int ans = (1 << len) - 2; for (int i = (len - 1), pos = 0; i >= 0; i--, pos++) { if (no[i] == 7 ) ans += (1 << pos); } cout << ans + 1 << endl; return 0; }
|
/* 2 to 1 MUX, select from two 32-bit input*/
module mux2to1for5bit(datain0,datain1, dataout, select);
input [4:0] datain0, datain1;
input select;
output [4:0] dataout;
reg [4:0] dataout;
/*whenever datain0 or datain1 or select signals is changed*/
always @(datain0 or datain1 or select)
begin
if (select == 0)
dataout = datain0;
else
dataout = datain1;
end
endmodule
/* 2 to 1 MUX, select from two 32-bit input*/
module mux2to1(datain0,datain1, dataout, select);
input [31:0] datain0, datain1;
input select;
output [31:0] dataout;
reg [31:0] dataout;
/*whenever datain0 or datain1 or select signals is changed*/
always @(datain0 or datain1 or select)
begin
if (select == 0)
dataout = datain0;
else
dataout = datain1;
end
endmodule
module muxTestbench;
reg [31:0] datain0,datain1;
reg select;
wire [31:0] dataout;
mux2to1 UUT(datain0, datain1, dataout,select);
initial begin
#20 datain0 = 8;
datain1 = 13;
select = 0;
#20 datain0 = 8;
datain1 = 13;
select = 1;
#20 datain0 = 20;
datain1 = 21;
select = 1;
#20 datain0 = 55;
datain1 = 66;
select = 1;
#20 datain0 = 55;
datain1 = 66;
select = 0;
end
initial
#120 $stop;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// ////
//// To Do: ////
//// - add support for other RAM's ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_128x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({1'b0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({1'b0, addr}),
.DI(di[31:16]),
.EN(ce),
.WE(we),
.DO(doq[31:16])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({2'b00, addr}),
.DI(di),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FA_FUNCTIONAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; template <typename Tp> inline void outarr(Tp _begin, Tp _end, const char* _delim = ) { for (Tp current = _begin; current != _end; ++current) { std::cout << *current << _delim; } std::cout << n ; } using ll = int64_t; using pii = std::pair<int, int>; constexpr int INF = 0x3f3f3f3f; constexpr int MOD = static_cast<const int>(1e9 + 7); int F(int x) { if (x == 1) { return 1; } return 12 * (x - 1); } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int a; cin >> a; ll ans = 0; for (int i = 1; i <= a; ++i) { ans += F(i); } cout << ans << n ; return 0; }
|
module t;
endmodule
class C;
function int f();
f = 17;
endfunction
extern function int g();
virtual function int f();
a;
endfunction // int
// pure virtual functions have no endfunction.
C a;
initial begin
$display("hello world");
$display("a of f is %d, g is %d", a.f(),a.g());
end
function int C::g();
g = 18;
endfunction // g
// pure virtual functions have no endfunction.
endclass // C
class pure_virt_func_class;
pure virtual function string pure_virt_func();
pure virtual function string pure_virt_func();
pure virtual function string pure_virt_func();
extern pure virtual task t();
pure virtual task t();
virtual task t();
/* body */
endtask // t
virtual function f();
/* body */
endfunction // f
endclass // pure_virt_func_class
class base_test extends uvm_test;
`uvm_component_utils(base_test)
typedef virtual my_if my_vif_t;
// A function definition starting with the virtual keyword should not be
// detected as a declaration. This issue is seen when an attempt to indent
// each declaration is done (when the verilog-auto-lineup variable is set
// to 'declarations).
// In other words, the "function" in "virtual function" below must not be
// aligned with "my_if" in the "typedef virtual my_if.." line above.
virtual function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
endfunction : start_of_simulation_phase
endclass : base_test
|
#include <bits/stdc++.h> struct TSubStr { TSubStr(const std::string& text, size_t begin, size_t end) : Text(text), Begin(begin), End(end) {} const std::string& Text; size_t Begin; size_t End; static inline size_t getId(const std::string& text, size_t begin, size_t end) { size_t id = 0; size_t power = 1; for (size_t i = begin; i < end; ++i) { id += (text[i] - a + 1) * power; power *= 27; } return id; } static inline size_t getId(const std::string& str) { size_t id = 0; size_t power = 1; for (size_t i = 0; i < str.size(); ++i) { id += (str[i] - a + 1) * power; power *= 27; } return id; } inline size_t getId() const { size_t id = 0; size_t power = 1; for (size_t i = Begin; i < End; ++i) { id += (Text[i] - a + 1) * power; power *= 27; } return id; } }; void FillIndex(const std::string& text, std::vector<std::vector<size_t> >& index) { index.clear(); index.resize(27 * 27 * 27 * 27); for (size_t i = 0; i < text.size(); ++i) { index[TSubStr::getId(text, i, i + 1)].push_back(i); if (i + 1 < text.size()) index[TSubStr::getId(text, i, i + 2)].push_back(i); if (i + 2 < text.size()) index[TSubStr::getId(text, i, i + 3)].push_back(i); if (i + 3 < text.size()) index[TSubStr::getId(text, i, i + 4)].push_back(i); } } std::string ReverseStr(const std::string& str) { std::string res(str); std::reverse(res.begin(), res.end()); return res; } struct TProblemQuery { TProblemQuery(const std::string& firstStr, const std::string& secondStr) { if (firstStr < secondStr) { FirstStr = firstStr; SecondStr = secondStr; } else { FirstStr = secondStr; SecondStr = firstStr; } } TProblemQuery(const TProblemQuery& rhs) : FirstStr(rhs.FirstStr), SecondStr(rhs.SecondStr) {} TProblemQuery() {} bool operator==(const TProblemQuery& rhs) const { return FirstStr == rhs.FirstStr && SecondStr == rhs.SecondStr; } std::string FirstStr; std::string SecondStr; }; struct TProblemQueryHash { size_t operator()(const TProblemQuery& query) const { size_t x = HashFn(query.FirstStr); size_t y = HashFn(query.SecondStr); return (x * 1000000009) ^ y; } std::hash<std::string> HashFn; }; inline void TryImprove( const std::string& freqStr, const std::string& text, const std::vector<size_t>& freqStrOccurencies, std::unordered_map<TProblemQuery, size_t, TProblemQueryHash>& results, int freqStrI, int textI, int len) { if (textI + len > text.size()) { return; } TProblemQuery query(freqStr, text.substr(textI, len)); if (results.count(query)) { size_t& res = results[query]; size_t begI = std::min<size_t>(textI, freqStrOccurencies[freqStrI]); size_t endI = std::max<size_t>( textI + len, freqStrOccurencies[freqStrI] + freqStr.size()); size_t potentialRes = endI - begI; if (freqStrI > 0) { begI = std::min<size_t>(textI, freqStrOccurencies[freqStrI - 1]); endI = std::max<size_t>( textI + len, freqStrOccurencies[freqStrI - 1] + freqStr.size()); potentialRes = std::min<size_t>(potentialRes, endI - begI); } res = std::min<size_t>(res, potentialRes); } } void ProcessFreq( const std::string& freqStr, const std::string& text, const std::vector<std::vector<size_t> >& index, std::unordered_map<TProblemQuery, size_t, TProblemQueryHash>& results, std::vector<bool>& processedAsFreq) { const std::vector<size_t>& freqStrOccurencies = index[TSubStr::getId(freqStr)]; int freqStrI = 0; int textI = 0; while (textI < text.size()) { if (freqStrI < freqStrOccurencies.size() - 1 && textI > freqStrOccurencies[freqStrI]) { ++freqStrI; continue; } TryImprove(freqStr, text, freqStrOccurencies, results, freqStrI, textI, 1); TryImprove(freqStr, text, freqStrOccurencies, results, freqStrI, textI, 2); TryImprove(freqStr, text, freqStrOccurencies, results, freqStrI, textI, 3); TryImprove(freqStr, text, freqStrOccurencies, results, freqStrI, textI, 4); ++textI; } processedAsFreq[TSubStr::getId(freqStr)] = true; } void ProcessQuery( const TProblemQuery& query, const std::string& text, const std::vector<std::vector<size_t> >& index, std::unordered_map<TProblemQuery, size_t, TProblemQueryHash>& results, std::vector<bool>& processedAsFreq) { if (index[TSubStr::getId(query.FirstStr)].empty() || index[TSubStr::getId(query.SecondStr)].empty()) { return; } if (processedAsFreq[TSubStr::getId(query.FirstStr)] || processedAsFreq[TSubStr::getId(query.SecondStr)]) { return; } if (index[TSubStr::getId(query.FirstStr)].size() > 800) { ProcessFreq(query.FirstStr, text, index, results, processedAsFreq); return; } if (index[TSubStr::getId(query.SecondStr)].size() > 800) { ProcessFreq(query.SecondStr, text, index, results, processedAsFreq); return; } const std::vector<size_t>& firstStrOccurencies = index[TSubStr::getId(query.FirstStr)]; const std::vector<size_t>& secondStrOccurencies = index[TSubStr::getId(query.SecondStr)]; size_t& res = results[query]; int firstI = 0; int secondI = 0; int potentialSubstrBegin = std::min(firstStrOccurencies[firstI], secondStrOccurencies[secondI]); int potentialSubstrEnd = std::max(firstStrOccurencies[firstI] + query.FirstStr.size(), secondStrOccurencies[secondI] + query.SecondStr.size()); size_t potentialRes = potentialSubstrEnd - potentialSubstrBegin; res = std::min(res, potentialRes); while (secondI < secondStrOccurencies.size() && secondStrOccurencies[secondI] < firstStrOccurencies[firstI]) { potentialSubstrBegin = std::min(firstStrOccurencies[firstI], secondStrOccurencies[secondI]); potentialSubstrEnd = std::max(firstStrOccurencies[firstI] + query.FirstStr.size(), secondStrOccurencies[secondI] + query.SecondStr.size()); potentialRes = potentialSubstrEnd - potentialSubstrBegin; res = std::min(res, potentialRes); ++secondI; } while (secondI < secondStrOccurencies.size()) { if (firstI < firstStrOccurencies.size() - 1 && firstStrOccurencies[firstI + 1] < secondStrOccurencies[secondI]) { ++firstI; continue; } potentialSubstrBegin = std::min(firstStrOccurencies[firstI], secondStrOccurencies[secondI]); potentialSubstrEnd = std::max(firstStrOccurencies[firstI] + query.FirstStr.size(), secondStrOccurencies[secondI] + query.SecondStr.size()); potentialRes = potentialSubstrEnd - potentialSubstrBegin; res = std::min(res, potentialRes); if (firstI < firstStrOccurencies.size() - 1) { potentialSubstrBegin = std::min(firstStrOccurencies[firstI + 1], secondStrOccurencies[secondI]); potentialSubstrEnd = std::max(firstStrOccurencies[firstI + 1] + query.FirstStr.size(), secondStrOccurencies[secondI] + query.SecondStr.size()); potentialRes = potentialSubstrEnd - potentialSubstrBegin; res = std::min(res, potentialRes); } ++secondI; } } int main() { std::string text; std::cin >> text; std::vector<std::vector<size_t> > index; FillIndex(text, index); std::vector<bool> processedAsFreq(27 * 27 * 27 * 27, false); std::unordered_map<TProblemQuery, size_t, TProblemQueryHash> results; results.max_load_factor(3.0); results.reserve(300000); std::vector<TProblemQuery> queries; size_t m; std::cin >> m; size_t NO_ANSWER = 1000000009; for (size_t i = 0; i < m; ++i) { std::string strFirst; std::string strSecond; std::cin >> strFirst; std::cin >> strSecond; TProblemQuery query(strFirst, strSecond); queries.push_back(query); results[query] = NO_ANSWER; } for (size_t i = 0; i < m; ++i) { ProcessQuery(queries[i], text, index, results, processedAsFreq); size_t res = results[queries[i]]; std::cout << (res == NO_ANSWER ? -1 : (int)res) << n ; } return 0; }
|
`timescale 1 ns / 100 ps
module helloonechar_tb #(parameter CLOCK_FREQ = 4800, parameter BAUD_RATE = 1200) ();
reg ext_clock;
wire uart_tx_pin;
wire uart_tx_led;
wire uart_clock_led;
wire reset;
/* uart tx */
wire uart_ready;
reg [7:0] uart_data;
reg uart_clock_enable;
reg [7:0] count;
wire uart_clock;
power_on_reset POR(
.clock(ext_clock),
.reset(reset));
always
#2 ext_clock = ~ext_clock;
initial begin
#500000 $finish;
end
initial begin
$dumpfile ("helloonechar_tb.vcd");
$dumpvars (0, helloonechar_tb);
ext_clock = 0;
end
initial begin
uart_data = 8'h60;
end
always @(negedge uart_ready or negedge reset) begin
if (~reset) begin
uart_clock_enable <= 1;
count <= 16;
end else begin
if (count == 0)
uart_clock_enable <= 0;
else
count <= count - 1;
end
end
uart_tx #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
SERIAL (.read_data(uart_data),
.read_clock_enable(uart_clock_enable),
.reset(reset),
.ready(uart_ready),
.tx(uart_tx_pin),
.clock(ext_clock),
.uart_clock(uart_clock));
assign uart_tx_led = uart_tx_pin;
assign uart_clock_led = uart_clock;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A2BB2O_PP_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/02/2016 03:56:05 PM
// Design Name:
// Module Name: I_DESNORM_FIXED_TO_FLOAT
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module I_DESNORM_FIXED_TO_FLOAT(
input wire CLK, //system clock
input wire [31:0] F, //VALOR BINARIO EN COMA FIJA
input wire RST_FF, //system reset
input wire Begin_FSM_FF, //INICIA LA CONVERSION
output wire ACK_FF, //INDICA QUE LA CONVERSION FUE REALIZADA
output wire [31:0] RESULT //RESULTADO FINAL
);
wire Bandcomp;
wire [7:0] Encd;
wire EN_REG1;
wire EN_REGmult;
wire LOAD;
wire MS_1;
wire EN_MS_1;
wire MS1_REG;
wire EN_REG2;
wire RST;
FF_D #(.P(1)) REG_MS1_I (
.CLK(CLK),
.RST(RST),
.EN(EN_MS_1),
.D(MS_1),
.Q(MS1_REG)
);
FSM_Convert_Fixed_To_Float FSM_CONVERT_FIXED_FLOAT(
.CLK(CLK), //system clock
.RST_FF(RST_FF), //system reset
.Bandcomp(Bandcomp),
.Begin_FSM_FF(Begin_FSM_FF), //inicia la maquina de estados
.Encd(Encd),
.EN_REG1(EN_REG1),
.EN_REGmult(EN_REGmult),
.LOAD(LOAD),
.MS_1(MS_1),
.ACK_FF(ACK_FF),
.EN_MS_1(EN_MS_1),
.EN_REG2(EN_REG2),
.RST(RST)
);
Convert_Fixed_To_Float CONVERT_FIXED_FLOAT(
.CLK(CLK),
.FIXED(F),
.EN_REG1(EN_REG1),
.EN_REGmult(EN_REGmult),
.LOAD(LOAD),
.MS_1(MS1_REG),
.Bandcomp(Bandcomp),
.FLOATOUT(RESULT),
.Encd(Encd),
.EN_REG2(EN_REG2),
.RST(RST)
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 5346 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w64,
w65,
w16,
w81,
w2592,
w2673,
w5346;
assign w1 = i_data0;
assign w16 = w1 << 4;
assign w2592 = w81 << 5;
assign w2673 = w81 + w2592;
assign w5346 = w2673 << 1;
assign w64 = w1 << 6;
assign w65 = w1 + w64;
assign w81 = w65 + w16;
assign o_data0 = w5346;
//multiplier_block area estimate = 4630.34891076765;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// file: Clock70MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock70MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70MHz_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n <= 2) { cout << -1; return 0; } if (n == 3) { cout << 210; return 0; } if ((n - 4) % 6 == 0) { cout << 1; for (int i = 0; i < n - 3; i++) cout << 0; cout << 50; } if ((n - 4) % 6 == 1) { cout << 1; for (int i = 0; i < n - 3; i++) cout << 0; cout << 80; } if ((n - 4) % 6 == 2) { cout << 1; for (int i = 0; i < n - 4; i++) cout << 0; cout << 170; } if ((n - 4) % 6 == 3) { cout << 1; for (int i = 0; i < n - 3; i++) cout << 0; cout << 20; } if ((n - 4) % 6 == 4) { cout << 1; for (int i = 0; i < n - 4; i++) cout << 0; cout << 200; } if ((n - 4) % 6 == 5) { cout << 1; for (int i = 0; i < n - 4; i++) cout << 0; cout << 110; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long m, n, x, y, p, q; int main() { cin >> n; for (long long k = 0; k < n; k++) { cin >> x >> y >> p >> q; m += (p - x + 1) * (q - y + 1); } cout << m; }
|
/**
* $Id: axi_slave.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya symplified AXI slave.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* AXI slave used also for simple bus master.
*
*
* /------\
* WR ADDRESS ----> | WR |
* WR DATA ----> | | -----------
* WR RESPONSE <---- | CH | |
* \------/ /--------\
* | SIMPLE | ---> WR/RD ADDRRESS
* AXI | | ---> WR DATA
* | RP | <--- RD DATA
* | BUS | <--- ACKNOWLEDGE
* /------\ \--------/
* RD ADDRESS ----> | RD | |
* RD DATA <---- | CH | -----------
* \------/
*
*
* Because AXI bus is quite complex simplier bus was created.
*
* It combines write and read channel, where write has bigger priority. Command
* is then send forward to red pitaya bus. When wite or read acknowledge is
* received AXI response is created and new AXI is accepted.
*
* To prevent AXI lockups because no response is received, this slave creates its
* own after 32 cycles (ack_cnt).
*
*/
module axi_slave
#(
parameter AXI_DW = 64 , // data width (8,16,...,1024)
parameter AXI_AW = 32 , // address width
parameter AXI_IW = 8 , // ID width
parameter AXI_SW = AXI_DW >> 3 // strobe width - 1 bit for every data byte
)
(
// global signals
input axi_clk_i , //!< AXI global clock
input axi_rstn_i , //!< AXI global reset
// axi write address channel
input [ AXI_IW-1: 0] axi_awid_i , //!< AXI write address ID
input [ AXI_AW-1: 0] axi_awaddr_i , //!< AXI write address
input [ 4-1: 0] axi_awlen_i , //!< AXI write burst length
input [ 3-1: 0] axi_awsize_i , //!< AXI write burst size
input [ 2-1: 0] axi_awburst_i , //!< AXI write burst type
input [ 2-1: 0] axi_awlock_i , //!< AXI write lock type
input [ 4-1: 0] axi_awcache_i , //!< AXI write cache type
input [ 3-1: 0] axi_awprot_i , //!< AXI write protection type
input axi_awvalid_i , //!< AXI write address valid
output axi_awready_o , //!< AXI write ready
// axi write data channel
input [ AXI_IW-1: 0] axi_wid_i , //!< AXI write data ID
input [ AXI_DW-1: 0] axi_wdata_i , //!< AXI write data
input [ AXI_SW-1: 0] axi_wstrb_i , //!< AXI write strobes
input axi_wlast_i , //!< AXI write last
input axi_wvalid_i , //!< AXI write valid
output axi_wready_o , //!< AXI write ready
// axi write response channel
output [ AXI_IW-1: 0] axi_bid_o , //!< AXI write response ID
output reg [ 2-1: 0] axi_bresp_o , //!< AXI write response
output reg axi_bvalid_o , //!< AXI write response valid
input axi_bready_i , //!< AXI write response ready
// axi read address channel
input [ AXI_IW-1: 0] axi_arid_i , //!< AXI read address ID
input [ AXI_AW-1: 0] axi_araddr_i , //!< AXI read address
input [ 4-1: 0] axi_arlen_i , //!< AXI read burst length
input [ 3-1: 0] axi_arsize_i , //!< AXI read burst size
input [ 2-1: 0] axi_arburst_i , //!< AXI read burst type
input [ 2-1: 0] axi_arlock_i , //!< AXI read lock type
input [ 4-1: 0] axi_arcache_i , //!< AXI read cache type
input [ 3-1: 0] axi_arprot_i , //!< AXI read protection type
input axi_arvalid_i , //!< AXI read address valid
output axi_arready_o , //!< AXI read address ready
// axi read data channel
output [ AXI_IW-1: 0] axi_rid_o , //!< AXI read response ID
output reg [ AXI_DW-1: 0] axi_rdata_o , //!< AXI read data
output reg [ 2-1: 0] axi_rresp_o , //!< AXI read response
output reg axi_rlast_o , //!< AXI read last
output reg axi_rvalid_o , //!< AXI read response valid
input axi_rready_i , //!< AXI read response ready
// RP system read/write channel
output [ AXI_AW-1: 0] sys_addr_o , //!< system bus read/write address.
output [ AXI_DW-1: 0] sys_wdata_o , //!< system bus write data.
output reg [ AXI_SW-1: 0] sys_sel_o , //!< system bus write byte select.
output reg sys_wen_o , //!< system bus write enable.
output reg sys_ren_o , //!< system bus read enable.
input [ AXI_DW-1: 0] sys_rdata_i , //!< system bus read data.
input sys_err_i , //!< system bus error indicator.
input sys_ack_i //!< system bus acknowledge signal.
);
//---------------------------------------------------------------------------------
//
// AXI slave Module
wire ack ;
reg [ 6-1: 0] ack_cnt ;
reg rd_do ;
reg [ AXI_IW-1: 0] rd_arid ;
reg [ AXI_AW-1: 0] rd_araddr ;
reg rd_error ;
wire rd_errorw ;
reg wr_do ;
reg [ AXI_IW-1: 0] wr_awid ;
reg [ AXI_AW-1: 0] wr_awaddr ;
reg [ AXI_IW-1: 0] wr_wid ;
reg [ AXI_DW-1: 0] wr_wdata ;
reg wr_error ;
wire wr_errorw ;
assign wr_errorw = (axi_awlen_i != 4'h0) || (axi_awsize_i != 3'b010); // error if write burst and more/less than 4B transfer
assign rd_errorw = (axi_arlen_i != 4'h0) || (axi_arsize_i != 3'b010); // error if read burst and more/less than 4B transfer
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
rd_do <= 1'b0 ;
rd_error <= 1'b0 ;
end
else begin
if (axi_arvalid_i && !rd_do && !axi_awvalid_i && !wr_do) // accept just one read request - write has priority
rd_do <= 1'b1 ;
else if (axi_rready_i && rd_do && ack)
rd_do <= 1'b0 ;
if (axi_arvalid_i && axi_arready_o) begin // latch ID and address
rd_arid <= axi_arid_i ;
rd_araddr <= axi_araddr_i ;
rd_error <= rd_errorw ;
end
end
end
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
wr_do <= 1'b0 ;
wr_error <= 1'b0 ;
end
else begin
if (axi_awvalid_i && !wr_do && !rd_do) // accept just one write request - if idle
wr_do <= 1'b1 ;
else if (axi_bready_i && wr_do && ack)
wr_do <= 1'b0 ;
if (axi_awvalid_i && axi_awready_o) begin // latch ID and address
wr_awid <= axi_awid_i ;
wr_awaddr <= axi_awaddr_i ;
wr_error <= wr_errorw ;
end
if (axi_wvalid_i && wr_do) begin // latch ID and write data
wr_wid <= axi_wid_i ;
wr_wdata <= axi_wdata_i ;
end
end
end
assign axi_awready_o = !wr_do && !rd_do ;
assign axi_wready_o = (wr_do && axi_wvalid_i) || (wr_errorw && axi_wvalid_i) ;
assign axi_bid_o = wr_awid ;
//assign axi_bresp_o = {wr_error,1'b0} ; // 2'b10 SLVERR
//assign axi_bvalid_o = (sys_wen_o && axi_bready_i) || (wr_error && axi_bready_i) ;
assign axi_arready_o = !rd_do && !wr_do && !axi_awvalid_i ;
assign axi_rid_o = rd_arid ;
//assign axi_rdata_o = sys_rdata_i ;
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
axi_bvalid_o <= 1'b0 ;
axi_bresp_o <= 2'h0 ;
axi_rlast_o <= 1'b0 ;
axi_rvalid_o <= 1'b0 ;
axi_rresp_o <= 2'h0 ;
end
else begin
axi_bvalid_o <= wr_do && ack ;
axi_bresp_o <= {(wr_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
axi_rlast_o <= rd_do && ack ;
axi_rvalid_o <= rd_do && ack ;
axi_rresp_o <= {(rd_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
axi_rdata_o <= sys_rdata_i ;
end
end
// acknowledge protection
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
ack_cnt <= 6'h0 ;
end
else begin
if ((axi_arvalid_i && axi_arready_o) || (axi_awvalid_i && axi_awready_o)) // rd || wr request
ack_cnt <= 6'h1 ;
else if (ack)
ack_cnt <= 6'h0 ;
else if (|ack_cnt)
ack_cnt <= ack_cnt + 6'h1 ;
end
end
assign ack = sys_ack_i || ack_cnt[5] || (rd_do && rd_errorw) || (wr_do && wr_errorw); // bus acknowledge or timeout or error
//------------------------------------------
// Simple slave interface
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
sys_wen_o <= 1'b0 ;
sys_ren_o <= 1'b0 ;
sys_sel_o <= {AXI_SW{1'b0}} ;
end
else begin
sys_wen_o <= wr_do && axi_wvalid_i && !wr_errorw ;
sys_ren_o <= axi_arvalid_i && axi_arready_o && !rd_errorw ;
sys_sel_o <= {AXI_SW{1'b1}} ;
end
end
assign sys_addr_o = rd_do ? rd_araddr : wr_awaddr ;
assign sys_wdata_o = wr_wdata ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INFint = 2147483647; const long long INF = 9223372036854775807ll; const long long MOD = 1000000007ll; const long double EPS = 1e-9; vector<int> p; vector<int> used; vector<vector<int> > g; long long ans = 0; void dfs(int v) { used[v] = 1; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (used[to]) { if (p[to] == p[v]) { ans++; } } else { p[to] = !p[v]; dfs(to); } } } int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; p.resize(n); g.resize(n); used.resize(n); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--, y--; g[x].push_back(y); g[y].push_back(x); } for (int i = 0; i < n; i++) { if (!used[i]) { p[i] = 0; dfs(i); } } ans /= 2; if ((n - ans) & 1) ans++; cout << ans << endl; fprintf(stderr, nTIME = %lf n , 1.0 * clock() / CLOCKS_PER_SEC); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, c, ans1, ans2, ans3, a[100005], dp[5]; pair<long long, long long> p[300005]; vector<long long> v; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; if (m == 0) { cout << -1 << n ; return 0; } for (long long i = 1; i <= m; i++) { cin >> p[i].first >> p[i].second; if (p[i].first == 1) { v.push_back(p[i].second); } else if (p[i].second == 1) { v.push_back(p[i].first); } } sort(v.begin(), v.end()); v.push_back(n + 1); a[1] = 1; for (int i = 2; i <= n; i++) { if (i != v[k]) { a[i] = 1; } else { k++; } } c = v[0]; for (long long i = 1; i <= m; i++) { if (p[i].first == c && a[p[i].second] == 0) { a[p[i].second] = 2; } else if (p[i].second == c && a[p[i].first] == 0) { a[p[i].first] = 2; } } for (long long i = 1; i <= n; i++) { if (a[i] == 0) { a[i] = 3; } } for (long long i = 1; i <= n; i++) { dp[a[i]]++; } if (dp[1] == 0 || dp[2] == 0 || dp[3] == 0 || dp[1] * dp[2] + dp[2] * dp[3] + dp[1] * dp[3] != m) { cout << -1 << n ; return 0; } for (long long i = 1; i <= m; i++) { if (a[p[i].first] == a[p[i].second]) { cout << -1 << n ; return 0; } } for (long long i = 1; i <= n; i++) { cout << a[i] << ; } cout << n ; }
|
#include <bits/stdc++.h> const int N = 300005; int t[N << 2], tag[N << 2], size[N << 2], st1[N], st2[N], tp1, tp2, n, x, y, a[N]; long long ans; void up(int x) { int t1 = t[x << 1] + tag[x << 1], t2 = t[x << 1 | 1] + tag[x << 1 | 1]; if (t1 == t2) size[x] = size[x << 1] + size[x << 1 | 1]; if (t1 < t2) size[x] = size[x << 1]; if (t1 > t2) size[x] = size[x << 1 | 1]; t[x] = std::min(t1, t2); } void pushdown(int x) { if (tag[x]) { t[x] += tag[x]; tag[x << 1] += tag[x]; tag[x << 1 | 1] += tag[x]; tag[x] = 0; } } void build(int k, int l, int r) { if (l == r) { t[k] = n + 1; size[k] = 1; return; } int mid = (l + r) >> 1; build(k << 1, l, mid); build(k << 1 | 1, mid + 1, r); up(k); } void modify(int k, int L, int R, int l, int r, int val) { if (r < l) return; if (L == l && R == r) { tag[k] = tag[k] + val; return; } int mid = (L + R) >> 1; pushdown(k); if (r <= mid) modify(k << 1, L, mid, l, r, val); else if (l > mid) modify(k << 1 | 1, mid + 1, R, l, r, val); else { modify(k << 1, L, mid, l, mid, val); modify(k << 1 | 1, mid + 1, R, mid + 1, r, val); } up(k); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &y); a[x] = y; } int tp1 = tp1 = 0; build(1, 1, n); for (int i = 1; i <= n; i++) { x = a[i]; while (tp1 && x > a[st1[tp1]]) modify(1, 1, n, st1[tp1 - 1] + 1, st1[tp1], x - a[st1[tp1]]), tp1--; st1[++tp1] = i; while (tp2 && x < a[st2[tp2]]) modify(1, 1, n, st2[tp2 - 1] + 1, st2[tp2], a[st2[tp2]] - x), tp2--; st2[++tp2] = i; modify(1, 1, n, i, i, -n - 1); modify(1, 1, n, 1, i - 1, -1); if (t[1] + tag[1] == 0) ans = ans + size[1]; } printf( %lld n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axis_dma_rx (
// adc interface
adc_clk,
adc_rst,
// dma interface
dma_clk,
dma_rst,
dma_start,
dma_stream,
dma_count,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00050063;
parameter PCORE_ID = 0;
// adc interface
input adc_clk;
output adc_rst;
// dma interface
input dma_clk;
output dma_rst;
output dma_start;
output dma_stream;
output [31:0] dma_count;
input dma_ovf;
input dma_unf;
input dma_status;
input [31:0] dma_bw;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_dma_stream = 'd0;
reg up_dma_start = 'd0;
reg [31:0] up_dma_count = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dma_start_d = 'd0;
reg dma_start_2d = 'd0;
reg dma_start = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_dma_ovf_s;
wire up_dma_unf_s;
wire up_dma_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_dma_stream <= 'd0;
up_dma_start <= 'd0;
up_dma_count <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_dma_stream <= up_wdata[1];
up_dma_start <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_dma_count <= up_wdata;
end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[1];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'd0, up_resetn};
8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
8'h21: up_rdata <= up_dma_count;
8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status_s};
8'h23: up_rdata <= dma_bw;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
ad_rst i_dma_rst_reg (.preset(up_preset_s), .clk(dma_clk), .rst(dma_rst));
// dma control & status
up_xfer_cntrl #(.DATA_WIDTH(34)) i_dma_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_dma_start,
up_dma_stream,
up_dma_count}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_cntrl ({ dma_start_s,
dma_stream,
dma_count}));
up_xfer_status #(.DATA_WIDTH(3)) i_dma_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_dma_ovf_s,
up_dma_unf_s,
up_dma_status_s}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_status ({ dma_ovf,
dma_unf,
dma_status}));
// start needs to be a pulse
always @(posedge dma_clk) begin
dma_start_d <= dma_start_s;
dma_start_2d <= dma_start_d;
dma_start <= dma_start_d & ~dma_start_2d;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ns
module system_tb();
reg [15:0] mem [ 0:262143 ];
reg clk;
reg reset_b = 1'b1;
wire [17:0] addr;
wire [15:0] data;
wire [15:0] data_in;
reg [15:0] data_out;
wire ramwe_b;
wire ramoe_b;
wire ramcs_b;
reg rxd = 1'b1;
wire txd;
integer i, j;
parameter TEST_DATA_FILE = "test_data.mem";
parameter BITTIME = / 115200;
reg [7:0] test_data[ 0:1023 ];
task serial_send_byte;
input [7:0] byte;
begin
if (byte == 10)
$display("%t: UART Rx: <lf>", $time);
else if (byte == 13)
$display("%t: UART Rx: <cr>", $time);
else
$display("%t: UART Rx: %s", $time, byte);
// start bit (0)
#BITTIME rxd = 1'b0;
// data bits, LSB first
for (j = 0; j < 8; j = j + 1)
#BITTIME rxd = byte[j];
// stop bit (1)
#BITTIME rxd = 1'b1;
end
endtask
system
DUT
(
.clk100(clk),
.sw4(reset_b),
.RAMWE_b(ramwe_b),
.RAMOE_b(ramoe_b),
.RAMCS_b(ramcs_b),
.ADR(addr),
.DAT(data),
.rxd(rxd),
.txd(txd)
);
initial begin
$timeformat(-6, 3, " us", 14);
$dumpvars;
// Initialize memory
for (i = 0; i < 262144; i = i + 1)
mem[i] = 0;
// Load test data
for (i = 0; i < 1024; i = i + 1)
test_data[i] = 0;
$readmemh(TEST_DATA_FILE, test_data);
// initialize 100MHz clock
clk = 1'b1;
// external reset
#1000
reset_b = 1'b0;
#1000
reset_b = 1'b1;
#(BITTIME * 10 * 30) ; // "OPC6 Monitor -"
serial_send_byte("l");
#(BITTIME * 10 * 50) ; // "Paste srecords followed by a blank line"
// Send srecords
i = 0;
while (test_data[i] != 0) begin
serial_send_byte(test_data[i]);
i = i + 1;
end
serial_send_byte(13);
serial_send_byte(13); // not sure why two blank lines are necessary
#(BITTIME * 10 * 10) ; // "-"
serial_send_byte("1");
serial_send_byte("0");
serial_send_byte("0");
serial_send_byte("0");
serial_send_byte("g");
#10000000 // wait a further 10ms for the test program to run
$finish;
end
always
#5 clk = !clk;
always @(posedge DUT.clk)
if (DUT.cpuclken) begin
if (DUT.vpa) begin
$display("%t: Fetch: %04x = %02x", $time, DUT.address, DUT.cpu_din);
end else if (DUT.vda) begin
if (DUT.rnw)
$display("%t: Mem Rd: %04x = %02x", $time, DUT.address, DUT.cpu_din);
else
$display("%t: Mem Wr: %04x = %02x", $time, DUT.address, DUT.cpu_dout);
end else if (DUT.vio) begin
if (DUT.rnw)
$display("%t: IO Rd: %04x = %02x", $time, DUT.address, DUT.cpu_din);
else
$display("%t: IO Wr: %04x = %02x", $time, DUT.address, DUT.cpu_dout);
end
end
always @(posedge DUT.clk)
if (DUT.cpuclken) begin
if (DUT.vio && !DUT.rnw && DUT.address[15:0] == 16'hfe09)
if (DUT.cpu_dout == 10)
$display("%t: UART Tx: <lf>", $time);
else if (DUT.cpu_dout == 13)
$display("%t: UART Tx: <cr>", $time);
else
$display("%t: UART Tx: %s", $time, DUT.cpu_dout);
end
assign data = (!ramcs_b && !ramoe_b && ramwe_b) ? data_out : 16'hZZZZ;
// This seem a bit of a hack, but the memory write
// was getting lost because the data was being tristated instantly
assign #(1) data_in = data;
always @(posedge ramwe_b)
if (ramcs_b == 1'b0) begin
mem[addr] <= data_in;
$display("%t: Ram Wr: %04x = %02x", $time, addr, data_in);
end
always @(addr)
data_out <= mem[addr];
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous frame FIFO
*/
module axis_async_frame_fifo #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8,
parameter DROP_WHEN_FULL = 0
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg drop_frame = 1'b0;
reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
// overflow in single packet
wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
wire write = input_axis_tvalid & (~full | DROP_WHEN_FULL);
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
wr_ptr_cur <= 0;
wr_ptr_gray <= 0;
drop_frame <= 0;
end else if (write) begin
if (full | full_cur | drop_frame) begin
// buffer full, hold current pointer, drop packet at end
drop_frame <= 1;
if (input_axis_tlast) begin
wr_ptr_cur <= wr_ptr;
drop_frame <= 0;
end
end else begin
mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_cur <= wr_ptr_cur + 1;
if (input_axis_tlast) begin
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur <= wr_ptr;
end else begin
// good packet, push new write pointer
wr_ptr_next = wr_ptr_cur + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
rd_ptr_gray <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__EINVP_PP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 1000000; const int OPAND = 2, OPOR = 3, OPXOR = 4, OPNOT = 5; int n; int op[MAXN]; vector<int> ch[MAXN]; int res[MAXN]; int ans[MAXN]; int dfsres(int at) { if (op[at] == 0 || op[at] == 1) { res[at] = op[at]; } else if (op[at] == OPNOT) { res[at] = 1 - dfsres(ch[at][0]); } else if (op[at] == OPAND) { int a = dfsres(ch[at][0]), b = dfsres(ch[at][1]); res[at] = a == 1 && b == 1 ? 1 : 0; } else if (op[at] == OPOR) { int a = dfsres(ch[at][0]), b = dfsres(ch[at][1]); res[at] = a == 1 || b == 1 ? 1 : 0; } else if (op[at] == OPXOR) { int a = dfsres(ch[at][0]), b = dfsres(ch[at][1]); res[at] = (a == 1) ^ (b == 1) ? 1 : 0; } else { assert(false); } return res[at]; } void dfsans(int at, int fix, bool neg) { if (op[at] == 0 || op[at] == 1) { ans[at] = fix != -1 ? fix : 1 - op[at]; if (fix == -1 && neg) ans[at] = 1 - ans[at]; } else if (op[at] == OPNOT) { dfsans(ch[at][0], fix, !neg); } else if (op[at] == OPAND) { for (int i = (0); i < (2); ++i) dfsans(ch[at][i], fix != -1 ? fix : res[ch[at][1 - i]] == 0 ? (neg ? 1 : 0) : -1, neg); } else if (op[at] == OPOR) { for (int i = (0); i < (2); ++i) dfsans(ch[at][i], fix != -1 ? fix : res[ch[at][1 - i]] == 1 ? (neg ? 0 : 1) : -1, neg); } else if (op[at] == OPXOR) { for (int i = (0); i < (2); ++i) dfsans(ch[at][i], fix != -1 ? fix : -1, res[ch[at][1 - i]] == 1 ? !neg : neg); } else { assert(false); } } void run() { scanf( %d , &n); for (int i = (0); i < (n); ++i) { char buff[10]; scanf( %s , buff); if (strcmp(buff, AND ) == 0) { int a, b; scanf( %d%d , &a, &b); --a, --b; op[i] = OPAND; ch[i].push_back(a); ch[i].push_back(b); } else if (strcmp(buff, OR ) == 0) { int a, b; scanf( %d%d , &a, &b); --a, --b; op[i] = OPOR; ch[i].push_back(a); ch[i].push_back(b); } else if (strcmp(buff, XOR ) == 0) { int a, b; scanf( %d%d , &a, &b); --a, --b; op[i] = OPXOR; ch[i].push_back(a); ch[i].push_back(b); } else if (strcmp(buff, NOT ) == 0) { int a; scanf( %d , &a); --a; op[i] = OPNOT; ch[i].push_back(a); } else if (strcmp(buff, IN ) == 0) { int val; scanf( %d , &val); op[i] = val; } else { printf( err: %s n , buff); assert(false); } } dfsres(0); dfsans(0, -1, false); for (int i = (0); i < (n); ++i) if (op[i] == 0 || op[i] == 1) printf( %d , ans[i]); puts( ); } int main() { run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int ntests; cin >> ntests; while (ntests--) { int n, k, a, b; cin >> k >> n >> a >> b; if (k <= 1ll * n * b) cout << -1 << endl; else { long long x = (k - 1ll * n * b - 1) / (a - b); if (x > n) x = n; cout << x << endl; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BLACKBOX_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_BLACKBOX_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__macro_sparecell (
LO
);
output LO;
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_BLACKBOX_V
|
#include <bits/stdc++.h> int cmp(const void *a, const void *b) { return (*(int *)a - *(int *)b); } long long int mod; void f(long long int p) { long long ans = 1, n = 3; while (p) { if (p & 1) ans = (ans * n) % mod; n = (n * n) % mod; p = p >> 1; } ans--; while (ans < 0) ans += mod; printf( %lld , ans); } int main() { long long int n; scanf( %lld%lld , &n, &mod); f(n); return 0; }
|
/*
reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
error...
*/
module mem_tester(
clk,
rst_n,
led, // LED flashing or not
// SRAM signals
SRAM_DQ, // sram inout databus
SRAM_ADDR, // sram address bus
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N, //
SRAM_CE_N, //
SRAM_OE_N //
);
parameter SRAM_DATA_SIZE = 8;
parameter SRAM_ADDR_SIZE = 19;
inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
wire [SRAM_DATA_SIZE-1:0] SRAM_DQ;
output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
wire SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
input clk;
input rst_n;
output led; reg led;
reg inc_pass_ctr; // increment passes counter (0000-9999 BCD)
reg inc_err_ctr; // increment errors counter (10 red binary LEDs)
reg check_in_progress; // when 1 - enables errors checking
reg [19:0] ledflash;
always @(posedge clk)
begin
if( inc_pass_ctr )
ledflash <= 20'd0;
else if( !ledflash[19] )
ledflash <= ledflash + 20'd1;
end
always @(posedge clk)
begin
led <= ledflash[19] ^ was_error;
end
reg was_error;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
was_error <= 1'b0;
else if( inc_err_ctr )
was_error <= 1'b1;
end
reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
wire [SRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(sram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
defparam my_rnd.OUT_SIZE = SRAM_DATA_SIZE;
defparam my_rnd.LFSR_LENGTH = 41;
defparam my_rnd.LFSR_FEEDBACK = 3;
reg sram_start,sram_rnw;
wire sram_stop,sram_ready;
wire [SRAM_DATA_SIZE-1:0] sram_rdat;
sram_control my_sram( .clk(clk), .clk2(clk), .start(sram_start), .rnw(sram_rnw), .stop(sram_stop), .ready(sram_ready),
.rdat(sram_rdat), .wdat(rnd_out),
.SRAM_DQ(SRAM_DQ), .SRAM_ADDR(SRAM_ADDR),
.SRAM_CE_N(SRAM_CE_N), .SRAM_OE_N(SRAM_OE_N), .SRAM_WE_N(SRAM_WE_N) );
defparam my_sram.SRAM_DATA_SIZE = SRAM_DATA_SIZE;
defparam my_sram.SRAM_ADDR_SIZE = SRAM_ADDR_SIZE;
// FSM states and registers
reg [3:0] curr_state,next_state;
parameter RESET = 4'h0;
parameter INIT1 = 4'h1;
parameter INIT2 = 4'h2;
parameter BEGIN_WRITE1 = 4'h3;
parameter BEGIN_WRITE2 = 4'h4;
parameter BEGIN_WRITE3 = 4'h5;
parameter BEGIN_WRITE4 = 4'h6;
parameter WRITE = 4'h7;
parameter BEGIN_READ1 = 4'h8;
parameter BEGIN_READ2 = 4'h9;
parameter BEGIN_READ3 = 4'hA;
parameter BEGIN_READ4 = 4'hB;
parameter READ = 4'hC;
parameter END_READ = 4'hD;
parameter INC_PASSES1 = 4'hE;
parameter INC_PASSES2 = 4'hF;
// FSM dispatcher
always @*
begin
case( curr_state )
RESET:
next_state <= INIT1;
INIT1:
if( sram_stop )
next_state <= INIT2;
else
next_state <= INIT1;
INIT2:
next_state <= BEGIN_WRITE1;
BEGIN_WRITE1:
next_state <= BEGIN_WRITE2;
BEGIN_WRITE2:
next_state <= BEGIN_WRITE3;
BEGIN_WRITE3:
next_state <= BEGIN_WRITE4;
BEGIN_WRITE4:
next_state <= WRITE;
WRITE:
if( sram_stop )
next_state <= BEGIN_READ1;
else
next_state <= WRITE;
BEGIN_READ1:
next_state <= BEGIN_READ2;
BEGIN_READ2:
next_state <= BEGIN_READ3;
BEGIN_READ3:
next_state <= BEGIN_READ4;
BEGIN_READ4:
next_state <= READ;
READ:
if( sram_stop )
next_state <= END_READ;
else
next_state <= READ;
END_READ:
next_state <= INC_PASSES1;
INC_PASSES1:
next_state <= INC_PASSES2;
INC_PASSES2:
next_state <= BEGIN_WRITE1;
default:
next_state <= RESET;
endcase
end
// FSM sequencer
always @(posedge clk,negedge rst_n)
begin
if( !rst_n )
curr_state <= RESET;
else
curr_state <= next_state;
end
// FSM controller
always @(posedge clk)
begin
case( curr_state )
//////////////////////////////////////////////////
RESET:
begin
// various initializings begin
inc_pass_ctr <= 1'b0;
check_in_progress <= 1'b0;
rnd_init <= 1'b1; //begin RND init
rnd_save <= 1'b0;
rnd_restore <= 1'b0;
sram_start <= 1'b1;
sram_rnw <= 1'b1; // start condition for sram controller, in read mode
end
INIT1:
begin
sram_start <= 1'b0; // end sram start
end
INIT2:
begin
rnd_init <= 1'b0; // end rnd init
end
//////////////////////////////////////////////////
BEGIN_WRITE1:
begin
rnd_save <= 1'b1;
sram_rnw <= 1'b0;
end
BEGIN_WRITE2:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_WRITE3:
begin
sram_start <= 1'b0;
end
/* BEGIN_WRITE4:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
WRITE:
begin
sram_start <= 1'b0;
end
*/
//////////////////////////////////////////////////
BEGIN_READ1:
begin
rnd_restore <= 1'b1;
sram_rnw <= 1'b1;
end
BEGIN_READ2:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_READ3:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
/* BEGIN_READ4:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
READ:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
*/
END_READ:
begin
check_in_progress <= 1'b0;
end
INC_PASSES1:
begin
inc_pass_ctr <= 1'b1;
end
INC_PASSES2:
begin
inc_pass_ctr <= 1'b0;
end
endcase
end
// errors counter
always @(posedge clk)
inc_err_ctr <= check_in_progress & sram_ready & ((sram_rdat==rnd_out)?0:1);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.setf(ios::fixed); cout.precision(20); const int MAX_N = (int)1e7; vector<bool> isPrime(MAX_N, true); isPrime[1] = false; for (int i = 2; i < MAX_N; i++) { if (isPrime[i]) { for (int j = 2 * i; j < MAX_N; j += i) { isPrime[j] = false; } } } int n, m; cin >> n >> m; long long sum = 0; vector<set<int>> has(n + 10); vector<int> u, v, w; auto push = [&](int a, int b, int c) { u.push_back(a); v.push_back(b); w.push_back(c); has[a].insert(b); has[b].insert(a); m--; sum += c; }; push(1, n, 2); for (int i = 1; i + 1 < n; i++) { if (i + 1 == n - 1) { int w = 2; while (!isPrime[sum + w]) { w++; } push(i, i + 1, w); break; } push(i, i + 1, 2); } assert(isPrime[sum]); cout << 2 << << sum << n ; for (int i = 1; i <= n && m > 0; i++) { for (int j = i + 1; j <= n && m > 0; j++) { if (has[i].count(j)) { continue; } const int MAX_VALUE = (int)1e8; push(i, j, MAX_VALUE); } } for (int i = 0; i < ((int)(u).size()); i++) { cout << u[i] << << v[i] << << w[i] << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 510; int n, k; int a[MAX], b[MAX]; void init() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; cin >> k; for (int i = 1; i <= k; i++) cin >> b[i]; } bool valid(int i, int l, int r) { int x = i, y = i, sum = a[i]; while (true) { int old_x = x, old_y = y; while (x - 1 >= l && sum > a[x - 1]) { x--; sum += a[x]; } while (y + 1 <= r && sum > a[y + 1]) { y++; sum += a[y]; } if (old_x == x && old_y == y) break; } return x == l && y == r; } void print(int i, int l, int r) { int x = i, y = i, sum = a[i]; while (true) { int old_x = x, old_y = y; while (x - 1 >= l && sum > a[x - 1]) { cout << x << L << n ; x--; sum += a[x]; } while (y + 1 <= r && sum > a[y + 1]) { cout << x << R << n ; y++; sum += a[y]; } if (old_x == x && old_y == y) break; } } void process() { vector<pair<int, pair<int, int> > > p; bool found = true; int l, r = n, pb = k; while (r >= 1 && pb >= 1) { l = r; int sum = a[r]; while (l - 1 >= 1 && a[l - 1] + sum <= b[pb]) { l--; sum += a[l]; } if (sum == b[pb]) { bool exist = false; for (int i = l; i <= r; i++) if (valid(i, l, r)) { exist = true; p.push_back(make_pair(i, make_pair(l, r))); break; } if (exist) { sum = 0; pb--; } else { found = false; break; } } else { found = false; break; } r = l - 1; } if (r != 0 || pb != 0) found = false; if (!found) cout << NO ; else { cout << YES << n ; for (int i = 0; i < (int)p.size(); i++) print(p[i].first, p[i].second.first, p[i].second.second); } } int main() { ios_base::sync_with_stdio(false); init(); process(); }
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#include <bits/stdc++.h> long long dx[4] = {0, -1, 0, 1}; long long dy[4] = {1, 0, -1, 0}; using namespace std; class pa3 { public: long long x, y, z; pa3(long long x = 0, long long y = 0, long long z = 0) : x(x), y(y), z(z) {} bool operator<(const pa3 &p) const { if (x != p.x) return x < p.x; if (y != p.y) return y < p.y; return z < p.z; } bool operator>(const pa3 &p) const { if (x != p.x) return x > p.x; if (y != p.y) return y > p.y; return z > p.z; } bool operator==(const pa3 &p) const { return x == p.x && y == p.y && z == p.z; } bool operator!=(const pa3 &p) const { return !(x == p.x && y == p.y && z == p.z); } }; class pa4 { public: double x; long long y, z, w; pa4(double x = 0, long long y = 0, long long z = 0, long long w = 0) : x(x), y(y), z(z), w(w) {} bool operator<(const pa4 &p) const { if (x != p.x) return x < p.x; if (y != p.y) return y < p.y; if (z != p.z) return z < p.z; return w < p.w; } bool operator>(const pa4 &p) const { if (x != p.x) return x > p.x; if (y != p.y) return y > p.y; if (z != p.z) return z > p.z; return w > p.w; } bool operator==(const pa4 &p) const { return x == p.x && y == p.y && z == p.z && w == p.w; } }; class pa2 { public: long long x, y; pa2(long long x = 0, long long y = 0) : x(x), y(y) {} pa2 operator+(pa2 p) { return pa2(x + p.x, y + p.y); } pa2 operator-(pa2 p) { return pa2(x - p.x, y - p.y); } bool operator<(const pa2 &p) const { return x != p.x ? x < p.x : y < p.y; } bool operator>(const pa2 &p) const { return x != p.x ? x > p.x : y > p.y; } bool operator==(const pa2 &p) const { return abs(x - p.x) == 0 && abs(y - p.y) == 0; } bool operator!=(const pa2 &p) const { return !(abs(x - p.x) == 0 && abs(y - p.y) == 0); } }; class Point { public: double x, y; Point(double x = 0, double y = 0) : x(x), y(y) {} Point operator+(Point p) { return Point(x + p.x, y + p.y); } Point operator-(Point p) { return Point(x - p.x, y - p.y); } Point operator*(double a) { return Point(x * a, y * a); } Point operator/(double a) { return Point(x / a, y / a); } double absv() { return sqrt(norm()); } double norm() { return x * x + y * y; } bool operator<(const Point &p) const { return x != p.x ? x < p.x : y < p.y; } bool operator==(const Point &p) const { return fabs(x - p.x) < (1e-10) && fabs(y - p.y) < (1e-10); } }; struct Segment { Point p1, p2; }; double dot(Point a, Point b) { return a.x * b.x + a.y * b.y; } double cross(Point a, Point b) { return a.x * b.y - a.y * b.x; } bool parareru(Point a, Point b, Point c, Point d) { return abs(cross(a - b, d - c)) < (1e-10); } double distance_ls_p(Point a, Point b, Point c) { if (dot(b - a, c - a) < (1e-10)) return (c - a).absv(); if (dot(a - b, c - b) < (1e-10)) return (c - b).absv(); return abs(cross(b - a, c - a)) / (b - a).absv(); } bool is_intersected_ls(Segment a, Segment b) { if (a.p1 == b.p1 || a.p2 == b.p1 || a.p1 == b.p2 || a.p2 == b.p2) return false; if (parareru((a.p2), (a.p1), (a.p1), (b.p2)) && parareru((a.p2), (a.p1), (a.p1), (b.p1))) { if (dot(a.p1 - b.p1, a.p1 - b.p2) < (1e-10)) return true; if (dot(a.p2 - b.p1, a.p2 - b.p2) < (1e-10)) return true; if (dot(a.p1 - b.p1, a.p2 - b.p1) < (1e-10)) return true; if (dot(a.p1 - b.p2, a.p2 - b.p2) < (1e-10)) return true; return false; } else return (cross(a.p2 - a.p1, b.p1 - a.p1) * cross(a.p2 - a.p1, b.p2 - a.p1) < (1e-10)) && (cross(b.p2 - b.p1, a.p1 - b.p1) * cross(b.p2 - b.p1, a.p2 - b.p1) < (1e-10)); } double segment_dis(Segment a, Segment b) { if (is_intersected_ls(a, b)) return 0; double r = distance_ls_p(a.p1, a.p2, b.p1); r = min(r, distance_ls_p(a.p1, a.p2, b.p2)); r = min(r, distance_ls_p(b.p1, b.p2, a.p2)); r = min(r, distance_ls_p(b.p1, b.p2, a.p1)); return r; } Point intersection_ls(Segment a, Segment b) { Point ba = b.p2 - b.p1; double d1 = abs(cross(ba, a.p1 - b.p1)); double d2 = abs(cross(ba, a.p2 - b.p1)); double t = d1 / (d1 + d2); return a.p1 + (a.p2 - a.p1) * t; } string itos(long long i) { ostringstream s; s << i; return s.str(); } long long gcd(long long v, long long b) { if (v > b) return gcd(b, v); if (v == b) return b; if (b % v == 0) return v; return gcd(v, b % v); } double distans(double x1, double y1, double x2, double y2) { double rr = (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); return sqrt(rr); } long long beki(long long wa, long long rr, long long warukazu) { if (rr == 0) return 1 % warukazu; if (rr == 1) return wa % warukazu; if (rr % 2 == 1) return (beki(wa, rr - 1, warukazu) * wa) % warukazu; long long zx = beki(wa, rr / 2, warukazu); return (zx * zx) % warukazu; } double bekid(double w, long long r) { if (r == 0) return 1.0; if (r == 1) return w; if (r % 2) return bekid(w, r - 1) * w; double f = bekid(w, r / 2); return f * f; } long long a[1000020]; void dfs(long long r) { if (r == 0) return; if (r == 2) { a[1] = 2, a[2] = 1; return; } long long t = -1; for (long long j = 0; j < 30; j++) if (r & (1 << j)) t = j; long long g = (1 << (t + 1)) - 1; for (long long i = (1 << t); i <= r; i++) { a[i] = g - i; a[g - i] = i; } dfs(g - r - 1); } bool ch(long long r) { if (r % 2) return false; dfs(r); return true; } vector<long long> ve[30]; void ch2(long long r) { cout << YES << endl; if (r == 6) { cout << 3 6 1 5 4 2 << endl; return; } ve[0].push_back(6); ve[0].push_back(1); ve[0].push_back(5); ve[0].push_back(4); ve[0].push_back(7); ve[0].push_back(2); ve[0].push_back(3); for (long long i = 8; i <= r; i++) { long long t = 0; for (long long j = 0; j < 30; j++) if (i & (1 << j)) t = j; ve[t].push_back(i); } for (long long i = 0; i < 30; i++) if (ve[i].size()) { cout << ve[i].back() << ; for (long long j = 0; j < ve[i].size() - 1; j++) cout << ve[i][j] << ; } cout << endl; exit(0); } signed main() { long long n; cin >> n; if (ch(n)) { cout << YES << endl; for (long long i = 1; i <= n; i++) cout << a[i] << ; cout << endl; } else cout << NO << endl; if (n <= 5 || (n & (-n)) == n) cout << NO << endl; else ch2(n); return 0; for (long long i = 1; i <= n; i++) ch2(i); return 0; }
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#include <bits/stdc++.h> using namespace std; struct segment { int l, r, fu; bool operator<(const segment &temp) const { return l < temp.l; } }; segment sg[5000]; int cnt_sg; const int inf = 1e9; int xx[400], yy[400]; int cnt_x, cnt_y; struct rectangle { int lx, ly, rx, ry; }; rectangle rec[99]; int n, m, k, cnt, mc[1111][1111], nc[1111][11111], list[99], cnt_list, ls[99], cnt_ls; long long ans, now; char str[1111][1111]; bool vsx[400], vsy[400]; int main() { int i, j, s, p, q, id, dx1, dx2, dy1, dy2, lx, ly, rx, ry, pn; scanf( %d%d%d , &n, &m, &k); for (i = 0; i < n; i++) scanf( %s , str[i]); cnt = 0; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { if (str[i][j] == * && !(i > 0 && str[i - 1][j] == * ) && !(j > 0 && str[i][j - 1] == * )) { rec[cnt].lx = i; rec[cnt].ly = j; for (s = i; s < n; s++) { for (p = j; p < m; p++) { if (str[s][p] != * ) break; } if (p == j) break; rec[cnt].ry = p - 1; } rec[cnt++].rx = s - 1; } } memset(mc, 0, sizeof(mc)); memset(nc, 0, sizeof(nc)); for (i = 0; i < k; i++) mc[rec[i].lx][rec[i].ly]++; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { mc[i + 1][j] += mc[i][j]; mc[i][j + 1] += mc[i][j]; mc[i + 1][j + 1] -= mc[i][j]; } cnt_x = cnt_y = 0; for (i = 0; i < k; i++) { xx[cnt_x++] = rec[i].lx; xx[cnt_x++] = rec[i].rx; if (rec[i].lx - 1 >= 0) xx[cnt_x++] = rec[i].lx - 1; if (rec[i].rx + 1 < n) xx[cnt_x++] = rec[i].rx + 1; yy[cnt_y++] = rec[i].ly; yy[cnt_y++] = rec[i].ry; if (rec[i].ly - 1 >= 0) yy[cnt_y++] = rec[i].ly - 1; if (rec[i].ry + 1 < m) yy[cnt_y++] = rec[i].ry + 1; } sort(xx, xx + cnt_x); sort(yy, yy + cnt_y); int nn = 0; for (i = 0; i < cnt_x; i++) { if (nn == 0 || xx[nn - 1] < xx[i]) xx[nn++] = xx[i]; } cnt_x = nn; nn = 0; for (i = 0; i < cnt_y; i++) { if (nn == 0 || yy[nn - 1] < yy[i]) yy[nn++] = yy[i]; } cnt_y = nn; ans = 0; for (i = 0; i < cnt_x; i++) { if (i == 0) dx1 = xx[i] + 1; else dx1 = xx[i] - xx[i - 1]; for (j = i + 1; j <= cnt_x; j++) { if (j == cnt_x) dx2 = n - xx[j - 1]; else dx2 = xx[j] - xx[j - 1]; cnt_sg = 0; for (s = 0; s < k; s++) { if (rec[s].rx < xx[i] || rec[s].lx > xx[j - 1]) continue; if ((rec[s].rx >= xx[i] && rec[s].lx < xx[i]) || (rec[s].rx > xx[j - 1] && rec[s].lx <= xx[j - 1])) sg[cnt_sg].fu = 1; else sg[cnt_sg].fu = 0; sg[cnt_sg].l = rec[s].ly; sg[cnt_sg++].r = rec[s].ry; } sort(sg, sg + cnt_sg); nn = 0; for (s = 0; s < cnt_sg; s++) { if (nn == 0 || sg[nn - 1].r < sg[s].l) sg[nn++] = sg[s]; else if (sg[nn - 1].r < sg[s].r) { sg[nn - 1].r = sg[s].r; sg[nn - 1].fu = max(sg[nn - 1].fu, sg[s].fu); } } cnt_sg = nn; for (s = 1; s <= cnt_sg; s++) { if (s < cnt_sg) dy2 = sg[s].l - sg[s - 1].r; else dy2 = m - sg[s - 1].r; pn = 0; for (p = s - 1; p >= 0; p--) { lx = xx[i]; ly = sg[p].l; rx = xx[j - 1]; ry = sg[s - 1].r; int rs = mc[rx][ry]; if (lx > 0) rs -= mc[lx - 1][ry]; if (ly > 0) rs -= mc[rx][ly - 1]; if (lx > 0 && ly > 0) rs += mc[lx - 1][ly - 1]; if (rs > 3 || sg[p].fu == 1) break; if (rs == 0) continue; if (p == 0) dy1 = sg[p].l + 1; else dy1 = sg[p].l - sg[p - 1].r; for (q = 0; q < k; q++) { if (rec[q].lx >= lx && rec[q].rx <= rx && rec[q].ly >= ly && rec[q].ry <= ry) continue; if (rec[q].lx <= rx && rec[q].rx >= xx[i] && rec[q].ly <= ry && rec[q].ry >= ly) break; } if (q >= k) pn += dy1; } ans += (long long)pn * (long long)dy2 * (long long)dx1 * (long long)dx2; } } } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> const int N = 1e5 + 5, M = 2e5 + 5, logN = 17 + 1; int n, m, root, idx, a[N], f[N][logN], dfn[N], seq[N], sz[N], dep[N]; int tot, lnk[N], ter[M], nxt[M]; long long seg[N << 2], tag[N << 2]; void pushup(int rt) { seg[rt] = seg[rt << 1] + seg[rt << 1 | 1]; } void build(int rt, int l, int r) { if (l == r) { seg[rt] = a[seq[l]]; return; } int mid = (l + r) >> 1; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); pushup(rt); } void update(int rt, int l, int r, long long k) { seg[rt] += 1LL * (r - l + 1) * k; tag[rt] += k; } void pushdown(int rt, int l, int r) { if (!tag[rt]) return; int mid = (l + r) >> 1; update(rt << 1, l, mid, tag[rt]); update(rt << 1 | 1, mid + 1, r, tag[rt]); tag[rt] = 0; } void modify(int x, int y, int rt, int l, int r, int k) { if (x <= l && r <= y) { update(rt, l, r, k); return; } pushdown(rt, l, r); int mid = (l + r) >> 1; if (x <= mid) modify(x, y, rt << 1, l, mid, k); if (mid < y) modify(x, y, rt << 1 | 1, mid + 1, r, k); pushup(rt); } long long query(int x, int y, int rt, int l, int r) { if (x <= l && r <= y) return seg[rt]; pushdown(rt, l, r); int mid = (l + r) >> 1; long long ret = 0; if (x <= mid) ret += query(x, y, rt << 1, l, mid); if (mid < y) ret += query(x, y, rt << 1 | 1, mid + 1, r); return ret; } void add(int u, int v) { ter[++tot] = v, nxt[tot] = lnk[u], lnk[u] = tot; } void dfs(int u, int fa) { dep[u] = dep[fa] + 1, f[u][0] = fa, dfn[u] = ++idx, seq[idx] = u, sz[u] = 1; for (int i = 1; (1 << i) <= dep[u]; ++i) f[u][i] = f[f[u][i - 1]][i - 1]; for (int i = lnk[u]; i; i = nxt[i]) { int v = ter[i]; if (v == fa) continue; dfs(v, u), sz[u] += sz[v]; } } int lca(int u, int v) { if (dep[u] > dep[v]) u ^= v ^= u ^= v; for (int i = 17; ~i; --i) if (dep[f[v][i]] >= dep[u]) v = f[v][i]; if (u == v) return u; for (int i = 17; ~i; --i) if (f[u][i] ^ f[v][i]) u = f[u][i], v = f[v][i]; return f[u][0]; } int getlca(int u, int v, int p) { int x = lca(u, v), y = lca(u, p), z = lca(v, p); if (dep[y] > dep[x]) x = y; if (dep[z] > dep[x]) x = z; return x; } int jump(int u, int d) { for (int i = 17; ~i; --i) if (d & (1 << i)) u = f[u][i]; return u; } void treeModify(int u, int k) { int l = dfn[u], r = dfn[u] + sz[u] - 1; if (u == root) modify(1, n, 1, 1, n, k); else if (dfn[root] < l || dfn[root] > r) modify(l, r, 1, 1, n, k); else { int son = jump(root, dep[root] - dep[u] - 1); modify(1, n, 1, 1, n, k), modify(dfn[son], dfn[son] + sz[son] - 1, 1, 1, n, -k); } } long long treeQuery(int u) { int l = dfn[u], r = dfn[u] + sz[u] - 1; if (u == root) return query(1, n, 1, 1, n); else if (dfn[root] < l || dfn[root] > r) return query(l, r, 1, 1, n); else { int son = jump(root, dep[root] - dep[u] - 1); return query(1, n, 1, 1, n) - query(dfn[son], dfn[son] + sz[son] - 1, 1, 1, n); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); add(u, v), add(v, u); } dfs(1, 0); build(1, 1, n); root = 1; while (m--) { int opt; scanf( %d , &opt); if (opt == 1) { scanf( %d , &root); } else if (opt == 2) { int u, v, x; scanf( %d%d%d , &u, &v, &x); treeModify(getlca(u, v, root), x); } else { int x; scanf( %d , &x); printf( %lld n , treeQuery(x)); } } return 0; }
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#include <bits/stdc++.h> using namespace std; long long a[20]; long long b[20][10][10]; long long c[20][10][10]; long long dp(long long n, int p) { long long n0 = n; long long ans = 0; while (n >= 10) { long long m = n; long long e = 0; while ((m + 10) % (a[e] * 10) < 10) e++; if (e == 1 || a[e] >= n) { long long m = n; int k = 0; while (m != 0) { if (m % 10 >= k) k = m % 10; m = m / 10; } ans += 1; if (p < k) n -= k; else n -= p; continue; } int i = 0; int k = 0; for (i; m != 0; i++) { if (i >= e && m % 10 >= k) k = m % 10; m = m / 10; } if (k < p) k = p; if (b[e][(n + 10) % a[e]][k] == -1) { dp(n % a[e], k); } ans += b[e][(n + 10) % a[e]][k]; n = n / a[e] * a[e] + c[e][(n + 10) % a[e]][k]; } long long e = 0; while ((n0 + 10) % (a[e] * 10) < 10) e++; if (a[e] > n0) { b[e][(n0 + 10) % a[e]][p] = ans; c[e][(n0 + 10) % a[e]][p] = n; } return ans; } int main() { a[0] = 1; for (int i = 1; i <= 18; i++) a[i] = a[i - 1] * 10; for (int i = 0; i < 20; i++) for (int j = 0; j < 10; j++) for (int k = 0; k < 10; k++) { b[i][j][k] = -1; c[i][j][k] = -1; } long long n; cin >> n; if (n == 0) { cout << 0 << endl; return 0; } cout << dp(n, 0) + 1 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> a(n), b(m); int an; cin >> an; for (int i = 0; i < an; ++i) { int t; cin >> t; a[t] = 1; } int bn; cin >> bn; for (int i = 0; i < bn; ++i) { int t; cin >> t; b[t] = 1; } int lim = n * m; while (1) { bool ch = false; for (int i = 0; i < lim; ++i) { if (a[i % n] != b[i % m]) { ch = true; a[i % n] = b[i % m] = 1; } } if (!ch) break; } bool ans = true; for (int i = 0; i < n; ++i) ans &= a[i]; for (int i = 0; i < m; ++i) ans &= b[i]; cout << (ans ? Yes : No ); return 0; }
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//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Mux packets from multiple FIFO interfaces onto a single one.
// Can alternate or give priority to one port (port 0)
// In prio mode, port 1 will never get access if port 0 is always busy
module fifo19_mux
#(parameter prio = 0)
(input clk, input reset, input clear,
input [18:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
input [18:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
output [18:0] data_o, output src_rdy_o, input dst_rdy_i);
wire [18:0] data0_int, data1_int;
wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int;
fifo_short #(.WIDTH(19)) mux_fifo_in0
(.clk(clk), .reset(reset), .clear(clear),
.datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o),
.dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int));
fifo_short #(.WIDTH(19)) mux_fifo_in1
(.clk(clk), .reset(reset), .clear(clear),
.datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o),
.dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int));
localparam MUX_IDLE0 = 0;
localparam MUX_DATA0 = 1;
localparam MUX_IDLE1 = 2;
localparam MUX_DATA1 = 3;
reg [1:0] state;
wire eof0 = data0_int[17];
wire eof1 = data1_int[17];
wire [18:0] data_int;
wire src_rdy_int, dst_rdy_int;
always @(posedge clk)
if(reset | clear)
state <= MUX_IDLE0;
else
case(state)
MUX_IDLE0 :
if(src0_rdy_int)
state <= MUX_DATA0;
else if(src1_rdy_int)
state <= MUX_DATA1;
MUX_DATA0 :
if(src0_rdy_int & dst_rdy_int & eof0)
state <= prio ? MUX_IDLE0 : MUX_IDLE1;
MUX_IDLE1 :
if(src1_rdy_int)
state <= MUX_DATA1;
else if(src0_rdy_int)
state <= MUX_DATA0;
MUX_DATA1 :
if(src1_rdy_int & dst_rdy_int & eof1)
state <= MUX_IDLE0;
default :
state <= MUX_IDLE0;
endcase // case (state)
assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0;
assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
fifo_short #(.WIDTH(19)) mux_fifo
(.clk(clk), .reset(reset), .clear(clear),
.datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
.dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
endmodule // fifo19_mux
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module maquina_4_estados(clock_50mhz, clock_1hz, segmentos, anodos,estado);
input clock_50mhz; //entrada de oscilacion del cristal externo
output clock_1hz; //clock 1 segundo
output reg [6:0] segmentos = 7'b3F; //apagar segmentos
output reg [1:0] anodos = 0; //encender display1 y display 2 con el rotabit
output reg [1:0] estado = 0; //estado inicial para conectar 2 leds, 00, 01, 10, 11, 00 y se repite
reg [25:0] cuenta_para_1hz = 0; //inicializacion de la variable que servira para generar la salida de 1hz
reg [25:0] cuenta_para_2khz = 0;
reg clock_2khz = 0;
reg [1:0] rotabit = 0; // para otra maquina de estados
parameter [6:0] cero = 0; //falta definir constante
parameter [6:0] uno = 0; //falta definir parameter
parameter [6:0] dos = 0; // falta definir parameter
parameter [6:0] tres = 0; //falta definir parameter
always @(posedge clock_50mhz) //genera una señal de 1hz
begin
cuenta_para_1hz = cuenta_para_1hz + 1;
if(cuenta_para_1hz == 25_000_000)
begin
clock_1hz = ~clock_1hz; //genera la señal de oscialcion, esta señal empezo en 0, valor inicial
cuenta_para_1hz = 0; // resetea el contador
end
end
always @(posedge clock_50mhz) // genera 1 señal de 2khz bueno no es cierto, hay que calcular bien el valor limite de la cuenta
begin
cuenta_para_2khz = cuenta_para_2khz + 1;
if(cuenta_para_2khz == 55_000)
begin
clock_2khz = ~clock_2khz; //genera la señal de oscialcion, esta señal empezo en 0, valor inicial
cuenta_para_2khz = 0; // resetea el contador
end
end
always @(posedge clock_2khz)
begin
case(rotabit)
0: rotabit <= 1;
1: rotabit <= 0;
endcase
end
always @(rotabit)
begin
case(rotabit)
0: anodos = 2'b01;
1: anodos= 2'b10;
endcase
end
always @(posedge clock_1hz)
begin
case(estado)
0: estado <= 1;
1: estado <= 2;
2: estado <= 3;
3: estado <= 4;
endcase
end
always @(estado)
begin
case(estado)
0: segmentos = cero;
1: segmentos = uno;
2: segmentos = dos;
3: segmentos = tres;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, n, x, j, c = 0; cin >> n >> x; if (n >= x) { for (i = 2; i <= n; i++) { if (x % i == 0 && (x / i) <= n) c++; } cout << c + 1 << endl; } else { for (i = 2; i <= n; i++) { if (x % i == 0 && (x / i) <= n) c++; } cout << c << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int NUM = 2e5 + 10; struct node { int index, q; bool operator<(const node &a) const { return index + q < a.index + a.q; } } no[NUM]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d%d , &no[i].index, &no[i].q); sort(no, no + n); int ans = 1, last = 0; for (int i = 1; i < n; i++) { if (no[i].index - no[i].q >= no[last].index + no[last].q) { last = i; ans++; } } printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_FUNCTIONAL_V
|
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $
//
// Module: fallthrough_small_fifo.v
// Project: utils
// Description: small fifo with fallthrough i.e. data valid when rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 2/11/09 -- jnaous: Rewrote to make much more efficient.
// 5/11/11 -- hyzeng: Rewrote based on http://www.billauer.co.il/reg_fifo.html
// to improve timing by adding output register
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module fallthrough_small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
reg fifo_valid, middle_valid, dout_valid;
reg [(WIDTH-1):0] middle_dout;
wire [(WIDTH-1):0] fifo_dout;
wire fifo_empty, fifo_rd_en;
wire will_update_middle, will_update_dout;
// orig_fifo is just a normal (non-FWFT) synchronous or asynchronous FIFO
small_fifo
#(.WIDTH (WIDTH),
.MAX_DEPTH_BITS (MAX_DEPTH_BITS),
.PROG_FULL_THRESHOLD (PROG_FULL_THRESHOLD))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (fifo_rd_en),
.dout (fifo_dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (fifo_empty),
.reset (reset),
.clk (clk)
);
assign will_update_middle = fifo_valid && (middle_valid == will_update_dout);
assign will_update_dout = (middle_valid || fifo_valid) && (rd_en || !dout_valid);
assign fifo_rd_en = (!fifo_empty) && !(middle_valid && dout_valid && fifo_valid);
assign empty = !dout_valid;
always @(posedge clk) begin
if (reset)
begin
fifo_valid <= 0;
middle_valid <= 0;
dout_valid <= 0;
dout <= 0;
middle_dout <= 0;
end
else
begin
if (will_update_middle)
middle_dout <= fifo_dout;
if (will_update_dout)
dout <= middle_valid ? middle_dout : fifo_dout;
if (fifo_rd_en)
fifo_valid <= 1;
else if (will_update_middle || will_update_dout)
fifo_valid <= 0;
if (will_update_middle)
middle_valid <= 1;
else if (will_update_dout)
middle_valid <= 0;
if (will_update_dout)
dout_valid <= 1;
else if (rd_en)
dout_valid <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, inf = 1061109567; const long long infll = 4557430888798830399; const int N = 2e5 + 5; int n, q, a[N], cnt[N]; bool last[N], first[N]; vector<int> app[N]; bool start[N]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> q; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) app[a[i]].push_back(i); for (int i = 0; i < N; i++) if (app[i].size()) { first[app[i][0]] = 1; last[app[i].back()] = 1; } int thing = 0; memset(start, 0, sizeof start); start[0] = 1; for (int i = 0; i < n; i++) { if (first[i]) thing++; if (last[i]) thing--; if (!thing) start[i + 1] = 1; } int ans = 0; int cur = 0; while (cur < n) { int nxt = n - 1; for (int i = cur + 1; i < n; i++) if (start[i]) { nxt = i - 1; break; } int lolMax = 0; for (int i = cur; i < nxt + 1; i++) { cnt[a[i]]++; lolMax = max(lolMax, cnt[a[i]]); } ans += lolMax; for (int i = cur; i < nxt + 1; i++) cnt[a[i]]--; cur = nxt + 1; } cout << n - ans; return 0; }
|
module tracemon_tb();
reg[31:0] wave2decode_instr_pc;
reg[31:0] wave2decode_instr;
reg wave2decode_instr_valid;
reg[8:0] wave2decode_sgpr_base;
reg[9:0] wave2decode_vgpr_base;
reg[9:0] wave2decode_lds_base;
reg salu2exec_wr_exec_en;
reg[63:0] salu2exec_wr_exec_value;
reg salu2exec_wr_vcc_en;
reg[63:0] salu2exec_wr_vcc_value;
reg salu_wr_scc_en;
reg salu_wr_scc_value;
reg salu2sgpr_dest_wr_en;
reg[8:0] salu2sgpr_dest_addr;
reg[31:0] salu2sgpr_dest_data;
reg simd12exec_wr_vcc_en;
reg[63:0] simd12exec_wr_vcc_value;
reg simd12vgpr_dest_wr_en;
reg[9:0] simd12vgpr_dest_addr;
reg[2047:0] simd12vgpr_dest_data;
reg[63:0] simd12vgpr_wr_mask;
reg simd22exec_wr_vcc_en;
reg[63:0] simd22exec_wr_vcc_value;
reg simd22vgpr_dest_wr_en;
reg[9:0] simd22vgpr_dest_addr;
reg[2047:0] simd22vgpr_dest_data;
reg[63:0] simd22vgpr_wr_mask;
reg simd32exec_wr_vcc_en;
reg[63:0] simd32exec_wr_vcc_value;
reg simd32vgpr_dest_wr_en;
reg[9:0] simd32vgpr_dest_addr;
reg[2047:0] simd32vgpr_dest_data;
reg[63:0] simd32vgpr_wr_mask;
reg simd42exec_wr_vcc_en;
reg[63:0] simd42exec_wr_vcc_value;
reg simd42vgpr_dest_wr_en;
reg[9:0] simd42vgpr_dest_addr;
reg[2047:0] simd42vgpr_dest_data;
reg[63:0] simd42vgpr_wr_mask;
reg lsu2sgpr_dest_wr_en;
reg[8:0] lsu2sgpr_dest_addr;
reg[31:0] lsu2sgpr_dest_data;
reg lsu2vgpr_dest_wr_en;
reg[2047:0] lsu2vgpr_dest_data;
reg[9:0] lsu_dest_str_addr;
reg[63:0] lsu_dest_str_mask;
reg[2047:0] lsu_addr;
reg[2047:0] lsu_store_data;
reg issue_halt;
reg[5:0] issue_halt_wfid;
reg salu_retire_valid, simd1_retire_valid, simd2_retire_valid, simd3_retire_valid, simd4_retire_valid, lsu_retire_valid;
reg[31:0] salu_retire_pc, simd1_retire_pc, simd2_retire_pc, simd3_retire_pc, simd4_retire_pc, lsu_retire_pc;
reg[5:0] wave2decode_wfid, salu_wfid, simd1_wfid, simd2_wfid, simd3_wfid, simd4_wfid, lsu_wfid;
reg clk, rst;
tracemon tm(
wave2decode_instr_valid,
wave2decode_instr,
wave2decode_instr_pc,
wave2decode_sgpr_base,
wave2decode_vgpr_base,
wave2decode_lds_base,
wave2decode_wfid,
salu2exec_wr_exec_en,
salu2exec_wr_exec_value,
salu2exec_wr_vcc_en,
salu2exec_wr_vcc_value,
salu_wr_scc_en,
salu_wr_scc_value,
salu2sgpr_dest_wr_en,
salu2sgpr_dest_addr,
salu2sgpr_dest_data,
simd12exec_wr_vcc_en,
simd12exec_wr_vcc_value,
simd12vgpr_dest_wr_en,
simd12vgpr_dest_addr,
simd12vgpr_dest_data,
simd12vgpr_wr_mask,
simd22exec_wr_vcc_en,
simd22exec_wr_vcc_value,
simd22vgpr_dest_wr_en,
simd22vgpr_dest_addr,
simd22vgpr_dest_data,
simd22vgpr_wr_mask,
simd32exec_wr_vcc_en,
simd32exec_wr_vcc_value,
simd32vgpr_dest_wr_en,
simd32vgpr_dest_addr,
simd32vgpr_dest_data,
simd32vgpr_wr_mask,
simd42exec_wr_vcc_en,
simd42exec_wr_vcc_value,
simd42vgpr_dest_wr_en,
simd42vgpr_dest_addr,
simd42vgpr_dest_data,
simd42vgpr_wr_mask,
lsu2sgpr_dest_wr_en,
lsu2sgpr_dest_addr,
lsu2sgpr_dest_data,
lsu2vgpr_dest_wr_en,
lsu2vgpr_dest_data,
lsu_dest_str_addr,
lsu_dest_str_mask,
lsu_addr,
lsu_store_data,
issue_halt,
issue_halt_wfid,
salu_retire_valid,
salu_retire_pc,
salu_wfid,
simd1_retire_valid,
simd1_retire_pc,
simd1_wfid,
simd2_retire_valid,
simd2_retire_pc,
simd2_wfid,
simd3_retire_valid,
simd3_retire_pc,
simd3_wfid,
simd4_retire_valid,
simd4_retire_pc,
simd4_wfid,
lsu_retire_valid,
lsu_retire_pc,
lsu_wfid,
clk,
rst
);
initial begin
clk = 0;
while (1) begin
#2;
clk = ~clk;
end
end
initial begin
rst = 1;
salu_retire_valid = 0;
simd1_retire_valid = 0;
simd2_retire_valid = 0;
simd3_retire_valid = 0;
simd4_retire_valid = 0;
lsu_retire_valid = 0;
#11
wave2decode_instr_valid = 1;
wave2decode_instr_pc = 0;
wave2decode_instr = 10;
wave2decode_sgpr_base = 1;
wave2decode_vgpr_base = 2;
wave2decode_lds_base = 3;
wave2decode_wfid = 0;
#4
wave2decode_instr_valid = 1;
wave2decode_instr_pc = 1;
wave2decode_instr = 20;
wave2decode_sgpr_base = 1;
wave2decode_vgpr_base = 2;
wave2decode_lds_base = 3;
wave2decode_wfid = 0;
#4
wave2decode_instr_valid = 1;
wave2decode_instr_pc = 2;
wave2decode_instr = 30;
wave2decode_sgpr_base = 1;
wave2decode_vgpr_base = 2;
wave2decode_lds_base = 3;
wave2decode_wfid = 0;
/*
#4
salu_retire_valid = 1;
salu_retire_pc = 0;
salu_wfid = 0;
salu2sgpr_dest_wr_en = 1;
salu_wr_scc_en = 1;
salu2sgpr_dest_data = 23;
salu2sgpr_dest_addr = 4;
salu_wr_scc_value = 1;
#4
salu_retire_valid = 0;
*/
/*
#4
simd3_retire_valid = 1;
simd3_retire_pc = 2;
simd3_wfid = 0;
simd32vgpr_wr_mask = 7;
simd32vgpr_dest_wr_en = 1;
simd32exec_wr_vcc_en = 0;
simd32vgpr_dest_data = 2048'h0000_1234_0000_5678;
simd32vgpr_dest_addr = 4;
simd32exec_wr_vcc_value = 1;
simd4_retire_valid = 1;
simd4_retire_pc = 1;
simd4_wfid = 0;
simd42vgpr_wr_mask = 10;
simd42vgpr_dest_wr_en = 1;
simd42exec_wr_vcc_en = 1;
simd42vgpr_dest_data = 2047'h0000_1234_0000_5678;
simd42vgpr_dest_addr = 4;
simd42exec_wr_vcc_value = 2;
#4
simd3_retire_valid = 0;
simd4_retire_valid = 0;
*/
#4
lsu_retire_valid = 1;
lsu_retire_pc = 0;
lsu_wfid = 0;
lsu2vgpr_dest_wr_en = 1;
lsu_dest_str_addr = 6;
lsu_addr = 2047'h0000_1234_0000_5678;
lsu_dest_str_mask = 7;
lsu2vgpr_dest_data = 15;//2047'h0000_5678_0000_1234;
#4
lsu_retire_valid = 0;
#10
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, t, k; vector<int> g[200010]; int par[200010]; int nodeId; int leaf; vector<int> deep[200010]; int a[200010]; void createGraph(int x, int level) { if (level > t) return; for (int i = 1; i <= a[level]; i++) { g[x].push_back(++nodeId); par[nodeId] = x; deep[level].push_back(nodeId); } leaf += a[level]; if (level != t) leaf--; createGraph(nodeId, level + 1); } void adjust(int dp) { queue<int> Q; for (int i : deep[dp]) { if (g[i].size() == 0) { Q.push(i); } } int size = deep[dp + 1].size(); for (int i = 0; i < size - 1; i++) { if (Q.empty()) break; if (leaf <= k) break; int node = deep[dp + 1][i]; par[node] = Q.front(); Q.pop(); --leaf; } } int main(int argc, char const *argv[]) { nodeId = 1; scanf( %d %d %d , &n, &t, &k); for (int i = 1; i <= t; i++) { scanf( %d , a + i); } createGraph(1, 1); if (leaf < k) { printf( -1 n ); exit(0); } for (int i = 1; i < t; i++) { adjust(i); } if (leaf != k) { printf( -1 n ); exit(0); } printf( %d n , n); for (int i = 2; i <= n; i++) { printf( %d %d n , par[i], i); } return 0; }
|
#include <bits/stdc++.h> int main(void) { char a[3][3]; scanf( %3s , a[0]); scanf( %3s , a[1]); scanf( %3s , a[2]); for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) if (a[i][j] != a[((((i)-1) * -1) + 1)][((((j)-1) * -1) + 1)]) { puts( NO ); return EXIT_SUCCESS; } puts( YES ); return EXIT_SUCCESS; }
|
#include <bits/stdc++.h> using namespace std; int helper(long long int edges, long long int nodes) { if (edges == nodes - 1) return nodes - 1; edges -= nodes - 1; return nodes - 1 - ceil((1.0 + sqrt(1.0 + 8.0 * edges)) / 2.0); } int main() { ios::sync_with_stdio(false); ; cin.tie(0); ; long long int i, j, q, n, lo, mid, hi; cin >> q; while (q--) { cin >> n; lo = n - 1; hi = (n * (n - 1)) / 2 + 1; while (hi - lo > 1) { mid = (lo + hi) / 2; if (helper(mid, n) >= (mid + 1) / 2) lo = mid; else hi = mid; } cout << lo << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
|
/*
*
* Copyright (c) 2013
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module ff_sub (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
input [255:0] rx_p,
output reg tx_done = 1'b0,
output reg [255:0] tx_a = 256'd0
);
reg carry;
always @ (posedge clk)
begin
if (!tx_done)
begin
if (carry)
tx_a <= tx_a + rx_p;
tx_done <= 1'b1;
end
if (reset)
begin
{carry, tx_a} <= rx_a - rx_b;
tx_done <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6, maxm = 1e6; unsigned int degree[maxn + 10], blk[maxn + 10]; namespace find { unsigned int fa[maxn + 10], siz[maxn + 10]; inline void Init(const unsigned int n) { iota(fa, fa + n + 1, 0); fill(siz, siz + n + 1, 1); } unsigned int GetFather(const unsigned int x) { return fa[x] == x ? x : fa[x] = GetFather(fa[x]); } inline void Merge(const unsigned int x, const unsigned int y) { unsigned int fx = GetFather(x), fy = GetFather(y); if (fx == fy) return; if (siz[fx] < siz[fy]) swap(fx, fy); fa[fy] = fx; siz[fx] += siz[fy]; } } // namespace find int main() { ios_base::sync_with_stdio(false); unsigned int n, m; cin >> n >> m; find::Init(n); for (unsigned int i = 0; i < m; ++i) { unsigned int a, b; cin >> a >> b; find::Merge(a, b); ++degree[a]; ++degree[b]; } unsigned long long ans = 0; const unsigned int r = find::GetFather(1); bool fl = true; for (unsigned int i = 1; i <= n; ++i) { if (degree[i] & 0x01) ++blk[find::GetFather(i)]; if (degree[i] && find::GetFather(i) != r) fl = false; } if (fl && !blk[r]) { cout << 0 << endl; return 0; } for (unsigned int i = 1; i <= n; ++i) if (find::GetFather(i) == i) { ans += blk[i] / 2; if (degree[i] && !blk[i]) ++ans; } if (!degree[1] && find::siz[1] == 1 && find::GetFather(1) == 1) ++ans; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[200010]; long long vis[200100]; long long x, n, k, sum, y; string s; long long dfs(long long x, long long k, long long y) { if (x == y) return k; return dfs(a[x], k + 1, y); } long long poww(long long ba) { if (ba == 0) return 1; if (ba == 1) return 3; if (ba % 2 == 0) return poww(ba / 2) * poww(ba / 2); return poww(ba / 2) * poww(ba / 2) * 3; } int main() { long long q; cin >> q; while (q--) { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { cout << dfs(a[i], 0, i) + 1 << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int a, b, x, y, n; cin >> a >> b >> x >> y >> n; cout << min(max(x, a - n) * max(y, b - n + min(n, a - x)), max(y, b - n) * max(x, a - n + min(n, b - y))) << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDLCLKP_PP_SYMBOL_V
|
#include <bits/stdc++.h> typedef long long ll; using namespace std; int main(){ ios::sync_with_stdio(0); cin.tie(0); ll t; cin >> t; while(t--){ ll n; cin >> n; ll x[n]; for(ll i=0; i<n; i++){ cin >> x[i]; } vector<ll> v; for(ll i=0; i<n; i++){ for(ll j=0; j<n; j++){ if(i != j && find(v.begin(), v.end(), abs(x[i]-x[j])) == v.end()){ v.push_back(abs(x[i]-x[j])); } } } cout << v.size() << n ; } }
|
/*
* SPI input timing:
* CS is active low
* CLK is rising edge
*
* The clk_pin is clk/2.
* TODO: generated clk_pin with a DDR output so that it is one bit per cycle.
*/
module mpc4922(
input clk,
input reset,
// physical interface
output cs_pin,
output clk_pin,
output data_pin,
// logical interface
input [11:0] value,
input axis,
input strobe,
output ready
);
parameter GAIN = 1'b1; // Normal gain
parameter BUFFERED = 1'b1; // buffered
parameter SHUTDOWN = 1'b1; // not shutdown
reg [15:0] cmd;
reg [4:0] bits;
assign ready = !reset && bits == 0;
assign cs_pin = ready; // negative logic
assign data_pin = cmd[15];
always @(posedge clk)
begin
if (reset) begin
bits <= 0;
clk_pin <= 0;
end else
if (strobe) begin
cmd <= { axis, BUFFERED, GAIN, SHUTDOWN, value };
bits <= 16;
clk_pin <= 0;
end else
if (bits != 0) begin
if (clk_pin) begin
// change when it is currently high
cmd <= { cmd[14:0], 1'b0 };
clk_pin <= 0;
bits <= bits - 1;
end else begin
// rising edge clocks the data
clk_pin <= 1;
end
end else begin
clk_pin <= 0;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// CLOCK_MODULE
//
//
// Description: This module takes the reference clock as
// input, and produces a divided clock on a global clock net suitable
// for driving application logic connected to the Aurora User Interface.
//
`timescale 1 ns / 10 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_0_CLOCK_MODULE #
(
parameter MULT = 14,
parameter DIVIDE = 1,
parameter CLK_PERIOD = 10.240 ,
parameter OUT0_DIVIDE = 28,
parameter OUT1_DIVIDE = 14,
parameter OUT2_DIVIDE = 20,
parameter OUT3_DIVIDE = 8
)
(
INIT_CLK, // ymei
INIT_CLK_O,
CLK,
CLK_LOCKED,
USER_CLK,
SYNC_CLK,
MMCM_NOT_LOCKED
);
`define DLY #1
//***********************************Port Declarations*******************************
input INIT_CLK; // ymei
output INIT_CLK_O;
input CLK;
input CLK_LOCKED;
output USER_CLK;
output SYNC_CLK;
output MMCM_NOT_LOCKED;
//*********************************Wire Declarations**********************************
(* KEEP = "TRUE" *) wire clk_not_locked_i;
wire sync_clk_i;
wire user_clk_i;
wire clkfbout_i;
wire clkfbout;
wire locked_i;
wire clk_in_i;
//*********************************Main Body of Code**********************************
// 7 series MMCM module starts here
// Invert gtp clock locked
assign clk_not_locked_i = !CLK_LOCKED;
assign MMCM_NOT_LOCKED = !locked_i;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVIDE),
.CLKFBOUT_MULT_F (MULT),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (OUT0_DIVIDE),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLK_PERIOD),
.CLKOUT1_DIVIDE (OUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (OUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (OUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (),
.CLKOUT0 (user_clk_i),
.CLKOUT0B (),
.CLKOUT1 (sync_clk_i),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clk_in_i),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_i),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (clk_not_locked_i));
// BUFG for the feedback clock. The feedback signal is phase aligned to the input
// and must come from the CLK0 or CLK2X output of the PLL. In this case, we use
// the CLK0 output.
BUFG txout_clock_net_i
(
.I(CLK),
.O(clk_in_i)
);
BUFG sync_clock_net_i
(
.I(sync_clk_i),
.O(SYNC_CLK)
);
BUFG user_clk_net_i
(
.I(user_clk_i),
.O(USER_CLK)
);
/* ymei
IBUFDS IBUFDS_INIT_CLK
(
.I (INIT_CLK_P),
.IB (INIT_CLK_N),
.O (INIT_CLK_IN)
);
BUFG initclk_bufg_i
(
.I (INIT_CLK_IN),
.O (INIT_CLK_O)
);
*/
// 7 series MMCM module ends here
// ymei
assign INIT_CLK_O = INIT_CLK;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int max_n = 300011, log_n = 32, max_m = 111, mod = 1000000007, inf = 1011111111; const long double eps = 1e-7; struct bor { stack<pair<int, int> > st; int t[max_n][27], res[max_n], sz[max_n], n; bor() { for (int i = 0; i < max_n; ++i) { for (int q = 0; q < 27; ++q) { t[i][q] = -1; } } } void add(int x, int y, char c) { t[x][c - a ] = y; } int get_sz(int v) { int ans = 1; for (int i = 0; i < 26; ++i) { if (t[v][i] != -1) { ans += get_sz(t[v][i]); } } return sz[v] = ans; } int mrg(int v, int v1) { int ans = 1; for (int i = 0; i < 27; ++i) { if (t[v][i] != -1 && t[v1][i] != -1) { ans += mrg(t[v][i], t[v1][i]); } else if (t[v][i] != -1) { t[v1][i] = t[v][i]; st.push(make_pair(v1, i)); } } return ans; } void get(int v, int p) { int mx = 0, mxx = -1; for (int i = 0; i < 26; ++i) { if (t[v][i] != -1 && mx < sz[t[v][i]]) { mx = sz[t[v][i]]; mxx = i; } } if (mxx == -1) { return; } res[p]++; for (int i = 0; i < 26; ++i) { if (i == mxx) continue; if (t[v][i] != -1) { res[p] += mrg(t[v][i], t[v][mxx]); } } while (st.size()) { t[st.top().first][st.top().second] = -1; st.pop(); } } void get_all(int v, int p) { get(v, p); for (int i = 0; i < 26; ++i) { if (t[v][i] != -1) { get_all(t[v][i], p + 1); } } } }; bor br; int n; int main() { cin >> n; for (int i = 0; i < n - 1; ++i) { int a, b; char c; cin >> a >> b >> c; br.add(a - 1, b - 1, c); } br.get_sz(0); br.get_all(0, 0); int mx = 0, mxx = 0; for (int i = 0; i < n; ++i) { if (mx < br.res[i]) { mx = br.res[i]; mxx = i; } } cout << n - mx << endl << mxx + 1 << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
|
//-----------------------------------------------------
// Design Name : hw2_B_testbench
// File Name : hw2_B_testbench.v
// Function : This program will test hw2_B.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
module hw2_B_testbench ;
reg in;
reg clk, rst_n;
wire out;
hw2_B B(
in,
clk,
rst_n,
out,
);
initial begin
#0 rst_n = 1'b0; clk = 1'b0;
#20 rst_n = 1'b1; in = 1'b0;
$display ("====================================================================");
$display ("Time %t", $time);
$display ("rst_n = %b\tin = %b\tout = %b",
rst_n, in, out);
$display ("====================================================================");
end
wire [17:0] inputArr = 18'b0111_0001_0011_1110_00; // Test pattern
integer i;
initial begin
#20 $display ("Simulate hw2_B");
for (i = 17; i >= 0; i = i - 1) begin
#20 in = inputArr[i];
$display ("====================================================================");
$display ("Time %t", $time);
$display ("rst_n = %b\tin = %b\tout = %b",
rst_n, in, out);
$display ("====================================================================");
end
#40 $finish;
end
always begin
#10 clk = ~clk;
end
initial begin
$fsdbDumpfile("hw2_B_testbench.fsdb");
$fsdbDumpvars;
end
endmodule // End of Module hw2_B_testbench
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2017 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/);
// Note that a packed array is required, otherwise some simulators will return bad
// results using *ElemVecVal() routines instead of scalar *Elem() routines.
bit [0:0] i_bit_p1_u1 [2:-2];
bit [0:0] o_bit_p1_u1 [2:-2];
bit [0:0] q_bit_p1_u1 [2:-2];
bit [60:0] i_bit61_p1_u1 [2:-2];
bit [60:0] o_bit61_p1_u1 [2:-2];
bit [60:0] q_bit61_p1_u1 [2:-2];
bit [91:0] i_bit92_p1_u1 [2:-2];
bit [91:0] o_bit92_p1_u1 [2:-2];
bit [91:0] q_bit92_p1_u1 [2:-2];
bit [11:0] i_bit12_p1_u2 [2:-2] [-3:3];
bit [11:0] o_bit12_p1_u2 [2:-2] [-3:3];
bit [11:0] q_bit12_p1_u2 [2:-2] [-3:3];
bit [29:1] i_bit29_p1_u3 [2:-2] [-3:3] [4:-4];
bit [29:1] o_bit29_p1_u3 [2:-2] [-3:3] [4:-4];
bit [29:1] q_bit29_p1_u3 [2:-2] [-3:3] [4:-4];
import "DPI-C" function void dpii_bit_vecval_p1_u1
(int bits, int p, int u, input bit [0:0] i [], output bit [0:0] o [], output bit [0:0] q []);
import "DPI-C" function void dpii_bit61_vecval_p1_u1
(int bits, int p, int u, input bit [60:0] i [], output bit [60:0] o [], output bit [60:0] q []);
import "DPI-C" function void dpii_bit92_vecval_p1_u1
(int bits, int p, int u, input bit [91:0] i [], output bit [91:0] o [], output bit [91:0] q []);
import "DPI-C" function void dpii_bit12_vecval_p1_u2
(int bits, int p, int u, input bit [11:0] i [] [], output bit [11:0] o [] [], output bit [11:0] q [] []);
import "DPI-C" function void dpii_bit29_vecval_p1_u3
(int bits, int p, int u, input bit [29:1] i [] [] [], output bit [29:1] o [] [] [], output bit [29:1] q [] [] []);
logic [0:0] i_logic_p1_u1 [2:-2];
logic [0:0] o_logic_p1_u1 [2:-2];
logic [0:0] q_logic_p1_u1 [2:-2];
logic [60:0] i_logic61_p1_u1 [2:-2];
logic [60:0] o_logic61_p1_u1 [2:-2];
logic [60:0] q_logic61_p1_u1 [2:-2];
logic [91:0] i_logic92_p1_u1 [2:-2];
logic [91:0] o_logic92_p1_u1 [2:-2];
logic [91:0] q_logic92_p1_u1 [2:-2];
logic [11:0] i_logic12_p1_u2 [2:-2] [-3:3];
logic [11:0] o_logic12_p1_u2 [2:-2] [-3:3];
logic [11:0] q_logic12_p1_u2 [2:-2] [-3:3];
logic [29:1] i_logic29_p1_u3 [2:-2] [-3:3] [4:-4];
logic [29:1] o_logic29_p1_u3 [2:-2] [-3:3] [4:-4];
logic [29:1] q_logic29_p1_u3 [2:-2] [-3:3] [4:-4];
import "DPI-C" function void dpii_logic_vecval_p1_u1
(int logics, int p, int u, input logic [0:0] i [], output logic [0:0] o [], output logic [0:0] q []);
import "DPI-C" function void dpii_logic61_vecval_p1_u1
(int logics, int p, int u, input logic [60:0] i [], output logic [60:0] o [], output logic [60:0] q []);
import "DPI-C" function void dpii_logic92_vecval_p1_u1
(int logics, int p, int u, input logic [91:0] i [], output logic [91:0] o [], output logic [91:0] q []);
import "DPI-C" function void dpii_logic12_vecval_p1_u2
(int logics, int p, int u, input logic [11:0] i [] [], output logic [11:0] o [] [], output logic [11:0] q [] []);
import "DPI-C" function void dpii_logic29_vecval_p1_u3
(int logics, int p, int u, input logic [29:1] i [] [] [], output logic [29:1] o [] [] [], output logic [29:1] q [] [] []);
import "DPI-C" function int dpii_failure();
reg [95:0] crc;
initial begin
crc = 96'h8a10a572_5aef0c8d_d70a4497;
begin
for (int a=-2; a<=2; a=a+1) begin
i_bit_p1_u1[a] = crc[0];
i_bit61_p1_u1[a] = crc[60:0];
i_bit92_p1_u1[a] = crc[91:0];
for (int b=-3; b<=3; b=b+1) begin
i_bit12_p1_u2[a][b] = crc[11:0];
for (int c=-4; c<=4; c=c+1) begin
i_bit29_p1_u3[a][b][c] = crc[29:1];
crc = {crc[94:0], crc[95]^crc[2]^crc[0]};
end
end
end
dpii_bit_vecval_p1_u1(1, 1, 1, i_bit_p1_u1, o_bit_p1_u1, q_bit_p1_u1);
dpii_bit61_vecval_p1_u1(61, 1, 1, i_bit61_p1_u1, o_bit61_p1_u1, q_bit61_p1_u1);
dpii_bit92_vecval_p1_u1(92, 1, 1, i_bit92_p1_u1, o_bit92_p1_u1, q_bit92_p1_u1);
dpii_bit12_vecval_p1_u2(12, 1, 2, i_bit12_p1_u2, o_bit12_p1_u2, q_bit12_p1_u2);
dpii_bit29_vecval_p1_u3(29, 1, 3, i_bit29_p1_u3, o_bit29_p1_u3, q_bit29_p1_u3);
for (int a=-2; a<=2; a=a+1) begin
`checkh(o_bit_p1_u1[a], ~i_bit_p1_u1[a]);
`checkh(q_bit_p1_u1[a], ~i_bit_p1_u1[a]);
`checkh(o_bit61_p1_u1[a], ~i_bit61_p1_u1[a]);
`checkh(q_bit61_p1_u1[a], ~i_bit61_p1_u1[a]);
`checkh(o_bit92_p1_u1[a], ~i_bit92_p1_u1[a]);
`checkh(q_bit92_p1_u1[a], ~i_bit92_p1_u1[a]);
for (int b=-3; b<=3; b=b+1) begin
`checkh(o_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]);
`checkh(q_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]);
for (int c=-4; c<=4; c=c+1) begin
`checkh(o_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]);
`checkh(q_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]);
end
end
end
end
begin
for (int a=-2; a<=2; a=a+1) begin
i_logic_p1_u1[a] = crc[0];
i_logic61_p1_u1[a] = crc[60:0];
i_logic92_p1_u1[a] = crc[91:0];
for (int b=-3; b<=3; b=b+1) begin
i_logic12_p1_u2[a][b] = crc[11:0];
for (int c=-4; c<=4; c=c+1) begin
i_logic29_p1_u3[a][b][c] = crc[29:1];
crc = {crc[94:0], crc[95]^crc[2]^crc[0]};
end
end
end
dpii_logic_vecval_p1_u1(1, 1, 1, i_logic_p1_u1, o_logic_p1_u1, q_logic_p1_u1);
dpii_logic61_vecval_p1_u1(61, 1, 1, i_logic61_p1_u1, o_logic61_p1_u1, q_logic61_p1_u1);
dpii_logic92_vecval_p1_u1(92, 1, 1, i_logic92_p1_u1, o_logic92_p1_u1, q_logic92_p1_u1);
dpii_logic12_vecval_p1_u2(12, 1, 2, i_logic12_p1_u2, o_logic12_p1_u2, q_logic12_p1_u2);
dpii_logic29_vecval_p1_u3(29, 1, 3, i_logic29_p1_u3, o_logic29_p1_u3, q_logic29_p1_u3);
for (int a=-2; a<=2; a=a+1) begin
`checkh(o_logic_p1_u1[a], ~i_logic_p1_u1[a]);
`checkh(q_logic_p1_u1[a], ~i_logic_p1_u1[a]);
`checkh(o_logic61_p1_u1[a], ~i_logic61_p1_u1[a]);
`checkh(q_logic61_p1_u1[a], ~i_logic61_p1_u1[a]);
`checkh(o_logic92_p1_u1[a], ~i_logic92_p1_u1[a]);
`checkh(q_logic92_p1_u1[a], ~i_logic92_p1_u1[a]);
for (int b=-3; b<=3; b=b+1) begin
`checkh(o_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]);
`checkh(q_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]);
for (int c=-4; c<=4; c=c+1) begin
`checkh(o_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]);
`checkh(q_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]);
end
end
end
end
if (dpii_failure()!=0) begin
$write("%%Error: Failure in DPI tests\n");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void chmin(T &x, const T &y) { if (x > y) x = y; } template <typename T> void chmax(T &x, const T &y) { if (x < y) x = y; } inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 48; ch = getchar(); } return x * f; } const int N = 5000 + 10; const int mod = 1e9 + 7; int n, dp[N][30], len, a[N], C[N][N], ans; signed main() { n = read(); for (int i = 1; i <= n; i++) { int ch; ch = getchar() - a + 1; if (ch != a[len]) a[++len] = ch; } C[0][0] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; dp[0][0] = 1; for (int i = 1; i <= len; i++) for (int j = i; j; j--) { int cur = a[i]; dp[j][cur] = 0; for (int k = 0; k <= 26; k++) if (k != cur) dp[j][cur] = (dp[j][cur] + dp[j - 1][k]) % mod; } for (int i = 1; i <= len; i++) { int tmp = 0; for (int j = 1; j <= 26; j++) tmp = (tmp + dp[i][j]) % mod; (ans += 1LL * tmp * C[n][i] % mod) %= mod; } cout << ans; return 0; ; }
|
// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_rx
// ============================================================
// File Name: LVDS_AD.v
// Megafunction Name(s):
// altlvds_rx
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module LVDS_AD (
rx_in,
rx_inclock,
rx_locked,
rx_out,
rx_outclock);
input [7:0] rx_in;
input rx_inclock;
output rx_locked;
output [95:0] rx_out;
output rx_outclock;
wire sub_wire0;
wire [95:0] sub_wire1;
wire sub_wire2;
wire rx_locked = sub_wire0;
wire [95:0] rx_out = sub_wire1[95:0];
wire rx_outclock = sub_wire2;
altlvds_rx altlvds_rx_component (
.rx_inclock (rx_inclock),
.rx_in (rx_in),
.rx_locked (sub_wire0),
.rx_out (sub_wire1),
.rx_outclock (sub_wire2),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset ({8{1'b0}}),
.rx_channel_data_align ({8{1'b0}}),
.rx_coreclk ({8{1'b1}}),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset ({8{1'b0}}),
.rx_dpa_locked (),
.rx_dpll_enable ({8{1'b1}}),
.rx_dpll_hold ({8{1'b0}}),
.rx_dpll_reset ({8{1'b0}}),
.rx_enable (1'b1),
.rx_fifo_reset ({8{1'b0}}),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset ({8{1'b0}}),
.rx_syncclock (1'b0));
defparam
altlvds_rx_component.common_rx_tx_pll = "OFF",
altlvds_rx_component.deserialization_factor = 12,
altlvds_rx_component.implement_in_les = "ON",
altlvds_rx_component.inclock_data_alignment = "UNUSED",
altlvds_rx_component.inclock_period = 20000,
altlvds_rx_component.inclock_phase_shift = 521,
altlvds_rx_component.input_data_rate = 600,
altlvds_rx_component.intended_device_family = "Cyclone III",
altlvds_rx_component.lpm_hint = "CBX_MODULE_PREFIX=LVDS_AD",
altlvds_rx_component.lpm_type = "altlvds_rx",
altlvds_rx_component.number_of_channels = 8,
altlvds_rx_component.pll_self_reset_on_loss_lock = "ON",
altlvds_rx_component.port_rx_channel_data_align = "PORT_UNUSED",
altlvds_rx_component.port_rx_data_align = "PORT_UNUSED",
altlvds_rx_component.registered_data_align_input = "OFF",
altlvds_rx_component.registered_output = "ON",
altlvds_rx_component.use_external_pll = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "600"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "12"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INCLOCK_PHASE_SHIFT STRING "56.25"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: Int_Device STRING "Cyclone III"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "1"
// Retrieval info: PRIVATE: Le_Serdes STRING "ON"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "8"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "50.00"
// Retrieval info: PRIVATE: PLL_Period STRING "20.000"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "0"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "0"
// Retrieval info: PRIVATE: Use_Ext_Data_Align NUMERIC "0"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "12"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "ON"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "UNUSED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "20000"
// Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "521"
// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "600"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: PORT_RX_CHANNEL_DATA_ALIGN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_RX_DATA_ALIGN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: REGISTERED_DATA_ALIGN_INPUT STRING "OFF"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: USED_PORT: rx_in 0 0 8 0 INPUT NODEFVAL rx_in[7..0]
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT_CLK_EXT GND rx_inclock
// Retrieval info: USED_PORT: rx_locked 0 0 0 0 OUTPUT NODEFVAL rx_locked
// Retrieval info: USED_PORT: rx_out 0 0 96 0 OUTPUT NODEFVAL rx_out[95..0]
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL rx_outclock
// Retrieval info: CONNECT: @rx_in 0 0 8 0 rx_in 0 0 8 0
// Retrieval info: CONNECT: rx_out 0 0 96 0 @rx_out 0 0 96 0
// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
// Retrieval info: CONNECT: rx_locked 0 0 0 0 @rx_locked 0 0 0 0
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LVDS_AD_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:640000000 ) using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); template <class T> T sqr(T x) { return x * x; } const int maxn = (int)(1e5) + 10; const int inf = (int)(2e9); struct Edge { int to, w, num; Edge() : to(0), w(0), num(0) {} Edge(int to, int w, int num) : to(to), w(w), num(num) {} }; int n, L; int x[maxn], d[maxn], t[maxn], p[maxn]; vector<Edge> g[2 * maxn]; vector<int> pt; int dist[2 * maxn], pred[2 * maxn], num[2 * maxn]; int main() { scanf( %d%d , &n, &L); set<int> spt; spt.insert(0); pt.push_back(0); spt.insert(L); pt.push_back(L); for (int i = 0; i < n; i++) { scanf( %d%d%d%d , &x[i], &d[i], &t[i], &p[i]); if (d[i] <= t[i] || x[i] - p[i] < 0) continue; if (spt.find(x[i] - p[i]) == spt.end()) { pt.push_back(x[i] - p[i]); spt.insert(x[i] - p[i]); } if (spt.find(x[i] + d[i]) == spt.end()) { pt.push_back(x[i] + d[i]); spt.insert(x[i] + d[i]); } } sort(pt.begin(), pt.end()); int N = (int)((pt).size()); for (int i = 0; i < n; i++) { if (d[i] <= t[i] || x[i] - p[i] < 0) continue; int v = int(lower_bound(pt.begin(), pt.end(), x[i] - p[i]) - pt.begin()); int u = int(lower_bound(pt.begin(), pt.end(), x[i] + d[i]) - pt.begin()); g[v].push_back(Edge(u, p[i] + t[i], i + 1)); } for (int i = 0; i < N - 1; i++) { g[i].push_back(Edge(i + 1, pt[i + 1] - pt[i], 0)); g[i + 1].push_back(Edge(i, pt[i + 1] - pt[i], 0)); } set<pair<int, int> > sd; for (int i = 0; i < N; i++) { dist[i] = inf; pred[i] = -1; num[i] = 0; } dist[0] = 0; sd.insert(make_pair(0, 0)); while (!sd.empty()) { int v = sd.begin()->second; sd.erase(sd.begin()); for (int i = 0; i < g[v].size(); i++) { if (dist[g[v][i].to] > dist[v] + g[v][i].w) { sd.erase(make_pair(dist[g[v][i].to], g[v][i].to)); dist[g[v][i].to] = dist[v] + g[v][i].w; pred[g[v][i].to] = v; num[g[v][i].to] = g[v][i].num; sd.insert(make_pair(dist[g[v][i].to], g[v][i].to)); } } } cout << dist[N - 1] << endl; vector<int> trp; for (int v = N - 1; pred[v] != -1; v = pred[v]) { if (num[v] != 0) trp.push_back(num[v]); } reverse(trp.begin(), trp.end()); cout << (int)((trp).size()) << endl; for (int i = 0; i < (int)((trp).size()); i++) { cout << trp[i] << ; } return 0; }
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_2_0 (
dout
);
output wire [2-1 : 0] dout;
xlconstant #(
.CONST_VAL(2'd0),
.CONST_WIDTH(2)
) inst (
.dout(dout)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:08:56 05/21/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(
);
endmodule
module RICPU(
input clk,
input clk_ram,
input rst,
output [31:0] A, B,
output [31:0] ALU_F,
output [6:0] MW,
output reg FR_ZF, FR_OF,
output [31:0] Mem_R_Data
);
reg Write_Reg;
reg Mem_Write;
reg [2:0] ALU_OP;
wire [31:0] Inst_code;
wire [5:0] op_code; // Inst_code
wire [4:0] rs_addr;
wire [4:0] rt_addr;
wire [4:0] rd_addr;
// wire [4:0] shamt;
wire [5:0] func;
wire [15:0] imm;
wire [31:0] imm_Data;
wire OF, ZF;
wire [31:0] ALU_A, ALU_B;
wire [31:0] Reg_Data_B;
wire [4:0] Reg_W_Addr;
wire [31:0] Reg_W_Data;
wire [6:0] Mem_Addr;
//I
reg [0:0] rd_rt_s;
reg [0:0] imm_s;
reg [0:0] rt_imm_s;
reg [0:0] alu_mem_s;
assign op_code = Inst_code[31:26];
assign rs_addr = Inst_code[25:21];
assign rt_addr = Inst_code[20:16];
assign rd_addr = Inst_code[15:11];
// assign shamt = [10:6];
assign func = Inst_code[5:0];
assign imm = Inst_code[15:0];
assign Mem_Addr = {1'b0,ALU_F[5:0]};
assign Reg_W_Addr = (rd_rt_s) ? rt_addr : rd_addr;
assign imm_Data = (imm_s) ? {{16{imm[15]}},imm}: {{16{1'b0}},imm};
assign ALU_B = (rt_imm_s) ? imm_Data : Reg_Data_B;
assign Reg_W_Data = (alu_mem_s) ? Mem_R_Data : ALU_F;
assign MW = Mem_Addr;
assign A = ALU_A;
assign B = ALU_B;
ALU theALU (
.A(ALU_A),
.B(ALU_B),
.ZF(ZF),
.OF(OF),
.F(ALU_F),
.ALU_OP(ALU_OP)
);
IF_M IFM (
.clka(clk),
.rst(rst),
.Inst_code(Inst_code)
);
register REGS(
.clk(~clk),
.Reset(rst),
.R_Addr_A(rs_addr),
.R_Addr_B(rt_addr),
.W_Addr(Reg_W_Addr),
.W_Data(Reg_W_Data),
.Write_Reg(Write_Reg),
.R_Data_A(ALU_A),
.R_Data_B(Reg_Data_B)
);
RAM theRAM (
.clka(clk_ram), // input clka
.wea(Mem_Write), // input [0 : 0] wea
.addra(Mem_Addr), // input [6 : 0] addra
.dina(Reg_Data_B), // input [31 : 0] dina
.douta(Mem_R_Data) // output [31 : 0] douta
);
always @(*)
begin
ALU_OP = 3'b000;
Write_Reg = 1'b0;
Mem_Write = 1'b0;
rd_rt_s = 1'b0;
rt_imm_s = 1'b0;
alu_mem_s = 1'b0;
if(op_code==6'b000000)
begin
Write_Reg = 1'b1;
case (func)
6'b100000: ALU_OP = 3'b100;
6'b100010: ALU_OP = 3'b101;
6'b100100: ALU_OP = 3'b000;
6'b100101: ALU_OP = 3'b001;
6'b100110: ALU_OP = 3'b010;
6'b100111: ALU_OP = 3'b011;
6'b101011: ALU_OP = 3'b110;
6'b000100: ALU_OP = 3'b111;
default: ALU_OP = 3'b000;
endcase
end
else
begin
Write_Reg = 1'b1;
rd_rt_s = 1'b1;
rt_imm_s = 1'b1;
imm_s = 1'b0;
case (op_code)
6'b001000://addi rt, rs, imm
begin
imm_s = 1'b1;
ALU_OP = 3'b100;
end
6'b001100://andi rt, rs, imm
begin
ALU_OP = 3'b000;
end
6'b001110://xori rt, rs, imm
begin
ALU_OP = 3'b010;
end
6'b001011://sltiu rt, rs, imm
begin
ALU_OP = 3'b110;
end
6'b100011:// lw rt, offset(rs)
begin
imm_s = 1'b1;
alu_mem_s = 1'b1;
ALU_OP = 3'b100;
end
6'b101011:// sw rt, offset(rs)
begin
imm_s = 1'b1;
Write_Reg = 1'b0;
ALU_OP = 3'b100;
Mem_Write = 1'b1;
rd_rt_s = 1'bz;
alu_mem_s = 1'bz;
end
default: ALU_OP = 3'b000;
endcase
end
end
always @(negedge clk)
begin
FR_ZF <= ZF;
FR_OF <= OF;
end
endmodule
//EXPR 7
module IF_M(
input [0:0] clka,
input [0:0] rst,
output [31:0] Inst_code
);
wire [31:0] douta;
wire [5:0] addra;
reg [31:0] PC;
wire [31:0] PC_new;
IROM Inst_addr (
.clka(clka), // input clka
.addra(addra), // input [5 : 0] addra
.douta(douta) // output [31 : 0] douta
);
assign PC_new = PC + 4;
assign Inst_code = douta;
assign addra = PC[7:2];
always@(posedge clka or posedge rst)
begin
if(rst)
begin
PC[31:0]<=32'd0;
end
else
begin
PC<=PC_new;
end
end
endmodule
module register(clk, Reset, R_Addr_A, R_Addr_B, W_Addr, W_Data, Write_Reg, R_Data_A, R_Data_B
);
input clk;
input Reset;
input Write_Reg;
input [4:0] R_Addr_A, R_Addr_B, W_Addr;
input [31:0] W_Data;
output [31:0] R_Data_A;
output [31:0] R_Data_B;
reg [31:0] REGISTERS[0:31];
integer i;
assign R_Data_A = (R_Addr_A==5'b00000)? 32'h0000_0000 : REGISTERS[R_Addr_A];
assign R_Data_B = (R_Addr_B==5'b00000)? 32'h0000_0000 : REGISTERS[R_Addr_B];
always @(posedge clk or posedge Reset)
begin
if(Reset)
begin
for(i=0; i<=31; i=i+1)
begin
REGISTERS[i]<=32'h0000_0000;
end
end
else
begin
if(Write_Reg && (W_Addr != 5'b00000))
begin
REGISTERS[W_Addr]<=W_Data;
end
else
begin
REGISTERS[W_Addr]<=REGISTERS[W_Addr];
end
end
end
endmodule
module ALU(A, B, ZF, OF, F, ALU_OP);
input [2:0] ALU_OP;
input [31:0] A, B;
output reg [31:0] F;
output reg ZF, OF;
reg C32;
always @(*)
begin
case(ALU_OP)
3'd0:begin //and
F = A&B;
OF = 0;
end
3'd1:begin //or
F = A|B;
OF = 0;
end
3'd2:begin //xor
F = A^B;
OF = 0;
end
3'd3:begin //nor
F = ~(A|B);
OF = 0;
end
3'd4:begin //add
{C32, F} = A + B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd5:begin //sub
{C32, F} = A - B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd6:begin //slt
if (A<B)
begin
F = 32'd1;
end
else
begin
F = 32'd0;
end
OF = 0;
end
3'd7:begin //sll
F=B<<A;
OF=0;
end
default:begin
F=A;
OF = 0;
end
endcase
if (F == 32'd0)
begin
ZF = 1;
end
else
begin
ZF = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void dfs(const vector<vector<int> >& edge_list, vector<bool>& visited, int i, int& edges) { visited[i] = true; for (int j : edge_list[i]) { if (!visited[j]) dfs(edge_list, visited, j, edges); if (j >= i) ++edges; } } int main() { int n, m, u, v; scanf( %d %d , &n, &m); vector<int> deg_noloop(n, 0); vector<vector<int> > edge_list(n); vector<bool> visited(n, false); long long nonloops = 0, loops = 0, good_paths = 0; int start = 0, edges = 0; for (int i = 0; i < m; i++) { scanf( %d %d , &u, &v); --u; --v; start = u; if (u != v) { edge_list[u].push_back(v); edge_list[v].push_back(u); ++deg_noloop[u]; ++deg_noloop[v]; ++nonloops; } else { edge_list[u].push_back(v); ++loops; } } dfs(edge_list, visited, start, edges); for (int i = 0; i < n; i++) { long long deg = deg_noloop[i]; if (deg >= 2) good_paths += (deg) * (deg - 1) / 2; } good_paths += loops * nonloops + (loops) * (loops - 1) / 2; if (edges < m) good_paths = 0; printf( %lld n , good_paths); }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> pts[1001]; int n; int main() { cin >> n; for (int i = 0; i <= n; i++) { scanf( %d%d , &pts[i].first, &pts[i].second); } int ans = 0; char last = U ; for (int i = 1; i < n; i++) { char cur; if (pts[i].first == pts[i + 1].first) { if (pts[i].second > pts[i + 1].second) { cur = D ; } else { cur = U ; } } else if (pts[i].second == pts[i + 1].second) { if (pts[i].first > pts[i + 1].first) { cur = L ; } else { cur = R ; } } if (last == R && cur == U ) ++ans; else if (last == U && cur == L ) ++ans; else if (last == L && cur == D ) ++ans; else if (last == D && cur == R ) ++ans; last = cur; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200000]; int b[200000]; int c[200001]; int t[200001]; vector<int> x; vector<int> ans; int add(int r, int cr, int d) { if (c[r] == t[r]) cr--; t[r] += d; if (c[r] == t[r]) cr++; return cr; } int main() { int n, m, p, i, j; scanf( %d %d %d , &n, &m, &p); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < m; i++) { scanf( %d , &b[i]); x.push_back(b[i]); } x.push_back(1000000001); sort(x.begin(), x.end()); x.erase(unique(x.begin(), x.end()), x.end()); int k = x.size(); for (i = 0; i < n; i++) { int pos = lower_bound(x.begin(), x.end(), a[i]) - x.begin(); if (a[i] == x[pos]) a[i] = pos; else a[i] = k - 1; } for (i = 0; i < k; i++) { c[i] = 0; t[i] = 0; } for (i = 0; i < m; i++) { int pos = lower_bound(x.begin(), x.end(), b[i]) - x.begin(); c[pos]++; } int cr = 1; long long d = (long long)p * (m - 1); for (i = 0; i < p; i++) { if (i + d >= n) continue; for (j = 0; j < m; j++) cr = add(a[i + p * j], cr, 1); if (cr == k) ans.push_back(i); j = i + p * m; while (j < n) { cr = add(a[j], cr, 1); cr = add(a[j - p * m], cr, -1); if (cr == k) ans.push_back(j - p * (m - 1)); j += p; } int l = j - p; for (j = 0; j < m; j++) cr = add(a[l - p * j], cr, -1); } sort(ans.begin(), ans.end()); printf( %d n , ans.size()); for (i = 0; i < ans.size(); i++) printf( %d , ans[i] + 1); puts( ); return 0; }
|
`include "constants.v"
module fp16_smult (
input wire [31: 0] a,
input wire [31: 0] b,
output reg [31: 0] prod
);
function [31: 0] fp16_mult;
input [31: 0] a;
input [31: 0] b;
reg [31: 0] prod;
reg [31: 0] product_hi;
reg [31: 0] product_lo;
reg [31: 0] A;
reg [31: 0] B;
reg [31: 0] C;
reg [31: 0] D;
reg [31: 0] AC;
reg [31: 0] BD;
reg [31: 0] AD_CB;
reg [31: 0] ad_cb_temp;
begin
A = (a >> 16);
B = a & 'hFFFF;
C = (b >> 16);
D = b & 'hFFFF;
AC = A * C;
BD = B * D;
AD_CB = A * D + C * B;
ad_cb_temp = AD_CB << 16;
product_hi = AC + (AD_CB);
product_lo = BD + ad_cb_temp;
if (product_lo < BD) begin
product_lo = product_lo + 1;
end
prod = (product_hi << 16) | (product_lo >> 16);//{product_hi[15: 0], product_lo[15: 0]};
if (product_hi >> 31 != product_lo >> 15) begin
prod = `FP16_OVERFLOW;
end
fp16_mult = prod;
end
endfunction
always @(*) begin
prod = fp16_mult(a, b);
if (prod == `FP16_OVERFLOW) begin
prod = ((a >= 0) == (b >= 0)) ? `FP16_MAXIMUM : `FP16_MINIMUM;
end
end
endmodule
|
// Verilog netlist generated by Workcraft 3
module VME (d, lds, dtack, dsr, dsw, ldtack);
input dsr, dsw, ldtack;
output d, lds, dtack;
wire U1_ON, IN_BUBBLE3_ON, IN_BUBBLE5_ON, U7_ON, IN_BUBBLE10_ON, OUT_BUBBLE1_ON, U14_ON, IN_BUBBLE16_ON, IN_BUBBLE18_ON, U20_ON, IN_BUBBLE23_ON, IN_BUBBLE25_ON, IN_BUBBLE28_ON, OUT_BUBBLE2_ON, U31_ON, IN_BUBBLE33_ON, OUT_BUBBLE3_ON, U36_ON;
IND3D1 U1 (.ZN(U1_ON), .A1(OUT_BUBBLE3_ON), .B1(ldtack), .B2(dsr));
// This inverter should have a short delay
INVD1 IN_BUBBLE3 (.ZN(IN_BUBBLE3_ON), .I(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE5 (.ZN(IN_BUBBLE5_ON), .I(ldtack));
OAI221D1 U7 (.ZN(U7_ON), .A1(IN_BUBBLE3_ON), .A2(d), .B1(IN_BUBBLE5_ON), .B2(OUT_BUBBLE3_ON), .C(dsw));
ND2D1 U8 (.ZN(d), .A1(U7_ON), .A2(U1_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE10 (.ZN(IN_BUBBLE10_ON), .I(OUT_BUBBLE3_ON));
INVD1 OUT_BUBBLE1 (.ZN(OUT_BUBBLE1_ON), .I(U14_ON));
OAI221D1 U14 (.ZN(U14_ON), .A1(d), .A2(dsr), .B1(dsr), .B2(OUT_BUBBLE2_ON), .C(IN_BUBBLE10_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE16 (.ZN(IN_BUBBLE16_ON), .I(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE18 (.ZN(IN_BUBBLE18_ON), .I(dsw));
OAI31D1 U20 (.ZN(U20_ON), .A1(IN_BUBBLE18_ON), .A2(IN_BUBBLE16_ON), .A3(d), .B(OUT_BUBBLE3_ON));
C2 U21 (.Q(lds), .A(U20_ON), .B(OUT_BUBBLE1_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE23 (.ZN(IN_BUBBLE23_ON), .I(OUT_BUBBLE3_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE25 (.ZN(IN_BUBBLE25_ON), .I(OUT_BUBBLE2_ON));
AOI221D1 U26 (.ZN(dtack), .A1(IN_BUBBLE23_ON), .A2(dsw), .B1(d), .B2(OUT_BUBBLE3_ON), .C(IN_BUBBLE25_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE28 (.ZN(IN_BUBBLE28_ON), .I(OUT_BUBBLE3_ON));
INVD1 OUT_BUBBLE2 (.ZN(OUT_BUBBLE2_ON), .I(U31_ON));
OAI222D1 U31 (.ZN(U31_ON), .A1(IN_BUBBLE28_ON), .A2(dsw), .B1(OUT_BUBBLE2_ON), .B2(d), .C1(d), .C2(lds));
// This inverter should have a short delay
INVD1 IN_BUBBLE33 (.ZN(IN_BUBBLE33_ON), .I(d));
INVD1 OUT_BUBBLE3 (.ZN(OUT_BUBBLE3_ON), .I(U36_ON));
AOI32D1 U36 (.ZN(U36_ON), .A1(IN_BUBBLE33_ON), .A2(ldtack), .A3(OUT_BUBBLE2_ON), .B1(ldtack), .B2(OUT_BUBBLE3_ON));
// signal values at the initial state:
// IN_BUBBLE10_ON IN_BUBBLE16_ON IN_BUBBLE18_ON IN_BUBBLE23_ON IN_BUBBLE25_ON IN_BUBBLE28_ON IN_BUBBLE33_ON IN_BUBBLE3_ON IN_BUBBLE5_ON !OUT_BUBBLE1_ON !OUT_BUBBLE2_ON !OUT_BUBBLE3_ON U14_ON U1_ON U20_ON U31_ON U36_ON U7_ON !d !dsr !dsw !dtack !lds !ldtack
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000004; int a[N]; int spf[N], prime[N]; int cntp[N]; void sieve() { int i, j; for (i = 2; i < N; i++) { if (!prime[i]) { for (j = 1; 1LL * i * j < N; j++) { prime[i * j] = 1; if (!spf[i * j]) spf[i * j] = i; } } } } int main() { int n, k; scanf( %d %d , &n, &k); int i; sieve(); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) { int val = a[i]; while (val > 1) { int sf = spf[val], cnt = 0; while (val % sf == 0) { val = val / sf; cnt++; } cntp[sf] = max(cntp[sf], cnt); } } while (k > 1) { int sf = spf[k], cnt = 0; while (k % sf == 0) { k = k / sf; cnt++; } if (cnt > cntp[sf]) { printf( No n ); return 0; } } printf( Yes n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_PP_SYMBOL_V
|
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