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#include <bits/stdc++.h> using namespace std; using namespace std::chrono; void solve() { int n; cin >> n; int a, b, c; cin >> a >> b >> c; string s; cin >> s; int ap = 0, bp = 0, cp = 0; for (auto i : s) { if (i == R ) ap++; else if (i == P ) bp++; else cp++; } int wins = min(b, ap) + min(c, bp) + min(a, cp); if (wins >= ceil(((long double)1.0 * n / 2))) { cout << YES n ; string ans(n, A ); for (int i = 0; i < n; ++i) { if (s[i] == R ) { if (b > 0) { ans[i] = P ; b--; } else ans[i] = X ; } else if (s[i] == P ) { if (c > 0) { ans[i] = S ; c--; } else ans[i] = X ; } else { if (a > 0) { ans[i] = R ; a--; } else ans[i] = X ; } } for (int i = 0; i < n; ++i) { if (ans[i] == X ) { if (a > 0) { ans[i] = R ; a--; } else if (b > 0) { ans[i] = P ; b--; } else { ans[i] = S ; } } } cout << ans << n ; } else cout << NO n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; for (int i = 1; i <= t; ++i) { solve(); } }
|
/*
* DSI Core
* Copyright (C) 2013-2014 twl <>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
`include "dsi_defs.vh"
`timescale 1ns/1ps
/*
* dsi_packet_assembler.v
*
* Puts together DSI packets and produces a packed data stream for the PHY.
*/
module dsi_packet_assembler
(
clk_i,
rst_n_i,
p_req_i,
p_islong_i,
p_type_i,
p_wcount_i,
p_command_i,
p_payload_i,
p_dreq_o,
p_dlast_o,
p_last_i,
phy_d_o,
phy_dvalid_o,
phy_hs_request_o,
phy_hs_dreq_i,
num_lanes_i
);
parameter g_pixels_per_clock = 1;
parameter g_num_lanes = 3;
input clk_i;
input rst_n_i;
input p_req_i;
input p_islong_i;
input [5:0] p_type_i;
input [15:0] p_wcount_i;
input [15:0] p_command_i;
input [g_pixels_per_clock * 24-1:0] p_payload_i;
input p_last_i;
output p_dreq_o;
output p_dlast_o;
output [g_num_lanes*8-1:0] phy_d_o;
output [g_num_lanes-1:0] phy_dvalid_o;
output phy_hs_request_o;
input phy_hs_dreq_i;
input [2:0] num_lanes_i;
`define ST_LP_MODE 3
`define ST_IDLE 0
`define ST_PAYLOAD 1
`define ST_CRC 2
reg [3:0] state;
reg [15:0] tx_count;
wire [15:0] tx_count_next;
reg [47:0] pack_data;
wire pack_req;
reg pack_req_d0;
reg [3:0] pack_size;
reg pack_valid;
wire pack_empty;
reg pack_flush;
wire [g_num_lanes-1:0] pack_qvalid;
dsi_packer
#(
.g_input_bytes(3*g_pixels_per_clock),
.g_output_bytes(g_num_lanes)
)
U_Packer
(
.clk_i(clk_i),
.rst_n_i(rst_n_i),
.d_i(pack_data),
.d_size_i(pack_size),
.d_req_o(pack_req),
.d_valid_i(pack_valid),
.d_empty_o(pack_empty),
.q_o(phy_d_o),
.q_req_i(phy_hs_dreq_i),
.q_valid_o(pack_qvalid),
.q_flush_i(pack_flush),
.q_size_i(num_lanes_i)
);
reg crc_reset,crc_valid;
wire [15:0] crc_value;
reg [2:0] crc_nbytes = g_pixels_per_clock * 3;
dsi_crc
#(
.g_max_data_bytes(g_pixels_per_clock * 3)
)
U_CRC
(
.clk_i(clk_i),
.rst_i(crc_reset),
.valid_i(crc_valid),
.nbytes_i(crc_nbytes),
.d_i(p_payload_i),
.crc_o(crc_value)
);
reg [23:0] pack_header;
wire [23:0] pack_header_swapped;
wire [7:0] ecc_value;
always @*
if(p_islong_i)
pack_header <= { 2'b00, p_type_i, p_wcount_i[7:0], p_wcount_i[15:8] };
else
pack_header <= { 2'b00, p_type_i, p_command_i[7:0], p_command_i[15:8] };
assign pack_header_swapped [7:0] = pack_header[23:16];
assign pack_header_swapped [15:8] = pack_header[15:8];
assign pack_header_swapped [23:16] = pack_header[7:0];
dsi_parity U_ECC
(
.d_i(pack_header_swapped),
.p_o(ecc_value)
);
always @*
begin
crc_valid <= (state == `ST_PAYLOAD ? pack_req_d0 : 0);
crc_reset <= (state == `ST_IDLE ? 1: 0 );
end
assign p_idle_o = (state == `ST_IDLE || state == `ST_LP_MODE);
always@(posedge clk_i)
pack_req_d0 <= pack_req;
always@(posedge clk_i)
if(!rst_n_i) begin
state <= `ST_LP_MODE;
end else begin
case (state)
`ST_LP_MODE:
if(p_req_i && pack_req_d0 && phy_hs_dreq_i) begin
state <= `ST_IDLE;
end
`ST_IDLE: begin
if(pack_req_d0) begin
tx_count <= p_wcount_i;
if(p_islong_i)
state <= `ST_PAYLOAD;
else begin
if(p_last_i)
state <= `ST_LP_MODE;
else
state <= `ST_IDLE;
end
end else if(!p_req_i)
state <= `ST_LP_MODE;
end // case: `ST_IDLE
`ST_PAYLOAD:
if(pack_valid)
begin
tx_count <= tx_count - g_pixels_per_clock * 3;
if(tx_count == g_pixels_per_clock * 3)
state <= `ST_CRC;
else if(!p_req_i)
state <= `ST_LP_MODE;
end
`ST_CRC:
if(pack_req_d0) begin
state <= `ST_IDLE;
end
endcase // case (state)
end // else: !if(!rst_n_i)
always@*
begin
case (state)
`ST_LP_MODE: begin
pack_data <= ({g_num_lanes{`DSI_SYNC_SEQ}});
pack_size <= num_lanes_i;
pack_valid <= pack_req_d0 && p_req_i && phy_hs_dreq_i;
pack_flush <= ~p_req_i;
end
`ST_IDLE: begin
pack_data <= ({pack_header, ecc_value});
pack_size <= 4;
pack_valid <= pack_req_d0;
pack_flush <= 0;
end
`ST_PAYLOAD: begin
pack_data <= p_payload_i;
pack_size <= g_pixels_per_clock * 3;
pack_valid <= pack_req_d0;
pack_flush <= 0;
end
`ST_CRC: begin
pack_data <= {crc_value[7:0], crc_value[15:8]};
pack_size <= 2;
pack_valid <= pack_req_d0;
pack_flush <= ~p_req_i;
end
default: begin
pack_flush <= 0;
pack_data <= 0;
pack_size <= num_lanes_i;
pack_valid <= 0;
end
endcase // case (state)
end
assign phy_hs_request_o = p_req_i || (state != `ST_LP_MODE) || !pack_empty;
assign phy_dvalid_o = pack_qvalid;
reg p_dreq;
assign p_dreq_o = p_dreq;
always @*
case(state)
`ST_PAYLOAD:
if (tx_count == 3 * g_pixels_per_clock && pack_valid)
p_dreq <= 0;
else
p_dreq <= pack_req & p_req_i & phy_hs_dreq_i;
`ST_CRC:
p_dreq <= pack_req & p_req_i & phy_hs_dreq_i & pack_valid;
default: p_dreq <= pack_req & p_req_i & phy_hs_dreq_i;
endcase
endmodule // dsi_packet_assembler
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int dist[501][501]; int INF = 1000000000; int s[501][501]; int c[501][501]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { dist[i][j] = INF; c[i][j] = INF; } memset(s, 0, sizeof(s)); for (int i = 1; i <= n; i++) { dist[i][i] = 0; } for (int i = 1; i <= m; i++) { int x, y, l; cin >> x >> y >> l; dist[x][y] = l; dist[y][x] = l; c[x][y] = l; c[y][x] = l; } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { if (dist[i][k] + dist[k][j] < dist[i][j]) { dist[i][j] = dist[i][k] + dist[k][j]; } } memset(s, 0, sizeof(s)); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) for (int k = 1; k <= n; k++) if (c[k][j] && dist[i][k] + c[k][j] == dist[i][j]) s[i][j]++; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { int ans = 0; for (int k = 1; k <= n; k++) if (dist[i][k] < INF && dist[k][j] < INF) if (dist[i][k] + dist[k][j] == dist[i][j]) ans += s[i][k]; cout << ans << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long x, y, z, t1, t2, t3; int main() { scanf( %lld%lld%lld%lld%lld%lld , &x, &y, &z, &t1, &t2, &t3); puts(abs(x - y) * t1 >= abs(x - y) * t2 + abs(x - z) * t2 + 3 * t3 ? YES : NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; int n, k, maxn = 2000000001; int b[100001]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 0; i < k; i++) { int r = (n - (k - i) * (k - i - 1) / 2) / (k - i); if (r <= 0) { cout << NO ; return 0; } if (r > maxn) { b[i] = maxn; n -= maxn; maxn = maxn * 2; } else { b[i] = r; n -= r; maxn = r * 2; } if (i == k - 1 && n != 0) { cout << NO ; return 0; } } cout << YES << endl; for (int i = 0; i < k; i++) cout << b[i] << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_BLACKBOX_V
`define SKY130_FD_SC_HS__OR3_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; while (cin >> n) { vector<int> v; int x; for (int i = 0; i < n; i++) { cin >> x; v.push_back(x); } bool in = false; int cnt = 0; bool f = true; bool s = false, l = false; int ind1 = 1, ind2 = 1; for (int i = 1; i < n; i++) { bool d = false; while (v[i - 1] > v[i] && i < n) { d = true; if (f) { ind1 = i; ind2 = i + 1; f = false; } else { ind2 = i + 1; } if (i - 1 == 0) s = true; if (i == n - 1) l = true; i++; } if (d) { d = false; cnt++; } } bool val = false; if (cnt == 0) val = 1; else if (cnt == 1) { if (s && l) val = true; else if (s && v[ind1 - 1] < v[ind2]) val = true; else if (l && v[ind2 - 1] > v[ind1 - 2]) val = true; else if (v[ind1 - 1] < v[ind2] && v[ind2 - 1] > v[ind1 - 2]) val = true; } if (val) { cout << yes << endl; cout << ind1 << << ind2 << endl; } else { cout << no << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int N = 1510; int DP[27][N][N]; int ans[27][N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; string s; cin >> s; memset(DP, 0, sizeof(DP)); memset(ans, 0, sizeof(ans)); DP[s[0] - a ][0][0] = 1; for (int i = (int)1; i < (int)N; i++) DP[s[0] - a ][0][i] = 1; for (char ch = a ; ch <= z ; ch++) { if (s[0] == ch) continue; for (int i = (int)1; i < (int)N; i++) DP[ch - a ][0][i] = 1; } for (int i = (int)1; i < (int)(int)(s.size()); i++) { for (char ch = a ; ch <= z ; ch++) { if (s[i] == ch) { int len = 0; for (int k = i; k >= 0; k--) { if (s[k] != ch) break; len++; } DP[ch - a ][i][0] = len; } for (int j = (int)1; j < (int)N; j++) { if (ch == s[i]) DP[ch - a ][i][j] = 1 + DP[ch - a ][i - 1][j]; else DP[ch - a ][i][j] = 1 + DP[ch - a ][i - 1][j - 1]; } } } for (char ch = a ; ch <= z ; ch++) { for (int j = 0; j < N; j++) { for (int i = (int)0; i < (int)(int)(s.size()); i++) ans[ch - a ][j] = max(ans[ch - a ][j], DP[ch - a ][i][j]); } } int q; cin >> q; for (int i = (int)0; i < (int)q; i++) { int m; char ch; cin >> m >> ch; cout << ans[ch - a ][m] << endl; } return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 5,
parameter dat_width = 8
)
(
input clk, reset,
input rd1, wr1,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
reg wr, rd;
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
reg [31:0] count;
initial wr<=0;
initial rd<=0;
initial count<=0;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk) begin
wr=0;
if (wr1==1)
begin
if (count==0)
begin
wr <=~wr;
count <= 2;
end
else
begin
count <=count-1;
end
end
else
begin
wr=0;
end
end
always @(negedge clk) begin
wr=0;
if (wr1==1)
begin
if (count==0)
begin
wr <=~wr;
count <= 1;
end
else
begin
count <=count-1;
end
end
else
begin
wr=0;
end
end
always @(posedge clk) begin
if (rd1)
begin
if (count==0)
begin
rd <=~rd;
count <= 1;
end
else
begin
count <=count-1;
end
end
else
begin
rd=0;
end
end
always @(posedge clk) begin
if (rd1)
begin
if (count==0)
begin
rd <=~rd;
count <= 2;
end
else
begin
count <=count-1;
end
end
else
begin
rd=0;
end
end
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge reset, posedge wr, posedge rd)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
// Simple verilog simulation of an openFIRE core
// instantiated without fsl nor interruptions
`timescale 1ns/1ns
module Test_openFIRE;
reg clock, reset;
wire [31:0] dmem_addr;
reg [31:0] dmem_data_in;
wire [31:0] dmem_data_out;
wire dmem_we;
wire dmem_re;
wire [1:0] dmem_input_sel;
reg dmem_done;
wire [31:0] imem_addr;
reg [31:0] imem_data_in;
wire imem_re;
reg imem_done;
reg [31:0] memory [0:4095];
initial $readmemh("memory.txt", memory);
reg [800:0] memory_comments [0:100];
initial $readmemh("memory_comments.txt", memory_comments);
reg [800:0] imem_data_in_comments;
// Instantie openFIRE
openfire_cpu openfire_cpu(
clock, reset,
dmem_addr, dmem_data_in, dmem_data_out,
dmem_we, dmem_re, dmem_input_sel, dmem_done,
imem_addr, imem_data_in, imem_re, imem_done
);
initial begin
clock = 1'b1;
reset = 1'b1;
dmem_done = 1'b0;
imem_done = 1'b0;
#15 reset = 1'b0;
end
always #5 clock = ~clock;
// Simulating a "perfect" memory
// The simulated memory is reading/writing the data in less than a clock tick
always @(posedge ~clock) begin
if(~reset) begin
if(imem_re) begin
imem_data_in <= memory[imem_addr>>2];
imem_data_in_comments <= memory_comments[imem_addr>>2];
imem_done <= 1;
end
else begin
imem_done <= 0;
end
if(dmem_re) begin
dmem_data_in <= memory[dmem_addr>>2];
dmem_done <= 1;
end
else if(dmem_we) begin
memory[dmem_addr>>2] <= dmem_data_out;
dmem_done <= 1;
end
else begin
dmem_done <= 0;
end
end
end
always @(posedge ~clock) begin
if(~reset) begin
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int input(long long int n, vector<long long int> &ve); long long int input(long long int n, vector<long long int> &ve) { long long int val; for (long long int i = 0; i < n; i++) { cin >> val; ve.push_back(val); } return 0; } int main(void) { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, a, m, b; vector<long long int> vis, v; vector<vector<long long int>> adj; cin >> n >> m; vis.resize(n + 2, 0); adj.resize(n + 2); for (long long int i = 0; i < m; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } for (long long int i = 1; i < n + 1; i++) { if (adj[i].size() != n - 1) { v.push_back(i); } else { vis[i] = 1; } } if (v.size() == 0) { cout << YES << endl; for (long long int i = 0; i < n; i++) { cout << b ; } cout << endl; } else { vis[v[0]] = 2; for (long long int i = 0; i < adj[v[0]].size(); i++) { if (vis[adj[v[0]][i]] == 0) { vis[adj[v[0]][i]] = 2; } } long long int in = -1; for (long long int i = 0; i < v.size(); i++) { if (vis[v[i]] == 0) { vis[v[i]] = 3; in = i; break; } } long long int flag = 0; if (in != -1) { for (long long int i = 0; i < adj[v[in]].size(); i++) { if (vis[adj[v[in]][i]] == 0) { vis[adj[v[in]][i]] = 3; } else if (vis[adj[v[in]][i]] == 2) { flag = 1; break; } } } if (flag == 1) { cout << NO << endl; return 0; } for (long long int i = 0; i < v.size(); i++) { long long int x = vis[v[i]]; if (x == 0) { flag = 1; break; } } long long int two = 0, three = 0; for (long long int i = 1; i < n + 1; i++) { if (vis[i] == 2) { two++; } else if (vis[i] == 3) { three++; } else { two++; three++; } } for (long long int i = 0; i < v.size(); i++) { long long int x = vis[v[i]]; if (x != 1) { if (x == 2) { if (adj[v[i]].size() != two - 1) { flag = 1; break; } } else { if (adj[v[i]].size() != three - 1) { flag = 1; break; } } for (long long int j = 0; j < adj[v[i]].size(); j++) { if (vis[adj[v[i]][j]] != x && vis[adj[v[i]][j]] != 1) { flag = 1; break; } } } if (flag == 1) { break; } } if (flag == 1) { cout << NO << endl; } else { cout << YES << endl; for (long long int i = 1; i < n + 1; i++) { if (vis[i] == 1) { cout << b ; } else if (vis[i] == 2) { cout << a ; } else { cout << c ; } } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int L, v, l, r, d; cin >> L >> v >> l >> r; if (r == l && r % v == 0) d = 1; else d = r / v - (l - 1) / v; cout << L / v - d << n ; } return 0; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ulight_fifo_clock_sel (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 2: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 2: 0] data_out;
wire [ 2: 0] out_port;
wire [ 2: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {3 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[2 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[2010]; long long C[2010][2010]; long long A[2010]; bool use[2010]; int n, m, N; void init() { memset(use, 0, sizeof(use)); C[0][0] = 1; for (int i = 1; i <= 2000; ++i) C[i][0] = 1; for (int i = 1; i <= 2000; ++i) for (int j = 1; j <= i; ++j) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % 1000000007; A[0] = 1; A[1] = 1; for (int i = 2; i <= 2000; ++i) A[i] = (A[i - 1] * i) % 1000000007; n = 0; } void solve() { long long Ans = 1; Ans = A[n]; for (int i = 1; i <= N; ++i) if (a[i] == -1 && !use[i]) m++; long long tmp = 0; for (int i = 1; i <= m; ++i) { if (i & 1) tmp = (tmp + (C[m][i] * A[n - i]) % 1000000007) % 1000000007; else tmp = (1000000007 + tmp - (C[m][i] * A[n - i]) % 1000000007) % 1000000007; } cout << (Ans + 1000000007 - tmp) % 1000000007; } int main() { scanf( %d , &N); init(); for (int i = 1; i <= N; ++i) { scanf( %d , &a[i]); if (a[i] != -1) use[a[i]] = 1; else n++; } solve(); return 0; }
|
// DEFINES
`define BITS0 9 // Bit width of the operands
`define BITS1 8 // Bit width of the operands
`define BITS2 18 // Bit width of the operands
`define BITS3 36 // Bit width of the operands
// sees if the softaware matches simple primitives
module bm_match2_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-1:0] f_in;
output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS2-1:0] out2;
output [`BITS0-1:0] out3;
output [`BITS2-1:0] out4;
output [`BITS2-1:0] out5;
reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
reg [`BITS2-1:0] out2;
wire [`BITS0-1:0] out3;
wire [`BITS2-1:0] out4;
wire [`BITS2-1:0] out5;
assign out3 = a_in + b_in;
assign out4 = a_in * b_in + c_in * d_in;
assign out5 = a_in * b_in + c_in * d_in + e_in * f_in + a_in * c_in;
always @(posedge clock)
begin
out0 <= a_in * b_in + c_in * d_in;
out1 <= c_in + d_in;
out2 <= a_in * b_in + c_in * d_in + e_in * f_in + a_in * c_in;
end
endmodule
|
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
// always be low.
assign pwr_hi = 1'b0;
assign pwr_lo = 1'b0;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1;
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
end
// Divide 13.56 MHz by 32 to produce the SSP_CLK
// The register is bigger to allow higher division factors of up to /128
reg [6:0] ssp_clk_divider;
always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
assign ssp_clk = ssp_clk_divider[4];
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
// this is arbitrary, because it's just a bitstream.
// One nasty issue, though: I can't make it work with both rx and tx at
// once. The phase wrt ssp_clk must be changed. TODO to find out why
// that is and make a better fix.
reg [2:0] ssp_frame_divider_to_arm;
always @(posedge ssp_clk)
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
reg [2:0] ssp_frame_divider_from_arm;
always @(negedge ssp_clk)
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
reg ssp_frame;
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
if(mod_type == 3'b000) // not modulating, so listening, to ARM
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
else
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
reg modulating_carrier;
always @(mod_type or ssp_clk or ssp_dout)
if(mod_type == 3'b000)
modulating_carrier <= 1'b0; // no modulation
else if(mod_type == 3'b001)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == 3'b010)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else
modulating_carrier <= 1'b0; // yet unused
// This one is all LF, so doesn't matter
assign pwr_oe2 = modulating_carrier;
// Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_oe1 = modulating_carrier;
assign pwr_oe4 = modulating_carrier;
// This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0;
assign dbg = after_hysteresis;
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace rel_ops; const int inf = ~0u >> 2; const long long INF = ~0ull >> 2; const double err = 1e-11; const double pi = acos(-1); inline long long read() { long long x; if (scanf( %lld , &x) == -1) exit(0); return x; } inline double readf() { double x; if (scanf( %lf , &x) == -1) exit(0); return x; } template <typename _> inline _ sqr(_ x) { return x * x; } ostream &operator<<(ostream &o, const pair<int, int> &x) { return o << ( << x.first << , << x.second << ) ; } mt19937 rnd(time(0)); const int N = 20010; const int mod = (0 ? 1000000007 : 998244353); long long T; string s; deque<char> a; set<char> Set; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> T; while (T--) { cin >> s; Set.clear(); a.clear(); long long i = 0, f = 1; for (auto c : s) { if (Set.empty()) { Set.insert(c); a.push_back(c); continue; } if (Set.count(c)) { if (i != 0 && a[i - 1] == c) { i--; continue; } if (i != (long long)a.size() - 1 && a[i + 1] == c) { i++; continue; } f = false; } else { if (i == 0) { a.push_front(c); Set.insert(c); continue; } if (i == (long long)a.size() - 1) { a.push_back(c); Set.insert(c); i++; continue; } f = false; } } if (f) { cout << YES << endl; for (long long i = ( a ), _ = ( z + 1); i < _; i++) if (!Set.count(i)) { a.push_back(i); } for (auto i : a) cout << char(i); cout << endl; } else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 2e5 + 5; vector<int> adj[Maxn]; int sz[Maxn]; int n; long long ret, ans; void dfs_init(int u, int f) { sz[u] = 1; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == f) continue; dfs_init(v, u); sz[u] += sz[v]; } ret += sz[u]; } void dfs(int u, int f, long long ret) { ans = max(ans, ret); for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == f) continue; dfs(v, u, ret + n - 2 * sz[v]); } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } ans = ret = 0; dfs_init(1, 0); dfs(1, 0, ret); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, size_t N> struct ma : array<T, N> { T &operator[](size_t n) { return (*static_cast<array<T, N> *>(this))[n]; } }; template <class T> string to_str(const T &a) { ostringstream os; os << a; return os.str(); } template <> string to_str<long double>(const long double &a) { ostringstream os; os.precision(10); os.setf(ios::fixed); os << a; return os.str(); } template <class T> T from_str(const string &s) { istringstream is; T val; is >> val; return val; } int cond = (long long)0; map<int, vector<int> > nei; int dat[(int)1e5 + 11]; void solve() { int n, m; scanf( %d%d , &n, &m); for (auto i = (0); i < (m); ++i) { scanf( %d , &dat[i]); } long long turn = 0; for (auto i = (0); i < (m - 1); ++i) { int a = dat[i], b = dat[i + 1]; turn += abs(a - b); if (a != b) { nei[a].push_back(b); nei[b].push_back(a); } } long long res = turn; for (auto &it : (nei)) { auto kol = it.second; sort((kol).begin(), (kol).end()); int mid = kol.size() / 2; long long cand1 = 0; long long cand2 = 0; for (auto &jt : (kol)) { cand1 += abs(it.first - jt); cand2 += abs(jt - kol[mid]); } res = min(res, turn + cand2 - cand1); } cout << res << endl; } void brute() {} void gen(int i, int n, int k) {} int main(int argc, char **argv) { ios::sync_with_stdio(false); vector<string> args; int nr_test = -1; int t = 1; for (auto i = (1); i <= (argc - 1); ++i) args.push_back(argv[i]); for (auto &it : (args)) if (it == q ) cond = 10000000; for (auto &it : (args)) if (it == all ) t = 1000; for (auto &it : (args)) if (atoi(it.c_str()) > 0) nr_test = atoi(it.c_str()); for (auto &it : (args)) if (it == b ) { brute(); return 0; } for (auto &it : (args)) if (it == g && args.size() >= 4) { gen(atoi(args[1].c_str()), atoi(args[2].c_str()), atoi(args[3].c_str())); return 0; } for (auto i = (1); i <= (t); ++i) { if (nr_test == -1 || i <= nr_test) solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void solve() { long long n, i, j; cin >> n; long long x[n]; for (i = 0; i < n; i++) { cin >> x[i]; } long long m; cin >> m; long long y[m]; for (i = 0; i < m; i++) { cin >> y[i]; } long long k; cin >> k; long long z[k]; for (i = 0; i < k; i++) { cin >> z[i]; } long long a, b; sort(x, x + n); sort(y, y + m); sort(z, z + k); cin >> a >> b; double r = double(x[n - 1] * sqrt((double(b * y[m - 1])) / double(a * z[0] + b * y[m - 1]))); cout << fixed << setprecision(18) << r << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(NULL); ; long long t = 1; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { double n, m; cin >> n >> m; printf( %.10lf n , n * pow(1.000000011, m)); return 0; }
|
//#############################################################################
//# Function: BCD Seven Segment Decoderh #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_7seg_decode ( input [3:0] bcd, //0-9
output a, //a segment (1=0ff)
output b, //b segment
output c, //c segment
output d, //d segment
output e, //e segment
output f, //f segment
output g //g segment
);
reg a,b,c,d,e,f,g;
always @ (*)
case(bcd[3:0])
4'h0 : {a,b,c,d,e,f,g} = 7'b0000001;
4'h1 : {a,b,c,d,e,f,g} = 7'b1001111;
4'h2 : {a,b,c,d,e,f,g} = 7'b0010010;
4'h3 : {a,b,c,d,e,f,g} = 7'b0000110;
4'h4 : {a,b,c,d,e,f,g} = 7'b1001100;
4'h5 : {a,b,c,d,e,f,g} = 7'b0100100;
4'h6 : {a,b,c,d,e,f,g} = 7'b0100000;
4'h7 : {a,b,c,d,e,f,g} = 7'b0001111;
4'h8 : {a,b,c,d,e,f,g} = 7'b0000000;
4'h9 : {a,b,c,d,e,f,g} = 7'b0001100;
default : {a,b,c,d,e,f,g} = 7'b1111111;
endcase // case (in[3:0])
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: YCbCr to RGB Color Doamin Converter.
// ( 10 Bits Resolution )
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Chen :| 05/09/05 :| Initial Revision
// --------------------------------------------------------------------
module YCbCr2RGB
(
// input data
iY,
iCb,
iCr,
// output data
Red,
Green,
Blue,
// controller
oDVAL,
iDVAL,
iRESET,
iCLK
);
// Input
input [7:0] iY,iCb,iCr;
input iDVAL,iRESET,iCLK;
// Output
output [9:0] Red,Green,Blue;
output reg oDVAL;
// Internal Registers/Wires
reg [9:0] oRed,oGreen,oBlue;
reg [3:0] oDVAL_d;
reg [19:0] X_OUT,Y_OUT,Z_OUT;
wire [26:0] X,Y,Z;
assign Red = oRed;
assign Green= oGreen;
assign Blue = oBlue;
always@(posedge iCLK)
begin
if(iRESET)
begin
oDVAL<=0;
oDVAL_d<=0;
oRed<=0;
oGreen<=0;
oBlue<=0;
end
else
begin
// Red
if(X_OUT[19])
oRed<=0;
else if(X_OUT[18:0]>1023)
oRed<=1023;
else
oRed<=X_OUT[9:0];
// Green
if(Y_OUT[19])
oGreen<=0;
else if(Y_OUT[18:0]>1023)
oGreen<=1023;
else
oGreen<=Y_OUT[9:0];
// Blue
if(Z_OUT[19])
oBlue<=0;
else if(Z_OUT[18:0]>1023)
oBlue<=1023;
else
oBlue<=Z_OUT[9:0];
// Control
{oDVAL,oDVAL_d}<={oDVAL_d,iDVAL};
end
end
always@(posedge iCLK)
begin
if(iRESET)
begin
X_OUT<=0;
Y_OUT<=0;
Z_OUT<=0;
end
else
begin
X_OUT<=( X - 114131 ) >>7;
Y_OUT<=( Y + 69370 ) >>7;
Z_OUT<=( Z - 141787 ) >>7;
end
end
// Y 596, 0, 817
MAC_3 u0( iY, iCb, iCr,
17'h00254, 17'h00000, 17'h00331,
X, iRESET, iCLK);
// Cb 596, -200, -416
MAC_3 u1( iY, iCb, iCr,
17'h00254, 17'h3FF38, 17'h3FE60,
Y, iRESET, iCLK);
// Cr 596, 1033, 0
MAC_3 u2( iY, iCb, iCr,
17'h00254, 17'h00409, 17'h00000,
Z, iRESET, iCLK);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool comp(int& a, int& b) { return b < a; } int main() { int n; cin >> n; vector<pair<int, int>> source(n), team1, team2; long long sum_team1 = 0, sum_team2 = 0; for (int i = 0; i < n; ++i) { cin >> source[i].first; source[i].second = i; } sort(source.begin(), source.end()); int i = 0, par = 1; while (!source.empty()) { if (par) { team1.push_back(source.back()); source.pop_back(); par = 0; sum_team1 += team1.back().first; } else { team2.push_back(source.back()); source.pop_back(); par = 1; sum_team2 += team2.back().first; } } cout << team1.size() << n ; for (int i = 0; i < team1.size(); ++i) cout << team1[i].second + 1 << ; cout << n ; cout << team2.size() << n ; for (int i = 0; i < team2.size(); ++i) cout << team2[i].second + 1 << ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (lin64) Build Mon Oct 10 19:07:26 MDT 2016
// Date : Thu May 4 16:19:46 2017
// Host : david-desktop-arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dave/openMixR/fpga/vivado/openmixr_base/openmixr_base.srcs/sources_1/ip/init_config_rom/init_config_rom_stub.v
// Design : init_config_rom
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tfbg484-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_4,Vivado 2016.3" *)
module init_config_rom(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[31:0]" */;
input clka;
input [9:0]addra;
output [31:0]douta;
endmodule
|
/*
* Copyright (c) 2000 Peter monta ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Reworked slightly to be self checking.
module main;
wire y;
reg a,b;
reg error;
assign y = a && (b ? 0 : 1);
initial
begin
error = 0;
#1 ; // get passed the time 0 race problems ;-)
b = 1;
a = 1;
#1 ;
if(y !== 0)
begin
$display("FAILED");
error = 1;
end
#1 ;
b = 0;
#1 ;
if(y !== 1)
begin
$display("FAILED");
error = 1;
end
if(error === 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; long long score, sum = 0; cin >> n; vector<int> ara(n); for (int i = 0; i < n; i++) { cin >> ara[i]; sum += ara[i]; } sort(ara.begin(), ara.end()); reverse(ara.begin(), ara.end()); score = sum; for (int i = n - 1; i >= 0; i--) { sum -= ara[i]; score += (ara[i] + sum); } score -= ara[0]; cout << score << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1 << 30; int n, m, str[100100], lim[100100], up[100100], D[100100], col[100100 * 4]; long long ans; vector<int> F[100100 * 4]; vector<long long> sum2[100100 * 4], sum[100100 * 4]; bool cmp(int x, int y) { return D[x] > D[y]; } void build(int node, int l, int r) { col[node] = -2; if (l == r) { F[node].push_back(l); sum[node].push_back(up[l]); sum2[node].push_back(lim[l]); return; } int mid = (l + r) >> 1, son = node << 1; build(son, l, mid); build(son | 1, mid + 1, r); F[node].resize(r - l + 1); sum[node].resize(r - l + 1); sum2[node].resize(r - l + 1); merge(F[son].begin(), F[son].end(), F[son | 1].begin(), F[son | 1].end(), F[node].begin(), cmp); sum[node][0] = up[F[node][0]], sum2[node][0] = lim[F[node][0]]; for (int i = 1, size = F[node].size(); i < size; i++) { sum[node][i] = sum[node][i - 1] + up[F[node][i]]; sum2[node][i] = sum2[node][i - 1] + lim[F[node][i]]; } } void update(int node) { if (col[node] > 0) col[node << 1] = col[(node << 1) | 1] = col[node]; } void getans(int node, int l, int r, int ll, int rr, int t) { if (l > rr || ll > r) return; if (ll <= l && rr >= r && (col[node] > 0 || col[node] == -2)) { if (col[node] > 0) { int dif = t - col[node]; int l = -1, r = F[node].size() - 1; while (l < r) { int mid = (l + r + 1) >> 1; if (D[F[node][mid]] >= dif) l = mid; else r = mid - 1; } if (l >= 0) ans += sum[node][l] * dif - sum2[node][l]; ans += sum2[node][F[node].size() - 1]; } else { for (int i = 0, size = F[node].size(); i < size; i++) ans += min((long long)lim[F[node][i]], (long long)t * up[F[node][i]] + str[F[node][i]]); } col[node] = t; return; } update(node); int mid = (l + r) >> 1, son = node << 1; getans(son, l, mid, ll, rr, t); getans(son | 1, mid + 1, r, ll, rr, t); if (col[son] == col[son | 1]) col[node] = col[son]; else col[node] = -1; } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d %d %d , &str[i], &lim[i], &up[i]), D[i] = up[i] == 0 ? Maxn : lim[i] / up[i]; build(1, 1, n); int t, l, r; cin >> m; for (int i = 1; i <= m; i++) { scanf( %d %d %d , &t, &l, &r); ans = 0; getans(1, 1, n, l, r, t); printf( %lld n , ans); } }
|
#include <bits/stdc++.h> using namespace std; char mat[6][40]; int t[6], n, v[6]; int solve() { if (t[v[4]] != t[v[1]] + t[v[3]] - 1) return 0; if (t[v[5]] != t[v[0]] + t[v[2]] - 1) return 0; if (mat[v[0]][0] != mat[v[1]][0]) return 0; if (mat[v[0]][t[v[0]] - 1] != mat[v[4]][0]) return 0; if (mat[v[1]][t[v[1]] - 1] != mat[v[5]][0]) return 0; if (mat[v[5]][t[v[5]] - 1] != mat[v[3]][0]) return 0; if (mat[v[3]][t[v[3]] - 1] != mat[v[2]][t[v[2]] - 1]) return 0; if (mat[v[4]][t[v[4]] - 1] != mat[v[2]][0]) return 0; if (mat[v[5]][t[v[0]] - 1] != mat[v[4]][t[v[1]] - 1]) return 0; return 1; } int main() { n = 6; vector<string> ans, aux; for (int i = 0; i < n; i++) { scanf( %s , mat[i]); t[i] = strlen(mat[i]); } for (int i = 0; i < n; i++) v[i] = i; do { int k = solve(); if (!k) continue; aux.resize(t[v[4]]); for (int i = 0; i < t[v[4]]; i++) { aux[i].resize(t[v[5]]); for (int j = 0; j < t[v[5]]; j++) aux[i][j] = . ; } for (int i = 0; i < t[v[0]]; i++) aux[0][i] = mat[v[0]][i]; for (int i = 0; i < t[v[1]]; i++) aux[i][0] = mat[v[1]][i]; for (int i = 0; i < t[v[2]]; i++) aux[aux.size() - 1][i + t[v[0]] - 1] = mat[v[2]][i]; for (int i = 0; i < t[v[3]]; i++) aux[t[v[1]] - 1 + i][t[v[5]] - 1] = mat[v[3]][i]; for (int i = 0; i < t[v[4]]; i++) aux[i][t[v[0]] - 1] = mat[v[4]][i]; for (int i = 0; i < t[v[5]]; i++) aux[t[v[1]] - 1][i] = mat[v[5]][i]; if (ans.size() == 0 || aux < ans) ans = aux; } while (next_permutation(v, v + n)); if (ans.size() == 0) printf( Impossible n ); else { for (int i = 0; i < ans.size(); i++) printf( %s n , ans[i].c_str()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n1, n2; int k1, k2; int main() { cin >> n1 >> n2 >> k1 >> k2; if (n1 > n2) cout << First << endl; else cout << Second << endl; return 0; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ddr_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out, // write data to OUT_FIFO
output afull // almost full signal to controller
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 :
DEPTH == 9 ? 4 : 'bx);
// Set watermark. Always give the MC 5 cycles to engage flow control.
localparam ALMOST_FULL_VALUE = DEPTH - 5;
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1] ;
(* keep = "true", max_fanout = 3 *) reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 3 *) reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS:0] entry_cnt;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
wire wr_en;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
rd_ptr <= 'b0;
rd_ptr_timing <= 'b0;
end
else if ((!my_empty[4]) & (!full_in)) begin
rd_ptr <= nxt_rd_ptr;
rd_ptr_timing <= nxt_rd_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 9'h1ff;
else begin
if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
my_empty[3:0] <= 4'b0000;
else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
end
if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
my_empty[8:4] <= 5'b00000;
else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
end
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
wr_ptr <= 'b0;
wr_ptr_timing <= 'b0;
end
else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
wr_ptr <= nxt_wr_ptr;
wr_ptr_timing <= nxt_wr_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_full <= 6'b000000;
else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
my_full <= 6'b000000;
else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
end
end
always @ (posedge clk)
begin
if (rst)
entry_cnt <= 'b0;
else if (wr_en_in & full_in & !my_full[4])
entry_cnt <= entry_cnt + 1'b1;
else if (!wr_en_in & !full_in & !my_empty[7])
entry_cnt <= entry_cnt - 1'b1;
end
assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<int> digits; vector<vector<bool>> dp; vector<int> bin_digits; bool can; void In() { cin >> n >> k; digits.resize(n); string next; for (int i = 0; i < n; i++) { cin >> next; digits[i] = stoi(next, 0, 2); } } int GetDistance(int from, int result) { int count = 0; for (int bit = 0; bit <= 6; bit++) { int num = 1 << bit; int first = from & num; int second = result & num; if (first != second) { if (first == 0) count++; else return -1; } } return count; } bool Solve() { bin_digits.push_back(stoi( 1110111 , 0, 2)); bin_digits.push_back(stoi( 0010010 , 0, 2)); bin_digits.push_back(stoi( 1011101 , 0, 2)); bin_digits.push_back(stoi( 1011011 , 0, 2)); bin_digits.push_back(stoi( 0111010 , 0, 2)); bin_digits.push_back(stoi( 1101011 , 0, 2)); bin_digits.push_back(stoi( 1101111 , 0, 2)); bin_digits.push_back(stoi( 1010010 , 0, 2)); bin_digits.push_back(stoi( 1111111 , 0, 2)); bin_digits.push_back(stoi( 1111011 , 0, 2)); dp.resize(n + 1, vector<bool>(k + 1, false)); dp[n][0] = true; for (int n_index = n - 1; n_index >= 0; n_index--) for (int i = 0; i <= k; i++) for (int j = 0; j <= 9; j++) { int next_distance = GetDistance(digits[n_index], bin_digits[j]); if (next_distance == -1) continue; if (i - next_distance < 0) continue; if (dp[n_index + 1][i - next_distance]) dp[n_index][i] = true; } if (!dp[0][k]) return false; return true; } void Out() { if (!can) { cout << -1 << endl; return; } for (int n_index = 0; n_index < n; n_index++) { int distance; int next_digit; for (int j = 0; j <= 9; j++) { int next_distance = GetDistance(digits[n_index], bin_digits[j]); if (next_distance == -1) continue; if (k - next_distance < 0) continue; if (dp[n_index + 1][k - next_distance]) { next_digit = j; distance = next_distance; } } k -= distance; cout << next_digit; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); In(); can = Solve(); Out(); }
|
#include <bits/stdc++.h> using namespace std; long long int MAX3(long long int x, long long int y, long long int z) { long long int t = max(x, y); return max(t, z); } long long int power(long long int x, long long int n) { long long int i, ans = 1; for (i = 1; i <= (n); i += 1) { ans = ans * x; } return ans; } void solve() { long long int n, i, sum = 0; vector<long long int> a; cin >> n; for (i = 0; i < (n); i += 1) { long long int x; cin >> x; a.push_back(x); if (i % 2 == 0) sum += x; } vector<long long int> a1, a2; long long int m1 = 0, m2 = 0; for (i = 0; i < (n - 1); i += 1) { long long int t = -a[i] + a[i + 1]; i++; a1.push_back(t); } for (i = 1; i < (n - 1); i += 1) { long long int t = -a[i + 1] + a[i]; i++; a2.push_back(t); } long long int s = a1.size(); long long int max_so_far = 0; long long int max_ending_here = 0; for (i = 0; i < (s); i += 1) { max_ending_here += a1[i]; max_so_far = max(max_so_far, max_ending_here); if (max_ending_here < 0) max_ending_here = 0; } m1 = max_so_far; max_so_far = 0; max_ending_here = 0; s = a2.size(); for (i = 0; i < (s); i += 1) { max_ending_here += a2[i]; max_so_far = max(max_so_far, max_ending_here); if (max_ending_here < 0) max_ending_here = 0; } m2 = max_so_far; long long int ans = max(m1, m2); cout << ans + sum << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { solve(); } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_1r1w_16x10.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
//Verilog code automatically generated by genregfile
module jbi_1r1w_16x10(
do,
rd_a,
wr_a,
di,
rd_clk,
wr_clk,
csn_wr
);
output [9:0] do;
input [3:0] rd_a;
input [3:0] wr_a;
input [9:0] di;
input rd_clk;
input wr_clk;
input csn_wr;
wire cs_wr;
reg [9:0] dout;
wire wrstrb_0000;
wire wrstrb_0001;
wire wrstrb_0010;
wire wrstrb_0011;
wire wrstrb_0100;
wire wrstrb_0101;
wire wrstrb_0110;
wire wrstrb_0111;
wire wrstrb_1000;
wire wrstrb_1001;
wire wrstrb_1010;
wire wrstrb_1011;
wire wrstrb_1100;
wire wrstrb_1101;
wire wrstrb_1110;
wire wrstrb_1111;
wire [9:0] mem_0000;
wire [9:0] mem_0001;
wire [9:0] mem_0010;
wire [9:0] mem_0011;
wire [9:0] mem_0100;
wire [9:0] mem_0101;
wire [9:0] mem_0110;
wire [9:0] mem_0111;
wire [9:0] mem_1000;
wire [9:0] mem_1001;
wire [9:0] mem_1010;
wire [9:0] mem_1011;
wire [9:0] mem_1100;
wire [9:0] mem_1101;
wire [9:0] mem_1110;
wire [9:0] mem_1111;
assign cs_wr = ~csn_wr;
assign do = dout;
assign wrstrb_0000 = ~wr_a[3] & ~wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0001 = ~wr_a[3] & ~wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_0010 = ~wr_a[3] & ~wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0011 = ~wr_a[3] & ~wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_0100 = ~wr_a[3] & wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0101 = ~wr_a[3] & wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_0110 = ~wr_a[3] & wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0111 = ~wr_a[3] & wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1000 = wr_a[3] & ~wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1001 = wr_a[3] & ~wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1010 = wr_a[3] & ~wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1011 = wr_a[3] & ~wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1100 = wr_a[3] & wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1101 = wr_a[3] & wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1110 = wr_a[3] & wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1111 = wr_a[3] & wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
dffe_ns #(10) U_dff_mem0000( .en(wrstrb_0000),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0000[9:0]));
dffe_ns #(10) U_dff_mem0001( .en(wrstrb_0001),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0001[9:0]));
dffe_ns #(10) U_dff_mem0010( .en(wrstrb_0010),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0010[9:0]));
dffe_ns #(10) U_dff_mem0011( .en(wrstrb_0011),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0011[9:0]));
dffe_ns #(10) U_dff_mem0100( .en(wrstrb_0100),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0100[9:0]));
dffe_ns #(10) U_dff_mem0101( .en(wrstrb_0101),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0101[9:0]));
dffe_ns #(10) U_dff_mem0110( .en(wrstrb_0110),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0110[9:0]));
dffe_ns #(10) U_dff_mem0111( .en(wrstrb_0111),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0111[9:0]));
dffe_ns #(10) U_dff_mem1000( .en(wrstrb_1000),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1000[9:0]));
dffe_ns #(10) U_dff_mem1001( .en(wrstrb_1001),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1001[9:0]));
dffe_ns #(10) U_dff_mem1010( .en(wrstrb_1010),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1010[9:0]));
dffe_ns #(10) U_dff_mem1011( .en(wrstrb_1011),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1011[9:0]));
dffe_ns #(10) U_dff_mem1100( .en(wrstrb_1100),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1100[9:0]));
dffe_ns #(10) U_dff_mem1101( .en(wrstrb_1101),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1101[9:0]));
dffe_ns #(10) U_dff_mem1110( .en(wrstrb_1110),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1110[9:0]));
dffe_ns #(10) U_dff_mem1111( .en(wrstrb_1111),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1111[9:0]));
always@(rd_a
or mem_0000
or mem_0001
or mem_0010
or mem_0011
or mem_0100
or mem_0101
or mem_0110
or mem_0111
or mem_1000
or mem_1001
or mem_1010
or mem_1011
or mem_1100
or mem_1101
or mem_1110
or mem_1111
)
begin
case(rd_a)
4'b0000 : dout= mem_0000;
4'b0001 : dout= mem_0001;
4'b0010 : dout= mem_0010;
4'b0011 : dout= mem_0011;
4'b0100 : dout= mem_0100;
4'b0101 : dout= mem_0101;
4'b0110 : dout= mem_0110;
4'b0111 : dout= mem_0111;
4'b1000 : dout= mem_1000;
4'b1001 : dout= mem_1001;
4'b1010 : dout= mem_1010;
4'b1011 : dout= mem_1011;
4'b1100 : dout= mem_1100;
4'b1101 : dout= mem_1101;
4'b1110 : dout= mem_1110;
4'b1111 : dout= mem_1111;
// CoverMeter line_off
default: dout= mem_0000;
// CoverMeter line_on
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 100; int n, x, t; long long ans, s[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &x); t = 0; while (x) { t += x % 2; x /= 2; } ++s[t]; } for (int i = 1; i <= N; ++i) ans += s[i] * (s[i] - 1) / 2; cout << ans; }
|
module scheduler_router(clk, rst, wen, Data_in_N, Data_in_S, Data_in_W, Data_in_E, Data_in_ready_N, Data_in_ready_S, Data_in_ready_W,
Data_in_ready_E, Data_out_N, Data_out_S, Data_out_W, Data_out_E,
Data_out_ready_N, Data_out_ready_S, Data_out_ready_W, Data_out_ready_E,
Data_out_valid_N, Data_out_valid_S, Data_out_valid_W, Data_out_valid_E,
Data_in_valid_N, Data_in_valid_E, Data_in_valid_S, Data_in_valid_W,
noc_locationx, noc_locationy);
parameter WIDTH=36;
parameter DEPTH=8;
parameter ADDR=4;
parameter lhsCount=5;
parameter rhsCount=5;
input clk;
input rst;
input wen;
input [WIDTH-1:0] Data_in_N;
input [WIDTH-1:0] Data_in_E;
input [WIDTH-1:0] Data_in_S;
input [WIDTH-1:0] Data_in_W;
//input [WIDTH-1:0] Data_in_L;
input Data_in_ready_N;
input Data_in_ready_E;
input Data_in_ready_S;
input Data_in_ready_W;
//input Data_in_ready_L;
output [WIDTH-1:0] Data_out_N;
output [WIDTH-1:0] Data_out_E;
output [WIDTH-1:0] Data_out_S;
output [WIDTH-1:0] Data_out_W;
//output [WIDTH-1:0] Data_out_L;
output Data_out_ready_N;
output Data_out_ready_E;
output Data_out_ready_S;
output Data_out_ready_W;
//output Data_out_ready_L;
output Data_out_valid_N;
output Data_out_valid_E;
output Data_out_valid_S;
output Data_out_valid_W;
input [1:0] noc_locationx;
input [1:0] noc_locationy;
input Data_in_valid_N;
input Data_in_valid_E;
input Data_in_valid_S;
input Data_in_valid_W;
wire [4:0] Data_in_valid;
assign Data_in_valid[0] = Data_in_valid_N;
assign Data_in_valid[1] = Data_in_valid_E;
assign Data_in_valid[2] = Data_in_valid_S;
assign Data_in_valid[3] = Data_in_valid_W;
wire [31:0] Data_router2scheduler;
wire [WIDTH-1:0] Data_scheduler2router;
wire Ready_router2scheduler;
wire Ready_scheduler2router;
wire [5*WIDTH-1:0] Data_out;
assign Data_out_N = Data_out[WIDTH-1:0];
assign Data_out_E = Data_out[2*WIDTH-1:WIDTH];
assign Data_out_S = Data_out[3*WIDTH-1:2*WIDTH];
assign Data_out_W = Data_out[4*WIDTH-1:3*WIDTH];
assign Data_router2scheduler = Data_out[5*WIDTH-1:4*WIDTH+4];
wire [4:0] Data_out_ready;
assign Data_out_ready[0] = Data_out_ready_N;
assign Data_out_ready[1] = Data_out_ready_E;
assign Data_out_ready[2] = Data_out_ready_S;
assign Data_out_ready[3] = Data_out_ready_W;
//assign Data_out_ready[4] = 1;
//assign Ready_router2scheduler = 1;
wire [4:0] Data_out_valid;
assign Data_out_valid_N = Data_out_valid[0];
assign Data_out_valid_E = Data_out_valid[1] ;
assign Data_out_valid_S = Data_out_valid[2] ;
assign Data_out_valid_W = Data_out_valid[3] ;
wire Valid_router2scheduler;
assign Valid_router2scheduler = Data_out_valid[4];
//assign Data_out_valid[4] = Ready_router2scheduler;
/*
reg [4:0] Data_out_ready;
always@* begin
Data_out_ready[0] = Data_out_ready_N;
Data_out_ready[1] = Data_out_ready_E;
Data_out_ready[2] = Data_out_ready_S;
Data_out_ready[3] = Data_out_ready_W;
Data_out_ready[4] = Ready_router2scheduler;
end
reg [4:0] Data_out_valid;
always@* begin
Data_out_valid[0] = Data_out_valid_N;
Data_out_valid[1] = Data_out_valid_E;
Data_out_valid[2] = Data_out_valid_S;
Data_out_valid[3] = Data_out_valid_W;
//assign Data_out_valid[4] = Ready_router2scheduler;
end
*/
wire [5*WIDTH-1:0] Data_in;
assign Data_in[WIDTH-1:0] = Data_in_N;
assign Data_in[2*WIDTH-1:WIDTH] = Data_in_E;
assign Data_in[3*WIDTH-1:2*WIDTH] = Data_in_S;
assign Data_in[4*WIDTH-1:3*WIDTH] = Data_in_W;
assign Data_in[5*WIDTH-1:4*WIDTH] = Data_scheduler2router;
//Connect to 'bustorouter_ready' of router
wire [4:0] Data_in_ready;
assign Data_in_ready[0] = Data_in_ready_N;
assign Data_in_ready[1] = Data_in_ready_E;
assign Data_in_ready[2] = Data_in_ready_S;
assign Data_in_ready[3] = Data_in_ready_W;
//assign Data_in_ready[4] = Ready_scheduler2router;
scheduler1 sch0(
.clk(clk),
.reset(rst),
.wen(wen),
.enablein(Valid_router2scheduler),
.datain(Data_router2scheduler),
.dataout(Data_scheduler2router),
.full(),
.empty(),
.enableout(Ready_scheduler2router));
router router0(
.clk(clk),
.reset_b(rst),
.bustorouter_data(Data_in),
.bustorouter_ready(Data_in_ready),
// Input
.bustorouter_valid(Data_in_valid),
.X(noc_locationx),
.Y(noc_locationy),
.routertobus_data(Data_out),
.routertobus_ready(Data_out_ready),
.routertobus_valid(Data_out_valid)
);
endmodule
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int n; vector<set<int> > g(200000); vector<int> used(200000); int main() { int n, m, k; cin >> n >> m >> k; vector<int> x(m); vector<int> y(m); for (int i = 0; i < m; i++) { cin >> x[i] >> y[i]; x[i]--; y[i]--; g[x[i]].insert(y[i]); g[y[i]].insert(x[i]); } set<pair<int, int> > s; vector<int> v(n); for (int i = 0; i < n; i++) { s.insert(make_pair(g[i].size(), i)); v[i] = g[i].size(); } while (s.size()) { int a = s.begin()->first; int b = s.begin()->second; if (a < k) { s.erase(make_pair(a, b)); v[b] = 0; for (auto i = g[b].begin(); i != g[b].end(); i++) if (v[*i] >= k) { s.erase(make_pair(v[*i], *i)); v[*i]--; s.insert(make_pair(v[*i], *i)); } } else break; } vector<int> ans(m); ans[m - 1] = s.size(); for (int i = m - 1; i >= 1; i--) { int fl = 0; if (s.find(make_pair(v[x[i]], x[i])) != s.end()) fl++; if (s.find(make_pair(v[y[i]], y[i])) != s.end()) fl++; if (fl != 2) ans[i - 1] = ans[i]; else { s.erase(make_pair(v[x[i]], x[i])); s.erase(make_pair(v[y[i]], y[i])); v[x[i]]--; v[y[i]]--; s.insert(make_pair(v[x[i]], x[i])); s.insert(make_pair(v[y[i]], y[i])); g[x[i]].erase(y[i]); g[y[i]].erase(x[i]); while (s.size()) { int a = s.begin()->first; int b = s.begin()->second; if (a < k) { s.erase(make_pair(a, b)); v[b] = 0; for (auto i = g[b].begin(); i != g[b].end(); i++) if (v[*i] >= k) { s.erase(make_pair(v[*i], *i)); v[*i]--; s.insert(make_pair(v[*i], *i)); } } else break; } ans[i - 1] = s.size(); } } for (int i = 0; i < m; i++) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long base = 1e9 + 7; const long long MAX_N = 2e5 + 7; long long dd2[MAX_N]; void Solves() { long long n, k; cin >> n >> k; long long l[n + 1]; long long r[n + 1]; priority_queue<pair<long long, long long>, vector<pair<long long, long long> > > pq1; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > pq2; vector<pair<long long, long long> > dd[MAX_N]; for (int i = 1; i <= n; i++) { cin >> l[i] >> r[i]; dd[l[i]].push_back(pair<long long, long long>(r[i], i)); } int countt = 0; int sum = 0; vector<pair<long long, long long> > ans; for (int i = 1; i <= 2e5; i++) { for (auto j : dd[i]) { pq1.push(j); pq2.push(j); sum++; } while (!pq2.empty()) { pair<long long, long long> gg = pq2.top(); if (gg.first < i) { pq2.pop(); if (dd2[gg.second] == 0) countt++; dd2[gg.second]++; } else break; } while (sum - countt > k) { pair<long long, long long> gg = pq1.top(); pq1.pop(); if (dd2[gg.second] == 0) countt++; dd2[gg.second]++; ans.push_back(gg); } } cout << ans.size() << n ; for (auto j : ans) cout << j.second << ; } int main() { Solves(); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Async clears must not race with clocks if we want repeatable results
reg set_l = in[20];
reg clr_l = in[21];
always @ (negedge clk) begin
set_l <= in[20];
clr_l <= in[21];
end
//====== Mux
wire [1:0] qm;
// delay z a b sel
udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]);
udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]);
`define verilatorxx
`ifdef verilatorxx
reg [1:0] ql;
reg [1:0] qd;
// No sequential tables, yet
// always @* begin
// if (!clk) ql = in[13:12];
// end
always @(posedge clk or negedge set_l or negedge clr_l) begin
if (!set_l) qd <= ~2'b0;
else if (!clr_l) qd <= 2'b0;
else qd <= in[17:16];
end
`else
//====== Latch
// wire [1:0] ql;
// // q clk d
// udp_latch l0 (ql[0], !in[8], in[12]);
// udp_latch l1 (ql[1], !in[8], in[13]);
//====== DFF
wire [1:0] qd;
//always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]);
// q clk d set_l clr_l
udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l);
udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l);
`endif
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm};
// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
// Note not all simulators agree about the latch result. Maybe have a race?
`define EXPECTED_SUM 64'hb73acf228acaeaa3
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
primitive udp_mux2 (z, a, b, sel);
output z;
input a, b, sel;
table
//a b s o
? 1 1 : 1 ;
? 0 1 : 0 ;
1 ? 0 : 1 ;
0 ? 0 : 0 ;
1 1 x : 1 ;
0 0 x : 0 ;
endtable
endprimitive
primitive udp_latch (q, clk, d);
output q; reg q;
input clk, d;
table
//clk d q q'
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
primitive udp_dff (q, clk, d, set_l, clr_l);
output q;
input clk, d, set_l, clr_l;
reg q;
table
//ck d s c : q : q'
r 0 1 ? : ? : 0 ;
r 1 ? 1 : ? : 1 ;
* 1 ? 1 : 1 : 1 ;
* 0 1 ? : 0 : 0 ;
f ? ? ? : ? : - ;
b * ? ? : ? : - ;
? ? 0 ? : ? : 1 ;
b ? * 1 : 1 : 1 ;
x 1 * 1 : 1 : 1 ;
? ? 1 0 : ? : 0 ;
b ? 1 * : 0 : 0 ;
x 0 1 * : 0 : 0 ;
endtable
endprimitive
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#include <bits/stdc++.h> using namespace std; const int M = (int)1e9 + 7; const int N = (int)2e5 + 5; struct trio { long long a; long long b; long long c; }; trio dp[2][N]; long long ps[N]; int main() { cout.precision(15); cout.setf(ios::fixed); int n, k; int i; cin >> n >> k; vector<int> v(n); for (i = 0; i < n; i++) { cin >> v[i]; if (i == 0) ps[i] = v[i]; else ps[i] = ps[i - 1] + v[i]; } long long ma = 0, p1, p2; for (i = k - 1; i < n; i++) { dp[0][i].a = ps[i] - (i >= k ? ps[i - k] : 0); dp[0][i].b = i; if (i >= k) if (dp[0][i - 1].a >= dp[0][i].a) { dp[0][i].a = dp[0][i - 1].a; dp[0][i].b = dp[0][i - 1].b; } if (i >= (2 * k - 1)) { dp[1][i].a = dp[0][i - k].a + ps[i] - (i >= k ? ps[i - k] : 0); dp[1][i].b = dp[0][i - k].b; } if (dp[1][i].a > ma) { ma = dp[1][i].a; p1 = dp[1][i].b; p2 = i; } } cout << p1 + 2 - k << << p2 + 2 - k << n ; }
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// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_slave_wrp #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
// If the fifo depth is zero, the module will perform the write ack here,
// otherwise it will take the write ack from the input s_writeack.
parameter integer FIFO_DEPTH = 0, // >= 0 (0 disables)
parameter integer PIPELINE = 1 // 0|1
)
(
input clock,
input resetn,
acl_arb_intf m_intf,
input logic s_writeack,
acl_ic_wrp_intf wrp_intf,
output logic stall
);
generate
if( NUM_MASTERS > 1 )
begin
// This slave endpoint may not directly talk to the ACTUAL slave. In
// this case we need a fifo to store which master each write ack should
// go to. If FIFO_DEPTH is 0 then we assume the writeack can be
// generated right here (the way it was done originally)
if( FIFO_DEPTH > 0 )
begin
// We don't have to worry about bursts, we'll fifo each transaction
// since writeack behaves like readdatavalid
logic rf_empty, rf_full;
acl_ll_fifo #(
.WIDTH( ID_W ),
.DEPTH( FIFO_DEPTH )
)
write_fifo(
.clk( clock ),
.reset( ~resetn ),
.data_in( m_intf.req.id ),
.write( ~m_intf.stall & m_intf.req.write ),
.data_out( wrp_intf.id ),
.read( wrp_intf.ack & ~rf_empty),
.empty( rf_empty ),
.full( rf_full )
);
// Register slave writeack to guarantee fifo output is ready
always @( posedge clock or negedge resetn )
begin
if( !resetn )
wrp_intf.ack <= 1'b0;
else
wrp_intf.ack <= s_writeack;
end
assign stall = rf_full;
end
else if( PIPELINE == 1 )
begin
assign stall = 1'b0;
always @( posedge clock or negedge resetn )
if( !resetn )
begin
wrp_intf.ack <= 1'b0;
wrp_intf.id <= 'x; // don't need to reset
end
else
begin
// Always register the id. The ack signal acts as the enable.
wrp_intf.id <= m_intf.req.id;
wrp_intf.ack <= 1'b0;
if( ~m_intf.stall & m_intf.req.write )
// A valid write cycle. Ack it.
wrp_intf.ack <= 1'b1;
end
end
else
begin
assign wrp_intf.id = m_intf.req.id;
assign wrp_intf.ack = ~m_intf.stall & m_intf.req.write;
assign stall = 1'b0;
end
end
else // NUM_MASTERS == 1
begin
// Only one master so don't need to check the id.
if ( FIFO_DEPTH == 0 )
begin
assign wrp_intf.ack = ~m_intf.stall & m_intf.req.write;
assign stall = 1'b0;
end
else
begin
assign wrp_intf.ack = s_writeack;
assign stall = 1'b0;
end
end
endgenerate
endmodule
|
#include<bits/stdc++.h> #define y1 dmytxdy #define pb push_back #define fi first #define se second #define mp make_pair using namespace std; typedef long long ll; typedef unsigned long long ull; typedef pair<int,int> pii; typedef pair<ll,ll> pll; typedef long double ld; template <typename T> bool chkmin(T &x,T y){return x>y?x=y,1:0;} template <typename T> bool chkmax(T &x,T y){return x<y?x=y,1:0;} int readint(){ int x=0,f=1; char ch=getchar(); while(ch< 0 ||ch> 9 ){if(ch== - )f=-1;ch=getchar();} while(ch>= 0 &&ch<= 9 ){x=x*10+ch- 0 ;ch=getchar();} return x*f; } const int cys=998244353,g=3,invg=(cys+1)/g; int n,k,N,l; ll fac[100005],inv[100005]; int A[300000],B[300000],r[300000]; ll mod(ll x){return x>=cys?x-cys:x;} ll qpow(ll x,ll p){ ll ret=1; for(;p;p>>=1,x=x*x%cys) if(p&1) ret=ret*x%cys; return ret; } void init(int m){ l=0; for(N=1;N<m;N<<=1) l++; for(int i=1;i<N;i++) r[i]=(r[i>>1]>>1)|((i&1)<<(l-1)); } void ntt(int *A,int N,int f){ for(int i=1;i<N;i++) if(i<r[i]) swap(A[i],A[r[i]]); for(int i=1;i<N;i<<=1){ int wn=qpow(f>0?g:invg,(cys-1)/(i<<1)); for(int j=0;j<N;j+=(i<<1)){ for(int k=j,w=1;k<j+i;k++,w=1ll*w*wn%cys){ int x=A[k],y=1ll*w*A[k+i]%cys; A[k]=mod(x+y); A[k+i]=mod(x+cys-y); } } } if(f<0){ ll invn=qpow(N,cys-2); for(int i=0;i<N;i++) A[i]=A[i]*invn%cys; } } int main(){ n=readint(); k=readint(); fac[0]=inv[0]=1; for(int i=1;i<=k;i++) fac[i]=fac[i-1]*i%cys; inv[k]=qpow(fac[k],cys-2); for(int i=k-1;i>=1;i--) inv[i]=inv[i+1]*(i+1)%cys; for(int i=0;i<=k;i++) A[i]=i&1?cys-inv[i]:inv[i]; for(int i=0;i<=k;i++) B[i]=qpow(i,k)*inv[i]%cys; init(k+k+1); ntt(A,N,1); ntt(B,N,1); for(int i=0;i<N;i++) A[i]=1ll*A[i]*B[i]%cys; ntt(A,N,-1); ll now=1,ans=0; for(int i=1;i<=k;i++){ now=now*(n-i+1)%cys; if(!now) break; ans=(ans+A[i]*now%cys*qpow(n+1,n-i))%cys; } printf( %lld n ,ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, d; cin >> x >> d; long long start = 1; vector<long long> arr; while (x > 0) { int toPrint = 1; while ((1LL << toPrint) - 1 <= x) toPrint++; toPrint--; for (long long i = start; i < start + toPrint; i++) arr.push_back(start); start += toPrint + d + 1; x -= ((1LL << toPrint) - 1); } if (arr.size() > 1e4 || start >= 1e18) { cout << -1 ; return 0; } cout << arr.size() << endl; for (int i = 0; i < arr.size(); i++) cout << arr[i] << ; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_comp_gen_fx_color
(
input clk,
input rstn,
input signed [31:0] dx_fx, // 16.16
input signed [31:0] dy_fx, // 16.16
input [95:0] cmp_i,
output [7:0] curr_i
);
reg signed [57:0] ix;
reg signed [57:0] iy;
reg signed [57:0] ixy;
reg signed [19:0] curr;
assign curr_i = (curr[19]) ? 8'h00 : // Under flow.
(curr[18]) ? 8'hff : // Over flow.
curr[17:10]; // Normal.
wire [17:0] sp_fx;
wire signed [25:0] idx_fx;
wire signed [25:0] idy_fx;
assign sp_fx = flt_fx_8p10(cmp_i[95:64]);
assign idx_fx = flt_fx_16p10(cmp_i[63:32]);
assign idy_fx = flt_fx_16p10(cmp_i[31:0]);
always @(posedge clk) begin
ix <= dx_fx * idx_fx; // 16.16 * 16.10 = 32.26
iy <= dy_fx * idy_fx; // 16.16 * 16.10 = 32.26
ixy <= iy + ix; // 32.26 + 32.26 = 32.26
curr <= ixy[35:16] + {2'b00, sp_fx}; // 10.10 + 10.10 = 10.10
end
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
function [25:0] flt_fx_16p10;
input [31:0] fp_in; // Floating point in IEEE fmt
// 16.10, Color.
reg [7:0] bias_exp; /* Real exponent -127 - 128 */
reg [7:0] bias_exp2; /* Real exponent 2's comp */
reg [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
begin
bias_mant = {25'h0001, fp_in[22:0]};
bias_exp = fp_in[30:23] - 8'd127;
bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[38:13];
flt_fx_16p10 = (fp_in[31]) ? ~fixed_out[25:0] + 26'h1 : fixed_out[25:0];
end
endfunction
function [17:0] flt_fx_8p10;
input [31:0] fp_in; // Floating point in IEEE fmt
// 16.10, Color.
reg [7:0] bias_exp; /* Real exponent -127 - 128 */
reg [7:0] bias_exp2; /* Real exponent 2's comp */
reg [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
begin
bias_mant = {25'h0001, fp_in[22:0]};
bias_exp = fp_in[30:23] - 8'd127;
bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[31:13];
flt_fx_8p10 = (fp_in[31]) ? ~fixed_out[17:0] + 18'h1 : fixed_out[17:0];
end
endfunction
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_rows_V_channel1_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_rows_V_channel1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_rows_V_channel1_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_rows_V_channel1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_tc
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_tc.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_tc.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_tc
//
// No user `defines in this module
module avfb_tc
//
// Generated module i_avfb_tc
//
(
BC_RA_02_fail_o
);
// Generated Module Outputs:
output BC_RA_02_fail_o;
// Generated Wires:
wire BC_RA_02_fail_o;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_tc_ctrl
avfb_tc_ctrl i_avfb_tc_ctrl (
);
// End of Generated Instance Port Map for i_avfb_tc_ctrl
endmodule
//
// End of Generated Module rtl of avfb_tc
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
//
// The given generate loops should only access valid bits of mask, since that
// is defined by SIZE. However since the loop range is larger, this only works
// if short-circuited evaluation of the generate loop is in place.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
`define MAX_SIZE 4
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (2'b11))
i_test_gen (.clk (clk));
// This is only a compilation test, but for good measure we do one clock
// cycle.
integer count;
initial begin
count = 0;
end
always @(posedge clk) begin
if (count == 1) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
count = count + 1;
end
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that rely on short-circuiting of the logic to avoid errors.
generate
genvar g;
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < SIZE) && MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g >= SIZE) || ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g < SIZE) -> ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ( g < SIZE ? MASK[g] : 1'b0) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
// The other way round
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ( g >= SIZE ? 1'b0 : MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_1_V
`define SKY130_FD_SC_LP__A221O_1_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_1 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_1_V
|
#include <bits/stdc++.h> using namespace std; bool vowel(char c) { string s = aeiou ; for (int i = 0; i < 5; i++) if (c == s[i]) return true; return false; } bool rhyme(string s1, string s2, int k) { int i = s1.size() - 1, j = s2.size() - 1; int cnt = 0; while (i >= 0 && j >= 0) { if (s1[i] != s2[j]) return false; if (vowel(s1[i])) cnt++; if (cnt == k) return true; i--; j--; } return false; } int main() { int n, k; cin >> n >> k; string scheme[4] = { aabb , abab , abba , aaaa }; int ans = -1; for (int i = 0; i < n; i++) { string s[4]; cin >> s[0] >> s[1] >> s[2] >> s[3]; int temp = -1; if (rhyme(s[0], s[1], k) && rhyme(s[2], s[3], k) && rhyme(s[0], s[2], k)) { temp = 3; } else if (rhyme(s[0], s[1], k) && rhyme(s[2], s[3], k)) { temp = 0; } else if (rhyme(s[0], s[2], k) && rhyme(s[1], s[3], k)) { temp = 1; } else if (rhyme(s[0], s[3], k) && rhyme(s[1], s[2], k)) { temp = 2; } else { ans = -1; break; } if (ans < 0) ans = temp; else if (temp == 3 && ans >= 0 && ans <= 2) continue; else if (ans == 3 && temp >= 0 && temp <= 2) ans = temp; else if (temp != ans) { ans = -1; break; } } if (ans >= 0) cout << scheme[ans] << endl; else cout << NO << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_TB_V
`define SKY130_FD_SC_HDLL__AND4B_TB_V
/**
* and4b: 4-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hdll__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_TB_V
|
#include <bits/stdc++.h> using namespace std; inline int bit(int x, int i) { return (x >> i) & 1; } inline int two(int x) { return 1 << x; } int n, s[110], m, team[110], dp[20][1 << 20]; char op[110]; bool vis[20][1 << 20]; int go(int mi, int ban) { if (mi == m) return 0; int &ret = dp[mi][ban]; if (vis[mi][ban]) return ret; vis[mi][ban] = 1; ret = -514514514; for (int i = 0; i < (int)(n); i++) if (!bit(ban, i)) { int now = go(mi + 1, ban | two(i)); int str = (op[mi] == p ? s[i] : 0); if (mi + 1 < m && team[mi + 1] != team[mi]) now = str - now; else now = str + now; ret = max(ret, now); } return ret; } int main() { scanf( %d , &(n)); for (int i = 0; i < (int)(n); i++) scanf( %d , &(s[i])); scanf( %d , &(m)); for (int i = 0; i < (int)(m); i++) scanf( %c %d , op + i, team + i); sort(s, s + n, greater<int>()); n = m; int ans = go(0, 0); if (team[0] == 2) ans *= -1; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long RAND(long long n) { return abs((rand() << 15) + rand()) % n; } bool check(int i, int j, int n) { return ((i >= 0) && (j >= 0) && (i < n) && (j < n)); } int move_x[] = {1, 0}; int move_y[] = {0, 1}; vector<vector<vector<vector<bool>>>> solve(vector<vector<int>> &a) { int n = a.size(); vector<vector<vector<vector<bool>>>> ans( n, vector<vector<vector<bool>>>( n, vector<vector<bool>>(n, vector<bool>(n, false)))); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { ans[i][j][i][j] = true; } } for (int len = 1; len <= 2 * n - 2; ++len) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int x = 0; x <= len; ++x) { int k = i + x, t = j + len - x; if (!check(k, t, n) || a[i][j] != a[k][t]) { continue; } if ((abs(k - i) + abs(t - j)) == 1) { ans[i][j][k][t] = true; continue; } for (int i1 = 0; i1 < 2; ++i1) { for (int i2 = 0; i2 < 2; ++i2) { int next_x = i + move_x[i1], next_y = j + move_y[i1]; int prev_x = k - move_x[i2], prev_y = t - move_y[i2]; if (!check(next_x, next_y, n) || !check(prev_x, prev_y, n)) { continue; } if (next_x > prev_x || next_y > prev_y) { continue; } if (ans[next_x][next_y][prev_x][prev_y]) { ans[i][j][k][t] = ans[next_x][next_y][prev_x][prev_y]; } } } } } } } return ans; } int query(int i, int j, int t, int k) { i++; j++; t++; k++; cout << ? << i << << j << << t << << k << endl << flush; int ans; cin >> ans; if (ans == -1) { exit(0); } return !ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; vector<vector<int>> a(n, vector<int>(n, 0)); a[0][0] = 1; a[n - 1][n - 1] = 0; for (int i = 2; i < n; ++i) { a[0][i] = a[0][i - 2] ^ query(0, i - 2, 0, i); } a[1][0] = a[0][1] ^ query(0, 1, 1, 2) ^ query(1, 0, 1, 2); for (int i = 2; i < n; ++i) { a[i][0] = a[i - 2][0] ^ query(i - 2, 0, i, 0); } for (int i = 1; i < n; ++i) { for (int j = 1; j < n; ++j) { a[i][j] = a[i - 1][j - 1] ^ query(i - 1, j - 1, i, j); } } vector<vector<int>> b = a; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if ((i + j) % 2 == 1) { b[i][j] = 1 - a[i][j]; } } } vector<vector<vector<vector<bool>>>> A = solve(a); vector<vector<vector<vector<bool>>>> B = solve(b); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int k = i; k < n; ++k) { for (int t = j; t < n; ++t) { if ((abs(k - i) + abs(t - j)) < 2) { continue; } if (A[i][j][k][t] ^ B[i][j][k][t]) { if (!query(i, j, k, t) == A[i][j][k][t]) { cout << ! n ; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cout << a[i][j]; } cout << endl; } return 0; } else { swap(a, b); cout << ! n ; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cout << a[i][j]; } cout << endl; } return 0; } } } } } } return 0; }
|
/*
Filename : EX2MEM.v
Compiler : Quartus II
Description : EX to MEM register
INPUT : clk, rst, EN, all active high
RegWrite_In, MemWrite_In, MemRead_In,
[31:0] PC_In, ALUOut_In, DataBusB_In
[4:0] AddrC_In,
[3:0] PCSrc_In,
[1:0] MemtoReg_In,
OUTPUT : RegWrite_Out, MemWrite_Out, MemRead_Out,
[31:0] PC_Out, ALUOut_Out, DataBusB_In
[4:0] AddrC_Out,
[3:0] PCSrc_Out,
[1:0] MemtoReg_Out,
Author : Yeoman Zhuang
Release : *
*/
module EX2MEM(
input clk, rst,
input RegWrite_In, MemWrite_In, MemRead_In,
input [31:0] PC_In, ALUOut_In, DataBusB_In,
// !!! AddrC i.e. EX2MEM_Rd
input [4:0] AddrC_In,
input [1:0] MemtoReg_In,
output reg RegWrite_Out, MemWrite_Out, MemRead_Out,
output reg [31:0] PC_Out, ALUOut_Out, DataBusB_Out,
output reg [4:0] AddrC_Out,
output reg [1:0] MemtoReg_Out
);
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
RegWrite_Out <= 0;
MemWrite_Out <= 0;
MemRead_Out <= 0;
PC_Out <= 0;
ALUOut_Out <= 0;
AddrC_Out <= 0;
MemtoReg_Out <= 0;
DataBusB_Out <= 0;
end else begin
RegWrite_Out <= RegWrite_In;
MemWrite_Out <= MemWrite_In;
MemRead_Out <= MemRead_In;
PC_Out <= PC_In;
ALUOut_Out <= ALUOut_In;
AddrC_Out <= AddrC_In;
MemtoReg_Out <= MemtoReg_In;
DataBusB_Out <= DataBusB_In;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void qmax(long long &x, int y) { if (x < y) x = y; } void qmin(long long &x, long long y) { if (x > y) x = y; } inline long long read() { char s; long long k = 0, base = 1; while ((s = getchar()) != - && s != EOF && !(isdigit(s))) ; if (s == EOF) exit(0); if (s == - ) base = -1, s = getchar(); while (isdigit(s)) { k = k * 10 + (s ^ 0 ); s = getchar(); } return k * base; } inline void write(int x) { static char cnt, num[15]; cnt = 0; if (!x) { printf( 0 ); return; } for (; x; x /= 10) num[++cnt] = x % 10; for (; cnt; putchar(num[cnt--] + 48)) ; } const int maxn = 1e5 + 100; int n, m, k, s, X, Y; int a[maxn]; int po[maxn], ne[maxn * 2], to[maxn * 2], id; void add(int x, int y) { id++; to[id] = y; ne[id] = po[x]; po[x] = id; } int dis[maxn], vis[maxn]; queue<int> q; int c[maxn][101]; void spfa(int x) { memset(vis, 0, sizeof(vis)); memset(dis, 0x3f3f3f3f, sizeof(dis)); int inf = dis[0]; while (!q.empty()) q.pop(); for (int i = 1; i <= n; i++) if (a[i] == x) { dis[i] = 0; vis[i] = 1; q.push(i); } while (!q.empty()) { int u = q.front(), v; q.pop(); vis[u] = 0; for (int i = po[u]; i; i = ne[i]) { v = to[i]; if (dis[v] > dis[u] + 1) { dis[v] = dis[u] + 1; if (!vis[v]) { vis[v] = 1; q.push(v); } } } } for (int i = 1; i <= n; i++) c[i][x] = dis[i]; } int main() { n = read(); m = read(); k = read(); s = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= m; i++) { X = read(); Y = read(); add(X, Y); add(Y, X); } for (int i = 1; i <= k; i++) spfa(i); for (int i = 1; i <= n; i++) { long long sum = 0; sort(c[i] + 1, c[i] + k + 1); for (int j = 1; j <= s; j++) sum += c[i][j]; printf( %lld , sum); } }
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* WATCHDOG TIMER */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer: */
/* - Clock source selection. */
/* */
/* Author(s): */
/* - Olivier Girard, */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer mclk_counter;
always @ (posedge mclk)
mclk_counter <= mclk_counter+1;
integer r5_counter;
always @ (posedge r5[0] or negedge r5[0])
r5_counter <= r5_counter+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
`ifdef WATCHDOG
// WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2
//--------------------------------------------------------
@(r15 === 16'h0001);
@(posedge r5[0]);
@(negedge mclk);
mclk_counter = 0;
r5_counter = 0;
repeat(1024) @(negedge mclk);
if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
`ifdef SMCLK_DIVIDER
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");
`else
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");
`endif
`else
`ifdef WATCHDOG_NOMUX_ACLK
`ifdef LFXT_DOMAIN
if (r5_counter !== 0) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 4 =====");
`else
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 5 =====");
`endif
`else
`ifdef SMCLK_DIVIDER
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 6 =====");
`else
if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 7 =====");
`endif
`endif
`endif
`else
if (r5_counter !== 8) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 8 =====");
`endif
// WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1
//--------------------------------------------------------
@(r15 === 16'h1001);
@(negedge r5[0]);
@(negedge mclk);
mclk_counter = 0;
r5_counter = 0;
repeat(7815) @(negedge mclk);
if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");
`else
`ifdef WATCHDOG_NOMUX_ACLK
`ifdef LFXT_DOMAIN
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 3 =====");
`else
if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 4 =====");
`endif
`else
if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 5 =====");
`endif
`endif
`else
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 6 =====");
`endif
`else
tb_skip_finish("| (the Watchdog is not included) |");
`endif
stimulus_done = 1;
end
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; int b[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; int c = 0, r = 0; for (int i = 0; i < n; i++) { if (a[i] == 0 and b[i] == 1) c++; if (a[i] == 1 and b[i] == 0) r++; } if (r > c) { cout << 1 << endl; } else if (r == 0) cout << -1 << endl; else { int val = ceil(((float)(c + 1) / (float)r)); cout << val << endl; } return 0; }
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_reset_inv_synchronizer # (
parameter FREQUENCY = 512
)(
input wire clk_in,
input wire rst_in,
output wire rst_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also
// asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the
// downstream logic is also removed from reset synchronously. This module is designed for active-low reset use.
(* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0;
(* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0;
(* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0;
(* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0;
reg rst_in_out = 1'b0;
always @(posedge clk_in, negedge rst_in) begin
if (!rst_in) begin
rst_in_meta <= 1'b0;
rst_in_sync1 <= 1'b0;
rst_in_sync2 <= 1'b0;
rst_in_sync3 <= 1'b0;
rst_in_out <= 1'b0;
end
else begin
rst_in_meta <= 1'b1;
rst_in_sync1 <= rst_in_meta;
rst_in_sync2 <= rst_in_sync1;
rst_in_sync3 <= rst_in_sync2;
rst_in_out <= rst_in_sync3;
end
end
assign rst_out = rst_in_out;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CRC_chk.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:16 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module CRC_chk(
Reset ,
Clk ,
CRC_data ,
CRC_init ,
CRC_en ,
//From CPU
CRC_chk_en ,
CRC_err
);
input Reset ;
input Clk ;
input[7:0] CRC_data ;
input CRC_init ;
input CRC_en ;
//From CPU
input CRC_chk_en ;
output CRC_err ;
//******************************************************************************
//internal signals
//******************************************************************************
reg [31:0] CRC_reg;
wire[31:0] Next_CRC;
//******************************************************************************
//input data width is 8bit, and the first bit is bit[0]
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
always @ (posedge Clk or posedge Reset)
if (Reset)
CRC_reg <=32'hffffffff;
else if (CRC_init)
CRC_reg <=32'hffffffff;
else if (CRC_en)
CRC_reg <=NextCRC(CRC_data,CRC_reg);
assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; int main() { string a; cin >> a; int sz = int(a.size()); for (__typeof(sz) i = 0; i < sz; i++) for (__typeof(sz) j = 0; j < sz; j++) if (a.substr(0, i) + a.substr(j + 1) == CODEFORCES ) { cout << YES n ; return 0; } cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int i, j, k, n, m, l; const int N = 1e5 + 8; int vis[N]; vector<int> adj[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } queue<int> q; q.push(1); memset(vis, 0, sizeof(vis)); vis[1] = 1; l = 0; long long ev = 0, od = 0; while (1) { int c = q.size(); if (!c) break; while (c) { int s = q.front(); q.pop(); c--; if (l & 1) ev++; else od++; for (auto u : adj[s]) { if (!vis[u]) { vis[u] = 1; q.push(u); } } } l++; } cout << (ev * od - (n - 1)) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int T, N, val[53][53], rk[53][53], fr[103]; vector<int> peo[53]; int pos[53]; void go(bool flg) { queue<int> q; for (int i = 1; i <= N; ++i) { peo[i].clear(); for (int j = 1; j <= N; ++j) peo[i].push_back(j); sort(peo[i].begin(), peo[i].end(), [&](int p, int q) { return (val[i][p] < val[i][q]) ^ flg; }); q.push(i); pos[i] = fr[i] = fr[i + N] = 0; } for (int i = 1; i <= N; ++i) { vector<int> tmp; for (int j = 1; j <= N; ++j) tmp.push_back(j); sort(tmp.begin(), tmp.end(), [&](int p, int q) { return (val[p][i] > val[q][i]) ^ flg; }); for (int j = 0; j < tmp.size(); ++j) rk[i][tmp[j]] = j + 1; } while (!q.empty()) { int t = q.front(); q.pop(); while (!fr[t]) { int tar = peo[t][pos[t]++]; if (!fr[tar + N] || rk[tar][fr[tar + N]] > rk[tar][t]) { fr[fr[tar + N]] = 0; if (fr[tar + N]) q.push(fr[tar + N]); fr[tar + N] = t; fr[t] = tar + N; } } } } int main() { for (cin >> T; T; --T) { cin >> N; for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) cin >> val[i][j]; cout << B << endl; char c; cin >> c; if (c == D ) for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) val[i][j] = -val[i][j]; int p; cin >> p; go(p > N); while (p != -1) { cout << fr[p] << endl; cin >> p; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 2e5 + 10; const int mod = 1e9 + 7; struct pairNode { char ch; long long times; pairNode(char ch = 0, long long times = 0) : ch(ch), times(times) {} ~pairNode() = default; bool operator==(const pairNode &rhs) const { return ch == rhs.ch && times == rhs.times; } bool operator!=(const pairNode &rhs) const { return ch != rhs.ch || times != rhs.times; } bool operator>=(const pairNode &rhs) const { return ch == rhs.ch && times >= rhs.times; } }; int tS, tT; vector<pairNode> S, T, newT; int nxt[M]; inline void getInput(vector<pairNode> &S, int len) { char cur = 0, ch[3]; long long curtimes = 0, times; for (int i = 0; i < len; ++i) { scanf( %I64d-%s , ×, ch); if (ch[0] == cur) { curtimes += times; } else { if (i) S.push_back(pairNode(cur, curtimes)); cur = ch[0]; curtimes = times; } } S.push_back(pairNode(cur, curtimes)); } int main() { S.clear(); T.clear(); cin >> tS >> tT; getInput(S, tS); getInput(T, tT); if (T.size() == 1) { long long ans = 0; for (int i = 0; i < S.size(); ++i) if (S[i] >= T[0]) ans += S[i].times - T[0].times + 1; cout << ans << endl; return 0; } if (T.size() == 2) { long long ans = 0; for (int i = 0; i < S.size() - 1; ++i) if (S[i] >= T[0] && S[i + 1] >= T[1]) ++ans; cout << ans << endl; return 0; } for (int i = 1; i < T.size() - 1; ++i) newT.push_back(T[i]); nxt[0] = -1; int k = -1; for (int i = 1; i < newT.size(); ++i) { while (k != -1 && newT[k + 1] != newT[i]) k = nxt[k]; if (newT[k + 1] == newT[i]) ++k; nxt[i] = k; } long long ans = 0; k = -1; for (int i = 0; i < S.size(); ++i) { while (k != -1 && newT[k + 1] != S[i]) k = nxt[k]; if (newT[k + 1] == S[i]) ++k; if (k == newT.size() - 1) { if (i >= newT.size() && i + 1 <= S.size() && S[i - newT.size()] >= T[0] && S[i + 1] >= T[T.size() - 1]) ++ans; k = nxt[k]; } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; int qmul(int a, int b) { a = (a % mod + mod) % mod; b = (b % mod + mod) % mod; int ans = 0; while (b) { if (b & 1) ans = (ans + a) % mod; a = (a << 1) % mod; b >>= 1; } return ans; } int qpow(int a, int p) { int ans = 1; while (p) { if (p & 1) ans = qmul(ans, a); a = qmul(a, a); p >>= 1; } return ans; } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { int n, a, p = 0, q = 1; cin >> n; for (int i = 1; i <= n; i++) { cin >> a; p = qmul((p + q) % mod, 100); q = qmul(q, a); int r = gcd(p, q); p = p / r; q = q / r; } cout << qmul(p, qpow(q, mod - 2)) << endl; return 0; }
|
`timescale 1ns/1ps
`include "../global.v"
module SigRegisterFile_tb();
reg clk;
reg reset;
reg writeEnableR0, writeEnableR1;
reg [31:0] writeValueR0, writeValueR1;
reg shiftEnableR0;
reg [3:0] readSelectA, readSelectB;
wire [31:0] readResultA, readResultB;
SigRegisterFile DUT(clk, reset, writeEnableR0, writeEnableR1, writeValueR0, writeValueR1,
shiftEnableR0, readSelectA, readSelectB, readResultA, readResultB);
initial forever begin
#10 clk = ~clk;
end
initial begin
clk = 0;
reset = 1;
writeEnableR0 = 1'b1;
writeEnableR1 = 1'b1;
writeValueR0 = 32'h0000aaaa;
writeValueR1 = 32'h0000bbbb;
shiftEnableR0 = 1'b0;
readSelectA = 3'b000;
readSelectB = 3'b001;
#20 reset = 0;
@(posedge clk);
@(posedge clk);
writeEnableR0 = 1'b0;
writeEnableR1 = 1'b0;
shiftEnableR0 = 1'b1;
@(posedge clk);
writeEnableR0 = 1'b0;
writeEnableR1 = 1'b0;
shiftEnableR0 = 1'b0;
readSelectA = 3'b010;
readSelectB = 3'b011;
#20 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s1, s2; set<char> st; vector<int> t[300]; int bin_search(char k, int ind) { int l = 0, r = t[k].size() - 1, m; while (l < r) { m = (l + r) / 2; if (ind == t[k][m]) return t[k][m]; if (ind < t[k][m]) r = m; else l = m + 1; } if (l && t[k][l - 1] == ind) return t[k][l - 1]; return t[k][l]; } int main() { cin >> s1 >> s2; for (int i = 0; i < s1.size(); i++) t[s1[i]].push_back(i); for (int j = 0; j < s2.size(); j++) if (!t[s2[j]].size()) { cout << -1 ; return 0; } int ans = 1, j = 0; for (int i = 0; i < s2.size(); i++) { int p = bin_search(s2[i], j); if (p < j) { ans++; j = bin_search(s2[i], 0) + 1; } else { j = p + 1; } } printf( %d , ans); return 0; }
|
module MEMWB_Reg (
input clk,
input rst,
input flush,
input stall,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] ALU_output_i,
output [32-1:0] ALU_output_o,
input [32-1:0] Mem_output_i,
output [32-1:0] Mem_output_o,
input [5-1:0] RegFwd_i,
output [5-1:0] RegFwd_o
);
Latch #(.width(2)) MEMWB_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch MEMWB_ALU_output (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (ALU_output_i),
.data_o (ALU_output_o)
);
Latch MEMWB_Mem_output (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Mem_output_i),
.data_o (Mem_output_o)
);
Latch #(.width(5)) MEMWB_RegFwd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (RegFwd_i),
.data_o (RegFwd_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, k; cin >> n >> k; string second; cin >> second; vector<long long> cnt(k, 0); for (long long i = 0; i < n; i++) { cnt[second[i] - A ]++; } long long ans = cnt[0]; for (long long i = 0; i < k; i++) { ans = min(ans, cnt[i]); } cout << ans * k << endl; } signed main() { long long n = 1; while (n--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int bound = 400; struct qq { int id, vl; bool operator<(const qq &temp) const { return vl < temp.vl; } }; qq bk[210000 / bound][bound], ns; int nk[210000 / bound]; struct pp { int vl, id, min_value, value; int flag; bool operator<(const pp &temp) const { return vl < temp.vl; } }; pp bl[210000 / bound][2 * bound], now; int num[210000 / bound], num_bl, cnt_list, np[2 * bound]; int m, n, a[220000], num_q, ans, nw; int lower_bound(int left, int right, qq bl[], int x) { int mid; while (left <= right) { mid = (left + right) >> 1; if (bl[mid].vl < x) left = mid + 1; else right = mid - 1; } return right; } int lower_bound(int left, int right, pp bl[], int x) { int mid; while (left <= right) { mid = (left + right) >> 1; if (bl[mid].vl < x) left = mid + 1; else right = mid - 1; } return right; } int main() { int i, j, s, p, q, ip, id, l, r, x, fir; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) scanf( %d , &a[i]); memset(num, 0, sizeof(num)); memset(nk, 0, sizeof(nk)); num_bl = 0; for (i = 0; i < n; i++) { if (i % bound == 0) { for (j = i; j < min(n, i + bound); j++) { if (j + m < n) { now.id = j; now.vl = a[j]; now.flag = -1; bl[num_bl][num[num_bl]++] = now; now.id = j + m; now.vl = a[j + m]; now.flag = 1; bl[num_bl][num[num_bl]++] = now; } ns.id = j; ns.vl = a[j]; bk[num_bl][nk[num_bl]++] = ns; } num_bl++; } } for (i = 0; i < num_bl; i++) { sort(bl[i], bl[i] + num[i]); sort(bk[i], bk[i] + nk[i]); for (j = i * bound; j < min((i + 1) * bound, n); j++) np[j - i * bound] = 0; for (j = 0; j < num[i]; j++) { bl[i][j].value = bl[i][j].flag; ip = bl[i][j].id; if (bl[i][j].flag > 0) ip -= m; np[ip - i * bound] += bl[i][j].flag; if (bl[i][j].flag < 0) { if (bl[i][j].id + m >= n) { bl[i][j].value = 0; np[ip - i * bound]++; } } if (j) { bl[i][j].value += bl[i][j - 1].value; } bl[i][j].min_value = 0; nw = 0; for (s = i * bound; s < min((i + 1) * bound, n); s++) { nw += np[s - i * bound]; if (bl[i][j].min_value > nw) bl[i][j].min_value = nw; } } } scanf( %d , &num_q); ans = 0; while (num_q--) { scanf( %d%d%d , &l, &r, &x); l--; r--; x ^= ans; ans = 0; id = l / bound; nw = fir = 0; for (i = l; i <= min(l + m - 1, (l / bound + 1) * bound - 1); i++) { if (a[i] < x) fir++; } if (l + m - 1 >= (l / bound + 1) * bound) { for (i = (l + m - 1) / bound * bound; i <= l + m - 1; i++) { if (a[i] < x) fir++; } for (i = l / bound + 1; i < (l + m - 1) / bound; i++) { id = lower_bound(0, nk[i] - 1, bk[i], x); fir += (id + 1); } } for (i = l; i <= min(r - 1, (l / bound + 1) * bound - 1); i++) { if (i + m < n) { if (a[i] < x) nw--; if (a[i + m] < x) nw++; if (ans > nw) ans = nw; } } if (r - 1 >= (l / bound + 1) * bound) { for (i = l / bound + 1; i < (r - 1) / bound; i++) { id = lower_bound(0, num[i] - 1, bl[i], x); if (id >= 0) { if (nw + bl[i][id].min_value < ans) ans = nw + bl[i][id].min_value; nw += bl[i][id].value; } } for (i = ((r - 1) / bound) * bound; i <= r - 1; i++) { if (i + m < n) { if (a[i] < x) nw--; if (a[i + m] < x) nw++; if (ans > nw) ans = nw; } } } ans += fir; printf( %d n , ans); } return 0; }
|
module intermediator_tb;
parameter INTERMEDIATOR_DEPTH = 1024;
parameter LOG2_INTERMEDIATOR_DEPTH = log2(INTERMEDIATOR_DEPTH - 1);
reg clk, rst, wr0;
reg [LOG2_INTERMEDIATOR_DEPTH - 1:0] row0;
reg [65:0] v0;
reg wr1;
reg [LOG2_INTERMEDIATOR_DEPTH - 1:0] row1;
reg [65:0] v1;
wire push_to_adder;
wire [LOG2_INTERMEDIATOR_DEPTH - 1:0] row_to_adder;
wire [65:0] v0_to_adder;
wire [65:0] v1_to_adder;
wire push_to_y;
wire [65:0] v_to_y;
reg eof;
intermediator #(8) dut(clk, rst, wr0, row0, v0, wr1, row1, v1, push_to_adder, row_to_adder, v0_to_adder, v1_to_adder, push_to_y, v_to_y, eof);
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
#3000 $display("watchdog reached");
$finish;
end
integer i;
initial begin
rst = 1;
wr0 = 0;
row0 = 0;
v0 = 0;
wr1 = 0;
row1 = 0;
v1 = 0;
eof = 0;
#100 rst = 0;
#100 wr0 = 1;
#10 wr0 = 0;
#10 wr0 = 1;
#10 wr0 = 0;
//TODO: figure out
for(i = 0; i < 8; i = i + 1) begin
wr0 = 1;
row0 = i;
#10;
end
wr0 = 0;
#2000 wr0 = 1;
row0 = 4;
wr1 = 1;
row1 = 5;
#10 wr0 = 0;
wr1 = 0;
#100 wr0 = 1;
row0 = 4;
wr1 = 1;
row1 = 4;
#10 wr0 = 0;
wr1 = 0;
end
integer store_count;
initial store_count = 0;
integer adder_count;
initial adder_count = 0;
always @(posedge clk) begin
//$display("debug: ");
//$display("%d", push_to_adder);
if(dut.p0_stage_1)
$display("p0_stage_1");
if(dut.p0_stage_2) begin
$display("p0_stage_2");
$display("r0_stage_2: %d", dut.r0_stage_2);
$display("occupency0_stage_2_comb: %d", dut.occupency0_stage_2_comb);
end
if(dut.p0_stage_3) begin
$display("p0_stage_3");
$display("occupency0_stage_3: %d", dut.occupency0_stage_3);
end
if(dut.to_store_stage_2_comb)
$display("to_store_stage_2_comb");
//$display("to_store_stage_2_comb: %d", dut.to_store_stage_2_comb);
if(dut.p0_retrieve_from_intermediator_stage_4)
$display("p0_retrieve_stage_4");
if(dut.p0_store_to_intermediator_stage_4)
$display("p0_store_stage_4");
if(dut.p0_retrieve_from_intermediator_stage_4 || dut.p0_store_to_intermediator_stage_4) begin
end
if(dut.p0_stage_5)
$display("p0_stage_5");
if(dut.p0_stage_6)
$display("p0_stage_6");
if(dut.row_cmp_stage_3)
$display("row_cmp_stage_3");
//$display("p1_stage3: %d", dut.p1_stage_3);
if(push_to_adder) begin
$display("pushed to adder count: %d time: %d", adder_count, $time);
adder_count = adder_count + 1;
end
if(push_to_y) begin
$display("pushed to y count: %d", store_count);
store_count = store_count + 1;
//$finish;
end
end
`include "common.vh"
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "cmd_seq/cmd_seq.v"
`include "cmd_seq/cmd_seq_core.v"
`include "seq_rec/seq_rec.v"
`include "seq_rec/seq_rec_core.v"
`include "utils/ramb_8_to_n.v"
// `include "utils/glbl.v"
`include "utils/ODDR_sim.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/flag_domain_crossing.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam CMD_SEQ_BASEADDR = 32'h1000;
localparam CMD_SEQ_HIGHADDR = 32'h2000 - 1;
localparam SEQ_REC_BASEADDR = 32'h2000;
localparam SEQ_REC_HIGHADDR = 32'h1_3000 - 1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
localparam CMD_MEM_SIZE = 2048;
wire EX_START_PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(BUS_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire CMD_DATA;
wire CMD_EXT_START_ENABLE;
wire CMD_READY;
wire CMD_START_FLAG;
cmd_seq #(
.BASEADDR(CMD_SEQ_BASEADDR),
.HIGHADDR(CMD_SEQ_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.OUTPUTS(1),
.CMD_MEM_SIZE(CMD_MEM_SIZE)
) i_cmd_seq (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_IN(BUS_CLK),
.CMD_CLK_OUT(),
.CMD_DATA(CMD_DATA),
.CMD_EXT_START_FLAG(EX_START_PULSE),
.CMD_EXT_START_ENABLE(CMD_EXT_START_ENABLE),
.CMD_READY(CMD_READY),
.CMD_START_FLAG(CMD_START_FLAG)
);
reg EX_START_PULSE_FF, EX_START_PULSE_FF2, EX_START_PULSE_FF3, EX_START_PULSE_FF4;
always @(posedge BUS_CLK) begin
EX_START_PULSE_FF <= EX_START_PULSE;
EX_START_PULSE_FF2 <= EX_START_PULSE_FF;
EX_START_PULSE_FF3 <= EX_START_PULSE_FF2;
EX_START_PULSE_FF4 <= EX_START_PULSE_FF3;
end
reg CMD_DATA_FF;
always @(posedge BUS_CLK) begin
CMD_DATA_FF <= CMD_DATA; // delay data, SEQ_EXT_START signal hast to come first by 1 clock cycle
end
reg CMD_READY_FF, CMD_READY_FF2, CMD_READY_FF3;
always @(posedge BUS_CLK) begin
CMD_READY_FF <= CMD_READY; // delay for short pulses
CMD_READY_FF2 <= CMD_READY_FF;
CMD_READY_FF3 <= CMD_READY_FF2;
end
wire test;
assign test = (CMD_START_FLAG && (!CMD_READY_FF || !CMD_READY_FF2)) || (EX_START_PULSE_FF4 && CMD_EXT_START_ENABLE);
seq_rec #(
.BASEADDR(SEQ_REC_BASEADDR),
.HIGHADDR(SEQ_REC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(CMD_MEM_SIZE*8*4),
.IN_BITS(8)
) i_seq_rec (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START((CMD_START_FLAG && (!CMD_READY_FF || !CMD_READY_FF2)) || (EX_START_PULSE_FF4 && CMD_EXT_START_ENABLE)), // all output modes
// .SEQ_EXT_START(EX_START_PULSE_FF4 && CMD_EXT_START_ENABLE), // output mode 0
// .SEQ_EXT_START(EX_START_PULSE_FF3 && CMD_EXT_START_ENABLE), // output mode 1
.SEQ_CLK(BUS_CLK),
.SEQ_IN({7'b0, CMD_DATA_FF}) // all output modes
);
initial begin
$dumpfile("cmd_seq.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t, n; cin >> n; if (n == 0) cout << 1 << endl; else if (n % 4 == 1) cout << 8 << endl; else if (n % 4 == 2) cout << 4 << endl; else if (n % 4 == 3) cout << 2 << endl; else cout << 6 << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int m = 0, i = 0, c[100], x, y, s1 = 0, s2 = 0, ans = 0; scanf( %d , &m); for (i = 0; i < m; i++) { scanf( %d , &c[i]); s1 += c[i]; } scanf( %d%d , &x, &y); for (i = 0; i < m; i++) { s1 -= c[i]; s2 += c[i]; if ((s1 >= x) && (s1 <= y) && (s2 >= x) && (s2 <= y)) { ans = i + 2; break; } } printf( %d , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__TAP_FUNCTIONAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_FUNCTIONAL_PP_V
|
`timescale 1ns/100ps
module testbench();
reg clock, reset;
initial begin clock=0; reset=1; end
always
begin
#10;
clock = !clock;
end
//
// Instantaite RLE...
//
reg enable, arm;
reg [1:0] rle_mode;
reg [3:0] disabledGroups;
reg [31:0] dataIn;
reg validIn;
wire [31:0] dataOut;
rle_enc rle (clock, reset, enable, arm, rle_mode, disabledGroups, dataIn, validIn, dataOut, validOut);
reg [31:0] last_dataOut;
initial last_dataOut = 0;
always @ (posedge clock)
begin
#1;
if (enable && validOut)
begin
case (disabledGroups)
4'b1110 : if (dataOut[7])
$display ("%t: RLE=%d. Value=%x", $realtime, dataOut[6:0], last_dataOut[6:0]);
else
begin
$display ("%t: Value=%x", $realtime, dataOut[6:0]);
last_dataOut = dataOut;
end
4'b1100 : if (dataOut[15])
$display ("%t: RLE=%d. Value=%x", $realtime, dataOut[14:0], last_dataOut[14:0]);
else
begin
$display ("%t: Value=%x", $realtime, dataOut[14:0]);
last_dataOut = dataOut;
end
default : if (dataOut[31])
$display ("%t: RLE=%d. Value=%x", $realtime, dataOut[30:0], last_dataOut[30:0]);
else
begin
$display ("%t: Value=%x", $realtime, dataOut[30:0]);
last_dataOut = dataOut;
end
endcase
end
end
//
// Generate sequence of data...
//
task issue_block;
input [31:0] count;
input [31:0] value;
integer i;
begin
// $display ("%t: count=%d value=%08x",$realtime,count,value);
#1; dataIn = ~value; validIn = 1'b1; @(posedge clock);
for (i=0; i<count; i=i+1) begin #1; dataIn = value; validIn = 1'b1; @(posedge clock); end
end
endtask
task issue_pattern;
begin
#1; dataIn = 32'h41414141; validIn = 1'b1; @(posedge clock);
#1; dataIn = 32'h42424242; validIn = 1'b0; @(posedge clock);
#1; dataIn = 32'h43434343; validIn = 1'b1; @(posedge clock);
#1; dataIn = 32'h43434343; validIn = 1'b0; @(posedge clock);
#1; dataIn = 32'h43434343; validIn = 1'b0; @(posedge clock);
#1; dataIn = 32'h43434343; validIn = 1'b1; @(posedge clock);
issue_block(2,32'h44444444);
issue_block(3,32'h45454545);
issue_block(4,32'h46464646);
issue_block(8,32'h47474747);
issue_block(16,32'h48484848);
issue_block(32,32'h49494949);
issue_block(64,32'h4A4A4A4A);
issue_block(128,32'h4B4B4B4B);
issue_block(129,32'h4C4C4C4C);
issue_block(130,32'h4D4D4D4D);
issue_block(131,32'h4E4E4E4E);
issue_block(256,32'h4F4F4F4F);
issue_block(512,32'h50505050);
issue_block(1024,32'h51515151);
issue_block(2048,32'h52525252);
issue_block(4096,32'h53535353);
issue_block(8192,32'h54545454);
issue_block(16384,32'h55555555);
issue_block(32768,32'h56565656);
issue_block(65536,32'h57575757);
repeat (10) begin #1; dataIn = 32'hFFFFFFFF; validIn = 1'b0; @(posedge clock); end
end
endtask
//
// Generate test sequence...
//
initial
begin
enable = 0;
arm = 1;
repeat (10) @(posedge clock);
reset = 0;
rle_mode = 0;
disabledGroups = 4'b1110; // 8'bit mode
repeat (10) @(posedge clock);
issue_pattern();
repeat (10) @(posedge clock);
enable = 1; // turn on RLE...
repeat (10) @(posedge clock);
fork
begin
issue_pattern();
end
begin
repeat (48000) @(posedge clock);
#1 enable = 0;
end
join
repeat (10) @(posedge clock);
$finish;
end
//
// Initialized wavedump...
//
reg [0:511] targetsst[0:0];
reg gotsst;
integer i;
initial
begin
$timeformat (-9,1," ns",0);
$display ("%t: Starting wave dump...",$realtime);
$dumpfile ("waves.dump");
$dumpvars(0);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O41AI_BEHAVIORAL_PP_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; constexpr int N = 5e5 + 5; vector<int> elm[N]; struct SegTree { struct Dat { int l, r; Dat *lc, *rc; long long lmx, rmx, mx, sum; int len() { return r - l + 1; } void fset(long long kval) { lmx = rmx = mx = sum = kval; } void pushup() { lmx = max(lc->lmx, lc->sum + rc->lmx); rmx = max(rc->rmx, rc->sum + lc->rmx); mx = max({lc->mx, rc->mx, lc->rmx + rc->lmx}); sum = lc->sum + rc->sum; } void pushdown() {} } dat[N << 2]; int siz = 0; void init(int n) { function<Dat *(int, int)> build = [&](int l, int r) { Dat &nw = dat[siz++]; nw = {l, r}; if (l == r) { } else { int mid = (l + r) >> 1; nw.lc = build(l, mid), nw.rc = build(mid + 1, r); nw.pushup(); } return &nw; }; build(1, n); } template <typename Fn> void travsal(int l, int r, Fn f) { function<void(Dat &)> trav = [&](Dat &p) { if (r < p.l || l > p.r) return; if (p.l >= l && p.r <= r) { return f(p); } else { p.pushdown(); int mid = (l + r) >> 1; trav(*p.lc); trav(*p.rc); p.pushup(); } }; trav(dat[0]); } void update(int x, long long val) { travsal(x, x, [&](Dat &e) { e.fset(val); }); } int query() { return dat[0].mx; } } seg; int a[N]; int main() { ios::sync_with_stdio(false); int n, c; cin >> n >> c; seg.init(n); int base = 0; for (int i = 1; i < n + 1; i++) { cin >> a[i]; if (a[i] == c) seg.update(i, -1), base++; else elm[a[i]].push_back(i); } int ans = base; for (int i = 1; i < N; i++) { if (elm[i].empty()) continue; for (int pos : elm[i]) seg.update(pos, 1); ans = max(ans, base + seg.query()); for (int pos : elm[i]) seg.update(pos, 0); } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int n; set<string> s; int main() { cin >> n; getchar(); while (n--) { string ss; getline(cin, ss); s.insert(ss); } cout << s.size(); return 0; }
|
module CacheDelay(clk, sigIn, waitCnt, sigOut);
/***
This delay works by caching a large number of signal inputs on clock (pos) edges, and selecting where in the time series to output based on the requested delay. The last element in the cache is popped, and the first (zeroth) element pushed, on every clock cycle.
Ted Golfinopoulos, 19 Sep 2012
***/
parameter WAIT_CNT_SIZE=12; //Cache must have same number of bits as maximum number in wait counter.
parameter CACHE_SIZE=2048;
//Make a huge cache.
reg [CACHE_SIZE-1:0] cache;
input [WAIT_CNT_SIZE-1:0] waitCnt;
input clk;
input sigIn;
output sigOut;
reg sigOutReg;
initial begin
#0
cache=1'b0; //Reset cache.
end
always @(posedge clk) begin
cache={cache[CACHE_SIZE-2:0],sigIn}; //Pop out oldest data point, and push newest data point.
end
assign sigOut=cache[waitCnt]; //Look up Index, waitCnt, in cache.
endmodule
//module CacheDelay(clk, sigIn, waitCnt, sigOut, diagOut);
//output diagOut;
//Try a shift operation
//cache=(cache<<1)+sigIn;
//assign diagOut=cache[3]; //Diagnostic out
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 100010; long long n, m, k, x, y, z, a, b, c, t1, t2, cnt, p; long long X[MAXN]; long long Y[MAXN]; bool X2[MAXN]; bool Y2[MAXN]; long long powmod(long long a, long long b) { if (!b) return 1; if (b & 1) return a * powmod(a, b - 1) % p; return powmod(a * a % p, b >> 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> k; if ((m ^ n) & 1) return cout << 0 << n , 0; ; for (int i = 0; i < k; i++) { cin >> a >> b >> c; X[a]++; Y[b]++; if (c == -1) { X2[a] ^= 1; Y2[b] ^= 1; } } for (int i = 1; i <= n; i++) if (X[i] == m) { if (!X2[i]) return cout << 0 << n , 0; ; t1++; } for (int i = 1; i <= m; i++) if (Y[i] == n) { if (!Y2[i]) return cout << 0 << n , 0; ; t2++; } cnt = (n - t1 - 1) * (m - t2 - 1) - (k - t1 * m - t2 * n + t1 * t2); cin >> p; cout << powmod(2, cnt) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_2_V
`define SKY130_FD_SC_HDLL__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_2_V
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e5 + 10, MOD = 1e9 + 7; long long n, T, ni[MAXN], jie[MAXN], jie_ni[MAXN], A[MAXN], ans, sum; long long sum_N, sum_K; void Init() { ni[1] = 1; for (long long i = 2; i <= MAXN - 10; i++) { ni[i] = ((MOD - (MOD / i)) * ni[MOD % i] % MOD) % MOD; } jie_ni[0] = 1; for (long long i = 1; i <= MAXN - 10; i++) { jie_ni[i] = jie_ni[i - 1] * ni[i] % MOD; } jie[0] = 1; for (long long i = 1; i <= MAXN - 10; i++) { jie[i] = jie[i - 1] * i % MOD; } } long long Quick(long long x, long long y) { long long res = 1, a = x; while (y) { if (y & 1) res *= a, res %= MOD; a = a * a, a %= MOD; y /= 2; } return res; } long long C(long long x, long long y) { if (y == 0) return 1; if (x == y) return 1; return (jie[x] * jie_ni[y]) % MOD * jie_ni[x - y] % MOD; } long long work(long long N, long long K) { if (sum_N == 0) { sum_N = 1; for (long long i = 1; i <= K; i++) sum_N += C(N, i), sum_N %= MOD; sum_K = K; return sum_N; } else { sum_N = (sum_N * 2 - C(N - 1, sum_K) + MOD) % MOD; for (long long i = sum_K; i >= K + 1; i--) { sum_N -= C(N, i), sum_N = (sum_N + MOD) % MOD; } sum_K = K; return sum_N; } } signed main() { cin >> n >> T; Init(); for (long long i = 1; i <= n; i++) cin >> A[i]; long long BASE = 1; for (long long i = 1; i <= n; i++) { sum += A[i]; BASE = BASE * 2; BASE %= MOD; if (T - sum >= i) { ans++; ans %= MOD; } else if (T - sum < 0) { break; } else { ans += (work(i, T - sum) * Quick(BASE, MOD - 2)) % MOD; ans %= MOD; } } cout << ans; return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
//
//
//===----------------------------------------------------------------------===//
module acl_stall_monitor #(NODES=32) (
input clock,
input resetn,
input [NODES-1:0] valid,
input [NODES-1:0] stall_in,
input [NODES-1:0] stall_out,
output [32*NODES-1:0] stall_count
);
reg [31:0] stall_count_mem[NODES-1:0];
generate
genvar i;
for (i=0; i<NODES; i=i+1)
begin : node_gen
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
stall_count_mem[i] <= 32'h0;
end
else
begin
if ( valid[i] && stall_out[i] && !stall_in[i])
stall_count_mem[i] <= stall_count_mem[i] + 2'h01;
end
end
assign stall_count[i] = stall_count_mem[i];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> int n, m, sol; int D[100005]; int main() { scanf( %d %d , &n, &m); int p = 1; for (int i = 1; i <= m; ++i) { p = p + p; if (p >= 1000000009) p -= 1000000009; } D[1] = p - 1; for (int i = 2; i <= n; ++i) { int now = p - i; if (now < 0) now += 1000000009; D[i] = (1LL * D[i - 1] * now) % 1000000009; } printf( %d n , D[n]); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Thu Jun 22 05:51:07 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../highlow.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.3 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: ent_b.v,v $
// Revision 1.3 2006/06/22 07:20:00 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using pll = pair<ll, ll>; using pil = pair<int, ll>; using pli = pair<ll, int>; using vs = vector<string>; using vvs = vector<vs>; using vvvs = vector<vvs>; using vb = vector<bool>; using vvb = vector<vb>; using vvvb = vector<vvb>; using vi = vector<int>; using vvi = vector<vi>; using vvvi = vector<vvi>; using vl = vector<ll>; using vvl = vector<vl>; using vvvl = vector<vvl>; using vd = vector<double>; using vvd = vector<vd>; using vvvd = vector<vvd>; using vpii = vector<pii>; using vvpii = vector<vpii>; using vvvpii = vector<vvpii>; template <class T> bool amax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool amin(T &a, const T &b) { if (b < a) { a = b; return 1; } return 0; } ll ri() { ll l; cin >> l; return l; } string rs() { string s; cin >> s; return s; } template <class T> T read() { T t; cin >> t; return t; } template <class T, class U> ostream &operator<<(ostream &o, const pair<T, U> &p) { return o << ( << p.first << , << p.second << ) ; } ostream &operator<<(ostream &o, const vb &t) { for (auto &&e : t) o << #. [e]; return o; } template <class T> ostream &operator<<(ostream &o, const vector<T> &t) { o << { ; for (auto &&e : t) o << e << , ; o << } << endl; return o; } void panic() { cout << NO << endl; exit(0); } string solve() { int n = ri(); int k = ri(); auto s = rs(); int w = 0, l = 0, d = 0, u = 0; for (auto &&c : s) { if (c == W ) w++; else if (c == L ) l++; else if (c == D ) d++; else if (c == ? ) u++; } vvi dp(n + 1, vi(2 * k + 1)); vvi fp(n + 1, vi(2 * k + 1)); if (s[n - 1] == D ) { panic(); } if (s[n - 1] == W || s[n - 1] == ? ) { dp[n][k + k] = 1; } if (s[n - 1] == L || s[n - 1] == ? ) { dp[n][0] = 1; } for (int i = int(n) - 1; i >= int(0); i--) for (int j = int(1); j < int(2 * k); ++j) { char r = s[i]; if (r == W || r == ? ) { if (amax(dp[i][j], dp[i + 1][j + 1])) { fp[i][j] = j + 1; } } if (r == L || r == ? ) { if (amax(dp[i][j], dp[i + 1][j - 1])) { fp[i][j] = j - 1; } } if (r == D || r == ? ) { if (amax(dp[i][j], dp[i + 1][j])) { fp[i][j] = j; } } }; ; if (dp[0][k] == 0) panic(); vi A; { int x = k; for (int i = int(0); i < int(n + 1); ++i) { A.emplace_back(x); x = fp[i][x]; } }; string ans; for (int i = int(0); i < int(n); ++i) { if (A[i] == A[i + 1]) ans += D ; else if (A[i] > A[i + 1]) ans += L ; else if (A[i] < A[i + 1]) ans += W ; }; ; for (int i = int(0); i < int(n); ++i) { assert(s[i] == ? || ans[i] == s[i]); } return ans; } void Main() { cout << solve() << endl; } int main() { cin.tie(nullptr); ios::sync_with_stdio(false); Main(); return 0; }
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#include <bits/stdc++.h> int main() { char a[8][8]; char x, y; int i, j, b = 0; for (i = 0; i < 8; i++) for (j = 0; j < 8; j++) a[i][j] = 1; scanf( %c%c , &x, &y); x -= a ; y -= 1 ; a[x][y] = 0; for (i = 0; i < 8; i++) { a[x][i] = 0; a[i][y] = 0; } if (x >= 2 && y >= 1) a[x - 2][y - 1] = 0; if (x >= 1 && y >= 2) a[x - 1][y - 2] = 0; if (x >= 2 && y <= 6) a[x - 2][y + 1] = 0; if (x >= 1 && y <= 5) a[x - 1][y + 2] = 0; if (x <= 5 && y >= 1) a[x + 2][y - 1] = 0; if (x <= 6 && y >= 2) a[x + 1][y - 2] = 0; if (x <= 5 && y <= 6) a[x + 2][y + 1] = 0; if (x <= 6 && y <= 5) a[x + 1][y + 2] = 0; while (1) { scanf( %c , &x); if (x == n ) break; } scanf( %c%c , &x, &y); x -= a ; y -= 1 ; a[x][y] = 0; if (x >= 2 && y >= 1) a[x - 2][y - 1] = 0; if (x >= 1 && y >= 2) a[x - 1][y - 2] = 0; if (x >= 2 && y <= 6) a[x - 2][y + 1] = 0; if (x >= 1 && y <= 5) a[x - 1][y + 2] = 0; if (x <= 5 && y >= 1) a[x + 2][y - 1] = 0; if (x <= 6 && y >= 2) a[x + 1][y - 2] = 0; if (x <= 5 && y <= 6) a[x + 2][y + 1] = 0; if (x <= 6 && y <= 5) a[x + 1][y + 2] = 0; for (i = 0; i < 8; i++) for (j = 0; j < 8; j++) b += a[i][j]; printf( %d , b); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 1ll; long long lim = 0, Ans = 0; struct Plan { long long pos; long long c, p; } a[N]; struct Tree { long long c, p; Tree() { c = p = 0; }; } t[N << 2ll]; struct Acht { long long a, b; Acht() { a = b = 0; }; }; bool ctrl(Plan u, Plan v) { return u.pos < v.pos; } inline void pushup(long long u) { t[u].c = t[u << 1ll].c + t[u << 1ll | 1ll].c; t[u].p = t[u << 1ll].p + t[u << 1ll | 1ll].p; } void update(long long u, long long l, long long r, long long pos) { if (l == r && l == a[pos].p) { t[u].c += a[pos].c; t[u].p += a[pos].c * a[pos].p; return; } long long mid = (l + r) >> 1ll; if (a[pos].p <= mid) update(u << 1ll, l, mid, pos); else update(u << 1ll | 1ll, mid + 1ll, r, pos); pushup(u); } Acht query(long long u, long long l, long long r, long long rnk) { if (l == r) { Acht res; if (rnk == t[u].c) res.a = l; else res.a = l - 1ll, res.b = l * rnk; return res; } if (t[u].c == rnk) { Acht res; res.a = r; return res; } long long mid = (l + r) >> 1ll; if (t[u << 1ll].c >= rnk) return query(u << 1ll, l, mid, rnk); return query(u << 1ll | 1ll, mid + 1ll, r, rnk - t[u << 1ll].c); } long long query(long long u, long long l, long long r, long long a, long long b) { if (a <= l && r <= b) return t[u].p; long long mid = (l + r) >> 1ll; long long res = 0; if (a <= mid) res += query(u << 1ll, l, mid, a, b); if (b > mid) res += query(u << 1ll | 1ll, mid + 1ll, r, a, b); return res; } signed main() { long long n, k, m; scanf( %lld%lld%lld , &n, &k, &m); for (long long i = 1ll; i <= m; ++i) { long long y = i << 1ll, x = y - 1ll; scanf( %lld%lld%lld%lld , &a[x].pos, &a[y].pos, &a[x].c, &a[x].p); a[y].pos++, a[y].c = -a[x].c, a[y].p = a[x].p; lim = max(lim, a[x].p); } sort(a + 1ll, a + (m << 1ll | 1ll), ctrl); update(1ll, 1ll, lim, 1ll); for (long long i = 2; i <= (m << 1ll); ++i) { long long itv = a[i].pos - a[i - 1ll].pos; if (t[1ll].c <= k) Ans += t[1ll].p * itv; else { Acht tmp = query(1ll, 1ll, lim, k); long long res = tmp.b; if (tmp.a) res += query(1ll, 1ll, lim, 1ll, tmp.a); Ans += res * itv; } update(1ll, 1ll, lim, i); } printf( %lld , Ans); return 0; }
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#include <bits/stdc++.h> template <typename Y> inline bool updmin(Y &a, Y b) { if (a > b) { a = b; return 1; } return 0; } template <typename Y> inline bool updmax(Y &a, Y b) { if (a < b) { a = b; return 1; } return 0; } template <typename Y> inline Y abs(Y a) { if (a < 0) a = -a; return a; } template <typename Y> inline Y sqr(Y a) { return a * a; } int read() { int w = 1, q = 0, ch = ; for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) w = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) q = q * 10 + ch - 48; return q * w; } inline void FileIO() { freopen( .in , r , stdin); freopen( .out , w , stdout); } int n, m, h; const int N = 100020; std::vector<int> G[N], s; int tim = 0, cnt = 0; int low[N], dfn[N], vis[N], bel[N]; void tarjan(int p) { vis[p] = 1; s.push_back(p); low[p] = dfn[p] = ++tim; for (int t : G[p]) { if (!dfn[t]) { tarjan(t); updmin(low[p], low[t]); } else if (vis[t]) { updmin(low[p], dfn[t]); } } if (low[p] == dfn[p]) { ++cnt; while (s.back() != p) { int cur = s.back(); s.pop_back(); vis[cur] = 0; bel[cur] = cnt; } bel[p] = cnt; vis[p] = 0; s.pop_back(); } } int u[N], size[N], out[N]; int main() { n = read(); m = read(); h = read(); for (int i = 1; i <= n; i++) { u[i] = read(); } for (int i = 1; i <= m; i++) { int x = read(), y = read(); if ((u[x] + 1) % h == u[y]) { G[x].push_back(y); } if ((u[y] + 1) % h == u[x]) { G[y].push_back(x); } } for (int i = 1; i <= n; i++) { if (!dfn[i]) { tarjan(i); } } for (int i = 1; i <= n; i++) { size[bel[i]]++; for (int j : G[i]) { if (bel[i] != bel[j]) { out[bel[i]]++; } } } int ans = n + 1, pos = 0; for (int i = 1; i <= cnt; i++) { if (!out[i] && updmin(ans, size[i])) { pos = i; } } printf( %d n , ans); for (int i = 1; i <= n; i++) { if (bel[i] == pos) { printf( %d , i); } } return 0; }
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//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_mux.v
//
// *Module Description:
// Standard clock mux for the openMSP430
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_clock_mux (
// OUTPUTs
clk_out, // Clock output
// INPUTs
clk_in0, // Clock input 0
clk_in1, // Clock input 1
reset, // Reset
scan_mode, // Scan mode (clk_in0 is selected in scan mode)
select // Clock selection
);
// OUTPUTs
//=========
output clk_out; // Clock output
// INPUTs
//=========
input clk_in0; // Clock input 0
input clk_in1; // Clock input 1
input reset; // Reset
input scan_mode; // Scan mode (clk_in0 is selected in scan mode)
input select; // Clock selection
//===========================================================================================================================//
// 1) CLOCK MUX //
//===========================================================================================================================//
// //
// The following (glitch free) clock mux is implemented as following: //
// //
// //
// //
// //
// +-----. +--------+ +--------+ //
// select >>----+-------------O| \ | | | | +-----. //
// | | |---| D Q |---| D Q |--+-------| \ //
// | +-------O| / | | | | | | |O-+ //
// | | +-----' | | | | | +--O| / | //
// | | | /\ | | /\ | | | +-----' | //
// | | +--+--+--+ +--+--+--+ | | | //
// | | O | | | | //
// | | | | | | | +-----. //
// clk_in0 >>----------------------------------+------------+-----------+ +--| \ //
// | | | | |----<< clk_out //
// | | +---------------------------------------+ +--| / //
// | | | | +-----' //
// | +---------------------------------------------+ | //
// | | | | //
// | | +-----. +--------+ +--------+ | | //
// | +-O| \ | | | | | +-----. | //
// | | |---| D Q |---| D Q |--+-------| \ | //
// +--------------| / | | | | | |O-+ //
// +-----' | | | | +--O| / //
// | /\ | | /\ | | +-----' //
// +--+--+--+ +--+--+--+ | //
// O | | //
// | | | //
// clk_in1 >>----------------------------------+------------+-----------+ //
// //
// //
//===========================================================================================================================//
//-----------------------------------------------------------------------------
// Wire declarations
//-----------------------------------------------------------------------------
wire in0_select;
reg in0_select_s;
reg in0_select_ss;
wire in0_enable;
wire in1_select;
reg in1_select_s;
reg in1_select_ss;
wire in1_enable;
wire clk_in0_inv;
wire clk_in1_inv;
wire gated_clk_in0;
wire gated_clk_in1;
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
//-----------------------------------------------------------------------------
assign in0_select = ~select & ~in1_select_ss;
always @ (posedge clk_in0_inv or posedge reset)
if (reset) in0_select_s <= 1'b1;
else in0_select_s <= in0_select;
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1'b1;
else in0_select_ss <= in0_select_s;
assign in0_enable = in0_select_ss | scan_mode;
//-----------------------------------------------------------------------------
// CLK_IN1 Selection
//-----------------------------------------------------------------------------
assign in1_select = select & ~in0_select_ss;
always @ (posedge clk_in1_inv or posedge reset)
if (reset) in1_select_s <= 1'b0;
else in1_select_s <= in1_select;
always @ (posedge clk_in1 or posedge reset)
if (reset) in1_select_ss <= 1'b0;
else in1_select_ss <= in1_select_s;
assign in1_enable = in1_select_ss & ~scan_mode;
//-----------------------------------------------------------------------------
// Clock MUX
//-----------------------------------------------------------------------------
//
// IMPORTANT NOTE:
// Because the clock network is a critical part of the design,
// the following combinatorial logic should be replaced with
// direct instanciation of standard cells from target library.
// Don't forget the "dont_touch" attribute to make sure
// synthesis won't mess it up.
//
// Replace with standard cell INVERTER
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
// Replace with standard cell AND2
assign clk_out = (gated_clk_in0 & gated_clk_in1);
endmodule // omsp_clock_gate
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#include<bits/stdc++.h> #define ll long long int #define mod 1000000007 using namespace std; int main() { int t; cin>>t; while(t--) { int n; cin>>n; int A[n]; for(int i=0;i<n;i++) { cin>>A[i]; } bool flag=true; for(int i=0;i<n;i++) if(A[i]!=i+1) {flag=false; break;} if(flag) cout<< 0 <<endl; else if((A[0]==1)||(A[n-1]==n)) cout<< 1 <<endl; else if((A[0]==n)&&(A[n-1]==1)) cout<< 3 <<endl; else cout<< 2 <<endl; } }
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#include <bits/stdc++.h> using namespace std; long long int nextAlice[7][7]; long long int nextBob[7][7]; long long int nodeNum[7][7]; pair<long long int, long long int> curScore; pair<long long int, long long int> cycScore; pair<long long int, long long int> gameScore(long long int x, long long int y) { if (x == y) return make_pair(0, 0); if ((x == 3 && y == 2) || (x == 2 && y == 1) || (x == 1 && y == 3)) return make_pair(1, 0); if ((y == 3 && x == 2) || (y == 2 && x == 1) || (y == 1 && x == 3)) return make_pair(0, 1); } void addPair(pair<long long int, long long int> x) { curScore.first += x.first; curScore.second += x.second; } void addPairCyc(pair<long long int, long long int> x) { cycScore.first += x.first; cycScore.second += x.second; } int main() { long long int i, j, k, l, m, n, x, y, z, a, b, r, curnode, curAlice, curBob, tx, ty; scanf( %lld , &k); scanf( %lld , &a); scanf( %lld , &b); for (i = 1; i <= 3; i++) for (j = 1; j <= 3; j++) scanf( %lld , &nextAlice[i][j]); for (i = 1; i <= 3; i++) for (j = 1; j <= 3; j++) scanf( %lld , &nextBob[i][j]); curnode = 1; curAlice = a; curBob = b; while (nodeNum[curAlice][curBob] == 0) { x = curAlice; y = curBob; nodeNum[x][y] = curnode++; curAlice = nextAlice[x][y]; curBob = nextBob[x][y]; } x = curAlice; y = curBob; l = curnode - nodeNum[x][y]; i = 0; curAlice = a; curBob = b; while (!(curAlice == x && curBob == y)) { tx = curAlice; ty = curBob; i++; if (i > k) { printf( %lld %lld n , curScore.first, curScore.second); return 0; } addPair(gameScore(curAlice, curBob)); curAlice = nextAlice[tx][ty]; curBob = nextBob[tx][ty]; } k = k - i; bool flag = true; curAlice = x; curBob = y; while (flag || !(curAlice == x && curBob == y)) { flag = false; tx = curAlice; ty = curBob; addPairCyc(gameScore(curAlice, curBob)); curAlice = nextAlice[tx][ty]; curBob = nextBob[tx][ty]; } addPair(make_pair(k / l * cycScore.first, k / l * cycScore.second)); k = k % l; curAlice = x; curBob = y; while (k > 0) { tx = curAlice; ty = curBob; addPair(gameScore(curAlice, curBob)); curAlice = nextAlice[tx][ty]; curBob = nextBob[tx][ty]; k--; } printf( %lld %lld n , curScore.first, curScore.second); return 0; }
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`timescale 1 ns / 1 ps
module pwm_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire pwm_out,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
pwm_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) pwm_v1_0_S00_AXI_inst (
.pwm_out(pwm_out),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int i, j, k; int n, m, idx; string s, s2; cin >> s; n = s.length(); int cnt = 0; for (i = 0; i < n; i++) { if (s[i] == a ) cnt++; } k = 0; idx = 0; for (i = 0; i < n; i++) { if (k == cnt) break; if (s[i] == a ) k++, idx = i + 1; else s2.push_back(s[i]); } k = n - idx; k -= s2.length(); if (k % 2 == 0) { k /= 2; j = idx; idx += k; while (k > 0) { s2.push_back(s[j]); j++; k--; } k = s.length() - 1; for (i = s2.length() - 1; i >= 0; i--) { if (s2[i] != s[k]) { cout << :( ; return 0; } k--; } for (i = 0; i < idx; i++) cout << s[i]; } else cout << :( ; return 0; }
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#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); } void online_judge() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } const int flag_max = 0x3f3f3f3f; const long long OO = 1e9; const double EPS = (1e-7); int dcmp(double x, double y) { return fabs(x - y) <= EPS ? 0 : x < y ? -1 : 1; } long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } int n, p; int F = 0; map<pair<int, int>, bool> check; vector<pair<int, int>> pa_ir; void dfs(int star) { for (int i = star + 1; i <= n; i++) { if (!check[{star, i}]) { F++; check[{star, i}] = 1; check[{i, star}] = 1; pa_ir.push_back({star, i}); dfs(i); } } } int main() { fast(); int t; cin >> t; while (t--) { cin >> n >> p; p = 2 * n + p; pa_ir.clear(); check.clear(); dfs(1); sort(((pa_ir).begin()), ((pa_ir).end())); for (int i = 0; i < p; i++) { cout << pa_ir[i].first << << pa_ir[i].second << n ; } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_2_V
`define SKY130_FD_SC_HD__DLXBN_2_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxbn_2 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxbn_2 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_2_V
|
// File: MUX4_1_MS_TBV.v
// Generated by MyHDL 0.10
// Date: Sun Sep 23 18:20:41 2018
`timescale 1ns/10ps
module MUX4_1_MS_TBV (
);
// myHDL -> Verilog testbench for module `MUX4_1_MS`
reg x0 = 0;
reg x1 = 0;
wire y;
reg x2 = 0;
reg x3 = 0;
reg s0 = 0;
reg s1 = 0;
wire [68:0] x0TV;
wire [68:0] x1TV;
wire [68:0] x2TV;
wire [68:0] x3TV;
wire [68:0] s0TV;
wire [68:0] s1TV;
wire MUX4_1_MS0_0_x0x1_yWire;
wire MUX4_1_MS0_0_MUX2_1_Combo1_0_1_y;
assign x0TV = 69'd2296870857426870268;
assign x1TV = 69'd34723282962276803050;
assign x2TV = 69'd118059162071741130356;
assign x3TV = 69'd196765270119568550582;
assign s0TV = 69'd137438953451;
assign s1TV = 69'd9007061817884663;
always @(x0, x3, s0, x2, y, x1, s1) begin: MUX4_1_MS_TBV_PRINT_DATA
$write("%h", x0);
$write(" ");
$write("%h", x1);
$write(" ");
$write("%h", x2);
$write(" ");
$write("%h", x3);
$write(" ");
$write("%h", s0);
$write(" ");
$write("%h", s1);
$write(" ");
$write("%h", y);
$write("\n");
end
assign MUX4_1_MS0_0_x0x1_yWire = (((!s0) && x0) | (s0 && x1));
assign MUX4_1_MS0_0_MUX2_1_Combo1_0_1_y = (((!s0) && x2) | (s0 && x3));
assign y = (((!s1) && MUX4_1_MS0_0_x0x1_yWire) | (s1 && MUX4_1_MS0_0_MUX2_1_Combo1_0_1_y));
initial begin: MUX4_1_MS_TBV_STIMULES
integer i;
for (i=0; i<69; i=i+1) begin
x0 <= x0TV[i];
x1 <= x1TV[i];
x2 <= x2TV[i];
x3 <= x3TV[i];
s0 <= s0TV[i];
s1 <= s1TV[i];
# 1;
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int blk_size; struct node { int l, r, id; long long int ans = 0; }; bool compare(node a, node b) { if (a.l / blk_size != b.l / blk_size) return (a.l) / blk_size < (b.l) / blk_size; return a.r < b.r; } bool compare2(node a, node b) { return a.id < b.id; } long long int freq[3000001]; int main() { ios_base::sync_with_stdio(false); ; int n, m, k; cin >> n >> m >> k; std::vector<int> a(n), pxor(n + 1); for (int i = 0; i < n; i++) cin >> a[i]; pxor[0] = 0; for (int i = 1; i <= n; i++) pxor[i] = pxor[i - 1] ^ a[i - 1]; blk_size = sqrt(n + 1); std::vector<node> q(m); for (int i = 0; i < m; i++) { cin >> q[i].l >> q[i].r; q[i].id = i; } sort(q.begin(), q.end(), compare); int start = 0, end = 0; long long int ans = 0; freq[0] = 1; for (int i = 0; i < m; i++) { int l = q[i].l - 1, r = q[i].r; while (start > l) { start--; ans += freq[pxor[start] ^ k]; freq[pxor[start]]++; } while (start < l) { freq[pxor[start]]--; ans -= freq[pxor[start] ^ k]; start++; } while (end > r) { freq[pxor[end]]--; ans -= freq[pxor[end] ^ k]; end--; } while (end < r) { end++; ans += freq[pxor[end] ^ k]; freq[pxor[end]]++; } q[i].ans = ans; } sort(q.begin(), q.end(), compare2); for (int i = 0; i < m; i++) cout << q[i].ans << n ; return 0; }
|
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