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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
`define SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2B_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_SYMBOL_V
`define SKY130_FD_SC_HS__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
// Sixth order IIR filter //////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module IIR6_32bit_fixed (audio_out, audio_in,
scale,
b1, b2, b3, b4, b5, b6, b7,
a2, a3, a4, a5, a6, a7,
clk, data_val, rst, audio_out_val);
// The filter is a "Direct Form II Transposed"
//
// a(1)*y(n) = b(1)*x(n) + b(2)*x(n-1) + ... + b(nb+1)*x(n-nb)
// - a(2)*y(n-1) - ... - a(na+1)*y(n-na)
//
// If a(1) is not equal to 1, FILTER normalizes the filter
// coefficients by a(1).
//
// one audio sample, 16 bit, 2's complement
output reg signed [31:0] audio_out;
output reg signed audio_out_val;
// one audio sample, 16 bit, 2's complement
input wire signed [31:0] audio_in;
// shift factor for output
input wire [2:0] scale;
// filter coefficients
input wire signed [31:0] b1, b2, b3, b4, b5, b6, b7, a2, a3, a4, a5, a6, a7;
input wire clk, data_val, rst;
/// filter vars
wire signed [31:0] f1_mac_new, f1_coeff_x_value;
reg signed [31:0] f1_coeff, f1_mac_old, f1_value;
// input to filter
reg signed [31:0] x_n;
// input history x(n-1), x(n-2)
reg signed [31:0] x_n1, x_n2, x_n3, x_n4, x_n5, x_n6;
// output history: y_n is the new filter output, BUT it is
// immediately stored in f1_y_n1 for the next loop through
// the filter state machine
reg signed [31:0] f1_y_n1, f1_y_n2, f1_y_n3, f1_y_n4, f1_y_n5, f1_y_n6;
// MAC operation
signed_mult f1_c_x_v (.out(f1_coeff_x_value), .a(f1_coeff), .b(f1_value));
assign f1_mac_new = f1_mac_old + f1_coeff_x_value;
// state variable
reg [3:0] state;
///////////////////////////////////////////////////////////////////
//Run the filter state machine FAST so that it completes in one
//audio cycle
always @ (posedge clk)
begin
if (rst) begin
state <= 4'd15; //turn off the state machine
f1_value <= 0;
f1_coeff <= 0;
f1_mac_old <= 0;
x_n <= 0;
x_n1 <= 0;
x_n2 <= 0;
x_n3 <= 0;
x_n4 <= 0;
x_n5 <= 0;
x_n6 <= 0;
f1_y_n1 <= 0;
f1_y_n2 <= 0;
f1_y_n3 <= 0;
f1_y_n4 <= 0;
f1_y_n5 <= 0;
f1_y_n6 <= 0;
audio_out_val <= 0;
end
else begin
case (state)
1:
begin
// set up b1*x(n)
f1_mac_old <= 32'd0;
f1_coeff <= b1;
f1_value <= (audio_in >>> 1);
//register input
x_n <= (audio_in >>> 1);
// next state
state <= 4'd2;
end
2:
begin
// set up b2*x(n-1)
f1_mac_old <= f1_mac_new;
f1_coeff <= b2;
f1_value <= x_n1;
// next state
state <= 4'd3;
end
3:
begin
// set up b3*x(n-2)
f1_mac_old <= f1_mac_new;
f1_coeff <= b3;
f1_value <= x_n2;
// next state
state <= 4'd4;
end
4:
begin
// set up b4*x(n-3)
f1_mac_old <= f1_mac_new;
f1_coeff <= b4;
f1_value <= x_n3;
// next state
state <= 4'd5;
end
5:
begin
// set up b5*x(n-4)
f1_mac_old <= f1_mac_new;
f1_coeff <= b5;
f1_value <= x_n4;
// next state
state <= 4'd6;
end
6:
begin
// set up b6*x(n-5)
f1_mac_old <= f1_mac_new;
f1_coeff <= b6;
f1_value <= x_n5;
// next state
state <= 4'd7;
end
7:
begin
// set up b7*x(n-6)
f1_mac_old <= f1_mac_new;
f1_coeff <= b7;
f1_value <= x_n6;
// next state
state <= 4'd8;
end
8:
begin
// set up -a2*y(n-1)
f1_mac_old <= f1_mac_new;
f1_coeff <= a2;
f1_value <= f1_y_n1;
//next state
state <= 4'd9;
end
9:
begin
// set up -a3*y(n-2)
f1_mac_old <= f1_mac_new;
f1_coeff <= a3;
f1_value <= f1_y_n2;
//next state
state <= 4'd10;
end
4'd10:
begin
// set up -a4*y(n-3)
f1_mac_old <= f1_mac_new;
f1_coeff <= a4;
f1_value <= f1_y_n3;
//next state
state <= 4'd11;
end
4'd11:
begin
// set up -a5*y(n-4)
f1_mac_old <= f1_mac_new;
f1_coeff <= a5;
f1_value <= f1_y_n4;
//next state
state <= 4'd12;
end
4'd12:
begin
// set up -a6*y(n-5)
f1_mac_old <= f1_mac_new;
f1_coeff <= a6;
f1_value <= f1_y_n5;
//next state
state <= 4'd13;
end
13:
begin
// set up -a7*y(n-6)
f1_mac_old <= f1_mac_new;
f1_coeff <= a7;
f1_value <= f1_y_n6;
//next state
state <= 4'd14;
end
14:
begin
// get the output
// and put it in the LAST output var
// for the next pass thru the state machine
//mult by four because of coeff scaling
// to prevent overflow
f1_y_n1 <= f1_mac_new<<scale;
audio_out <= f1_y_n1;
audio_out_val <= 1'b1;
// update output history
f1_y_n2 <= f1_y_n1;
f1_y_n3 <= f1_y_n2;
f1_y_n4 <= f1_y_n3;
f1_y_n5 <= f1_y_n4;
f1_y_n6 <= f1_y_n5;
// update input history
x_n1 <= x_n;
x_n2 <= x_n1;
x_n3 <= x_n2;
x_n4 <= x_n3;
x_n5 <= x_n4;
x_n6 <= x_n5;
//next state
state <= 4'd15;
end
15:
begin
// wait for data valid signal
audio_out_val <= 1'b0;
if (data_val)
begin
state <= 4'd1;
end
end
default:
begin
// default state is end state
state <= 4'd15;
end
endcase
end
end
endmodule
///////////////////////////////////////////////////
//// signed mult of 2.30 format 2'comp ////////////
///////////////////////////////////////////////////
module signed_mult (out, a, b);
output [31:0] out;
input signed [31:0] a;
input signed [31:0] b;
wire signed [31:0] out;
wire signed [63:0] mult_out;
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[63], mult_out[59:30]};
endmodule
//////////////////////////////////////////////////
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_SRAM_inputs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 14: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 14: 0] data_out;
wire [ 14: 0] out_port;
wire [ 14: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {15 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[14 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 10.1.03
// \ \ Application : xaw2verilog
// / / Filename : FB_MULT_ADD.v
// /___/ /\ Timestamp : 06/27/2012 17:04:17
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle H:/Firmware_archive/Ben/stopped40MHz/FONT5_9Chan/FB_MULT_ADD.xaw -st FB_MULT_ADD.v
//Design Name: FB_MULT_ADD
//Device: xc5vlx50t-3ff1136
//
// Module FB_MULT_ADD
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module FB_MULT_ADD(A_IN,
B_IN,
CEMULTCARRYIN_IN,
CLK_IN,
C_IN,
P_OUT);
input [20:0] A_IN;
input [12:0] B_IN;
input CEMULTCARRYIN_IN;
input CLK_IN;
input [47:0] C_IN;
output [47:0] P_OUT;
wire GND_ALUMODE;
wire [2:0] GND_BUS_3;
wire [17:0] GND_BUS_18;
wire [29:0] GND_BUS_30;
wire [47:0] GND_BUS_48;
wire GND_OPMODE;
wire VCC_OPMODE;
assign GND_ALUMODE = 0;
assign GND_BUS_3 = 3'b000;
assign GND_BUS_18 = 18'b000000000000000000;
assign GND_BUS_30 = 30'b000000000000000000000000000000;
assign GND_BUS_48 = 48'b000000000000000000000000000000000000000000000000;
assign GND_OPMODE = 0;
assign VCC_OPMODE = 1;
DSP48E DSP48E_INST (.A({A_IN[20:20], A_IN[20:20], A_IN[20:20], A_IN[20:20],
A_IN[20:20], A_IN[20:20], A_IN[20:20], A_IN[20:20], A_IN[20:20],
A_IN[20:0]}),
.ACIN(GND_BUS_30[29:0]),
.ALUMODE({GND_ALUMODE, GND_ALUMODE, GND_ALUMODE,
GND_ALUMODE}),
.B({B_IN[12:12], B_IN[12:12], B_IN[12:12], B_IN[12:12],
B_IN[12:12], B_IN[12:0]}),
.BCIN(GND_BUS_18[17:0]),
.C(C_IN[47:0]),
.CARRYCASCIN(GND_ALUMODE),
.CARRYIN(GND_ALUMODE),
.CARRYINSEL(GND_BUS_3[2:0]),
.CEALUMODE(VCC_OPMODE),
.CEA1(VCC_OPMODE),
.CEA2(VCC_OPMODE),
.CEB1(VCC_OPMODE),
.CEB2(VCC_OPMODE),
.CEC(VCC_OPMODE),
.CECARRYIN(VCC_OPMODE),
.CECTRL(VCC_OPMODE),
.CEM(VCC_OPMODE),
.CEMULTCARRYIN(CEMULTCARRYIN_IN),
.CEP(VCC_OPMODE),
.CLK(CLK_IN),
.MULTSIGNIN(GND_ALUMODE),
.OPMODE({GND_OPMODE, VCC_OPMODE, VCC_OPMODE, GND_OPMODE,
VCC_OPMODE, GND_OPMODE, VCC_OPMODE}),
.PCIN(GND_BUS_48[47:0]),
.RSTA(GND_ALUMODE),
.RSTALLCARRYIN(GND_ALUMODE),
.RSTALUMODE(GND_ALUMODE),
.RSTB(GND_ALUMODE),
.RSTC(GND_ALUMODE),
.RSTCTRL(GND_ALUMODE),
.RSTM(GND_ALUMODE),
.RSTP(GND_ALUMODE),
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.CARRYOUT(),
.MULTSIGNOUT(),
.OVERFLOW(),
.P(P_OUT[47:0]),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.PCOUT(),
.UNDERFLOW());
defparam DSP48E_INST.ACASCREG = 1;
defparam DSP48E_INST.ALUMODEREG = 0;
defparam DSP48E_INST.AREG = 1;
defparam DSP48E_INST.AUTORESET_PATTERN_DETECT = "FALSE";
defparam DSP48E_INST.AUTORESET_PATTERN_DETECT_OPTINV = "MATCH";
defparam DSP48E_INST.A_INPUT = "DIRECT";
defparam DSP48E_INST.BCASCREG = 1;
defparam DSP48E_INST.BREG = 1;
defparam DSP48E_INST.B_INPUT = "DIRECT";
defparam DSP48E_INST.CARRYINREG = 0;
defparam DSP48E_INST.CARRYINSELREG = 0;
defparam DSP48E_INST.CREG = 1;
defparam DSP48E_INST.MASK = 48'h3FFFFFFFFFFF;
defparam DSP48E_INST.MREG = 1;
defparam DSP48E_INST.MULTCARRYINREG = 1;
defparam DSP48E_INST.OPMODEREG = 0;
defparam DSP48E_INST.PATTERN = 48'h000000000000;
defparam DSP48E_INST.PREG = 1;
defparam DSP48E_INST.SEL_MASK = "MASK";
defparam DSP48E_INST.SEL_PATTERN = "PATTERN";
defparam DSP48E_INST.SEL_ROUNDING_MASK = "SEL_MASK";
defparam DSP48E_INST.USE_MULT = "MULT_S";
defparam DSP48E_INST.USE_PATTERN_DETECT = "NO_PATDET";
defparam DSP48E_INST.USE_SIMD = "ONE48";
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxt = 300001; typedef int mang[maxt + 10]; struct mystr { int val[4]; }; mang bit1, bit2; mystr a[100010]; int n, dem, vt = 1; long long d, m; vector<pair<long long, pair<int, int>>> b; int kq[100010]; vector<int> s; int getbit(int x, mang bit) { int res = -maxt; for (; x > 0; x -= x & (-x)) res = max(res, bit[x]); return res; } void updatebit(int x, int val, mang& bit) { for (; x <= maxt; x += x & (-x)) bit[x] = max(bit[x], val); } int main() { ios::sync_with_stdio(0); cin >> n >> d; for (int i = 1; i <= n; i++) { cin >> m; b.push_back({m, {i, 1}}); b.push_back({m - d, {i, 2}}); b.push_back({m + d, {i, 3}}); } b.push_back({(int)-1e18, {0, 0}}); sort(b.begin(), b.end()); for (int i = 1; i < b.size(); i++) { if (b[i].first != b[i - 1].first) dem++; a[b[i].second.first].val[b[i].second.second] = dem; } for (int i = 1; i <= n; i++) { int longt = max(getbit(a[i].val[2], bit1), getbit(maxt - a[i].val[3], bit2)) + 1; updatebit(a[i].val[1], longt, bit1); updatebit(maxt - a[i].val[1], longt, bit2); kq[i] = longt; if (kq[i] >= kq[vt]) vt = i; } cout << kq[vt] << n ; for (int i = vt; i >= 1; i--) if (kq[vt] == kq[i] + 1 && (a[i].val[1] <= a[vt].val[2] || a[i].val[1] >= a[vt].val[3])) { s.push_back(vt); vt = i; } cout << vt << ; for (int i = s.size() - 1; i >= 0; i--) cout << s[i] << ; return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, ”/ STACK : 38777216“ using namespace std; const int N = 100005; const int inf = 1000 * 1000 * 1000; const int mod = 1000 * 1000 * 1000 + 7; string s; int a, b, c, d, t; int main() { cin >> t >> s; if (t % 4 != 0) { cout << === << endl; return 0; } t /= 4; for (int i = 0; i < 4 * t; i++) { if (s[i] == A ) a++; if (s[i] == C ) b++; if (s[i] == G ) c++; if (s[i] == T ) d++; } if (a > t || b > t || c > t || d > t) { cout << === << endl; return 0; } a = t - a; b = t - b; c = t - c; d = t - d; for (int i = 0; i < 4 * t; i++) { if (s[i] != ? ) continue; if (a > 0) { s[i] = A ; a--; continue; } if (b > 0) { s[i] = C ; b--; continue; } if (c > 0) { s[i] = G ; c--; continue; } s[i] = T ; d--; } cout << s << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int prime[1000005]; int ans[5]; int idx; set<int> s, s1; set<int>::iterator it; int main() { int i, j; for (i = 2; i <= 1000000; i++) { if (prime[i] == 1) continue; for (j = i + i; j <= 1000000; j += i) prime[j] = 1; } int n; scanf( %d , &n); if (n == 1) printf( 1 n ); else if (n == 2) printf( 2 n ); else { long long sum = n; for (i = 2; i < n; i++) { if (n % i == 0) s.insert(i); } int countt = 0; for (i = n - 1; i >= 1; i--) { bool no = 0; for (it = s.begin(); it != s.end(); it++) { if (i % (*it) == 0) { no = 1; break; } } if (!no) { sum *= (long long)i; countt++; } if (countt == 2) break; } long long sum1 = n - 1; for (i = 2; i < n - 1; i++) { if ((n - 1) % i == 0) s1.insert(i); } countt = 0; for (i = n - 2; i >= 1; i--) { bool no = 0; for (it = s1.begin(); it != s1.end(); it++) { if (i % (*it) == 0) { no = 1; break; } } if (!no) { sum1 *= (long long)i; countt++; } if (countt == 2) break; } printf( %I64d n , max(sum, sum1)); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_4_V
`define SKY130_FD_SC_HDLL__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_4_V
|
#include <bits/stdc++.h> using namespace std; int a[1010], ans[1010]; int main() { int n, i, cur = 0, x, y, l1 = 1, l2 = 1; cin >> n; for (i = 1; i < n; i++) { cin >> x >> y; if (x > y) swap(x, y); a[x]++; if (y != n) { cout << NO ; return 0; } } for (i = 1; i < n; i++) { cur += a[i]; if (cur > i) { cout << NO ; return 0; } } cout << YES << endl; ans[1] = n; for (i = n - 1; i; i--) { if (!a[i]) { while (ans[l2]) l2++; ans[l2] = i; continue; } l1 += a[i]; ans[l1] = i; } for (i = 1; i < n; i++) cout << ans[i] << << ans[i + 1] << endl; return 0; }
|
// psi2c_readback.v
`timescale 1 ps / 1 ps
module psi2c_readback
(
input clk,
input sync,
input reset,
input go,
input rda,
input sync2,
input i2c_send,
output [31:0]d
);
reg rdaff;
always @(posedge clk or posedge reset) rdaff <= reset ? 0 : rda;
wire nto; // not timeout
wire last;
wire running;
srff_timeout ffto
(
.clk(clk),
.sync(sync),
.reset(reset),
.s(go),
.r(running),
.to_disable(i2c_send),
.q(nto)
);
rda_bitcounter bitcounter
(
.aclr(reset),
.clk_en(sync),
.clock(clk),
.cnt_en(running),
.sset(sync && !rda && rdaff && nto),
.cout(last),
.q()
);
assign running = !last;
// shift register
reg [28:0]shiftreg;
always @(posedge clk or posedge reset)
begin
if (reset) shiftreg <= 0;
else if (running && sync) shiftreg <= {shiftreg[28:0], rdaff};
end
// rda data mapper
wire [4:0]ha = shiftreg[7:3];
wire [2:0]pa = shiftreg[2:0];
wire [7:0]ra = {shiftreg[28:25], shiftreg[23:20]};
wire [7:0]rd = {shiftreg[18:15], shiftreg[13:10]};
wire start = shiftreg[8];
wire _s3 = shiftreg[24];
wire _rw = shiftreg[19];
wire _d4 = shiftreg[14];
wire _d0 = shiftreg[9];
assign d = {running || nto, 2'b00, _s3, _rw, _d4, _d0, start, ha, pa, ra, rd};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [0:15]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, isum = 0; cin >> n; if (n % 2 == 0) cout << ((n + 1) * (n + 1) - 1) / 4; else cout << ((n + 1) * (n + 1)) / 4; }
|
#include <bits/stdc++.h> using namespace std; inline void solve() { long long n; cin >> n; vector<bool> isp(n + 1, 1); vector<long long> maxx(n + 1, -1); isp[0] = isp[1] = 0; for (long long i = 2; i <= n; i++) { if (isp[i]) { if (i * 2 <= n) { for (long long j = i * 2; j <= n; j += i) { isp[j] = 0; maxx[j] = max(maxx[j], i); } } } } long long best = 1, now = n; for (long long j = 2; j * j <= n; j++) { while (now % j == 0) { now /= j; best = max(best, j); } } best = max(best, now); long long ans = n - best + 1; for (long long i = n - best + 1; i < n; i++) { ans = min(ans, i - maxx[i] + 1); } cout << ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; stack<char> st; string s, ans = ; char mn[111111]; long long n; int main() { cin >> s; n = s.size(); mn[n - 1] = s[n - 1]; for (int i = n - 2; i >= 0; i--) { mn[i] = min(mn[i + 1], s[i]); } for (int i = 0; i < n;) { if (st.empty()) { st.push(s[i]); i++; } else if (st.top() <= mn[i]) { ans += st.top(); st.pop(); } else { st.push(s[i]); i++; } } while (!st.empty()) { ans += st.top(); st.pop(); } cout << ans; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:03:09 03/24/2015
// Design Name: clk_divider
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/clk_divider_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clk_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module clk_divider_test;
// Inputs
reg rst;
reg clk;
// Outputs
wire div_clk_2, div_clk_3, div_clk_4;
// Instantiate the Unit Under Test (UUT)
clk_divider #(.DIV(2)) uut2 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_2)
);
clk_divider #(.DIV(3)) uut3 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_3)
);
clk_divider #(.DIV(500)) uut4 (
.rst(rst),
.clk(clk),
.div_clk(div_clk_4)
);
reg [31:0] ctr_d, ctr_q;
always @(*) begin
ctr_d = ctr_q;
if(div_clk_4) begin
ctr_d = ctr_q + 1;
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 0;
end else begin
ctr_q <= ctr_d;
end
end
initial begin
// Initialize Inputs
clk = 0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
@(negedge rst); // wait for reset
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
$finish;
end
endmodule
|
#include <bits/stdc++.h> int main() { char arr[200]; int i, j, jp, g, t, cl, jm, a, m, n; scanf( %d%d , &cl, &jm); scanf( %c , &arr[0]); for (i = 1; i <= cl; i++) scanf( %c , &arr[i]); for (i = 1; i <= cl; i++) { if (arr[i] == G ) { g = i; } if (arr[i] == T ) { t = i; } } if (g > t) { m = t; n = g; a = g - t; } else { m = g; n = t; a = t - g; } for (i = m; i < n; i = i + jm) { if (arr[i] == # ) { printf( NO n ); return 0; } } if ((a % jm) == 0) printf( YES n ); else printf( NO n ); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int INF = 1e9 + 7; const int N = 2e5 + 7; const int M = 5e6 + 7; int a[N], f[N], ans[N]; int get(int x) { int k = ceil(sqrt(abs(x) * 1.00)); for (int i = 2; i <= k; i++) while (x % (i * i) == 0) x /= i * i; return x; } signed main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] = get(a[i]); } f[1] = -1; for (int i = 2; i <= n; i++) { for (int j = i - 1; j >= 1; --j) if (a[i] == a[j]) { f[i] = j; break; } } for (int i = 1; i <= n; i++) { int num = 0; for (int j = i; j <= n; j++) { if (f[j] < i && a[j] != 0) num++; if (!num) ans[1]++; else ans[num]++; } } for (int i = 1; i <= n; i++) cout << ans[i] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long in() { int32_t x; scanf( %d , &x); return x; } inline long long lin() { long long x; scanf( %lld , &x); return x; } const long long maxn = 200 + 10; const long long inf = 1e18 + 1; long long a[maxn][maxn], mini[maxn], res[maxn], dp[maxn][maxn], id[maxn], what[maxn]; long long N; inline void calcDp() { memset(dp, 0, sizeof dp); dp[N][0] = 1; for (long long i = N - 1; i >= 0; i--) { for (long long j = 0; j <= i; j++) { dp[i][j] = min(dp[i + 1][j + 1] * bool(what[i] != 1) + (j && what[i] != 0 ? dp[i + 1][j - 1] : 0), inf); } } } int32_t main() { long long n = in(), m = in(), k = lin(); N = n + m - 1; memset(mini, 63, sizeof mini); memset(res, -1, sizeof res); memset(what, -1, sizeof what); for (long long i = 0; i < n; i++) for (long long j = 0; j < m; j++) a[i][j] = in(); for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) mini[i + j] = min(mini[i + j], a[i][j]); } iota(id, id + n + m - 1, 0); sort(id, id + n + m - 1, [](const long long &a, const long long &b) { return mini[a] < mini[b]; }); for (long long _ = 0; _ < n + m - 1; _++) { long long i = id[_]; what[i] = 0; calcDp(); if (dp[0][0] >= k) continue; k -= dp[0][0]; what[i] = 1; } for (long long i = 0; i < n; i++, cout << n ) { for (long long j = 0; j < m; j++) { cout << (what[i + j] == 0 ? ( : ) ); } } }
|
#include <bits/stdc++.h> using namespace std; int vis[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int dis[n][n]; vector<int> arr(n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> dis[i][j]; for (int i = 0; i < n; i++) cin >> arr[i]; reverse(arr.begin(), arr.end()); vector<long long> ans; for (int k = 0; k < n; k++) { int x = arr[k] - 1; vis[x] = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { dis[i][j] = min(dis[i][j], dis[i][x] + dis[x][j]); } } long long sum = 0; for (int i = 0; i < n; i++) { if (!vis[i]) continue; for (int j = 0; j < n; j++) if (vis[j]) sum += dis[i][j]; } ans.push_back(sum); } reverse(ans.begin(), ans.end()); for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unordered_map<int, int> nums; int n; cin >> n; while (n--) { int dummy; cin >> dummy; nums[dummy]++; } int res = 0; for (auto p : nums) res = max(res, p.second); cout << res << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_TB_V
`define SKY130_FD_SC_LP__ISOLATCH_TB_V
/**
* isolatch: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__isolatch.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 SLEEP_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SLEEP_B = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SLEEP_B = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
sky130_fd_sc_lp__isolatch dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_TB_V
|
#include <bits/stdc++.h> inline long long MAX2(long long a, long long int b) { return (a) > (b) ? (a) : (b); } inline long long MAX3(long long a, long long b, long long c) { return (a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)); } inline long long MIN2(long long a, long long b) { return (a) < (b) ? (a) : (b); } inline long long MIN3(long long a, long long b, long long c) { return (a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c)); } using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int q; cin >> q; while (q--) { int b, w; cin >> b >> w; vector<pair<int, int> > co; if (b > w) { if (b > 3 * w + 1) { cout << NO n ; continue; } int x = 1e5 + 1, y = 1e5 + 1; int i = 0; while (i < w - 1) { co.push_back(pair<int, int>(x, y)); y++; co.push_back(pair<int, int>(x, y)); y++; i++; } co.push_back(pair<int, int>(x, y)); y++; int si = co.size(); int req = b - w + 1; i = 0; while (i < si && req > 0) { co.push_back(pair<int, int>(co[i].first - 1, co[i].second)); req--; if (req == 0) break; co.push_back(pair<int, int>(co[i].first + 1, co[i].second)); req--; i += 2; } if (req > 0) { co.push_back(pair<int, int>(co[0].first, co[0].second - 1)); req--; } if (req > 0) { co.push_back( pair<int, int>(co[2 * (w - 1)].first, co[2 * (w - 1)].second + 1)); req--; } } else { if (w > 3 * b + 1) { cout << NO n ; continue; } int x = 1e5, y = 1e5 + 1; int i = 0; while (i < b - 1) { co.push_back(pair<int, int>(x, y)); y++; co.push_back(pair<int, int>(x, y)); y++; i++; } co.push_back(pair<int, int>(x, y)); y++; int si = co.size(); int req = w - b + 1; i = 0; while (i < si && req > 0) { co.push_back(pair<int, int>(co[i].first - 1, co[i].second)); req--; if (req == 0) break; co.push_back(pair<int, int>(co[i].first + 1, co[i].second)); req--; i += 2; } if (req > 0) { co.push_back(pair<int, int>(co[0].first, co[0].second - 1)); req--; } if (req > 0) { co.push_back( pair<int, int>(co[2 * (b - 1)].first, co[2 * (b - 1)].second + 1)); req--; } } cout << YES n ; int i, si = co.size(); for (i = 0; i < si; i++) cout << co[i].first << << co[i].second << n ; } cerr << n << Time elapsed : << clock() * 1000.0 / CLOCKS_PER_SEC << ms << n ; }
|
#include <bits/stdc++.h> #pragma optimise GCC(-O2) using namespace std; mt19937_64 rang( chrono::high_resolution_clock::now().time_since_epoch().count()); int rng(int lim) { uniform_int_distribution<int> uid(0, lim - 1); return uid(rang); } long long INF = LLONG_MAX; const long long M = 1000000007; long long powm(long long, long long); long long foo(long long a) { long long ct = 1; long long tp = a; while (tp > 0) { tp -= ct; ct++; } return ct; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; long long hr = 0; long long mn = 0; hr += 10 * (s[0] - 0 ); hr += (s[1] - 0 ); mn += 10 * (s[3] - 0 ); mn += (s[4] - 0 ); long long a; cin >> a; mn += a; long long ex = mn / 60; mn = mn % 60; hr += ex; hr %= 24; if (hr > 9 && mn > 9) cout << hr << : << mn; if (hr > 9 && mn <= 9) cout << hr << : << 0 << mn; if (hr <= 9 && mn > 9) cout << 0 << hr << : << mn; if (hr <= 9 && mn <= 9) cout << 0 << hr << : << 0 << mn; } long long powm(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % M; a = (a * a) % M; b >>= 1; } return res; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = int64_t; template <typename T, typename U> ostream& operator<<(ostream& _s, pair<T, U> _t) { _s << ( << _t.first << , << _t.second << ) ; return _s; } template <typename T, typename U> istream& operator>>(istream& _s, pair<T, U>& _t) { _s >> _t.first >> _t.second; return _s; } template <typename T> ostream& operator<<(ostream& _s, vector<T> _t) { for (int i = 0; i < (int)(_t.size()); i++) _s << (i ? : ) << _t[i]; return _s; } template <typename T> istream& operator>>(istream& _s, vector<T>& _t) { for (int i = 0; i < (int)(_t.size()); i++) _s >> _t[i]; return _s; } vector<int> val, comp, z, cont; int Time, ncomps; template <class G, class F> int dfs(int j, G& g, F f) { int low = val[j] = ++Time, x; z.push_back(j); for (auto& e : g[j]) if (comp[e] < 0) low = min(low, val[e] ?: dfs(e, g, f)); if (low == val[j]) { do { x = z.back(); z.pop_back(); comp[x] = ncomps; cont.push_back(x); } while (x != j); f(cont); cont.clear(); ncomps++; } return val[j] = low; } template <class G, class F> void scc(G& g, F f) { int n = g.size(); val.assign(n, 0); comp.assign(n, -1); Time = ncomps = 0; for (int i = 0; i < (int)(n); i++) if (comp[i] < 0) dfs(i, g, f); } void tassert(bool cond) { if (!cond) { while (1 < 2) { } } } void answer(int x) { cout << ! << (x + 1) << endl; cout << flush; exit(0); } bool ask(int a, int b) { cout << ? << (a + 1) << << (b + 1) << endl; cout << flush; int res; cin >> res; if (res == -1) { exit(123); } return bool(res); } int main() { int n, m; cin >> n >> m; vector<vector<int>> g(n); for (int i = 0; i < (int)(m); i++) { int x, y; cin >> x >> y; g[x - 1].push_back(y - 1); } vector<vector<int>> comps; scc(g, [&](vector<int>& v) { comps.push_back(v); }); vector<unordered_set<int>> cg(ncomps); for (int a = 0; a < (int)(n); a++) { for (int b : g[a]) { if (comp[a] != comp[b]) { cg[comp[a]].insert(comp[b]); } } } vector<int> indeg(ncomps, 0); for (int aa = 0; aa < (int)(ncomps); aa++) { for (int bb : cg[aa]) { indeg[bb]++; } } unordered_set<int> heads; for (int aa = 0; aa < (int)(ncomps); aa++) { if (indeg[aa] == 0) { heads.insert(aa); } } int head = *heads.begin(); int cap = comps[head].back(); comps[head].pop_back(); auto update = [&](int aa) { if (comps[aa].size() == 0) { heads.erase(aa); for (int bb : cg[aa]) { tassert(comps[bb].size() > 0); indeg[bb]--; if (indeg[bb] == 0) { heads.insert(bb); } } } }; while (true) { assert(heads.size()); if (heads.size() == 1) { answer(cap); } auto head2it = heads.begin(); if (head == (*head2it)) { head2it++; } int head2 = *head2it; tassert(!cg[head].count(head2)); int cap2 = comps[head2].back(); comps[head2].pop_back(); bool ok = ask(cap, cap2); if (!ok) { update(head); head = head2; cap = cap2; } else { update(head2); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_SYMBOL_V
`define SKY130_FD_SC_HS__AND4_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:user:KeyboardCtrl:1.0
// IP Revision: 2
(* X_CORE_INFO = "KeyboardCtrl,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "KeyboardCtrl_0,KeyboardCtrl,{}" *)
(* CORE_GENERATION_INFO = "KeyboardCtrl_0,KeyboardCtrl,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=KeyboardCtrl,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,SYSCLK_FREQUENCY_HZ=100000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module KeyboardCtrl_0 (
key_in,
is_extend,
is_break,
valid,
err,
PS2_DATA,
PS2_CLK,
rst,
clk
);
output wire [7 : 0] key_in;
output wire is_extend;
output wire is_break;
output wire valid;
output wire err;
inout wire PS2_DATA;
inout wire PS2_CLK;
input wire rst;
input wire clk;
KeyboardCtrl #(
.SYSCLK_FREQUENCY_HZ(100000000)
) inst (
.key_in(key_in),
.is_extend(is_extend),
.is_break(is_break),
.valid(valid),
.err(err),
.PS2_DATA(PS2_DATA),
.PS2_CLK(PS2_CLK),
.rst(rst),
.clk(clk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_2_V
`define SKY130_FD_SC_LP__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_2_V
|
#include <bits/stdc++.h> using namespace std; long long read() { long long f = 1, x = 0; char ss = getchar(); while (ss < 0 || ss > 9 ) { if (ss == - ) f = -1; ss = getchar(); } while (ss >= 0 && ss <= 9 ) { x = x * 10 + ss - 0 ; ss = getchar(); } return f * x; } long long seed, vmax; long long rnd() { long long res = seed; seed = (seed * 7 + 13) % 1000000007; return res; } const int maxn = 100010; int n, m; long long a[maxn]; struct node { int ll, rr; mutable long long val; bool operator<(const node& tt) const { return ll < tt.ll; } }; set<node> st; long long qpow(long long a, long long k, long long p) { long long res = 1; a %= p; while (k > 0) { if (k & 1) res = (res * a) % p; a = (a * a) % p; k >>= 1; } return res; } set<node>::iterator split(int pos) { set<node>::iterator it = st.lower_bound(node{pos}); if (it != st.end() && it->ll == pos) return it; --it; int ll = it->ll, rr = it->rr; long long val = it->val; st.erase(it); st.insert(node{ll, pos - 1, val}); return st.insert(node{pos, rr, val}).first; } void assign(int ll, int rr, long long val) { set<node>::iterator itr = split(rr + 1), itl = split(ll); st.erase(itl, itr); st.insert(node{ll, rr, val}); } void add(int ll, int rr, long long val) { set<node>::iterator itr = split(rr + 1), itl = split(ll); for (; itl != itr; ++itl) itl->val += val; } long long kth(int ll, int rr, int k) { vector<pair<long long, int> > vec; set<node>::iterator itr = split(rr + 1), itl = split(ll); for (; itl != itr; ++itl) vec.push_back(pair<long long, int>(itl->val, itl->rr - itl->ll + 1)); sort(vec.begin(), vec.end()); for (vector<pair<long long, int> >::iterator it = vec.begin(); it != vec.end(); ++it) { k -= it->second; if (k <= 0) return it->first; } return -1; } long long qsum(int ll, int rr, long long x, long long y) { long long res = 0; set<node>::iterator itr = split(rr + 1), itl = split(ll); for (; itl != itr; ++itl) res += (qpow(itl->val, x, y) * ((itl->rr - itl->ll + 1) % y)) % y, res %= y; return res; } int main() { n = read(); m = read(); seed = read(); vmax = read(); for (int i = 1; i <= n; ++i) { a[i] = (rnd() % vmax) + 1; st.insert(node{i, i, a[i]}); } for (int i = 1; i <= m; ++i) { int op = (rnd() % 4) + 1; int ll = (rnd() % n) + 1, rr = (rnd() % n) + 1; long long x, y; if (ll > rr) swap(ll, rr); if (op == 3) x = (rnd() % (rr - ll + 1)) + 1; else x = (rnd() % vmax) + 1; if (op == 4) y = (rnd() % vmax) + 1; if (op == 1) add(ll, rr, x); else if (op == 2) assign(ll, rr, x); else if (op == 3) printf( %lld n , kth(ll, rr, x)); else if (op == 4) printf( %lld n , qsum(ll, rr, x, y)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } long long int lcm(long long int a, long long int b) { return a * b / gcd(a, b); } int n, m, cnt[11][11], a[22], b[22], tr[11], mx; void bktk(int i) { if (i == n + 1) { int ans = 0; memset(cnt, 0, sizeof(cnt)); for (int j = 1; j <= m; j++) cnt[min(tr[a[j]], tr[b[j]])][max(tr[b[j]], tr[a[j]])]++; for (int j = 1; j <= 6; j++) for (int k = 1; k <= 6; k++) if (cnt[j][k]) ans++; mx = max(ans, mx); return; } for (int j = 1; j <= 6; j++) { tr[i] = j; bktk(i + 1); } } int main() { cin >> n >> m; if (n < 7) { cout << m << endl; return 0; } for (int i = 1; i <= m; i++) cin >> a[i] >> b[i]; bktk(1); cout << mx << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_dmask_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_dmask_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_dmask_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_dmask_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [2*DataWidth-1:0] ParamCounterPreset_i
);
// Sensor FSM
localparam stDisabled = 2'b00;
localparam stIdle = 2'b01;
localparam stXfer = 2'b10;
localparam stNotify = 2'b11;
reg [1:0] SensorFSM_State;
reg [1:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_NextState = stIdle;
end
end
stIdle: begin
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
else
begin
SensorFSM_TimerEnable = 1'b1; // timer running
end
end
stXfer: begin
if (MeasureFSM_Done_i == 1'b1)
begin
SensorFSM_TimerPreset = 1'b1;
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [2*DataWidth-1:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 16'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= ParamCounterPreset_i;
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Final Cursor
// File : final_cursor.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
// This module generates the final cursor by using the
// cursor-y and cursor-x position. The cursor blinking
// is achieved by counting 32 Vsync's.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module final_cursor
(
input h_reset_n,
input t_crt_clk,
input c_shift_ld, // Load signal to Attribute serializer
input m_att_data_b32, // cursor text attribute
input c_cr0b_b6, // Text cursor skew control 1
input c_cr0b_b5, // Text cursor skew control 0
input c_cr0a_b5, // Disable Text cursor
input c_t_vsync, // Vertical sync.
input ar12_b4, // cursor blink disable (Vid status mux [0])
output cursor_blink_rate,
output finalcursor,
output char_blink_rate
);
reg mux_op;
reg [2:0] shifted_data;
reg ctvsync_hold;
reg [4:0] blink_rate;
wire [2:0] m_att_data_b32_d; // delayed m_att_data_b32
wire int_final_cursor;
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) shifted_data <= 3'b0;
else if (c_shift_ld) shifted_data <= {shifted_data[1:0], m_att_data_b32};
assign m_att_data_b32_d = shifted_data;
// CR06[6:5] defines the skew applied to the cursor for proper alignment
always @*
case({c_cr0b_b6, c_cr0b_b5})
2'b00: mux_op = m_att_data_b32;
2'b01: mux_op = m_att_data_b32_d[0];
2'b10: mux_op = m_att_data_b32_d[1];
2'b11: mux_op = m_att_data_b32_d[2];
endcase
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) begin
ctvsync_hold <= 1'b0;
blink_rate <= 5'b0;
end else begin
ctvsync_hold <= c_t_vsync;
// Disable blinking if this bit is set.
if (ar12_b4)
blink_rate <= 5'b0;
// Otherwise increment the blinker on every edge of vertical sync.
// The actual edge should not matter.
else if (c_t_vsync && ~ctvsync_hold)
blink_rate <= blink_rate + 1'b1;
end
// Cursor blinks faster than characters
assign cursor_blink_rate = ~blink_rate[3];
assign char_blink_rate = blink_rate[4];
assign int_final_cursor = ~( ~cursor_blink_rate | (~mux_op) );
assign finalcursor = (int_final_cursor & (~c_cr0a_b5));
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_wbs (
input wire clk_50,
input wire reset_n,
// slave wishbone interface (from SDHC)
input wire wbs_clk_i,
input wire [31:0] wbs_adr_i,
output wire [31:0] wbs_dat_o,
input wire [31:0] wbs_dat_i,
input wire [3:0] wbs_sel_i,
input wire wbs_cyc_i,
input wire wbs_stb_i,
input wire wbs_we_i,
output wire wbs_ack_o,
// port to cached block ram
output wire bram_wbs_clk,
output wire [15:0] bram_wbs_addr,
output reg bram_wbs_wren,
output reg [31:0] bram_wbs_data,
input wire [31:0] bram_wbs_q,
input wire logical_init_done,
output reg wb_read,
output reg wb_write,
output reg [9:0] wb_block,
input wire wb_ack,
input wire wb_done
);
`include "ftl_const.vh"
assign bram_wbs_clk = wbs_clk_i;
assign bram_wbs_addr = (wbs_adr_i % NAND_BLOCK_SIZE) / 4;
assign wbs_ack_o = wbs_ack & wbs_stb_i;
assign wbs_dat_o = bram_wbs_q;
reg wbs_ack;
reg wbs_stb_i_1;
reg wb_done_s_1;
wire reset_s;
wire logical_init_done_s;
wire wb_ack_s;
wire wb_done_s;
synch_3 a(reset_n, reset_s, wbs_clk_i);
synch_3 b(logical_init_done, logical_init_done_s, wbs_clk_i);
synch_3 c(wb_ack, wb_ack_s, wbs_clk_i);
synch_3 d(wb_done, wb_done_s, wbs_clk_i);
wire [9:0] req_block = wbs_adr_i / NAND_BLOCK_SIZE;
reg [9:0] req_block_latch;
reg [9:0] cached_block;
reg modified;
reg [3:0] state;
wire ftl_valid = wbs_adr_i >= 32'h200000;
parameter [3:0] ST_RESET = 'd0,
ST_IDLE = 'd1,
ST_READ = 'd2,
ST_WRITE = 'd3,
ST_IDLE_WAIT = 'd5,
ST_READ_DELAY = 'd6;
always @(posedge wbs_clk_i) begin
wbs_ack <= 0;
wbs_stb_i_1 <= wbs_stb_i;
wb_done_s_1 <= wb_done_s;
wb_read <= 0;
wb_write <= 0;
bram_wbs_wren <= 0;
case(state)
ST_RESET: begin
cached_block <= -1;
modified <= 0;
if(logical_init_done_s) state <= ST_IDLE;
end
ST_IDLE: begin
// on rising edge of WBS_STB_I
if(wbs_cyc_i & wbs_stb_i & ~wbs_stb_i_1 & ftl_valid) begin
if(wbs_we_i) begin
if((cached_block == req_block) && modified) begin
// write to bram
bram_wbs_data <= wbs_dat_i;
bram_wbs_wren <= 1;
wbs_ack <= 1;
end else begin
// switch blocks and mark modified
state <= ST_WRITE;
req_block_latch <= req_block;
end
//wbs_ack <= 1;
end else begin
if(cached_block == req_block) begin
// read from bram
state <= ST_READ_DELAY;
end else begin
// switch blocks and mark unmodified
state <= ST_READ;
req_block_latch <= req_block;
end
end
end
end
ST_IDLE_WAIT: begin
wbs_stb_i_1 <= 0; // make idle state fire again
if(~wb_ack_s) state <= ST_IDLE;
end
ST_WRITE: begin
modified <= 1;
wb_block <= req_block_latch;
wb_write <= 1;
if(wb_done_s & ~wb_done_s_1) begin
cached_block <= req_block_latch;
state <= ST_IDLE_WAIT;
end
end
ST_READ: begin
modified <= 0;
wb_block <= req_block_latch;
wb_read <= 1;
if(wb_done_s & ~wb_done_s_1) begin
cached_block <= req_block_latch;
state <= ST_IDLE_WAIT;
end
end
ST_READ_DELAY: begin
// delay for bram
wbs_ack <= 1;
state <= ST_IDLE;
end
endcase
if(~reset_s) begin
state <= ST_RESET;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int inf = 2e9 + 9; int n, m, p; pair<int, int> a[maxn], b[maxn]; pair<pair<int, int>, int> mon[maxn]; struct segment_tree { int val[maxn * 4], lazy[maxn * 4]; void build(int x, int l, int r) { if (l == r) { val[x] = -b[l].second; return; } int mid = (l + r) / 2; build(x * 2, l, mid); build(x * 2 + 1, mid + 1, r); val[x] = max(val[x * 2], val[x * 2 + 1]); } void push(int x) { if (lazy[x] == 0) return; int t = lazy[x]; val[x * 2] += t; lazy[x * 2] += t; val[x * 2 + 1] += t; lazy[x * 2 + 1] += t; lazy[x] = 0; } void upd(int x, int l, int r, int L, int R, int k) { if (L > r || l > R || L > R) return; if (l >= L && r <= R) { val[x] += k; lazy[x] += k; return; } push(x); int mid = (l + r) / 2; upd(x * 2, l, mid, L, R, k); upd(x * 2 + 1, mid + 1, r, L, R, k); val[x] = max(val[x * 2], val[x * 2 + 1]); } int get() { return val[1]; } } tree; void read_input() { cin >> n >> m >> p; for (int i = 1; i <= n; ++i) cin >> a[i].first >> a[i].second; for (int i = 1; i <= m; ++i) cin >> b[i].first >> b[i].second; for (int i = 1; i <= p; ++i) { int x, y, z; cin >> x >> y >> z; mon[i] = make_pair(pair<int, int>(x, y), z); } } void init() { sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); sort(mon + 1, mon + p + 1); tree.build(1, 1, m); } void solve() { int cur = 1; int ans = -inf; for (int i = 1; i <= n; ++i) { int ap = a[i].first; while (cur <= p && mon[cur].first.first < ap) { int p = upper_bound(b + 1, b + m + 1, pair<int, int>(mon[cur].first.second, inf)) - b; tree.upd(1, 1, m, p, m, mon[cur].second); ++cur; } ans = max(ans, -a[i].second + tree.get()); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); read_input(); init(); solve(); }
|
module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s == 0) o <= i[0*W+:W];
else if (s == 1) o <= i[1*W+:W];
else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
end
endmodule
module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s != 0)
if (s != 1)
if (s != 2)
if (s != 3)
if (s != 4) o <= i[4*W+:W];
else o <= i[0*W+:W];
else o <= i[3*W+:W];
else o <= i[2*W+:W];
else o <= i[1*W+:W];
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 2) o[W-2:0] <= i[2*W+:W-1];
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
end
endmodule
module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
if (s == 0) o <= i[0*W+:W];
// else if (s == 1) o <= i[1*W+:W];
// else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else o <= {W{1'bx}};
end
endmodule
module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 3) o <= i[3*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 4) o <= i[4*W+:W];
if (s == 0) o <= i[0*W+:W];
end
endmodule
module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s == 0) o <= i[0*W+:W];
else if (s == 1) o <= i[1*W+:W];
else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else if (s == 0) o <= {W{1'b0}};
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 0) o <= i[0*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
if (s == 0) o <= i[2*W+:W];
end
endmodule
module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
case (s)
0: o <= i[0*W+:W];
default:
case (s)
1: o <= i[1*W+:W];
2: o <= i[2*W+:W];
default:
case (s)
3: o <= i[3*W+:W];
4: o <= i[4*W+:W];
5: o <= i[5*W+:W];
default:
case (s)
6: o <= i[6*W+:W];
default: o <= i[7*W+:W];
endcase
endcase
endcase
endcase
end
endmodule
module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[2] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[4*W+:W];
else
o <= i[5*W+:W];
else
if (s[2] == 1'b0)
o <= i[6*W+:W];
else
o <= i[7*W+:W];
endmodule
module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[2] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
o <= i[4*W+:W];
endmodule
module cliffordwolf_nonexclusive_select (
input wire x, y, z,
input wire a, b, c, d,
output reg o
);
always @* begin
o = a;
if (x) o = b;
if (y) o = c;
if (z) o = d;
end
endmodule
module cliffordwolf_freduce (
input wire [1:0] s,
input wire a, b, c, d,
output reg [3:0] o
);
always @* begin
o = {4{a}};
if (s == 0) o = {3{b}};
if (s == 1) o = {2{c}};
if (s == 2) o = d;
end
endmodule
module case_nonexclusive_select (
input wire [1:0] x, y,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0: o = b;
2: o = b;
1: o = c;
default: begin
o = a;
if (y == 0) o = d;
if (y == 1) o = e;
end
endcase
end
endmodule
module case_nonoverlap (
input wire [2:0] x,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0, 2: o = b; // Creates $reduce_or
1: o = c;
default:
case (x)
3: o = d; 4: o = d; // Creates $reduce_or
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule
module case_overlap (
input wire [2:0] x,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0, 2: o = b; // Creates $reduce_or
1: o = c;
default:
case (x)
0: o = 1'b1; // OVERLAP!
3, 4: o = d; // Creates $reduce_or
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule
module case_overlap2 (
input wire [2:0] x,
input wire a, b, c, d, e,
output reg o
);
always @* begin
case (x)
0: o = b; 2: o = b; // Creates $reduce_or
1: o = c;
default:
case (x)
0: o = d; 2: o = d; // Creates $reduce_or
3: o = d; 4: o = d; // Creates $reduce_or
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule
|
//
`timescale 1ns/1ps
module test_afifo_sram ();
parameter DEPTH =256, ADDRESS_WIDTH = 8, WIDTH=8;
parameter clk_period = 2;
parameter half_period = 1;
reg CLK;
reg REN;
reg WEN;
reg RESET;
reg valid;
reg [WIDTH-1:0] Data_in [DEPTH-1:0];
wire [WIDTH-1:0] Data_out [DEPTH-1:0];
wire [DEPTH-1:0] Full_out;
wire [DEPTH-1:0] Empty_out;
MatrixInput_sram #(.DEPTH(DEPTH),.ADDRESS_WIDTH(ADDRESS_WIDTH),.WIDTH(WIDTH)) DUT (
.CLK(CLK),.valid(valid),.REN(REN),.WEN(WEN),.RESET(RESET),
.Data_in(Data_in),.Data_out(Data_out),.Full_out(Full_out),.Empty_out(Empty_out));
always begin
#half_period
CLK = ~CLK;
end
initial begin
RESET = 1'b1;
valid = 1'b0;
REN = 1'b0;
WEN = 1'b0;
CLK = 1'b0;
$dumpfile("test.vcd") ;
$dumpvars;
#20 RESET=1'b0;
#clk_period
for (integer i=0;i<DEPTH;i++)
Data_in[i] = 8'haa;
writeMem();
#clk_period
for (integer i=0;i<DEPTH;i++)
Data_in[i] = 8'hbb;
writeMem();
#clk_period
#clk_period
#clk_period readMem();
#clk_period readMem();
#clk_period
#clk_period
#clk_period $finish;
end
task writeMem;
//input [WIDTH-1:0] wdata [DEPTH-1:0];
begin
WEN = 1;
//D = wdata;
#clk_period
WEN = 0;
end
endtask
task readMem;
begin
REN = 1;
valid = 1;
#clk_period
REN = 0;
valid = 0;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, d, h; struct edge { int n1; int n2; }; edge vertices[100000]; int main() { cin >> n >> d >> h; if (d > 2 * h || (h == 1 && d == 1 && n > 2)) cout << -1 << endl; else { int idx = 0; int usedNode = 1; for (int i = 0; i < h; i++) { vertices[idx++] = edge{usedNode - 1, usedNode++}; } if (d > h) { vertices[idx++] = edge{0, usedNode++}; for (int i = 1; i < (d - h); i++) { vertices[idx++] = edge{usedNode - 1, usedNode++}; } } int start = (h > 1) ? 1 : 0; for (int i = h + (d - h); i < n - 1; i++) { vertices[idx++] = edge{start, usedNode++}; } for (int i = 0; i < n - 1; i++) { cout << vertices[i].n1 + 1 << << vertices[i].n2 + 1 << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 110; long long dp[N][N][N]; char s[N]; int a[N]; long long f[N]; void update(long long &x, long long y) { if (y == -1) return; if (x == -1 || x < y) x = y; } bool vis[N][N][N]; long long dfs(int l, int r, int p) { if (l > r) return a[p]; if (vis[l][r][p]) return dp[l][r][p]; vis[l][r][p] = true; if (l == r) { return dp[l][r][p] = f[p + 1]; } dp[l][r][p] = dfs(l, r - 1, 0) + f[p + 1]; for (int k = l; k < r; k++) if (s[k] == s[r]) { update(dp[l][r][p], dfs(l, k, p + 1) + dfs(k + 1, r - 1, 0)); } return dp[l][r][p]; } int main() { int n; cin >> n; cin >> (s + 1); for (int i = 1; i <= n; i++) cin >> a[i]; f[0] = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= i; j++) f[i] = max(f[i], f[i - j] + a[j]); memset(dp, -1, sizeof(dp)); cout << dfs(1, n, 0) << endl; return 0; }
|
module jfulladdertb;
wire y, carryout;
reg a,b,carryin;
jfulladder jfa(y,carryout,a,b,carryin);
initial
begin
$display("RSLT\tA\tB\tCYIN\t\tCYOUT\tSUM");
a = 0; b = 0; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 0; b = 0; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 0; b = 1; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 0; b = 1; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 0; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 0; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 1; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 1; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100005]; int l[100005]; int r[100005]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= n; i++) { l[i] = min(l[i - 1] + 1, a[i]); } for (int i = n; i >= 1; i--) { r[i] = min(r[i + 1] + 1, a[i]); } int ma = 0; for (int i = 1; i <= n; i++) { ma = max(ma, min(l[i], r[i])); } cout << ma << endl; }
|
#include <bits/stdc++.h> using namespace std; int IN() { int x = 0, f = 0, ch; for (; (ch = getchar()) < 0 || ch > 9 ;) f = (ch == - ); for (; ch >= 0 && ch <= 9 ; (ch = getchar())) x = x * 10 + ch - 0 ; return f ? -x : x; } int M, edge[1005][1005], son[1005][1005], idx[1005][1005]; inline void Plu(int& a, int b) { a += b; if (a >= 1000000007) a -= 1000000007; } struct Tree { int N, D, st[1005]; int F[1005][15], G[1 << 15]; struct Lin { int v, next; } E[1005 << 1]; void Link(int u, int v) { E[++D] = (Lin){v, st[u]}; st[u] = D; E[++D] = (Lin){u, st[v]}; st[v] = D; } void Init(int kind) { N = IN(); for (int i = 2, lim = N; i <= lim; i++) { int u = IN(), v = IN(); Link(u, v); if (kind) { edge[u][++*edge[u]] = v; edge[v][++*edge[v]] = u; } } if (kind) M = N; } void DFS(int u, int f) { for (int i = st[u], v; i; i = E[i].next) if ((v = E[i].v) != f) DFS(v, u); for (int a = 1, lim = M; a <= lim; a++) { int U = (1 << *son[a]) - 1; for (int j = 0, lim = U; j <= lim; j++) G[j] = 0; G[0] = 1; for (int i = st[u], v; i; i = E[i].next) if ((v = E[i].v) != f) { for (int s = U, lim = 0; s >= lim; s--) if (G[s]) { for (int j = 1, lim = *son[a]; j <= lim; j++) { int b = son[a][j], t = 1 << (idx[a][b] - 1); if (!(t & s)) Plu(G[s | t], 1ll * G[s] * F[v][b] % 1000000007); } } } F[u][a] = G[U]; } } int Work(int Rt) { for (int i = 1, lim = N; i <= lim; i++) for (int j = 1, lim = M; j <= lim; j++) F[i][j] = 0; DFS(1, 0); int ret = 0; for (int i = 1, lim = N; i <= lim; i++) Plu(ret, F[i][Rt]); return ret; } } A, B; int Pow(int a, int b) { int ret = 1; for (; b; b >>= 1, a = 1ll * a * a % 1000000007) if (b & 1) ret = 1ll * ret * a % 1000000007; return ret; } void DFS(int u, int f) { for (int i = 1, lim = *edge[u]; i <= lim; i++) { int v = edge[u][i]; if (v != f) { son[u][++*son[u]] = v; idx[u][v] = *son[u]; DFS(v, u); } } } int main(int argc, char* argv[]) { A.Init(0); B.Init(1); int retA = 0, retB = 0; for (int i = 1, lim = M; i <= lim; i++) { for (int j = 0, lim = M; j <= lim; j++) for (int k = 0, lim = M; k <= lim; k++) son[j][k] = idx[j][k] = 0; DFS(i, 0); Plu(retA, A.Work(i)); Plu(retB, B.Work(i)); } cout << 1ll * retA * Pow(retB, 1000000007 - 2) % 1000000007 << endl; cerr << retA << << retB << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; char a[102]; char b[102]; char c[102]; int main() { gets(a); gets(b); int l = strlen(a); int i; for (i = l - 1; i >= 0; i--) { if (a[i] == z ) { a[i] = a ; } else { a[i] = a[i] + 1; break; } } if (!strcmp(a, b)) cout << No such string ; else cout << a; return 0; }
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#include <bits/stdc++.h> int f[1200000], g[30][30], h[30][30], o[30], p[30], q[30][30]; char c[30][30]; int i, j, k, l, m, n, t, u, v; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %s , c[i] + 1); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) c[i][j] = c[i][j] - 96; memset(o, 12, sizeof(o)); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { scanf( %d , &g[i][j]); if (g[i][j] < o[i]) o[i] = g[i][j]; } for (i = 1; i <= m; i++) for (j = 1; j <= 26; j++) { for (k = 1, l = 0, u = 0, v = 0; k <= n; k++) if (c[k][i] == j) { l = l | (1 << (k - 1)); u = u + g[k][i]; if ((!v) || (g[v][i] < g[k][i])) v = k; } h[i][j] = l, q[i][j] = u - g[v][i]; } for (i = 1; i <= n; i++) p[i] = 1 << (i - 1); t = (1 << n) - 1; memset(f, 12, sizeof(f)); f[0] = 0; for (i = 1; i <= m; i++) { for (k = 1; k <= 26; k++) if (h[i][k]) { for (j = t; j > 0; j--) if (((j | h[i][k]) == j) && (f[j] > f[j - h[i][k]] + q[i][k])) f[j] = f[j - h[i][k]] + q[i][k]; for (j = t; j > 0; j--) if (((j | h[i][k]) != j) && (f[j])) for (l = t ^ j; l != 0; l = l - (l & (-l))) if (f[j] > f[j + (l & (-l))]) f[j] = f[j + (l & (-l))]; } } for (k = 1; k <= 20; k++) for (j = t; j > 0; j--) if ((j & p[k]) && (f[j] > f[j - p[k]] + o[k])) f[j] = f[j - p[k]] + o[k]; printf( %d , f[(1 << n) - 1]); return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { int n, cnt = 0; cin >> n; vector<vector<int>> adj(n); vector<int> deg(n); for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; x--, y--; adj[x].push_back(y); adj[y].push_back(x); deg[x]++, deg[y]++; } for (int i = 0; i < n; i++) if (deg[i] == 1) cnt++; else if (deg[i] == 2) { cnt = 0; break; } if ((long long)cnt * (cnt - 1) >= 2 * (n - 1)) cout << YES << n ; else cout << NO << n ; } int main() { ios_base ::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); solve(); return 0; }
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#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &p) { os << { << p.first << , << p.second << } ; return os; } const int N = 3e5 + 5; const int oo = 1e9 + 7; const int LOGN = 30; long long bigmod(long long a, long long p, long long m) { long long res = 1; long long x = a; while (p) { if (p & 1) { res = (res * x) % m; } x = (x * x) % m; p = p >> 1; } return res; } int basis[N][LOGN]; void insert_vec(int t, int x) { for (int i = LOGN - 1; i >= 0; i--) basis[t][i] = basis[t - 1][i]; for (int i = LOGN - 1; i >= 0; i--) { if ((x >> i) & 1) { if (!basis[t][i]) { basis[t][i] = x; return; } else { x ^= basis[t][i]; } } } } int ans(int t, int x) { int tot = t; for (int i = LOGN - 1; i >= 0; i--) { if (basis[t][i]) { tot--; if ((x >> i) & 1) x ^= basis[t][i]; } else { if ((x >> i) & 1) return 0; } } return bigmod(2, tot, oo); } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; for (int i = 1; i <= n; i++) { int x; cin >> x; insert_vec(i, x); } while (q--) { int l, x; cin >> l >> x; cout << ans(l, x) << n ; } }
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#include <bits/stdc++.h> using namespace std; int mod(int val) { return val > 0 ? val : -val; } int main() { int g[2], b[2]; cin >> g[0] >> g[1] >> b[0] >> b[1]; bool pass = false; if (((g[1] + 1) * 2 >= b[0]) && (b[0] - g[1]) > -2) { pass = true; } if ((g[0] + 1) * 2 >= b[1] && (b[1] - g[0]) > -2) { pass = true; } if (pass) { cout << YES << endl; } else { cout << NO << endl; } }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m, k; cin >> n >> m >> k; if (n > m) swap(n, m); set<long long> vals; for (long long i = 1; i <= n; ++i) { if (vals.count(n / i)) { for (long long j = n / i; j >= 1; --j) { vals.insert(j); } break; } vals.insert(n / i); } long long res = -1; int diff = 2; vals.insert(n); vals.insert(m); for (long long x : vals) { for (long long i = n / x - diff; i <= n / x + diff; ++i) { if (i < 0 || i >= n) continue; long long j = k - i; if (j < 0 || j >= m) continue; res = max(res, 1LL * (n / (i + 1)) * (m / (j + 1))); } for (long long i = x - diff; i <= x + diff; ++i) { if (i < 0 || i >= n) continue; long long j = k - i; if (j < 0 || j >= m) continue; res = max(res, 1LL * (n / (i + 1)) * (m / (j + 1))); } } if (k < n) res = max(res, 1LL * m * (n / (k + 1))); if (k < m) res = max(res, 1LL * n * (m / (k + 1))); cout << res << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 200009; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) { long long n, m; cin >> n >> m; long long a[n + 5]; long long na[n + 5]; for (long long i = 1; i <= n; i++) { cin >> a[i]; na[i] = a[i]; } sort(na + 1, na + n + 1); long long p[m + 5]; unordered_map<long long, long long> mp; for (long long i = 1; i <= m; i++) { cin >> p[i]; mp[p[i]] = 1; } for (long long i = 1; i <= n; i++) { for (long long i = 1; i < n; i++) { if (mp[i] == 1 && a[i] > a[i + 1]) { swap(a[i], a[i + 1]); } } } long long f = 1; for (long long i = 1; i <= n; i++) { if (a[i] != na[i]) { f = 0; cout << NO << n ; break; } } if (f == 1) { cout << YES << n ; } } return 0; }
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// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Fri May 9 13:48:22 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_182/clk_182_stub.v
// Design : clk_182
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_182(clk_200MHz, clk_182MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_200MHz,clk_182MHz,locked" */;
input clk_200MHz;
output clk_182MHz;
output locked;
endmodule
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__OR4B_FUNCTIONAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4b (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D_N ;
// Local signals
wire DN not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_FUNCTIONAL_V
|
module conmutacion
(
input [3:0] centenas,
input [3:0] decenas,
input [3:0] unidades,
input C,
input De,
input U,
input CLKOUTseg,
output reg [1:0] mostrar,
output reg [3:0] digito
);
reg logic0;
reg [1:0] titileo;
initial
begin
titileo = 0;
end
always@(posedge CLKOUTseg)
begin
if(C && De && U)
begin
/*if(titileo == 3)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(De && U)
begin
/*if(titileo == 1)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(U)
begin
titileo <= 1;
end
else
begin
titileo <= 0;
end
end
end
end
always@(posedge CLKOUTseg)
begin
case(titileo)
2'b00:
begin
mostrar = 2'b01;
digito = 0;
end
2'b01:
begin
mostrar = 2'b01;
digito = unidades;
end
2'b10:
begin
mostrar = 2'b10;
digito = decenas;
end
2'b11:
begin
mostrar = 2'b11;
digito = centenas;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = ((ans % m) * (a % m)) % m; b /= 2; a = ((a % m) * (a % m)) % m; } return ans % m; } long long a[10]; long long fac[202]; void factorial() { fac[0] = 1; for (int i = 1; i < 200; i++) { fac[i] = fac[i - 1] * i; fac[i] %= (long long)(1000 * 1000 * 1000 + 7); } } long long c(long long n, long long k) { long long nemo = fac[n]; long long deno = fac[k] * fac[n - k]; deno %= (long long)(1000 * 1000 * 1000 + 7); long long invdeno = pow(deno, (long long)(1000 * 1000 * 1000 + 7) - 2, (long long)(1000 * 1000 * 1000 + 7)); long long pro = nemo * invdeno; pro %= (long long)(1000 * 1000 * 1000 + 7); return pro; } long long dp[105][10]; long long solve(int len, int curnum) { if (len < 0) return 0; if (curnum == 9) { return len >= a[9]; } long long ans = 0; if (dp[len][curnum] != -1) return dp[len][curnum]; if (curnum == 0) { for (int i = a[curnum]; i < len; i++) { ans += solve(len - i, curnum + 1) * c(len - 1, i); ans %= (long long)(1000 * 1000 * 1000 + 7); } } else { for (int i = a[curnum]; i <= len; i++) { ans += solve(len - i, curnum + 1) * c(len, i); ans %= (long long)(1000 * 1000 * 1000 + 7); } } return dp[len][curnum] = (ans % (long long)(1000 * 1000 * 1000 + 7)); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; factorial(); for (int i = 0; i < 10; i++) cin >> a[i]; long long ans = 0; for (int i = 0; i <= n; i++) { if (i >= a[9]) dp[i][9] = 1; else dp[i][9] = 0; } for (int k = 0; k <= n; k++) { for (int j = 8; j >= 0; j--) { if (j != 0) { for (int l = a[j]; l <= k; l++) { dp[k][j] += dp[k - l][j + 1] * c(k, l); dp[k][j] %= (long long)(1000 * 1000 * 1000 + 7); } } else { for (int l = a[j]; l <= k; l++) { dp[k][j] += dp[k - l][j + 1] * c(k - 1, l); dp[k][j] %= (long long)(1000 * 1000 * 1000 + 7); } } } } for (int i = 1; i <= n; i++) { ans += dp[i][0]; ans %= (long long)(1000 * 1000 * 1000 + 7); } cout << ans; }
|
module i2s_clkctrl_apb (
input clk, // Interface clock
input reset_n, // asynchronous, active low
// APB
input [4:0] paddr, // apb address
input penable, // apb enable
input pwrite, // apb write strobe
input [31:0] pwdata, // apb data in
input psel, // apb select
output reg [31:0] prdata, // apb data out
output pready, // apb ready
// Clock inputs, synthesized in PLL or external TCXOs
input clk_48, // this clock, divided by mclk_devisor, should be 22.
input clk_44,
// In slave mode, an external master makes the clocks
input ext_bclk,
input ext_playback_lrclk,
input ext_capture_lrclk,
output master_slave_mode, // 1 = master, 0 (default) = slave
// Clock derived outputs
output clk_sel_48_44, // 1 = mclk derived from 44, 0 (default) mclk derived from 48
output mclk,
output bclk,
output playback_lrclk,
output capture_lrclk
);
/*
* Example: Input clock is 24.5760MHz
* mclk_divisor = 0 (divide by (0+1)*2=2) => mclk = 12.288MHz
* bclk_divisor = 3 (divide by (3+1)*2=8) => bclk = 3.072MHz
* lrclk_divisor = 15 (divide by (15*16+15+1)*2=512) => lrclk = 0.048MHz
*
* Example: Input clock is 33.8688MHz
* mclk_divisor = 0 (divide by (0+1)*2=2) => mclk = 16.9344MHz
* bclk_divisor = 5 (divide by (5+1)*2=12) => bclk = 2.8224MHz
* lrclk_divisor = 23 (divide by (23*16+15+1)*2=768 => lrclk = 0.0441MHz
*/
reg [31:0] cmd_reg1;
wire cmd_sel1 = psel && (paddr == 0);
reg [31:0] cmd_reg2;
wire cmd_sel2 = psel && (paddr == 4);
assign master_slave_mode = cmd_reg1[0]; // 1 = master, 0 (default) = slave
assign clk_sel_48_44 = cmd_reg1[1]; // 1 = mclk derived from 44, 0 (default) mclk derived from 48
wire cmd_reg2_wr = cmd_sel2 & pwrite & penable;
// Register access
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
cmd_reg1 <= 0;
cmd_reg2 <= 0;
end
else
begin
if (cmd_sel1 & pwrite & penable) // write cmd
cmd_reg1 <= pwdata;
else if (cmd_sel1 & ~pwrite & ~penable) // cmd readback
prdata <= cmd_reg1;
if (cmd_reg2_wr) // write cmd
cmd_reg2 <= pwdata;
else if (cmd_sel2 & ~pwrite & ~penable) // cmd readback
prdata <= cmd_reg2;
end
end
wire mclk48;
wire bclk48;
wire playback_lrclk48;
wire capture_lrclk48;
audio_clock_generator playback_gen48 (
.clk (clk_48),
.reset_n (reset_n),
.cmd_reg1 (cmd_reg1),
.cmd_reg2 (cmd_reg2),
.mclk (mclk48),
.bclk (bclk48),
.lrclk_clear(cmd_reg2_wr),
.lrclk1 (playback_lrclk48),
.lrclk2 (capture_lrclk48)
);
wire mclk44;
wire bclk44;
wire playback_lrclk44;
wire capture_lrclk44;
audio_clock_generator playback_gen44 (
.clk (clk_44),
.reset_n (reset_n & ~cmd_reg2_wr),
.cmd_reg1 (cmd_reg1),
.cmd_reg2 (cmd_reg2),
.mclk (mclk44),
.bclk (bclk44),
.lrclk_clear(cmd_reg2_wr),
.lrclk1 (playback_lrclk44),
.lrclk2 (capture_lrclk44)
);
// Output muxes
assign mclk = clk_sel_48_44 ? mclk44 : mclk48;
assign bclk = master_slave_mode
? (clk_sel_48_44 ? bclk44 : bclk48)
: ext_bclk;
assign playback_lrclk = master_slave_mode
? (clk_sel_48_44 ? playback_lrclk44 : playback_lrclk48)
: ext_playback_lrclk;
assign capture_lrclk = master_slave_mode
? (clk_sel_48_44 ? capture_lrclk44 : capture_lrclk48)
: ext_capture_lrclk;
// APB
assign pready = penable; // always ready (no wait states)
endmodule
module audio_clock_generator (
input clk,
input reset_n,
input [31:0] cmd_reg1,
input [31:0] cmd_reg2,
output mclk,
output bclk,
input lrclk_clear,
output lrclk1,
output lrclk2
);
wire [7:0] mclk_divisor = cmd_reg1[31:24]; // divide by (n + 1)*2
wire [7:0] bclk_divisor = cmd_reg1[23:16]; // divide by (n + 1)*2
wire [7:0] lrclk1_divisor = cmd_reg2[15:8]; // divide by (n + 1)*2*16
wire [7:0] lrclk2_divisor = cmd_reg2[7:0]; // divide by (n + 1)*2*16
clk_divider #(.N(8)) mclk_divider (
.clk (clk),
.reset_n (reset_n),
.max_count (mclk_divisor),
.q (mclk)
);
clk_divider #(.N(8)) bclk_divider (
.clk (clk),
.reset_n (reset_n),
.max_count (bclk_divisor),
.q (bclk)
);
clk_divider #(.N(12)) lrclk1_divider (
.clk (clk),
.reset_n (reset_n & ~lrclk),
.max_count ({lrclk1_divisor, 4'b1111}),
.q (lrclk1)
);
clk_divider #(.N(12)) lrclk2_divider (
.clk (clk),
.reset_n (reset_n & ~lrclk_clear),
.max_count ({lrclk2_divisor, 4'b1111}),
.q (lrclk2)
);
endmodule
module clk_divider #(parameter N = 8) (
input clk,
input reset_n,
input [N-1:0] max_count,
output reg q
);
reg [N-1:0] counter;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
q <= 0;
counter <= 0;
end
else
begin
if (counter == max_count)
begin
counter <= 0;
q <= ~q;
end
else
counter <= counter + 1;
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi_Once.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_2pi_Once
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Wrap_2pi_Once
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_2pi_Once
(
x,
wrap
);
input signed [31:0] x; // sfix32_En27
output signed [31:0] wrap; // sfix32_En27
wire signed [31:0] Two_Pi1_out1; // sfix32_En27
wire Relational_Operator_relop1;
wire signed [31:0] Two_Pi3_out1; // sfix32_En27
wire Relational_Operator1_relop1;
wire signed [31:0] Two_Pi2_out1; // sfix32_En27
wire signed [31:0] Add2_out1; // sfix32_En27
wire signed [31:0] Switch1_out1; // sfix32_En27
wire signed [31:0] Two_Pi_out1; // sfix32_En27
wire signed [31:0] Add1_out1; // sfix32_En27
wire signed [31:0] Switch_out1; // sfix32_En27
// Wrap 2pi Once
// <S25>/Two Pi1
assign Two_Pi1_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Relational Operator
assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 :
1'b0);
// <S25>/Two Pi3
assign Two_Pi3_out1 = 32'sb00000000000000000000000000000000;
// <S25>/Relational Operator1
assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 :
1'b0);
// <S25>/Two Pi2
assign Two_Pi2_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Add2
assign Add2_out1 = x + Two_Pi2_out1;
// <S25>/Switch1
assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x :
Add2_out1);
// <S25>/Two Pi
assign Two_Pi_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Add1
//
// <S25>/Position_Hi_Data_Type
assign Add1_out1 = x - Two_Pi_out1;
// <S25>/Switch
assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1 :
Add1_out1);
assign wrap = Switch_out1;
endmodule // controllerHdl_Wrap_2pi_Once
|
`timescale 1 ns / 1 ps
module PWM_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface PWM_AXI
parameter integer C_PWM_AXI_DATA_WIDTH = 32,
parameter integer C_PWM_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire pwm,
output wire interrupt,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface PWM_AXI
input wire pwm_axi_aclk,
input wire pwm_axi_aresetn,
input wire [C_PWM_AXI_ADDR_WIDTH-1 : 0] pwm_axi_awaddr,
input wire [2 : 0] pwm_axi_awprot,
input wire pwm_axi_awvalid,
output wire pwm_axi_awready,
input wire [C_PWM_AXI_DATA_WIDTH-1 : 0] pwm_axi_wdata,
input wire [(C_PWM_AXI_DATA_WIDTH/8)-1 : 0] pwm_axi_wstrb,
input wire pwm_axi_wvalid,
output wire pwm_axi_wready,
output wire [1 : 0] pwm_axi_bresp,
output wire pwm_axi_bvalid,
input wire pwm_axi_bready,
input wire [C_PWM_AXI_ADDR_WIDTH-1 : 0] pwm_axi_araddr,
input wire [2 : 0] pwm_axi_arprot,
input wire pwm_axi_arvalid,
output wire pwm_axi_arready,
output wire [C_PWM_AXI_DATA_WIDTH-1 : 0] pwm_axi_rdata,
output wire [1 : 0] pwm_axi_rresp,
output wire pwm_axi_rvalid,
input wire pwm_axi_rready
);
reg [C_PWM_AXI_DATA_WIDTH-1:0]duty_reg_latch;
wire [C_PWM_AXI_DATA_WIDTH-1:0]duty_reg;
wire [C_PWM_AXI_DATA_WIDTH-1:0]period_reg;
wire [C_PWM_AXI_DATA_WIDTH-1:0]ctrl_reg;
wire [C_PWM_AXI_DATA_WIDTH-1:0]status_reg;
// Instantiation of Axi Bus Interface PWM_AXI
PWM_v1_0_PWM_AXI # (
.C_S_AXI_DATA_WIDTH(C_PWM_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_PWM_AXI_ADDR_WIDTH)
) PWM_v1_0_PWM_AXI_inst (
.duty_reg_out(duty_reg),
.period_reg_out(period_reg),
.ctrl_reg_out(ctrl_reg),
.status_reg_out(status_reg),
.S_AXI_ACLK(pwm_axi_aclk),
.S_AXI_ARESETN(pwm_axi_aresetn),
.S_AXI_AWADDR(pwm_axi_awaddr),
.S_AXI_AWPROT(pwm_axi_awprot),
.S_AXI_AWVALID(pwm_axi_awvalid),
.S_AXI_AWREADY(pwm_axi_awready),
.S_AXI_WDATA(pwm_axi_wdata),
.S_AXI_WSTRB(pwm_axi_wstrb),
.S_AXI_WVALID(pwm_axi_wvalid),
.S_AXI_WREADY(pwm_axi_wready),
.S_AXI_BRESP(pwm_axi_bresp),
.S_AXI_BVALID(pwm_axi_bvalid),
.S_AXI_BREADY(pwm_axi_bready),
.S_AXI_ARADDR(pwm_axi_araddr),
.S_AXI_ARPROT(pwm_axi_arprot),
.S_AXI_ARVALID(pwm_axi_arvalid),
.S_AXI_ARREADY(pwm_axi_arready),
.S_AXI_RDATA(pwm_axi_rdata),
.S_AXI_RRESP(pwm_axi_rresp),
.S_AXI_RVALID(pwm_axi_rvalid),
.S_AXI_RREADY(pwm_axi_rready)
);
integer count=0;
integer max=4096;
reg enable=1'b0;
// Add user logic here
always@(posedge (pwm_axi_aclk))begin
if (ctrl_reg[0]==1)begin//Ctrl_reg 0 = enable
enable<=1;
max<=period_reg;
end
else
enable<=0;
if (ctrl_reg[1]==1)begin//Ctrl_reg 1 = hardware pwm
end
else begin
end
end
always@(posedge(pwm_axi_aclk))begin
if (enable==1'b1)begin
if (count<max)
count=count+1;
else begin
duty_reg_latch=duty_reg;//Latch duty cycle at end of window
count=0;
end
end
else
count=0;
end
assign pwm = duty_reg_latch < count ? 1'b1 : 1'b0;
assign interrupt = (count == max) ? 1'b1: 1'b0;
// User logic ends
endmodule
|
#include <bits/stdc++.h> int g[(1 << 22)][4], f[23], n, m, a, b; void output(int v, int u) { if (u == 0) return; if (v == 0) return; output(g[v][1], u - 1); printf( %d , g[v][2]); } int cnt(int v) { int ret = 0; for (; v; v >>= 1) if (v & 1) ret++; return ret; } int main(void) { memset(g, 127, sizeof(g)); scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d%d , &a, &b), f[a] |= 1 << (b - 1), f[b] |= 1 << (a - 1); for (int i = 1; i <= n; i++) f[i] |= 1 << (i - 1), g[f[i]][1] = 0, g[f[i]][2] = i, g[f[i]][3] = 0; for (int i = 1; i <= n; i++) g[f[i]][3]++; for (int i = 1; i <= n; i++) if (g[f[i]][3] == cnt(f[i])) g[f[i]][0] = 0; else g[f[i]][0] = 1; for (int i = 1; i <= (1 << n) - 1; i++) if (g[i][0]) for (int j = 1; j <= n; j++) if ((i | (1 << (j - 1))) == i) { int gf = i | f[j]; if (g[gf][0] > g[i][0] + 1) g[gf][0] = g[i][0] + 1, g[gf][1] = i, g[gf][2] = j; } printf( %d n , g[(1 << n) - 1][0]); output((1 << n) - 1, g[(1 << n) - 1][0]); printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_0_V
`define SKY130_FD_SC_LP__O2BB2A_0_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_0 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_0 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_0_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2000010; int a[N], pos[N], cnt[N]; long long ans[N], res; struct node { int l, r, idx; bool operator<(const node& x) const { if (pos[l] == pos[x.l]) return r < x.r; return l < x.l; } } q[N]; int L, R, n, m, k; void update(int x, int add) { if (add > 0) { res += cnt[a[x] ^ k]; cnt[a[x]]++; } else { cnt[a[x]]--; res -= cnt[a[x] ^ k]; } } int main() { scanf( %d%d%d , &n, &m, &k); int sz = sqrt(n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); a[i] ^= a[i - 1]; pos[i] = i / sz; } for (int i = 1; i <= m; ++i) { scanf( %d%d , &q[i].l, &q[i].r); q[i].idx = i; } sort(q + 1, q + m + 1); cnt[0] = 1; L = 1, R = 0, res = 0; for (int i = 1; i <= m; ++i) { while (q[i].l < L) update(--L - 1, 1); while (q[i].l > L) update(L++ - 1, -1); while (q[i].r < R) update(R--, -1); while (q[i].r > R) update(++R, 1); ans[q[i].idx] = res; } for (int i = 1; i <= m; ++i) printf( %I64d n , ans[i]); return 0; }
|
//-----------------------------------------------------------------
//
// Filename : xlclockdriver.v
//
// Date : 6/29/2004
//
// Description : Verilog description of a clock enable generator block.
// This code is synthesizable.
//
// Assumptions : period >= 1
//
// Mod. History : Translated VHDL clockdriver to Verilog
// : Added pipeline registers
//
// Mod. Dates : 6/29/2004
// : 12/14/2004
//
//-------------------------------------------------------------------
`timescale 1 ns / 10 ps
module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);
parameter signed [31:0] log_2_period = 1;
parameter signed [31:0] period = 2;
parameter signed [31:0] use_bufg = 1'b0;
parameter signed [31:0] pipeline_regs = 5;
input sysclk;
input sysclr;
input sysce;
output clk;
output clr;
output ce;
output ce_logic;
//A maximum value of 8 would allow register balancing to the tune of 10^8
//It is set to 8 since we do not have more than 10^8 nets in an FPGA
parameter signed [31:0] max_pipeline_regs = 8;
//Check if requested pipeline regs are greater than the max amount
parameter signed [31:0] num_pipeline_regs = (max_pipeline_regs > pipeline_regs)? pipeline_regs : max_pipeline_regs;
parameter signed [31:0] factor = num_pipeline_regs/period;
parameter signed [31:0] rem_pipeline_regs = num_pipeline_regs - (period * factor) + 1;
//Old constant values
parameter [log_2_period-1:0] trunc_period = ~period + 1;
parameter signed [31:0] period_floor = (period>2)? period : 2;
parameter signed [31:0] power_of_2_counter = (trunc_period == period) ? 1 : 0;
parameter signed [31:0] cnt_width = (power_of_2_counter & (log_2_period>1)) ? (log_2_period - 1) : log_2_period;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus1 = period_floor-2;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus2 = (period-3>0)? period-3 : 0;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus_regs = ((period-rem_pipeline_regs)>0)? (period-rem_pipeline_regs) : 0;
reg [cnt_width-1:0] clk_num;
reg temp_ce_vec;
wire [num_pipeline_regs:0] ce_vec;
wire [num_pipeline_regs:0] ce_vec_logic;
wire internal_ce;
wire internal_ce_logic;
reg cnt_clr;
wire cnt_clr_dly;
genvar index;
initial
begin
clk_num = 'b0;
end
assign clk = sysclk ;
assign clr = sysclr ;
// Clock Number Counter
always @(posedge sysclk)
begin : cntr_gen
if (sysce == 1'b1)
begin:hc
if ((cnt_clr_dly == 1'b1) || (sysclr == 1'b1))
begin:u1
clk_num = {cnt_width{1'b0}};
end
else
begin:u2
clk_num = clk_num + 1 ;
end
end
end
// Clear logic for counter
generate
if (power_of_2_counter == 1)
begin:clr_gen_p2
always @(sysclr)
begin:u1
cnt_clr = sysclr;
end
end
endgenerate
generate
if (power_of_2_counter == 0)
begin:clr_gen
always @(clk_num or sysclr)
begin:u1
if ( (clk_num == clk_for_ce_pulse_minus1) | (sysclr == 1'b1) )
begin:u2
cnt_clr = 1'b1 ;
end
else
begin:u3
cnt_clr = 1'b0 ;
end
end
end // block: clr_gen
endgenerate
synth_reg_w_init #(1, 0, 'b0000, 1)
clr_reg(.i(cnt_clr),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(cnt_clr_dly));
//Clock Enable Generation
generate
if (period > 1)
begin:pipelined_ce
always @(clk_num)
begin:np_ce_gen
if (clk_num == clk_for_ce_pulse_minus_regs)
begin
temp_ce_vec = 1'b1 ;
end
else
begin
temp_ce_vec = 1'b0 ;
end
end
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg(.i(ce_vec[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec[index]));
end //block ce_pipeline
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline_logic
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg_logic(.i(ce_vec_logic[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec_logic[index]));
end //block ce_pipeline
assign ce_vec_logic[num_pipeline_regs] = temp_ce_vec;
assign ce_vec[num_pipeline_regs] = temp_ce_vec;
assign internal_ce = ce_vec[0];
assign internal_ce_logic = ce_vec_logic[0];
end // block: pipelined_ce
endgenerate
generate
if (period > 1)
begin:period_greater_than_1
if (use_bufg == 1'b1)
begin:use_bufg
BUFG ce_bufg_inst(.I(internal_ce), .O(ce));
BUFG ce_logic_bufg_inst(.I(internal_ce_logic), .O(ce_logic));
end
else
begin:no_bufg
assign ce = internal_ce;
assign ce_logic = internal_ce_logic;
end
end
endgenerate
generate
if (period == 1)
begin:period_1
assign ce = sysce;
assign ce_logic = sysce;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (1 << 30) - 1; const int maxn = 100010; char s[maxn]; int calc(char a, char b) { int mx = 30; mx = min(mx, a > b ? a - b : b - a); mx = min(mx, a > b ? b + 26 - a : a + 26 - b); return mx; } int main() { scanf( %s , s); int len = strlen(s); int ans = 0; ans += calc( a , s[0]); for (int i = 0; i < len - 1; i++) ans += calc(s[i], s[i + 1]); printf( %d , ans); return 0; }
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// ============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_adder.v
// Title : Integer adder / subtractor with comparison flag generation
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_adder (
// ----- Inputs -------
adder_op_x,
adder_op_x_n,
operand_0_x,
operand_1_x,
// ----- Outputs -------
adder_result_x,
adder_carry_n_x,
adder_overflow_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
input adder_op_x_n; // Inverted version of adder_op_x
input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
wire [`LM32_WORD_RNG] adder_result_x;
output adder_carry_n_x; // Inverted carry
wire adder_carry_n_x;
output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
reg adder_overflow_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire a_sign; // Sign (i.e. positive or negative) of operand 0
wire b_sign; // Sign of operand 1
wire result_sign; // Sign of result
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_addsub addsub (
// ----- Inputs -----
.DataA (operand_0_x),
.DataB (operand_1_x),
.Cin (adder_op_x),
.Add_Sub (adder_op_x_n),
// ----- Ouputs -----
.Result (adder_result_x),
.Cout (adder_carry_n_x)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Extract signs of operands and result
assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
// Determine whether an overflow occured when performing a subtraction
always @(*)
begin
// +ve - -ve = -ve -> overflow
// -ve - +ve = +ve -> overflow
if ( (!a_sign & b_sign & result_sign)
|| (a_sign & !b_sign & !result_sign)
)
adder_overflow_x = `TRUE;
else
adder_overflow_x = `FALSE;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_PP_BLACKBOX_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_sincos_fused(clock, resetn, dataa, result_a, result_b, enable);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result_a; // sin
output [31:0] result_b; // cos
// Latency is 38.
fp_sincos_fused fused(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout_sin(result_a[31]),
.exponentout_sin(result_a[30:23]),
.mantissaout_sin(result_a[22:0]),
.signout_cos(result_b[31]),
.exponentout_cos(result_b[30:23]),
.mantissaout_cos(result_b[22:0]));
endmodule
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#include <bits/stdc++.h> using namespace std; template <class T> void max_swap(T& a, const T& b) { a = max(a, b); } template <class T> void min_swap(T& a, const T& b) { a = min(a, b); } const double EPS = 1e-8; const double PI = acos(-1.0); const int dx[] = {0, 1, 0, -1}; const int dy[] = {1, 0, -1, 0}; bool valid_pos(int x, int y, int w, int h) { return 0 <= x && x < w && 0 <= y && y < h; } int main() { ios::sync_with_stdio(false); string s, t; cin >> s >> t; int n = s.size(), m = t.size(); static int dp[5555][5555]; const int mod = 1000000007; for (int i = 0; i < n; ++i) { int sum = 0; for (int j = 0; j < m; ++j) { if (s[i] == t[j]) { (dp[i + 1][j + 1] += sum + 1) %= mod; } (sum += dp[i][j + 1]) %= mod; } } int res = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) (res += dp[i + 1][j + 1]) %= mod; cout << res << endl; }
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#include <bits/stdc++.h> template <typename T> std::istream& operator>>(std::istream& input, std::vector<T>& v) { for (T& a : v) input >> a; return input; } void answer(int v) { std::cout << v << n ; } void solve(const std::vector<size_t>& id) { int z = 0; std::unordered_map<size_t, size_t> x; for (const size_t a : id) { if (a == 0) continue; const size_t c = ++x[a]; if (c > 2) return answer(-1); z += (c == 2); } answer(z); } int main() { size_t n; std::cin >> n; std::vector<size_t> id(n); std::cin >> id; solve(id); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1010; int n, m, maxw, tot, w[maxn], b[maxn], fa[maxn], sumw[maxn], sumb[maxn], dp[maxn << 1][maxn], f[maxn]; vector<int> child[maxn]; vector<pair<int, int> > vec; unordered_set<int> ancestor; void init() { for (int i = 1; i <= n; i++) { fa[i] = i; sumw[i] = w[i]; sumb[i] = b[i]; } } int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } void unite(int x, int y) { x = find(x), y = find(y); if (x == y) return; fa[x] = y; sumw[y] += sumw[x]; sumb[y] += sumb[x]; } int main() { scanf( %d %d %d , &n, &m, &maxw); for (int i = 1; i <= n; i++) { scanf( %d , &w[i]); } for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); } init(); while (m--) { int x, y; scanf( %d %d , &x, &y); unite(x, y); } for (int i = 1; i <= n; i++) { child[find(i)].push_back(i); ancestor.insert(find(i)); } for (int x : ancestor) { int last = tot; for (int y : child[x]) { tot++; for (int z = 0; z <= maxw; z++) { dp[tot][z] = f[z]; if (z >= w[y]) { dp[tot][z] = max(dp[tot][z], f[z - w[y]] + b[y]); } } } tot++; for (int y = 0; y <= maxw; y++) { dp[tot][y] = f[y]; if (y >= sumw[x]) { dp[tot][y] = max(dp[tot][y], f[y - sumw[x]] + sumb[x]); } } for (int y = last + 1; y <= tot; y++) { for (int z = 0; z <= maxw; z++) { f[z] = max(f[z], dp[y][z]); } } } printf( %d n , *max_element(f, f + maxw + 1)); return 0; }
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#include <bits/stdc++.h> using namespace std; string solve(string s, int t) { while (t--) { for (int i = s.size() - 1; i >= 1; i--) { if (s[i] == G && s[i - 1] == B ) { swap(s[i], s[i - 1]); i--; } } } return s; } int main() { int n, t; cin >> n >> t; string s; cin >> s; cout << solve(s, t); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long maxn = 2e6 + 6; const long long MOD = 1e9 + 7; bool comparator(long long i, long long j) { return (i < j); } struct setCompare { bool operator()(const int64_t& lhs, const int64_t& rhs) const {} }; long long power(long long x, long long i) { long long ans = 1; while (i > 0) { if (i & 1) ans = (ans * x) % MOD; i >>= 1; x = (x * x) % MOD; } return ans; } long long power(long long x, long long i, long long mod) { long long ans = 1; while (i > 0) { if (i & 1) ans = (ans * x) % mod; i >>= 1; x = (x * x) % mod; } return ans; } long long modInverse(long long x, long long mod) { return power(x, mod - 2, mod); } bool isPalindrome(string s) { long long limit = s.length() / 2; for (long long i = 0; i < limit; i++) if (s[i] != s[s.length() - i - 1]) return false; return true; } long long gcd(long long x, long long y) { long long t; while (y != 0) t = x % y, x = y, y = t; return x; } bool isVowel(char ch) { if (ch == a || ch == i || ch == e || ch == u || ch == o || ch == y ) { return true; } return false; } bool isPrime(long long n) { long long root = sqrt(n); for (long long i = 2; i <= root; i++) if (n % i == 0) return 0; return 1; } long double getDisSquare(long double asdfg, long double qwert, long double gfdsa, long double trewq) { return ((asdfg - gfdsa) * (asdfg - gfdsa) + (qwert - trewq) * (qwert - trewq)); } bool isSquareHelper(long long asdfg, long long qwert, long long gfdsa, long long trewq, long long x3, long long y3, long long x4, long long y4) { long double d1, d2, d3, d4, d5, d6; d1 = getDisSquare(asdfg, qwert, gfdsa, trewq); d2 = getDisSquare(gfdsa, trewq, x3, y3); d3 = getDisSquare(x3, y3, x4, y4); d4 = getDisSquare(x4, y4, asdfg, qwert); if (d1 == d2 && d1 == d3 && d1 == d4) { d5 = getDisSquare(asdfg, qwert, x3, y3); d6 = getDisSquare(gfdsa, trewq, x4, y4); if (d5 == d6) { return 1; } } return 0; } bool isSquare(long long asdfg, long long qwert, long long gfdsa, long long trewq, long long x3, long long y3, long long x4, long long y4) { if (isSquareHelper(asdfg, qwert, gfdsa, trewq, x3, y3, x4, y4) || isSquareHelper(asdfg, qwert, gfdsa, trewq, x4, y4, x3, y3) || isSquareHelper(asdfg, qwert, x3, y3, gfdsa, trewq, x4, y4)) return 1; else return 0; } bool isEqualateralTriangle(long long asdfg, long long qwert, long long gfdsa, long long trewq, long long x3, long long y3) { long long d1 = getDisSquare(asdfg, qwert, gfdsa, trewq); long long d2 = getDisSquare(gfdsa, trewq, x3, y3); long long d3 = getDisSquare(x3, y3, asdfg, qwert); if (d1 == d2 && d1 == d3) { return 1; } else return 0; } bool isRightAngleTriangleHelper(long long asdfg, long long qwert, long long gfdsa, long long trewq, long long x3, long long y3) { long long d1 = getDisSquare(asdfg, qwert, gfdsa, trewq); long long d2 = getDisSquare(gfdsa, trewq, x3, y3); long long d3 = getDisSquare(x3, y3, asdfg, qwert); if (d2 == (d1 + d3)) { return 1; } return 0; } bool isRightAngleTriangle(long long asdfg, long long qwert, long long gfdsa, long long trewq, long long x3, long long y3) { if (isRightAngleTriangleHelper(asdfg, qwert, gfdsa, trewq, x3, y3) || isRightAngleTriangleHelper(gfdsa, trewq, x3, y3, asdfg, qwert) || isRightAngleTriangleHelper(x3, y3, asdfg, qwert, gfdsa, trewq)) return 1; return 0; } bool areCollinear(long long asdfg, long long qwert, long long gfdsa, long long trewq, long long x3, long long y3) { return ((x3 - asdfg) * (trewq - qwert) == (y3 - qwert) * (gfdsa - asdfg)); } long long n, a, b, c, t[maxn], k; void getInput() { cin >> n >> a >> b >> c >> k; for (long long i = 0; i < n; i++) cin >> t[i]; } void getAnswer() {} void solve() { sort(t, t + n); long long ans = 0; long long x, y; x = a / b; y = a % b; for (long long i = 0; i < n; i++) { if (b >= c) { ans += a; } else { long long tt = k - t[i]; ans += (a - b * tt + c * tt); } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) getInput(), solve(); return 0; }
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//======================================================================
//
// uart.v
// ------
// Top level wrapper for the uart core.
//
// A simple universal asynchronous receiver/transmitter (UART)
// interface. The interface contains 16 byte wide transmit and
// receivea buffers and can handle start and stop bits. But in
// general is rather simple. The primary purpose is as host
// interface for the coretest design. The core also has a
// loopback mode to allow testing of a serial link.
//
// Note that the UART has a separate API interface to allow
// a control core to change settings such as speed. But the core
// has default values to allow it to start operating directly
// after reset. No config should be needed.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module uart(
input wire clk,
input wire reset_n,
// External interface.
input wire rxd,
output wire txd,
// Internal receive interface.
output wire rxd_syn,
output [7 : 0] rxd_data,
input wire rxd_ack,
// Internal transmit interface.
input wire txd_syn,
input wire [7 : 0] txd_data,
output wire txd_ack,
// API interface.
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
// Debug output.
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// API addresses.
parameter ADDR_CORE_NAME0 = 8'h00;
parameter ADDR_CORE_NAME1 = 8'h01;
parameter ADDR_CORE_TYPE = 8'h02;
parameter ADDR_CORE_VERSION = 8'h03;
parameter ADDR_BIT_RATE = 8'h10;
parameter ADDR_DATA_BITS = 8'h11;
parameter ADDR_STOP_BITS = 8'h12;
// Core ID constants.
parameter CORE_NAME0 = 32'h75617274; // "uart"
parameter CORE_NAME1 = 32'h20202020; // " "
parameter CORE_TYPE = 32'h20202031; // " 1"
parameter CORE_VERSION = 32'h302e3031; // "0.01"
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 50 MHz, 9600 bps
// Divisor = 50*10E6 / 9600 = 5208
parameter DEFAULT_BIT_RATE = 16'd5208;
parameter DEFAULT_DATA_BITS = 4'h8;
parameter DEFAULT_STOP_BITS = 2'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [15 : 0] bit_rate_reg;
reg [15 : 0] bit_rate_new;
reg bit_rate_we;
reg [3 : 0] data_bits_reg;
reg [3 : 0] data_bits_new;
reg data_bits_we;
reg [1 : 0] stop_bits_reg;
reg [1 : 0] stop_bits_new;
reg stop_bits_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [15 : 0] bit_rate;
wire [1 : 0] stop_bits;
wire core_rxd;
wire core_txd;
wire core_rxd_syn;
wire [7 : 0] core_rxd_data;
wire core_rxd_ack;
wire core_txd_syn;
wire [7 : 0] core_txd_data;
wire core_txd_ack;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign txd = core_txd;
assign core_rxd = rxd;
assign rxd_syn = core_rxd_syn;
assign rxd_data = core_rxd_data;
assign core_rxd_ack = rxd_ack;
assign core_txd_syn = txd_syn;
assign core_txd_data = txd_data;
assign txd_ack = core_txd_ack;
assign read_data = tmp_read_data;
assign error = tmp_error;
assign debug = core_rxd_data;
//----------------------------------------------------------------
// core
//
// Instantiation of the uart core.
//----------------------------------------------------------------
uart_core core(
.clk(clk),
.reset_n(reset_n),
// Configuration parameters
.bit_rate(bit_rate_reg),
.data_bits(data_bits_reg),
.stop_bits(stop_bits_reg),
// External data interface
.rxd(core_rxd),
.txd(core_txd),
// Internal receive interface.
.rxd_syn(core_rxd_syn),
.rxd_data(core_rxd_data),
.rxd_ack(core_rxd_ack),
// Internal transmit interface.
.txd_syn(core_txd_syn),
.txd_data(core_txd_data),
.txd_ack(core_txd_ack)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
bit_rate_reg <= DEFAULT_BIT_RATE;
data_bits_reg <= DEFAULT_DATA_BITS;
stop_bits_reg <= DEFAULT_STOP_BITS;
end
else
begin
if (bit_rate_we)
begin
bit_rate_reg <= bit_rate_new;
end
if (data_bits_we)
begin
data_bits_reg <= data_bits_new;
end
if (stop_bits_we)
begin
stop_bits_reg <= stop_bits_new;
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The core API that allows an internal host to control the
// core functionality.
//----------------------------------------------------------------
always @*
begin: api
// Default assignments.
bit_rate_new = 16'h0000;
bit_rate_we = 0;
data_bits_new = 4'h0;
data_bits_we = 0;
stop_bits_new = 2'b00;
stop_bits_we = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
// Write operations.
case (address)
ADDR_BIT_RATE:
begin
bit_rate_new = write_data[15 : 0];
bit_rate_we = 1;
end
ADDR_DATA_BITS:
begin
data_bits_new = write_data[3 : 0];
data_bits_we = 1;
end
ADDR_STOP_BITS:
begin
stop_bits_new = write_data[1 : 0];
stop_bits_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
else
begin
// Read operations.
case (address)
ADDR_CORE_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_CORE_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_CORE_TYPE:
begin
tmp_read_data = CORE_TYPE;
end
ADDR_CORE_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
ADDR_BIT_RATE:
begin
tmp_read_data = {16'h0000, bit_rate_reg};
end
ADDR_DATA_BITS:
begin
tmp_read_data = {28'h0000000, data_bits_reg};
end
ADDR_STOP_BITS:
begin
tmp_read_data = {30'h0000000, stop_bits_reg};
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end
endmodule // uart
//======================================================================
// EOF uart.v
//======================================================================
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr(n + 1, -1); for (int i = 1; i <= n; i++) { int temp; cin >> temp; arr[i] = temp; } int ans = 0; vector<int> mini(n + 1, -1); vector<int> maxi(n + 1, -1); vector<int> equal(n + 1, -1); equal[1] = 1; mini[1] = 1; maxi[1] = 1; for (int i = 2; i <= n; i++) { if (arr[i] != arr[i - 1]) equal[i] = 1; else { equal[i] = equal[i - 1] + 1; mini[i] = mini[i - 1] + 1; maxi[i] = maxi[i - 1] + 1; } if (arr[i] > arr[i - 1]) { maxi[i] = max(mini[i - 1] + 1, equal[i - 1] + 1); mini[i] = 1; } if (arr[i] < arr[i - 1]) { mini[i] = max(maxi[i - 1] + 1, equal[i - 1] + 1); maxi[i] = 1; } int temp = max(mini[i], max(maxi[i], equal[i])); if (temp > ans) ans = temp; } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; vector<vector<int> > graph, trees, chains; vector<int> head, sub, mxs, mp, idx; int dfs(int ind = 0) { sub[ind] = 1; mxs[ind] = 0; for (auto u : graph[ind]) { sub[ind] += dfs(u); mxs[ind] = max(mxs[ind], sub[u]); } return sub[ind]; } void HLD(int ind = 0, int chain = 0) { pair<int, int> mx = {INT_MIN, INT_MIN}; if (chains[chain].empty()) head[chain] = ind; chains[chain].push_back(ind); mp[ind] = chain; idx[ind] = chains[chain].size() - 1; for (auto u : graph[ind]) { mx = max(mx, make_pair(sub[u], u)); } if (mx.first >= 0) { HLD(mx.second, chain); for (auto u : graph[ind]) { if (u == mx.second) continue; chains.push_back(vector<int>()); head.push_back(0); HLD(u, chains.size() - 1); } } } int x; void build(int n = 0, int l = 0, int r = chains[x].size() - 1) { if (l == r) { trees[x][n] = mxs[chains[x][l]]; return; } int md = (l + r) >> 1; build(2 * n + 1, l, md); build(2 * n + 2, md + 1, r); trees[x][n] = min(trees[x][2 * n + 1], trees[x][2 * n + 2]); } int K, ind; pair<bool, int> qry(int n = 0, int l = 0, int r = chains[x].size() - 1) { if (l == r) { return {K >= trees[x][n], chains[x][l]}; } int md = (l + r) >> 1; if (ind <= md && trees[x][2 * n + 1] <= K) { return qry(2 * n + 1, l, md); } else if (ind <= r && trees[x][2 * n + 2] <= K) return qry(2 * n + 2, md + 1, r); else return {false, -1}; } void s(int &x) { register int c = getchar(); x = 0; for (; (c < 48 || c > 57); c = getchar()) ; for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } } int main() { int N, Q, u, v; s(N), s(Q); graph.resize(N); mxs.resize(N); sub.resize(N); mp.resize(N); idx.resize(N); for (int i = 1; i < N; i++) { v = i; s(u); u--; graph[u].push_back(v); } dfs(); chains.push_back(vector<int>()); head.push_back(0); HLD(); trees.resize(chains.size()); for (x = 0; x < (int)chains.size(); x++) { trees[x].resize(4 * chains[x].size()); build(); } while (Q--) { s(v); v--; x = mp[v]; K = sub[v] / 2; printf( %d n , qry().second + 1); } return 0; }
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#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a > b) return a; return b; } long long min(long long a, long long b) { if (a < b) return a; return b; } const int MOD = 1e9 + 7, N = 102, L = 3005, INF = INT_MAX; pair<long long, long long> a[N]; long long dp[L][N][2]; int main() { int n, l; cin >> n >> l; for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } for (int i = 1; i <= l; i++) { for (int j = 0; j < n; j++) { if (a[j].first == i) dp[i][j][0] = 1; else if (a[j].first < i) { for (int c = 0; c < n; c++) { if (c == j) continue; if (a[c].second == a[j].first) dp[i][j][0] += dp[i - a[j].first][c][0]; if (a[c].first == a[j].first && a[c].first != a[c].second) dp[i][j][0] += dp[i - a[j].first][c][1]; dp[i][j][0] %= MOD; } } if (a[j].second == i) dp[i][j][1] = 1; else if (a[j].second < i) { for (int c = 0; c < n; c++) { if (c == j) continue; if (a[c].second == a[j].second) dp[i][j][1] += dp[i - a[j].second][c][0]; if (a[c].first == a[j].second && a[c].first != a[c].second) dp[i][j][1] += dp[i - a[j].second][c][1]; dp[i][j][1] %= MOD; } } } } long long ans = 0; for (int i = 0; i < n; i++) { ans += dp[l][i][0]; if (a[i].first != a[i].second) ans += dp[l][i][1]; ans %= MOD; } cout << ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int Nmax = 2e5 + 17; inline int sqr(int x) { return x * x; } int main(void) { int a[6]; for (int i = 0; i < 6; i++) cin >> a[i]; cout << sqr(a[0] + a[1] + a[2]) - sqr(a[0]) - sqr(a[2]) - sqr(a[4]); }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_TB_V
`define SKY130_FD_SC_HD__O211AI_TB_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o211ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__o211ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_TB_V
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#include <bits/stdc++.h> using namespace std; long long M; const int N_MAX = 2; template <class T> void mul(int n, const T A[N_MAX][N_MAX], const T x[N_MAX], T y[N_MAX]) { static T z[N_MAX]; for (int i = 0; i < (n); i++) { z[i] = 0; for (int j = 0; j < (n); j++) z[i] = (z[i] + A[i][j] * x[j]) % M; } for (int i = 0; i < (n); i++) y[i] = z[i]; } template <class T> void mul(int n, const T A[N_MAX][N_MAX], const T B[N_MAX][N_MAX], T C[N_MAX][N_MAX]) { static T tmp[N_MAX][N_MAX]; for (int i = 0; i < (n); i++) for (int j = 0; j < (n); j++) { tmp[i][j] = 0; for (int k = 0; k < (n); k++) tmp[i][j] = (tmp[i][j] + A[i][k] * B[k][j]) % M; } for (int i = 0; i < (n); i++) for (int j = 0; j < (n); j++) C[i][j] = tmp[i][j]; } template <class T> void pow(int n, const T A[N_MAX][N_MAX], long long m, T B[N_MAX][N_MAX]) { static T tmp[N_MAX][N_MAX]; for (int i = 0; i < (n); i++) for (int j = 0; j < (n); j++) { tmp[i][j] = A[i][j]; B[i][j] = (i == j ? 1 : 0); } for (int t = 0; m > 0; t++) { if (m & (1LL << t)) { mul(n, B, tmp, B); m -= 1LL << t; } mul(n, tmp, tmp, tmp); } } long long fib(long long n) { long long A[2][2] = {{1, 1}, {1, 0}}, x[2] = {1, 0}; pow(2, A, n - 1, A); mul(2, A, x, x); return x[0]; } int main() { long long l, r, k; cin >> M >> l >> r >> k; vector<long long> cand; for (long long i = 1; i * i <= r; i++) { cand.push_back(i); for (int j = -1; j <= 1; j++) { cand.push_back(l / i + j); cand.push_back(r / i + j); } } long long idx = 1; for (int i = 0; i < (cand.size()); i++) { long long a = cand[i]; if (a > 0 && r / a - (l - 1) / a >= k) idx = max(idx, a); } cout << fib(idx) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 200005; const int MOD = 1000000007; long long fun(long long a, long long b) { if (a > b) return a; return b; } void swp(long long *a, long long *b) { long long temp = *a; *a = *b; *b = temp; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); ; int n; cin >> n; char ch; long long x, y; cin >> ch >> x >> y; if (x > y) swp(&x, &y); long long mx = x, my = y; n--; while (n--) { cin >> ch >> x >> y; if (x > y) swp(&x, &y); if (ch == + ) { mx = fun(mx, x); my = fun(my, y); } else { if ((x >= mx && y >= my) || (x >= my && y >= mx)) cout << YES n ; else cout << NO n ; } } }
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#include <bits/stdc++.h> using namespace std; int b, d, ct; int gcd(int x, int y) { return y ? gcd(y, x % y) : x; } int main() { cin >> b >> d; while (gcd(b, d) > 1) { d /= gcd(b, d); ++ct; } if (d == 1) cout << 2-type n << ct << n ; else if (!ct && b % d == 1) cout << 3-type n ; else if (!ct && b % d == d - 1) cout << 11-type n ; else if ((b - 1) * (b + 1) / (b % 2 + 1) % d == 0) cout << 6-type n ; else cout << 7-type n ; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:35:14 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_2_0_stub.v
// Design : design_1_axi_gpio_2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o,
gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[7:0],gpio_io_o[7:0],gpio_io_t[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_strehbi_DSP48_5(
input [8 - 1:0] in0,
input [22 - 1:0] in1,
input [30 - 1:0] in2,
output [32 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $signed(in1);
assign b = $signed(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_strehbi(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_strehbi_DSP48_5 hls_contrast_strehbi_DSP48_5_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 18 10:48:44 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_rxn1, srio_rxp1, srio_txn0, srio_txp0,
srio_txn1, srio_txp1, s_axis_iotx_tvalid, s_axis_iotx_tready, s_axis_iotx_tlast,
s_axis_iotx_tdata, s_axis_iotx_tkeep, s_axis_iotx_tuser, m_axis_iorx_tvalid,
m_axis_iorx_tready, m_axis_iorx_tlast, m_axis_iorx_tdata, m_axis_iorx_tkeep,
m_axis_iorx_tuser, s_axi_maintr_rst, s_axi_maintr_awvalid, s_axi_maintr_awready,
s_axi_maintr_awaddr, s_axi_maintr_wvalid, s_axi_maintr_wready, s_axi_maintr_wdata,
s_axi_maintr_bvalid, s_axi_maintr_bready, s_axi_maintr_bresp, s_axi_maintr_arvalid,
s_axi_maintr_arready, s_axi_maintr_araddr, s_axi_maintr_rvalid, s_axi_maintr_rready,
s_axi_maintr_rdata, s_axi_maintr_rresp, sim_train_en, force_reinit, phy_mce,
phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset, phy_debug, gtrx_disperr_or,
gtrx_notintable_or, port_error, port_timeout, srio_host, port_decode_error, deviceid,
idle2_selected, phy_lcl_master_enable_out, buf_lcl_response_only_out,
buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out, phy_lcl_phy_next_fm_out,
phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out, phy_lcl_phy_rcvd_buf_stat_out,
phy_lcl_maint_only_out, port_initialized, link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_txn0,srio_txp0,srio_txn1,srio_txp1,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
input srio_rxn1;
input srio_rxp1;
output srio_txn0;
output srio_txp0;
output srio_txn1;
output srio_txp1;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct data { int u, v, w; } p[400500]; int father[200100]; int use[200100]; int coo(struct data a, struct data b) { if (a.w > b.w) return 1; return 0; } int find(int x) { return x == father[x] ? x : father[x] = find(father[x]); } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) father[i] = i; for (int i = 1; i <= m; i++) { scanf( %d%d%d , &p[i].u, &p[i].v, &p[i].w); } sort(p + 1, p + m + 1, coo); long long ans = 0; for (int i = 1; i <= m; i++) { int x = find(p[i].u), y = find(p[i].v); if (use[x] && use[y]) continue; if (x == y) use[x] = 1; else { father[x] = y; use[y] |= use[x]; } ans += p[i].w; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; double calcC(int N, int M) { if (M > N) return 0; M = min(N - M, M); double res = 1; for (int i = 1; i <= M; ++i) res *= N - M + i, res /= i; return res; } int main() { int N, M; while (cin >> N >> M) { double result = 0; for (int k = 1; k <= N; ++k) { double tmp = 1; tmp = calcC(M, k) * calcC(N * M - M, N - k) * k * k; tmp /= calcC(N * M, N) * N * N; result += tmp; } result *= N; cout << setprecision(10) << result << endl; } }
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } template <typename T> void printVec(const T &v, char sep = ) { for (auto &i : v) cout << i << sep; } template <typename T> void printVecPair(const T &v, char sep = ) { for (auto &i : v) cout << i.first << << i.second << sep; } int n, k; vector<string> dig; string number[10]; int convert(string s1, string s2) { int ans = 0; for (int i = 0; i < 7; i++) { if (s1[i] != s2[i]) { if (s1[i] == 0 ) ans++; else return -1; } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; dig.resize(n); number[0] = 1110111 ; number[1] = 0010010 ; number[2] = 1011101 ; number[3] = 1011011 ; number[4] = 0111010 ; number[5] = 1101011 ; number[6] = 1101111 ; number[7] = 1010010 ; number[8] = 1111111 ; number[9] = 1111011 ; for (int i = 0; i < n; cin >> dig[i++]) ; vector<vector<bool>> dp(n, vector<bool>(k + 1)); for (int i = 0; i <= 9; i++) { int cost = convert(dig[n - 1], number[i]); if (cost != -1 && cost <= k) dp[n - 1][cost] = true; } for (int i = n - 2; i >= 0; i--) { for (int j = 0; j <= k; j++) { for (int d = 0; d <= 9; d++) { int cost = convert(dig[i], number[d]); if (cost != -1 && j - cost >= 0 && dp[i + 1][j - cost]) { dp[i][j] = true; } } } } vector<int> ans(n); for (int i = 0; i < n; i++) { bool flag = 0; for (int d = 9; d >= 0; d--) { int cost = convert(dig[i], number[d]); if (cost != -1 && k >= cost && i != n - 1 && dp[i + 1][k - cost]) { flag = 1; ans[i] = d; k -= cost; break; } if (cost == k && i == n - 1) { ans[i] = d; flag = 1; k -= cost; break; } } if (!flag) { cout << -1 n ; return 0; } } for (int i = 0; i < n; i++) cout << ans[i]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { int n, e; set<int> v; map<int, int> m; cin >> n; for (long long int i = 0; i < n; i++) { cin >> e; m[e]++; if (m[e] == 1) v.insert(e); } int np = 0, ps = 0; while (!v.empty()) { ps = 0; for (map<int, int>::iterator itm = m.begin(); itm != m.end(); itm++) { while (itm->second != 0 && itm->first >= ps) { itm->second -= 1; ps += 1; } if (itm->second == 0) v.erase(itm->first); } np++; } cout << np; } return 0; }
|
#include <bits/stdc++.h> const int SIZE = 5e5 + 5; using namespace std; vector<pair<int, int> > v; set<pair<int, int> > H; bool used[SIZE]; int b[SIZE]; int main() { int(n); scanf( %d , &n); for (int i = 0; i < (n); ++i) { int(x); scanf( %d , &x); v.push_back(make_pair(x, i)); H.insert(make_pair(i, x)); } long long an = 0; sort((v).begin(), (v).end()); for (int i = 0; i < (((int)(v).size())); ++i) { if (v[i].second == 0 || v[i].second == n - 1) continue; set<pair<int, int> >::iterator it = H.lower_bound(make_pair(v[i].second, 0)); set<pair<int, int> >::iterator it2 = it; int now = it->second; it2--; int tmp = it2->second; it2++; it2++; tmp = min(it2->second, tmp); if (now <= tmp) { used[i] = 1; an += tmp; H.erase(it); } } int bn = 0; for (set<pair<int, int> >::iterator it = H.begin(); it != H.end(); it++) { b[bn++] = it->second; } if (bn > 2) { sort(b, b + bn); for (int i = 0; i + 2 < bn; i++) an += b[i]; } cout << an << endl; return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_iobuf
(
input ADC_CLK,
input ADC_DCO_P, ADC_DCO_N,
(* IOB="TRUE" *)
output reg ADC_DCO,
input ADC_FCO_P, ADC_FCO_N,
(* IOB="TRUE" *)
output reg ADC_FCO,
(* IOB="TRUE" *)
input ADC_ENC,
output ADC_ENC_P, ADC_ENC_N,
input [3:0] ADC_IN_P, ADC_IN_N,
output [13:0] ADC_IN0, ADC_IN1, ADC_IN2, ADC_IN3
);
(* IOB="TRUE" *)
wire ADC_DCO_BUF;
(* IOB="TRUE" *)
wire ADC_FCO_BUF;
(* IOB="TRUE" *)
wire [3:0] ADC_IN_BUF;
(* IOB="TRUE" *)
wire ADC_ENC_BUF;
(* IOB="TRUE" *)
reg [3:0] ADC_IN;
// I/O BUFFERS
always@(negedge ADC_CLK)
ADC_DCO <= ADC_DCO_BUF;
always@(negedge ADC_CLK)
ADC_FCO <= ADC_FCO_BUF;
always@(negedge ADC_CLK)
ADC_IN <= ADC_IN_BUF;
//always@(negedge ADC_CLK)
// ADC_ENC_BUF <= ADC_ENC;
assign ADC_ENC_BUF = ADC_ENC;
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_FCO (
.O(ADC_FCO_BUF), // Clock buffer output
.I(ADC_FCO_P), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_FCO_N) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS // Specify the input I/O standard
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
)
IBUFDS_ADC_DCO (
.O(ADC_DCO_BUF), // Buffer output
.I(ADC_DCO_P), // Diff_p buffer input (connect directly to top-level port)
.IB(ADC_DCO_N) // Diff_n buffer input (connect directly to top-level port)
);
//BUFG ADC_BUFG_INST (.I(ADC_FCO_PB), .O(ADC_FCO));
OBUFDS #(
.IOSTANDARD("LVDS_25") // Specify the output I/O standard
) OBUFDS_ADC_ENC (
.O(ADC_ENC_P), // Diff_p output (connect directly to top-level port)
.OB(ADC_ENC_N), // Diff_n output (connect directly to top-level port)
.I(ADC_ENC_BUF) // Buffer input
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_0 (
.O(ADC_IN_BUF[0]), // Clock buffer output
.I(ADC_IN_P[0]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[0]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_1 (
.O(ADC_IN_BUF[1]), // Clock buffer output
.I(ADC_IN_P[1]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[1]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_2 (
.O(ADC_IN_BUF[2]), // Clock buffer output
.I(ADC_IN_P[2]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[2]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_3 (
.O(ADC_IN_BUF[3]), // Clock buffer output
.I(ADC_IN_P[3]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[3]) // Diff_n clock buffer input (connect directly to top-level port)
);
reg [1:0] fco_sync;
always@(negedge ADC_CLK) begin
fco_sync <= {fco_sync[0],ADC_FCO};
end
wire adc_des_rst;
assign adc_des_rst = fco_sync[0] & !fco_sync[1] ;
reg [15:0] adc_des_cnt;
always@(negedge ADC_CLK) begin
if(adc_des_rst)
adc_des_cnt[0] <= 1;
else
adc_des_cnt <= {adc_des_cnt[14:0],1'b0};
end
wire adc_load;
assign adc_load = adc_des_cnt[12];
reg [13:0] adc_out_sync [3:0];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: gen
reg [13:0] adc_des;
always@(negedge ADC_CLK) begin
adc_des <= {adc_des[12:0],ADC_IN[i]};
end
reg [13:0] adc_des_syn;
always@(negedge ADC_CLK) begin
if(adc_load)
adc_des_syn <= adc_des;
end
always@(posedge ADC_ENC)
adc_out_sync[i] <= adc_des_syn;
end
endgenerate
assign ADC_IN0 = adc_out_sync[0];
assign ADC_IN1 = adc_out_sync[1];
assign ADC_IN2 = adc_out_sync[2];
assign ADC_IN3 = adc_out_sync[3];
`ifdef SYNTHESIS_
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(ADC_CLK),
.TRIG0({ADC_IN0, adc_load, adc_des_rst, fco_sync, ADC_IN[0]})
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; bool func(pair<long long,long long> &fi,pair<long long,long long>&se){ return fi.first<se.first; } int main() { int t=1; cin>>t; while(t--){ long long a,b,n; cin>>a>>b>>n; pair<long long,long long>arr[n]; for(int i=0;i<n;i++){ cin>>arr[i].first; } for(int i=0;i<n;i++){ cin>>arr[i].second; } sort(arr,arr+n,func); bool gamovida=true; for(int i=0;i<n;i++){ int num=arr[i].second/a; if(num*a<arr[i].second)num++; b-=arr[i].first*num; if(b<=0&&i!=n-1){ gamovida=false; } if(b<=0&&i==n-1){ if(b+arr[i].first<=0){ gamovida=false; } } } if(gamovida==false){ cout<< NO <<endl; continue; } if(gamovida==false){ cout<< NO <<endl; }else{ cout<< YES <<endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bitset<501> bt[1010]; int c[505]; int ans[250001], tot; int main() { tot = 0; int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &c[i]); bt[0].set(0); int maxn = 0; for (int i = 1; i <= n; i++) { int lim = maxn; for (int j = lim; j >= 0; j--) { if (j + c[i] > k) continue; bt[j + c[i]] |= bt[j]; bt[j + c[i]] |= bt[j] << c[i]; } maxn = maxn + c[i]; } for (int i = 0; i <= 500; i++) { if (bt[k].test(i)) { ans[tot++] = i; } } printf( %d n , tot); for (int i = 0; i < tot; i++) { printf( %d , ans[i]); if (i == tot - 1) printf( n ); else printf( ); } }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001
) (
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK,
input wire DI,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire EXT_ENABLE,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
timestamp_core #(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER)
) i_timestamp_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK(CLK),
.DI(DI),
.TIMESTAMP_OUT(TIMESTAMP_OUT),
.EXT_TIMESTAMP(EXT_TIMESTAMP),
.EXT_ENABLE(EXT_ENABLE),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, res = 0, cp = 0, cn = 0, cz = 0; cin >> n; vector<long long> arr(n); for (long long i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] > 0) cp++; else if (arr[i] < 0) cn++; else cz++; } if (cp > (cn + cz)) { cout << 1 ; } else if (cn > (cp + cz)) { cout << -1 ; } else { if (cp == (cn + cz) && n % 2 == 0) cout << 1 ; else if (cn == (cp + cz) && n % 2 == 0) cout << -1 ; else cout << 0 ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_LP_V
`define SKY130_FD_SC_LP__NAND2_LP_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_lp (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_lp (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_LP_V
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_phy_dm_iob.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:17 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - To fix timing issues with Synplicity 9.6.1, syn_preserve
// attribute added for the instance u_dm_ce. PK. 11/11/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dm_iob
(
input clk90,
input dm_ce,
input mask_data_rise,
input mask_data_fall,
output ddr_dm
);
wire dm_out;
wire dm_ce_r;
FDRSE_1 u_dm_ce
(
.Q (dm_ce_r),
.C (clk90),
.CE (1'b1),
.D (dm_ce),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve=1 */;
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("SAME_EDGE")
)
u_oddr_dm
(
.Q (dm_out),
.C (clk90),
.CE (dm_ce_r),
.D1 (mask_data_rise),
.D2 (mask_data_fall),
.R (1'b0),
.S (1'b0)
);
OBUF u_obuf_dm
(
.I (dm_out),
.O (ddr_dm)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int x, y, n, d, x_i, y_i; vector<pair<int, int> > v; double dist(double x1, double y1) { return sqrt(pow(x1, 2) + pow(y1, 2)); } int a[605][605]; int f(int _x, int _y) { if (a[200 + _x][200 + _y] == -1) { int tmp = 1; if (dist(_x, _y) <= d) { for (auto _i : v) { if (f(_x + _i.first, _y + _i.second)) { tmp = 0; break; } } } else { tmp = 0; } a[200 + _x][200 + _y] = tmp; } return a[200 + _x][200 + _y]; } int main() { ios::sync_with_stdio(0); cin >> x >> y >> n >> d; (memset(a, -1, sizeof(a))); for (int(i) = (0); (i) < (n); (i)++) { cin >> x_i >> y_i; v.push_back({x_i, y_i}); } cout << (!f(x, y) ? Anton : Dasha ) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, z; int sol; int s[100009]; cin >> x >> y; s[0] = 0; for (int i = 1; i < x; i++) { cin >> z; s[i] = z + s[i - 1]; } sol = s[y]; for (int i = y + 1; i < x; i++) { sol = min(sol, s[i] - s[i - y]); } cout << sol << endl; }
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#include <bits/stdc++.h> using namespace std; struct Medianer { priority_queue<int> low; priority_queue<int, vector<int>, greater<int> > high; Medianer() {} int getMedian() { return low.top(); } void insert(int a) { if (low.empty()) low.push(a); else if (a > low.top()) { high.push(a); } else low.push(a); while (low.size() > high.size()) { high.push(low.top()); low.pop(); } while (low.size() < high.size()) { low.push(high.top()); high.pop(); } } size_t size() { return low.size() + high.size(); } }; Medianer *merge(Medianer *a, Medianer *b) { if (a->size() < b->size()) swap(a, b); while (!b->low.empty()) { a->insert(b->low.top()); b->low.pop(); } while (!b->high.empty()) { a->insert(b->high.top()); b->high.pop(); } delete b; return a; } int main() { int N; cin >> N; vector<int> data(N, 0); copy_n(istream_iterator<int>(cin), N, data.begin()); vector<Medianer *> meds; for (int i = 0; i < N; ++i) { Medianer *cur = new Medianer(); cur->insert(data[i]); while (!meds.empty() && cur->getMedian() < meds.back()->getMedian()) { cur = merge(meds.back(), cur); meds.pop_back(); } meds.push_back(cur); } unsigned long long ret = 0; for (int i = 0, j = 0; i < (int)meds.size(); ++i) { for (int k = 0; k < (int)meds[i]->size(); ++k, ++j) { ret += abs(data[j] - meds[i]->getMedian()); } delete meds[i]; } cout << ret; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, d; int v[50 + 5]; bool F[5000000 + 5]; int main() { scanf( %d%d , &n, &d); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); F[0] = true; int sum = 0; for (int i = 1; i <= n; i++) { sum += v[i]; for (int j = sum; j >= v[i]; j--) F[j] |= F[j - v[i]]; } int ans = 0, day = 0; bool found = false; while (1) { for (int i = d; i >= 1; i--) { if (F[ans + i]) { ans += i; day++; found = true; break; } } if (!found) break; else found = false; } printf( %d %d n , ans, day); return 0; }
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#include <bits/stdc++.h> using namespace std; long long ans = 0; string s; int main() { ios_base::sync_with_stdio(false); cin >> s; int id = -1; for (int i = 0; i < (int)s.length(); i++) { for (int j = 1; j <= 4 && i - 2 * j >= 0; j++) if (s[i] == s[i - j] && s[i - j] == s[i - 2 * j]) id = max(id, i - 2 * j); ans += id + 1; } cout << ans; return 0; }
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