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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int maxN = 1 << 18; template <class T1, class T2> inline void remax(T1& a, T2 b) { a = max(a, (T1)b); } int deg[maxN], fat[maxN]; vector<int> G[maxN]; queue<int> Q; long long w[maxN]; pair<long long, int> leg[2][maxN]; void solve() { int n, m; scanf( %d%d , &n, &m); for (int i = (1); i < (int)(n + 1); i++) scanf( %lld , w + i); bool tree = m == n - 1; while (m--) { int a, b; scanf( %d%d , &a, &b); G[a].push_back(b); G[b].push_back(a); deg[a]++, deg[b]++; } int s, prv = 0; scanf( %d , &s); if (tree) deg[s] = maxN; for (int i = (1); i < (int)(n + 1); i++) if (deg[i] == 1) Q.push(i); while (!Q.empty()) { int v = Q.front(); Q.pop(); for (int u : G[v]) if (deg[u] > 1) { pair<long long, int> prop = {leg[0][v].first + w[v], v}; fat[v] = u; if (leg[0][u].first <= prop.first) leg[1][u] = leg[0][u], leg[0][u] = prop; else if (leg[1][u].first < prop.first) leg[1][u] = prop; if (--deg[u] == 1) Q.push(u); } } long long res = 0, finish = 0; while (deg[s] < 2) { res += w[s]; remax(finish, leg[0][s].second == prv ? leg[1][s].first : leg[0][s].first); prv = s; s = fat[s]; } remax(finish, leg[0][s].second == prv ? leg[1][s].first : leg[0][s].first); for (int i = (1); i < (int)(n + 1); i++) if (deg[i] > 1) { res += w[i]; if (i != s) remax(finish, leg[0][i].first); } res += finish; printf( %lld n , res); } int main() { int t; t = 1; while (t--) solve(); return 0; }
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// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:v_axi4s_vid_out:3.0
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_v_axi4s_vid_out_0_0 (
aclk,
rst,
aclken,
aresetn,
s_axis_video_tdata,
s_axis_video_tvalid,
s_axis_video_tready,
s_axis_video_tuser,
s_axis_video_tlast,
fid,
vid_io_out_clk,
vid_io_out_ce,
vid_active_video,
vid_vsync,
vid_hsync,
vid_vblank,
vid_hblank,
vid_field_id,
vid_data,
vtg_vsync,
vtg_hsync,
vtg_vblank,
vtg_hblank,
vtg_active_video,
vtg_field_id,
vtg_ce,
locked,
wr_error,
empty
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst_intf RST" *)
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken_intf CE" *)
input wire aclken;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_intf RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_in TDATA" *)
input wire [15 : 0] s_axis_video_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_in TVALID" *)
input wire s_axis_video_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_in TREADY" *)
output wire s_axis_video_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_in TUSER" *)
input wire s_axis_video_tuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_in TLAST" *)
input wire s_axis_video_tlast;
input wire fid;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 vid_io_out_clk_intf CLK" *)
input wire vid_io_out_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 vid_io_out_ce_intf CE" *)
input wire vid_io_out_ce;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out ACTIVE_VIDEO" *)
output wire vid_active_video;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out VSYNC" *)
output wire vid_vsync;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out HSYNC" *)
output wire vid_hsync;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out VBLANK" *)
output wire vid_vblank;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out HBLANK" *)
output wire vid_hblank;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out FIELD" *)
output wire vid_field_id;
(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_out DATA" *)
output wire [15 : 0] vid_data;
(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_in VSYNC" *)
input wire vtg_vsync;
(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_in HSYNC" *)
input wire vtg_hsync;
(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_in VBLANK" *)
input wire vtg_vblank;
(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_in HBLANK" *)
input wire vtg_hblank;
(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_in ACTIVE_VIDEO" *)
input wire vtg_active_video;
(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_in FIELD" *)
input wire vtg_field_id;
output wire vtg_ce;
output wire locked;
output wire wr_error;
output wire empty;
v_axi4s_vid_out_v3_0_axi4s_vid_out_top #(
.C_S_AXIS_VIDEO_DATA_WIDTH(8),
.C_S_AXIS_VIDEO_FORMAT(0),
.VID_OUT_DATA_WIDTH(16),
.C_S_AXIS_VIDEO_TDATA_WIDTH(16),
.RAM_ADDR_BITS(10),
.HYSTERESIS_LEVEL(12),
.FILL_GUARDBAND(3),
.VTG_MASTER_SLAVE(1)
) inst (
.aclk(aclk),
.rst(rst),
.aclken(aclken),
.aresetn(aresetn),
.s_axis_video_tdata(s_axis_video_tdata),
.s_axis_video_tvalid(s_axis_video_tvalid),
.s_axis_video_tready(s_axis_video_tready),
.s_axis_video_tuser(s_axis_video_tuser),
.s_axis_video_tlast(s_axis_video_tlast),
.fid(fid),
.vid_io_out_clk(vid_io_out_clk),
.vid_io_out_ce(vid_io_out_ce),
.vid_active_video(vid_active_video),
.vid_vsync(vid_vsync),
.vid_hsync(vid_hsync),
.vid_vblank(vid_vblank),
.vid_hblank(vid_hblank),
.vid_field_id(vid_field_id),
.vid_data(vid_data),
.vtg_vsync(vtg_vsync),
.vtg_hsync(vtg_hsync),
.vtg_vblank(vtg_vblank),
.vtg_hblank(vtg_hblank),
.vtg_active_video(vtg_active_video),
.vtg_field_id(vtg_field_id),
.vtg_ce(vtg_ce),
.locked(locked),
.wr_error(wr_error),
.empty(empty)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int n, a, b; int check(int p) { int res; res = a / p + b / p; if (a / p == 0 || b / p == 0) return 0; if (res >= n) return 1; else return 0; } int main() { int l, r, mid; scanf( %d%d%d , &n, &a, &b); r = a + b; l = 1; while (r - l > 1) { mid = (r + l) / 2; if (check(mid)) l = mid; else r = mid; } printf( %d n , l); return 0; }
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// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_ad.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No user `defines in this module
module ent_ad
//
// Generated Module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
wire port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
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#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, a[N], place[N], BIT[N]; long long inverse, res[N]; set<int> firstHalf, secondHalf; long long sumFirst = 0, sumSecond = 0; long long fenwickGet(int x) { long long res = 0; for (; x <= n; x += x & -x) res += BIT[x]; return res; } void stable(set<int>& f, set<int>& s) { while (f.size() > s.size()) { int leftLarge = *f.rbegin(); f.erase(leftLarge); s.insert(leftLarge); sumFirst -= leftLarge; sumSecond += leftLarge; } while (f.size() < s.size()) { int rightSmall = *s.begin(); s.erase(rightSmall); f.insert(rightSmall); sumFirst += rightSmall; sumSecond -= rightSmall; } } void fenwickUpdate(int x) { for (; x; x -= x & -x) BIT[x] += 1; } long long sol(int cur) { inverse += fenwickGet(cur); fenwickUpdate(cur); if (firstHalf.size() > 0) { if (cur > *firstHalf.rbegin()) { secondHalf.insert(cur); sumSecond += cur; } else { firstHalf.insert(cur); sumFirst += cur; } } else { firstHalf.insert(cur); sumFirst += cur; } stable(firstHalf, secondHalf); long long middle = *firstHalf.rbegin(); long long n = firstHalf.size(), m = secondHalf.size(); return inverse + middle * n - sumFirst - n * (n - 1) / 2 + sumSecond - middle * m - m * (m + 1) / 2; } void solve() { inverse = 0; for (int i = 1; i <= n; ++i) { char c = (i == n ? n : ); cout << sol(place[i]) << c; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); place[a[i]] = i; } solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; for (int i = 1; i <= 400; i++) s += to_string(i); int n; cin >> n; cout << s[n - 1]; }
|
// dtb_daq.v
`timescale 1 ns / 1 ps
module dtb_daq
(
input clk_daq,
input clk_sys,
input [7:0]sclk,
input reset,
input sync,
// control
input [1:0]ctrl_adc_address,
input ctrl_adc_write,
input [15:0]ctrl_adc_writedata,
input ctrl_adc_read,
output [15:0]ctrl_adc_readdata,
input [3:0]ctrl_deser160,
// pattern generator
input [5:0]pg,
input i2c_trigger,
input tin,
input tout,
// adc input port
input [11:0]adc_data,
input adc_or,
// data channel 1
input sdata1,
// data simulator
input evsim_enable,
input evsim_write,
input [15:0]evsim_data,
// data output channel 1
output reg daq0_write,
output reg [15:0]daq0_writedata,
input daq0_running,
output [5:0]TP
);
// pattern generator signals
wire pg_trigger; // trigger signal for probe
wire pg_rest; // TBM reset
wire pg_res; // ROC reset
wire pg_cal; // calibrate
wire pg_trg; // trigger
wire pg_tok; // token in
assign {pg_trigger, pg_rest, pg_res, pg_cal, pg_trg, pg_tok} = pg;
wire write_ana;
wire [15:0]data_ana;
wire write_roc;
wire [15:0]data_roc;
adc_readout adc_in
(
.clk(clk_daq),
.sync(sync),
.reset(reset),
.avs_ctrl_address(ctrl_adc_address),
.avs_ctrl_write(ctrl_adc_write),
.avs_ctrl_writedata(ctrl_adc_writedata),
.avs_ctrl_read(ctrl_adc_read),
.avs_ctrl_readdata(ctrl_adc_readdata),
.run(daq0_running),
.trig1(pg_trigger),
.trig2(i2c_trigger),
.tin(tin),
.tout(tout),
.adc_data(adc_data),
.adc_or(adc_or),
.write(write_ana),
.writedata(data_ana),
.TP(TP)
);
deser160 channel1_roc
(
.clk(clk_daq),
.sync(sync),
.reset(reset),
.sclk0(sclk[0]),
.sclk180(sclk[4]),
.ctrl(ctrl_deser160),
.sdata(sdata1),
.tin(tin),
.tout(tout),
.run(daq0_running),
.write(write_roc),
.data(data_roc)
);
always @(*)
begin
if (evsim_enable)
begin
daq0_write <= evsim_write;
daq0_writedata <= evsim_data;
end
else if (write_ana)
begin
daq0_write <= write_ana;
daq0_writedata <= data_ana;
end
else
begin
daq0_write <= write_roc;
daq0_writedata <= data_roc;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double EPS = 1e-9; const int oo = 210000000; int n; vector<int> p[4]; vector<int> g[201]; int solve(int x) { bool used[201]; for (int i = 1; i <= n; i++) used[i] = 0; int ans = 0, m = 0; while (m < n) { bool flag1 = 0; for (int i = 0; i < p[x].size(); i++) { int cur = p[x][i]; if (used[cur]) continue; bool flag = 1; for (int j = 0; j < g[cur].size(); j++) if (!used[g[cur][j]]) { flag = 0; break; } if (flag) { flag1 = 1; m++; used[cur] = 1; } } if (!flag1) { x++; if (x > 3) x = 1; ans++; } } return ans; } int main() { cin >> n; for (int i = 1; i <= n; i++) { int tmp; cin >> tmp; p[tmp].push_back(i); } for (int i = 1; i <= n; i++) { int k; cin >> k; for (int j = 0; j < k; j++) { int tmp1; cin >> tmp1; g[i].push_back(tmp1); } } int ans = oo; ans = min(ans, solve(1)); ans = min(ans, solve(2)); ans = min(ans, solve(3)); cout << ans + n << endl; return (0); }
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module RegisterTestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] test_in,test_in2;
reg test_clk,test_reset,test_load,test_load2;
wire [31:0] test_out;
//module Register2(input [31:0] IN,IN2,input Clk, Reset,Load,Load2,output [31:0] OUT);
Register2 test_reg(.IN(test_in),
.IN2(test_in2),
.Clk(test_clk),
.Reset(test_reset),
.Load(test_load),
.Load2(test_load2),
.OUT(test_out));
reg Clk,Reset;
/*
generate
genvar i;
for (i=0; i<15; i=i+1) begin : dff
custom i_custom(
.clk(clk)
,.input(DFF_i[i])
,.output(DFF_o[i])
);
end
endgenerate
*/
initial fork
test_in=0 ; test_in2=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ; test_load2=0 ;
#1 test_in=1;#1 test_in2=0; #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;
#2 test_in=1;#2 test_in2=0; #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;
#3 test_in=0;#3 test_in2=0; #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;
#4 test_in=0;#4 test_in2=1; #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;
#5 test_in=0;#5 test_in2=1; #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;
#6 test_in=0;#6 test_in2=1; #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;
#7 test_in=1;#7 test_in2=0; #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;
#8 test_in=1;#8 test_in2=0; #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;
#9 test_in=0;#9 test_in2=0; #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;
#10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;
#11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;
#12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;
join
always
#1 test_clk = ~test_clk;
initial #sim_time $finish; //Especifica cuando termina la simulacion
initial begin
$dumpfile("RegisterTestBench.vcd");
$dumpvars(0,RegisterTestBench);
$display(" Test Results" ); // imprime header
$monitor("T = %d,test_out = %d,test_in = %d,test_in2 = %d,test_clk = %d,test_reset = %d,test_load = %d,test_load2 = %d",$time,test_out,test_in,test_in2,test_clk,test_reset,test_load,test_load2 ); //imprime se~ales
end
endmodule
//iverilog Register2.v RegisterTestBench.v
//gtkwave RegisterTestBench.vcd
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#include <bits/stdc++.h> using namespace std; int n, type[100001], a[100001], lead[100001], cur[100001]; bool vs[100001]; void input() { scanf( %d , &n); for (int i = 1, _b = n; i <= _b; i++) scanf( %d , &type[i]); int x; memset(lead, 0, sizeof(lead)); memset(a, 0, sizeof(a)); for (int i = 1, _b = n; i <= _b; i++) { scanf( %d , &x); a[x] = i; lead[x]++; } } void dfs(int i) { vs[i] = true; if (type[i]) { cur[i] = 1; return; } if (lead[a[i]] != 1 && !type[a[i]]) return; if (!vs[a[i]]) dfs(a[i]); if (cur[a[i]]) cur[i] = cur[a[i]] + 1; } void process() { memset(vs, false, sizeof(vs)); memset(cur, 0, sizeof(cur)); for (int i = 0, _b = n; i <= _b; i++) if (lead[i] != 1 && !type[i]) vs[i] = true; for (int i = 1, _b = n; i <= _b; i++) { if (!vs[i]) dfs(i); } int ans = 0; int st = 0; for (int i = 1, _b = n; i <= _b; i++) { if (ans < cur[i]) { ans = cur[i]; st = i; } } cout << ans << endl; while (!type[st]) { printf( %d , st); st = a[st]; } cout << st; } int main() { input(); process(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k; string out, chr; cin >> n >> k; for (int i = 0; i < k; ++i) chr += a + i; for (int i = 0; i < n; ++i) out += chr[i % k]; cout << out; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tt; cin >> tt; while (tt--) { int k; cin >> k; string s, a, b; cin >> s >> a >> b; int n = (int)(s).size(); vector<int> x; vector<int> p(k, -1); bool goodx = true; for (int i = 0; i < n; ++i) { int c = s[i] - a ; if (p[c] != -1) { if (p[c] < a[i] - a ) { goodx = false; break; } else if (p[c] == a[i] - a ) { continue; } else { goodx = true; break; } } p[c] = a[i] - a ; x.push_back(i); } bool found = false; for (int u = 0; u <= (int)(x).size(); ++u) { if (u == (int)(x).size() && !goodx) { continue; } p.assign(k, -1); vector<bool> occ(k, false); bool ok = true; for (int i = 0; i < u; ++i) { if (occ[a[x[i]] - a ]) { ok = false; break; } occ[a[x[i]] - a ] = true; p[s[x[i]] - a ] = a[x[i]] - a ; } if (u < (int)(x).size()) { int pos = a[x[u]] - a + 1; while (pos < k && occ[pos]) { ++pos; } if (pos == k) { ok = false; } else { p[s[x[u]] - a ] = pos; occ[pos] = true; } } if (!ok) { continue; } int pos = 0; for (int i = 0; i < n; ++i) { if (p[s[i] - a ] != -1) { continue; } while (occ[pos]) { ++pos; } p[s[i] - a ] = pos; occ[pos] = true; } string res = ; for (int i = 0; i < n; ++i) { res += char(p[s[i] - a ] + a ); } if (res > b) { continue; } found = true; cout << YES n ; for (int i = 0; i < k; ++i) { if (p[i] != -1) { continue; } while (occ[pos]) { ++pos; } p[i] = pos; occ[pos] = true; } for (int i = 0; i < k; ++i) { cout << char(p[i] + a ); } cout << n ; break; } if (!found) { cout << NO n ; } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 5; int n, k; int v[MAXN], c[MAXN], a[MAXN]; double f[MAXN]; int rv[MAXN][20], rc[MAXN][20]; inline int GetV(int l, int r) { int x = log2(r - l + 1); return max(rv[l][x], rv[r + 1 - (1 << x)][x]); } inline int GetC(int l, int r) { int x = log2(r - l + 1); return min(rc[l][x], rc[r + 1 - (1 << x)][x]); } inline int Cal(int pos) { if (100 * v[pos] > c[pos]) return c[pos]; int left = pos, right = n, t; while (left <= right) { int mid = (left + right) >> 1; if (GetV(pos, mid) * 100 <= GetC(pos, mid)) { t = mid; left = mid + 1; } else right = mid - 1; } int ans = GetV(pos, t) * 100; if (t < n) ans = max(ans, GetC(pos, t + 1)); return ans; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) scanf( %d , &v[i]); for (int i = 1; i <= n; ++i) scanf( %d , &c[i]); for (int i = 1; i <= n; ++i) rv[i][0] = v[i], rc[i][0] = c[i]; int lgn = log2(n); for (int j = 1; j <= lgn; ++j) { int last = n + 1 - (1 << j); for (int i = 1; i <= last; ++i) { rv[i][j] = max(rv[i][j - 1], rv[i + (1 << (j - 1))][j - 1]); rc[i][j] = min(rc[i][j - 1], rc[i + (1 << (j - 1))][j - 1]); } } for (int i = 1; i <= n; ++i) a[i] = Cal(i); f[0] = 1.0 * k / (n - k + 1); for (int i = 1; i <= n - k + 1; ++i) f[i] = f[i - 1] * (n - i - k + 2) / (n - i + 1); sort(a + 1, a + n + 1); double ans = 0; for (int i = 1; i <= n - k + 1; ++i) ans += a[i] * f[i]; cout << fixed << setprecision(9) << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int diff(long long int x, long long int y) { if (x > y) { return x - y; } else { return y - x; } } int main() { long long int n; cin >> n; long long int arr[n]; for (long long int i = 0; i < n; i++) { cin >> arr[i]; } long long int count = 0; long long int ans = 0; for (long long int i = 0; i < n; i++) { if (arr[i] == 1) { count++; if (count > ans) { ans = count; } } else { count = 0; } } if (count != 0) { for (int i = 0; i < n; i++) { if (arr[i] == 1) { count++; if (count > ans) { ans = count; } } else { break; } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct point { int i; int j; }; int main() { vector<char> s; int n, m; char c; char a[102][102]; point first; first.i = -1; point last; memset(a, 0, sizeof(a)); scanf( %d %d %c , &n, &m, &c); getchar(); for (int i = 0; i < n + 1; i++) { a[i][0] = c; a[i][m + 1] = c; } for (int i = 0; i < m + 1; i++) { a[0][i] = c; a[n + 1][i] = c; } for (int i = 1; i < n + 1; i++) { for (int j = 1; j < m + 1; j++) { scanf( %c , &c); a[i][j] = c; if (c == a[0][0]) { if (first.i < 0) { first.i = i; first.j = j; } last.i = i; last.j = j; } } getchar(); } int can; for (int i = first.i; i < last.i + 1; i++) { for (int j = first.j; j < last.j + 1; j++) { can = count(s.begin(), s.end(), a[i][j]); if (a[i - 1][j] != . && count(s.begin(), s.end(), a[i - 1][j]) == 0) s.push_back(a[i - 1][j]); if (a[i][j - 1] != . && count(s.begin(), s.end(), a[i][j - 1]) == 0) s.push_back(a[i][j - 1]); if (a[i][j + 1] != . && count(s.begin(), s.end(), a[i][j + 1]) == 0) s.push_back(a[i][j + 1]); if (a[i + 1][j] != . && count(s.begin(), s.end(), a[i + 1][j]) == 0) s.push_back(a[i + 1][j]); } } if (s.size()) printf( %d n , s.size() - 1); else printf( %d n , s.size()); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_SYMBOL_V
`define SKY130_FD_SC_LS__DLXTP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_SYMBOL_V
|
module test;
integer i;
reg [7:0] c;
reg [31:0] fd[15:0];
initial begin
// Open some MCDs and FD's to play with
$display("Open some files");
for (i = 0; i < 4; i = i+1) begin
fd[i] = $fopen("/dev/null");
$display("open MCD returned %x", fd[i]);
end
for (i = 4; i < 6; i = i+1) begin
fd[i] = $fopen("/dev/null", "r");
$display("open FD ('r') returned %x", fd[i]);
end
for (i = 6; i < 8; i = i+1) begin
fd[i] = $fopen("/dev/null", "w");
$display("open FD ('w') returned %x", fd[i]);
end
for (i = 8; i < 10; i = i+1) begin
fd[i] = $fopen("/dev/null", "a");
$display("open FD ('a') returned %x", fd[i]);
end
// Show what's open
$test;
// Different systems have different buffer sizes so flush here.
$fflush;
// access some of the files
$fdisplay(1, "write to MCD 1");
$fdisplay(2, "write to MCD 2");
$fflush;
$fdisplay(32'h8000_0000, "write to FD 0"); // stdin so invisible
$fdisplay(32'h8000_0001, "write to FD 1");
$fdisplay(32'h8000_0002, "write to FD 2"); // stderr is normally unbuffered
// so will appear before stdout
// close all the stuff we opened
$display("Close some files");
for (i = 0; i < 10; i = i+1) begin
$fclose(fd[i]);
end
// try closing special and already closed
$fclose(1);
$fclose(2);
$fclose(32'h4000_0000);
$fclose(32'h8000_0000);
$fclose(32'h8000_0001);
$fclose(32'h8000_0002);
$fclose(32'h8000_0003);
// Now for something really insane
$fclose(32'h81ca_1ca0);
// Show what's open
$test;
// access to null MCD/FD's
$fdisplay(32'h4000_0000, "write to NULL MCD");
$fdisplay(32'h8000_000f, "write to NULL FD");
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// syncflop.v ////
//// ////
//// ////
//// A generic synchronization device between two clock domains ////
//// ////
//// Author(s): ////
//// Nathan Yawn () ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// This is a synchronization element between two clock domains. It
// uses toggle signaling - that is, clock domain 1 changes the state
// of TOGGLE_IN to indicate a change, rather than setting the level
// high. When TOGGLE_IN changes state, the output on D_OUT will be
// set to level '1', and will hold that value until D_RST is held
// high during a rising edge of DEST_CLK. D_OUT will be updated
// on the second rising edge of DEST_CLK after the state of
// TOGGLE_IN has changed.
// RESET is asynchronous. This is necessary to coordinate the reset
// between different clock domains with potentially different reset
// signals.
//
// Ports:
// DEST_CLK: Clock for the target clock domain
// D_SET: Synchronously set the output to '1'
// D_CLR: Synchronously reset the output to '0'
// RESET: Set all FF's to '0' (asynchronous)
// TOGGLE_IN: Toggle data signal from source clock domain
// D_OUT: Output to clock domain 2
// Top module
module syncflop(
DEST_CLK,
D_SET,
D_RST,
RESET,
TOGGLE_IN,
D_OUT
);
input DEST_CLK;
input D_SET;
input D_RST;
input RESET;
input TOGGLE_IN;
output D_OUT;
reg sync1;
reg sync2;
reg syncprev;
reg srflop;
wire syncxor;
wire srinput;
wire D_OUT;
// Combinatorial assignments
assign syncxor = sync2 ^ syncprev;
assign srinput = syncxor | D_SET;
assign D_OUT = srflop | syncxor;
// First DFF (always enabled)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) sync1 <= 1'b0;
else sync1 <= TOGGLE_IN;
end
// Second DFF (always enabled)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) sync2 <= 1'b0;
else sync2 <= sync1;
end
// Third DFF (always enabled, used to detect toggles)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) syncprev <= 1'b0;
else syncprev <= sync2;
end
// Set/Reset FF (holds detected toggles)
always @ (posedge DEST_CLK or posedge RESET)
begin
if(RESET) srflop <= 1'b0;
else if(D_RST) srflop <= 1'b0;
else if (srinput) srflop <= 1'b1;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sin_taylor_seriesbkb
#(parameter
ID = 1,
NUM_STAGE = 6,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
sin_taylor_series_ap_dmul_4_max_dsp_64 sin_taylor_series_ap_dmul_4_max_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; #define ll long long #define pi pair<int, int> #define pll pair<long long, long long> #define vi vector<int> #define vll vector<long long> #define vpi vector<pair<int, int>> #define vvi vector<vector<int>> #define mii map<int, int> #define mmii multimap<int, int> #define umii unordered_map<int, int> #define umsii unordered_multimap<int, int> #define si set<int> #define msi multiset<int> #define usi unordered_set<int> #define umsi unordered_multiset<int> #define sc set<char> #define f(i, s, e) for (long long int i = s; i < e; i++) #define cf(i, s, e) for (long long int i = s; i <= e; i++) #define rf(i, e, s) for (long long int i = e - 1; i >= s; i--) #define pb push_back #define mp make_pair #define eb emplace_back #define F first #define S second #define all(x) x.begin(), x.end() #define rall(x) x.rbegin(), x.rend() template <class T> void print_v(vector<T> &v) { cout << [ ; for (auto x : v) cout << x << , ; cout << b b] n ; } template <class T> long long int sum_v(vector<T> &v) { long long int ans = 0; for (auto a : v) ans += a; return ans; } #define MOD 1000000007 #define PI 3.1415926535897932384626433832795 ll min(ll a, int b) { if (a < b) return a; return b; } ll min(int a, ll b) { if (a < b) return a; return b; } ll max(ll a, int b) { if (a > b) return a; return b; } ll max(int a, ll b) { if (a > b) return a; return b; } ll gcd(ll a, ll b) { if (b == 0) return a; return gcd(b, a % b); } ll lcm(ll a, ll b) { return a / gcd(a, b) * b; } string to_upper(string a) { for (int i = 0; i < (int)a.size(); ++i) if (a[i] >= a && a[i] <= z ) a[i] -= a - A ; return a; } string to_lower(string a) { for (int i = 0; i < (int)a.size(); ++i) if (a[i] >= A && a[i] <= Z ) a[i] += a - A ; return a; } bool prime(ll a) { if (a == 1) return 0; for (int i = 2; i <= round(sqrt(a)); ++i) if (a % i == 0) return 0; return 1; } void yes() { cout << YES n ; } void no() { cout << NO n ; } typedef long int int32; typedef unsigned long int uint32; typedef long long int int64; typedef unsigned long long int uint64; void dfs(vvi &graph, vi &ans, si &visited, int node) { if (ans[node] == -1 || ans[node] == 2) return; if (visited.count(node)) { vi stack; vi tempvisited(graph.size()); stack.push_back(node); while (!stack.empty()) { int val = stack.back(); stack.pop_back(); ans[val] = -1; tempvisited[val] = 1; for (int i : graph[val]) { if (!tempvisited[i]) stack.push_back(i); } } return; } visited.insert(node); if (ans[node] != -1) ans[node] = min(ans[node] + 1, 2); for (int i : graph[node]) { dfs(graph, ans, visited, i); } visited.erase(node); } void solve() { int n, m; cin >> n >> m; vvi graph(n + 1); vi ans(n + 1); si visited; f(i, 0, m) { int a, b; cin >> a >> b; graph[a].push_back(b); } dfs(graph, ans, visited, 1); cf(i, 1, n) cout << ans[i] << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; long long x[5003], a[5003], b[5003], c[5003], d[5003]; vector<int> path; long long weight[5003][5003]; long long edge(int i, int j) { long long ans = abs(x[i] - x[j]); if (j < i) ans += (c[i] + b[j]); if (i < j) ans += (d[i] + a[j]); return ans; } int main() { int n, s, e; cin >> n >> s >> e; for (int i = 1; i <= n; i++) cin >> x[i]; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> b[i]; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= n; i++) cin >> d[i]; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) weight[i][j] = edge(i, j); long long ans = weight[s][e]; path.push_back(s); path.push_back(e); for (int i = 1; i <= n; i++) { if (i == s || i == e) continue; int insert_at = 0; long long best = 1e12; for (int j = 0; j < path.size() - 1; j++) { long long temp = weight[path[j]][i] + weight[i][path[j + 1]] - weight[path[j]][path[j + 1]]; if (temp < best) { best = temp; insert_at = j; } } ans += best; vector<int>::iterator ins = find(path.begin(), path.end(), path[insert_at]); ins++; path.insert(ins, i); } cout << ans << endl; }
|
//#############################################################################
//# Function: Statically configured arbiter #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_arbiter #( parameter N = 1,
parameter TYPE = "FIXED" // or ROUNDROBIN, FAIR
)
(
input [N-1:0] requests, //request vector
output [N-1:0] grants //grant (one hot)
);
wire [N-1:0] waitmask;
genvar j;
generate
if(TYPE=="FIXED")
begin : arbiter_fixed
assign waitmask[0] = 1'b0;
for (j=N-1; j>=1; j=j-1)
begin : gen_arbiter
assign waitmask[j] = |requests[j-1:0];
end
end
endgenerate
//grant circuit
assign grants[N-1:0] = requests[N-1:0] & ~waitmask[N-1:0];
endmodule // oh_arbiter
|
/*
* File: lsu_mem2reg.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Description:
* MUX for load data
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module lsu_mem2reg(addr, lsu_op, memdata, regdata);
parameter width = `OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] memdata;
output [width-1:0] regdata;
//
//
//
reg [width-1:0] regdata;
reg [width-1:0] aligned;
//
// Alignment: get data from memory bus
// align data to lsb according to access address
always @(addr or memdata) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(addr) // synopsys parallel_case infer_mux
`else
case(addr) // synopsys parallel_case
`endif
3'b000:
aligned = memdata;
3'b001:
aligned = {8'b0, memdata[55:0]};
3'b010:
aligned = {16'b0, memdata[47:0]};
3'b011:
aligned = {24'b0, memdata[39:0]};
3'b100:
aligned = {32'b0, memdata[31:0] };
3'b101:
aligned = {40'b0, memdata[23:0]};
3'b110:
aligned = {48'b0, memdata[15:0]};
3'b111:
aligned = {56'b0, memdata[7:0]};
default:
aligned = memdata;
endcase
end
//
// Bytes
// mux data and extend according to instruction type
always @(lsu_op or aligned) begin
`ifdef pippo_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(lsu_op) // synopsys parallel_case infer_mux
`else
case(lsu_op) // synopsys parallel_case
`endif
`LSUOP_LB: begin
regdata[63:16] = {56{aligned[7]}};
regdata[7:0] = aligned[7:0];
end
`LSUOP_LBU: begin
regdata[63:8] = 56'b0;
regdata[7:0] = aligned[7:0];
end
`LSUOP_LH: begin
regdata[63:16] = {48{aligned[31]}};
regdata[31:16] = aligned[15:0];
end
`LSUOP_LHU: begin
regdata[63:16] = 48'b0;
regdata[15:0] = aligned[15:0];;
end
`LSUOP_LW: begin
regdata[63:32] = {32{aligned[31]}};
regdata[31:0] = aligned[31:0]};
end
`LSUOP_LWU: begin
regdata[63:0] = {32{1'b0}};
regdata[31:0] = aligned[31:0]};
end
`LSUOP_LD: begin
regdata[63:0] = aligned[63:0];
end
default:
regdata[63:0] = aligned[63:0];
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLXTN_BEHAVIORAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtn (
VPWR ,
VGND ,
Q ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input D ;
input GATE_N;
// Local signals
wire gate buf_Q ;
wire gate GATE_N_delayed;
wire gate D_delayed ;
reg notifier ;
wire GATE ;
wire awake ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int Max_N(1050); int N; double P[Max_N][Max_N], F[Max_N], G[Max_N], V[Max_N]; bool done[Max_N]; int main() { scanf( %d , &N); for (int i = 1; i <= N; ++i) { V[i] = 1.0; for (int j = 1; j <= N; ++j) scanf( %lf , P[i] + j), P[i][j] /= 100.0; if (i < N) F[i] = 1E100; } for (int u;;) { u = -1; for (int x = 1; x <= N; ++x) if (!done[x] && (u == -1 || F[x] < F[u])) u = x; if (u == -1) break; done[u] = true; for (int v = 1; v <= N; ++v) if (!done[v] && P[v][u] != 0.0) G[v] += V[v] * P[v][u] * F[u], V[v] *= (1.0 - P[v][u]), F[v] = 1.0 / (1.0 - V[v]) + G[v] / (1.0 - V[v]); } printf( %.10lf , F[1]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_PP_V
/**
* srdlrtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, SLEEP_B, KAPWR, VGND, VPWR);
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int x, y, idx; cin >> x >> y >> idx; if (idx == 0) cout << x << endl; else if (idx == 1) cout << y << endl; else { idx -= 2; int z; while (true) { z = x + y; idx--; if (idx < 0) break; x = y; y = z; } cout << z << endl; } }
|
#include <bits/stdc++.h> const int N = 810; const int M = 10; int mod[N][M]; int ans[N], inv[N], a[N]; int n; void print() { if (ans[1] > n / 2) { for (int i = 1; i <= n; ++i) { ans[i] = n + 1 - ans[i]; } } printf( ! ); for (int i = 1; i <= n; ++i) { printf( %d , ans[i]); } puts( ); } int ask(std::vector<int> vec, int calcmod) { int n = vec.size(); printf( ? %d , n); for (auto u : vec) { printf( %d , u); } puts( ); fflush(stdout); int ret; scanf( %d , &ret); if (calcmod > 0) { if (ret) { int sum = 0; for (auto u : vec) { if (u != calcmod) { sum = (sum + ans[u]) % n; } } mod[calcmod][n] = (n - sum) % n; } } return ret; } int main() { scanf( %d , &n); memset(mod, -1, sizeof(mod)); mod[1][2] = 1; for (int i = 1; i < n; ++i) { mod[i + 1][2] = mod[i][2] ^ (1 - ask({i, i + 1}, 0)); } for (int i = 1; i <= 4 && i <= n / 2; ++i) { std::vector<int> todo; for (int j = 1; j <= n; ++j) { if (!ans[j]) { todo.emplace_back(j); } } for (auto j : todo) { std::vector<int> vec; for (auto k : todo) { if (j != k) { vec.emplace_back(k); } } if (ask(vec, 0)) { ans[j] = mod[j][2] == i % 2 ? i : n + 1 - i; inv[ans[j]] = j; } } } if (n <= 8) { print(); return 0; } for (int i = 3; i <= 7; i += 2) { using pii = std::pair<int, int>; std::vector<pii> to_check; std::vector<int> known; for (int j = 0; j <= i / 2; ++j) { to_check.emplace_back(1, n - 3 + j); } for (int j = 1; j <= i / 2; ++j) { to_check.emplace_back(i / 2 + 1, n - 3 + j); } for (int j = 0; j <= i / 2; ++j) { known.emplace_back(j + 1); known.emplace_back(j + n - 3); } for (auto p : to_check) { for (int j = 1; j <= n; ++j) { if (ans[j] || mod[j][i] != -1) { continue; } std::vector<int> vec = {j}; for (auto u : known) { if (u == p.first || u == p.second) { continue; } vec.emplace_back(inv[u]); } ask(vec, j); } } } for (int i = 1; i <= n; ++i) { if (ans[i]) { continue; } ask({inv[1], inv[2], inv[3], i}, i); if (mod[i][4] != -1) { continue; } ask({inv[1], inv[2], inv[4], i}, i); if (mod[i][4] != -1) { continue; } mod[i][4] = mod[i][2] == 1 ? 3 : 0; } std::vector<bool> calced(8); int sum = 0; for (int i = 1; i <= 4; ++i) { sum += n - 4 + i; sum += i; } for (int i = 1; i <= 4; ++i) { calced[(8 - (sum - i) % 8) % 8] = true; } for (int i = 1; i <= n; ++i) { if (ans[i]) { continue; } int pos = 0; for (int j = 1; j <= 4; ++j) { if ((sum - j) % 4 == (4 - mod[i][4]) % 4) { pos = j; break; } } std::vector<int> vec = {i}; for (int j = 1; j <= 4; ++j) { vec.emplace_back(inv[n - 4 + j]); if (j != pos) { vec.emplace_back(inv[j]); } } ask(vec, i); if (mod[i][8] == -1) { mod[i][8] = (calced[mod[i][4]] ? 4 : 0) ^ mod[i][4]; } } for (int i = 1; i <= n; ++i) { if (ans[i]) { continue; } for (int j = 1; j <= n; ++j) { bool flag = true; for (auto u : {3, 5, 7, 8}) { if (j % u != mod[i][u]) { flag = false; break; } } if (flag) { ans[i] = j; break; } } } print(); }
|
#include <bits/stdc++.h> using namespace std; int who(int n) { if (n < 5) { return n; } else { n -= 5; return who(n / 2); } } int main(int argc, char** argv) { int n, m; cin >> n >> m; vector<vector<char> > snake(n, vector<char>(m, # )); for (int i = 1; i < n; i += 2) { for (int j = (i / 2) % 2; j < m - 1 + (i / 2) % 2; ++j) { snake[i][j] = . ; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cout << snake[i][j]; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[205], b[205]; long long dp[205][205], k; int n, m; char ans[205]; bool cmp(int x, int y) { return a[x] < a[y]; } int main() { scanf( %d%d , &n, &m); cin >> k; int t = n + m - 1; for (int i = 0; i < t; i++) { a[i] = n * m; b[i] = i; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int tmp; scanf( %d , &tmp); if (tmp < a[i + j]) a[i + j] = tmp; } sort(b, b + t, cmp); for (int q = 0; q < t; q++) { ans[b[q]] = ( ; dp[0][0] = 1; for (int i = 0; i < t; i++) for (int j = i & 1; j <= i && j <= t - i; j += 2) if (dp[i][j]) { if (dp[i][j] > k) dp[i][j] = k; if (ans[i] != ) ) dp[i + 1][j + 1] += dp[i][j]; if (ans[i] != ( && j) dp[i + 1][j - 1] += dp[i][j]; dp[i][j] = 0; } if (dp[t][0] < k) { k -= dp[t][0]; ans[b[q]] = ) ; } dp[t][0] = 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout.put(ans[i + j]); puts( ); } return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 2875 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w511,
w64,
w575,
w2300,
w2875;
assign w1 = i_data0;
assign w2300 = w575 << 2;
assign w2875 = w575 + w2300;
assign w511 = w512 - w1;
assign w512 = w1 << 9;
assign w575 = w511 + w64;
assign w64 = w1 << 6;
assign o_data0 = w2875;
//multiplier_block area estimate = 5259.03845465735;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module scales video streams on the DE boards. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Video_In_Scaler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Frame's Channel Width
parameter DW = 15; // Frame's Data Width
parameter EW = 0; // Frame's Empty Width
parameter WIW = 9; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 640;
parameter WIDTH_DROP_MASK = 4'b0101;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 8; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 320; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [CW: 0] stream_out_channel;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [CW: 0] internal_channel;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_channel = 'h0;
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_shrink Shrink_Frame (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// Bidirectional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Shrink_Frame.DW = DW,
Shrink_Frame.WW = WIW,
Shrink_Frame.HW = HIW,
Shrink_Frame.WIDTH_IN = WIDTH_IN,
Shrink_Frame.WIDTH_DROP_MASK = WIDTH_DROP_MASK,
Shrink_Frame.HEIGHT_DROP_MASK = HEIGHT_DROP_MASK;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[1000000 + 342]; set<int> ans; bool incl[1000000 + 342]; bool isleader[1000000 + 342]; map<pair<int, int>, bool> egd; int main() { ios::sync_with_stdio(false); int n, m, x, y; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> x >> y; if (egd[make_pair(x, y)] == false) { adj[x].push_back(y); egd[make_pair(x, y)] = true; } } for (int i = 1; i <= n; i++) { if (incl[i] == false) { for (auto next : adj[i]) { if (next > i) if (incl[next] == false) { incl[next] = true; } } } } for (int i = n; i >= 1; i--) { if (incl[i] == false) { ans.insert(i); for (auto next : adj[i]) { incl[next] = true; } } } cout << ans.size() << n ; for (auto bc : ans) cout << bc << ; return 0; }
|
`include "tx.v"
`include "hardReset.v"
`include "registers.v"
`include "reg_interface.v"
module tcpci(output wire Start_tHardResetComplete_timer,
output wire Request_PHY_to_Send_Hard_Reset,
output wire Request_PHY_to_Send_Cable_Reset,
output wire Stop_PHY_attempting_to_send_Hard_Reset,
output wire Stop_PHY_attempting_to_send_Cable_Reset,
output wire Stop_tHardResetComplete_timer,
output wire Start_CRCReceiveTimer,
output wire Stop_CRCReceiverTimer,
output wire MessageIDCounter,
output wire MessageID,
output wire MessageID_mismatch,
output wire SOP_mismatch,
output wire MessageID_SOP_match,
output wire [7:0] TRANSMIT_BYTE_COUNT,
output wire [7:0] TRANSMIT_HEADER_LOW,
output wire [7:0] TRANSMIT_HEADER_HIGH,
output wire [7:0] TRANSMIT_DATA_OBJECTS,
output wire [7:0] I2C_slave_reg_out,
output wire [7:0] ALERT_LOW,
input wire tHard_Reset_Complete_expires,
input wire Hard_Reset_sent,
input wire Cable_Reset_sent,
input wire tHardResetComplete_expires,
input wire PRL_Rx_Message_Discard,
input wire Hard_Reset_received,
input wire Cable_Reset_received,
input wire RetryCounter,
input wire CRCReceiveTimer_Timeout,
input wire GoodCRC_Response_from_PHY,
input wire Message_discarded_bus_Idle,
input wire [7:0] I2C_slave_reg_in,
input wire [7:0] I2C_slave_reg_addr,
input wire I2C_slave_reg_in_enb,
input wire reset,
input wire clk);
localparam ALERT_ADDR_LOW = 8'h10;
localparam ALERT_ENB_LOW = 1'h1;
reg ir_ri0_enb, ir_ri1_enb, ir_ri2_enb;
wire [7:0] ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data,TRANSMIT, TX_BUF_HEADER_BYTE_1, RX_BUF_HEADER_BYTE_1, RX_BUF_FRAME_TYPE;
reg [7:0] ir_ri1_in_data, ir_ri2_in_data, ir_ri2_address;
wire ALERT_TransmitSuccessful_TX,ALERT_TransmitSuccessful_HR;
wire ALERT_TransmitSOP_MessageFailed_TX,ALERT_TransmitSOP_MessageFailed_HR;
assign ir_ri2_enb=0;
assign ir_ri2_address=8'h00;
REG_INTERFACE reg_interface(I2C_slave_reg_out, ALERT_LOW, ow_ri2_out_data, TRANSMIT, TX_BUF_HEADER_BYTE_1, RX_BUF_HEADER_BYTE_1, RX_BUF_FRAME_TYPE, I2C_slave_reg_addr, ALERT_ADDR_LOW, ir_ri2_address, I2C_slave_reg_in, ir_ri1_in_data, ir_ri2_in_data, I2C_slave_reg_in_enb, ALERT_ENB_LOW, ir_ri2_enb, reset, clk);
tx TX( ALERT_TransmitSOP_MessageFailed_TX, ALERT_TransmitSuccessful_TX, MessageID_mismatch, SOP_mismatch, MessageID_SOP_match, TRANSMIT_BYTE_COUNT, TRANSMIT_HEADER_LOW, TRANSMIT_HEADER_HIGH, TRANSMIT_DATA_OBJECTS, Start_CRCReceiveTimer, Stop_CRCReceiverTimer, MessageIDCounter, MessageID, TRANSMIT [2:0], PRL_Rx_Message_Discard, Hard_Reset_received, Cable_Reset_received, RetryCounter, CRCReceiveTimer_Timeout, GoodCRC_Response_from_PHY, Message_discarded_bus_Idle, TX_BUF_HEADER_BYTE_1, RX_BUF_HEADER_BYTE_1, RX_BUF_FRAME_TYPE, clk, reset);
hardReset me_HR(Start_tHardResetComplete_timer, Request_PHY_to_Send_Hard_Reset, Request_PHY_to_Send_Cable_Reset, Stop_PHY_attempting_to_send_Hard_Reset, Stop_PHY_attempting_to_send_Cable_Reset, Stop_tHardResetComplete_timer, ALERT_TransmitSuccessful_HR, ALERT_TransmitSOP_MessageFailed_HR, TRANSMIT[2:0], tHard_Reset_Complete_expires, Hard_Reset_sent, Cable_Reset_sent, tHardResetComplete_expires, reset, clk);
always @(ALERT_TransmitSuccessful_TX,ALERT_TransmitSuccessful_HR, ALERT_TransmitSOP_MessageFailed_TX, ALERT_TransmitSOP_MessageFailed_HR)
begin
ir_ri1_in_data={ALERT_LOW[7:7],ALERT_TransmitSuccessful_HR+ALERT_TransmitSuccessful_TX,ALERT_LOW[5:5],ALERT_TransmitSOP_MessageFailed_HR
+ALERT_TransmitSOP_MessageFailed_TX,ALERT_LOW[3:0]};
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_4_V
`define SKY130_FD_SC_MS__XNOR3_4_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_4_V
|
#include <bits/stdc++.h> long long RemoveZeros(long long a) { long long temp; long long x = 0; long long i = 10; while (a > 0) { if (a % 10 != 0) { temp = (a % 10) * i; x += temp; i *= 10; } a /= 10; } return x / 10; } using namespace std; int main() { long long a, b, c; cin >> a >> b; c = a + b; long long a1 = RemoveZeros(a); long long b1 = RemoveZeros(b); long long c1 = RemoveZeros(c); if (a1 + b1 == c1) cout << YES ; else cout << NO ; return 0; }
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
`include "spiflash.v"
module testbench;
reg clk;
always #5 clk = (clk === 1'b0);
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
repeat (6) begin
repeat (50000) @(posedge clk);
$display("+50000 cycles");
end
$finish;
end
wire [7:0] leds;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire flash_io2;
wire flash_io3;
always @(leds) begin
#1 $display("%b", leds);
end
hx8kdemo uut (
.clk (clk ),
.leds (leds ),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1)/*,
.flash_io2(flash_io2),
.flash_io3(flash_io3)*/
);
spiflash spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(flash_io2),
.io3(flash_io3)
);
endmodule
|
/* ********************************************************************************************* */
/* * Activity Indicator LED Module * */
/* * Authors: * */
/* * André Bannwart Perina * */
/* ********************************************************************************************* */
/* * Copyright (c) 2016 André B. Perina * */
/* * * */
/* * Permission is hereby granted, free of charge, to any person obtaining a copy of this * */
/* * software and associated documentation files (the "Software"), to deal in the Software * */
/* * without restriction, including without limitation the rights to use, copy, modify, * */
/* * merge, publish, distribute, sublicense, and/or sell copies of the Software, and to * */
/* * permit persons to whom the Software is furnished to do so, subject to the following * */
/* * conditions: * */
/* * * */
/* * The above copyright notice and this permission notice shall be included in all copies * */
/* * or substantial portions of the Software. * */
/* * * */
/* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * */
/* * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR * */
/* * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE * */
/* * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * */
/* * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * */
/* * DEALINGS IN THE SOFTWARE. * */
/* ********************************************************************************************* */
module ActivityLED(
clk,
rst_n,
sig_in,
led_out
);
/* Usual inputs */
input clk;
input rst_n;
/* Input signal and LED output */
input sig_in;
output led_out;
reg prevSigIn;
reg [23:0] ledCounter;
assign led_out = ledCounter[22];
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
prevSigIn <= 'b0;
ledCounter <= 'h0;
end
else begin
/* If changes are detected in sig_in, the LED will blink */
prevSigIn <= sig_in;
if(!ledCounter) begin
if(sig_in && !prevSigIn) begin
ledCounter <= 'h1;
end
end
else begin
ledCounter <= ledCounter + 'h1;
end
end
end
endmodule
|
module tb_SystolicDataSetupRow #(
parameter DATA_BITS = 8,
parameter MATRIX_SIZE = 8,
parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1
) ();
reg clock;
reg reset;
integer count;
reg [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:MATRIX_SIZE-1];
wire [DATA_BITS-1:0] data_out [0:OUTPUT_SIZE-1][0:MATRIX_SIZE-1];
SystolicDataSetupCol #(
.DATA_BITS(DATA_BITS),
.MATRIX_SIZE(MATRIX_SIZE),
.OUTPUT_SIZE(OUTPUT_SIZE)
) DUT (
.clock(clock),
.reset(reset),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clock = 1'b0;
reset = 1'b0;
$dumpfile("Systolic.vcd") ;
$dumpvars;
end
always begin
#5 clock = ~clock;
#5 clock = ~clock;
end
initial begin
#10 reset = 1'b1;
#20 reset = 1'b0;
#30
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j=0 ; j< MATRIX_SIZE;j++)
data_in[i][j]=8'h00;
#60
count=0;
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j =0; j< MATRIX_SIZE;j++) begin
data_in[i][j]=count;
count= count+1;
end
#50
count=0;
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j=0 ; j< MATRIX_SIZE;j++) begin
data_in[i][j]=count+3;
count= count+1;
end
#50 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
wire GCLK_b ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK_b , m0n, CLK );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, pair<int, int> > > V; const int maxn = 1010; int n, N; int a[maxn][maxn], r[maxn], c[maxn]; void sr(int x, int y) { if (x == y) return; V.push_back(make_pair(1, pair<int, int>(x, y))); for (int i = 1; i <= N; ++i) swap(a[x][i], a[y][i]); swap(r[x], r[y]); } void sc(int x, int y) { if (x == y) return; V.push_back(make_pair(2, pair<int, int>(x, y))); for (int i = 1; i <= N; ++i) swap(a[i][x], a[i][y]); swap(c[x], c[y]); } int main() { int x, y, i, j; scanf( %d , &n), N = n; for (i = 1; i < n; ++i) { scanf( %d%d , &x, &y); a[x][y] = 1, ++r[x], ++c[y]; } while (n > 1) { for (i = 1; i <= n; ++i) { for (j = i; j <= n; ++j) if (a[i][j]) break; if (a[i][j]) break; } if (!a[i][j]) break; sr(i, n), sc(j, 1); for (i = 1; i <= n; ++i) if (!c[i]) break; sc(i, n); for (i = 1; i <= n; ++i) c[i] -= a[n][i], r[i] -= a[i][n]; --n; } printf( %d n , V.size()); for (typeof(V.end()) i = V.begin(); i != V.end(); ++i) printf( %d %d %d n , i->first, (i->second).first, (i->second).second); return 0; }
|
module test;
reg clk = 0;
reg reset = 1;
wire [31:0] io_in_bits;
wire [7:0] io_in_bits_l2Protocol;
wire [7:0] io_in_bits_eth_l3Type;
wire [7:0] io_in_bits_ipv4_ttl;
initial begin
reset = 1;
#250 reset = 0;
end
always #100 clk = ~clk;
Top
Top(
.clk(clk),
.reset(reset),
.io_in_ready( io_in_ready),
.io_in_valid( io_in_valid),
.io_in_bits_l2Protocol( io_in_bits_l2Protocol),
.io_in_bits_eth_dstAddr( io_in_bits_eth_dstAddr),
.io_in_bits_eth_srcAddr( io_in_bits_eth_srcAddr),
.io_in_bits_eth_l3Type( io_in_bits_eth_l3Type),
.io_in_bits_eth_length( io_in_bits_eth_length),
.io_in_bits_ipv4_version( io_in_bits_ipv4_version),
.io_in_bits_ipv4_hLength( io_in_bits_ipv4_hLength),
.io_in_bits_ipv4_tos( io_in_bits_ipv4_tos),
.io_in_bits_ipv4_length( io_in_bits_ipv4_length),
.io_in_bits_ipv4_identification( io_in_bits_ipv4_identification),
.io_in_bits_ipv4_flagsOffset( io_in_bits_ipv4_flagsOffset),
.io_in_bits_ipv4_ttl( io_in_bits_ipv4_ttl),
.io_in_bits_ipv4_protocol( io_in_bits_ipv4_protocol),
.io_in_bits_ipv4_chksum( io_in_bits_ipv4_chksum),
.io_in_bits_ipv4_srcAddr( io_in_bits_ipv4_srcAddr),
.io_in_bits_ipv4_dstAddr( io_in_bits_ipv4_dstAddr),
.io_out_ready( io_out_ready),
.io_out_valid( io_out_valid),
.io_out_bits_l2Protocol( io_out_bits_l2Protocol),
.io_out_bits_eth_dstAddr( io_out_bits_eth_dstAddr),
.io_out_bits_eth_srcAddr( io_out_bits_eth_srcAddr),
.io_out_bits_eth_l3Type( io_out_bits_eth_l3Type),
.io_out_bits_eth_length( io_out_bits_eth_length),
.io_out_bits_ipv4_version( io_out_bits_ipv4_version),
.io_out_bits_ipv4_hLength( io_out_bits_ipv4_hLength),
.io_out_bits_ipv4_tos( io_out_bits_ipv4_tos),
.io_out_bits_ipv4_length( io_out_bits_ipv4_length),
.io_out_bits_ipv4_identification( io_out_bits_ipv4_identification),
.io_out_bits_ipv4_flagsOffset( io_out_bits_ipv4_flagsOffset),
.io_out_bits_ipv4_ttl( io_out_bits_ipv4_ttl),
.io_out_bits_ipv4_protocol( io_out_bits_ipv4_protocol),
.io_out_bits_ipv4_chksum( io_out_bits_ipv4_chksum),
.io_out_bits_ipv4_srcAddr( io_out_bits_ipv4_srcAddr),
.io_out_bits_ipv4_dstAddr( io_out_bits_ipv4_dstAddr),
.io_pcIn_valid( io_pcIn_valid),
.io_pcIn_bits_request( io_pcIn_bits_request),
.io_pcIn_bits_moduleId( io_pcIn_bits_moduleId),
.io_pcIn_bits_portId( io_pcIn_bits_portId),
.io_pcIn_bits_pcValue( io_pcIn_bits_pcValue),
.io_pcIn_bits_pcType( io_pcIn_bits_pcType),
.io_pcOut_valid( io_pcOut_valid),
.io_pcOut_bits_request( io_pcOut_bits_request),
.io_pcOut_bits_moduleId( io_pcOut_bits_moduleId),
.io_pcOut_bits_portId( io_pcOut_bits_portId),
.io_pcOut_bits_pcValue( io_pcOut_bits_pcValue),
.io_pcOut_bits_pcType (io_pcOut_bits_pcType)
);
integer count;
assign io_in_bits_l2Protocol = 8'd128;
assign io_in_bits_eth_l3Type = 8'd64;
assign io_in_bits_ipv4_ttl = 8'd3;
assign io_in_valid = 1'b1;
assign io_out_ready = 1'b1;
always @(negedge clk) begin;
#50;
end
always @(posedge clk) begin
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int m[1000][1000]; int main() { m[0][0] = 1; m[0][1] = 2; m[1][0] = 2; m[1][1] = 3; m[2][0] = 3; m[2][1] = 1; int n; scanf( %d , &n); int g = 4; int d = 2; int cur = 0; while (g <= n) { m[cur][d] = g; ++g; if (cur == d) { ++d; for (int i = 0; i < d; ++i) { m[d][i] = m[i][d - 1]; } cur = 0; } else ++cur; } printf( %d n , d + 1); for (int i = 0; i <= d; ++i) { for (int j = 0; j < d; ++j) { printf( %d , m[i][j]); } printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_1_V
`define SKY130_FD_SC_HDLL__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_1_V
|
#include <bits/stdc++.h> using namespace std; namespace fgraph { const int MAXV = 50; const int MAXE = 10 * MAXV * MAXV; const int INF = (1 << 30); struct edge { int to, cap, flow, cost; edge *nxt, *rev; } edges[MAXE + 5], *adj[MAXV + 5], *cur[MAXV + 5], *ecnt = edges; void addedge(int u, int v, int c, int w) { edge *p = (++ecnt), *q = (++ecnt); (*p) = (edge){v, c, 0, w, adj[u], q}, adj[u] = p; (*q) = (edge){u, 0, 0, -w, adj[v], p}, adj[v] = q; } int d[MAXV + 5], h[MAXV + 5], s, t; bool relabel() { for (int i = s; i <= t; i++) h[i] += d[i], d[i] = INF, cur[i] = adj[i]; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > que; que.push(make_pair(d[t] = 0, t)); while (!que.empty()) { int k = que.top().first, x = que.top().second; que.pop(); if (k != d[x]) continue; for (edge *p = adj[x]; p; p = p->nxt) { if (p->rev->cap > p->rev->flow) { int dis = k + p->rev->cost + (h[x] - h[p->to]); if (dis < d[p->to]) que.push(make_pair(d[p->to] = dis, p->to)); } } } return d[s] != INF; } bool vis[MAXV + 5]; int aug(int x, int tot) { if (x == t) return tot; vis[x] = true; int sum = 0; for (edge *&p = cur[x]; p; p = p->nxt) { int dis = d[p->to] + p->cost + (h[p->to] - h[x]); if (d[x] == dis && !vis[p->to] && p->cap > p->flow) { int del = aug(p->to, min(tot - sum, p->cap - p->flow)); sum += del, p->flow += del, p->rev->flow -= del; if (sum == tot) break; } } vis[x] = false; return sum; } } // namespace fgraph int f[55]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); fgraph::addedge(u, v, 1, w); } int cnt = 0; fgraph::s = 1, fgraph::t = n; for (cnt = 0; fgraph::relabel(); cnt++) f[cnt + 1] = f[cnt] + fgraph::d[1] + fgraph::h[1], fgraph::aug(1, 1); int q; scanf( %d , &q); for (int i = 1; i <= q; i++) { int x; scanf( %d , &x); double ans = 1E12; for (int j = 1; j <= cnt; j++) ans = min(ans, 1.0 * (x + f[j]) / j); printf( %.9f n , ans); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:44:06 07/28/2013
// Design Name:
// Module Name: SimpleQuadratureCounter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BBot_SimpleQuadratureCounter(
input clock,
input reset_l,
input A,
input B,
output [31:0] CurrentCount,
output Direction
);
reg BPrevious;
reg APrevious;
reg ACurrent;
reg BCurrent;
reg[31:0] Count;
reg[31:0] CountOutput;
reg Dir;
reg DirectionOutput;
always @(posedge clock) begin
if (reset_l == 1'b0)
begin
Count[31:0] <= 32'h80000000;
end
else
begin
if( (APrevious != A) || (BPrevious != B))
begin
//Every time A or B changes evaluate this XOR
//If the result is 1 we count up if it's 0 we count down
if (A ^ BPrevious)
begin
Count <= Count + 1'b1;
Dir <= 1'b1;
end
else begin
Count <= Count - 1'b1;
Dir <= 1'b0;
end
end
end
end
always @(negedge clock) begin
//On the negedge of clock set the previous values and
//send the count out the door
APrevious <= A;
BPrevious <= B;
CountOutput <= Count;
DirectionOutput <= Dir;
end
assign CurrentCount = CountOutput;
assign Direction = DirectionOutput;
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[200010]; int main() { int n; cin >> n; if (n & 1) { puts( YES ); bool f = true; for (int i = 0; i < n; i++) { if (f) ans[i + n] = (i + 1) * 2, ans[i] = (i + 1) * 2 - 1; else ans[i] = (i + 1) * 2, ans[i + n] = (i + 1) * 2 - 1; f = !f; } for (int i = 0; i < (n * 2); i++) { cout << ans[i] << ; } } else puts( NO ); }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007; const long long int p = 27; string s; long long int hashnum(int lw, int up) { if ((up - lw) % 2 == 0) return (((hashnum(lw, (lw + up) / 2) * p) % mod + 1) * ((hashnum((lw + up) / 2, up) * p) % mod + 1)) % mod; long long int res = 0; for (int i = lw; i < up; i++) { res *= p; res %= mod; res += (s[i] - a ); res %= mod; } return res; } int main() { cin >> s; long long int tmp = hashnum(0, s.length()); cin >> s; long long int tmp1 = hashnum(0, s.length()); if (tmp == tmp1) puts( YES ); else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; char str[110]; int n, ans, len; bool arr[110][220][55][2]; int main() { scanf( %s%d , str + 1, &n); len = strlen(str + 1); arr[0][100][0][0] = true; for (int i = 1; str[i]; ++i) for (int j = 100 - i; j <= 100 + i; ++j) for (int k = 0; k <= i && k <= n; ++k) for (int l = 0; l <= 1; ++l) { if (str[i] == T ) { if (arr[i - 1][j][k][l ^ 1]) arr[i][j][k][l] = true; if (k > 0 && (arr[i - 1][j + ((l == 0) ? -1 : 1)][k - 1][l])) arr[i][j][k][l] = true; } else { if (arr[i - 1][j + ((l == 0) ? -1 : 1)][k][l]) arr[i][j][k][l] = true; if (k > 0 && arr[i - 1][j][k - 1][l ^ 1]) arr[i][j][k][l] = true; } } for (int j = 100 - len; j <= 100 + len; ++j) for (int k = n; k >= 0; k -= 2) for (int l = 0; l <= 1; ++l) if (arr[len][j][k][l]) ans = max(ans, abs(100 - j)); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, a[200005 / 2], ans = -1, cnt = 0; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> k; for (int i = 1; i <= n + 1; i++) { if (i < n + 1) cin >> a[i]; else a[i] = a[i - 1]; if (a[i] != a[i - 1]) cnt++; else { ans = max(ans, cnt); cnt = 1; } ans = max(ans, cnt); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; using lint = long long; const lint linf = 1e18 + 7; const lint inf = 1e9 + 7; const int MOD = 1000000007; void press(vector<long long>& x) { map<int, int> memo; int n = x.size(); for (int i = 0; i < n; ++i) { memo[x[i]] += 1; } int cur = 1; for (auto& val : memo) { val.second = cur; ++cur; } for (int i = 0; i < n; ++i) { x[i] = memo[x[i]]; } } void solve() { int n; cin >> n; vector<lint> a(n, 0); for (int i = 0; i < n; ++i) cin >> a[i]; auto b = a; press(b); vector<vector<int>> dp(n + 5, vector<int>(3, 0)); vector<int> cnt(n + 5, 0); for (int i = 0; i < n; ++i) cnt[b[i]] += 1; int res = n - 1; for (int i = 0; i < n; ++i) { if (dp[b[i]][0] == 0) { dp[b[i]][0] = max(dp[b[i] - 1][1], dp[b[i] - 1][2]) + 1; } if (dp[b[i]][1] + 1 < cnt[b[i]]) { ++dp[b[i]][1]; } else { dp[b[i]][2] = dp[b[i]][0] + dp[b[i]][1]; dp[b[i]][1] += 1; } int hoge = dp[b[i]][1] + cnt[b[i] + 1] - dp[b[i] + 1][1]; res = min(res, n - hoge); hoge = cnt[b[i]] - dp[b[i]][1] + dp[b[i] - 1][2] + 1; res = min(res, n - hoge); } for (int i = 1; i <= n; ++i) { for (int j = 0; j < 3; ++j) { res = min(res, n - dp[i][j]); } } cout << res << n ; } signed main() { cin.tie(0); ios::sync_with_stdio(false); int t; cin >> t; for (int i = 0; i < t; ++i) { solve(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module fft32( CLK ,RST ,ED ,START ,DReal ,DImag ,RDY ,DOReal ,DOImag, ifft ); //Add overflow , check weather shift & ADDR is needed
parameter total_bits = 32;
input CLK;
input RST;
input ED;
input START;
input ifft;
input [total_bits-1:0] DReal;
input [total_bits-1:0] DImag;
output reg RDY;
output [total_bits-1:0] DOReal;
output [total_bits-1:0] DOImag;
wire [total_bits-1:0] dr1;
wire [total_bits-1:0] di1;
wire [total_bits+3:0] dr2;
wire [total_bits+3:0] di2;
wire [total_bits-1:0] dr3;
wire [total_bits-1:0] di3;
wire [total_bits-1:0] dr4;
wire [total_bits-1:0] di4;
wire rdy1,rdy2,rdy3;
wire [3:0] ADDR;
reg [5:0] AR;
assign ADDR = AR[3:0];
initial
AR<=0;
RAM1 #(total_bits) ram_1(.CLK(CLK),.RST(RST),.ED(ED),.START(START),.DReal(DReal),.DImag(DImag),.RDY(rdy1),.DOReal(dr1),.DOImag(di1));
fft16 #(total_bits) fft_16(.ED(ED),.RST(RST),.CLK(CLK),.START(rdy1),.ifft(ifft),.DIImag(di1),.DIReal(dr1),.DOImag(di2),.DOReal(dr2),.RDY(rdy2));
weight #(total_bits) wcalc(.CLK(CLK) ,.RST(RST),.ED(ED),.START(rdy2),.DReal(dr2[total_bits-1:0]),.DImag(di2[total_bits-1:0]),.DOReal(dr3),.DOImag(di3),.RDY(rdy3));
odd_RAM #(total_bits) oram(.CLK(CLK),.RST(RST),.ED(ED),.START(rdy2),.ADDR(ADDR),.DReal(dr2[total_bits-1:0]),.DImag(di2[total_bits-1:0]),.DOReal(dr4),.DOImag(di4));
reg [total_bits-1:0] data_ra[0:15];
reg [total_bits-1:0] data_im[0:15];
reg [1:0] state;
reg [total_bits-1:0] ra;
reg [total_bits-1:0] im;
assign DOReal = ra;
assign DOImag = im;
always@(posedge CLK)begin
if(RST) begin
AR<=32;
state<=0;
end
else if(rdy3) begin
AR<=0;
state<=1;
end
else if(ED)begin
RDY<=0;
if(state==1) begin //Check for overflow
ra<=dr4 + dr3;
im<=di4 + di3;
data_ra[AR[3:0]] <= dr4 - dr3;
data_im[AR[3:0]] <= di4 - di3;
end
else if(state==2) begin
ra <= data_ra[AR[3:0]];
im <= data_im[AR[3:0]];
end
if(AR==15)
state<=2;
if(AR<32)
AR<=AR+1;
if(AR==0&&state==1)
RDY<=1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_BLACKBOX_V
`define SKY130_FD_SC_HD__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_BLACKBOX_V
|
/*
* 8-bit rotate module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_rxr8 (
input [7:0] x,
input ci,
input [3:0] y,
input e,
output reg [7:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[7:1]} : {ci, x[0], x[7:1]};
5'd02: {co,w} <= e ? {x[1:0], ci, x[7:2]} : {ci, x[1:0], x[7:2]};
5'd03: {co,w} <= e ? {x[2:0], ci, x[7:3]} : {ci, x[2:0], x[7:3]};
5'd04: {co,w} <= e ? {x[3:0], ci, x[7:4]} : {ci, x[3:0], x[7:4]};
5'd05: {co,w} <= e ? {x[4:0], ci, x[7:5]} : {ci, x[4:0], x[7:5]};
5'd06: {co,w} <= e ? {x[5:0], ci, x[7:6]} : {ci, x[5:0], x[7:6]};
5'd07: {co,w} <= e ? {x[6:0], ci, x[7]} : {ci, x[6:0], x[7]};
5'd08: {co,w} <= {x,ci};
endcase
endmodule
|
/***********************************************************************
Single Port RAM that maps to a Xilinx/Lattice BRAM
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This is a program memory for the AVR. It maps to a Xilinx/Lattice
BRAM.
This version can be modified by the CPU (i. e. SPM instruction)
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the BSD license
------------------------------------------------------------------------------
Design unit: SinglePortPM(Xilinx) (Entity and architecture)
File name: pm_s_rw.in.v (template used)
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
Target FPGA: Spartan 3 (XC3S1500-4-FG456)
iCE40 (iCE40HX4K)
Language: Verilog
Wishbone: No
Synthesis tools: Xilinx Release 9.2.03i - xst J.39
iCEcube2.2016.02
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module lattuino_1_blPM_4
#(
parameter WORD_SIZE=16,// Word Size
parameter FALL_EDGE=0, // Ram clock falling edge
parameter ADDR_W=13 // Address Width
)
(
input clk_i,
input [ADDR_W-1:0] addr_i,
output [WORD_SIZE-1:0] data_o,
input we_i,
input [WORD_SIZE-1:0] data_i
);
localparam ROM_SIZE=2**ADDR_W;
reg [ADDR_W-1:0] addr_r;
reg [WORD_SIZE-1:0] rom[0:ROM_SIZE-1];
initial begin
$readmemh("../../../Work/lattuino_1_bl_4_v.dat",rom,1720);
end
generate
if (!FALL_EDGE)
begin : use_rising_edge
always @(posedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_rising_edge
else
begin : use_falling_edge
always @(negedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_falling_edge
endgenerate
assign data_o=rom[addr_r];
endmodule // lattuino_1_blPM_4
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O2111AI_PP_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, q; cin >> n >> m >> q; int a[n][m]; struct a { int o; int p; } arr[q]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } int fo[n]; for (int i = 0; i < n; i++) { int c = 0; int max = 0; for (int j = 0; j < m; j++) { if (a[i][j] == 1) c++; if (c > max) max = c; if (a[i][j] == 0) c = 0; } fo[i] = max; } for (int i = 0; i < q; i++) { cin >> arr[i].o; cin >> arr[i].p; arr[i].o--; arr[i].p--; } for (int i = 0; i < q; i++) { a[arr[i].o][arr[i].p] = a[arr[i].o][arr[i].p] ^ 1; int max = 0; int c = 0; for (int j = 0; j < m; j++) { if (a[arr[i].o][j] == 1) c++; if (c > max) max = c; if (a[arr[i].o][j] == 0) c = 0; } fo[arr[i].o] = max; int maxi = 0; for (int j = 0; j < n; j++) { if (fo[j] > maxi) maxi = fo[j]; } cout << maxi << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long Maxn = 1e5 + 7; const long long Max = 1e3 + 7; const long long Mod = 1e9 + 7; const long long Inf = 1e9 + 7; string s[Maxn], V[Maxn]; long long ans[5]; long long check(char t) { if (t == u || t == o || t == a || t == i || t == e ) return true; return false; } void f(long long a, long long b, long long c, long long d) { if (V[a] == V[b] && V[c] == V[d]) ; else ans[1] = 0; if (V[a] == V[c] && V[b] == V[d]) ; else ans[2] = 0; if (V[a] == V[d] && V[c] == V[b]) ; else ans[3] = 0; if (V[a] == V[b] && V[c] == V[d] && V[c] == V[b]) ; else ans[4] = 0; } void print(long long i) { if (i == 1) cout << aabb << endl; if (i == 2) cout << abab << endl; if (i == 3) cout << abba << endl; if (i == 4) cout << aaaa << endl; } int main() { long long n, k; cin >> n >> k; for (long long i = 1; i <= 4 * n; i++) { cin >> s[i]; long long K = k; for (long long j = s[i].size() - 1; K && j >= 0; j--) { V[i] += s[i][j]; if (check(s[i][j])) K--; } if (K) { cout << NO << endl; return 0; } } ans[1] = ans[2] = ans[3] = ans[4] = 1; for (long long i = 1; i <= n; i++) { long long st = (i - 1) * 4; f(st + 1, st + 2, st + 3, st + 4); } for (long long i = 4; i >= 1; i--) { if (ans[i]) { print(i); return 0; } } cout << NO << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e+5; char str[2 * maxn + 5]; int main() { int cishu; cin >> cishu; while (cishu--) { int n; cin >> n; for (int a = 0; a < n - 1; a++) cin >> str[a]; str[n - 1] = 0 ; int tmp = n; for (int i = 0; i < n; i++) { if (str[i] == < ) { int amt = 2; for (int a = i + 1; a < n; a++) { if (str[a] == < ) amt++; else break; } int print = tmp - amt + 1; tmp = print - 1; for (int b = 0; b < amt; b++) printf( %d%c , print++, i + b == n - 1 ? n : ); i = i + amt - 1; } else printf( %d%c , tmp--, i == n - 1 ? n : ); } tmp = 1; for (int i = 0; i < n; i++) { if (str[i] == > ) { int amt = 2; for (int a = i + 1; a < n; a++) { if (str[a] == > ) amt++; else break; } int print = tmp + amt - 1; tmp = print + 1; for (int b = 0; b < amt; b++) printf( %d%c , print--, i + b == n - 1 ? n : ); i = i + amt - 1; } else printf( %d%c , tmp++, i == n - 1 ? n : ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int num; while (n--) { scanf( %d , &num); printf( %d n , num > 2 ? num - 2 : 0); } }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
wire valid_start_state;
wire valid_next_state;
assign valid_test_expr = ~((^test_expr)^(^test_expr));
assign valid_start_state = ~((^start_state)^(^start_state));
assign valid_next_state = ~((^next_state)^(^next_state));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SHARED_CODE
reg [width-1:0] r_start_state, r_next_state;
reg assert_state;
`ifdef OVL_SYNTHESIS
`else
initial begin
assert_state = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (valid_start_state == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_state contains X or Z");
end
if (valid_next_state == 1'b1)
begin
// Do nothing
end
else
begin
if (start_state != test_expr)
begin
// Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"next_state contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (assert_state == 1'b0) begin // INIT_STATE
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
end
else begin // CHECK_STATE
if (test_expr == r_next_state) begin
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
else
assert_state <= 1'b0; // done ok.
end
else if (test_expr != r_start_state) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Test expression transitioned from value start_state to a value other than next_state"); // test_expr moves to unexpected state
`endif // OVL_ASSERT_ON
if (test_expr == start_state) begin
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("start_state covered");
end
end
`endif // OVL_COVER_ON
assert_state <= 1'b1; // CHECK_STATE
r_start_state <= start_state;
r_next_state <= next_state;
end
else
assert_state <= 1'b0; // done error.
end
end
end
else begin
assert_state <= 1'b0;
r_start_state <= {width{1'b0}};
r_next_state <= {width{1'b0}};
end
end // always
`endif // OVL_SHARED_CODE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_2_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_2_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s25 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s25.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_2_V
|
/*
* Copyright (c) 2000 Chris Lattner <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test;
reg [31:0] buff[256*2*2-1:0];
reg [31:0] x;
initial
begin
buff[0] = 0;
x = 256;
buff[x+0] = 1234;
if (buff[0] != 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int div1(int a, int b) { if (a % b == 0) return a / b; else return a / b + 1; } int main() { int k, n, s, p; while (scanf( %d%d%d%d , &k, &n, &s, &p) != EOF) { int ever_need = div1(n, s); int ans = div1(ever_need * k, p); printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 203; const int mod = 1e9 + 7; vector<int> g[N]; int dp[N]; int ans, n; int len1, len2; void cal(int u, int fa, int &len) { dp[u] = 0; int &mx1 = dp[u], mx2 = 0; int v; for (__typeof((g[u]).begin()) v = (g[u]).begin(); v != (g[u]).end(); v++) { if (*v == fa) continue; cal(*v, u, len); if (mx2 < dp[*v] + 1) { mx2 = dp[*v] + 1; if (mx2 > mx1) swap(mx1, mx2); } } len = max(len, mx1 + mx2); } void dfs(int u, int fa) { int v; for (__typeof((g[u]).begin()) v = (g[u]).begin(); v != (g[u]).end(); v++) { if (*v == fa) continue; len1 = len2 = 0; cal(*v, u, len1); cal(u, *v, len2); ans = max(ans, len1 * len2); dfs(*v, u); } } int main() { int i, j; scanf( %d , &n); for (i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } dfs(1, 0); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[10000], m, x, v[10000], sol[10000]; void g(int n) { for (int i = 2; i <= 1000; i++) { for (int q = i; q <= 1000; q++) { if (q % i != 0 && i * q <= 1000) v[i * q] = 1; } } } int main() { int k = 0; cin >> n; g(n); for (int i = 2; i <= n; i++) { if (v[i] == 0) { sol[k] = i; k++; } } cout << k << endl; for (int i = 0; i < k; i++) { cout << sol[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long N, K; long long Top, Bot, H[200005], cnt[200005]; long long hcnt[200005]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N >> K; Top = 0, Bot = 2e5; for (int i = 0; i <= N - 1; i++) { cin >> H[i]; cnt[H[i]]++; Top = max(Top, H[i]); Bot = min(Bot, H[i]); } long long curc = 0; for (int i = Top; i >= 1; i--) { curc += cnt[i]; hcnt[i] += curc; } long long cutt = 0; int ans = 0; for (int i = Top; i >= Bot + 1; i--) { if (cutt + hcnt[i] > K) { ans++; cutt = hcnt[i]; } else cutt += hcnt[i]; } if (cutt) ans++; cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1100; const long long M = 260; const long long mod = 998244353; const long long MOD = 998244353; const long double eps = 0.000000001; const long long P = 1336; const long long inf = 1e16; mt19937 gen(chrono::high_resolution_clock::now().time_since_epoch().count()); long long n, k; vector<pair<long long, long long> > a; long long dp[N][N]; long long solve(long long x) { for (long long j = 0; j < k; j++) { for (long long i = 0; i < n; i++) { dp[j][i] = 0; if (j == 0) dp[j][i] = 1; } } long long ans = 0; for (long long j = 1; j < k; j++) { long long uk = 0, s = 0; for (long long i = 0; i < n; i++) { while (uk < n && a[uk].first + x <= a[i].first) { s += dp[j - 1][uk]; s %= mod; uk++; } dp[j][i] = s; if (j == k - 1) { ans += dp[j][i]; ans %= mod; } } } return ans; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); srand(time(0)); cin >> n >> k; a.resize(n); long long ma = 0; for (long long i = 0; i < n; i++) { cin >> a[i].first; ma = max(ma, a[i].first); a[i].second = i; } sort(a.begin(), a.end()); long long ans = 0, s = 0; for (long long i = ma / (k - 1); i >= 1; i--) { long long c = solve(i); c -= s; c += mod; c %= mod; s += c; s %= mod; c *= i; c %= mod; ans += c; ans %= mod; } cout << ans; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:32 06/24/2014
// Design Name:
// Module Name: seg_scroll
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg_scroll(
input clk,
input clr,
input [19:0] scroll_datain,
output [15:0] scroll_dataout
);
reg [26:0] q;
reg [23:0] msg_array;
always @(posedge clk_3 or posedge clr)
begin
if(clr==1)
begin
msg_array [19:0] <= scroll_datain[19:0];
msg_array [23:20] <= 'hC;
end
else
begin
msg_array [19:0] <= msg_array[23:4];
msg_array [23:20] <= msg_array[3:0];
end
end
assign scroll_dataout[15:0] = msg_array[15:0];
// 3 Hz scroll clk generator
always @(posedge clk or posedge clr)
begin
if(clr==1)
q<=0;
else
q<=q+1;
end
assign clk_3 = q[26];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// input clk is 24MHz
`include "min_max_tracker.v"
module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,
output [7:0] max, output [7:0] min,
output [7:0] high_threshold, output [7:0] highz_threshold,
output [7:0] lowz_threshold, output [7:0] low_threshold,
output edge_state, output edge_toggle);
min_max_tracker tracker(clk, adc_d, lf_ed_threshold, min, max);
// auto-tune
assign high_threshold = (max + min) / 2 + (max - min) / 4;
assign highz_threshold = (max + min) / 2 + (max - min) / 8;
assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
assign low_threshold = (max + min) / 2 - (max - min) / 4;
// heuristic to see if it makes sense to try to detect an edge
wire enabled =
(high_threshold > highz_threshold)
& (highz_threshold > lowz_threshold)
& (lowz_threshold > low_threshold)
& ((high_threshold - highz_threshold) > 8)
& ((highz_threshold - lowz_threshold) > 16)
& ((lowz_threshold - low_threshold) > 8);
// Toggle the output with hysteresis
// Set to high if the ADC value is above the threshold
// Set to low if the ADC value is below the threshold
reg is_high = 0;
reg is_low = 0;
reg is_zero = 0;
reg trigger_enabled = 1;
reg output_edge = 0;
reg output_state;
always @(posedge clk)
begin
is_high <= (adc_d >= high_threshold);
is_low <= (adc_d <= low_threshold);
is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
end
// all edges detection
always @(posedge clk)
if (enabled) begin
// To enable detecting two consecutive peaks at the same level
// (low or high) we check whether or not we went back near 0 in-between.
// This extra check is necessary to prevent from noise artifacts
// around the threshold values.
if (trigger_enabled & (is_high | is_low)) begin
output_edge <= ~output_edge;
trigger_enabled <= 0;
end else
trigger_enabled <= trigger_enabled | is_zero;
end
// edge states
always @(posedge clk)
if (enabled) begin
if (is_high)
output_state <= 1'd1;
else if (is_low)
output_state <= 1'd0;
end
assign edge_state = output_state;
assign edge_toggle = output_edge;
endmodule
|
`default_nettype none
`define CLKFREQ 36000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk
);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk
);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data // data
);
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[20000], i, j, s = 1; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n; i++) { if (a[i] % 2) { printf( %d n , (s + a[i]) / 2); s *= -1; } else printf( %d n , a[i] / 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> tree[n + 1]; for (int i = 2; i <= n; i++) { int p; cin >> p; tree[p].push_back(i); } bool is_spruce = true; for (int i = 1; i <= n; i++) { if (tree[i].empty()) continue; else { int count = 0; for (auto c : tree[i]) { if (count == 3) break; if (tree[c].size() == 0) count++; } if (count != 3) { is_spruce = false; break; } } } if (is_spruce) cout << Yes << endl; else cout << No << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_PP_V
/**
* iso1n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SLEEP, SLEEP, VPWR, KAGND );
or or0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_SLEEP);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<pair<int, int> > v; for (int i = 0; i < n; i++) { int a; cin >> a; v.push_back(make_pair(a, i)); } sort(v.begin(), v.end()); int cur = 0; vector<int> ans; for (int i = 0; i < v.size() && cur + v[i].first <= k; i++) { cur += v[i].first; ans.push_back(v[i].second); } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) { cout << ans[i] + 1 << ; } }
|
#include <bits/stdc++.h> using namespace std; struct trip { int a, b, c; }; const int MAXINT = 100; int n, temp; vector<int> pos, neg; bool zeros = false; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> temp; if (temp > 0) pos.push_back(temp); else if (temp < 0) neg.push_back(temp); else zeros = true; } if (!pos.size() && !neg.size()) cout << 0 << endl; if (pos.size() == 0 && neg.size() == 1) { if (zeros) cout << 0 << endl; else cout << neg[0] << endl; } for (int e : pos) cout << e << ; if (neg.size() % 2 == 0) for (int e : neg) cout << e << ; else { sort(neg.begin(), neg.end()); int N = neg.size(); for (int i = 0; i < N - 1; i++) cout << neg[i] << ; } return 0; }
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic ODDR module
*/
module oddr #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] d1,
input wire [WIDTH-1:0] d2,
output wire [WIDTH-1:0] q
);
/*
Provides a consistent output DDR flip flop across multiple FPGA families
_____ _____ _____ _____
clk ____/ \_____/ \_____/ \_____/ \_____
_ ___________ ___________ ___________ ___________ __
d1 _X____D0_____X____D2_____X____D4_____X____D6_____X__
_ ___________ ___________ ___________ ___________ __
d2 _X____D1_____X____D3_____X____D5_____X____D7_____X__
_____ _____ _____ _____ _____ _____ _____ _____ ____
d _____X_D0__X_D1__X_D2__X_D3__X_D4__X_D5__X_D6__X_D7_
*/
genvar n;
generate
if (TARGET == "XILINX") begin
for (n = 0; n < WIDTH; n = n + 1) begin : oddr
if (IODDR_STYLE == "IODDR") begin
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.SRTYPE("ASYNC")
)
oddr_inst (
.Q(q[n]),
.C(clk),
.CE(1'b1),
.D1(d1[n]),
.D2(d2[n]),
.R(1'b0),
.S(1'b0)
);
end else if (IODDR_STYLE == "IODDR2") begin
ODDR2 #(
.DDR_ALIGNMENT("C0"),
.SRTYPE("ASYNC")
)
oddr_inst (
.Q(q[n]),
.C0(clk),
.C1(~clk),
.CE(1'b1),
.D0(d1[n]),
.D1(d2[n]),
.R(1'b0),
.S(1'b0)
);
end
end
end else if (TARGET == "ALTERA") begin
altddio_out #(
.WIDTH(WIDTH),
.POWER_UP_HIGH("OFF"),
.OE_REG("UNUSED")
)
altddio_out_inst (
.aset(1'b0),
.datain_h(d1),
.datain_l(d2),
.outclocken(1'b1),
.outclock(clk),
.aclr(1'b0),
.dataout(q)
);
end else begin
reg [WIDTH-1:0] d_reg_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] d_reg_2 = {WIDTH{1'b0}};
reg [WIDTH-1:0] q_reg = {WIDTH{1'b0}};
always @(posedge clk) begin
d_reg_1 <= d1;
d_reg_2 <= d2;
end
always @(posedge clk) begin
q_reg <= d1;
end
always @(negedge clk) begin
q_reg <= d_reg_2;
end
assign q = q_reg;
end
endgenerate
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; long long iHateGeometry[100001]; int main() { int N; scanf( %d , &N); long long maxi = -1, sum = 0; for (int i = 0; i < N; i++) { scanf( %lld , &iHateGeometry[i]); sum += iHateGeometry[i]; maxi = max(maxi, iHateGeometry[i]); } printf( %lld n , 2 * maxi - sum + 1); }
|
#include <bits/stdc++.h> using namespace std; long long find_smallest_number_with_cumulative_sum_greater_or_equal_than_sum( long long sum) { long long lower = 0, upper = (long long)15E8, mid; while (lower < upper) { mid = (lower + upper) / 2; if (mid * (mid + 1) / 2 >= sum) upper = mid; else lower = mid + 1; } return lower; } long long find_answer(long long n, long long H) { long long lower = H - 1, upper = (long long)15E8, mid; while (lower < upper) { mid = (lower + upper) / 2; long long current_sum = mid * (mid + 1) / 2 - H * (H - 1) / 2; long long remaining_sum = n - current_sum; if (find_smallest_number_with_cumulative_sum_greater_or_equal_than_sum( remaining_sum) <= mid + 1) upper = mid; else lower = mid + 1; } long long current_sum = lower * (lower + 1) / 2 - H * (H - 1) / 2; long long remaining_sum = n - current_sum; long long total_blocks_till_now = lower - (H - 1); return total_blocks_till_now + find_smallest_number_with_cumulative_sum_greater_or_equal_than_sum( remaining_sum); } int main() { long long n, H; cin >> n >> H; cout << find_answer(n, H) << endl; return 0; }
|
//From: "Chris Kappler" <>
//Verilint 440 off // WARNING: Clock is used as a reset
//Verilint 394 off // WARNING: Multiple clocks in the always block
//Verilint 71 off // WARNING: Case statement without default clause
module x (/*AUTOARG*/
// Outputs
a, b, c,
// Inputs
clk, reset_l, in_a, in_b, in_c
);
input clk, reset_l, in_a,in_b,in_c;
output a,b,c;
reg a,b,c;
always @(posedge clk or negedge reset_l) begin
if (!reset_l) begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= #1 0;
b <= #1 0;
// End of automatics
end
else begin
a <= in_a;
b <= in_b;
c <= in_c;
end
end
always @(posedge clk or negedge reset_l) begin
casex ({reset_l,in_a})
2'b1_x: begin
a <= in_a;
b <= in_b;
c <= in_c;
end
2'b0_x: begin
c <= 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a <= #1 0;
b <= #1 0;
// End of automatics
end
endcase
end
always @(/*AS*/in_a or in_b or reset_l) begin
casex ({reset_l,in_a})
2'b1_x: begin
a = in_a;
b = in_b;
end
2'b0_x: begin
c = 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a = 0;
b = 0;
// End of automatics
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: nil
// verilog-assignment-delay: "#1 "
// End:
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; const int maxm = 2000005; const int inf = 0x3f3f3f3f; const int mod = 1000000000 + 7; void init() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); }; int n, m; vector<int> v[100005]; vector<int> vv[100005]; int sum[100005]; int to[100005]; int cnt = 0; bool cmp(int x, int y) { return x > y; } int main() { init(); cin >> n >> m; int mx = 0; int top = 0; for (int i = 1; i <= n; i++) { int id, score; cin >> id >> score; if (sum[id] == 0) to[++cnt] = id; v[id].push_back(score); sum[id]++; mx = max(mx, sum[id]); } for (int kk = 1; kk <= cnt; kk++) { int i = to[kk]; sort(v[i].begin(), v[i].end(), cmp); if (v[i].size()) vv[i].push_back(v[i][0]); for (int j = 1; j < v[i].size(); j++) { int k = vv[i][j - 1]; if (k <= 0) break; vv[i].push_back(k + v[i][j]); } } int ans = 0; for (int i = 1; i <= mx; i++) { int tmp = 0; for (int k = 1; k <= cnt; k++) { int j = to[k]; if (sum[j] < i) continue; if (i > vv[j].size()) continue; if (vv[j][i - 1] < 0) continue; tmp += vv[j][i - 1]; } ans = max(ans, tmp); } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vpi = vector<pair<int, int>>; using pi = pair<int, int>; const int nax = 1e5 + 7; const int mod = 1e9 + 7; const int inf = numeric_limits<int>::max() - (int)9e6; struct monotonic_queue { queue<int> qu; deque<int> mx, mn; void push(int v) { qu.push(v); while (mx.size() && mx.back() < v) mx.pop_back(); mx.push_back(v); while (mn.size() && mn.back() > v) mn.pop_back(); mn.push_back(v); } void pop() { if (mx.front() == qu.front()) mx.pop_front(); if (mn.front() == qu.front()) mn.pop_front(); qu.pop(); } int front() const { return qu.front(); } int max() const { return mx.front(); } int min() const { return mn.front(); } int size() const { return qu.size(); } bool empty() { return qu.empty(); } }; int n; void test() { cin >> n; int s, l; cin >> s >> l; vi v(n); for (int i = 0; i < (int)n; i++) cin >> v[i]; monotonic_queue q; vi g(n, n); for (int i = n - 1, j = n - 1; i >= 0; i--) { while (j >= 0 and (q.empty() or (((q.max() - q.min()) <= s)))) { q.push(v[j--]); } g[i] = (((q.max() - q.min()) <= s) ? j : j + 1); if (((int)(q).size())) q.pop(); } while (((int)(q).size())) q.pop(); vi dp(n + 1, inf); dp[0] = 0; for (int i = l, j = 0; i <= n; i++) { q.push(dp[i - l]); while (((int)(q).size()) and j <= g[i - 1]) q.pop(), j++; if (((int)(q).size())) dp[i] = q.min() + 1; } cout << (dp[n] >= inf ? -1 : dp[n]); } signed main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); int T = 1; while (T--) { test(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100100; int N, M; int app[MAXN]; char type[MAXN]; int P[MAXN]; bool check(int leader) { set<int> users; users.insert(leader); for (int i = 0; i < M; i++) { if (type[i] == + ) users.insert(P[i]); else users.erase(P[i]); if (!users.empty() && users.find(leader) == users.end()) return false; } return true; } int main() { cin >> N >> M; for (int i = 0; i < M; i++) cin >> type[i] >> P[i]; int offp = 0; for (int i = 0; i < M; i++) { if (type[i] == - && !app[P[i]]) offp = P[i]; app[P[i]] = true; } if (offp != 0) { if (check(offp)) app[offp] = false; } else { if (check(P[0])) app[P[0]] = false; } int total = 0; for (int i = 1; i <= N; i++) total += !app[i]; cout << total << n ; for (int i = 1; i <= N; i++) if (!app[i]) cout << i << ; return 0; }
|
(
input rst_b,
input p1_clk,
input p1_select,
input p1_rdnw,
input p2_clk,
input p2_select,
input p2_rdnw,
output p2_data_available,
output p1_full
);
// Initial state: 0 = empty; 1 = full
parameter init = 0;
reg req;
reg req_s1;
reg req_s2;
reg ack;
reg ack_s1;
reg ack_s2;
always @ (`p1edge p1_clk or negedge rst_b )
begin
if (!rst_b) begin
req <= init;
ack_s1 <= 1'b0;
ack_s2 <= 1'b0;
end else begin
ack_s1 <= ack;
ack_s2 <= ack_s1;
case (req)
1'b0:
if (!ack_s2 & p1_select & !p1_rdnw)
req <= 1'b1;
1'b1:
if (ack_s2)
req <= 1'b0;
endcase
end
end
assign p1_full = req | ack_s2;
always @ (`p2edge p2_clk or negedge rst_b )
begin
if (!rst_b) begin
ack <= 1'b0;
req_s1 <= init;
req_s2 <= init;
end else begin
req_s1 <= req;
req_s2 <= req_s1;
case (ack)
1'b0:
if (req_s2 & p2_select & p2_rdnw)
ack <= 1'b1;
1'b1:
if (!req_s2)
ack <= 1'b0;
endcase
end
end
assign p2_data_available = !ack & req_s2;
endmodule
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#include <bits/stdc++.h> using namespace std; int p[] = {0, 5, 7, 5}; int main() { for (int k = 1; k <= 3; k++) { string s; getline(cin, s); int tot = 0; for (int i = 0; i < s.size(); i++) if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u ) tot++; if (tot != p[k]) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } inline void judge() { freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); } const int maxn = 200005; int n, Q, s[maxn], m[maxn], t[maxn], l[maxn], r[maxn], R[maxn]; set<pair<pair<int, int>, int> > res; namespace seg { long long suma[maxn << 5], sumb[maxn << 5]; int ls[maxn << 5], rs[maxn << 5], tot; inline void update(int x) { suma[x] = suma[ls[x]] + suma[rs[x]]; sumb[x] = sumb[ls[x]] + sumb[rs[x]]; } inline void add(int x, int &y, int place, int va, int vb, int l, int r) { y = ++tot; suma[y] = suma[x]; sumb[y] = sumb[x]; ls[y] = ls[x]; rs[y] = rs[x]; suma[y] += va; sumb[y] += vb; if (l == r) { return; } int md = (l + r) >> 1; if (place <= md) add(ls[x], ls[y], place, va, vb, l, md); else add(rs[x], rs[y], place, va, vb, md + 1, r); } inline long long queryA(int x, int l, int r, int lq, int rq) { if (!x) return 0; if (lq <= l && r <= rq) return suma[x]; long long res = 0; int md = (l + r) >> 1; if (lq <= md) res += queryA(ls[x], l, md, lq, rq); if (rq > md) res += queryA(rs[x], md + 1, r, lq, rq); return res; } inline long long queryB(int x, int l, int r, int lq, int rq) { if (!x) return 0; if (lq <= l && r <= rq) return sumb[x]; long long res = 0; int md = (l + r) >> 1; if (lq <= md) res += queryB(ls[x], l, md, lq, rq); if (rq > md) res += queryB(rs[x], md + 1, r, lq, rq); return res; } } // namespace seg int qtot = 0; int root[maxn]; inline long long query(int l, int r, int tme) { tme = min(tme, 99999); return seg::queryA(root[r], 0, 100001, 0, tme) - seg::queryA(root[l - 1], 0, 100001, 0, tme) + 1ll * (seg::queryB(root[r], 0, 100001, tme + 1, 100001) - seg::queryB(root[l - 1], 0, 100001, tme + 1, 100001)) * tme; } int main() { read(n); for (int i = (1); i <= (n); i++) read(s[i]), read(m[i]), read(R[i]); for (int i = (1); i <= (n); i++) res.insert(make_pair(make_pair(i, i), -1)); read(Q); for (int i = (1); i <= (Q); i++) read(t[i]), read(l[i]), read(r[i]); for (int i = (1); i <= (n); i++) { if (R[i] == 0) { seg::add(root[i - 1], root[i], 100001, 0, R[i], 0, 100001); continue; } int t = floor((long double)m[i] / R[i] + 0.99999999); assert(1ll * t * R[i] >= m[i]); assert(1ll * (t - 1) * R[i] < m[i]); seg::add(root[i - 1], root[i], t, m[i], R[i], 0, 100001); } for (int i = (1); i <= (Q); i++) { long long ans = 0; set<pair<pair<int, int>, int> >::iterator it = res.upper_bound(make_pair(make_pair(l[i], n + 1), 1)); vector<set<pair<pair<int, int>, int> >::iterator> rubi; rubi.clear(); it--; if (it->first.first < l[i]) { res.insert(make_pair(make_pair(it->first.first, l[i] - 1), it->second)); } int tmp1 = it->first.second, tmp2 = it->second; res.erase(it); res.insert(make_pair(make_pair(l[i], tmp1), tmp2)); it = res.upper_bound(make_pair(make_pair(l[i], n + 1), 1)); it--; for (;;) { if (it->second == -1) { assert(it->first.first == it->first.second); ans += min( (long long)m[it->first.first], (long long)s[it->first.first] + 1ll * R[it->first.first] * t[i]); } else { ans += query(it->first.first, min(it->first.second, r[i]), t[i] - it->second); long long res = 0; } rubi.push_back(it); if (it->first.second > r[i]) { res.insert( make_pair(make_pair(r[i] + 1, it->first.second), it->second)); break; } if (it->first.second == r[i]) break; it++; } for (set<pair<pair<int, int>, int> >::iterator x : rubi) res.erase(x); res.insert(make_pair(make_pair(l[i], r[i]), t[i])); cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int n; long long int u; string s; int q; int count(long long int number) { if (!number) return 0; int result = 0; while (number % 2 == 0) { result++; number >>= 1; } return result; } long long int solve(long long int start, string s) { int tmp = count(n + 1) - 1; for (int i = 0; i < s.size(); ++i) { int zeros = count(start); long long int total = ((long long int)1 << (zeros + 1)) - 1; if (s[i] == U ) { if (zeros < tmp) { long long int tmp_one = start + (total - 1) / 2 + 1; long long int tmp_two = start - (total - 1) / 2 - 1; if (count(tmp_one) == zeros + 1) { start = tmp_one; } else start = tmp_two; } } else { if (s[i] == L ) { if (zeros) { long long int left = (total - 1) / 2; start = start - left + ((left - 1) / 2); } } else { if (s[i] == R ) { if (zeros) { long long int right = (total - 1) / 2; start = start + (right - 1) / 2 + 1; } } } } } return start; } int main() { cin >> n >> q; for (int i = 0; i < q; ++i) { cin >> u >> s; cout << solve(u, s) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 400010; const int P = 1000000007; int m, n, mi[N], l[N], r[N]; char a[N], ans[N]; bool Check(int t, int x) { if (++t < x) return 0; return ((r[t] - r[t - x] * mi[x]) * mi[t - x] == l[t] - l[t - x]); } bool Dfs(int k, bool has) { if (k == n) { puts(ans); return true; } for (ans[k] = (has ? a[k] : a ); ans[k] <= z ; ++ans[k]) { l[k + 1] = l[k] + ans[k] * mi[k]; r[k + 1] = r[k] * P + ans[k]; if (!Check(k, m) && !Check(k, m + 1) && Dfs(k + 1, has && (a[k] == ans[k]))) return true; } return false; } int main() { scanf( %d%s , &m, a); int i; for (i = (n = strlen(a)) - 1; i >= 0 && a[i] == z ; --i) a[i] = a ; if (i < 0) { puts( Impossible ); return 0; } ++a[i]; mi[0] = 1; for (int i = 1; i <= n; ++i) mi[i] = mi[i - 1] * P; if (!Dfs(0, 1)) puts( Impossible ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: franp.com
// Engineer: Fran Pregernik <>
//
// Create Date: 01/06/2017 05:35:32 AM
// Design Name:
// Module Name: clk_divider_15_1_mhz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module trig_generator(
// Declare the attributes above the port declaration
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 IN_CLK CLK" *)
// Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
// Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
(* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *)
input IN_CLK, // (required)
output RADAR_TRIG // (required)
);
clk_divider #(300300) cd(
.IN_SIG(IN_CLK),
.OUT_SIG(RADAR_TRIG)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_SYMBOL_V
`define SKY130_FD_IO__TOP_REFGEN_SYMBOL_V
/**
* top_refgen: The REFGEN block (sky130_fd_io__top_refgen) is used to
* provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
* Verilog HDL for "sky130_fd_io",
* "sky130_fd_io_top_refgen" "behavioral_tmp".
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen (
//# {{control|Control Signals}}
input HLD_H_N ,
input IBUF_SEL ,
input OD_H ,
//# {{power|Power}}
input VREF_SEL ,
input VREG_EN ,
input VTRIP_SEL ,
inout REFLEAK_BIAS,
output VINREF ,
input VOHREF ,
output VOUTREF
);
// Voltage supply signals
wire VCCD ;
wire VCCHIB ;
wire VDDA ;
wire VDDIO ;
wire VDDIO_Q;
wire VSSD ;
wire VSSIO ;
wire VSSIO_Q;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void rd(T &x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); x *= f; } const int maxn = 1e5 + 5; int n, m; int ans[maxn]; struct node { int x, op, id; bool operator<(const node &b) const { return x == b.x ? id < b.id : x < b.x; } } p[maxn]; struct segment_tree { int op[maxn << 2], tag[maxn << 2]; void pushdown(int u) { if (tag[u]) { op[u << 1] = op[u << 1 | 1] = 1; tag[u << 1] = tag[u << 1 | 1] = tag[u]; tag[u] = 0; } if (op[u] == -1) { op[u << 1] *= -1; op[u << 1 | 1] *= -1; op[u] = 1; } } void build(int u, int l, int r) { op[u] = 1; if (l == r) return (void)(op[u] = p[l].op); int mid = l + r >> 1; build(u << 1, l, mid); build(u << 1 | 1, mid + 1, r); } void cover(int u, int l, int r, int ql, int qr, int v) { if (ql <= l && r <= qr) return (void)(op[u] = 1, tag[u] = v); int mid = l + r >> 1; pushdown(u); if (ql <= mid) cover(u << 1, l, mid, ql, qr, v); if (qr > mid) cover(u << 1 | 1, mid + 1, r, ql, qr, v); } void change(int u, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) return (void)(op[u] *= -1); int mid = l + r >> 1; pushdown(u); if (ql <= mid) change(u << 1, l, mid, ql, qr); if (qr > mid) change(u << 1 | 1, mid + 1, r, ql, qr); } void query(int u, int l, int r) { if (l == r) { int res = tag[u] ? tag[u] * op[u] : op[u]; ans[p[l].id] = res * p[l].x; return; } int mid = l + r >> 1; pushdown(u); query(u << 1, l, mid); query(u << 1 | 1, mid + 1, r); } } seg; int main() { rd(n), rd(m); for (int i = (1); i <= (n); ++i) { int x; rd(x); p[i] = (node){abs(x), x > 0 ? 1 : -1, i}; } sort(p + 1, p + n + 1); seg.build(1, 1, n); while (m--) { char s[5]; int x; scanf( %s , s); rd(x); if (s[0] == < ) { if (x < 0) { int pos = (lower_bound(p + 1, p + n + 1, (node){abs(x) + 1, 0, 0}) - p); if (pos <= n) seg.cover(1, 1, n, pos, n, 1); } else { int pos = (lower_bound(p + 1, p + n + 1, (node){abs(x), 0, 0}) - p); if (pos <= n) seg.cover(1, 1, n, pos, n, 1); if (pos > 1) seg.change(1, 1, n, 1, pos - 1); } } else { if (x > 0) { int pos = (lower_bound(p + 1, p + n + 1, (node){abs(x) + 1, 0, 0}) - p); if (pos <= n) seg.cover(1, 1, n, pos, n, -1); } else { int pos = (lower_bound(p + 1, p + n + 1, (node){abs(x), 0, 0}) - p); if (pos <= n) seg.cover(1, 1, n, pos, n, -1); if (pos > 1) seg.change(1, 1, n, 1, pos - 1); } } } seg.query(1, 1, n); for (int i = (1); i <= (n); ++i) printf( %d , ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFSBP_PP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_PP_BLACKBOX_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR / DDR2 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR / DDR2 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR10.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr2_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 1: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 1: 0] mem_dm;
inout [ 15: 0] mem_dq;
inout [ 1: 0] mem_dqs;
inout [ 1: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_we_n;
output pnf;
output [ 3: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 1: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 1: 0] mem_dm;
wire [ 15: 0] mem_dq;
wire [ 1: 0] mem_dqs;
wire [ 1: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 3: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [ 31: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 3: 0] mem_local_size;
wire [ 31: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 3: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr2 ddr2_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[1 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[1 : 0]),
.mem_dqsn (mem_dqsn[1 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 1 bits from example driver output because of 2:1 data rate
assign mem_local_addr[8 : 0] = mem_local_col_addr[9 : 1];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr2_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 22]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[21 : 9]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[3 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bin2bcd9.v: 9-bit Binay to BCD Converter; Double Dabble / Shift&Add3 Algorithm //
// //
// Ameer M.S. Abdelhadi (; ), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module bin2bcd9 (
input [8 :0] bin, // binary
output reg [11:0] bcd // bcd {hundreds,tens,ones}
);
reg [19:0] z;
integer i;
always @(bin) begin
for(i = 0; i <= 19; i = i+1) z[i] = 0;
z[11:3] = bin;
for(i = 0; i <= 5; i = i+1) begin
if(z[12:9 ] > 4) z[12:9 ] = z[12:9 ] + 3;
if(z[16:13] > 4) z[16:13] = z[16:13] + 3;
z[19:1] = z[18:0];
end
bcd = {1'b0,z[19:9]};
end
endmodule
|
`define bsg_dff_reset_macro(bits) \
if (harden_p && width_p==bits) \
begin: macro \
bsg_rp_tsmc_40_dff_nreset_s1_b``bits dff(.clk_i \
,.data_i \
,.nreset_i(~reset_i) \
,.data_o); \
end
module bsg_dff_reset #(width_p=-1, harden_p=1)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
`bsg_dff_reset_macro(90)
else `bsg_dff_reset_macro(89)
else `bsg_dff_reset_macro(88)
else `bsg_dff_reset_macro(87)
else `bsg_dff_reset_macro(86)
else `bsg_dff_reset_macro(85)
else `bsg_dff_reset_macro(84)
else `bsg_dff_reset_macro(83)
else `bsg_dff_reset_macro(82)
else `bsg_dff_reset_macro(81)
else `bsg_dff_reset_macro(80)
else `bsg_dff_reset_macro(79)
else `bsg_dff_reset_macro(78)
else `bsg_dff_reset_macro(77)
else `bsg_dff_reset_macro(76)
else `bsg_dff_reset_macro(75)
else `bsg_dff_reset_macro(74)
else `bsg_dff_reset_macro(73)
else `bsg_dff_reset_macro(72)
else `bsg_dff_reset_macro(71)
else `bsg_dff_reset_macro(70)
else `bsg_dff_reset_macro(69)
else `bsg_dff_reset_macro(68)
else `bsg_dff_reset_macro(67)
else `bsg_dff_reset_macro(66)
else `bsg_dff_reset_macro(65)
else `bsg_dff_reset_macro(64)
else `bsg_dff_reset_macro(63)
else `bsg_dff_reset_macro(62)
else `bsg_dff_reset_macro(61)
else `bsg_dff_reset_macro(60)
else `bsg_dff_reset_macro(59)
else `bsg_dff_reset_macro(58)
else `bsg_dff_reset_macro(57)
else `bsg_dff_reset_macro(56)
else `bsg_dff_reset_macro(55)
else `bsg_dff_reset_macro(54)
else `bsg_dff_reset_macro(53)
else `bsg_dff_reset_macro(52)
else `bsg_dff_reset_macro(51)
else `bsg_dff_reset_macro(50)
else `bsg_dff_reset_macro(49)
else `bsg_dff_reset_macro(48)
else `bsg_dff_reset_macro(47)
else `bsg_dff_reset_macro(46)
else `bsg_dff_reset_macro(45)
else `bsg_dff_reset_macro(44)
else `bsg_dff_reset_macro(43)
else `bsg_dff_reset_macro(42)
else `bsg_dff_reset_macro(41)
else `bsg_dff_reset_macro(40)
else `bsg_dff_reset_macro(39)
else `bsg_dff_reset_macro(38)
else `bsg_dff_reset_macro(37)
else `bsg_dff_reset_macro(36)
else `bsg_dff_reset_macro(35)
else `bsg_dff_reset_macro(34)
else `bsg_dff_reset_macro(33)
else `bsg_dff_reset_macro(32)
else `bsg_dff_reset_macro(31)
else `bsg_dff_reset_macro(30)
else `bsg_dff_reset_macro(29)
else `bsg_dff_reset_macro(28)
else `bsg_dff_reset_macro(27)
else `bsg_dff_reset_macro(26)
else `bsg_dff_reset_macro(25)
else `bsg_dff_reset_macro(24)
else `bsg_dff_reset_macro(23)
else `bsg_dff_reset_macro(22)
else `bsg_dff_reset_macro(21)
else `bsg_dff_reset_macro(20)
else `bsg_dff_reset_macro(19)
else `bsg_dff_reset_macro(18)
else `bsg_dff_reset_macro(17)
else `bsg_dff_reset_macro(16)
else `bsg_dff_reset_macro(15)
else `bsg_dff_reset_macro(14)
else `bsg_dff_reset_macro(13)
else `bsg_dff_reset_macro(12)
else `bsg_dff_reset_macro(11)
else `bsg_dff_reset_macro(10)
else `bsg_dff_reset_macro(9)
else `bsg_dff_reset_macro(8)
else `bsg_dff_reset_macro(7)
else `bsg_dff_reset_macro(6)
else `bsg_dff_reset_macro(5)
else `bsg_dff_reset_macro(4)
else `bsg_dff_reset_macro(3)
else
begin: notmacro_dff_reset
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
begin
if (reset_i)
data_r <= width_p ' (0);
else
data_r <= data_i;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_reset)
|
#include <bits/stdc++.h> struct IO { static const int L = 1000000; char a[L], b[L], *s, *t, *p, c; IO() : p(b) {} ~IO() { fwrite(b, 1, p - b, stdout); } char gc() { if (s == t) t = (s = a) + fread(a, 1, L, stdin); return *s++; } void gs(char* st) { for (c = gc(); !isgraph(c); c = gc()) ; *st++ = c; for (c = gc(); isgraph(c); c = gc()) *st++ = c; *st++ = 0; } template <class T> operator T() { static T x; static bool neg; for (c = gc(); c != - && !isdigit(c); c = gc()) ; if ((neg = c == - )) c = gc(); x = c - 0 ; for (c = gc(); isdigit(c); c = gc()) x = x * 10 + (c - 0 ); return neg ? -x : x; } void pc(const char ch) { if (p == b + L) fwrite(p = b, 1, L, stdout); *p++ = ch; } template <class T> void print(T x, const char end = n ) { static char cs[30], *q; static T y; if (x == 0) pc( 0 ); else { if (x < 0) pc( - ), x = -x; for (q = cs; x; x = y) y = x / 10, *q++ = x - y * 10 + 0 ; while (q != cs) pc(*--q); } if (end) pc(end); } void ps(const char* st, const char end = n ) { while (*st) pc(*st++); if (end) pc(end); } } io; int main() { static int i, n; static char a[200], r[3]; io.gs(a + 1); n = strlen(a + 1); for ((i) = (2); (i) < (n); ++(i)) { r[0] = a[i - 1]; r[1] = a[i]; r[2] = a[i + 1]; std::sort(r, r + 3); if (r[0] == A && r[1] == B && r[2] == C ) { io.ps( Yes ); return 0; } } io.ps( No ); return 0; }
|
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