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#include <bits/stdc++.h> int main() { int n, flag = 0; while (scanf( %d , &n) != EOF) { int a[n]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] == 1) { flag = 1; } } if (flag == 1) printf( -1 n ); else printf( 1 n ); } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_demux
*/
module test_axis_demux_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
reg enable = 0;
reg drop = 0;
reg [$clog2(M_COUNT)-1:0] select = 0;
// Outputs
wire s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready,
enable,
drop,
select
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_demux_4.lxt");
$dumpvars(0, test_axis_demux_4);
end
axis_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI outputs
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.enable(enable),
.drop(drop),
.select(select)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 50; const int magic = 2500; struct Node { int from, to, delta, add; Node(int from, int to, int delta, int add) : from(from), to(to), delta(delta), add(add) {} }; int n, a[maxn], c[maxn], q[maxn], id[maxn], b[maxn], ans[maxn], Q; vector<Node> All; void BuildInterval() { for (auto&& x : All) for (int i = x.from; i <= x.to; ++i) b[id[i]] -= x.delta, ans[id[i]] += x.add; for (int i = 1; i <= Q; ++i) id[i] = i; sort(id + 1, id + Q + 1, [&](const int& x, const int& y) { return b[x] < b[y]; }); All.clear(); All.push_back(Node(1, Q, 0, 0)); } int main(int argc, char* argv[]) { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d%d , c + i, q + i), id[i] = i; sort(id + 1, id + n + 1, [&](const int& x, const int& y) { return q[x] > q[y] || (q[x] == q[y] && c[x] < c[y]); }); for (int i = 1; i <= n; ++i) a[i] = c[id[i]]; scanf( %d , &Q); for (int i = 1; i <= Q; ++i) scanf( %d , b + i); BuildInterval(); for (int i = 1; i <= n; ++i) { for (int j = 0, limit = All.size(); j < limit; ++j) { if (All[j].from > All[j].to) continue; if (b[id[All[j].from]] - All[j].delta >= a[i]) All[j].delta += a[i], ++All[j].add; else if (b[id[All[j].to]] - All[j].delta >= a[i]) { int l = All[j].from + 1, r = All[j].to; while (l < r) { int mid = l + r >> 1; if (b[id[mid]] - All[j].delta >= a[i]) r = mid; else l = mid + 1; } All.push_back(Node(l, All[j].to, All[j].delta + a[i], All[j].add + 1)); All[j].to = l - 1; } } if (All.size() > magic || i == n) BuildInterval(); } for (int i = 1; i <= Q; ++i) printf( %d , ans[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int maxn = 2e5 + 10; int N, K; int L[105], R[105]; struct min_segtree { int tree[maxn * 3]; void init() { for (int i = 0; i <= 2 * 2 * N + 2048; ++i) tree[i] = INF; } void update(int l, int r, int pos, int id, int val) { if (l > r || pos < l || pos > r) return; if (l == pos && pos == r) { tree[id] = val; return; } int mid = (l + r) >> 1; if (pos <= mid) update(l, mid, pos, id << 1, val); else update(mid + 1, r, pos, id << 1 | 1, val); tree[id] = min(tree[id << 1], tree[id << 1 | 1]); } int query(int l, int r, int x, int y, int id) { if (l > r || x > y || r < x || l > y) return INF; if (l <= x && y <= r) return tree[id]; int mid = (x + y) >> 1; if (r <= mid) return query(l, r, x, mid, id << 1); if (l > mid) return query(l, r, mid + 1, y, id << 1 | 1); return min(query(l, r, x, mid, id << 1), query(l, r, mid + 1, y, id << 1 | 1)); } } DP[105]; int main() { scanf( %d %d , &N, &K); int i, j, lim = 2 * N; for (i = 1; i <= K; ++i) scanf( %d %d , &L[i], &R[i]); for (i = 0; i <= K; ++i) { DP[i].init(); } DP[0].update(0, lim, 0, 1, 0); for (i = 1; i <= K; ++i) { for (j = 0; j <= lim && j <= R[i]; ++j) { int zero = (j - R[i] + R[i - 1] >= 0) ? DP[i - 1].query(j - R[i] + R[i - 1], j - R[i] + R[i - 1], 0, lim, 1) : INF; int one = 1 + DP[i - 1].query(max(0, R[i - 1] - j), min(lim, R[i - 1] - j + R[i] - L[i]), 0, lim, 1); int two = 2 + DP[i - 1].query(max(0, j - R[i] + R[i - 1]), min(lim, j - R[i] + R[i - 1] + R[i] - L[i]), 0, lim, 1); DP[i].update(0, lim, j, 1, min(zero, min(one, two))); } } if (R[K] - N < 0 || DP[K].query(R[K] - N, R[K] - N, 0, lim, 1) >= INF) { printf( Hungry n ); } else { printf( Full n%d n , DP[K].query(R[K] - N, R[K] - N, 0, lim, 1)); } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long l, i = 0, n, d, t; cin >> d >> n; if (d != 1 && n == 0) { cout << No solution n ; return 0; } cout << n; for (t = 1; t <= d - 1; t++) cout << 0; cout << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] in = crc[7:0];
/*AUTOWIRE*/
wire out0;
wire out1;
wire out2;
wire out3;
wire out4;
wire out5;
wire out6;
wire out7;
/*SelFlop AUTO_TEMPLATE(.n(@),
.out(out@)); */
SelFlop selflop0(/*AUTOINST*/
// Outputs
.out (out0), // Templated
// Inputs
.clk (clk),
.in (in[7:0]),
.n (0)); // Templated
SelFlop selflop1(/*AUTOINST*/
// Outputs
.out (out1), // Templated
// Inputs
.clk (clk),
.in (in[7:0]),
.n (1)); // Templated
SelFlop selflop2(/*AUTOINST*/
// Outputs
.out (out2), // Templated
// Inputs
.clk (clk),
.in (in[7:0]),
.n (2)); // Templated
SelFlop selflop3(/*AUTOINST*/
// Outputs
.out (out3), // Templated
// Inputs
.clk (clk),
.in (in[7:0]),
.n (3)); // Templated
// Aggregate outputs into a single result vector
wire outo = out0|out1|out2|out3;
wire outa = out0&out1&out2&out3;
wire outx = out0^out1^out2^out3;
wire [63:0] result = {61'h0, outo, outa, outx};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h118c5809c7856d78
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module SelFlop(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, n
);
input clk;
input [7:0] in;
input [2:0] n;
output reg out;
// verilator no_inline_module
always @(posedge clk) begin
out <= in[n];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, v[5000], d[5000], p[5000]; bool used[5000]; int main() { cin >> n; for (long long i = 0; i < n; i++) { used[i] = true; cin >> v[i] >> d[i] >> p[i]; } vector<long long> ans; for (long long i = 0; i < n; i++) { long long t = 0; while ((p[t] >= 0 || !used[t]) && t < n) t++; if (t == n) { t = 0; while (!used[t]) t++; used[t] = false; if (t == n) break; ans.push_back(t + 1); long long k = 0; for (long long j = t + 1; j < n; j++) if (used[j] && k <= v[t]) { p[j] -= (v[t] - k); k++; } continue; } used[t] = false; for (long long j = t + 1; j < n; j++) p[j] -= d[t]; } cout << ans.size() << endl; for (long long i = 0; i < ans.size(); i++) if (p[ans[i] - 1] >= 0) cout << ans[i] << ; return 0; }
|
//Frequency of
//Frequency of 50Hz w/ 50MHz clock
//so 50000000/50=
//also Log2()=~20
//For accuracy lets reset when reaches ?
//
//Now in terms of Pulse width generally 1ms to 2ms
//this results in 50,000 to 100,000 CMPR value
//MIN: 50M * 1.0m = 50,000 = 50,000,000 * .000000001
//CENTER: 50M * 1.5m = 75,000
//MAX: 50M * 2.0m = 100,000
//
//lets try an 8 bit resolution allowing 256 steps
//First scale 0-255 to 50,000-100,000 so 50,000/255=~196
//we could also try a simpler division since 1ms/256 = 3.9us
//we could do (50Mz*1.0ms)/256 which will result in 195
//Offset (CENTER-((Steps/2)*2^Resolution))/2^resolution =~offset
//offset 165
//THIS MODULE ASSUMES SERVO RANGE IS FROM 1ms to 2ms
module Servo #(
parameter CLK_FREQUENCY = 50000000,//we want a 50Mhz clock so 10ns this makes
parameter VALUE_SCALING = 256,
parameter CTR_LEN = 21,//basically we can adjust the speed by mult CLKFREQ by SPEED
parameter SPEED_DATA_LEN = 5,//this will give us a value of 30 and log2 will give 5
parameter POSITION_DATA_LEN = 8,
parameter ADDR_LEN = 8,
parameter MAX_RAM_POS = 256,
parameter DATA_LEN = 13
)(
input clk,
input rst,
input [DATA_LEN-1:0] data,
output reg [ADDR_LEN-1:0] address,
output reg servo_q
);
wire[CTR_LEN-1:0] freq;
wire[SPEED_DATA_LEN-1:0] speed;
assign speed = data[POSITION_DATA_LEN+:SPEED_DATA_LEN-1];//LOOK AT VALUES TO THE LEFT OR MSB
assign freq = CLK_FREQUENCY*(speed/1000.0);//VERY COSTLY BUT MAKES LIFE EASY(MANY CIRCUITS ARE MADE FOR THIS DECLARATION)
//SECTION 1 DEAL WITH CHANGING ADDRESS
reg[CTR_LEN-1:0] ctr;
always@(posedge clk)begin
if(rst)begin
address<= '0;
ctr <= '0;
end else begin
ctr = ctr + 1'b1;
if(ctr>=freq )begin//THIS IS WHAT SPEED REALLY MEANS
if(address!=MAX_RAM_POS-1)begin
address <= address+1'b1;
end
ctr = '0;
end
end
end
//SECTION 2 DEAL WITH SERVO
wire[POSITION_DATA_LEN-1:0] pos;
wire[CTR_LEN-1-8:0] pulseCount ;//we will shift by 8 by selecting top 12 bit
assign pos = data[0+:POSITION_DATA_LEN-1];
//Doing this would be the same as a tick the pulseCount increments by 1 every certain amount of clock cycles
assign pulseCount = ctr[8+:CTR_LEN-1];//+ indicate increasing from starting point, - decreasing
always @(posedge clk) begin
servo_q = pulseCount < (pos + 9'd165) ;
//servo_q = pulseCount < {4'b0001,pos};
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1100; struct VIS { int c, p; int id; bool operator<(const VIS& t) const { if (p == t.p) return c < t.c; return p > t.p; } } A[MAXN]; struct TAB { int c; int id; bool operator<(const int t) const { return c < t; } bool operator<(const TAB& t) const { return c < t.c; } } Tb[MAXN]; bool vis[MAXN]; struct PAIR { int v; int t; bool operator<(const PAIR& t) const { return v < t.v; } } pai[MAXN]; int len; int sum; int main() { int N, K; while (scanf( %d , &(N)) != EOF) { for (int i = (1); i < (N + 1); ++i) { scanf( %d%d , &A[i].c, &A[i].p); A[i].id = i; } sort(A + 1, A + N + 1); scanf( %d , &(K)); for (int i = (1); i < (K + 1); ++i) { scanf( %d , &(Tb[i].c)); Tb[i].id = i; } sort(Tb + 1, Tb + K + 1); len = 0; sum = 0; memset(vis, 0, sizeof(vis)); for (int i = (1); i < (N + 1); ++i) { int p = lower_bound(Tb + 1, Tb + K + 1, A[i].c) - Tb; while (p <= K && vis[p]) ++p; if (p > K) continue; vis[p] = 1; sum += A[i].p; pai[len].v = A[i].id; pai[len].t = Tb[p].id; ++len; } sort(pai, pai + len); printf( %d %d n , len, sum); for (int k = (0); k < (len); ++k) { printf( %d %d n , pai[k].v, pai[k].t); } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/04 10:27:15
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Left | Right
// LDX-227 <- pwm_l1 | pwm_r1 -> LDX-227
// LDX-218 <- pwm_l2 | pwm_r2 -> LDX-218
// LDX-218 <- pwm_l3 | pwm_r3 -> LDX-218
module Top( clk,rst_n,
sw,btn,DIPsw,LED,
trig,echo,
RS232_rx,RS232_tx,
SCL,SDA,
dig,seg,
out_pwm_l1,out_pwm_l2,out_pwm_l3,out_pwm_r1,out_pwm_r2,out_pwm_r3
);
//Defcult system clock and reset signal
input clk,rst_n;
//Button and switch signal
input sw;
input [4:0] btn;
input [3:0] DIPsw;
//Signal for UART Bluetooth module
input RS232_rx;
output RS232_tx;
//Signal for UltraSonic module
input echo;
output trig;
//Signal for I2C module 24C02
inout SCL, SDA;
output [3:0] dig;
output [7:0] seg;
output wire out_pwm_l1,out_pwm_l2,out_pwm_l3,out_pwm_r1,out_pwm_r2,out_pwm_r3;
output wire [7:0] LED;
wire isRunningFlag,resetFlag;
//wire setOffsetFlag;
wire [3:0] hwCtrlActionGroup;
wire interrupt;
wire [7:0] bt_data;
wire [23:0] distance;
wire SCL_en,SCL_o,SDA_en,SDA_o;
reg SCL_i,SDA_i;
//Bluetooth Module
UART_top ins_Bluetooth(
.clk(clk),
.rst_n(rst_n),
.tx_int(interrupt),
.data_in(data_reg),
.RS232_rx(RS232_rx),
.RS232_tx(RS232_tx),
.data_out(bt_data)
);
//I2C module 24C02
assign SCL = (SCL_en)?1'bz:SCL_o;//enable is low meant to write
assign SDA = (SDA_en)?1'bz:SDA_o;
always @ (SCL_en)//read the inout port when enable signal is high
if(SCL_en) SCL_i = SCL;
always @ (SDA_en)
if(SDA_en) SDA_i = SDA;
EEPROM_Top ins_24C02(
.clk(clk),
.rst_n(rst_n),
.rw_en(),
.data_in(),
.data_out(),
.SCL_en(SCL_en),
.SCL_o(SCL_o),
.SCL_i(SCL_i),
.SDA_en(SDA_en),
.SDA_o(SDA_o),
.SDA_i(SDA_i)
);
write_en, flag_write_done,flag_error,flag_read_done,
assign LED[0] = isRunningFlag;
assign LED[1] = resetFlag;
assign LED[7:4] = hwCtrlActionGroup;
pwm_ctrl ins_pwm_ctrl(
.clk(clk),
.rst_n(rst_n),
.ActionGroupCtrl(hwCtrlActionGroup),
.distance(distance),
.resetFlag(resetFlag),
.isRunningFlag(isRunningFlag),
//.runLoopFlag(runLoopFlag),
//.run1StepFlag(run1StepFlag),
//.setOffsetFlag(1'b0),
.out_pwm_l1(out_pwm_l1),
.out_pwm_l2(out_pwm_l2),
.out_pwm_l3(out_pwm_l3),
.out_pwm_r1(out_pwm_r1),
.out_pwm_r2(out_pwm_r2),
.out_pwm_r3(out_pwm_r3),
.clk_int(interrupt));
data_in ins_dataIn(
.clk(clk),
.rst_n(rst_n),
.sw(sw),
.btn(btn),
.DIPsw(DIPsw),
.resetFlag(resetFlag),
.isRunningFlag(isRunningFlag),
//.runLoopFlag(runLoopFlag),
//.run1StepFlag(run1StepFlag),
.agCtrlFlag(hwCtrlActionGroup)
//.setOffsetFlag(setOffsetFlag)
);
segDisplayDriver ins_segDisplay(
.clk(clk),
.data(distance[23:8]),
.out_dig(dig),
.out_seg(seg));
Sonic ins_ultraSonic(
.clk(clk),
.rst_n(rst_n),
.trig(trig),
.echo(echo),
.distance(distance));
// reg en_forward; //Ç°½øʹÄÜ
// reg en_back; //ºóÍËʹÄÜ
// reg en_keepdistance; //±£³Ö¾àÀëʹÄÜ
// reg en_welcome; //»¶ÓʹÄÜ
// reg en_kick; //ÌßÍÈÔ˶¯
// reg en_slide; //»¬²½Ô˶¯
reg [7:0] data_reg;
reg digitFlag=0; //λÊýÇл»±êÖ¾
//reg out_of_distance=0; //¾àÀë¹ýÔ¶±êÖ¾
//reg in_distance=0; //¾àÀë¹ý½ü±êÖ¾
always@(posedge interrupt)
if(digitFlag==0) begin
digitFlag<=1;
data_reg <= {4'b0011,distance[15:12]};
end
else begin
digitFlag<=0;
data_reg <= {4'b0011,distance[19:16]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> G[14]; int dp[1 << 14], dp2[14][14][1 << 14]; vector<int> re[1 << 14]; pair<int, int> last_pair[1 << 14]; int pre[1 << 14]; int last[14][14][1 << 14]; bool v[1 << 14]; int main() { int n, m, x, y; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &y); G[x - 1].push_back(y - 1); G[y - 1].push_back(x - 1); } for (int i = 0; i < n; i++) v[1 << i] = 1; memset(dp, 0x3f, sizeof(dp)); dp[1] = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < (1 << n); k++) { dp2[i][j][k] = 0x3f3f3f3f; } for (int i = 0; i < n; i++) for (auto x : G[i]) { dp2[i][x][0] = 1; last[i][x][0] = i; } for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < n; j++) { if ((i >> j) & 1) continue; for (int k = 0; k < n; k++) { if ((i >> k) & 1) continue; if (j == k || dp2[j][k][i] == 0x3f3f3f3f) continue; for (auto z : G[k]) { if ((i >> z) & 1) continue; if (z == last[j][k][i]) continue; int tmp = i ^ (1 << k); if (dp2[j][z][tmp] == 0x3f3f3f3f) { dp2[j][z][tmp] = 1; last[j][z][tmp] = k; } } } } } for (int i = 0; i < n; i++) dp[1 << i] = 0; for (int i = 0; i < (1 << n); i++) for (int j = 0; j < n; j++) { if ((i >> j) & 1) re[i].push_back(j); } for (int i = 0; i < (1 << n); i++) { for (int j = i; j; j = (j - 1) & i) { int tmp = i ^ j; int cnt = __builtin_popcount(j) + 1; if (dp[i] < dp[tmp] + cnt) continue; for (auto x : re[tmp]) for (auto y : re[tmp]) { if (dp2[x][y][j] == 1) { dp[i] = min(dp[i], dp[tmp] + cnt); last_pair[i] = make_pair(x, y); pre[i] = tmp; } } } } if (dp[(1 << n) - 1] == 0x3f3f3f3f) { printf( -1 n ); } else { printf( %d n , dp[(1 << n) - 1]); int now = (1 << n) - 1; while (!v[now]) { int x = last_pair[now].first, y = last_pair[now].second; int tmp = now ^ pre[now]; while (tmp) { int tmp1 = last[x][y][tmp]; printf( %d %d n , y + 1, tmp1 + 1); y = tmp1; tmp ^= (1 << tmp1); } printf( %d %d n , x + 1, y + 1); now = pre[now]; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c; cin >> a >> b >> c; long long Min = min(a, b); Min = min(Min, c); long long day = 0; while (a + b + c >= 7 && a >= 3 && b >= 2 && c >= 2) { a -= 3; b -= 2; c -= 2; day += 7; } long long ans = 0; long long _a = a, _b = b, _c = c; for (long long i = 1; i <= 7; i++) { long long tmp = 0; a = _a; b = _b; c = _c; for (long long j = i; j <= i + 7; j++) { long long _j = j % 7; if (_j == 1 || _j == 4 || _j == 0) { if (!a) { ans = max(ans, tmp); break; } a--; tmp++; } if (_j == 2 || _j == 6) { if (!b) { ans = max(ans, tmp); break; } b--; tmp++; } if (_j == 3 || _j == 5) { if (!c) { ans = max(ans, tmp); break; } c--; tmp++; } } ans = max(ans, tmp); } cout << day + ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_4_V
`define SKY130_FD_SC_HD__DLCLKP_4_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_4 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// This test demonstrates how not only parameters but the type of a parent
// interface could propagate down to child modules, changing their data type
// determinations. Note presently unsupported in all commercial simulators.
interface ifc;
parameter MODE = 0;
generate
// Note block must be named per SystemVerilog 2005
if (MODE==1) begin : g
integer value;
end
else if (MODE==2) begin : g
real value;
end
endgenerate
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itop1a();
ifc #(1) itop1b();
ifc #(2) itop2a();
ifc #(2) itop2b();
wrapper c1 (.isuba(itop1a),
.isubb(itop1b),
.i_valuea(14.1),
.i_valueb(15.2));
wrapper c2 (.isuba(itop2a),
.isubb(itop2b),
.i_valuea(24.3),
.i_valueb(25.4));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (itop1a.g.value != 14) $stop;
if (itop1b.g.value != 15) $stop;
if (itop2a.g.value != 24) $stop;
if (itop2b.g.value != 25) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module wrapper
(
ifc isuba,
ifc isubb,
input real i_valuea,
input real i_valueb
);
lower subsuba (.isub(isuba), .i_value(i_valuea));
lower subsubb (.isub(isubb), .i_value(i_valueb));
endmodule
module lower
(
ifc isub,
input real i_value
);
always @* begin
`error Commercial sims choke on cross ref here
isub.g.value = i_value;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) f = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return x * f; } int n, m; int dp[45][1 << 7][1 << 7]; int cnt[1 << 7]; void init() { for (int i = 0; i < (1 << m); i++) { for (int x = i; x; x >>= 1) if ((x & 1)) cnt[i]++; cnt[i] = m - cnt[i]; } } bool ok(int j, int k, int l) { int state = k | (k << 1) | (k >> 1) | j | l; return (state & ((1 << m) - 1)) == ((1 << m) - 1); } int main() { n = read(), m = read(); if (n < m) swap(n, m); init(); memset(dp, -0x3f3f3f3f, sizeof dp); for (int i = 0; i < (1 << m); i++) dp[0][0][i] = 0; for (int i = 0; i < n; i++) for (int j = 0; j < (1 << m); j++) for (int k = 0; k < (1 << m); k++) if (dp[i][j][k] >= 0) for (int l = 0; l < (1 << m); l++) if (ok(j, k, l)) dp[i + 1][k][l] = max(dp[i + 1][k][l], dp[i][j][k] + cnt[k]); int ans = 0; for (int i = 0; i < (1 << m); i++) ans = max(ans, dp[n][i][0]); printf( %d n , ans); return 0; }
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e2 + 10; const int INF = 1 << 30; char str[MAXN][MAXN]; int Pow(int a, int b) { if (b == 0) return 1; int res = 1; while (b--) res *= a; return res; } int main() { int a, b, n; while (scanf( %d%d%d , &a, &b, &n) != EOF) { if (a == 0) { if (b == 0) printf( 1 n ); else printf( No solution n ); continue; } if (b % a) { printf( No solution n ); continue; } a = b / a; int res = -INF; if (a < 0) { a = -a; if (n % 2 == 0) { printf( No solution n ); continue; } for (int i = 0; i <= 1000; i++) { if (Pow(i, n) == a) { res = i; break; } if (Pow(i, n) > a) break; } res = -res; } else { for (int i = 0; i <= 1000; i++) { if (Pow(i, n) == a) { res = i; break; } if (Pow(i, n) > a) break; } } if (res == -INF) { printf( No solution n ); } else { printf( %d n , res); } } return 0; }
|
// megafunction wizard: %LPM_FIFO+%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_32x512a.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_32x512a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
output [9:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x512a_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; int main() { int k = 0; int a, b, c; string s1, s2, s3; cin >> s1 >> s2 >> s3; a = s1.size(); b = s2.size(); c = s3.size(); if ((a + b) != c) { cout << NO ; return 0; } s1 = s1 + s2; for (int i = 0; i < c; i++) { for (int j = 0; j < c; j++) { if (s1[i] == s3[j]) { k++; s3[j] = 0 ; break; } } } if (k == c) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, max = -1; cin >> n; long long int a[n], b[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = n - 1; i >= 0; i--) { if (max < a[i]) { max = a[i]; b[n - i] = 0; } else { b[n - i] = max + 1 - a[i]; } } for (int i = n; i > 0; i--) { cout << b[i] << ; } return 0; }
|
`timescale 1ns / 1ps
module lab6phase1I2C2015fall_tb;
reg Go, Reset, clock;
wire SCL, ClockLocked;
wire [2:0] State=uut.ControlUnit.State;
wire [2:0] NextState=uut.ControlUnit.NextState;
wire ControlClock=uut.ControlUnit.Clock;
wire ClockI2C=uut.ControlUnit.ClockI2C;
wire BaudEnable=uut.ControlUnit.BaudEnable;
wire StartStopAck=uut.ControlUnit.StartStopAck;
wire ShiftOrHold=uut.DataUnit.ShiftOrHold;
wire ShiftDataOut=uut.DataUnit.ShiftDataOut;
wire SDA;
lab6phase1I2C2015fall uut(1'b0,Go,Reset,ClockLocked,SCL,SDA);
assign uut.ClockOut=clock;
defparam uut.ControlUnit.Timer.Divider=2;
defparam uut.BaudRate=3;
defparam uut.ClockFrequency=12;
wire Timeout=uut.ControlUnit.Timeout;
wire [3:0] DataCounter = uut.ControlUnit.DataCounter;
wire [15:0] baud_count = uut.DataUnit.BaudUnit.baud_count;
initial begin Go = 0; Reset = 0; clock = 0; end
always #4 clock=~clock;
initial fork
#0 Reset=1; #12 Reset=0;
#0 Go=0; #21 Go=1; #61 Go=0; #470 Go=1; #479 Go=0;
#600 $stop;
join
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; const int MOD = 1e9 + 7; int a[MAXN]; class Matrix { public: void prinf() { for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { cout << a[i][j]; } cout << endl; } } long long a[2][2]; Matrix() { memset(a, 0, sizeof a); } void init() { for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) a[i][j] = (i == j); } Matrix operator+(const Matrix &B) const { Matrix C; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) C.a[i][j] = (a[i][j] + B.a[i][j]) % MOD; return C; } Matrix operator*(const Matrix &B) const { Matrix C; for (int i = 0; i < 2; i++) for (int k = 0; k < 2; k++) for (int j = 0; j < 2; j++) C.a[i][j] = (C.a[i][j] + 1LL * a[i][k] * B.a[k][j]) % MOD; return C; } Matrix operator^(const int &t) const { Matrix A = (*this), res; res.init(); int p = t; while (p) { if (p & 1) res = res * A; A = A * A; p >>= 1; } return res; } }; Matrix sum[MAXN << 2], add[MAXN << 2], f; void pushdown(int rt) { sum[rt << 1] = sum[rt << 1] * add[rt]; sum[rt << 1 | 1] = sum[rt << 1 | 1] * add[rt]; add[rt << 1] = add[rt << 1] * add[rt]; add[rt << 1 | 1] = add[rt << 1 | 1] * add[rt]; add[rt].init(); } void pushup(int rt) { sum[rt] = sum[rt << 1] + sum[rt << 1 | 1]; } void build(int l, int r, int rt) { sum[rt].init(); add[rt].init(); if (l == r) { sum[rt] = f ^ (a[l] - 1); return; } int m = (l + r) >> 1; build(l, m, rt << 1); build(m + 1, r, rt << 1 | 1); pushup(rt); } void update(int L, int R, Matrix v, int l, int r, int rt) { if (L <= l && R >= r) { sum[rt] = sum[rt] * v; add[rt] = add[rt] * v; return; } pushdown(rt); int m = (l + r) >> 1; if (L <= m) update(L, R, v, l, m, rt << 1); if (R > m) update(L, R, v, m + 1, r, rt << 1 | 1); pushup(rt); } long long query(int L, int R, int l, int r, int rt) { if (L <= l && R >= r) { return sum[rt].a[0][0]; } pushdown(rt); int m = (l + r) >> 1; int cnt = 0; if (L <= m) cnt = (cnt + query(L, R, l, m, rt << 1)) % MOD; if (R > m) cnt = (cnt + query(L, R, m + 1, r, rt << 1 | 1)) % MOD; return cnt; } int main() { int m, n; f.a[0][0] = 1; f.a[0][1] = 1; f.a[1][0] = 1; f.a[1][1] = 0; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); build(1, n, 1); int a1, b, c; for (int i = 0; i < m; i++) { scanf( %d %d %d , &a1, &b, &c); if (a1 == 1) { int s; scanf( %d , &s); update(b, c, f ^ s, 1, n, 1); } else { cout << query(b, c, 1, n, 1) % MOD << endl; } } }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 7981 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w7936,
w7967,
w16,
w7983,
w2,
w7981;
assign w1 = i_data0;
assign w16 = w1 << 4;
assign w2 = w1 << 1;
assign w31 = w32 - w1;
assign w32 = w1 << 5;
assign w7936 = w31 << 8;
assign w7967 = w31 + w7936;
assign w7981 = w7983 - w2;
assign w7983 = w7967 + w16;
assign o_data0 = w7981;
//multiplier_block area estimate = 7298.12158343824;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// --------------------------------------------------------------------
// ng_TPG.v - Time Pulse Generator
//
// AGC instructions are implemented in groups of 12 steps, called timing pulses. The timing
// pulses, named TP1 through TP12, are produced by the Time Pulse Generator (TPG). Each set
// of 12 timing pulses is called an instruction subsequence. Simple instructions, such as TC,
// execute in a single subsequence of 12 pulses. More complex instructions require several
// subsequences.
// --------------------------------------------------------------------
module ng_TPG(
input CLK1, // Clock Pulse 1
input CLK0, // Clock Pulse 0
input NPURST, // Master reset, negative logic
input F17X, // Clock divided by 17
input FCLK, // Fast Clock enable
input F13X, // Clock divided by 13
input INST, // Instruction increment
input NRUN, // Run mode, negative logic
input SNI, // SELECT NEXT INST 1=select next instruction (SNI register)
input OUT8, // Output 8 standby enable
input NSA, // Standby allowed, negative logic
input NSTEP, // Next Step, negative logic
output reg [3:0] TPG, // Time Pulse regsiter output
output STBY // Standby alert signal
);
// --------------------------------------------------------------------
// Time Pulse Gate Signals
// --------------------------------------------------------------------
wire TPG0 = !(!NPURST | !(F17X | !FCLK)); // Time Pulse Gate 0
wire TPG1 = !(!F13X & FCLK); // Time Pulse Gate 1
wire TPG2 = !(!(INST & !SNI) & NRUN); // Time Pulse Gate 2
wire TPG3 = !(!SNI | !OUT8 | NSA); // Time Pulse Gate 3
wire TPG4 = NSTEP; // Time Pulse Gate 4
wire TPG5 = !(NSTEP & NRUN); // Time Pulse Gate 5
// --------------------------------------------------------------------
// Counter Control Signals
// --------------------------------------------------------------------
wire CNT_D1 = !(!NTP12 & TPG3);
wire CNT_PE = !(!(!TPG3|NTP12) | !(NTP12|!TPG2|TPG3) | !(NWAIT|!TPG5));
wire CNT_CET = !(!(NWAIT|TPG5) | (!(NSTBY|TPG0) | !(NPWRON|TPG1) | !(NSRLSE|TPG4)));
// --------------------------------------------------------------------
// Counter Logic:
// --------------------------------------------------------------------
always @(posedge CLK1 or negedge NPURST)
if(!NPURST) TPG <= 4'h0; // Clear register on reset
else if(!CNT_PE) TPG <= {2'b00, CNT_D1, 1'b0}; // Request load D1
else if(CNT_CET) TPG <= TPG + 4'd1; // Increment counter
// --------------------------------------------------------------------
// Time Pulse values:
//
// TPG
// ---
// 0 Standby
// 1 Power on
// 2 - 13 Instruction sequence
// 14 Sequence release
// 15 Wait
// --------------------------------------------------------------------
wire NSTBY = !(TPG == 0);
wire NPWRON = !(TPG == 1);
wire NTP12 = !(TPG == 13);
wire NSRLSE = !(TPG == 14);
wire NWAIT = !(TPG == 15);
assign STBY = NSTBY;
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_BEHAVIORAL_PP_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_4_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_4_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_4_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_4_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e1 + 5; map<int, int> mp; long long n, arr[MAXN], brr[MAXN], crr[MAXN]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; brr[i] = arr[i]; } sort(arr, arr + n); for (int i = 0; i < n; i++) { crr[i] = arr[(i + 1) % n]; } for (int i = 0; i < n; i++) { mp[arr[i]] = crr[i]; } for (int i = 0; i < n; i++) { cout << mp[brr[i]] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int v[200005]; bool inQ[200005]; vector<pair<int, int> > foo; int main() { int n, k, q, p, m, i, j; bool ok; pair<int, int> x; cin >> n >> k >> m; for (i = 1; i <= n; ++i) cin >> v[i]; priority_queue<pair<int, int> > pq; for (j = 0; j < m; ++j) { cin >> q >> p; if (q == 1) { if (!inQ[p]) { pq.push({v[p], p}); inQ[p] = 1; } } else { if (!inQ[p]) ok = 0; else { ok = i = 0; while (!pq.empty() && i < k) { x = pq.top(); pq.pop(); foo.push_back(x); if (x.second == p) { ok = true; break; } ++i; } while (!foo.empty()) { pq.push(foo.back()); foo.pop_back(); } } if (ok == true) cout << YES n ; else cout << NO n ; } } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:49:15 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output UART0_TX;
input UART0_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100 + 7; const int M = 59; const int mid = M / 2; const int mod = 1e9 + 9; const int inf = 1e6 + 3; const long long linf = 1ll * inf * inf; const double pi = acos(-1); const double eps = 1e-7; const double ep = 1e-5; const int maxn = 1e5 + 7; const double PI = acos(-1); int C, W, H; int dp[2][107]; struct matrix { long long a[N][N]; int n, m; matrix(int _n, int _m) { n = _n; m = _m; memset(a, 0, sizeof(a)); } matrix(int _n, int _m, bool itype) { n = _n; m = _m; if (itype) { for (int i = (1); i < (n + 1); i++) a[i][i] = 1; } } matrix operator*(matrix u) { matrix c(n, u.m); for (int i = 1; i <= c.n; i++) { for (int j = 1; j <= c.m; j++) { long long tmp = 0; for (int t = 1; t <= m; t++) tmp = (tmp + (long long)a[i][t] * u.a[t][j]) % inf; c.a[i][j] = tmp; } } return c; } void print() { for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) printf( %lld , a[i][j]); printf( n ); } } }; void solve() { cin >> C >> W >> H; matrix b(W + 1, W + 1); for (int i = (2); i < (W + 2); i++) { b.a[i - 1][i] = H; } for (int i = (1); i < (W + 2); i++) b.a[i][1] = 1; matrix I(W + 1, W + 1, true); while (C > 0) { if (C & 1) { I = I * b; } b = b * b; C >>= 1; } matrix res(1, W + 1); res.a[1][1] = 1; res = res * I; int ans = 0; for (int i = (1); i < (res.m + 1); i++) ans = (ans + res.a[1][i]) % inf; cout << ans; } int main() { int T = 1; for (int i = (1); i < (T + 1); i++) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int arr[200005]; map<int, int> mp; int main() { int n, k; cin >> n >> k; vector<int> v; for (int i = 0; i < n; i++) { int a; cin >> a; v.push_back(a); } sort(v.begin(), v.end()); int ans = 1e9; for (int i = 0; i < n; i++) { int zz = v[i]; int cnt = 0; mp[zz]++; if (mp[zz] == k) ans = min(ans, arr[zz]); while (zz > 0) { zz /= 2; mp[zz]++; cnt++; arr[zz] += cnt; if (mp[zz] == k) { ans = min(ans, arr[zz]); } } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; long long ans; int n, m, k; long long C[1100][1100]; long long s1[1100][1100]; long long p[1100][1100]; long long f[1100100]; long long Pow(long long i, int x) { long long tmp = 1; while (x) { if (x & 1) tmp = tmp * i % (1000000007LL); i = i * i % (1000000007LL); x >>= 1; } return tmp; } void work() { memset(s1, 0, sizeof(s1)); int i = n; for (int j = 1; j <= i; j++) { s1[i][j] = Pow(j, i); for (int k = 1; k < j; k++) { s1[i][j] += (1000000007LL) - C[j][k] * s1[i][k] % (1000000007LL); s1[i][j] %= (1000000007LL); } } } void pre() { memset(C, 0, sizeof(C)); for (int i = 0; i <= 1000; i++) C[i][0] = 1; for (int i = 1; i <= 1000; i++) for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % (1000000007LL); f[0] = 1; for (int i = 1; i <= 1000000; i++) f[i] = f[i - 1] * i % (1000000007LL); for (int i = 1; i <= 1000; i++) p[i][0] = 1; for (int i = 1; i <= 1000; i++) for (int j = 1; j <= 1000; j++) { p[i][j] = (p[i][j - 1] * i) % (1000000007LL); } } long long Inv(long long x) { return Pow(x, (1000000007LL) - 2LL); } long long C_(int x, int y) { return f[x] * Inv(f[y]) % (1000000007LL) * Inv(f[x - y]) % (1000000007LL); } int main() { pre(); while (~scanf( %d%d%d , &n, &m, &k)) { ans = 0; work(); long long tt; if (m == 1) { ans = Pow(k, n); } else if (m > 2) { for (int i = 1; i <= min(n, k); i++) for (int j = 0; j + i <= min(n, k); j++) { if ((i | j) && i + 2 * j <= k) { tt = C_(k, i) * C_(k - i, j) % (1000000007LL) * C_(k - i - j, j) % (1000000007LL); ans += ((s1[n][i + j] * s1[n][i + j]) % (1000000007LL) * Pow(i, (m - 2) * n) % (1000000007LL)) * tt % (1000000007LL); ans %= (1000000007LL); } } } else { for (int i = 1; i <= min(n, k); i++) { ans += C_(k, i) * s1[n][i] % (1000000007LL) * C_(k, i) % (1000000007LL) * s1[n][i] % (1000000007LL); ans %= (1000000007LL); } } printf( %I64d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; void quickly_quickly_kro() { long long n; cin >> n; vector<long long> v(n); for (long long i = 0; i < n; i++) cin >> v[i]; ; map<long long, long long> M, N, I; for (long long i = 0; i < n; i++) { if (v[i] != 0) M[v[i]]++; else I[i]++; } for (long long i = 1; i < n + 1; i++) { if (M[i] == 0) { N[i]++; } } for (auto k : I) { if ((N.find(k.first + 1) != N.end())) { auto it = N.find(k.first + 1); if (it != N.begin()) it--; else it++; v[k.first] = it->first; N.erase(it); } } for (long long i = 0; i < n; i++) { if (v[i] == 0) { auto it = N.begin(); pair<long long, long long> p = *it; v[i] = p.first; N.erase(it); } } for (long long i = 0; i < n; i++) cout << v[i] << ; } signed main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) { quickly_quickly_kro(); cout << n ; ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int arr[100][100]; int main() { int n, a, b; scanf( %d , &n); for (int i = 0; i < n * n; i++) { scanf( %d%d , &a, &b); if (!arr[a][b]) { printf( %d , i + 1); for (int y = 0; y <= n; y++) { arr[a][y] = 1; arr[y][b] = 1; } } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { char arr[100][100]; int m, n, k = 0; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> arr[i]; } if (m == 1 || n == 1) { cout << 0; return 0; } for (int i = 0; i < n - 1; i++) { for (int j = 0; j < m - 1; j++) { if ( f != arr[i][j] && f != arr[i + 1][j] && f != arr[i][j + 1] && f != arr[i + 1][j + 1]) continue; if ( a != arr[i][j] && a != arr[i + 1][j] && a != arr[i][j + 1] && a != arr[i + 1][j + 1]) continue; if ( c != arr[i][j] && c != arr[i + 1][j] && c != arr[i][j + 1] && c != arr[i + 1][j + 1]) continue; if ( e != arr[i][j] && e != arr[i + 1][j] && e != arr[i][j + 1] && e != arr[i + 1][j + 1]) continue; k++; } } cout << k; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; const int N = 300010; class cmp { public: bool operator()(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { if (a.first == b.first) return a.second > b.second; return a.first < b.first; } }; long long int a[N], b[N], fact[N]; long long int mod = 998244353; void cal() { fact[1] = 1; for (long long int i = 2; i < N; i++) { fact[i] = ((fact[i - 1] % mod) * (i % mod)) % mod; } } bool sort1(const pair<long long int, long long int> &x, const pair<long long int, long long int> &y) { if (x.first == y.first) return x.second < y.second; return x.first < y.first; } void solve() { long long int n; cin >> n; cal(); memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); long long int i, x, y, f = 0; vector<pair<long long int, long long int>> v; for (i = 0; i < n; i++) { cin >> x >> y; a[x]++; b[y]++; v.push_back({x, y}); if (a[x] == n || b[y] == n) f = 1; } if (f) { cout << 0 << endl; return; } long long int ans = fact[n]; long long int ans1 = 1; for (i = 1; i < N; i++) { if (a[i]) { long long int cnt = fact[a[i]]; ans1 = ((ans1 % mod) * (cnt % mod)) % mod; } } ans = (ans - ans1 + mod) % mod; long long int ans2 = 1; for (i = 1; i < N; i++) { if (b[i]) { long long int cnt = fact[b[i]]; ans2 = ((ans2 % mod) * (cnt % mod)) % mod; } } ans = (ans - ans2 + mod) % mod; sort(v.begin(), v.end(), sort1); long long int k = 0; for (i = 0; i < n - 1; i++) { if (v[i].second > v[i + 1].second) { k = 1; break; } } if (k == 0) { ans1 = 1; for (i = 0; i < n;) { long long int j = i; long long int cnt = 0; while (j < n && v[i].first == v[j].first && v[i].second == v[j].second) { j++; cnt++; } i = j; cnt = fact[cnt]; ans1 = ((ans1 % mod) * (cnt % mod)) % mod; } ans = (ans + ans1) % mod; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long Mod = 1e9 + 7; const long long INF = (long long)(1e18) + 5; const long long N = 2e5 + 5, M = 18; int n, m, p; int a[N]; tuple<long long, long long, long long> b[N]; long long suf_s[N], suf_c[N]; long long dp[N], prev_dp[N]; void solve(int i, int j, int l, int r) { if (j < i) return; int mid = i + j >> 1; long long best = INF, idx = -1; long long cnt = 0, sum = 0; if (mid < l) { sum += suf_s[mid] - suf_s[l]; cnt += suf_c[mid] - suf_c[l]; } for (int k = max(mid, l); k <= r; k++) { auto [t, c, s] = b[k]; sum += s; cnt += c; long long cur = sum + cnt * t + prev_dp[k + 1]; if (cur < best) best = cur, idx = k; } dp[mid] = best; solve(i, mid - 1, l, idx); solve(mid + 1, j, idx, r); } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m >> p; for (int i = 1; i < n; i++) cin >> a[i], a[i] += a[i - 1]; map<long long, long long> cnt, sum; long long ans2 = 0; for (int i = 0; i < m; i++) { int h, t; cin >> h >> t; h--; cnt[t - a[h]]++; sum[t - a[h]] += a[h] - t; } m = 0; for (auto [i, j] : cnt) b[m++] = {i, j, sum[i]}; for (int i = m; i >= 0; i--) { auto [t, c, s] = b[i]; suf_s[i] = s + suf_s[i + 1]; suf_c[i] = c + suf_c[i + 1]; } for (int i = 0; i < m; i++) dp[i] = INF; while (p--) { swap(dp, prev_dp); solve(0, m - 1, 0, m - 1); } cout << dp[0] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { const int maxn = 1005; char a[2 * maxn], b[maxn]; scanf( %s , a); scanf( %s , b); int lenA = strlen(a); int lenB = strlen(b); int cntA = 0, cntB = 0; int i; for (i = 0; i < lenA; i++) if (a[i] == 1 ) cntA++; for (i = 0; i < lenB; i++) if (b[i] == 1 ) cntB++; if (cntA % 2 == 0) { if (cntA < cntB) { puts( NO ); } else { puts( YES ); } } else { if (cntB - cntA > 1) { puts( NO ); } else { puts( YES ); } } }
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#include <bits/stdc++.h> using namespace std; int ans[11][11]; bool ok; string s; int sol; queue<int> dulj, broj; int pomocnopolje[11][11]; void bfs(int x, int y, int a, int b) { broj.push(a); dulj.push(1); int v[10] = {0}; while (!broj.empty()) { int duljina = dulj.front(); dulj.pop(); int br = broj.front(); broj.pop(); if (!v[(br + x) % 10]) { v[(br + x) % 10] = duljina; broj.push((br + x) % 10); dulj.push(duljina + 1); } if (!v[(br + y) % 10]) { v[(br + y) % 10] = duljina; broj.push((br + y) % 10); dulj.push(duljina + 1); } } pomocnopolje[a][b] = v[b] - 1; return; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> s; for (int i = 0; i < 10; i++) { for (int j = i; j < 10; j++) { ok = 1; sol = 0; for (int k = 0; k < 10; k++) { for (int l = 0; l < 10; l++) { bfs(i, j, k, l); } } for (int znj = 1; znj < s.size() and ok; znj++) { int a = s[znj - 1] - 0 , b = s[znj] - 0 ; if (pomocnopolje[a][b] >= 0) sol += pomocnopolje[a][b]; else ok = 0; } if (ok) { ans[i][j] = sol; ans[j][i] = sol; } else { ans[i][j] = -1; ans[j][i] = -1; } } } for (int i = 0; i < 10; i++) { for (int j = 0; j < 10; j++) { cout << ans[i][j] << ; } cout << endl; } return 0; }
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// file: clk_wiz_1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// _clk_txd___100.000______0.000______50.0______130.958_____98.575
// _clk_rxd___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_1,clk_wiz_v5_4_0_0,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_1
(
// Clock out ports
output clk_txd,
output clk_rxd,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input clk_in1
);
clk_wiz_1_clk_wiz inst
(
// Clock out ports
.clk_txd(clk_txd),
.clk_rxd(clk_rxd),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int j, k, n; int main() { long long int q; string x, y; map<string, string> m; map<string, string>::iterator it; cin >> q; while (q--) { cin >> x >> y; if (m.count(x)) { string z; z = m[x]; m.erase(x); m[y] = z; } else { m[y] = x; } } cout << m.size() << endl; for (it = m.begin(); it != m.end(); it++) cout << it->second << << it->first << endl; return 0; }
|
//
// Designed by Qiang Wu
//
// 2048 bytes, 64bit interface
`timescale 1ns/1ps
module packet_memory(
clk,
input_mode,
addr64,
data_in64,
data_out64,
byte_we8,
addr32,
data_in32,
data_out32,
byte_we4
);
input clk;
input input_mode; //1 for 64, 0 for 32
input [10:3] addr64;
input [63:0] data_in64;
output [63:0] data_out64;
input [7:0] byte_we8;
input [10:2] addr32;
input [31:0] data_in32;
output [31:0] data_out32;
input [3:0] byte_we4;
reg [63:0] data_out64;
reg [31:0] data_out32;
reg wea0;
reg web0;
reg [8:0] addra0;
reg [8:0] addrb0;
reg [31:0] dia0;
reg [31:0] dib0;
wire [31:0] doa0;
wire [31:0] dob0;
always @(*) begin
wea0 = 0;
web0 = 0;
if(input_mode == 1) begin
addra0[8:0] = {addr64[10:3], 1'b0};
addrb0[8:0] = {addr64[10:3], 1'b1};
dia0 = data_in64[31:0];
dib0 = data_in64[63:32];
data_out64 = {dob0, doa0};
if(byte_we8) begin
wea0 = 1;
web0 = 1;
end else begin
wea0 = 0;
web0 = 0;
end
end else begin
addra0[8:0] = addr32[10:2];
dia0 = data_in32[31:0];
data_out32 = doa0;
if(byte_we4) begin
wea0 = 1;
end else begin
wea0 = 0;
end
end
end
wire [3:0] dipa;
wire [3:0] dipb;
RAMB16_S36_S36 pm0(
.DOA (doa0),
.DOB (dob0),
.DOPA (),
.DOPB (),
.ADDRA (addra0),
.ADDRB (addrb0),
.CLKA (clk),
.CLKB (clk),
.DIA (dia0),
.DIB (dib0),
.DIPA (dipa),
.DIPB (dipb),
.ENA (1'b1),
.ENB (1'b1),
.SSRA (reset),
.SSRB (reset),
.WEA (wea0),
.WEB (web0)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int stop, n, k, x, i, ind, j, y[1000001], mini[2001][2001]; string s[2001]; struct name { int a[26]; int cnt; } trie[1000001]; vector<int> d[1000001]; int m; void add(int v, int pos) { if (pos > s[i].length()) return; if (trie[v].a[s[i][pos] - a ]) add(trie[v].a[s[i][pos] - a ], pos + 1); else { m++; trie[v].a[s[i][pos] - a ] = m; add(m, pos + 1); }; trie[v].cnt++; } void dp(int v) { for (int j = 0; j < 26; j++) if (trie[v].a[j]) dp(trie[v].a[j]); d[v].resize(trie[v].cnt + 1); for (int j = 0; j < 26; j++) { int p = trie[v].a[j]; if (p == 0) continue; int s = d[p].size() - 1; for (int k1 = d[v].size() - s - 1; k1 >= 0; k1--) for (int i = 1; i <= s; i++) { d[v][k1 + i] = max(d[v][k1 + i], d[v][k1] + d[p][i] + i * (i - 1) / 2); } } } int main() { cin >> n >> k; for (i = 1; i <= n; i++) { cin >> s[i]; add(0, 0); }; dp(0); cout << d[0][k]; return 0; }
|
#include <bits/stdc++.h> using namespace std; char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } long long read() { char ch = getchar(); long long x = 0; int op = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) op = -1; for (; isdigit(ch); ch = getchar()) x = (x << 1) + (x << 3) + ch - 0 ; return x * op; } long long n, t, a[200005], b[200005], x[200005], tg[200005]; int main() { n = read(), t = read(); for (int i = (1); i <= (n); i++) a[i] = read(); for (int i = (1); i <= (n); i++) { x[i] = read(); if (x[i] < i) return puts( No ), 0; } for (int i = (1); i <= (n); i++) b[i] = a[i] + t; for (int i = (1); i <= (n); i++) if (x[i] > i) tg[i]++, tg[x[i]]--; for (int i = (1); i <= (n); i++) { tg[i] += tg[i - 1]; b[i] = max(b[i], b[i - 1] + 1); if (tg[i]) b[i] = max(b[i], a[i + 1] + t); } for (int i = (1); i <= (n); i++) if (x[i] + 1 <= n) if (b[x[i]] - a[x[i] + 1] >= t) return puts( No ), 0; puts( Yes ); for (int i = (1); i <= (n); i++) cout << b[i] << ; return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4786) #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const double PI = acos(-1.0); const double eps = 1e-6; const int maxn = 2e5 + 5; int isu[maxn], sz[maxn], dis[maxn], kk; long long ans; vector<int> G[maxn]; void dfs1(int root, int fa, long long depth) { int siz = G[root].size(), nt; dis[root] = depth; if (isu[root]) { sz[root] = 1; ans += depth; } for (int i = 0; i < siz; i++) { nt = G[root][i]; if (nt == fa) continue; dfs1(nt, root, depth + 1LL); sz[root] += sz[nt]; } } void solve(int root, int fa) { if (kk <= 0) return; priority_queue<pair<int, int> > Q; int siz = G[root].size(), nt; for (int i = 0; i < siz; i++) { nt = G[root][i]; if (nt == fa) continue; if (sz[nt] > 0) { Q.push(make_pair(sz[nt], nt)); } } if (isu[root]) { Q.push(make_pair(1, root)); } pair<int, int> f1 = Q.top(), f2; int fir = f1.first, sec = f1.second, sum = 0; if (Q.size() == 1) { solve(sec, root); } else { Q.pop(); while (!Q.empty()) { f2 = Q.top(); Q.pop(); sum += f2.first; } sum = min(sum, kk); kk -= sum; ans -= 2LL * dis[root] * sum; if (kk > 0) solve(sec, root); } } int main() { int n, k, x, y; scanf( %d %d , &n, &k); kk = k; for (int i = 1; i <= 2 * k; i++) { scanf( %d , &x); isu[x] = 1; } for (int i = 1; i < n; i++) { scanf( %d %d , &x, &y); G[x].push_back(y); G[y].push_back(x); } ans = 0; dfs1(1, 0, 0); solve(1, 0); printf( %lld n , ans); return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/wram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Work RAM module; implements 2KB of on-board WRAM as fpga block RAM.
***************************************************************************************************/
`timescale 1ps / 1ps
module wram(
input clk_in, // system clock
input en_in, // chip enable
input r_nw_in, // read/write select (read: 0, write: 1)
input [10:0] a_in, // memory address
input [ 7:0] d_in, // data input
output [ 7:0] d_out // data output
);
wire wram_bram_we;
wire [7:0] wram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) wram_bram(
.clk(clk_in),
.we(wram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(wram_bram_dout)
);
assign wram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? wram_bram_dout : 8'h00;
endmodule
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`define bsg_mem_1rw_sync_macro_2rf(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc180_2rf_lg``lgEls``_w``bits``_m``mux``_bit mem \
( \
.CLKA (clk_i ) \
,.AA (addr_i) \
,.CENA(~(~w_i&v_i)) \
,.QA (data_o) \
\
,.CLKB(clk_i ) \
,.CENB(~(w_i&v_i)) \
,.WENB(~w_mask_i) \
,.AB (addr_i) \
,.DB (data_i) \
); \
end
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [width_p-1:0] w_mask_i
, input w_i
, output [width_p-1:0] data_o
);
// we use a 2 port RF because the 1 port RF
// does not support bit-level masking for 80-bit width
// alternatively we could instantiate 2 40-bit 1rw RF's
`bsg_mem_1rw_sync_macro_2rf(64,80,6,1) else
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
// synopsys translate_off
always_ff @(posedge clk_i)
if (v_i)
assert (addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hs__u_mux_2_1 u_mux_21 (de_d , buf_Q, D, DE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool isPrime[1000005] = {false}; vector<long long int> SPF(1000005); long long int fastPower(long long int a, long long int b) { if (b == 0) return 1; long long int prod = 1; while (b > 0) { if (b & 1) prod = prod * a; b = b >> 1; a = a * a; } return prod; } void sieve() { int i; for (i = 2; i < 1000005; ++i) isPrime[i] = 1; for (i = 2; i * i < 1000005; ++i) { if (isPrime[i]) { for (int j = i * i; j < 1000005; j += i) isPrime[j] = 0; } } } void printa(bool f) { if (f) cout << YES ; else cout << NO ; cout << n ; } bool flip(bool f) { if (f) return 0; return 1; } void solve() { long long int i, n; cin >> n; vector<long long int> a(n); for (i = 0; i < n; ++i) cin >> a[i]; sort(a.begin(), a.end()); long long int s = 0, m = a[n - 1]; for (i = 0; i < n - 1; ++i) s += a[i]; cout << abs(m - s) + 1 << n ; } int main() { int tc = 1; while (tc--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[55]; int main() { int n, i, j, k, ans, x; int len; while (cin >> a) { ans = 0; x = 0; len = strlen(a); for (i = 0; i < len; i++) { for (j = len - 1; j > i; j--) { for (k = i; k <= j; k++) { if (a[k] != a[j - k + i]) break; } if (k != j + 1) { ans = max(ans, j - i); } } } if (ans != 0) cout << ans + 1 << endl; else cout << 0 << endl; } return 0; }
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 13.1 cbx_altiobuf_out 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratixiii 2013:10:24:09:15:20:SJ cbx_stratixv 2013:10:24:09:15:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , inline , -ffast-math ) #pragma GCC target( avx,sse2,sse3,sse4,mmx ) inline long long read() { long long s(0); bool w(1); char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } long long l, r, n, m, x, y, num; int main() { n = read(), x = read(); for (int i = 1; i <= n; i++) { num = read(); l = l * x + num; } scanf( %lld%lld , &m, &y); for (int i = 1; i <= m; i++) { num = read(); r = r * y + num; } puts(l == r ? = : (l > r ? > : < )); }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 18 11:58:34 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; const long long mod = 1000000007; int grid[maxn][maxn]; inline void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); } int main() { fast(); int h, w; cin >> h >> w; for (int i = 0; i < h; i++) { int x; cin >> x; for (int j = 0; j < x; j++) grid[i][j] = 1; grid[i][x] = 2; } for (int j = 0; j < w; j++) { int x; cin >> x; for (int i = 0; i < x; i++) { if (grid[i][j] == 2) { cout << 0 << endl; return 0; } grid[i][j] = 1; } if (grid[x][j] == 1) { cout << 0 << endl; return 0; } grid[x][j] = 2; } int ans = 1; for (int i = 0; i < h; i++) for (int j = 0; j < w; j++) { if (grid[i][j] == 0) { ans = ans * 2 % mod; } } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:34:47 09/03/2013
// Design Name:
// Module Name: synchronizer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module synchronizer(clk, rst, sensor,reprogram, walk_btn, rst_out, sensor_out, walk_register,
reprogram_out);
input clk;
input rst;
input sensor;
input reprogram;
input walk_btn;
output rst_out;
output sensor_out;
output walk_register;
output reprogram_out;
reg rst_out, sensor_out, walk_register, reprogram_out;
initial
begin
rst_out <= 0;
sensor_out <= 0;
walk_register <= 0;
reprogram_out <= 0;
end
always @ (posedge clk)
begin
rst_out <= rst;
sensor_out <= sensor;
walk_register <= walk_btn;
reprogram_out <= reprogram;
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_calc_vram_addr.v
//
// *Module Description:
// Compute next Video-Ram address
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_reg_vram_addr (
// OUTPUTs
vid_ram_addr_nxt_o, // Next Video-RAM address
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
display_width_i, // Display width
gfx_mode_1_bpp_i, // Graphic mode 1 bpp resolution
gfx_mode_2_bpp_i, // Graphic mode 2 bpp resolution
gfx_mode_4_bpp_i, // Graphic mode 4 bpp resolution
gfx_mode_8_bpp_i, // Graphic mode 8 bpp resolution
gfx_mode_16_bpp_i, // Graphic mode 16 bpp resolution
vid_ram_addr_i, // Video-RAM address
vid_ram_addr_init_i, // Video-RAM address initialization
vid_ram_addr_step_i, // Video-RAM address step
vid_ram_width_i, // Video-RAM width
vid_ram_msk_mode_i, // Video-RAM Mask mode enable
vid_ram_win_mode_i, // Video-RAM Windows mode enable
vid_ram_win_x_swap_i, // Video-RAM X-Swap configuration
vid_ram_win_y_swap_i, // Video-RAM Y-Swap configuration
vid_ram_win_cl_swap_i // Video-RAM CL-Swap configuration
);
// OUTPUTs
//=========
output [`APIX_MSB:0] vid_ram_addr_nxt_o; // Next Video-RAM address
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input [`LPIX_MSB:0] display_width_i; // Display width
input gfx_mode_1_bpp_i; // Graphic mode 1 bpp resolution
input gfx_mode_2_bpp_i; // Graphic mode 2 bpp resolution
input gfx_mode_4_bpp_i; // Graphic mode 4 bpp resolution
input gfx_mode_8_bpp_i; // Graphic mode 8 bpp resolution
input gfx_mode_16_bpp_i; // Graphic mode 16 bpp resolution
input [`APIX_MSB:0] vid_ram_addr_i; // Video-RAM address
input vid_ram_addr_init_i; // Video-RAM address initialization
input vid_ram_addr_step_i; // Video-RAM address step
input [`LPIX_MSB:0] vid_ram_width_i; // Video-RAM width
input vid_ram_msk_mode_i; // Video-RAM Mask mode enable
input vid_ram_win_mode_i; // Video-RAM Windows mode enable
input vid_ram_win_x_swap_i; // Video-RAM X-Swap configuration
input vid_ram_win_y_swap_i; // Video-RAM Y-Swap configuration
input vid_ram_win_cl_swap_i; // Video-RAM CL-Swap configuration
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
reg [`APIX_MSB:0] vid_ram_line_addr;
reg [`LPIX_MSB:0] vid_ram_column_count;
// Detect when the current line refresh is done
wire vid_ram_line_done = vid_ram_addr_step_i & (vid_ram_column_count>=(vid_ram_width_i-{{`LPIX_MSB{1'b0}}, 1'b1}));
// Compute increment value depending on mask mode
wire [`APIX_MSB:0] plus_one_val = {`APIX_MSB+1{gfx_mode_1_bpp_i & ~vid_ram_msk_mode_i}} & { {{`VRAM_MSB{1'b0}}, 1'b1}, 4'b0000} |
{`APIX_MSB+1{gfx_mode_2_bpp_i & ~vid_ram_msk_mode_i}} & {1'b0, {{`VRAM_MSB{1'b0}}, 1'b1}, 3'b000 } |
{`APIX_MSB+1{gfx_mode_4_bpp_i & ~vid_ram_msk_mode_i}} & {2'b00, {{`VRAM_MSB{1'b0}}, 1'b1}, 2'b00 } |
{`APIX_MSB+1{gfx_mode_8_bpp_i & ~vid_ram_msk_mode_i}} & {3'b000, {{`VRAM_MSB{1'b0}}, 1'b1}, 1'b0 } |
{`APIX_MSB+1{gfx_mode_16_bpp_i | vid_ram_msk_mode_i}} & {4'b0000, {{`VRAM_MSB{1'b0}}, 1'b1} } ;
// Mux between initialization value and display width
wire [`LPIX_MSB:0] vid_ram_width_mux = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;
// Zero extension for LINT cleanup
wire [`APIX_MSB*3:0] vid_ram_width_norm = {{`APIX_MSB*3-`LPIX_MSB{1'b0}}, vid_ram_width_mux};
// Select base address for next calculation
wire [`APIX_MSB:0] next_base_addr = (vid_ram_addr_init_i | ~vid_ram_line_done | ~vid_ram_win_mode_i) ? vid_ram_addr_i :
vid_ram_line_addr ;
// Compute next address
wire [`APIX_MSB:0] next_addr = next_base_addr
+ (vid_ram_width_norm[`APIX_MSB:0] & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? (~vid_ram_win_y_swap_i & (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
- (vid_ram_width_norm[`APIX_MSB:0] & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? ( vid_ram_win_y_swap_i & (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
+ (plus_one_val & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? (~vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : (~vid_ram_win_mode_i & ~vid_ram_addr_init_i)}})
- (plus_one_val & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? ( vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}});
wire update_line_addr = (vid_ram_addr_init_i | vid_ram_line_done) & vid_ram_win_mode_i;
wire update_pixel_addr = update_line_addr | vid_ram_addr_step_i;
// Start RAM address of currentely refreshed line
always @(posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_line_addr <= {`APIX_MSB+1{1'b0}};
else if (update_line_addr) vid_ram_line_addr <= next_addr;
// Current RAM address of the currentely refreshed pixel
wire [`APIX_MSB:0] vid_ram_addr_nxt_o = update_pixel_addr ? next_addr : vid_ram_addr_i;
// Count the pixel number in the current line
// (used to detec the end of a line)
always @(posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_column_count <= {`LPIX_MSB+1{1'b0}};
else if (vid_ram_addr_init_i) vid_ram_column_count <= {`LPIX_MSB+1{1'b0}};
else if (vid_ram_line_done) vid_ram_column_count <= {`LPIX_MSB+1{1'b0}};
else if (vid_ram_addr_step_i) vid_ram_column_count <= vid_ram_column_count + {{`LPIX_MSB+1-5{1'b0}}, plus_one_val[4:0]};
endmodule // ogfx_reg_vram_addr
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * f; } const long long MAXN = 100010; const long long INF = 1e9; const long long Mod = 1e9 + 7; long long N; set<pair<long long, long long> > S; long long P; long long last = 0; long long h[9][MAXN + 1]; long long inv[MAXN + 1]; long long top; long long f[MAXN + 1]; long long g[9]; pair<long long, long long> sta[MAXN + 1]; const long long inv2 = (Mod + 1) / 2; inline void Add(long long x, long long fn) { if (top && fn == sta[top].second) S.erase(sta[top]), sta[top].first = x, S.insert(sta[top]); else sta[++top] = make_pair(x, fn), S.insert(sta[top]); } inline long long Qf(long long x) { return (*S.upper_bound(make_pair(x - 1, 3))).second; } inline long long OPR(long long i) { long long l = 1, r = i + 1, d = (r - l) / 3; long long a = Qf(d), b = Qf((r - d) - l), fx = 0; fx = 0; while (fx == a || fx == b) ++fx; return fx; } long long ifac[MAXN + 1]; int main() { N = read(); P = read(); long long now = 2; f[1] = f[2] = 0; Add(2, 0); for (long long i = 3;; i++) { long long l = 1, r = i + 1, d = (r - l) / 3; long long a = f[d], b = f[(r - d) - l]; f[i] = 0; while (f[i] == a || f[i] == b) ++f[i]; if (f[i] != f[i - 1]) { last = i, Add(i - 1, f[i - 1]); if (i > 1000) { now = i - 1; break; } } } long long lena = 1, lenb = 1; for (; now <= P;) { ++now; while (sta[lena].first * 3 < now) ++lena; while ((sta[lenb].first * 3) / 2 < now) ++lenb; now = max(min((sta[lenb].first * 3 / 2) - 3, sta[lena].first * 3 - 3), now); for (long long j = 1; j <= 10; j++) Add(now, OPR(now)), ++now; } --P; for (long long i = 1; i <= top; i++) { long long len = min(sta[i].first, P) - min(sta[i - 1].first, P); (g[sta[i].second] += len * (P + 1) % Mod - (min(sta[i].first, P) + min(sta[i - 1].first, P) + 1) * len % Mod * inv2 % Mod + Mod) %= Mod; } inv[1] = 1; ifac[0] = 1; for (long long i = 2; i <= N; i++) inv[i] = (Mod - (Mod / i) * inv[Mod % i] % Mod) % Mod; for (long long i = 1; i <= N; i++) ifac[i] = ifac[i - 1] * inv[i] % Mod; for (long long i = 0; i < 3; i++) { long long ans = 1; for (long long j = 0; j <= N; j++) { if ((!(j & 1)) || (!i)) for (long long k = N - j; k >= 0; k--) (h[i][k + j] += (i ? h[i - 1][k] : (!k ? 1 : 0)) * ans % Mod * ifac[j] % Mod) %= Mod; ans = ans * g[i] % Mod; } } long long fac = 1, pw = 1, sum = (g[0] + g[1] + g[2]) % Mod; for (long long i = 1; i <= N; i++) fac = fac * i % Mod, pw = pw * sum % Mod; printf( %lld n , (pw - h[2][N] * fac % Mod + Mod) % Mod); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, q, a[300003], near[300003][20], last[300003]; signed main() { cin >> n >> q; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = n; i >= 1; i--) { for (int k = 0; k < 20; k++) { near[i][k] = n + 1; if (((1 << k) & a[i]) && last[k]) near[i][k] = last[k]; for (int j = 0; j < 20; j++) { if (last[j] && ((a[i] >> j) & 1)) { near[i][k] = min(near[i][k], near[last[j]][k]); } } if (near[i][k] == n + 1) near[i][k] = i; } for (int k = 0; k < 20; k++) if ((a[i] >> k) & 1) last[k] = i; } while (q--) { int l, r; cin >> l >> r; for (int i = 0; i < 20; i++) { if (((a[r] >> i) & 1) && near[l][i] != l && near[l][i] <= r) { puts( Shi ); l = r; break; } } if (l < r) puts( Fou ); } }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bios86.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bios86 (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../bios86.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../bios86.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../bios86.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : pcie_brams_s6.v
// Description: BlockRAM module for Spartan-6 PCIe Block
//
// Arranges and connects brams
// Implements address decoding, datapath muxing and
// pipeline stages
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_brams_s6 #(
// the number of BRAMs to use
// supported values are:
// 1,2,4,9
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1
) (
input user_clk_i,
input reset_i,
input wen,
input [11:0] waddr,
input [35:0] wdata,
input ren,
input rce,
input [11:0] raddr,
output [35:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 36 :
(NUM_BRAMS == 2) ? 18 :
(NUM_BRAMS == 4) ? 9 :
4
);
localparam TCQ = 1;
//synthesis translate_off
initial begin
case (NUM_BRAMS)
1,2,4,9:;
default: begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default: begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default: begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default: begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
wire wen_int;
wire [11:0] waddr_int;
wire [35:0] wdata_int;
generate
if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_dly;
reg [11:0] waddr_dly;
reg [35:0] wdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
wen_dly <= #TCQ 1'b0;
waddr_dly <= #TCQ 12'b0;
wdata_dly <= #TCQ 36'b0;
end else begin
wen_dly <= #TCQ wen;
waddr_dly <= #TCQ waddr;
wdata_dly <= #TCQ wdata;
end
end
assign wen_int = wen_dly;
assign waddr_int = waddr_dly;
assign wdata_int = wdata_dly;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
wire ren_int;
wire [11:0] raddr_int;
wire [35:0] rdata_int;
generate
if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_dly;
reg [11:0] raddr_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
ren_dly <= #TCQ 1'b0;
raddr_dly <= #TCQ 12'b0;
end else begin
ren_dly <= #TCQ ren;
raddr_dly <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_dly;
assign raddr_int = raddr_dly;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate
if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [35:0] rdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
rdata_dly <= #TCQ 36'b0;
end else begin
rdata_dly <= #TCQ rdata_int;
end // else: !if(reset_i)
end
assign rdata = rdata_dly;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar i;
for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
pcie_bram_s6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
.wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
.ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
end
endgenerate
endmodule // pcie_brams_s6
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> a(n); vector<int> update(n); for (int i = 0; i < n; i++) { cin >> a[i]; update[i] = 0; } int accumalated = 0; for (int i = 0; i < m; i++) { int t; cin >> t; if (t == 1) { int v, x; cin >> v >> x; a[v - 1] = x; update[v - 1] = accumalated; } else if (t == 2) { int y; cin >> y; accumalated += y; } else { int q; cin >> q; cout << a[q - 1] + accumalated - update[q - 1] << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b; bool check(int k, int x, int y) { long long ca = 1LL * k * x; long long cb = 1LL * k * y; return ca <= a && cb <= b; } long long gcd(long long a, long long b) { if (!b) return a; else return gcd(b, a % b); } int main() { int x, y; cin >> a >> b >> x >> y; int l = 1, r = 2 * 1e9; long long ans = 2e9 + 1; long long g = gcd(x, y); x /= g; y /= g; while (l <= r) { int mid = (l + r) >> 1; if (check(mid, x, y)) { ans = mid; l = mid + 1; } else r = mid - 1; } if (ans == 2e9 + 1) cout << 0 0 << endl; else cout << x * ans << << y * ans << endl; }
|
module lcd (
input clk,
output reg lcd_rs,
output reg lcd_rw,
output reg lcd_e,
output reg [7:4] lcd_d,
output [4:0] mem_addr,
input [7:0] mem_bus
);
parameter n = 24;
parameter j = 17; // Initialization is slow, runs at clk/2^(j+2) ~95Hz
parameter k = 11; // Writing/seeking is fast, clk/2^(k_2) ~6KHz
parameter noop = 6'b010000; // Allows LCD to drive lcd_d, can be safely written any time
reg [n:0] count = 0;
reg [5:0] lcd_state = noop;
reg init = 1; // Start in initialization on power on
reg row = 0; // Writing to top or or bottom row
assign mem_addr = {row, count[k+6:k+3]};
initial count[j+7:j+2] = 11;
always @ (posedge clk) begin
count <= count + 1;
if (init) begin // initalization
case (count[j+7:j+2])
1: lcd_state <= 6'b000010; // function set
2: lcd_state <= 6'b000010;
3: lcd_state <= 6'b001000;
4: lcd_state <= 6'b000000; // display on/off control
5: lcd_state <= 6'b001100;
6: lcd_state <= 6'b000000; // display clear
7: lcd_state <= 6'b000001;
8: lcd_state <= 6'b000000; // entry mode set
9: lcd_state <= 6'b000110;
10: begin init <= ~init; count <= 0; end
endcase
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[j+1:j+0] & ~lcd_rw,lcd_state};
end else begin // Continuously update screen from memory
case (count[k+7:k+2])
32: lcd_state <= {3'b001,~row,2'b00}; // Move cursor to begining of next line
33: lcd_state <= 6'b000000;
34: begin count <= 0; row <= ~row; end // Restart and switch which row is being written
default: lcd_state <= {2'b10, ~count[k+2] ? mem_bus[7:4] : mem_bus[3:0]}; // Pull characters from bus
endcase
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[k+1:k+0] & ~lcd_rw,lcd_state};
end
end
endmodule
|
#include <bits/stdc++.h> const int N = 25, Mod = 1e6 + 3; const int n = 11; int y[N], k, inv[Mod + 2]; int fm[] = {404910, 950915, 220896, 410947, 30845, 962989, 30845, 410947, 220896, 950915, 404910}; inline int po(int x, int y) { int r = 1; while (y) { if (y & 1) r = 1ll * r * x % Mod; x = 1ll * x * x % Mod, y >>= 1; } return r; } int judge(int k) { int ans = 0, base = 1; for (int i = 1; i <= n; ++i) if (k != i) base = 1ll * base * (k - i) % Mod; if (1 <= k && k <= 11) return (1ll * base * fm[k - 1] % Mod * y[k] % Mod + Mod) % Mod; base = (base + Mod) % Mod; for (int i = 1; i <= n; ++i) ans = (ans + 1ll * base * inv[(k - i + Mod) % Mod] % Mod * fm[i - 1] % Mod * y[i] % Mod) % Mod; return ans; } int main() { for (int i = 1; i <= n; ++i) { printf( ? %d n , i); fflush(stdout); scanf( %d , &y[i]); } inv[0] = inv[1] = 1; for (int i = 2; i < Mod; ++i) inv[i] = 1ll * (Mod - Mod / i) * inv[Mod % i] % Mod; for (int k = 0; k < Mod; ++k) if (!judge(k)) { printf( ! %d n , k); fflush(stdout); return 0; } printf( ! -1 n ); fflush(stdout); }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T abs(T zz) { return zz < 0 ? -zz : zz; } template <typename T> inline T sqr(T zz) { return zz * zz; } const int MAGIC = 1000500; vector<int> used; vector<int> primes; bool is_prime(int n) { for (int p : primes) { if (p * p > n) break; if (n % p == 0) return false; } return true; } int main() { used = vector<int>(MAGIC, 0); for (int i = 2; i < MAGIC; ++i) { if (!used[i]) { primes.push_back(i); for (int j = i; j < MAGIC; j += i) { used[j] = true; } } } int n; cin >> n; if (is_prime(n) == 1) { cout << 1 << endl; return 0; } if (n % 2 == 0) { cout << 2 << endl; return 0; } if (is_prime(n - 2)) { cout << 2 << endl; return 0; } cout << 3 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int find_47(const string& s, int from) { for (int i = from; i < (s.size() - 1); i++) { if ((s[i] == 4 ) && (s[i + 1] == 7 )) return i; } return -1; } int main() { int n, k; cin >> n >> k; cin >> s; int from = 0; while (true) { if (k == 0) break; int ind = find_47(s, from); if (ind == -1) break; if (ind % 2 == 0) { if (ind + 2 >= n) { s[ind + 1] = 4 ; break; } if (s[ind + 2] == 7 ) { if (k % 2 == 1) s[ind + 1] = 4 ; break; } else { s[ind + 1] = 4 ; k--; from = ind + 2; } } else { if (s[ind - 1] == 4 ) { if (k % 2 == 1) s[ind] = 7 ; break; } else { s[ind] = 7 ; k--; from = ind + 1; } } } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> int A, B, M = 6, N; int main() { scanf( %d%d%d , &N, &A, &B); int nda = N / A; for (int i = 1; (i <= 2) && (B * i <= N); ++i) M = std::min((i ^ 3) + (4 - ((N - B * i) / A) * (i ^ 3) + nda - 1) / nda, M); printf( %d n , M); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int itr = 0; itr < t; itr++) { int n; vector<int> s; cin >> n; for (int i = 1; i <= n; i++) { int tmp; cin >> tmp; s.push_back(tmp); } int token = 0; for (int i = 0; i < s.size(); i++) { int flag = 0; for (int j = 2; j <= 2 + i; j++) { if (s[i] % j != 0) { flag = 1; break; } } if (flag == 0) { token = 1; break; } } if (token == 1) cout << NO n ; else cout << YES n ; } }
|
module spi_clock_generator(
//CLK
// i_clk is the system clock (10-200MHz)
input i_clk,
//RST
// i_reset is the system reset. This is a active high signal.
// '1' : reset is active
input i_reset,
//Controll inputs from registers
input i_spr0,
input i_spr1,
input i_cpol,
input i_cpha,
input i_mstr,
// Controll output to other logic
// o_sclk: This is the SPI clock. The polarity based on the i_cpol
// The frequency is derived by i_spr0 and i_spr1
output o_sclk,
// o_sclk_rising_edge: is active one sys clk long at the rising edge of
// the sclk.
output o_sclk_rising_edge,
// o_sclk_falling_edge: is active one sys clk long at the falling edge of
// the sclk.
output o_sclk_falling_edge,
// o_sample_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
output o_sample_spi_data,
// o_setup_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
// Note that this is the alter edge than o_sample_spi_data
output o_setup_spi_data
);
// The spi clock counter. The max value is depends on the frequency which
// derived by i_spr0 and i_spr1
reg [6:0] q_spi_sclk_cntr;
wire w_sclk_internal;
wire [1:0]w_clk_select;
reg q_sclk_internal_d1; //alwaysbe reg, d1->eggyel kesleltetett
wire w_sclk_rising_edge_internal;
wire w_sclk_falling_edge_internal;
wire w_sample_spi_data_internal;
wire w_setup_spi_data;
wire [1:0] w_sample_setup_select;
always @(posedge i_clk) begin : SCLK_CNTR
if (i_reset) begin
q_spi_sclk_cntr <= 7'b0 ;
end else begin
q_spi_sclk_cntr <= q_spi_sclk_cntr + 1;
end
end
assign w_clk_select={i_spr0,i_spr1};
assign w_sclk_internal = (w_clk_select==0) ? q_spi_sclk_cntr[1] :
(w_clk_select==1) ? q_spi_sclk_cntr[3] :
(w_clk_select==2) ? q_spi_sclk_cntr[5] :
(w_clk_select==3) ? q_spi_sclk_cntr[6] :
0; // soha nem jut ide
assign o_sclk = w_sclk_internal;
always @(posedge i_clk) begin : SCLK_EDGE_DETECT
if (i_reset) begin
q_sclk_internal_d1<=0;
end
else begin
q_sclk_internal_d1 <=w_sclk_internal;
end
end
//felfuto el
assign w_sclk_rising_edge_internal = (w_sclk_internal > q_sclk_internal_d1) ? 1:
0; //ha nagyobb az aktualis, mint az elozo ->felfuto
assign o_sclk_rising_edge = w_sclk_rising_edge_internal;
//lefuto el
assign w_sclk_falling_edge_internal = (w_sclk_internal < q_sclk_internal_d1) ? 1:
0; //ha kisebb ->lefuto
assign o_sclk_falling_edge = w_sclk_falling_edge_internal;
assign w_sample_setup_select={i_cpol,i_cpha};
//o_sample_spi_data
assign w_sample_spi_data_internal = (w_sample_setup_select==0) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==1) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==2) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==3) ? w_sclk_rising_edge_internal:
0;
assign o_sample_spi_data = w_sample_spi_data_internal;
//o_setup_spi_data
assign w_setup_spi_data = (w_sample_setup_select==0) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==1) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==2) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==3) ? w_sclk_falling_edge_internal:
0;
assign o_setup_spi_data = w_setup_spi_data;
// -- TODO --
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_rgmii_module.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
//
// $Revision: #1 $
// $Date: 2014/02/16 $
// Check in by : $Author: swbranch $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top level RGMII interface (receive and transmit) module.
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
);
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
wire m_rx_col;
reg m_rx_col_reg;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
wire speed_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col_reg = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col_reg = 1'b1;
end
end
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(m_rx_col_reg), //INPUT
.dout(m_rx_col));// OUTPUT
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(speed), //INPUT
.dout(speed_reg));// OUTPUT
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed_reg)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed_reg)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module quad_uart
#(parameter TXDEPTH = 1,
parameter RXDEPTH = 1)
(input clk_i, input rst_i,
input we_i, input stb_i, input cyc_i, output reg ack_o,
input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
output [3:0] rx_int_o, output [3:0] tx_int_o,
output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
);
// Register Map
localparam SUART_CLKDIV = 0;
localparam SUART_TXLEVEL = 1;
localparam SUART_RXLEVEL = 2;
localparam SUART_TXCHAR = 3;
localparam SUART_RXCHAR = 4;
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
reg [15:0] clkdiv[0:3];
wire [7:0] rx_char[0:3];
wire [3:0] tx_fifo_full, rx_fifo_empty;
wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
always @(posedge clk_i)
if (rst_i)
ack_o <= 1'b0;
else
ack_o <= wb_acc & ~ack_o;
integer i;
always @(posedge clk_i)
if (rst_i)
for(i=0;i<4;i=i+1)
clkdiv[i] <= 0;
else if (wb_wr)
case(adr_i[2:0])
SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
endcase // case(adr_i)
always @(posedge clk_i)
case (adr_i[2:0])
SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
endcase // case(adr_i)
genvar j;
generate
for(j=0;j<4;j=j+1)
begin : gen_uarts
simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
(.clk(clk_i),.rst(rst_i),
.fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
.fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
.clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
(.clk(clk_i),.rst(rst_i),
.fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
.fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
.clkdiv(clkdiv[j]),.rx(rx_i[j]));
end // block: gen_uarts
endgenerate
assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space
assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data
endmodule // quad_uart
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_BEHAVIORAL_V
|
module juniversalShiftRegisterTb;
wire [3:0] DATAOUT;
reg clock, reset;
reg [1:0] MODE;
reg [3:0] DATAIN;
juniversalShiftRegister jusr(DATAOUT, clock, reset, MODE, DATAIN);
initial
begin
clock =0; MODE = 2'b00; DATAIN = 4'b0000;
reset = 1; #10; reset = 0; #10;
$display("RSLT\tD == DOUT");
// Start testing Right Shift mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b01; DATAIN = 4'b0011; #10;
if ( DATAOUT === 4'b1000 ) // look at previous value of DATAOUT as well
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
MODE = 2'b01; DATAIN = 4'b0011; #10;
if ( DATAOUT === 4'b1100 ) // look at previous value of DATAOUT as well
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
// Start testing Left Shift mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b10; DATAIN = 4'b0111; #10;
if ( DATAOUT === 4'b0001 ) //
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
MODE = 2'b10; DATAIN = 4'b0111; #10;
if ( DATAOUT === 4'b0011 ) //
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
// Start testing parallel load mode
MODE = 2'b00; reset = 1; #10; reset = 0; #10;
MODE = 2'b11; DATAIN = 4'b1010; #10;
if ( DATAOUT === 4'b1010 )
$display("PASS\t%p is %p with %p", DATAIN, MODE, DATAOUT);
else
$display("FAIL\t%p is %p with %p", DATAIN, MODE, DATAOUT);
#20;
$finish;
end
always #5 clock = ~clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i; cin >> n; if (n == 1 || n == 2) cout << -1 ; else { for (i = n; i >= 1; i--) cout << i << ; cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O41AI_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 30, Mod = 1e9 + 7; const long long SQ = 330; unordered_map<int, int> Par[N]; map<pair<int, int>, int> ans; vector<int> G[N]; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); inline int find(int x, int c) { if (Par[c].find(x) == Par[c].end()) return x; return Par[c][x] = find(Par[c][x], c); } inline void merge(int x, int y, int c) { x = find(x, c); y = find(y, c); if (x == y) return; Par[c][x] = y; } int main() { ios::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b, c; cin >> a >> b >> c; G[a].push_back(c); G[b].push_back(c); merge(a, b, c); } for (int i = 1; i <= n; i++) { sort(G[i].begin(), G[i].end()); G[i].resize(unique(G[i].begin(), G[i].end()) - G[i].begin()); } int q; cin >> q; while (q--) { int a, b; cin >> a >> b; if (G[a].size() > G[b].size()) swap(a, b); if (G[a].size() == G[b].size() and a > b) swap(a, b); if (ans.count({a, b})) { cout << ans[{a, b}] << n ; continue; } int res = 0; for (auto u : G[a]) if (find(b, u) == find(a, u)) res++; ans[{a, b}] = res; cout << res << n ; } return (0); }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e15; long long q[300005]; long long d[300005]; long long dd[300005]; struct st { long long x, w, id; }; vector<st> v[300005]; st t; vector<long long> ans; long long sum; long long n, m; long long x, y, z; inline void dij(long long st) { for (long long i = 1; i <= n; ++i) d[i] = inf; set<pair<long long, long long> > s; d[st] = 0; s.insert(make_pair(0, st)); while (!s.empty()) { long long x = s.begin()->second; s.erase(s.begin()); for (long long i = 0; i < v[x].size(); ++i) { long long to = v[x][i].x; long long len = d[x] + v[x][i].w; if (d[to] > len) { s.erase(make_pair(d[to], to)); d[to] = len; s.insert(make_pair(d[to], to)); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (long long i = 1; i <= m; ++i) { cin >> x >> y >> z; t.x = y; t.w = z; t.id = i; v[x].push_back(t); t.x = x; v[y].push_back(t); } long long stt; cin >> stt; dij(stt); for (long long i = 1; i <= n; ++i) { long long mx = 1e9; for (long long j = 0; j < v[i].size(); ++j) { long long to = v[i][j].x; if (d[to] != d[i] - v[i][j].w) continue; mx = min(mx, v[i][j].w); } for (long long j = 0; j < v[i].size(); ++j) { long long to = v[i][j].x; if (d[to] != d[i] - v[i][j].w) continue; if (v[i][j].w == mx) { ans.push_back(v[i][j].id); sum += v[i][j].w; break; } } } cout << sum << n ; for (long long i = 0; i < ans.size(); ++i) cout << ans[i] << ; }
|
// file: dcm_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module dcm_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
dcm_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module: altor32_ram_sp - Single port RAM (used in cache)
//-----------------------------------------------------------------
module altor32_ram_sp
#(
parameter [31:0] WIDTH = 8,
parameter [31:0] SIZE = 14
)
(
input clk_i /*verilator public*/,
output [(WIDTH - 1):0] dat_o /*verilator public*/,
input [(WIDTH - 1):0] dat_i /*verilator public*/,
input [(SIZE - 1):0] adr_i /*verilator public*/,
input wr_i /*verilator public*/
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
reg [(SIZE - 1):0] rd_addr_q;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @ (posedge clk_i)
begin
if (wr_i == 1'b1)
ram[adr_i] <= dat_i;
rd_addr_q <= adr_i;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign dat_o = ram[rd_addr_q];
//-----------------------------------------------------------------
// Init Memory
//-----------------------------------------------------------------
`ifdef ALTOR32_CLEAR_RAM
integer i;
initial
begin
for (i=0;i<((2<< (SIZE-1)) - 1);i=i+1)
begin
ram[i] = 0;
end
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T nextInt() { T x = 0, p = 1; char ch; do { ch = getchar(); } while (ch <= ); if (ch == - ) { p = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * p; } const int maxN = (int)3e5 + 10; const int INF = (int)1e9; const int mod = (int)1e9 + 7; const long long LLINF = (long long)1e18; const long double pi = acos(-1.0); int x[2]; int y[2]; int r[2]; long double d; long double solve(int xa, int ya, int ra, int xb, int yb, int rb) { long double angle = 2 * acos((rb * 1LL * rb - ra * 1LL * ra - d * d) / (-2 * ra * d)); return pi * ra * ra * angle / (2 * pi) - 1LL * ra * ra * sin(angle) / 2; } int main() { cin >> x[0] >> y[0] >> r[0] >> x[1] >> y[1] >> r[1]; d = sqrtl((x[0] - x[1]) * 1LL * (x[0] - x[1]) + (y[0] - y[1]) * 1LL * (y[0] - y[1])); cout.precision(21); if (d >= r[0] + r[1]) { cout << 0 << n ; return 0; } if (d <= abs(r[0] - r[1])) { cout << pi * min(r[0], r[1]) * min(r[0], r[1]) << n ; return 0; } cout << solve(x[0], y[0], r[0], x[1], y[1], r[1]) + solve(x[1], y[1], r[1], x[0], y[0], r[0]) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int cntinv(vector<int> &a) { int n = a.size(); int ans = 0; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (a[j] < a[i]) ans++; } } return ans; } int main(int argc, char const *argv[]) { int n; scanf( %d , &n); vector<int> a(n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } int pv = (cntinv(a) & 1); int m; scanf( %d , &m); while (m--) { int l, r, swaps; scanf( %d , &l); scanf( %d , &r); l--; r--; swaps = (r - l + 1) >> 1; int cur = pv; if (swaps & 1) cur = 1 - cur; if (cur) printf( odd n ); else printf( even n ); pv = cur; } return 0; }
|
#include <bits/stdc++.h> using namespace std; string c; int main() { int i, j, k, n, m, l; scanf( %d%d , &n, &k); if (n * (n - 1) / 2 <= k) { puts( no solution ); return 0; } for (i = 1; i <= n; i++) printf( %d %d n , 0, i); return 0; }
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#include <bits/stdc++.h> using namespace std; int a1, a2, b1, b2, c1, c2; int main() { cin >> a1 >> b1 >> c1 >> a2 >> b2 >> c2; if (a1 == 0 && b1 == 0 && c1 != 0 || a2 == 0 && b2 == 0 && c2 != 0) { cout << 0 n ; return 0; } int m1 = b1 * a2, m2 = b2 * a1; if (m1 == m2) if (c1 * b2 != c2 * b1 || a1 * c2 != a2 * c1) cout << 0 n ; else cout << -1 n ; else cout << 1 n ; return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; char ch = getchar(); bool f = 0; for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = 1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return f ? -x : x; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(long long x) { write(x); puts( ); } void writep(long long x) { write(x); putchar( ); } const int N = 5e5 + 5, mo = 1e9 + 7; int n, m, a[N], fac[N], inv[N], b[N]; char s[N]; int C(int n, int m) { if (n < m) return 0; return (long long)fac[n] * inv[m] % mo * inv[n - m] % mo; } int ksm(int x, int p) { int res = 1; for (; p; p >>= 1, x = (long long)x * x % mo) if (p & 1) res = (long long)res * x % mo; return res; } void init(int n) { fac[0] = 1; for (int i = (int)(1); i <= (int)(n); i++) fac[i] = (long long)i * fac[i - 1] % mo; inv[n] = ksm(fac[n], mo - 2); for (int i = (int)(n - 1); i >= (int)(0); i--) inv[i] = (long long)(i + 1) * inv[i + 1] % mo; } int upd(int x, int y) { x += y; if (x >= mo) x -= mo; return x; } int main() { init(N - 1); n = read(); m = read(); scanf( %s , s + 1); for (int i = (int)(1); i <= (int)(n); i++) a[i] = s[i] - 0 ; reverse(a + 1, a + n + 1); int sum = 0, now = 1; b[1] = C(n - 1, m); for (int i = (int)(2); i <= (int)(n); i++) { sum = upd(sum, (long long)now * C(n - i, m - 1) % mo); now = (long long)10 * now % mo; b[i] = upd(sum, (long long)now * C(n - i, m) % mo); } int ans = 0; for (int i = (int)(1); i <= (int)(n); i++) ans = upd(ans, (long long)b[i] * a[i] % mo); cout << ans; }
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//faux_hd_command_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module faux_hd_command_layer (
input rst, //reset
input clk,
output command_layer_ready,
output command_layer_busy,
output hd_read_from_host,
output [31:0] hd_data_from_host,
output hd_write_to_host,
input [31:0] hd_data_to_host,
input transport_layer_ready,
output reg send_reg_stb,
output reg send_dma_act_stb,
output reg send_data_stb,
output reg send_pio_stb,
output reg send_dev_bits_stb,
input remote_abort,
input xmit_error,
input read_crc_fail,
input h2d_reg_stb,
input h2d_data_stb,
input pio_request,
output reg [15:0] pio_transfer_count,
output reg pio_direction,
output reg [7:0] pio_e_status,
//FIS Structure
input [7:0] h2d_command,
input [15:0] h2d_features,
input h2d_cmd_bit,
input [3:0] h2d_port_mult,
input [7:0] h2d_control,
input [7:0] h2d_device,
input [47:0] h2d_lba,
input [15:0] h2d_sector_count,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [7:0] d2h_status,
output reg [7:0] d2h_error,
output reg [3:0] d2h_port_mult,
output reg [7:0] d2h_device,
output reg [47:0] d2h_lba,
output reg [15:0] d2h_sector_count,
//command layer data interface
input cl_if_strobe,
output [31:0] cl_if_data,
output cl_if_ready,
input cl_if_activate,
output [23:0] cl_if_size,
input cl_of_strobe,
input [31:0] cl_of_data,
output [1:0] cl_of_ready,
input [1:0] cl_of_activate,
output [23:0] cl_of_size,
output [3:0] cl_state
);
//Parameters
parameter SLEEP_START = 4'h0;
parameter SEND_DIAGNOSTICS = 4'h1;
parameter IDLE = 4'h2;
parameter DMA_READY = 4'h3;
parameter READ_DATA = 4'h4;
parameter SEND_DATA = 4'h5;
parameter READ_IN_PROGRESS = 4'h6;
parameter SEND_STATUS = 4'h7;
parameter SLEEP_LENGTH = 100;
//Registers/Wires
reg [3:0] state = SLEEP_START;
wire idle;
reg [8:0] byte_count = 0;
reg [16:0] sector_count = 0;
reg [16:0] sector_size = 16'h0000;
reg [15:0] sleep_count = 0;
wire soft_reset;
//Asynchronous Logic
assign idle = (state == IDLE);
assign command_layer_busy = !idle;
assign command_layer_ready = idle;
//Short circuit the ping pong fifos
assign hd_read_from_host = cl_of_strobe;
assign hd_data_from_host = cl_of_data;
assign cl_of_ready = 1;
assign cl_of_size = 2048;
assign hd_write_to_host = cl_if_strobe;
assign cl_if_data = hd_data_to_host;
assign cl_if_ready = 1;
assign cl_if_size = 24'h0100;
assign soft_reset = h2d_control[`CONTROL_SRST_BIT];
assign cl_state = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= SLEEP_START;
send_reg_stb <= 0;
send_dma_act_stb <= 0;
send_data_stb <= 0;
send_pio_stb <= 0;
send_dev_bits_stb <= 0;
sector_count <= 0;
sector_size <= 1000;
sleep_count <= 0;
pio_transfer_count <= 0;
pio_direction <= 0;
pio_e_status <= 0;
d2h_interrupt <= 0;
d2h_notification <= 0;
d2h_status <= 8'h50;
d2h_error <= 1;
d2h_port_mult <= 0;
d2h_lba <= 1;
d2h_sector_count <= 1;
d2h_device <= 0;
byte_count <= 0;
end
else begin
//Strobe Lines
send_reg_stb <= 0;
send_dma_act_stb <= 0;
send_data_stb <= 0;
send_pio_stb <= 0;
send_dev_bits_stb <= 0;
if (soft_reset) begin
if (soft_reset) begin
$display ("Reset from soft reset");
end
state <= SLEEP_START;
sleep_count <= 0;
end
case (state)
SLEEP_START: begin
if (sleep_count < SLEEP_LENGTH) begin
sleep_count <= sleep_count + 1;
end
else begin
state <= SEND_DIAGNOSTICS;
end
end
SEND_DIAGNOSTICS: begin
$display ("Send Diagnostics");
send_reg_stb <= 1;
state <= IDLE;
end
IDLE: begin
if (h2d_reg_stb) begin
if (h2d_cmd_bit) begin
d2h_lba <= h2d_lba;
d2h_sector_count <= h2d_sector_count;
if (h2d_sector_count == 0) begin
sector_size <= 17'h10000;
end
else begin
sector_size <= h2d_sector_count;
end
case (h2d_command)
`COMMAND_DMA_READ_EX: begin
//send_data_stb <= 1;
sector_count <= 0;
state <= SEND_DATA;
end
`COMMAND_DMA_WRITE_EX: begin
send_dma_act_stb <= 1;
sector_count <= 0;
state <= DMA_READY;
end
default: begin
//unrecognized command
$display ("fcl: Unrecognized command from host");
end
endcase
end
end
end
DMA_READY: begin
if (transport_layer_ready) begin
send_dma_act_stb <= 1;
byte_count <= 0;
state <= READ_DATA;
end
end
READ_DATA: begin
if (cl_of_activate && cl_of_strobe) begin
byte_count <= byte_count + 4;
end
if(byte_count == 508) begin
sector_count <= sector_count + 1;
end
if (h2d_data_stb) begin
if (sector_count < sector_size) begin
state <= DMA_READY;
end
else begin
state <= SEND_STATUS;
end
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
sector_count <= sector_count + 1;
send_data_stb <= 1;
state <= READ_IN_PROGRESS;
//state <= SEND_STATUS;
end
end
READ_IN_PROGRESS: begin
if (!transport_layer_ready) begin
state <= SEND_STATUS;
end
//if (sector_count < sector_size) begin
// state <= SEND_DATA;
//end
//else begin
// if (transport_layer_ready) begin
// send_reg_stb <= 1;
// //Send a done register
// state <= SEND_STATUS;
// end
//end
end
SEND_STATUS: begin
if (transport_layer_ready) begin
send_reg_stb <= 1;
//Send a done register
state <= IDLE;
end
end
default: begin
$display ("fcl: Entered illegal state, restart");
state <= SLEEP_START;
sleep_count <= 0;
end
endcase
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int MAXN = 2025; const int MOD = 998244353; int n, k; namespace Task1 { int ans; int f[MAXN][MAXN]; int sum[MAXN][MAXN]; void solve() { f[0][n] = 1; for (int i = n; i >= 1; i--) sum[0][i] = 1; for (int i = 1; i <= n; i++) for (int j = i; j >= 1; j--) { f[i][j] = sum[i - j][j]; (ans += f[i][j]) %= MOD; sum[i][j] = (sum[i][j + 1] + f[i][j]) % MOD; } printf( %d n , ans); } } // namespace Task1 namespace Task2 { int ans, N; vector<int> f[MAXN][70]; vector<int> sum[MAXN][70]; void solve() { N = min(n, 65); for (int i = 0; i <= n; i++) { f[i][0].resize(MAXN); sum[i][0].resize(MAXN); for (int j = 1; j <= N; j++) { f[i][j].resize(i / j + 2); sum[i][j].resize(i / j + 2); } } f[0][0][n] = 1; for (int i = n; i >= 1; i--) sum[0][0][i] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= N; j++) for (int k = i / j; k >= 1; k--) { if (sum[i - j * k][j - 1].size() > k) f[i][j][k] = sum[i - j * k][j - 1][k]; (ans += f[i][j][k]) %= MOD; sum[i][j][k] = (sum[i][j][k + 1] + f[i][j][k]) % MOD; } printf( %d n , ans); } } // namespace Task2 namespace Task3 { int ans; vector<int> a; bool chk(vector<int> t) { int K = k; while (K--) { vector<int> tt; int sum = 0; for (int i = 0; i < t.size(); i++) sum += t[i]; if (sum > n) return 0; tt.resize(sum); int tot = 0; for (int i = t.size() - 1; i >= 0; i--) for (int j = 1; j <= t[i]; j++) tt[tot++] = i + 1; swap(tt, t); } return 1; } void dfs(int d) { if (d > 1 && !chk(a)) return; if (d > 1) ans++; int t = d > 1 ? a.back() : n; for (int i = 1; i <= t; i++) { a.push_back(i); int tmp = ans; dfs(d + 1); a.pop_back(); if (ans == tmp) return; } } void solve() { dfs(1); printf( %d n , ans); } } // namespace Task3 int main() { scanf( %d%d , &n, &k); if (k == 1) Task1::solve(); if (k == 2) Task2::solve(); if (k >= 3) Task3::solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long int i, m, n; double add, ans, t1, t2; scanf( %ld%ld , &m, &n); for (i = 1; i <= m; i++) { t1 = (double)i / m; t2 = (double)(i - 1) / m; add = i * (pow(t1, n) - pow(t2, n)); ans += add; } printf( %.7lf , ans); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; int n; pair<int, int> e[200005]; int deg[200005]; vector<int> Adj[200005]; void solve(); int main() { solve(); } void solve() { cin >> n; for (int i = 1; i <= n - 1; i++) { int u, v; cin >> u >> v; e[i] = {u, v}; Adj[u].push_back(v); Adj[v].push_back(u); } for (int i = 1; i <= n - 1; i++) { int u = e[i].first, v = e[i].second; int c = 0, d = 0; if (Adj[u].size() - 1 == 1) { cout << NO ; return; } if (Adj[v].size() - 1 == 1) { cout << NO ; return; } } cout << YES ; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int n, k, m, res = 0, sm = 0, edge = -1, nb = 1; int a[200055], b[200050], nxt[200505], dp[200005] = {0}, ans[500005]; multiset<int> st, st1, st2; set<int> stres; string s, s1, s2, s3, s4; vector<int> v[200050], vnode, vans, v3; vector<pair<int, int> > vv, vv1, adj, v1, v2; vector<pair<int, pair<int, int> > > vvv; priority_queue<int> q; map<int, int> mp; multiset<int>::iterator it, it1, it2; int voyel(char c) { if (c == a || c == e || c == i || c == o || c == u || c == y ) return 1; return 0; } int up[200005][20]; void solve() { int i, j; up[m + 1][0] = -1; for (i = 1; i <= m; i++) { int nxtt = nxt[b[i]]; int idx = lower_bound(v[nxtt].begin(), v[nxtt].end(), i) - v[nxtt].begin(); if (idx != v[nxtt].size()) { int idxb = v[nxtt][idx]; up[i][0] = idxb; } else up[i][0] = -1; } for (int j = 1; j < 20; j++) { for (i = 1; i <= m; i++) if (up[i][j - 1] != -1) up[i][j] = up[up[i][j - 1]][j - 1]; } for (i = 1; i <= m; i++) { int bsup = i; int x = n - 1; for (j = 19; j >= 0; j--) { if ((1 << j) <= x) { x -= (1 << j); if (bsup != -1) bsup = up[bsup][j]; } } if (bsup != -1) { dp[i] = bsup; } } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int i = 0, j = 0, x, y, z = 0, mx = 0, nb0 = 0, nb1 = 0, nbmax = 0, nbinf = 0, mm = 5e9, idx = 0, ok = 0, l, r, negatif = 0, positif = 0, q, d, res1 = 0; char c; cin >> n >> m >> q; for (i = 1; i <= n; i++) { cin >> a[i]; } for (i = 1; i <= n; i++) nxt[a[i]] = a[i + 1]; nxt[a[n]] = a[1]; for (i = 1; i <= m; i++) { cin >> b[i]; v[b[i]].push_back(i); } for (i = 1; i <= n; i++) { sort(v[i].begin(), v[i].end()); } memset(up, -1, sizeof(up)); solve(); idx = m + 1; mx = 5e9; for (i = m; i >= 1; i--) { if (dp[i]) mx = min(mx, dp[i]); ans[i] = mx; } s = ; while (q--) { cin >> x >> y; res = (ans[x] <= y); if (res != 0) s += 1 ; else s += 0 ; } cout << s; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( O3 ) #pragma GCC optimize( fast-math ) using namespace std; const int INF = 1e9; const long long INFll = 2e18; const int BASE1 = 179; const int BASE2 = 653; const long long MOD = 1e9 + 7; const int MAXN = 2e5; const long double PI = 3.1415926535; const long double EPS = 1e-10; void solve() { int n; cin >> n; vector<vector<char>> dop(n, vector<char>(n, * )); for (int i = 0; i < (n); i++) { for (int j = 0; j < (n); j++) { if (abs(i - n / 2) + abs(j - n / 2) <= n / 2) dop[i][j] = D ; } } for (int i = 0; i < (n); i++) { for (int j = 0; j < (n); j++) { cout << dop[i][j]; } cout << n ; } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(15); int t = 1; while (t--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n = 5, sum = 0; while (n--) { int a; cin >> a; sum += a; } if (sum == 0) { cout << -1 << endl; return 0; } cout << (sum % 5 == 0 ? sum / 5 : -1) << endl; }
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#include <bits/stdc++.h> std::map<std::string, std::string> opcodes; std::string next(std::string s) { std::string res = s; res[res.size() - 1]++; for (int i = (int)res.size() - 1; i >= 0; i--) { if (res[i] > f ) { res[i] = a ; res[i - 1]++; } } return res; } int check(std::string s) { if (s.size() == 1) return !!(s[0] == a ); std::string f = s.substr(0, 2); s.erase(0, 2); auto it = opcodes.find(f); if (it == opcodes.end()) return 0; s = it->second + s; return check(s); } int main() { std::ios_base::sync_with_stdio(0); int n, q; std::cin >> n >> q; std::string str = , fff, a, b; for (int i = 0; i < n; i++) str.push_back( a ); for (int i = 0; i < n; i++) fff.push_back( f ); for (int i = 0; i < q; i++) { std::cin >> a >> b; opcodes[a] = b; } int ans = 0; while (true) { ans += check(str); if (str == fff) break; else str = next(str); } std::cout << ans << std::endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int M = 1010; int n; vector<pair<int, int> > pt; vector<int> vx, vy; vector<int> gx[M], gy[M]; vector<tuple<int, int, int> > sh, sv; int pa[M], pb[M], ln, lm; vector<int> v[M]; bool used[M], used1[M]; vector<int> dx[M], dy[M]; bool dfs(int p) { used[p] = true; for (int i : v[p]) { if (pb[i] == -1 || (!used[pb[i]] && dfs(pb[i]))) { pa[p] = i; pb[i] = p; return true; } } return false; } void dfs_set(int p) { used[p] = true; for (int i : v[p]) { used1[i] = true; if (pb[i] != -1 && !used[pb[i]]) dfs_set(pb[i]); } } void kuhn() { memset(pa, -1, sizeof(pa)); memset(pb, -1, sizeof(pb)); for (int i = 0; i < ln; i++) { memset(used, 0, sizeof(used)); if (dfs(i)) continue; } memset(used, 0, sizeof(used)); memset(used1, 0, sizeof(used1)); for (int i = 0; i < ln; i++) if (pa[i] == -1) dfs_set(i); for (int i = 0; i < ln; i++) used[i] = (!used[i]); } int main() { ios::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; vx.push_back(x); vy.push_back(y); pt.push_back(make_pair(x, y)); } sort(vx.begin(), vx.end()); vx.resize(unique(vx.begin(), vx.end()) - vx.begin()); sort(vy.begin(), vy.end()); vy.resize(unique(vy.begin(), vy.end()) - vy.begin()); for (int i = 0; i < n; i++) { pt[i].first = lower_bound(vx.begin(), vx.end(), pt[i].first) - vx.begin(); pt[i].second = lower_bound(vy.begin(), vy.end(), pt[i].second) - vy.begin(); } for (int i = 0; i < n; i++) { gx[pt[i].first].push_back(pt[i].second); gy[pt[i].second].push_back(pt[i].first); } for (int i = 0; i < n; i++) sort(gx[i].begin(), gx[i].end()); for (int i = 0; i < n; i++) sort(gy[i].begin(), gy[i].end()); for (int y = 0; y < n; y++) if ((int)gy[y].size() > 1) for (int i = 0; i < (int)gy[y].size() - 1; i++) sh.push_back(make_tuple(gy[y][i], gy[y][i + 1], y)); for (int x = 0; x < n; x++) if ((int)gx[x].size() > 1) for (int i = 0; i < (int)gx[x].size() - 1; i++) sv.push_back(make_tuple(gx[x][i], gx[x][i + 1], x)); sort(sh.begin(), sh.end()); sort(sv.begin(), sv.end()); ln = sh.size(); lm = sv.size(); for (int i = 0; i < ln; i++) for (int j = 0; j < lm; j++) { if (!(get<0>(sh[i]) < get<2>(sv[j]) && get<2>(sv[j]) < get<1>(sh[i]))) continue; if (!(get<0>(sv[j]) < get<2>(sh[i]) && get<2>(sh[i]) < get<1>(sv[j]))) continue; v[i].push_back(j); } kuhn(); for (int y = 0; y < n; y++) if ((int)gy[y].size() >= 1) dy[y].push_back(gy[y][0]); for (int x = 0; x < n; x++) if ((int)gx[x].size() >= 1) dx[x].push_back(gx[x][0]); for (int i = 0; i < ln; i++) if (used[i]) { dy[get<2>(sh[i])].push_back(get<0>(sh[i])); dy[get<2>(sh[i])].push_back(get<1>(sh[i])); } for (int i = 0; i < lm; i++) if (used1[i]) { dx[get<2>(sv[i])].push_back(get<0>(sv[i])); dx[get<2>(sv[i])].push_back(get<1>(sv[i])); } for (int y = 0; y < n; y++) if ((int)gy[y].size() >= 1) dy[y].push_back(gy[y].back()); for (int x = 0; x < n; x++) if ((int)gx[x].size() >= 1) dx[x].push_back(gx[x].back()); int ans = 0; for (int y = 0; y < n; y++) ans += (int)dy[y].size(); ans /= 2; cout << ans << n ; for (int y = 0; y < n; y++) for (int i = 0; i < (int)dy[y].size(); i += 2) cout << vx[dy[y][i]] << << vy[y] << << vx[dy[y][i + 1]] << << vy[y] << n ; ans = 0; for (int x = 0; x < n; x++) ans += (int)dx[x].size(); ans /= 2; cout << ans << n ; for (int x = 0; x < n; x++) for (int i = 0; i < (int)dx[x].size(); i += 2) cout << vx[x] << << vy[dx[x][i]] << << vx[x] << << vy[dx[x][i + 1]] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e13; const int MAGIC = 3500000; long long add(long long x, long long y) { return (x + y) % MOD; } long long mul(long long x, long long y) { long long coef = (long double)(x)*y / MOD + 0.5; long long ret = x * y - coef * MOD; ret += ret < 0 ? MOD : 0; return ret; } struct mat { long long dat[2][2]; mat() { memset(dat, 0, sizeof(dat)); } } I, J; mat operator*(const mat& A, const mat& B) { mat ret; for (int i = 0; i < (int)(2); i++) for (int j = 0; j < (int)(2); j++) ret.dat[i][j] = add(mul(A.dat[i][0], B.dat[0][j]), mul(A.dat[i][1], B.dat[1][j])); return ret; } void init() { I.dat[0][0] = I.dat[1][1] = 1; J.dat[1][0] = J.dat[0][1] = J.dat[1][1] = 1; } long long calc(long long pos) { mat ans = I, cur = J; while (pos > 0) { if (pos & 1) ans = ans * cur; cur = cur * cur; pos >>= 1; } return ans.dat[1][0]; } long long pw[14], cyc[14]; long long X; int main() { init(); scanf( %lld , &X); pw[0] = 1; for (int i = 1; i <= (int)(13); i++) pw[i] = 10 * pw[i - 1]; cyc[0] = 1; cyc[1] = 60; cyc[2] = 300; cyc[3] = 1500; for (int i = 4; i <= 13; i++) cyc[i] = 10 * cyc[i - 1]; vector<long long> occ, nocc; occ.push_back(0); for (int i = 1; i <= (int)(13); i++) { int wt = cyc[i] / cyc[i - 1]; nocc.clear(); for (int j = 0; j < (int)(occ.size()); j++) for (int k = 0; k < (int)(wt); k++) if (calc(occ[j] + k * cyc[i - 1]) % pw[i] == X % pw[i]) nocc.push_back(occ[j] + k * cyc[i - 1]); occ = nocc; } sort(occ.begin(), occ.end()); printf( %lld n , occ.empty() ? -1 : occ[0]); return 0; }
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/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_OSERDES_MSG(OQ, CLK, CLKDIV, DI, OCE, SR);
output OQ;
input CLK, CLKDIV;
input [7:0] DI;
input OCE, SR;
wire SHIFT1, SHIFT2;
OSERDES OSERDES_inst1 (
.OQ(OQ), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(CLK), // 1-bit clock input
.CLKDIV(CLKDIV), // 1-bit divided clock input
.D1(DI[7]), // 1-bit parallel data input
.D2(DI[6]), // 1-bit parallel data input
.D3(DI[5]), // 1-bit parallel data input
.D4(DI[4]), // 1-bit parallel data input
.D5(DI[3]), // 1-bit parallel data input
.D6(DI[2]), // 1-bit parallel data input
.OCE(OCE), // 1-bit clock enable input
.REV(1'b0), // 1-bit reverse SR input
.SHIFTIN1(SHIFT1), // 1-bit data expansion input
.SHIFTIN2(SHIFT2), // 1-bit data expansion input
.SR(SR), // 1-bit set/reset input
.T1(), // 1-bit parallel 3-state input
.T2(), // 1-bit parallel 3-state input
.T3(), // 1-bit parallel 3-state input
.T4(), // 1-bit parallel 3-state input
.TCE(1'b1) // 1-bit 3-state signal clock enable input
);
defparam OSERDES_inst1.DATA_RATE_OQ = "DDR";
defparam OSERDES_inst1.DATA_RATE_TQ = "DDR";
defparam OSERDES_inst1.DATA_WIDTH = 8;
defparam OSERDES_inst1.SERDES_MODE = "MASTER";
defparam OSERDES_inst1.TRISTATE_WIDTH = 1;
OSERDES OSERDES_inst2 (
.OQ(), // 1-bit data path output
.SHIFTOUT1(SHIFT1), // 1-bit data expansion output
.SHIFTOUT2(SHIFT2), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(CLK), // 1-bit clock input
.CLKDIV(CLKDIV), // 1-bit divided clock input
.D1(), // 1-bit parallel data input
.D2(), // 1-bit parallel data input
.D3(DI[1]), // 1-bit parallel data input
.D4(DI[0]), // 1-bit parallel data input
.D5(), // 1-bit parallel data input
.D6(), // 1-bit parallel data input
.OCE(OCE), // 1-bit clock enable input
.REV(1'b0), // 1-bit reverse SR input
.SHIFTIN1(), // 1-bit data expansion input
.SHIFTIN2(), // 1-bit data expansion input
.SR(SR), // 1-bit set/reset input
.T1(), // 1-bit parallel 3-state input
.T2(), // 1-bit parallel 3-state input
.T3(), // 1-bit parallel 3-state input
.T4(), // 1-bit parallel 3-state input
.TCE(1'b1) // 1-bit 3-state signal clock enable input
);
defparam OSERDES_inst2.DATA_RATE_OQ = "DDR";
defparam OSERDES_inst2.DATA_RATE_TQ = "DDR";
defparam OSERDES_inst2.DATA_WIDTH = 8;
defparam OSERDES_inst2.SERDES_MODE = "SLAVE";
defparam OSERDES_inst2.TRISTATE_WIDTH = 1;
endmodule
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#include <bits/stdc++.h> using namespace std; vector<long long> ans; long long gcd(long long x, long long y) { while (true) { if (x == y) return x; if (x < y) { long long k = (y - 1) / x; ans.push_back(-k); y -= k * x; } else { long long k = (x - 1) / y; ans.push_back(k); x -= k * y; } } } int main() { long long x, y; cin >> x >> y; if (gcd(x, y) != 1) { puts( Impossible ); return 0; } for (int i = 0; i < ans.size(); i++) { printf( %I64d%c , abs(ans[i]), ans[i] > 0 ? A : B ); } return 0; }
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#include <bits/stdc++.h> using namespace std; inline int qr() { int f = 0, fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fu = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + c - 48; c = getchar(); } return f * fu; } const int N = 2e5 + 10; int a[N], n, k, T; pair<int, int> b[N]; int main() { T = qr(); while (T--) { n = qr(), k = qr(); for (register int i = 1; i <= n; ++i) a[i] = qr(); for (register int i = 1; i <= n; ++i) qr(); sort(a + 1, a + n + 1); int m = 0; for (register int i = 1; i <= n; ++i) { b[++m] = {a[i], 0}; int j = i; while (a[j] == a[i]) b[m].second++, j++; i = j - 1; } for (register int i = 1; i <= m; ++i) b[i].second += b[i - 1].second; if (k * 2 >= a[n] - a[1]) { printf( %d n , n); continue; } vector<int> st(m + 1); int ans = 0; for (int i = 1, j = 1; i <= m; i++) { while (b[i].first - b[j].first > k) j++; st[i] = max(st[i - 1], b[i].second - b[j - 1].second); ans = max(ans, b[i].second - b[j - 1].second + st[j - 1]); } printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k; int main() { cin >> n >> k; if (k >= (n * (n - 1)) / 2) cout << no solution ; else { for (int i = 0; i < n; ++i) cout << 0 << << i << n ; } return 0; }
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