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#include <bits/stdc++.h> using namespace std; int n, m, st, ed, i, j, ep = 1, h[1005]; long long d[1005][1005], dis[1005]; queue<int> q; struct node { int y, ne, v; } e[1000005]; void add(int a, int b, int v) { e[ep].y = b; e[ep].v = v; e[ep].ne = h[a]; h[a] = ep; ep++; } int main() { scanf( %d%d , &n, &m); scanf( %d%d , &st, &ed); for (i = 1; i <= m; i++) { int a, b, c; scanf( %d%d%d , &a, &b, &c); add(a, b, c); add(b, a, c); } memset(d, 0x3f, sizeof(d)); for (i = 1; i <= n; i++) { d[i][i] = 0; q.push(i); while (!q.empty()) { int s = q.front(); q.pop(); for (j = h[s]; j; j = e[j].ne) { if (d[i][s] + e[j].v < d[i][e[j].y]) { d[i][e[j].y] = d[i][s] + e[j].v; q.push(e[j].y); } } } } memset(h, 0, sizeof(h)); ep = 1; for (i = 1; i <= n; i++) { int a, b; scanf( %d%d , &a, &b); for (j = 1; j <= n; j++) if (d[i][j] <= a && i != j) add(i, j, b); } memset(dis, 0x3f, sizeof(dis)); dis[st] = 0; q.push(st); while (!q.empty()) { int s = q.front(); q.pop(); for (i = h[s]; i; i = e[i].ne) { if (dis[s] + e[i].v < dis[e[i].y]) { dis[e[i].y] = dis[s] + e[i].v; q.push(e[i].y); } } } if (dis[ed] < (1LL << 60)) printf( %I64d n , dis[ed]); else puts( -1 ); }
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#include <bits/stdc++.h> using namespace std; int a[111111], b[111111]; vector<int> id[111111]; int main() { int N, M; cin >> N >> M; for (int i = 1; i <= N; i++) id[i].clear(); for (int i = 0; i < M; i++) scanf( %d , a + i); long long tot = 0; for (int i = 1; i < M; i++) { if (a[i] == a[i - 1]) continue; id[a[i]].push_back(a[i - 1]); id[a[i - 1]].push_back(a[i]); tot += abs(a[i] - a[i - 1]); } long long d = 0; for (int i = 1; i <= N; i++) { sort(id[i].begin(), id[i].end()); long long s = 0; int k = id[i].size() / 2; for (int j = 0; j < id[i].size(); j++) s += abs(id[i][j] - id[i][k]) - abs(id[i][j] - i); if (d > s) d = s; } cout << tot + d << endl; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen_ds.v
// Version : 1.7
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen_ds (sys_clk_p, sys_clk_n);
output sys_clk_p;
output sys_clk_n;
parameter offset = 0;
parameter halfcycle = 500;
sys_clk_gen #(
.offset( offset ),
.halfcycle( halfcycle )
)
clk_gen (
.sys_clk(sys_clk_p)
);
assign sys_clk_n = !sys_clk_p;
endmodule // sys_clk_gen_ds
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History: 1.2 11/8/2010 Removed unused signals.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
wire COutb,COutd;
reg COuta,COutc;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
{COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
{COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// calculate how many buf still available
//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr;
assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; bool isPrime(int x) { for (int i = 2; i * i <= x; i++) if (x % i == 0) return false; return true; } int main() { cin >> n; for (int i = (1); i <= (1000); i++) if (!isPrime(n * i + 1)) { cout << i; return 0; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, CountDog[400]; char x[100005]; int main() { scanf( %d , &n); if (n == 1) { printf( Yes ); return 0; } for (int i = 1; i <= n; i++) { cin >> x[i]; CountDog[x[i]]++; } for (int i = 1; i <= n; i++) if (CountDog[x[i]] >= 2) { printf( Yes ); return 0; } printf( No ); }
|
#include <bits/stdc++.h> using namespace std; vector<char> sequ; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; long long num; cin >> n; vector<long long> a(n); vector<long long> b(n); for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } if (n == 1 && a[0] == b[0]) { cout << SMALL n0 n ; return 0; } if (n == 1) { cout << IMPOSSIBLE n ; return 0; } long long pep_op = 0, rev_op = 0; if (n == 2) { long long a0 = a[0], a1 = a[1], b0 = b[0], b1 = b[1]; if (a0 > a1) { swap(a0, a1); } while (1) { if ((a0 == b0 && a1 == b1) || (a0 == b1 && a1 == b0)) { if (a[0] != a0) { rev_op++; sequ.push_back( R ); } if (pep_op > 200000) cout << BIG n << pep_op << n ; else { cout << SMALL n << pep_op + rev_op << n ; int sz = sequ.size(); for (int i = sz - 1; i >= 0; i--) cout << sequ[i]; cout << n ; } return 0; } if (b0 > b1) { swap(b0, b1); sequ.push_back( R ); rev_op++; } if (a0 > b0 || a1 > b1) { cout << IMPOSSIBLE n ; return 0; } long long temp = (b1 - max(b0, a1)) % b0; long long pref = (b1 - max(b0, a1)) / b0; pep_op = pref + pep_op; if (pep_op <= 200000) { while (pref--) sequ.push_back( P ); } b1 = temp + max(b0, a1); if (b0 + b1 > a0 + a1) { long long temp1 = b0; b0 = b1 - b0; b1 = temp1; sequ.push_back( P ); sequ.push_back( R ); pep_op++; rev_op++; } } return 0; } while (b[0] + b[n - 1] > a[0] + a[n - 1]) { if (b[1] != b[0]) { bool order = true; if (b[1] > b[0]) { for (int i = 1; i < n; i++) { if (b[i] <= b[i - 1]) { order = false; break; } } } else if (b[0] > b[1]) { reverse(b.begin(), b.end()); for (int i = 1; i < n; i++) { if (b[i] <= b[i - 1]) { order = false; break; } } if (order == true) { sequ.push_back( R ); rev_op++; } } if (order == true) { for (int i = n - 1; i > 0; i--) b[i] = b[i] - b[i - 1]; sequ.push_back( P ); pep_op++; } else break; } else break; } int count = 0; int rcount = 0; for (int i = 0; i < n; i++) { if (a[i] == b[i]) count++; } for (int i = 0, j = n - 1; i < n; i++, j--) { if (a[i] == b[j]) rcount++; } if (rcount == n && count != n) { sequ.push_back( R ); rev_op++; } if (count == n || rcount == n) { if (pep_op <= 200000) { cout << SMALL n << pep_op + rev_op << n ; int sz = sequ.size(); for (int i = sz - 1; i >= 0; i--) cout << sequ[i]; cout << n ; } else cout << BIG n << pep_op << n ; } else { cout << IMPOSSIBLE n ; } return 0; }
|
//-----------------------------------------------------------------------------
//-- Generador de tonos de 1Khz, 2Khz, 3Khz y 4Khz
//-- (C) BQ. August 2015. Written by Juan Gonzalez
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
//-- Incluir las constantes del modulo del divisor
`include "divider.vh"
//-- Parameteros:
//-- clk: Reloj de entrada de la placa iCEstick
//-- data: Valor del contador de segundos, a sacar por los leds de la iCEstick
module tones(input wire clk, output wire ch0, ch1, ch2, ch3);
//-- Parametro del divisor. Fijarlo a 1Hz
//-- Se define como parametro para poder modificarlo desde el testbench
//-- para hacer pruebas
parameter F0 = `F_1KHz;
parameter F1 = `F_2KHz;
parameter F2 = `F_3KHz;
parameter F3 = `F_4KHz;
//-- Generador de tono 0
divider #(F0)
CH0 (
.clk_in(clk),
.clk_out(ch0)
);
//-- Generador de tono 1
divider #(F1)
CH1 (
.clk_in(clk),
.clk_out(ch1)
);
//-- Generador de tono 2
divider #(F2)
CH2 (
.clk_in(clk),
.clk_out(ch2)
);
//-- Generador de tono 3
divider #(F3)
CH3 (
.clk_in(clk),
.clk_out(ch3)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:18:56 06/07/2015
// Design Name: UART_IP
// Module Name: /home/sadique/Work/Verilog/Spartan6/USB-uart/uart_test.v
// Project Name: USB-uart
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_IP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart_test;
// Inputs
reg sys_clk;
reg RTS;
reg RX;
wire [7:0] RxD_par;
wire RxD_start;
// Outputs
wire CTS;
wire TX;
wire [7:0] TxD_par;
wire TxD_ready;
// Instantiate the Unit Under Test (UUT)
UART_IP uut (
.sys_clk(sys_clk),
.CTS(CTS),
.RTS(RTS),
.TX(TX),
.RX(RX),
.TxD_par(TxD_par),
.TxD_ready(TxD_ready),
.RxD_par(RxD_par),
.RxD_start(RxD_start)
);
// Loop parallel ouput as input
assign RxD_par = TxD_par;
assign RxD_start = TxD_ready;
initial begin
// Initialize Inputs
sys_clk = 0;
RTS = 0; // active low
RX = 1;
//RxD_par = 0;
//RxD_start = 0;
// Wait 100 ns for global reset to finish
#5000;
// Add stimulus here
#0 RX = 0; //Start bit
#8680 RX = 0; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 0; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#20000
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
end
always begin
#2.5 sys_clk <= !sys_clk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; set<int> d; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t, n, a, k = 0; cin >> t >> n; int x[200] = {}; for (int i = 1; i <= t; ++i) { cin >> a; if (x[a] >= 1) continue; else { x[a] += 1; d.insert(i); } } if (d.size() < n) cout << NO n ; else { cout << YES n ; for (auto i : d) { k += 1; cout << i << ; if (k == n) break; } } return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block is responsible determine the appropriate burst count based on the
master length register as well as the buffer watermark and eop/early termination
conditions.
Within this block is a burst counter which is used to control when the next burst
is started. This down counter is loaded with whatever burst count is presented
to the fabric and counts down when waitrequest is deasserted. When it reaches 1
it can either start another burst or reach 0. When the counter reaches 0 this is
considered the idle state which can occur if there is not enough data buffered to
start another burst.
During write bursts the address and burst count must be held for all the beats.
This block will register the address and burst count to keep these signals
held constant to the fabric. This block will not begin a burst until enough
data has been buffered to start the burst so it will assert the stall signal
to keep the write master from advancing to the next word (just like waitrequest)
and will filter the write signal accordingly.
Revision History:
1.0 Initial version
1.1 Added sw_stop and stopped so that the write master will not be
stopped in the middle of a burst write transaction.
1.2 Added the sink ready and valid signals to this block and qualified the
eop signal with them.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_burst_control (
clk,
reset,
sw_reset,
sw_stop,
length,
eop_enabled,
eop,
ready,
valid,
early_termination,
address_in,
write_in,
max_burst_count,
write_fifo_used,
waitrequest,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
address_out,
write_out,
burst_count,
stall,
reset_taken,
stopped
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE = 4;
parameter WORD_SIZE_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter WRITE_FIFO_USED_WIDTH = 5;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when the master supports programmable bursting.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input clk;
input reset;
input sw_reset;
input sw_stop;
input [LENGTH_WIDTH-1:0] length;
input eop_enabled;
input eop;
input ready;
input valid;
input early_termination;
input [ADDRESS_WIDTH-1:0] address_in;
input write_in;
input [BURST_COUNT_WIDTH-1:0] max_burst_count; // will be either a hardcoded input or programmable
input [WRITE_FIFO_USED_WIDTH:0] write_fifo_used; // using the fifo full MSB as well
input waitrequest; // this needs to be the waitrequest from the fabric and not the byte enable generator since partial transfers count as burst beats
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [ADDRESS_WIDTH-1:0] address_out;
output wire write_out;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
output wire stall; // need to issue a stall if there isn't enough data buffered to start a burst
output wire reset_taken; // if a reset occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
output wire stopped; // if a stop occurs in the middle of a burst larger than 1 then the write master needs to know that the burst hasn't completed yet
reg [ADDRESS_WIDTH-1:0] address_d1;
reg [BURST_COUNT_WIDTH-1:0] burst_counter; // interal statemachine register
wire idle_state;
wire decrement_burst_counter;
wire ready_during_idle_state; // when there is enough data buffered to start up the burst counter state machine again
wire ready_for_quick_burst; // when there is enough data bufferred to start another burst immediately
wire burst_begin_from_idle_state;
wire burst_begin_quickly; // start another burst immediately after the previous burst completes
wire burst_begin;
wire burst_of_one_enable; // asserted when partial word accesses are occuring or the last early termination word is being written out
wire [BURST_COUNT_WIDTH-1:0] short_length_burst;
wire [BURST_COUNT_WIDTH-1:0] short_packet_burst;
wire short_length_burst_enable;
wire short_early_termination_burst_enable;
wire short_packet_burst_enable;
wire [3:0] mux_select;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count;
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count_d1;
reg packet_complete;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_complete <= 0;
end
else
begin
if ((packet_complete == 1) & (write_fifo_used == 0))
begin
packet_complete <= 0;
end
else if ((eop == 1) & (ready == 1) & (valid == 1))
begin
packet_complete <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_d1 <= 0;
end
else if (burst_begin == 1)
begin
address_d1 <= (burst_begin_quickly == 1)? (address_in + WORD_SIZE) : address_in;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
burst_counter <= 0;
end
else
if ((burst_begin == 1) & (sw_reset == 0) & (sw_stop == 0)) // for reset and stop we need to let the burst complete so the fabric doesn't lock up
begin
burst_counter <= internal_burst_count;
end
else if (decrement_burst_counter == 1)
begin
burst_counter <= burst_counter - 1'b1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
internal_burst_count_d1 <= 0;
end
else if (burst_begin == 1)
begin
internal_burst_count_d1 <= internal_burst_count;
end
end
// state machine status and control
assign idle_state = (burst_counter == 0); // any time idle_state is set then there is no burst underway
assign decrement_burst_counter = (idle_state == 0) & (waitrequest == 0);
// control for all the various cases that a burst of one beat needs to be posted
assign burst_offset = address_in[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | (early_termination == 1) |
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 1) & (burst_offset != 0)) | // need to make sure bursts start on burst boundaries
((BURST_WRAPPING_SUPPORT == 1) & (idle_state == 0) & (burst_offset != (max_burst_count - 1))); // need to make sure bursts start on burst boundaries
assign short_length_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 0) & (burst_of_one_enable == 0);
assign short_early_termination_burst_enable = ((length >> WORD_SIZE_LOG2) < max_burst_count) & (eop_enabled == 1) & (burst_of_one_enable == 0); // trim back the burst count regardless if there is enough data buffered for a full burst
assign short_packet_burst_enable = (short_early_termination_burst_enable == 0) & (eop_enabled == 1) & (packet_complete == 1) & (write_fifo_used < max_burst_count) & (burst_of_one_enable == 0);
// various burst amounts that are not the max burst count or 1 that feed the internal_burst_count mux. short_length_burst is used when short_length_burst_enable or short_early_termination_burst_enable is asserted.
generate
if (BURST_COUNT_WIDTH > 1) begin
assign short_length_burst = (length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}};
assign short_packet_burst = (write_fifo_used & {(BURST_COUNT_WIDTH-1){1'b1}});
end
else begin
assign short_length_burst = 1'b1;
assign short_packet_burst = 1'b1;
end
endgenerate
// since the write master may not have enough data buffered in the FIFO to start a burst the FIFO fill level must be checked before starting another burst
assign ready_during_idle_state = (burst_of_one_enable == 1) | // burst of one is only enabled when there is data in the write fifo so write_fifo_used doesn't need to be checked in this case
((write_fifo_used >= short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used >= short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used >= short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used >= max_burst_count);
// same as ready_during_idle_state only we need to make sure there is more data in the fifo than the burst being posted (since the FIFO is in the middle of being popped)
assign ready_for_quick_burst = (length >= (max_burst_count << WORD_SIZE_LOG2)) & (burst_of_one_enable == 0) & // address and length lags by one clock cycle so this will let the state machine catch up
( ((write_fifo_used > short_length_burst) & (short_length_burst_enable == 1)) |
((write_fifo_used > short_length_burst) & (short_early_termination_burst_enable == 1)) |
((write_fifo_used > short_packet_burst) & (short_packet_burst_enable == 1)) |
(write_fifo_used > max_burst_count) );
// burst begin signals used to start up the burst counter state machine
assign burst_begin_from_idle_state = (write_in == 1) & (idle_state == 1) & (ready_during_idle_state == 1); // start the state machine up again
assign burst_begin_quickly = (write_in == 1) & (burst_counter == 1) & (waitrequest == 0) & (ready_for_quick_burst == 1); // enough data is buffered to start another burst immediately after the current burst
assign burst_begin = (burst_begin_quickly == 1) | (burst_begin_from_idle_state == 1);
assign mux_select = {short_packet_burst_enable, short_early_termination_burst_enable, short_length_burst_enable, burst_of_one_enable};
// one-hot mux that selects the appropriate burst count to present to the fabric
always @ (short_length_burst or short_packet_burst or max_burst_count or mux_select)
begin
case (mux_select)
4'b0001 : internal_burst_count = 1;
4'b0010 : internal_burst_count = short_length_burst;
4'b0100 : internal_burst_count = short_length_burst;
4'b1000 : internal_burst_count = short_packet_burst;
default : internal_burst_count = max_burst_count;
endcase
end
generate
if (BURST_ENABLE == 1)
begin
// outputs that need to be held constant throughout the entire burst transaction
assign address_out = address_d1;
assign burst_count = internal_burst_count_d1;
assign write_out = (idle_state == 0);
assign stall = (idle_state == 1);
assign reset_taken = (sw_reset == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct reset timing
assign stopped = (sw_stop == 1) & (idle_state == 1); // for bursts of 1 the write master logic will handle the correct stop timing
end
else
begin
assign address_out = address_in;
assign burst_count = 1; // this will be stubbed at the top level
assign write_out = write_in;
assign stall = 0;
assign reset_taken = sw_reset;
assign stopped = sw_stop;
end
endgenerate
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "setup.v"
module gen_capabilities(
output [31:0] capabilities
);
wire memorycard;
wire ac97;
wire pfpu;
wire tmu;
wire ethernet;
wire fmlmeter;
wire videoin;
wire midi;
wire dmx;
wire ir;
wire usb;
wire memtest;
assign capabilities = {
20'd0,
memtest,
usb,
ir,
dmx,
midi,
videoin,
fmlmeter,
ethernet,
tmu,
pfpu,
ac97,
memorycard
};
`ifdef ENABLE_MEMORYCARD
assign memorycard = 1'b1;
`else
assign memorycard = 1'b0;
`endif
`ifdef ENABLE_AC97
assign ac97 = 1'b1;
`else
assign ac97 = 1'b0;
`endif
`ifdef ENABLE_PFPU
assign pfpu = 1'b1;
`else
assign pfpu = 1'b0;
`endif
`ifdef ENABLE_TMU
assign tmu = 1'b1;
`else
assign tmu = 1'b0;
`endif
`ifdef ENABLE_ETHERNET
assign ethernet = 1'b1;
`else
assign ethernet = 1'b0;
`endif
`ifdef ENABLE_FMLMETER
assign fmlmeter = 1'b1;
`else
assign fmlmeter = 1'b0;
`endif
`ifdef ENABLE_VIDEOIN
assign videoin = 1'b1;
`else
assign videoin = 1'b0;
`endif
`ifdef ENABLE_MIDI
assign midi = 1'b1;
`else
assign midi = 1'b0;
`endif
`ifdef ENABLE_DMX
assign dmx = 1'b1;
`else
assign dmx = 1'b0;
`endif
`ifdef ENABLE_IR
assign ir = 1'b1;
`else
assign ir = 1'b0;
`endif
`ifdef ENABLE_USB
assign usb = 1'b1;
`else
assign usb = 1'b0;
`endif
`ifdef ENABLE_MEMTEST
assign memtest = 1'b1;
`else
assign memtest = 1'b0;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; using INT = long long; const int NN = 111; string tar; string s[NN]; int n; void dfs(int len) { if (!len) { for (int i = 1; i <= n; i++) { for (int j = 0; j < s[i].length(); j++) { int f = 1; for (int k = j; k < s[i].length(); k++) { if (k - j == tar.length()) { puts( YES ); exit(0); } if (tar[k - j] != s[i][k]) { f = 0; break; } } if (f) dfs(s[i].length() - j); } } return; } for (int i = 1; i <= n; i++) { int j = 0; for (; j < s[i].length(); j++) { if (tar[len + j] != s[i][j]) break; } if (len + j == tar.length()) { puts( YES ); exit(0); } if (j == s[i].length()) dfs(len + j); } } int main() { cin >> tar; cin >> n; for (int i = 1; i <= n; i++) cin >> s[i]; dfs(0); puts( NO ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_4_V
`define SKY130_FD_SC_MS__DFSTP_4_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfstp_4 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfstp_4 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; char str[25]; char times[6] = {4, 5, 6, 3, 2, 1}; int main() { scanf( %s , str); int len = strlen(str); char seat = str[len - 1]; long long rows = 0; for (int i = 0; i < len - 1; i++) { rows = rows * 10; rows += str[i] - 0 ; } long long sec; if (rows % 4 != 0) sec = rows / 4 * 16; else sec = (rows - 1) / 4 * 16; int tmp = rows % 4; if (!tmp) tmp = 4; if (tmp > 2) tmp -= 2; sec += (tmp - 1) * 7; sec += times[seat - a ]; printf( %I64d n , sec); return 0; }
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_r_channel.v
//
// Description:
// Read data channel module to buffer read data from MC, ignore
// extra data in case of BL8 and send the data to AXI.
// The MC will send out the read data as it is ready and it has to be
// accepted. The read data FIFO in the axi_mc_r_channel module will buffer
// the data before being sent to AXI. The address channel module will
// send the transaction information for every command that is sent to the
// MC. The transaction information will be buffered in a transaction FIFO.
// Based on the transaction FIFO information data will be ignored in
// BL8 mode and the last signal to the AXI will be asserted.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_mc_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// axi addr width
parameter integer C_AXI_ADDR_WIDTH = 32,
// Number of memory clocks per fabric clock
// = 2 for DDR2 or low frequency designs
// = 4 for DDR3 or high frequency designs
parameter C_MC_nCK_PER_CLK = 2,
// memory controller burst mode,
// values "8", "4" & "OTF"
parameter C_MC_BURST_MODE = "8"
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire [C_ID_WIDTH-1:0] rid ,
output wire [C_DATA_WIDTH-1:0] rdata ,
output wire [1:0] rresp ,
output wire rlast ,
output wire rvalid ,
input wire rready ,
input wire [C_DATA_WIDTH-1:0] mc_app_rd_data ,
input wire mc_app_rd_valid ,
input wire mc_app_rd_last ,
input wire mc_app_ecc_multiple_err ,
// Connections to/from axi_mc_ar_channel module
input wire r_push ,
output wire r_data_rdy ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast ,
input wire r_ignore_begin ,
input wire r_ignore_end
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 3+C_ID_WIDTH;
localparam P_DEPTH = 30;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH+1;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = (C_MC_BURST_LEN == 2)? 64 : 32;
localparam P_D_AWIDTH = (C_MC_BURST_LEN == 2)? 6: 5;
// AXI protocol responses:
localparam P_OKAY = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire done;
wire [C_ID_WIDTH+3-1:0] trans_in;
wire [C_ID_WIDTH+3-1:0] trans_out;
reg [C_ID_WIDTH+3-1:0] trans_buf_out_r1;
reg [C_ID_WIDTH+3-1:0] trans_buf_out_r;
wire tr_empty;
wire tr_rden;
reg [1:0] state;
wire [C_ID_WIDTH-1:0] rid_i;
wire assert_rlast;
wire ignore_begin;
wire ignore_end;
reg load_stage1;
wire load_stage2;
wire load_stage1_from_stage2;
wire rhandshake;
wire rlast_i;
wire r_valid_i;
wire [C_DATA_WIDTH:0] rd_data_fifo_in;
wire [C_DATA_WIDTH:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
reg rd_last_r;
wire fifo_rd_last;
wire trans_a_full;
wire trans_full;
reg r_ignore_begin_r;
reg r_ignore_end_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// localparam for 2 deep skid buffer
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign rresp = (rd_data_fifo_out[C_DATA_WIDTH] === 1) ? P_SLVERR : P_OKAY;
assign rid = rid_i;
assign rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign rlast = assert_rlast & ((~fifo_rd_last & ignore_end)
| (fifo_rd_last & ~ignore_end));
assign rvalid = ~rd_empty & ((~fifo_rd_last & ~ignore_begin)
| (fifo_rd_last & ~ignore_end ));
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(rvalid & rready) |
(((~fifo_rd_last & ignore_begin) | (fifo_rd_last & ignore_end )) & (~rd_empty));
// register for timing
always @(posedge clk) begin
r_ignore_begin_r <= r_ignore_begin;
r_ignore_end_r <= r_ignore_end;
end
assign trans_in[0] = r_ignore_end_r;
assign trans_in[1] = r_ignore_begin_r;
assign trans_in[2] = r_rlast;
assign trans_in[3+:C_ID_WIDTH] = r_arid;
always @(posedge clk) begin
if (reset) begin
rd_last_r <= 1'b0;
end else if (rhandshake) begin
rd_last_r <= ~rd_last_r;
end
end
assign fifo_rd_last = (C_MC_BURST_LEN == 1) ? 1'b1 : rd_last_r;
// rd data fifo
mig_7series_v4_0_axi_mc_fifo #
(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( mc_app_rd_valid ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {mc_app_ecc_multiple_err, mc_app_rd_data};
mig_7series_v4_0_axi_mc_fifo #
(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push ) ,
.rd_en ( tr_rden ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( trans_a_full) ,
.full ( trans_full ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign rid_i = trans_buf_out_r[3+:C_ID_WIDTH];
assign assert_rlast = trans_buf_out_r[2];
assign ignore_begin = trans_buf_out_r[1];
assign ignore_end = trans_buf_out_r[0];
assign done = fifo_rd_last & rhandshake;
assign fifo_full = (trans_a_full | trans_full) | (rd_a_full | rd_full);
assign r_data_rdy = ~fifo_full ;
// logic for 2 deep skid buffer for storing transaction data for timing
// loading the output of the buffer
always @(posedge clk) begin
if(load_stage1)
if(load_stage1_from_stage2)
trans_buf_out_r <= trans_buf_out_r1;
else
trans_buf_out_r <= trans_out;
end
// store data into the optional second stage
always @(posedge clk) begin
if(load_stage2)
trans_buf_out_r1 <= trans_out;
end
// condition to store data for the second stage
assign load_stage2 = ~tr_empty & state[1];
// Loading stage one conditions
always @ (*) begin
if( ((state == ZERO) && (~tr_empty)) ||
((state == ONE) && (~tr_empty) && (done)) ||
((state == TWO) && (done)))
load_stage1 = 1'b1;
else
load_stage1 = 1'b0;
end // always @ *
assign load_stage1_from_stage2 = (state == TWO);
always @(posedge clk)
begin
if(reset)
state <= ZERO;
else
case (state)
ZERO: if (~tr_empty) state <= ONE;
ONE: begin
if (done & tr_empty) state <= ZERO;
// if (~done & (~tr_empty)) state <= TWO;
else if (~done & (~tr_empty)) state <= TWO;
end
TWO: if (done) state <= ONE;
endcase
end
assign tr_rden = ((state == ZERO) || (state == ONE)) && (~tr_empty);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int M = 20; pair<int, int> dp[M][(1 << 10)]; int a[M], K, ten[M]; int Count(int st) { int rnt = 0; while (st) st &= st - 1, rnt++; return rnt; } pair<int, int> f(int pos, int st, int lead, int limit) { if (pos == -1) return Count(st) <= K ? pair<int, int>(0, 1) : pair<int, int>(0, 0); if (!limit && dp[pos][st].first != -1) return dp[pos][st]; int up = limit ? a[pos] : 9; pair<int, int> rnt = pair<int, int>(0, 0); for (int k = 0; k <= up; k++) { pair<int, int> p = f(pos - 1, k == 0 && lead ? 0 : st | (1 << k), k == 0 && lead, limit && k == up); rnt.first = (rnt.first + p.first + (long long)k * ten[pos] % MOD * p.second % MOD) % MOD; rnt.second = (rnt.second + p.second) % MOD; } if (!limit) dp[pos][st] = rnt; return rnt; } pair<int, int> Solve(long long n) { for (int i = 0; i < M; i++, n /= 10) a[i] = n % 10; return f(M - 1, 0, 1, 1); } int main() { for (int i = 0; i < M; i++) { ten[i] = i == 0 ? 1 : ten[i - 1] * 10ll % MOD; for (int j = 0; j < (1 << 10); j++) dp[i][j].first = -1; } long long l, r; scanf( %I64d%I64d%d , &l, &r, &K); pair<int, int> R = Solve(r), L = Solve(l - 1); printf( %d n , (R.first - L.first + MOD) % MOD); return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 9995 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w124,
w125,
w2000,
w1999,
w7996,
w9995;
assign w1 = i_data0;
assign w124 = w31 << 2;
assign w125 = w1 + w124;
assign w1999 = w2000 - w1;
assign w2000 = w125 << 4;
assign w31 = w32 - w1;
assign w32 = w1 << 5;
assign w7996 = w1999 << 2;
assign w9995 = w1999 + w7996;
assign o_data0 = w9995;
//multiplier_block area estimate = 7055.29440546471;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> inline int read() { int x = 0, f = 0; register char ch = getchar(); for (; ch < 48 || ch > 57; ch = getchar()) f |= ch == - ; for (; ch > 47 && ch < 58; ch = getchar()) x = (x << 1) + (x << 3) + (ch ^ 48); return f ? ~x + 1 : x; } using namespace std; int t[7005], l[7005], r[7005], x[7005], pos[7005][2], cnt; set<int> s; int main() { int n = read(), m = read(); for (int i = 0; i < m; ++i) { int k = read(); if (k == 1) t[++cnt] = read(), l[cnt] = read(), r[cnt] = read(), x[cnt] = read(); else { int lvl = read(); pos[lvl][1] = pos[lvl][0] = read(); s.clear(); for (int i = lvl; i < n; ++i) { int k = pos[i][0], j = 0, c = 0; for (; k; k >>= 1, ++j) c += k & 1; pos[i + 1][0] = pos[i][0] + j - (c == 1); k = pos[i][1], j = 0; for (; k; k >>= 1, ++j) ; pos[i + 1][1] = pos[i][1] + j; } for (int i = 1; i <= cnt; ++i) if (t[i] >= lvl && (l[i] <= pos[t[i]][0] && pos[t[i]][0] <= r[i] || l[i] <= pos[t[i]][1] && pos[t[i]][1] <= r[i] || pos[t[i]][0] <= l[i] && r[i] <= pos[t[i]][1])) s.insert(x[i]); printf( %d n , s.size()); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int t, a, b, c, d, k; cin >> t; while (t--) { cin >> a >> b >> c >> d >> k; int x = a / c; int y = b / d; if (a % c) x++; if (b % d) y++; if (x + y <= k) { cout << x << << k - x << endl; } else cout << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int w, b; int main() { for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { char s; cin >> s; if (s == Q ) { w += 9; } if (s == R ) { w += 5; } if (s == B ) { w += 3; } if (s == N ) { w += 3; } if (s == P ) { w += 1; } if (s == K ) { w += 0; } if (s == q ) { b += 9; } if (s == r ) { b += 5; } if (s == b ) { b += 3; } if (s == n ) { b += 3; } if (s == p ) { b += 1; } if (s == k ) { b += 0; } } } if (w > b) cout << White ; else if (w < b) cout << Black ; else cout << Draw ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_FUNCTIONAL_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlybuf4s25kapwr (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_FUNCTIONAL_V
|
`include "config.inc"
module gammaconv(
input clock,
input [4:0] gamma_config,
input in_wren,
input [`RAM_WIDTH-1:0] in_wraddr,
input [7:0] in_red,
input [7:0] in_green,
input [7:0] in_blue,
input in_starttrigger,
output reg wren,
output reg [`RAM_WIDTH-1:0] wraddr,
output reg [23:0] wrdata,
output reg starttrigger
);
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
gamma r(
.clock(clock),
.gamma_config(gamma_config),
.in(in_red),
.out(red)
);
gamma g(
.clock(clock),
.gamma_config(gamma_config),
.in(in_green),
.out(green)
);
gamma b(
.clock(clock),
.gamma_config(gamma_config),
.in(in_blue),
.out(blue)
);
reg wren_q;
reg [`RAM_WIDTH-1:0] wraddr_q;
reg starttrigger_q;
always @(posedge clock) begin
{ wren, wren_q } <= { wren_q, in_wren };
{ wraddr, wraddr_q } <= { wraddr_q, in_wraddr };
{ starttrigger, starttrigger_q } <= { starttrigger_q, in_starttrigger };
wrdata <= { red, green, blue };
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline char nc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline void read(int &x) { char c = nc(), b = 1; for (; !(c >= 0 && c <= 9 ); c = nc()) if (c == - ) b = -1; for (x = 0; c >= 0 && c <= 9 ; x = x * 10 + c - 0 , c = nc()) ; x *= b; } const int N = 55; const int M = 2505; struct edge { int u, v, w, f; int next; } G[M << 1]; int head[N], inum = 1; inline void add(int u, int v, int w, int f, int p) { G[p].u = u; G[p].v = v; G[p].w = w; G[p].f = f; G[p].next = head[u]; head[u] = p; } inline void link(int u, int v, int w, int f) { add(u, v, w, f, ++inum); add(v, u, -w, 0, ++inum); } int n, m, P; int S, T, Mincost; int Q[N * M], l, r; int dis[N], pre[N], ins[N]; inline bool SPFA() { for (int i = 1; i <= n; i++) dis[i] = 1 << 29, pre[i] = 0, ins[i] = 0; l = r = -1; Q[++r] = S, dis[S] = 0, ins[S] = 1; while (l < r) { int u = Q[++l]; ins[u] = 0; for (int p = head[u]; p; p = G[p].next) if (G[p].f && dis[G[p].v] > dis[u] + G[p].w) { dis[G[p].v] = dis[u] + G[p].w; pre[G[p].v] = p; if (!ins[G[p].v]) Q[++r] = G[p].v, ins[G[p].v] = 1; } } if (dis[T] == 1 << 29) return 0; Mincost += dis[T]; for (int p = pre[T]; p; p = pre[G[p].u]) G[p].f--, G[p ^ 1].f++; return 1; } int _, Qry[123456]; double Ans[123456]; int main() { int u, v, c, d; read(n); read(m); S = 1; T = n; for (int i = 1; i <= m; i++) read(u), read(v), read(d), c = 1, link(u, v, d, c); read(_); for (int i = 0; i < _; i++) read(Qry[i]); double ans = 1e20; int m = 0; for (int i = 0; i < _; i++) Ans[i] = 1e20; while (SPFA()) { m++; for (int i = 0; i < _; i++) Ans[i] = min(Ans[i], ((double)(Mincost + Qry[i])) / m); ans = min(ans, (double)(Mincost + P) / m); } for (int i = 0; i < _; i++) printf( %.10f n , Ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mn = 2e5 + 10; int bit[mn]; void update(int a, int b) { for (; a < mn; a += a & -a) bit[a] += b; } int query(int a) { int b = 0; for (; a; a -= a & -a) b += bit[a]; return b; } int a[mn], v[mn], n; void go() { int i; for (i = 0; i < n; i++) scanf( %d , a + i), a[i]++; for (i = 1; i <= n; i++) update(i, 1); for (i = 0; i < n; i++) { v[i] += query(a[i]) - 1; update(a[i], -1); } } int main() { int i; scanf( %d , &n); go(); go(); for (i = n - 1; i; i--) { if (v[i] >= n - i) v[i] -= n - i, v[i - 1]++; } v[0] %= n; for (i = 1; i <= n; i++) update(i, 1); for (i = 0; i < n; i++) { int cur = 0, tot = 0; for (int j = 1 << 17; j; j >>= 1) { if (cur + j > n) continue; if (tot + bit[cur + j] < v[i] + 1) cur += j, tot += bit[cur]; } printf( %d , cur); update(cur + 1, -1); } }
|
#include <bits/stdc++.h> using namespace std; int main() { double n, t, x = 1.000000011; scanf( %lf%lf , &n, &t); double res = n * pow(x, t); printf( %.12lf , res); return 0; }
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: YCbCr to RGB Color Doamin Converter.
// ( 10 Bits Resolution )
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Chen :| 05/09/05 :| Initial Revision
// --------------------------------------------------------------------
module YCbCr2RGB ( Red,Green,Blue,oDVAL,
iY,iCb,iCr,iDVAL,
iRESET,iCLK);
// Input
input [7:0] iY,iCb,iCr;
input iDVAL,iRESET,iCLK;
// Output
output [9:0] Red,Green,Blue;
output reg oDVAL;
// Internal Registers/Wires
reg [9:0] oRed,oGreen,oBlue;
reg [3:0] oDVAL_d;
reg [19:0] X_OUT,Y_OUT,Z_OUT;
wire [26:0] X,Y,Z;
assign Red = oRed;
assign Green= oGreen;
assign Blue = oBlue;
always@(posedge iCLK)
begin
if(iRESET)
begin
oDVAL<=0;
oDVAL_d<=0;
oRed<=0;
oGreen<=0;
oBlue<=0;
end
else
begin
// Red
if(X_OUT[19])
oRed<=0;
else if(X_OUT[18:0]>1023)
oRed<=1023;
else
oRed<=X_OUT[9:0];
// Green
if(Y_OUT[19])
oGreen<=0;
else if(Y_OUT[18:0]>1023)
oGreen<=1023;
else
oGreen<=Y_OUT[9:0];
// Blue
if(Z_OUT[19])
oBlue<=0;
else if(Z_OUT[18:0]>1023)
oBlue<=1023;
else
oBlue<=Z_OUT[9:0];
// Control
{oDVAL,oDVAL_d}<={oDVAL_d,iDVAL};
end
end
always@(posedge iCLK)
begin
if(iRESET)
begin
X_OUT<=0;
Y_OUT<=0;
Z_OUT<=0;
end
else
begin
X_OUT<=( X - 114131 ) >>7;
Y_OUT<=( Y + 69370 ) >>7;
Z_OUT<=( Z - 141787 ) >>7;
end
end
// Y 596, 0, 817
MAC_3 u0( iY, iCb, iCr,
17'h00254, 17'h00000, 17'h00331,
X, iRESET, iCLK);
// Cb 596, -200, -416
MAC_3 u1( iY, iCb, iCr,
17'h00254, 17'h3FF38, 17'h3FE60,
Y, iRESET, iCLK);
// Cr 596, 1033, 0
MAC_3 u2( iY, iCb, iCr,
17'h00254, 17'h00409, 17'h00000,
Z, iRESET, iCLK);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the add-compare
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules,
*/
//`include "acs.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_acs();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [3:0] new_pm; // Output signal npm
wire decision; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] brch_m1; // Input signal - bm1
reg [1:0] brch_m2; // Input signal - bm2
reg [3:0] path_m1; // Input signal - pm1
reg [3:0] path_m2; // Input signal - pm2
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
add_compare_select acs_cir (
// instance_name(signal name),
// Signal name can be the same as the instance name
new_pm,decision,path_m1,brch_m1,path_m2,brch_m2);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
path_m1 = 4'd0;
brch_m1 = 2'd0;
path_m2 = 4'd0;
brch_m2 = 2'd0;
// @t=1,
#1
path_m1 = 4'd0;
brch_m1 = 2'd1;
path_m2 = 4'd6;
brch_m2 = 2'd2;
// @t=2,
#1
path_m1 = 4'd7;
brch_m1 = 2'd2;
path_m2 = 4'd0;
brch_m2 = 2'd3;
// @t=3,
#1
path_m1 = 4'd14;
brch_m1 = 2'd1;
path_m2 = 4'd13;
brch_m2 = 2'd0;
// @t=4,
#1
path_m1 = 4'd9;
brch_m1 = 2'd3;
path_m2 = 4'd8;
brch_m2 = 2'd1;
// @t=5,
#1
path_m1 = 4'd15;
brch_m1 = 2'd1;
path_m2 = 4'd15;
brch_m2 = 2'd0;
// @t=6,
#1
path_m1 = 4'd15;
brch_m1 = 2'd1;
path_m2 = 4'd15;
brch_m2 = 2'd2;
// @t=7,
#1
path_m1 = 4'd13;
brch_m1 = 2'd3;
path_m2 = 4'd14;
brch_m2 = 2'd2;
// @t=8,
#1
path_m1 = 4'd14;
brch_m1 = 2'd3;
path_m2 = 4'd15;
brch_m2 = 2'd3;
// @t=9,
#1
path_m1 = 4'd15;
brch_m1 = 2'd3;
path_m2 = 4'd15;
brch_m2 = 2'd3;
// @t=10,
#1
path_m1 = 4'd16;
brch_m1 = 2'd8;
path_m2 = 4'd2;
brch_m2 = 2'd3;
// @t=11,
#1
path_m1 = 4'd12;
brch_m1 = 2'd2;
path_m2 = 4'd12;
brch_m2 = 2'd1;
// @t=12,
#1
path_m1 = 4'd9;
brch_m1 = 2'd1;
path_m2 = 4'd10;
brch_m2 = 2'd2;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-7; const int MOD = 1e9 + 7; const long long INFLL = 0x3f3f3f3f3f3f3f3f; const int INF = 0x3f3f3f3f; const int MAXN = 4e5 + 5; char s[MAXN]; int vis[200], t[200]; int check(int n, int l) { int need = (l / 2) * n, cnt = 0; for (int i = 0; i < 200; i++) cnt += vis[i] / 2; if (cnt >= need) return 1; return 0; } void solve(int n, int l) { vector<char> v1, v2; printf( %d n , n); for (int i = 0; i < 200; i++) { while (vis[i] >= 2) v1.push_back((char)i), vis[i] -= 2; if (vis[i]) v2.push_back((char)i); } for (int i = 0; i < n; i++) { int p = 0; while (p < l / 2) { s[p] = s[l - 1 - p] = v1[v1.size() - 1]; v1.pop_back(); p++; } if (l & 1) { if (v2.empty()) s[p] = v1[v1.size() - 1], v2.push_back(v1[v1.size() - 1]), v1.pop_back(); else s[p] = v2[v2.size() - 1], v2.pop_back(); } s[l] = 0; printf( %s , s); } } int main() { int n; cin >> n; scanf( %s , s + 1); for (int i = 1; i <= n; i++) vis[s[i]]++; int maxn = INF; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { if (check(i, n / i)) maxn = min(i, maxn); if (check(n / i, i)) maxn = min(n / i, maxn); } } solve(maxn, n / maxn); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)2e5 + 10; vector<int> res[maxn]; int main() { string s; cin >> s; stack<int> st, st2; int ma = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == 1 ) { if (st.empty()) { cout << -1 << endl; return 0; } res[st.top()].push_back(i + 1); st2.push(st.top()); st.pop(); } else { if (!st2.empty()) { res[st2.top()].push_back(i + 1); st.push(st2.top()); st2.pop(); } else { res[ma].push_back(i + 1); st.push(ma); ma++; } } } if (!st2.empty()) { cout << -1 << endl; return 0; } int cnt = 0; for (int i = 0; i < maxn; i++) if (!res[i].empty()) cnt++; cout << cnt << endl; for (int i = 0; i < maxn; i++) if (!res[i].empty()) { printf( %d , res[i].size()); for (int j = 0; j < res[i].size(); j++) { printf( %d , res[i][j]); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int a[2020]; void solve() { int n, x, y; cin >> n >> x >> y; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); reverse(a, a + n); int c = 0; cout << a[x - 1] - a[x]; } int main() { ios::sync_with_stdio(false); cin.tie(0); int T = 1; while (T--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_LP__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_BLACKBOX_V
|
//
// Copyright (c) 2015 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module pdp1_write_decoder(ma_op, ma_ac, ma_io, ma_cd, ma_w, ma_r);
input [0:4] ma_op;
input [0:17] ma_ac;
input [0:17] ma_io;
input [0:17] ma_cd;
output reg ma_w;
output reg [0:17] ma_r;
always @(ma_op or ma_ac or ma_io or ma_cd) begin
ma_w = 1'b1;
case(ma_op)
`PDP1_OP_CAL:
ma_r <= ma_ac;
`PDP1_OP_DAC:
ma_r <= ma_ac;
`PDP1_OP_DAP:
ma_r <= {ma_cd[0:5], ma_ac[6:17]};
`PDP1_OP_DIP:
ma_r <= {ma_ac[0:5], ma_cd[6:17]};
`PDP1_OP_DIO:
ma_r <= ma_io;
`PDP1_OP_DZM:
ma_r <= 0;
default:
ma_w <= 0;
endcase // case (ma_op)
end
endmodule // pdp1_write_decoder
|
#include <bits/stdc++.h> using namespace std; int v[1100][1100]; int main() { int n, k; cin >> n >> k; if (n > k + k) { cout << n * k << endl; for (int i = 1; i <= n; i++) { int t = k; for (int j = 1; j <= n; j++) if (i != j && !v[i][j] && !v[j][i] && t) { t--; v[i][j] = v[j][i] = 1; printf( %d %d n , i, j); } } } else printf( -1 n ); }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2000 * 100 + 1000; vector<long long> adj[N]; long long a[N], h[N], t[N]; bool mark[N]; long long f(long long p) { mark[p] = true; long long ans = h[p] * a[p]; t[p] = a[p]; for (auto q : adj[p]) if (mark[q] == false) { h[q] = h[p] + 1; ans += f(q); t[p] += t[q]; } return ans; } long long ans = 0, sum = 0; void calc(long long val, long long p) { mark[p] = true; ans = max(ans, val); for (auto q : adj[p]) if (mark[q] == false) { long long k = sum - 2 * t[q]; calc(val + k, q); } } int32_t main() { ios::sync_with_stdio(false); long long n; cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } for (long long i = 0; i < n - 1; i++) { long long u, v; cin >> u >> v; u--; v--; adj[u].push_back(v); adj[v].push_back(u); } long long val = f(0); for (long long i = 0; i < N; i++) mark[i] = false; calc(val, 0); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int fp(int abc, int parent[]) { if (parent[abc] == abc) return abc; int def = fp(parent[abc], parent); parent[abc] = def; return def; } void cycledmerge(vector<int> hub[], int n, int parent[]) { stack<int> urutan; for (int i = 0; i < n; i++) parent[i] = i; stack<pair<int, int> > ngurut; vector<int> sudah(n, 0); vector<int> adadiurutan(n, 0); vector<int> dari(n, -1); for (int i = 0; i < n; i++) { if (sudah[i]) continue; urutan.push(i); ngurut.push(make_pair(i, 0)); adadiurutan[i] = 1; sudah[i] = 1; while (!ngurut.empty()) { int id = ngurut.top().first; int val = ngurut.top().second; ngurut.pop(); if (val == (int)hub[id].size()) { while (!urutan.empty() && urutan.top() == id) urutan.pop(); adadiurutan[id] = 0; continue; } ngurut.push(make_pair(id, val + 1)); int next = hub[id][val]; if (dari[id] == next) continue; if (sudah[next] && !adadiurutan[fp(next, parent)]) continue; if (!sudah[next]) { sudah[next] = 1; urutan.push(next); ngurut.push(make_pair(next, 0)); adadiurutan[next] = 1; dari[next] = id; continue; } if (parent[fp(id, parent)] == fp(next, parent)) continue; parent[fp(id, parent)] = fp(next, parent); while (!urutan.empty() && urutan.top() != fp(next, parent)) { parent[fp(urutan.top(), parent)] = fp(next, parent); urutan.pop(); } } } return; } int main() { int p[200]; vector<int> hub[200]; int n, m; cin >> n >> m; for (int(i) = 0; (i) < (m); ++(i)) { int a, b; cin >> a >> b; --a; --b; hub[a].push_back(b); hub[b].push_back(a); } cycledmerge(hub, n, p); vector<int> ukuran(n, 0); for (int(i) = 0; (i) < (n); ++(i)) ukuran[p[i]]++; int numcyc = 0; for (int(i) = 0; (i) < (n); ++(i)) if (ukuran[i] >= 3) ++numcyc; if (numcyc != 1) { cout << NO << endl; return 0; } int besar = 0; for (int(i) = 0; (i) < (n); ++(i)) if (ukuran[i] >= 3) besar = ukuran[i]; int yesadj = 0; int noadj = 0; for (int(i) = 0; (i) < (n); ++(i)) for (int(j) = 0; (j) < (((int)hub[i].size())); ++(j)) { int k = hub[i][j]; if (k < i) continue; if (p[i] != p[k]) ++noadj; else ++yesadj; } if (yesadj != besar || noadj != (n - besar + 1) - 1) { cout << NO << endl; } else { cout << FHTAGN! << endl; } return 0; }
|
interface automodport_if
( input logic clk,
input logic rst_n
);
//----------------------------------------------------------------------------------------
// Group: Signals
logic req_val;
logic [63:0] req_dat;
logic req_credit;
logic [1:0] rsp_cmd;
logic [63:0] rsp_data;
logic rsp_credit;
logic in_pure;
logic out_pure;
logic manually_listed;
//----------------------------------------------------------------------------------------
// Group: Clocking blocks
clocking req_mon_cb @(posedge clk);
input rst_n;
input req_val;
input req_dat;
input req_credit;
input manually_listed;
endclocking : req_mon_cb
clocking rsp_drv_cb @(posedge clk);
input rst_n;
output rsp_cmd;
output rsp_data;
input rsp_credit;
endclocking : rsp_drv_cb
//----------------------------------------------------------------------------------------
// Group: Modports
modport req_mon_mp(clocking req_mon_cb);
modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
modport pure_mp(input in_pure, output out_pure);
//----------------------------------------------------------------------------------------
// Group: Methods
function void rsp_reset();
rsp_cmd = 2'b0;
rsp_data = 64'b0;
endfunction : rsp_reset
//----------------------------------------------------------------------------------------
// Group: Assertions
logic [1:0] cmd_m1;
always @(posedge clk) begin
cmd_m1 <= rsp_cmd;
if(rst_n) begin
if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
end
end
endinterface
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int a1, a2, a3, b1, b2, b3, n, total = 0; cin >> a1 >> a2 >> a3 >> b1 >> b2 >> b3 >> n; if ((a1 + a2 + a3) % 5 == 0) { total = total + (a1 + a2 + a3) / 5; } else { total = total + 1 + (a1 + a2 + a3) / 5; } if ((b1 + b2 + b3) % 10 == 0) { total = total + (b1 + b2 + b3) / 10; } else { total = total + 1 + (b1 + b2 + b3) / 10; } if (total <= n) { cout << YES ; } else { cout << NO ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_BLACKBOX_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_BLACKBOX_V
|
/*
* File: tb_top.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
* testbench for pippo-based system
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module tb_cbu_tasks();
reg clk;
reg rst;
//
// interconnections
//
wire [31:0] iimx_adr_o;
wire iimx_rqt_o;
wire [31:0] iimx_dat_i;
wire iimx_ack_i;
wire iimx_rty_i;
wire iimx_err_i;
wire [31:0] iimx_adr_i;
wire [31:0] dimx_adr_o;
wire dimx_rqt_o;
wire dimx_we_o;
wire [3:0] dimx_sel_o;
wire [31:0] dimx_dat_o;
wire [31:0] dimx_dat_i;
wire dimx_ack_i;
wire dimx_err_i;
wire RS232_TX_DATA;
wire RS232_RX_DATA;
wire [7:0] tb_rx_data;
wire tb_rx_done;
wire tb_tx_start;
wire tb_tx_busy;
wire [7:0] tb_tx_data;
//
// clk & rst
//
parameter HalfClkCycle = 7.8; // FPGA_64MHZ
parameter RstTime = 3;
initial begin
rst = 0;
dsu_rst = 0;
dsu_burn_enable = 0;
#RstTime rst = 1;
dsu_rst = 1;
#RstTime rst = 0;
dsu_rst = 0;
end
initial
clk = 1;
always #HalfClkCycle clk = ~clk;
//
// virtual console
//
always @ (tb_rx_done or tb_rx_data) begin
if (tb_rx_done)
$write("%s",tb_rx_data);
end
//
// DUT
//
top_pss top_pss(
.clk(clk),
.rst(rst),
.dsu_rst(dsu_rst),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_we(dsu_sram_we),
.txd(RS232_TX_DATA),
.rxd(RS232_RX_DATA),
.iimx_adr_o(iimx_adr_o),
.iimx_rqt_o(iimx_rqt_o),
.iimx_rty_i(iimx_rty_i),
.iimx_ack_i(iimx_ack_i),
.iimx_err_i(iimx_err_i),
.iimx_dat_i(iimx_dat_i),
.iimx_adr_i(iimx_adr_i),
.dimx_adr_o(dimx_adr_o),
.dimx_rqt_o(dimx_rqt_o),
.dimx_we_o(dimx_we_o),
.dimx_sel_o(dimx_sel_o),
.dimx_dat_o(dimx_dat_o),
.dimx_dat_i(dimx_dat_i),
.dimx_ack_i(dimx_ack_i),
.dimx_err_i(dimx_err_i)
);
//
// peripheral uartlite model
//
tb_dsu_rx tb_dsu_rx(
.clk(clk),
.rst(rst),
.RxD(RS232_TX_DATA),
.RxD_data_ready(tb_rx_done),
.RxD_data(tb_rx_data),
.RxD_endofpacket(),
.RxD_idle()
);
tb_dsu_tx tb_dsu_tx(
.clk(clk),
.rst(rst),
.TxD_start(tb_tx_start),
.TxD_data(tb_tx_data),
.TxD(RS232_RX_DATA),
.TxD_busy(tb_tx_busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; bitset<N> b; int p[N]; int cnt[N]; bool was[N]; int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , p + i); p[i]--; was[i] = false; } for (int i = 1; i <= n; i++) { cnt[i] = 0; } int c1 = 0, c2 = 0; for (int i = 0; i < n; i++) { if (was[i]) { continue; } int x = i; int len = 0; while (!was[x]) { was[x] = true; x = p[x]; len++; } c1 += len % 2; c2 += len / 2; cnt[len]++; } b.set(n); for (int i = 1; i <= n; i++) { if (cnt[i] == 0) { continue; } for (int j = 0; (1 << j) <= cnt[i]; j++) { int x = i * (1 << j); b |= (b >> x); cnt[i] -= (1 << j); } b |= (b >> (i * cnt[i])); } int ans_min = k; if (!b.test(n - k)) { ans_min++; } int ans_max = 0; ans_max += 2 * min(k, c2); k -= min(k, c2); ans_max += min(k, c1); printf( %d %d n , ans_min, ans_max); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_HS__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_SYMBOL_V
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module rc5 #(
parameter csr_addr = 4'h0,
parameter clk_freq = 100000000
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg rx_irq,
input rx
);
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
parameter divisor = clk_freq/596/16;
reg [15:0] enable16_counter;
wire enable16;
assign enable16 = (enable16_counter == 16'd0);
always @(posedge sys_clk) begin
if(sys_rst)
enable16_counter <= divisor - 1;
else begin
enable16_counter <= enable16_counter - 16'd1;
if(enable16)
enable16_counter <= divisor - 1;
end
end
//-----------------------------------------------------------------
// Synchronize rx
//-----------------------------------------------------------------
reg rx1;
reg rx2;
always @(posedge sys_clk) begin
rx1 <= rx;
rx2 <= rx1;
end
//-----------------------------------------------------------------
// RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [12:0] rx_reg;
reg [12:0] rx_data;
always @(posedge sys_clk) begin
if(sys_rst) begin
rx_irq <= 1'b0;
rx_busy <= 1'b0;
rx_count16 <= 4'd0;
rx_bitcount <= 4'd0;
end else begin
rx_irq <= 1'b0;
if(enable16) begin
if(~rx_busy) begin // look for start bit
if(rx2) begin // start bit found
rx_busy <= 1'b1;
rx_count16 <= 4'd13;
rx_bitcount <= 4'd0;
end
end else begin
rx_count16 <= rx_count16 + 4'd1;
if(rx_count16 == 4'd0) begin // sample
rx_bitcount <= rx_bitcount + 4'd1;
if(rx_bitcount == 4'd0) begin // verify startbit
if(~rx2)
rx_busy <= 1'b0;
end else if(rx_bitcount == 4'd14) begin
rx_busy <= 1'b0;
rx_data <= rx_reg;
rx_irq <= 1'b1;
end else
rx_reg <= {rx_reg[11:0], rx2};
end
end
end
end
end
//-----------------------------------------------------------------
// CSR interface
//-----------------------------------------------------------------
wire csr_selected = csr_a[13:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
end else begin
csr_do <= 32'd0;
if(csr_selected)
csr_do <= rx_data;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_SYMBOL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; int n; vector<int> point[2]; vector<pair<long long, int> > area[2], vec[4]; long long query(int type, int i, int j, int k) { printf( %d %d %d %d n , type, i, j, k); fflush(stdout); long long res; scanf( %lld , &res); return res; } int main() { scanf( %d , &n); for (int i = 3; i <= n; i++) { if (query(2, 1, 2, i) < 0) point[0].emplace_back(i); else point[1].emplace_back(i); } for (int i = 0; i < point[0].size(); i++) area[0].emplace_back(make_pair(query(1, 1, 2, point[0][i]), point[0][i])); for (int i = 0; i < point[1].size(); i++) area[1].emplace_back(make_pair(query(1, 1, 2, point[1][i]), point[1][i])); pair<long long, int> L, R; for (int i = 0; i < area[0].size(); i++) L = max(L, area[0][i]); for (int i = 0; i < area[1].size(); i++) R = max(R, area[1][i]); for (int i = 0; i < point[0].size(); i++) { if (point[0][i] == L.second) continue; if (query(2, 1, L.second, point[0][i]) < 0) vec[0].push_back(area[0][i]); else vec[1].push_back(area[0][i]); } for (int i = 0; i < point[1].size(); i++) { if (point[1][i] == R.second) continue; if (query(2, 1, R.second, point[1][i]) < 0) vec[2].emplace_back(area[1][i]); else vec[3].emplace_back(area[1][i]); } for (int i = 0; i <= 3; i++) sort(vec[i].begin(), vec[i].end()); printf( 0 1 ); for (int i = 0; i < vec[0].size(); i++) printf( %d , vec[0][i].second); if (L.second) printf( %d , L.second); for (int i = vec[1].size() - 1; i >= 0; i--) printf( %d , vec[1][i].second); printf( 2 ); for (int i = 0; i < vec[2].size(); i++) printf( %d , vec[2][i].second); if (R.second) printf( %d , R.second); for (int i = vec[3].size() - 1; i >= 0; i--) printf( %d , vec[3][i].second); printf( n ); fflush(stdout); }
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#include <bits/stdc++.h> int main(void) { int stack[100000 + 1], sp = 0, c; stack[0] = 0 ; while (c = getchar(), c != n ) { if (c == stack[sp]) --sp; else stack[++sp] = c; } printf( %s n , sp == 0 ? Yes : No ); exit(EXIT_SUCCESS); }
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#include <bits/stdc++.h> using namespace std; const double eps = 3e-5; double x, h, l; int main() { scanf( %lf , &x); for (double h = 1; h <= 10 + eps; h++) { if (h + eps < x) continue; l = h / (sqrt((h * h) / (x * x) - 1)) * 2.0; for (double q = 1; q <= 10 + eps; q++) if (l - q < eps && q - l < eps) { printf( %d %d , (int)q, (int)h); return 0; } } }
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#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; vector<int> fa; int n, m, q, g[300][300], x, y, c; int id(int x, int y) { return x * m + y; } int in(int x, int y) { return x >= 0 && y >= 0 && x < n && y < m; } int find(int x) { return fa[x] == x ? x : (fa[x] = find(fa[x])); } int merge(int x, int y) { int xx = find(x), yy = find(y); if (xx == yy) { return 0; } else { fa[xx] = yy; return 1; } } int ADD(int x, int y) { int p = id(x, y); if (fa[p] != INF) return 0; fa[p] = p; static int dx[] = {0, 0, 1, -1}; static int dy[] = {1, -1, 0, 0}; int r = 1; for (int i = (int)0; i < (int)4; ++i) { int nx = x + dx[i], ny = y + dy[i]; int pp = id(nx, ny); if (in(nx, ny) && fa[pp] != INF) { r -= merge(p, pp); } } return r; } struct P { int x, y, p; P(int x_, int y_, int p_) : x(x_), y(y_), p(p_) {} }; int main() { scanf( %d%d%d , &n, &m, &q); fa.resize(n * m); memset(g, 0, sizeof(g)); vector<vector<P>> add(1), del(1); int pc = 0, cc = 0; for (int i = (int)0; i < (int)q; ++i) { scanf( %d%d%d , &x, &y, &c); --x, --y; if (c != pc) { pc = c; ++cc; add.emplace_back(vector<P>{}), del.emplace_back(vector<P>{}); } c = cc; if (g[x][y] != c) { del[g[x][y]].emplace_back(x, y, i); add[c].emplace_back(x, y, i); g[x][y] = c; } } vector<int> df(q, 0); for (int i = (int)0; i < (int)n; ++i) for (int j = (int)0; j < (int)m; ++j) add[0].emplace_back(i, j, 0); for (int c = (int)1; c < (int)cc + 1; ++c) { if (add[c].empty()) continue; fill(fa.begin(), fa.end(), INF); for (auto &p : add[c]) { df[p.p] = ADD(p.x, p.y); } } df[0] += 1; for (int c = (int)0; c < (int)cc + 1; ++c) { fill(fa.begin(), fa.end(), INF); unordered_set<int> xx; for (auto &p : del[c]) { xx.insert(id(p.x, p.y)); } for (auto &p : add[c]) { if (!xx.count(id(p.x, p.y))) ADD(p.x, p.y); } int n = del[c].size(); for (int i = (int)n - 1; i >= (int)0; --i) { auto &p = del[c][i]; df[p.p] -= ADD(p.x, p.y); } } int cnt = 0; for (int i = (int)0; i < (int)q; ++i) { cnt += df[i]; printf( %d n , cnt); } }
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#include <bits/stdc++.h> using namespace std; set<int> S; priority_queue<pair<int, pair<int, int> >, vector<pair<int, pair<int, int> > >, greater<pair<int, pair<int, int> > > > H; int i, j, k, n, a[222222], nl, nr, sz, aa, bb, u[222222], o; pair<int, pair<int, int> > pp; set<pair<int, int> >::iterator it; char s[222222]; int next(int k) { set<int>::iterator it = S.find(k); ++it; if (it == S.end()) return -1; else return *it; } int pred(int k) { set<int>::iterator it = S.find(k); if (it == S.begin()) return -1; else { --it; return *it; } } int main() { scanf( %d , &n); gets(s); gets(s); for (i = 0; i < n; i++) if (s[i] == B ) ++aa; else ++bb; sz = min(aa, bb); printf( %d n , sz); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) S.insert(i); for (i = 1; i < n; i++) if (s[i - 1] != s[i]) H.push(make_pair(abs(a[i] - a[i - 1]), make_pair(i, i + 1))); o = 0; while (o != sz) { pp = H.top(); H.pop(); if (u[pp.second.first]) continue; if (u[pp.second.second]) continue; printf( %d %d n , pp.second.first, pp.second.second); nl = pred(pp.second.first); nr = next(pp.second.second); if (nl > -1 && nr > -1 && s[nl - 1] != s[nr - 1]) H.push(make_pair(abs(a[nl - 1] - a[nr - 1]), make_pair(nl, nr))); S.erase(S.find(pp.second.first)); S.erase(S.find(pp.second.second)); u[pp.second.first] = 1; u[pp.second.second] = 1; ++o; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long int n, m; long long int arr[300000]; vector<long long int> ans; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int TESTS, q, a, b, l, r, c, k, p, h, w, x, y, z, xs, ys, t, f; long double d; TESTS = 1; while (TESTS--) { cin >> n >> p; long long int maxi = 0; for (long long int i = 0; i <= n - 1; i++) cin >> arr[i], maxi = max(maxi, arr[i]); sort(arr, arr + n); for (long long int i = 1; i <= maxi; i++) { long long int num = 1; x = i; y = 0; while (y < n) { long long int ind = upper_bound(arr, arr + n, x) - arr; num *= ind - y; num %= p; x++; y++; } if (num) ans.push_back(i); } cout << ans.size() << n ; for (auto it : ans) cout << it << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long q; cin >> q; while (q--) { long long n, m; cin >> n; cin >> m; if (m > n || m % 10 == 0) { cout << 0 << n ; continue; } long long p = (n / m) / 10; long long q = (n / m) % 10; long long sum = 0; if (m % 2 == 0) sum = p * (40LL); else if (m % 5 == 0) sum = p * (25LL); else sum = p * (45LL); long long num = 0; for (long long i = 1; i <= q; i++) { num += m; sum += (num % 10); } cout << sum << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; bool f1(pair<long long, long long> x, pair<long long, long long> y) { return x.first > y.first; } bool f2(pair<long long, long long> x, pair<long long, long long> y) { return x.second > y.second; } bool f3(long long x, long long y) { return x > y; } bool fa(vector<long long> x, vector<long long> y) { return x[0] < y[0]; } long long fac(long long a) { if (a == 1 || a == 0) { return 1; } else { return (a * fac(a - 1)); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string a; cin >> a; vector<long long> b; if (a.size() == 1) { cout << a; exit(0); } a = a + 0 ; for (long long i = 0; i < a.size() - 1; i++) { if (a[i] == a[i + 1] && a[i] == a[i + 2]) { a[i] = 0 ; } } for (long long i = 0; i < a.size(); i++) { if (a[i] != 0 ) b.push_back(a[i]); } vector<long long> c; long long check = 0; for (long long i = 0; i < b.size() - 1; i++) { if (b[i] == b[i + 1]) { c.push_back(i); check++; } } if (check > 0) { for (long long i = 0; i < c.size() - 1; i++) { if (c[i] == c[i + 1] - 2) { b[c[i + 1]] = 0; i++; } } } for (long long i = 0; i < b.size(); i++) { if (b[i] != 0) { char g = b[i]; cout << g; } } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > ans; void merge(int l, int r, int lev) { if (lev == 0) { ans.push_back({l, r}); return; } int mid = (l + r) >> 1; merge(l, mid, lev - 1); merge(mid + 1, r, lev - 1); int j = mid + 1; for (int i = l; i <= mid; i++) { ans.push_back({i, j}); j++; } } int main(int argc, char** argv) { int n; scanf( %d , &n); if (n == 1) { printf( 0 ); return 0; } int t = 1; int lev = -1; while (t * 2 <= n) t *= 2, lev++; merge(1, t, lev); merge(n - t + 1, n, lev); cout << ans.size() << endl; for (int i = 0; i <= ans.size() - 1; i++) { printf( %d %d n , ans[i].first, ans[i].second); } return 0; }
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#include<iostream> #include<string.h> #include <fstream> #include <string> #include <vector> #include <iomanip> #include <cmath> #include <cstdlib> #include<map> #include <ctime> using namespace std; int main(){ long long int t; cin>>t; for(long long int mat=0;mat<t;mat=mat+1){ long long int total; cin>>total; long long int median; vector<long long int> array; for(long long int i=0;i<total;i=i+1){ char a; cin>>a; if(a== * ){ array.push_back(i); } } long long int n=array.size(); if(n%2==0){ median=n/2-1; } else{ median=n/2; } long long int ans=0; for(long long int i=0;i<array.size();i=i+1){ ans+=abs(array[i]-array[median])-abs(i-median); } cout<<ans<<endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { unsigned long long a, b; cin >> a >> b; if (max(a, b) % min(a, b)) { cout << -1 << endl; continue; } int dem = 0; long long p = max(a, b) / min(a, b); while (p != 1) { if (p % 8 == 0) { dem++; p /= 8; } else if (p % 4 == 0) { dem++; p /= 4; } else if (p % 2 == 0) { dem++; p /= 2; } else { dem = -1; break; } } cout << dem << endl; } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_MS__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_S_SYMBOL_V
/**
* udp_dlatch$P_pp$PKG$s: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_S_SYMBOL_V
|
/**
* bsg_fpu_preprocess.v
*
* @author Tommy Jung
*/
`include "bsg_defines.v"
module bsg_fpu_preprocess
#(parameter `BSG_INV_PARAM(e_p )
, parameter `BSG_INV_PARAM(m_p )
)
(
input [e_p+m_p:0] a_i
, output logic zero_o
, output logic nan_o
, output logic sig_nan_o
, output logic infty_o
, output logic exp_zero_o
, output logic man_zero_o
, output logic denormal_o
, output logic sign_o
, output logic [e_p-1:0] exp_o
, output logic [m_p-1:0] man_o
);
assign man_o = a_i[m_p-1:0];
assign exp_o = a_i[m_p+:e_p];
assign sign_o = a_i[e_p+m_p];
logic mantissa_zero;
logic exp_zero;
logic exp_ones;
assign mantissa_zero = (man_o == {m_p{1'b0}});
assign exp_zero = (exp_o == {e_p{1'b0}});
assign exp_ones = (exp_o == {e_p{1'b1}});
// outputs
assign zero_o = exp_zero & mantissa_zero;
assign nan_o = exp_ones & ~mantissa_zero;
assign sig_nan_o = nan_o & ~man_o[m_p-1];
assign infty_o = exp_ones & mantissa_zero;
assign exp_zero_o = exp_zero;
assign man_zero_o = mantissa_zero;
assign denormal_o = exp_zero & ~mantissa_zero;
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_preprocess)
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, set<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream &operator<<(ostream &os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } vector<long long> adj[500050]; long long a[500050], b[500050]; set<long long> s; void dfs(long long x, long long pr) { for (long long i = 0; i < adj[x].size(); i++) if (adj[x][i] != pr) a[adj[x][i]] = *s.begin(), s.erase(s.begin()); b[x] = *s.begin(); s.erase(s.begin()); for (long long j = adj[x].size() - 1; j >= 0; j--) if (adj[x][j] != pr) dfs(adj[x][j], x); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, x, y; cin >> n; if (n == 1) { cout << 1 2 ; return 0; } for (long long i = 2; i < 2 * n + 1; i++) s.insert(i); for (long long i = 0; i < n - 1; i++) cin >> x >> y, adj[x].push_back(y), adj[y].push_back(x); a[1] = 1; dfs(1, -1); for (long long i = 1; i < n + 1; i++) cout << a[i] << << b[i] << n ; return 0; }
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#include <iostream> #include <cmath> #include <map> #include <string> #include <vector> #include <algorithm> #define int long long using namespace std; string s; int a, b, c; int n, m, k; vector<int>vec, vec2; int arr[4000000], mark[4000000]; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> a; vec.push_back(a); } for (int i = 0; i < m; i++) { cin >> a; vec2.push_back(a); } if (n < m) { swap(n, m); swap(vec, vec2); } int iter = 0; for (auto i : vec) { mark[iter] = m; iter++; arr[i] = iter; } iter = 0; int pos; for (auto i : vec2) { iter++; if (arr[i] != 0) { pos = (arr[i] - iter + n) % n; mark[pos]--; } } pos = 0; int sum = 0; int len = 0; while (true) { sum += mark[pos]; pos += m; len += m; pos %= n; if (pos == 0) { break; } } k -= 2; int ans = (k / sum); ans *= len; k %= sum; k += 2; pos = 0; while (k > mark[pos]) { k -= mark[pos]; pos += m; ans += m; pos %= n; } int pos2 = 0; while (k > 0) { ans++; if (vec[(pos + pos2) % n] != vec2[pos2 % m]) { k--; } pos2++; } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); map<long long int, long long int> mpp; long long int n; cin >> n; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; mpp[__builtin_popcount(x)]++; } long long int ans = 0; for (auto p : mpp) { ans += (p.second) * (p.second - 1) / 2; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; long long arr[n + 5]; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); long long mn = arr[0]; long long mx = arr[n - 1]; long long cnt1 = 0, cnt2 = 0; for (int i = 0; i < n; i++) { if (arr[i] == mn) cnt1++; else if (arr[i] == mx) cnt2++; } cout << mx - mn << ; if (mn == mx) cout << n * 1LL * (n - 1) / 2; else cout << (long long)(cnt1 * cnt2); return 0; }
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#include <bits/stdc++.h> using namespace std; long long t, d, ct, q, ans, l, m, r, n, mx, mn, i, j, k, x, y, z, s; char ch; string ss = , str = ; map<pair<long long, long long>, long long> mp; set<long long> st; long long a[300003], b[300003]; vector<pair<long long, long long>> v; bool ask(long long k) { long long i; for (i = 0; i < v.size(); i++) if (v[i].first != k && v[i].second != k) break; if (i == v.size()) return 1; long long x = v[i].first; long long g = k; if (x > k) swap(x, k); if (a[x] + a[k] - mp[{x, k}] == m) return 1; x = v[i].second; if (x > g) swap(x, g); if (a[x] + a[g] - mp[{x, g}] == m) return 1; return 0; } int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); s = k = d = l = mx = m = mn = r = q = i = j = z = x = y = ct = ans = 0; cin >> n >> m; for (i = 0; i < m; i++) { cin >> x >> y, a[x]++, a[y]++; v.push_back({x, y}); if (x > y) swap(x, y); mp[{x, y}]++; } x = v[0].first; y = v[0].second; bool ya = ask(x); if (ya) { cout << YES ; return 0; } ya = ask(y); if (ya) { cout << YES ; return 0; } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p1 = 0, p2 = 0; cin >> n; int mid[1000], index = 0; for (int i = 0; i < n; i++) { int a; cin >> a; if (a % 2 == 0) { for (int j = 1; j <= (a / 2); j++) { int t; cin >> t; p1 += t; } for (int j = 1; j <= (a / 2); j++) { int t; cin >> t; p2 += t; } } else { for (int j = 1; j <= (a / 2); j++) { int t; cin >> t; p1 += t; } cin >> mid[index++]; for (int j = 1; j <= (a / 2); j++) { int t; cin >> t; p2 += t; } } } sort(mid, mid + index); for (int i = index - 1; i >= 0; i--) { if (((index - 1) % 2 == 0 && i % 2 == 0) || ((index - 1) % 2 == 1 && i % 2 == 1)) p1 += mid[i]; else p2 += mid[i]; } cout << p1 << << p2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t = 1, i; cin >> n; int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (i = 0; i < n - 1; i++) { if (a[i + 1] == a[i]) { t++; } else if (t > (n + 1) / 2) { cout << NO ; return 0; } else t = 1; } if (t > ((n + 1) / 2)) cout << NO ; else cout << YES ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; map<long long, long long> mp; int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n, m; cin >> n; vector<long long> v(n); for (int i = 0; i < n; ++i) { cin >> v[i]; if (mp.find(v[i]) == mp.end()) mp[v[i]] = 1; else mp[v[i]]++; } cin >> m; vector<long long> a(m), b(m); for (int i = 0; i < m; ++i) cin >> a[i]; for (int i = 0; i < m; ++i) cin >> b[i]; vector<pair<long long, pair<long long, long long> > > vp; for (int i = 0; i < m; ++i) { vp.push_back({mp[a[i]], {mp[b[i]], i}}); } sort(vp.begin(), vp.end()); int ans = vp.size() - 1; while (ans > 0 && vp[ans].first == vp[ans - 1].first && vp[ans].second.first == vp[ans - 1].second.first) ans--; cout << vp[ans].second.second + 1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n; long long sol(long long* data) { long long ans = 0, fang = 0, sum = 0; for (int i = 1; i <= n; i++) { ans += data[i] * data[i] * (i - 1); ans -= sum * data[i] * 2; ans += fang; fang += data[i] * data[i]; sum += data[i]; } return ans; } long long x[maxn], y[maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld%lld , x + i, y + i); sort(x + 1, x + n + 1); sort(y + 1, y + n + 1); cout << sol(x) + sol(y) << endl; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
// Internal 125 MHz clock
wire clk_dcm_out;
wire clk_int;
wire rst_int;
wire dcm_rst;
wire [7:0] dcm_status;
wire dcm_locked;
wire dcm_clkfx_stopped = dcm_status[2];
assign dcm_rst = ~reset_n | (dcm_clkfx_stopped & ~dcm_locked);
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
DCM_SP #(
.CLKIN_PERIOD(10),
.CLK_FEEDBACK("NONE"),
.CLKDV_DIVIDE(2.0),
.CLKFX_MULTIPLY(5.0),
.CLKFX_DIVIDE(4.0),
.PHASE_SHIFT(0),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.STARTUP_WAIT("FALSE"),
.CLKIN_DIVIDE_BY_2("FALSE")
)
clk_dcm_inst (
.CLKIN(clk_ibufg),
.CLKFB(1'b0),
.RST(dcm_rst),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_dcm_out),
.CLKFX180(),
.STATUS(dcm_status),
.LOCKED(dcm_locked),
.PSDONE()
);
BUFG
clk_bufg_inst (
.I(clk_dcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~dcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int n, t; int ask(int r) { cout << ? << 1 << << r << endl; int ans; cin >> ans; return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); srand(time(0)); cin >> n >> t; vector<int> a(1, t); int inv = 0, rep = 0; for (int i = n - 1; i >= 1; i--) { int t2 = ask(i); inv ^= 1; int cur = i - (t - t2 + i) / 2; if (inv) cur = i - cur; if (t2 == n - t && rep < 25) { i++; rep++; } else { a.push_back(cur); rep = 0; } t = t2; } reverse(a.begin(), a.end()); cout << ! << a[0]; for (int i = 1; i < (int)a.size(); i++) cout << a[i] - a[i - 1]; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 500000; int a[MAX], last[MAX], prv[MAX], inSet[MAX], current[MAX]; int n, k; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; memset(last, -1, sizeof(last)); memset(prv, -1, sizeof(prv)); for (int i = 0; i < n; i++) { cin >> a[i]; prv[i] = last[a[i]]; last[a[i]] = i; } set<pair<int, int> > s; int ans = 0; for (int i = n - 1; i >= 0; i--) { int cur = a[i]; if (inSet[cur]) { s.erase(s.find(make_pair(current[cur], cur))); s.insert(make_pair(prv[i], cur)); current[cur] = prv[i]; continue; } ans++; if (s.size() < k) { inSet[cur] = true; s.insert(make_pair(prv[i], cur)); current[cur] = prv[i]; } else { pair<int, int> fr = (*s.begin()); inSet[cur] = true; inSet[fr.second] = false; s.erase(s.begin()); s.insert(make_pair(prv[i], cur)); current[cur] = prv[i]; } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1001; int n, m, h, A[M], w, a; int main() { scanf( %d%d%d , &n, &m, &h); for (int i = 1; i <= m; i++) scanf( %d , &A[i]), w += A[i]; w--, n--; a = w - (A[h] - 1); if (n > w) { puts( -1 ); return 0; } if (n > a) { puts( 1 ); return 0; } double ans = 1.0; int x = a - n, y = w - n; for (int i = a + 1; i <= w; i++) ans = ans / (i * 1.0); for (int i = x + 1; i <= y; i++) ans = ans * (i * 1.0); printf( %.7lf n , 1.0 - ans); }
|
#include <bits/stdc++.h> long long int min(long long int x, long long int y) { return (x < y) ? x : y; } long long int max(long long int x, long long int y) { return (x > y) ? x : y; } long long int fastexpo(long long int base, long long int power) { long long int res = 1; while (power) { if (power % 2 == 0) { base *= base; power /= 2; } else { res *= base; power--; } } return res; } long long int modexpo(long long int base, long long int power, long long int mod) { long long int res = 1; while (power) { if (power % 2 == 0) { base = (base * base) % mod; power /= 2; } else { res = (base * res) % mod; power--; } } return res; } const long long int SN = 1e7; bool prime[SN + 1]; void SEIVE(int n) { memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } prime[0] = false; prime[1] = false; } using namespace std; int x[26], par[200010]; int find(int n) { if (par[n] == n) return n; else return par[n] = find(par[n]); } void solve() { int n; cin >> n; for (long long int i = 0; i < n + 1; i++) par[i] = i; for (long long int i = 1; i < n + 1; i++) { string s; cin >> s; for (long long int j = 0; j < s.size(); j++) { if (!x[s[j] - a ]) x[s[j] - a ] = i; else par[find(i)] = par[x[s[j] - a ]]; } } int ans = 0; for (long long int i = 1; i < n + 1; i++) { if (par[i] == i) ans++; } cout << ans; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; solve(); }
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module fpga_core (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 9600 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
assign uart_rts = 1'b1;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign led = uart_tx_axis_tdata;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module table_control #( parameter n_words = 40
)
( input clk
, input ctrl_reset_n
, input [26:0] tdatai // dispatch intf to tables
, input [14:0] twraddr
, input [2:0] twren
, output [26:0] tdata_0
, output [26:0] tdata_1
, output [26:0] tdata_2
, input [1:0] command
, output idle
);
localparam wbits = $clog2(n_words);
wire [26:0] tdatao [2:0];
assign tdata_0 = tdatao[0];
assign tdata_1 = tdatao[1];
assign tdata_2 = tdatao[2];
reg [14:0] trdaddr_reg, trdaddr_next;
reg trden_reg, trden_next;
reg [wbits-1:0] count_reg, count_next;
reg state_reg, state_next;
localparam ST_IDLE = 1'b0;
localparam ST_STRM = 1'b1;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_STRM = state_reg == ST_STRM;
localparam CMD_START = 2'b01;
localparam CMD_RESET = 2'b10;
localparam CMD_ABORT = 2'b11;
wire gotCMD_ABORT = command == CMD_ABORT;
wire [14:0] trdaddr = trdaddr_reg + {{(15-wbits){1'b0}},count_reg};
wire last_count = count_reg == (n_words - 1);
assign idle = inST_IDLE;
always_comb begin
trdaddr_next = trdaddr_reg;
trden_next = trden_reg;
count_next = count_reg;
state_next = state_reg;
case (state_reg)
ST_IDLE: begin
if (~trden_reg) begin
case (command)
CMD_RESET: begin
trdaddr_next = '0;
trden_next = '0;
count_next = '0;
end
CMD_START: begin
trden_next = '1;
count_next = '0;
end
default: state_next = ST_IDLE;
endcase
end else begin
state_next = ST_STRM;
count_next = count_reg + 1'b1;
end
end
ST_STRM: begin
if (last_count | gotCMD_ABORT) begin
trden_next = '0;
count_next = '0;
trdaddr_next = trdaddr_reg + n_words;
state_next = ST_IDLE;
end else begin
count_next = count_reg + 1'b1;
end
end
endcase
end
always_ff @(posedge clk or negedge ctrl_reset_n) begin
if (~ctrl_reset_n) begin
trdaddr_reg <= '0;
trden_reg <= '0;
count_reg <= '0;
state_reg <= '0;
end else begin
trdaddr_reg <= trdaddr_next;
trden_reg <= trden_next;
count_reg <= count_next;
state_reg <= state_next;
end
end
genvar TGen;
generate for(TGen=0; TGen<3; TGen++) begin: TGenInst
t_ram ramins( .aclr (~ctrl_reset_n)
, .clock (clk)
, .data (tdatai)
, .wraddress (twraddr)
, .wren (twren[TGen])
, .rden (trden_reg)
, .rdaddress (trdaddr)
, .q (tdatao[TGen])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; const long long llinf = 1e18 + 7; const double eps = 1e-15; const int mod = 1e9 + 7; int main() { ios::sync_with_stdio(false); int n, a[100001], k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; int i = n; while (i > 0 && a[n] == a[i]) i--; if (i >= k) cout << -1; else cout << i; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a >> b; if (a == b) { cout << 0 << n ; continue; } if (a - b > 5) { int answ = 0; int cant = (a - b) / 5; answ = answ + cant; a = a - cant * 5; if (a - b == 1 or a - b == 2) answ = answ + 1; else { if (a != b) answ = answ + 2; } cout << answ << n ; continue; } if (b - a > 5) { int answ = 0; int cant = (b - a) / 5; a = a + cant * 5; answ = answ + cant; if (b - a == 1 or b - a == 2) answ = answ + 1; else { if (a != b) answ = answ + 2; } cout << answ << n ; continue; } if (abs(a - b) == 1 or abs(a - b) == 2 or abs(a - b) == 5) cout << 1 << n ; else cout << 2 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, n; cin >> n; long long int arr[n]; vector<long long int> vec[100010]; for (i = 0; i < n; i++) { cin >> arr[i]; vec[arr[i]].push_back(i); } long long int y = 0, d; for (i = 0; i < 100010; i++) { long long int x = 0; if (vec[i].size() >= 2) { d = vec[i][1] - vec[i][0]; for (j = 1; j < vec[i].size(); j++) { if (d == (vec[i][j] - vec[i][j - 1])) { ++x; } } if ((x + 1) == vec[i].size()) { ++y; } } else if (vec[i].size() == 1) { ++y; } else { continue; } } cout << y << endl; vector<long long int> vec1[100010]; long long int z = 0; for (i = 0; i < 100010; i++) { long long int x = 0; d = 0; if (vec[i].size() >= 2) { d = vec[i][1] - vec[i][0]; for (j = 1; j < vec[i].size(); j++) { if (d == (vec[i][j] - vec[i][j - 1])) { ++x; } } if ((x + 1) == vec[i].size()) { cout << i << << d << endl; } } else if (vec[i].size() == 1) { cout << i << << d << endl; } else { continue; } } return 0; }
|
// Library - static, Cell - th22, View - schematic
// LAST TIME SAVED: May 23 15:00:43 2014
// NETLIST TIME: May 23 15:01:15 2014
`timescale 1ns / 1ns
module th22 ( y, a, b );
output y;
input a, b;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th22";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net24));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net24), .d(net15));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net24));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net35), .d(net15));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net35));
nfet_b N4 ( .d(net22), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net22), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net15), .g(y), .s(net22), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net34), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N0 ( .d(net15), .g(b), .s(net34), .b(cds_globals.gnd_));
inv I8 ( y, net15);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxstatem.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.4 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.2 2001/07/03 12:55:41 mohor
// Minor changes because of the synthesys warnings.
//
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
`include "timescale.v"
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
StateDrop
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input ByteCntEq0;
input ByteCntGreat2;
input MRxDEq5;
input Transmitting;
input MRxDEqD;
input IFGCounterEq24;
input ByteCntMaxFrame;
output [1:0] StateData;
output StateIdle;
output StateDrop;
output StatePreamble;
output StateSFD;
reg StateData0;
reg StateData1;
reg StateIdle;
reg StateDrop;
reg StatePreamble;
reg StateSFD;
wire StartIdle;
wire StartDrop;
wire StartData0;
wire StartData1;
wire StartPreamble;
wire StartSFD;
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame
);
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= #Tp 1'b0;
StateDrop <= #Tp 1'b1;
StatePreamble <= #Tp 1'b0;
StateSFD <= #Tp 1'b0;
StateData0 <= #Tp 1'b0;
StateData1 <= #Tp 1'b0;
end
else
begin
if(StartPreamble | StartSFD | StartDrop)
StateIdle <= #Tp 1'b0;
else
if(StartIdle)
StateIdle <= #Tp 1'b1;
if(StartIdle)
StateDrop <= #Tp 1'b0;
else
if(StartDrop)
StateDrop <= #Tp 1'b1;
if(StartSFD | StartIdle | StartDrop)
StatePreamble <= #Tp 1'b0;
else
if(StartPreamble)
StatePreamble <= #Tp 1'b1;
if(StartPreamble | StartIdle | StartData0 | StartDrop)
StateSFD <= #Tp 1'b0;
else
if(StartSFD)
StateSFD <= #Tp 1'b1;
if(StartIdle | StartData1 | StartDrop)
StateData0 <= #Tp 1'b0;
else
if(StartData0)
StateData0 <= #Tp 1'b1;
if(StartIdle | StartData0 | StartDrop)
StateData1 <= #Tp 1'b0;
else
if(StartData1)
StateData1 <= #Tp 1'b1;
end
end
assign StateData[1:0] = {StateData1, StateData0};
endmodule
|
#include <bits/stdc++.h> using namespace std; int get(long long a) { if (a < 4) return 0; if (a < 16) return 1; if (a < 82) return 2; if (a < 6724) return 0; if (a < 50626) return 3; if (a < 2562991876) return 1; return 2; } int main() { int cur = 0; int n; cin >> n; for (int i = 0; i < n; i++) { long long t; cin >> t; cur ^= get(t); } if ((cur) != 0) cout << Furlo ; else cout << Rublo ; }
|
#include <bits/stdc++.h> using namespace std; int a[200100]; int sub[200100]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { sub[i] = sub[i - 1] + a[i - 1]; a[i] = a[i] - sub[i]; } sort(a + 1, a + 1 + n); cout << a[n] << endl; memset(sub, 0, sizeof(sub)); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_2_V
`define SKY130_FD_SC_HS__XOR2_2_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor2_2 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_2_V
|
#include <bits/stdc++.h> using namespace std; int n, i, j, x, y, a[179000]; int main() { for (cin >> n >> x >> y, i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) { for (j = max(1, i - x); j <= min(n, i + y); j++) if (i != j && a[j] <= a[i]) break; if (j > min(n, i + y)) break; } cout << i; }
|
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`define MAC cyclone10gx_mac
`define MLAB cyclone10gx_mlab_cell
`endif
module __MISTRAL_VCC(output Q);
MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module __MISTRAL_GND(output Q);
MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
endmodule
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter [31:0] LUT = 32'h0000_0000;
`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter [3:0] LUT = 4'h0;
`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
parameter _TECHMAP_CELLNAME_ = "";
// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
// which takes in a hexadecimal string that could be used to initialise RAM.
// In the vendor simulation models, this appears to work fine, but Quartus,
// either intentionally or not, forgets about this parameter and initialises the
// RAM to zero.
//
// Because of this, RAM initialisation is presently disabled, but the source
// used to generate mem_init0 is kept (commented out) in case this gets fixed
// or an undocumented way to get Quartus to initialise from mem_init0 is found.
`MLAB #(
.logical_ram_name(_TECHMAP_CELLNAME_),
.logical_ram_depth(32),
.logical_ram_width(1),
.mixed_port_feed_through_mode("Dont Care"),
.first_bit_number(0),
.first_address(0),
.last_address(31),
.address_width(5),
.data_width(1),
.byte_enable_mask_width(1),
.port_b_data_out_clock("NONE"),
// .mem_init0($sformatf("%08x", INIT))
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.ena0(A1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter _TECHMAP_CELLNAME_ = "";
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input CLK1, A1EN, B1EN;
output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
cyclonev_ram_block #(
.operation_mode("dual_port"),
.logical_ram_name(_TECHMAP_CELLNAME_),
.port_a_address_width(CFG_ABITS),
.port_a_data_width(CFG_DBITS),
.port_a_logical_ram_depth(2**CFG_ABITS),
.port_a_logical_ram_width(CFG_DBITS),
.port_a_first_address(0),
.port_a_last_address(2**CFG_ABITS - 1),
.port_a_first_bit_number(0),
.port_b_address_width(CFG_ABITS),
.port_b_data_width(CFG_DBITS),
.port_b_logical_ram_depth(2**CFG_ABITS),
.port_b_logical_ram_width(CFG_DBITS),
.port_b_first_address(0),
.port_b_last_address(2**CFG_ABITS - 1),
.port_b_first_bit_number(0),
.port_b_address_clock("clock0"),
.port_b_read_enable_clock("clock0")
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portawe(A1EN),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.portbre(B1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(27),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(27),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(54),
.operation_mode("M27x27")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(18),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(18),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(36),
.operation_mode("M18x18_FULL")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(9),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(9),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(18),
.operation_mode("M9x9")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
|
`timescale 1ns / 1ps
module control( input [5:0] opcode,
input [5:0] special,
input branch_eq, // result of comparison for conditional branch
output reg [1:0] if_pc_source,
output id_rt_is_source, // rt is source
output ex_imm_command,
output reg ex_alu_src_b,
output reg ex_alu_rslt_src, // ? PC + 8 : alu_result => EX_MEM_alu_rslt
output reg [1:0] ex_dst_reg_sel,
output reg [1:0] ex_alu_op,
output reg mem_read,
output reg mem_write,
output reg wb_mem_to_reg,
output reg wb_reg_write );
//opcodes
localparam LW = 6'b100011,
SW = 6'b101011,
BEQ = 6'b000100,
RTYPE = 6'b000000,
J = 6'b000010,
JAL = 6'b000011,
ADDI = 6'b001000,
ANDI = 6'b001100,
ORI = 6'b001101,
XORI = 6'b001110,
SLTI = 6'b001010,
//special
JR = 6'b001000;
//--------------------------------
reg memory_op;
reg r_type_op;
reg immediate_op;
reg branch_op;
reg jump_op;
assign ex_imm_command = immediate_op;
assign id_rt_is_source = (r_type_op | branch_op | opcode == SW);
always @* begin
//default values
if_pc_source = 0;
ex_alu_src_b = 0;
ex_alu_rslt_src = 0;
ex_dst_reg_sel = 0;
ex_alu_op = 0;
mem_read = 0;
mem_write = 0;
wb_mem_to_reg = 0;
wb_reg_write = 0;
memory_op = ( (opcode == LW) | (opcode == SW) );
r_type_op = ( opcode == RTYPE );
branch_op = ( opcode == BEQ );
immediate_op = ( (opcode == ADDI) | (opcode == ANDI) | (opcode == ORI) | (opcode == XORI) | (opcode == SLTI) );
jump_op = ( (opcode == J) | (opcode == JAL));
if (memory_op) begin
ex_alu_src_b = 1'b1; // select sign_extend_offset input
ex_dst_reg_sel = 2'b00; // rt
ex_alu_op = 2'b00; // add op
wb_mem_to_reg = 1'b1; // select mem_out
if ( opcode == LW ) begin
mem_read = 1'b1;
wb_reg_write = 1'b1;
end
else
mem_write = 1'b1; // opcode == SW
end
else if (r_type_op) begin
ex_alu_src_b = 1'b0; // select B input
ex_dst_reg_sel = 2'b01; // rd
ex_alu_op = 2'b10; // operaction defined by func code
wb_mem_to_reg = 1'b0; // alu_out
wb_reg_write = 1'b1; // write result to regfile
end
else if (immediate_op) begin
ex_alu_src_b = 1'b1; // select sign_extend_offset input
ex_dst_reg_sel = 2'b00; // rt
ex_alu_op = 2'b10; // operation defined by function code
wb_mem_to_reg = 1'b0; // alu_out
wb_reg_write = 1'b1;
end
else if (branch_op) begin
if (branch_eq)
if_pc_source = 2'b01; // PC <= branch_addr
else
if_pc_source = 2'b00;
end
else if (jump_op)
if_pc_source = 2'b10; // PC <= jump_addr
if( opcode == JAL ) begin
ex_dst_reg_sel = 2'b10;
ex_alu_rslt_src = 1'b1; // EX_MEM_alu_result <= PC + 8
wb_reg_write = 1'b1;
end
else if (~|opcode) begin
if(special == JR) begin
if_pc_source = 2'b11;
end
else begin
//NOP
end
end
else begin
//NOP
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__OR4_FUNCTIONAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> const int MAXN = 1005; int a[MAXN]; int cnt[MAXN]; int main() { int n, k; while (scanf( %d%d , &n, &k) + 1) { memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if ((j - i) * k == a[j] - a[i]) { cnt[i]++; } } } int mm = 0; int p = 0; for (int i = 1; i <= n; i++) { if (cnt[i] > mm && a[i] - (i - 1) * k > 0) { mm = cnt[i]; p = i; } } printf( %d n , n - mm); for (int i = 1; i <= n; i++) { if ((i - p) * k != a[i] - a[p]) { if (a[i] - a[p] > (i - p) * k) { printf( - %d %d n , i, a[i] - a[p] - (i - p) * k); } else { printf( + %d %d n , i, (i - p) * k - a[i] + a[p]); } } } } return 0; }
|
`include "lo_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_simulate;
reg pck0;
reg [7:0] adc_d;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
reg cross_lo;
wire cross_hi;
wire dbg;
lo_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg)
);
integer i, counter=0;
// main clock
always #5 pck0 = !pck0;
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
task crank_dut;
begin
@(posedge pck0) ;
counter = counter + 1;
if (counter == 192) begin
counter = 0;
ssp_dout = $random;
cross_lo = 1;
end else begin
cross_lo = 0;
end
end
endtask
initial begin
pck0 = 0;
for (i = 0 ; i < 4096 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; void JIZZ(string output = ) { cout << output; exit(0); } const long double PI = 3.14159265358979323846264338327950288; const long double eps = 1e-13; const long long mod = 1e9 + 7; long long a[200005], pre[200005]; vector<int> good; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; long long k; cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) pre[i] = pre[i - 1] + a[i]; for (int i = 1; i <= n; ++i) if (a[i] > 1) good.push_back(i); good.push_back(n + 1); if (0) { long long ans = 0; for (int i = 1; i <= n; ++i) { long long s = 0, p = 1; for (int j = i; j <= n; ++j) { if (((long double)p) * a[j] > 2e18) break; p *= a[j], s += a[j]; if (s * k == p) cout << i << << j << endl, ++ans; } } cout << ans << endl; } long long ans = 0; for (int i = 1; i <= n; ++i) { long long p = a[i], s = a[i]; int now = i; auto ptr = upper_bound(good.begin(), good.end(), i); if (s * k <= p && p <= (s + *ptr - now) * k && p % k == 0) ++ans; while (p <= 2e18) { if (*ptr == n + 1) break; if (((long double)p) * a[*ptr] > 2e18) break; p *= a[*ptr]; s += pre[*ptr] - pre[now]; now = *ptr; ++ptr; if (s * k <= p && p <= (s + *ptr - now - 1) * k && p % k == 0) ++ans; } } cout << ans << endl; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: phy_rdctrl_sync.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:34 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Synchronization of read control signal from MC/PHY rdlvl logic (clk) to
// read capture logic (clk_rsync) clock domain. Also adds additional delay
// to account for read latency
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_rdctrl_sync.v,v 1.2 2010/02/26 08:58:34 pboya Exp $
**$Date: 2010/02/26 08:58:34 $
**$Author: pboya $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_rdctrl_sync.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_rdctrl_sync #
(
parameter TCQ = 100
)
(
input clk,
input rst_rsync, // Use only CLK_RSYNC[0] reset
// Control for control sync logic
input mc_data_sel,
input [4:0] rd_active_dly,
// DFI signals from MC/PHY rdlvl logic
input dfi_rddata_en,
input phy_rddata_en,
// Control for read logic, initialization logic
output reg dfi_rddata_valid,
output reg dfi_rddata_valid_phy,
output reg rdpath_rdy // asserted when read path
// ready for use
);
// # of clock cycles after RST_RSYNC has deasserted before init/cal logic
// is taken out of reset. This is only needed for simulation when the "no
// init/no cal" option is selected. In this case, PHY_INIT will assert
// DFI_INIT_COMPLETE signal almost instantaneously once it is taken out
// of reset - however, there are certain pipe stages that must "flush
// out" (related to circular buffer synchronization) for a few cycles after
// RST_RSYNC is deasserted - in particular, the one related to generating
// DFI_RDDATA_VALID must not drive an unknown value on the bus after
// DFI_INIT_COMPLETE is asserted.
// NOTE: # of cycles of delay required depends on the circular buffer
// depth for RD_ACTIVE - it should >= (0.5*depth + 1)
localparam RDPATH_RDY_DLY = 10;
wire rddata_en;
wire rddata_en_rsync;
wire rddata_en_srl_out;
reg [RDPATH_RDY_DLY-1:0] rdpath_rdy_dly_r;
//***************************************************************************
// Delay RDDATA_EN by an amount determined during read-leveling
// calibration to reflect the round trip delay from command issuance until
// when read data is returned
//***************************************************************************
assign rddata_en = (mc_data_sel) ? dfi_rddata_en : phy_rddata_en;
// May need to flop output of SRL for better timing
SRLC32E u_rddata_en_srl
(
.Q (rddata_en_srl_out),
.Q31 (),
.A (rd_active_dly),
.CE (1'b1),
.CLK (clk),
.D (rddata_en)
);
// Flop once more for better timing
always @(posedge clk) begin
// Only assert valid on DFI bus after initialization complete
dfi_rddata_valid <= #TCQ rddata_en_srl_out & mc_data_sel;
// Assert valid for PHY during initialization
dfi_rddata_valid_phy <= #TCQ rddata_en_srl_out;
end
//***************************************************************************
// Generate a signal that tells initialization logic that read path is
// ready for use (i.e. for read leveling). Use RST_RSYNC, and delay it by
// RDPATH_RDY_DLY clock cycles, then synchronize to CLK domain.
// NOTE: This logic only required for simulation; for final h/w, there will
// always be a long delay between RST_RSYNC deassertion and
// DFI_INIT_COMPLETE assertion (for DRAM init, and leveling)
//***************************************************************************
// First delay by X number of clock cycles to guarantee that RDPATH_RDY
// isn't asserted too soon after RST_RSYNC is deasserted (to allow various
// synchronization pipe stages to "flush"). NOTE: Only RST_RSYNC[0] (or
// any of the up to 4 RST_RSYNC's) is used - any of them is sufficient
// close enough in timing to use
always @(posedge clk or posedge rst_rsync) begin
if (rst_rsync)
rdpath_rdy_dly_r <= #TCQ {{RDPATH_RDY_DLY}{1'b0}};
else
rdpath_rdy_dly_r[RDPATH_RDY_DLY-1:1]
<= #TCQ {rdpath_rdy_dly_r[RDPATH_RDY_DLY-2:0], 1'b1};
end
// Flop once more to prevent ISE tools from analyzing asynchronous path
// through this flop to receiving logic
always @(posedge clk)
rdpath_rdy <= rdpath_rdy_dly_r[RDPATH_RDY_DLY-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, fwt[262144]; vector<int> a1, b1, c1, d1, e1, ans; void add(int x, int k) { for (; x < 262144; x += x & -x) { fwt[x] += k; } } int sum(int x) { int res = 0; for (; x; x -= x & -x) { res += fwt[x]; } return res; } int findSidx(int sum) { int x = 0; for (int j = 262144 / 2; j; j /= 2) { if (sum >= fwt[x + j]) { sum -= fwt[x + j]; x += j; } } return x; } vector<int> deB(vector<int>& a) { memset(fwt, 0, sizeof fwt); vector<int> res; for (int i = 0; i < n; ++i) { add(i + 1, 1); } for (int i = 0; i < n; ++i) { add(a[i] + 1, -1); res.push_back(sum(a[i] + 1)); } return res; } void makeA() { memset(fwt, 0, sizeof fwt); ans.resize(n, 0); for (int i = 0; i < n; ++i) { add(i + 1, 1); } for (int i = 0; i < n; ++i) { ans[i] = findSidx(e1[i]); add(ans[i] + 1, -1); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; a1.resize(n); b1.resize(n); e1.resize(n, 0); for (int i = 0; i < n; ++i) { cin >> a1[i]; } for (int j = 0; j < n; ++j) { cin >> b1[j]; } c1 = deB(a1), d1 = deB(b1); for (int i = n - 1; i >= 0; --i) { e1[i] += c1[i] + d1[i]; if (i) { e1[i - 1] += e1[i] / (n - i); } e1[i] %= (n - i); } makeA(); for (int i = 0; i < n; ++i) { cout << ans[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; int n, k; long long f[100009], g[100009]; vector<int> p; string s1, s2; int main() { cin >> s1 >> s2 >> k; int i; n = s1.size(); p.clear(); for (i = 1; i <= n; ++i) { if (s1 == s2) p.push_back(i - 1); s1.push_back(s1[0]); s1.erase(0, 1); } f[0] = 1LL; g[0] = 0LL; for (i = 1; i <= k; ++i) { f[i] = (g[i - 1] * (n - 1)) % MOD; g[i] = (f[i - 1] + g[i - 1] * (n - 2)) % MOD; } long long ans = 0LL; if (!p.empty()) { for (i = 0; i < p.size(); ++i) { if (p[i] == 0) ans = (ans + f[k]) % MOD; else ans = (ans + g[k]) % MOD; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const double eps = 1e-4, pi = acos(-1.0); const int maxS = 1e3 + 13; const int maxT = 20; const long long MOD = 1e9 + 7; using namespace std; struct point { int x, y; }; struct rs { int x, y, z; }; int n, m, i, j, k, x, y, z, S, T, ii, s, t, l, r, pos, len; int tot = 0, ans = 0, res = 0, kase = 0, cnt = 0; bool chk[maxS][maxS], flag = true; string s1, s2; char ch[maxS][maxS]; vector<rs> v; point dr[5] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {0, 0}}; bool fk(int x, int y, int len) { if (x - len < 0 || y - len < 0 || x + len >= n || y + len >= m) return false; int i; for (i = x - len; i <= x + len; i++) if (ch[i][y] == . ) return false; for (i = y - len; i <= y + len; i++) if (ch[x][i] == . ) return false; for (i = x - len; i <= x + len; i++) chk[i][y] = false; for (i = y - len; i <= y + len; i++) chk[x][i] = false; v.push_back({x, y, len}); return true; } bool ok(int x, int y) { int i, j, k, len; for (k = 0; k < 5; k++) { for (i = 1; i < max(n, m); i++) if (fk(x + dr[k].x * i, y + dr[k].y * i, i)) return true; } return false; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { cin >> ch[i][j]; if (ch[i][j] == * ) chk[i][j] = true; } for (i = 0; i < n; i++) for (j = 0; j < m; j++) if (flag && chk[i][j] && !ok(i, j)) flag = false; if (!flag) cout << -1 << endl; else { cout << v.size() << endl; for (auto t : v) cout << t.x + 1 << << t.y + 1 << << t.z << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k; cin >> n >> k; long long a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; } std::map<long long, long long> m; for (int i = 0; i < n; ++i) { m[a[i]]++; } long long l = 1, r = n / k, mid; multiset<long long> ans, s; multiset<long long>::iterator it; map<long long, long long> m1; while (l <= r) { mid = l + (r - l) / 2; long long c = 0; m1 = m; s.clear(); for (int i = 0; i < n; ++i) { if (m1[a[i]] >= mid) { s.insert(a[i]); c++; m1[a[i]] -= mid; } if (c == k) { break; } } if (c >= k) { ans = s; l = mid + 1; } else { r = mid - 1; } } for (it = ans.begin(); it != ans.end(); it++) { cout << *it << ; } cout << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: serdes_1_to_n_clk_ddr_s8_se.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors
// from 2 to 8 with single ended inputs
// Instantiates necessary BUFIO2 clock buffers
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serdes_1_to_n_clk_ddr_s8_se (clkin1, clkin2, rxioclkp, rxioclkn, rx_serdesstrobe, rx_bufg_x1) ;
parameter integer S = 8 ; // Parameter to set the serdes factor 1..8
input clkin1 ; // Input from single ended receiver pin
input clkin2 ; // Input from single ended receiver pin
output rxioclkp ; // IO Clock network
output rxioclkn ; // IO Clock network
output rx_serdesstrobe ; // Parallel data capture strobe
output rx_bufg_x1 ; // Global clock output
wire ddly_m; // Master output from IODELAY1
wire ddly_s; // Slave output from IODELAY1
wire rx_clk_in ; //
wire iob_data_in_p ; //
wire iob_data_in_n ; //
parameter RX_SWAP_CLK = 1'b0 ; // pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
IBUFG iob_clk_in1 (
.I (clkin1),
.O (rx_clk_in_p)) ;
IBUFG iob_clk_in2 (
.I (clkin2),
.O (rx_clk_in_n)) ;
assign iob_data_in_p = rx_clk_in_p ^ RX_SWAP_CLK ; // Invert clock as required
assign iob_data_in_n = ~rx_clk_in_n ^ RX_SWAP_CLK ; // Invert clock as required, remembering the 2nd parallel clock input needs to be inverted
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.SIM_TAPDELAY_VALUE (49), // nominal tap delay (sim parameter only)
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL"), // "NORMAL", "PCI"
.SERDES_MODE ("MASTER"), // <NONE>, MASTER, SLAVE
.IDELAY_TYPE ("FIXED"), // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN")) // "IO", "IDATAIN", "ODATAIN"
iodelay_m (
.IDATAIN (iob_data_in_p), // data from master IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (1'b0), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (1'b0), // Fabric clock (GCLK) for control signals
.CAL (1'b0), // Calibrate enable signal
.INC (1'b0), // Increment counter
.CE (1'b0), // Clock Enable
.RST (1'b0), // Reset delay line to 1/2 max in this case
.BUSY ()) ; // output signal indicating sync circuit has finished / calibration has finished
IODELAY2 #(
.DATA_RATE ("SDR"), // <SDR>, DDR
.SIM_TAPDELAY_VALUE (49), // nominal tap delay (sim parameter only)
.IDELAY_VALUE (0), // {0 ... 255}
.IDELAY2_VALUE (0), // {0 ... 255}
.ODELAY_VALUE (0), // {0 ... 255}
.IDELAY_MODE ("NORMAL"), // "NORMAL", "PCI"
.SERDES_MODE ("SLAVE"), // <NONE>, MASTER, SLAVE
.IDELAY_TYPE ("FIXED"), // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), // <STAY_AT_LIMIT>, WRAPAROUND
.DELAY_SRC ("IDATAIN")) // "IO", "IDATAIN", "ODATAIN"
iodelay_s (
.IDATAIN (iob_data_in_n), // data from slave IOB
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (1'b0), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (1'b0), // Fabric clock (GCLK) for control signals
.CAL (1'b0), // Calibrate control signal, never needed as the slave supplies the clock input to the PLL
.INC (1'b0), // Increment counter
.CE (1'b0), // Clock Enable
.RST (1'b0), // Reset delay line
.BUSY ()) ; // output signal indicating sync circuit has finished / calibration has finished
BUFG bufg_pll_x1 (.I(rx_bufio2_x1), .O(rx_bufg_x1) ) ;
BUFIO2_2CLK #(
.DIVIDE (S)) // The DIVCLK divider divide-by value; default 1
bufio2_2clk_inst (
.I (ddly_m), // Input source clock 0 degrees
.IB (ddly_s), // Input source clock 0 degrees
.IOCLK (rxioclkp), // Output Clock for IO
.DIVCLK (rx_bufio2_x1), // Output Divided Clock
.SERDESSTROBE (rx_serdesstrobe)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst (
.I (ddly_s), // N_clk input from IDELAY
.IOCLK (rxioclkn), // Output Clock
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
endmodule
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#include <bits/stdc++.h> using namespace std; bool win(long long a, long long b) { if (a > b) swap(a, b); if (a == 0) return false; if (!win(b % a, a)) return true; long long df = b - b % a; if (a % 2) return df % 2 == 0; else return df / a % (a + 1) % 2 == 0; } void solve() { long long a, b; cin >> a >> b; if (win(a, b)) cout << First << endl; else cout << Second << endl; } int main() { ios_base::sync_with_stdio(0); int T; cin >> T; for (int _ = 0; _ < (int)(T); _++) solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISOBUFSRC_FUNCTIONAL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_FUNCTIONAL_V
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