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/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* System top level
*/
`include "config.vh"
`include "common.vh"
`include "ocp_const.vh"
/*
* System top
*/
module sys_top (
clk,
nrst
);
input wire clk;
input wire nrst;
/** Local interconnect **/
/* CPU I-Bus */
wire [`ADDR_WIDTH-1:0] C_IAddr;
wire C_IRdC;
wire [`DATA_WIDTH-1:0] C_IData;
wire C_IRdy;
wire C_IErr;
/* CPU D-Bus */
wire [`ADDR_WIDTH-1:0] C_DAddr;
wire C_DCmd;
wire C_DRnW;
wire [`BEN_WIDTH-1:0] C_DBen;
wire [`DATA_WIDTH-1:0] C_DDataM;
wire [`DATA_WIDTH-1:0] C_DDataS;
wire C_DRdy;
wire C_DErr;
/* OCP I-Port */
wire [`ADDR_WIDTH-1:0] I_MAddr;
wire [2:0] I_MCmd;
wire [`DATA_WIDTH-1:0] I_MData;
wire [`BEN_WIDTH-1:0] I_MByteEn;
wire I_SCmdAccept;
wire [`DATA_WIDTH-1:0] I_SData;
wire [1:0] I_SResp;
/* OCP D-Port */
wire [`ADDR_WIDTH-1:0] D_MAddr;
wire [2:0] D_MCmd;
wire [`DATA_WIDTH-1:0] D_MData;
wire [`BEN_WIDTH-1:0] D_MByteEn;
wire D_SCmdAccept;
wire [`DATA_WIDTH-1:0] D_SData;
wire [1:0] D_SResp;
/* Slave ports */
wire [`ADDR_WIDTH-1:0] P_MAddr[0:4];
wire [2:0] P_MCmd[0:4];
wire [`DATA_WIDTH-1:0] P_MData[0:4];
wire [`BEN_WIDTH-1:0] P_MByteEn[0:4];
wire P_SCmdAccept[0:4];
wire [`DATA_WIDTH-1:0] P_SData[0:4];
wire [1:0] P_SResp[0:4];
/* CPU interrupt */
wire intr;
/* Timer interrupt */
wire timer_intr;
/* IBus-to-OCP */
`ifdef CONFIG_FABRIC2
ibus2ocp2 ibus_ocp(
.clk(clk),
.nrst(nrst),
`else
ibus2ocp ibus_ocp(
`endif
.i_IAddr(C_IAddr),
.i_IRdC(C_IRdC),
.o_IData(C_IData),
.o_IRdy(C_IRdy),
.o_IErr(C_IErr),
.o_MAddr(I_MAddr),
.o_MCmd(I_MCmd),
.o_MData(I_MData),
.o_MByteEn(I_MByteEn),
.i_SCmdAccept(I_SCmdAccept),
.i_SData(I_SData),
.i_SResp(I_SResp)
);
/* DBus-to-OCP */
`ifdef CONFIG_FABRIC2
dbus2ocp2 dbus_ocp(
.clk(clk),
.nrst(nrst),
`else
dbus2ocp dbus_ocp(
`endif
.i_DAddr(C_DAddr),
.i_DCmd(C_DCmd),
.i_DRnW(C_DRnW),
.i_DBen(C_DBen),
.i_DData(C_DDataM),
.o_DData(C_DDataS),
.o_DRdy(C_DRdy),
.o_DErr(C_DErr),
.o_MAddr(D_MAddr),
.o_MCmd(D_MCmd),
.o_MData(D_MData),
.o_MByteEn(D_MByteEn),
.i_SCmdAccept(D_SCmdAccept),
.i_SData(D_SData),
.i_SResp(D_SResp)
);
/* CPU */
uparc_cpu_top cpu(
.clk(clk),
.nrst(nrst),
.i_intr(intr),
.o_IAddr(C_IAddr),
.o_IRdC(C_IRdC),
.i_IData(C_IData),
.i_IRdy(C_IRdy),
.i_IErr(C_IErr),
.o_DAddr(C_DAddr),
.o_DCmd(C_DCmd),
.o_DRnW(C_DRnW),
.o_DBen(C_DBen),
.o_DData(C_DDataM),
.i_DData(C_DDataS),
.i_DRdy(C_DRdy),
.i_DErr(C_DErr)
);
/* Memory */
memory mem(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[0]),
.i_MCmd(P_MCmd[0]),
.i_MData(P_MData[0]),
.i_MByteEn(P_MByteEn[0]),
.o_SCmdAccept(P_SCmdAccept[0]),
.o_SData(P_SData[0]),
.o_SResp(P_SResp[0])
);
/* micro UART */
micro_uart uart(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[1]),
.i_MCmd(P_MCmd[1]),
.i_MData(P_MData[1]),
.i_MByteEn(P_MByteEn[1]),
.o_SCmdAccept(P_SCmdAccept[1]),
.o_SData(P_SData[1]),
.o_SResp(P_SResp[1])
);
/* Control device */
sim_control sim_ctl(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[2]),
.i_MCmd(P_MCmd[2]),
.i_MData(P_MData[2]),
.i_MByteEn(P_MByteEn[2]),
.o_SCmdAccept(P_SCmdAccept[2]),
.o_SData(P_SData[2]),
.o_SResp(P_SResp[2])
);
/* Interrupt controller */
intr_controller intr_ctrl(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[3]),
.i_MCmd(P_MCmd[3]),
.i_MData(P_MData[3]),
.i_MByteEn(P_MByteEn[3]),
.o_SCmdAccept(P_SCmdAccept[3]),
.o_SData(P_SData[3]),
.o_SResp(P_SResp[3]),
.o_intr(intr),
.i_intr_vec({31'b0, timer_intr})
);
/* Interval timer */
interval_timer timer(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[4]),
.i_MCmd(P_MCmd[4]),
.i_MData(P_MData[4]),
.i_MByteEn(P_MByteEn[4]),
.o_SCmdAccept(P_SCmdAccept[4]),
.o_SData(P_SData[4]),
.o_SResp(P_SResp[4]),
.o_intr(timer_intr)
);
/* Fabric */
`ifdef CONFIG_FABRIC2
fabric2 fab(
`else
fabric fab(
`endif
.clk(clk),
.nrst(nrst),
/* OCP interface: instructions (master) */
.i_I_MAddr(I_MAddr), .i_I_MCmd(I_MCmd),
.i_I_MData(I_MData), .i_I_MByteEn(I_MByteEn),
.o_I_SCmdAccept(I_SCmdAccept), .o_I_SData(I_SData),
.o_I_SResp(I_SResp),
/* OCP interface: data (master) */
.i_D_MAddr(D_MAddr), .i_D_MCmd(D_MCmd),
.i_D_MData(D_MData), .i_D_MByteEn(D_MByteEn),
.o_D_SCmdAccept(D_SCmdAccept), .o_D_SData(D_SData),
.o_D_SResp(D_SResp),
/* OCP interface: Port 0 (slave) */
.o_P0_MAddr(P_MAddr[0]), .o_P0_MCmd(P_MCmd[0]),
.o_P0_MData(P_MData[0]), .o_P0_MByteEn(P_MByteEn[0]),
.i_P0_SCmdAccept(P_SCmdAccept[0]), .i_P0_SData(P_SData[0]),
.i_P0_SResp(P_SResp[0]),
/* OCP interface: Port 1 (slave) */
.o_P1_MAddr(P_MAddr[1]), .o_P1_MCmd(P_MCmd[1]),
.o_P1_MData(P_MData[1]), .o_P1_MByteEn(P_MByteEn[1]),
.i_P1_SCmdAccept(P_SCmdAccept[1]), .i_P1_SData(P_SData[1]),
.i_P1_SResp(P_SResp[1]),
/* OCP interface: Port 2 (slave) */
.o_P2_MAddr(P_MAddr[2]), .o_P2_MCmd(P_MCmd[2]),
.o_P2_MData(P_MData[2]), .o_P2_MByteEn(P_MByteEn[2]),
.i_P2_SCmdAccept(P_SCmdAccept[2]), .i_P2_SData(P_SData[2]),
.i_P2_SResp(P_SResp[2]),
/* OCP interface: Port 3 (slave) */
.o_P3_MAddr(P_MAddr[3]), .o_P3_MCmd(P_MCmd[3]),
.o_P3_MData(P_MData[3]), .o_P3_MByteEn(P_MByteEn[3]),
.i_P3_SCmdAccept(P_SCmdAccept[3]), .i_P3_SData(P_SData[3]),
.i_P3_SResp(P_SResp[3]),
/* OCP interface: Port 4 (slave) */
.o_P4_MAddr(P_MAddr[4]), .o_P4_MCmd(P_MCmd[4]),
.o_P4_MData(P_MData[4]), .o_P4_MByteEn(P_MByteEn[4]),
.i_P4_SCmdAccept(P_SCmdAccept[4]), .i_P4_SData(P_SData[4]),
.i_P4_SResp(P_SResp[4])
);
endmodule /* sys_top */
|
module test(
input rst,
input clk,
input a0,
input wr_n,
input [ 7:0] din,
output signed [15:0] xleft,
output signed [15:0] xright,
output sample,
output [ 7:0] dout
);
wire wr_n, cen_fm, cen_fm2;
wire a0;
wire [7:0] din, dout;
jtframe_cen3p57 u_cen(
.clk ( clk ), // 48 MHz
.cen_3p57 ( cen_fm ),
.cen_1p78 ( cen_fm2 )
);
wire ct1, ct2, irq_n;
jt51 uut(
.rst ( rst ), // reset
.clk ( clk ), // main clock
.cen ( cen_fm ), // clock enable
.cen_p1 ( cen_fm2 ), // clock enable at half the speed
.cs_n ( 1'b0 ), // chip select
.wr_n ( wr_n ), // write
.a0 ( a0 ),
.din ( din ), // data in
.dout ( dout ), // data out
// peripheral control
.ct1 ( ct1 ),
.ct2 ( ct2 ),
.irq_n ( irq_n ), // I do not synchronize this signal
// Low resolution output (same as real chip)
.sample ( sample ), // marks new output sample
.left ( ),
.right ( ),
// Full resolution output
.xleft ( xleft ),
.xright ( xright ),
// unsigned outputs for sigma delta converters, full resolution
.dacleft ( ),
.dacright ( )
);
endmodule
module jtframe_cen3p57(
input clk, // 48 MHz
output reg cen_3p57,
output reg cen_1p78
);
wire [10:0] step=11'd105;
wire [10:0] lim =11'd1408;
wire [10:0] absmax = lim+step;
reg [10:0] cencnt=11'd0;
reg [10:0] next;
reg [10:0] next2;
always @(*) begin
next = cencnt+11'd105;
next2 = next-lim;
end
reg alt=1'b0;
always @(posedge clk) begin
cen_3p57 <= 1'b0;
cen_1p78 <= 1'b0;
if( cencnt >= absmax ) begin
// something went wrong: restart
cencnt <= 11'd0;
alt <= 1'b0;
end else
if( next >= lim ) begin
cencnt <= next2;
cen_3p57 <= 1'b1;
alt <= ~alt;
if( alt ) cen_1p78 <= 1'b1;
end else begin
cencnt <= next;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_32 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data.
tx_port_buffer_32 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(),
.TX_SENT(TX_SENT)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; struct Graph { int head[N], v[N << 1], w[N << 1], next[N << 1], e; void clear() { e = 0; memset(head, -1, sizeof(head)); } void add(int u, int v, int w) { this->v[e] = v; this->w[e] = w; next[e] = head[u]; head[u] = e++; } } G; int n, a[N], ans[N], id[N]; long long pre[N]; void dfs(int u, int d, long long sum) { id[d] = u; pre[d] = sum; int p = lower_bound(pre + 1, pre + 1 + d, sum - a[u]) - pre; ans[id[d - 1]]++; ans[id[p - 1]]--; for (int e = G.head[u]; ~e; e = G.next[e]) { int v = G.v[e], w = G.w[e]; dfs(v, d + 1, sum + w); ans[u] += ans[v]; } } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , a + i); } G.clear(); for (int i = 2; i <= n; i++) { int p, w; scanf( %d%d , &p, &w); G.add(p, i, w); } dfs(1, 1, 0); for (int i = 1; i <= n; i++) { printf( %d%c , ans[i], n [i == n]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long modulo(long long base, long long exp, long long m); int main() { int x; cin >> x; if (x <= 1) cout << -1 ; else { cout << x << << x; } return 0; } long long modulo(long long base, long long exp, long long m) { long long answer = 1; while (exp > 0) { if (exp % 2 == 1) answer = (answer * base) % m; exp = exp / 2; base = (base * base) % m; } return answer; }
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; cout << a[0]; for (int e = 1; e < a.size(); e++) if (a[e] < b[0]) cout << a[e]; else break; cout << b[0] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; int n; int data[maxn]; int f[25][maxn]; bool mark[(1 << 25)], tt; int res = 0, p; int tmp; int tm, tp; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> data[i]; memset(mark, 0, sizeof(mark)); for (int k = 0; k <= 20; k++) { p = -1; for (int i = n; i >= 1; i--) { if ((data[i] & (1 << k)) == 0) { if (p == -1) { p = i; } f[k][i] = p; } else p = -1; } } for (int i = 1; i <= n; i++) { tmp = data[i]; if (!mark[tmp]) { mark[tmp] = 1; res++; } p = i; while (p <= n) { tm = n + 1; for (int k = 0; k <= 20; k++) if ((tmp & (1 << k)) == 0 && f[k][i] < tm && f[k][i] > 0) { tp = k; tm = f[k][i]; } if (tm >= n) break; for (int k = 0; k <= 20; k++) if (f[k][i] == tm) tmp += (1 << k); if (!mark[tmp]) { mark[tmp] = 1; res++; } p = tm + 1; } } cout << res << endl; return 0; }
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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module bit_capture_control(
input negedge_clk,
input posedge_clk,
input rx_resetn,
input rx_din,
output reg bit_c_0,
output reg bit_c_1,
output reg bit_c_2,
output reg bit_c_3
);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
end
else
begin
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
end
end
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
bit_c_0 <= 1'b0;
bit_c_2 <= 1'b0;
end
else
begin
bit_c_0 <= rx_din;
bit_c_2 <= bit_c_0;
end
end
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
//Date : Sat Sep 23 22:44:16 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target zqynq_lab_1_design_wrapper.bd
//Design : zqynq_lab_1_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module zqynq_lab_1_design_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_5bits_tri_i,
leds_8bits_tri_o);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [4:0]btns_5bits_tri_i;
output [7:0]leds_8bits_tri_o;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [4:0]btns_5bits_tri_i;
wire [7:0]leds_8bits_tri_o;
zqynq_lab_1_design zqynq_lab_1_design_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.btns_5bits_tri_i(btns_5bits_tri_i),
.leds_8bits_tri_o(leds_8bits_tri_o));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, h, ok; long long cal(long long dep, long long pos, int tag) { if (ok) return 0; if (dep == 0) { ok = 1; return 0; } long long tmp; if (!tag) { if (pos > (1LL << (dep - 1))) tmp = (1LL << dep) + cal(dep - 1, pos - (1LL << (dep - 1)), 0); else tmp = 1LL + cal(dep - 1, pos, 1); } else { if (pos > (1LL << (dep - 1))) tmp = 1LL + cal(dep - 1, pos - (1LL << (dep - 1)), 0); else tmp = (1LL << dep) + cal(dep - 1, pos, 1); } return tmp; } int main() { while (cin >> h >> n) { ok = 0; cout << cal(h, n, 0) << endl; } }
|
#include <bits/stdc++.h> int main() { int n, i, ans = 0, a[200001] = {0}; scanf( %d , &n); for (i = 0; i < n; i++) { int x; scanf( %d , &x); if (a[100000 + x] == 0 && x != 0) { ans++; a[100000 + x] = 1; } } printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_2_V
`define SKY130_FD_SC_LS__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_SYMBOL_V
`define SKY130_FD_SC_LP__AND3B_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void File_input() { freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); } void FastInputOutput() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); } vector<char> geno[ z + 1]; int t, n; string str; bool vis[ z + 1], in[ z + 1]; int indeg[ z + 1]; void DFS(char a) { cout << a; for (auto i : geno[a]) { if (!vis[i]) { vis[i] = 1; DFS(i); } } } int main() { cin >> t; while (t--) { cin >> str; n = (long long)str.size(); for (int i = 0; i < n; i++) in[str[i]] = 1; for (int i = 1; i < n; i++) { geno[str[i - 1]].push_back(str[i]); indeg[str[i]]++; } } for (char a = a ; a <= z ; a++) { if (!vis[a] && in[a] && !indeg[a]) { DFS(a); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_SYMBOL_V
`define SKY130_FD_SC_MS__DLXBN_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long temp = 0, r, l, w, k = 0, m1, e, p, q, ans = 0, k1 = 0, k2 = 0, d = 0, a = 0, b = 0, s = 0, x, y, min1 = 1000000010, max1 = 0, m, c = 0, t = 0, i, n, c1 = 0, tot = 0, t1, k4 = 0, c2 = 0, j = 0, k3 = 0; char ch, ch1, ch2; string s1, s2, s3; signed main() { cin >> s1 >> s2; n = s1.length(); if (n == 1) { cout << 0; return 0; } k = 0; vector<long long> v1(110, 0), v2(110, 0); for (long long i = 1; i < n; i++) { if (s1[i] == s1[i - 1] && s1[i] == 0 && s2[i - 1] == 0 && !v1[i - 1] && !v1[i] && !v2[i - 1]) { v1[i] = 1, v1[i - 1] = 1, v2[i - 1] = 1; c++; } else if (s1[i] == s1[i - 1] && s1[i] == 0 && s2[i] == 0 && !v1[i - 1] && !v1[i] && !v2[i]) { v1[i] = 1, v1[i - 1] = 1, v2[i] = 1; c++; } else if (s2[i] == s2[i - 1] && s2[i] == 0 && s1[i - 1] == 0 && !v2[i - 1] && !v2[i] && !v1[i - 1]) { v2[i] = 1, v2[i - 1] = 1, v1[i - 1] = 1; c++; } else if (s2[i] == s2[i - 1] && s2[i] == 0 && s1[i] == 0 && !v2[i - 1] && !v2[i] && !v1[i]) { v2[i] = 1, v2[i - 1] = 1, v1[i] = 1; c++; } } cout << c; }
|
module ALU(
output reg [31:0] alu_out,
output flag_z, flag_v, flag_n,
input [31:0] in0, in1, //in0 is rs, in1 can be rt or sign/unsign-extended immediate value
input [4:0] shamt,
input [15:0] perf_cnt, //input from performance counter
input alu_ctrl0, alu_ctrl1, alu_ctrl2, alu_ctrl3
);
localparam ADD = 4'h0, SUB = 4'h1, LUI = 4'h2, MOV = 4'h3;
localparam AND = 4'h4, SLL = 4'h5, SRA = 4'h6, SRL = 4'h7;
localparam NOT = 4'h8, OR = 4'h9, XOR = 4'ha, ADDB = 4'hb;
localparam ADDBI = 4'hc, SUBB = 4'hd, SUBBI = 4'he, LLDC = 4'hf; //LDC stands for load counters
wire [3:0] alu_ctrl = {alu_ctrl3, alu_ctrl2, alu_ctrl1, alu_ctrl0};
//////wires for shift
wire [31:0] dsll0, dsll1, dsll2, dsll3, dsll4;
wire [31:0] dsrl0, dsrl1, dsrl2, dsrl3, dsrl4;
wire [31:0] dsra0, dsra1, dsra2, dsra3, dsra4;
//////wires for byte-wise arithmetic
wire [8:0] addb0_int, addb1_int, addb2_int, addb3_int;
wire [7:0] addb0, addb1, addb2, addb3;
wire [7:0] subb0, subb1, subb2, subb3;
//////ALU result
always @(alu_ctrl or in0 or in1) begin
case (alu_ctrl)
ADD: alu_out = in0 + in1;
SUB: alu_out = in0 - in1;
LUI: alu_out = {in1[15:0], 16'h0000}; //the concatenation is done before going into ALU
MOV: alu_out = in0;
AND: alu_out = in0 & in1;
SLL: alu_out = dsll4;
SRA: alu_out = dsra4;
SRL: alu_out = dsrl4;
NOT: alu_out = ~in0;
OR: alu_out = in0 | in1;
XOR: alu_out = in0 ^ in1;
ADDB: alu_out = {addb3, addb2, addb1, addb0}; //currently don't care about the correctness of these byte-wise ops
ADDBI: alu_out = {addb3, addb2, addb1, addb0};
SUBB: alu_out = {subb3, subb2, subb1, subb0};
SUBBI: alu_out = {subb3, subb2, subb1, subb0};
LLDC: alu_out = {16'h0000, perf_cnt};
endcase
end
//////flags //////our flag only used in branch instruction, we don't have overflow exception
assign flag_z = ~(|alu_out);
assign flag_n = alu_out[31];
assign flag_v = (in0[31] & in1[31] & ~alu_out[31]) || (~in0[31] & ~in1[31] & alu_out[31]);
///////////////////////////////////////////////////////////////////////////////////////////////
//////////////////log shifter//////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////
//shifter left logically (SLL) block
assign dsll0 = shamt[0] ? {in0[30:0], 1'b0} : in0; //shift left logic/arithmetic
assign dsll1 = shamt[1] ? {dsll0[29:0], 2'b00} : dsll0;
assign dsll2 = shamt[2] ? {dsll1[27:0], 4'h0} : dsll1;
assign dsll3 = shamt[3] ? {dsll2[23:0], 8'h00} : dsll2;
assign dsll4 = shamt[4] ? {dsll3[15:0], 16'h0000} : dsll3;
//SRL block
assign dsrl0 = shamt[0] ? {1'b0, in0[31:1]} : in0; //shift right logically
assign dsrl1 = shamt[1] ? {2'b00, dsrl0[31:2]} : dsrl0;
assign dsrl2 = shamt[2] ? {4'h0, dsrl1[31:4]} : dsrl1;
assign dsrl3 = shamt[3] ? {8'h00, dsrl2[31:8]} : dsrl2;
assign dsrl4 = shamt[4] ? {16'h0000, dsrl3[31:16]} : dsrl3;
//SRA block
assign dsra0 = shamt[0] ? { in0[31], in0[31:1]} : in0;
assign dsra1 = shamt[1] ? { {2{dsra0[31]}} , dsra0[31:2]} : dsra0; //shift right arithmetically
assign dsra2 = shamt[2] ? { {4{dsra1[31]}} , dsra1[31:4]} : dsra1;
assign dsra3 = shamt[3] ? { {8{dsra2[31]}} , dsra2[31:8]} : dsra2;
assign dsra4 = shamt[4] ? { {16{dsra3[31]}} , dsra3[31:16]} : dsra3;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////saturating unsigned arithmetic for byte-wise operation//////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
assign addb0_int = in0[7:0] + in1[7:0];
assign addb1_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[15:8] + in1[15:8];
assign addb2_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[23:16] + in1[23:16];
assign addb3_int = (alu_ctrl == ADDBI) ? in0[15:8] + in1[7:0] : in0[31:24] + in1[31:24];
assign addb0 = addb0_int[8] ? 8'hFF : addb0_int[7:0];
assign addb1 = addb1_int[8] ? 8'hFF : addb1_int[7:0];
assign addb2 = addb2_int[8] ? 8'hFF : addb2_int[7:0];
assign addb3 = addb3_int[8] ? 8'hFF : addb3_int[7:0];
assign subb0 = in0[7:0] - in1[7:0];
assign subb1 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[15:8] - in1[15:8];
assign subb2 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[23:16] - in1[23:16];
assign subb3 = (alu_ctrl == SUBBI) ? in0[15:8] - in1[7:0] : in0[31:24] - in1[31:24];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; long long x, q, b; for (int i = k - 1; i >= 1; i--) { x = n / i * k + i; q = x % k; b = x / k; if (q * b == n) return cout << x, 0; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100100; const int MAXK = 17; int X[MAXN]; long long Y[MAXN]; int N, M; int par[MAXN][MAXK]; int dpth[MAXN]; int Q[MAXN]; int ql = 0, qr = 0; int main() { ios_base::sync_with_stdio(0); cin >> N; for (int i = 1; i <= N; ++i) { cin >> X[i] >> Y[i]; } for (int i = N; i > 0; --i) { while (ql + 1 < qr) { int a = Q[qr - 1], b = Q[qr - 2]; if ((Y[b] - Y[i]) * (X[a] - X[i]) > (Y[a] - Y[i]) * (X[b] - X[i])) { --qr; } else break; } if (ql < qr) { par[i][0] = Q[qr - 1]; dpth[i] = dpth[Q[qr - 1]] + 1; } else par[i][0] = i; Q[qr] = i; ++qr; } for (int k = 0; k + 1 < MAXK; ++k) { for (int i = 1; i <= N; ++i) { par[i][k + 1] = par[par[i][k]][k]; } } cin >> M; for (int q = 0; q < M; ++q) { int a, b; cin >> a >> b; if (dpth[a] < dpth[b]) swap(a, b); for (int i = MAXK - 1; i >= 0; --i) { if (dpth[par[a][i]] >= dpth[b]) { a = par[a][i]; } } for (int i = MAXK - 1; i >= 0; --i) { if (par[a][i] != par[b][i]) { a = par[a][i]; b = par[b][i]; } } if (a != b) { a = par[a][0]; b = par[b][0]; } if (a != b) printf( what n ); printf( %d , a); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[1100]; int main() { scanf( %s , s); for (int i = 0; s[i]; i++) printf( %c , s[i]); for (int i = strlen(s) - 1; i >= 0; i--) printf( %c , s[i]); return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mi = 2e9; long long ma = -2 * 1e9; const int N = 1e5 + 5; int main() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long na, nb, ka, kb; cin >> na >> nb >> ka >> kb; long long a[na], b[nb]; for (int i = 0; i < na; ++i) cin >> a[i]; for (int i = 0; i < nb; ++i) cin >> b[i]; sort(a, a + na); sort(b, b + nb); long long x = nb - kb; if (a[ka - 1] < b[nb - 1] && b[x] > a[ka - 1]) cout << YES ; else cout << NO ; }
|
// “Alhamdulillah for Everything” #include<bits/stdc++.h> using namespace std; #define pai acos(-1) #define ff first #define ss second #define ll long long #define pb push_back #define mp make_pair #define pll pair<ll,ll> #define sz(a) (ll)a.size() #define endl n #define gcd(a, b) __gcd(a, b) #define lcm(a, b) ((a*b)/gcd(a,b)) #define all(vec) vec.begin(),vec.end() #define ms(a, b) memset(a,b,sizeof(a)) #define rep(i,n) for(int i= 0; i < int(n); i++) #define rep1(i,n) for(int i= 1; i <= n; i++) #define TEST_CASE(t) for(int zz=1;zz<=t;zz++) #define PRINT_CASE printf( Case %d: ,zz) #define fii freopen( input.txt , r ,stdin); #define foo freopen( output.txt , w ,stdout); #define boom ios_base::sync_with_stdio(0);cin.tie(NULL);cout.tie(NULL); const ll M = 1e9+7; const ll mxn = 1e5+7; const ll inf = 1e18; int main() { //boom; ll i,j,k,a,b,c,d,n,m,t,x,y,z,u,v; cin>>t; TEST_CASE(t) { cin>>n>>k; vector<ll>vec(n); for(i=0;i<n;i++) { cin>>vec[i]; } ll ans=0,sum=vec[0]; for(i=1;i<n;i++) { a=vec[i]*100; b=sum*k; if(a<b) { sum+=vec[i]; } else { ll tem=a-b+k-1; tem/=k; sum+=(vec[i]+tem); ans+=tem; } //cout<<i<< === <<sum<< ==== <<ans<<endl; } cout<<ans<<endl; } return 0; }
|
// Data RAM
module data_mem
(
input wire clk,
input wire[31:0] addr_dmem_ram_i,
input wire[31:0] wr_data_dmem_ram_i,
input wire[0:3] wr_strb_dmem_ram_i,
input wire wr_en_dmem_ram_i,
output wire[31:0] read_data_dmem_ram_o
);
parameter data_seg_begin = 32'h1000,
data_seg_size = 32'h100000;
// Byte Addressable mem
reg [31:0] dmem [0:data_seg_size];
wire[31:0] read_data;
wire[31:0] wr_strb = {wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],
wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],wr_strb_dmem_ram_i[3],
wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],
wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],wr_strb_dmem_ram_i[2],
wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],
wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],wr_strb_dmem_ram_i[1],
wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],
wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0],wr_strb_dmem_ram_i[0]};
assign read_data_dmem_ram_o = read_data;
always @(posedge clk)
if (wr_en_dmem_ram_i)
dmem[((addr_dmem_ram_i - data_seg_begin)&(~32'h3))>>2] <= ((wr_data_dmem_ram_i & wr_strb) | (~wr_strb & read_data));
assign read_data = dmem[((addr_dmem_ram_i - data_seg_begin)&(~32'h3))>>2];
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(* ################################################################# *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (mostly works), and Scheme (a bit
out of date). *)
Require Coq.extraction.Extraction.
Extraction Language OCaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
From Coq Require Import Arith.Arith.
From Coq Require Import Init.Nat.
From Coq Require Import Arith.EqNat.
From LF Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ################################################################# *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant eqb => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ################################################################# *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we first need
to set up the right correspondence between Coq strings and lists
of OCaml characters. *)
Require Import ExtrOcamlBasic.
Require Import ExtrOcamlString.
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
From LF Require Import Imp.
From LF Require Import ImpParser.
From LF Require Import Maps.
Extraction "imp.ml" empty_st ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ################################################################# *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(* ################################################################# *)
(** * Going Further *)
(** Further details about extraction can be found in the Extract
chapter in _Verified Functional Algorithms_ (_Software
Foundations_ volume 3). *)
(* Wed Jan 9 12:02:46 EST 2019 *)
|
`timescale 1ns/10ps
`include "defines.v"
module pc_trace (
`ifdef DEBUG
output reg [ 2:0] old_zet_st,
output reg [19:0] dat,
output reg new_pc,
output reg st,
output reg stb,
output ack,
output [ 4:0] pack,
output addr_st,
`endif
// PAD signals
output trx_,
input clk,
input rst,
input [19:0] pc,
input [ 2:0] zet_st,
output reg block
);
`ifndef DEBUG
// Registers and nets
reg [19:0] dat;
reg [ 2:0] old_zet_st;
reg new_pc;
reg st;
reg stb;
wire ack;
`endif
wire op_st;
wire rom;
// Module instantiations
send_addr ser0 (
`ifdef DEBUG
.pack (pack),
.st (addr_st),
`endif
.trx_ (trx_),
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat),
.wb_we_i (stb),
.wb_stb_i (stb),
.wb_cyc_i (stb),
.wb_ack_o (ack)
);
// Continous assignments
assign op_st = (zet_st == 3'b0);
assign rom = pc[19:16]==4'hf || pc[19:16]==4'hc;
// Behaviour
// old_zet_st
always @(posedge clk)
old_zet_st <= rst ? 3'b0 : zet_st;
// new_pc
always @(posedge clk)
new_pc <= rst ? 1'b0
: (op_st ? (zet_st!=old_zet_st && !rom) : 1'b0);
// block
always @(posedge clk)
block <= rst ? 1'b0
: (new_pc ? (st & !ack) : (ack ? 1'b0 : block));
// dat
always @(posedge clk)
dat <= rst ? 20'h0
: ((new_pc & !st) ? pc : (ack ? pc : dat));
// stb
always @(posedge clk)
stb <= rst ? 1'b0 : (ack ? 1'b0 : (st | new_pc));
// st
always @(posedge clk)
st <= rst ? 1'b0
: (st ? (ack ? (new_pc | block) : 1'b1) : new_pc);
endmodule
|
#include <bits/stdc++.h> using namespace std; auto clk = clock(); mt19937_64 rang( chrono::high_resolution_clock::now().time_since_epoch().count()); void test_case() { long long int n; cin >> n; long long int a[n + 1]; long long int t = -1, b = -1, c = -1; for (long long int i = 1; i <= n; i++) { cin >> a[i]; } for (long long int i = 2; i <= n - 1; i++) { for (long long int j = i - 1; j >= 1; j--) { if (a[j] < a[i]) { t = j; break; } } for (long long int j = i + 1; j <= n; j++) { if (a[j] < a[i]) { c = j; break; } } if (t != -1 && c != -1) { b = i; break; } t = -1, c = -1; } if (b != -1) { cout << YES << endl; cout << t << << b << << c << endl; } else cout << NO << endl; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); cout << fixed << setprecision(10); long long int t = 1; cin >> t; while (t--) { test_case(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 6010; vector<int> a[N]; int L[N], cnt, r[N], n, res = 0; void Refresh() { L[0] = cnt = 0; for (int i = 1; i <= n + 1; i++) L[i] = 10000000; } void DFS(int u, int p) { int Oldval, Oldid, Oldcnt = cnt; if (cnt == 0 || r[u] > L[cnt]) L[++cnt] = r[u]; else { Oldid = lower_bound(L, L + n + 1, r[u]) - L; Oldval = L[Oldid]; L[Oldid] = r[u]; } res = max(res, cnt); for (int i = 0; i < a[u].size(); i++) { int v = a[u][i]; if (v != p) DFS(v, u); } if (Oldcnt != cnt) L[cnt--] = 10000000; else L[Oldid] = Oldval; } int main() { ios_base::sync_with_stdio(0); int u, v; cin >> n; for (int i = 1; i <= n; i++) cin >> r[i]; for (int i = 1; i < n; i++) { cin >> u >> v; a[u].push_back(v); a[v].push_back(u); } for (int i = 1; i <= n; i++) { Refresh(); DFS(i, 0); } cout << res; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2,unroll-loops ) using namespace std; const int inf = 1000000010; const long long INF = 1000000000000001000LL; const int mod = 1000000007; const int MAXN = 100200, SQ = 320, NSQ = MAXN / SQ + 1; int n, m, w, u, v, x, y, t, a, b, maxb; int A[MAXN], B[MAXN], ans[MAXN], lazy[NSQ]; pair<long long, long long> X[MAXN]; vector<int> vec[MAXN]; struct CHT { pair<long long, int> cht[SQ]; int L, R; inline long long Inter(pair<long long, long long> x, pair<long long, long long> y) { if (x.first == y.first) return (x <= y ? -INF : INF); return (x.second - y.second) / (y.first - x.first) + ((x.second - y.second) % (y.first - x.first) > 0); } inline void Add(int a) { while (R && Inter(X[cht[R - 1].second], X[a]) <= cht[R - 1].first) R--; if (!R) cht[R++] = {-INF, a}; else cht[R] = {Inter(X[cht[R - 1].second], X[a]), a}, R++; } inline pair<long long, long long> Get(long long x) { while (L + 1 < R && cht[L + 1].first <= x) L++; int i = cht[L].second; return {X[i].first * x + X[i].second, i}; } } cht[NSQ]; void Build(int id) { int tl = id * SQ, tr = min(MAXN, tl + SQ); cht[id].L = cht[id].R = 0; for (int i = tl; i < tr; i++) { X[i].second += lazy[id] * X[i].first; cht[id].Add(i); } lazy[id] = 0; } void Add(int l, int r, int val) { int idl = -1, idr = -1; while (l < r && l % SQ) idl = l / SQ, X[l].second += val * l, l++; while (l < r && r % SQ) idr = r / SQ, r--, X[r].second += val * r; while (l < r) lazy[l / SQ] += val, l += SQ; if (idl != -1) Build(idl); if (idr != -1) Build(idr); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> w; for (int i = 1; i <= n; i++) { cin >> A[i] >> B[i]; vec[B[i]].push_back(i); maxb = max(maxb, B[i]); } for (int i = 0; i < MAXN; i++) X[i].first = i; for (int i = 0; i * SQ < MAXN; i++) Build(i); int ted = n; for (int i = 0; i <= maxb + 1; i++) { pair<long long, long long> p = {-inf, -1}; for (int j = 0; j * SQ + SQ <= MAXN; j++) p = max(p, cht[j].Get(lazy[j])); cout << p.first + 1ll * ted * i * w << << p.second << n ; for (int j : vec[i]) Add(0, A[j] + 1, +1), ted--; } return 0; }
|
/*
########################################################################
########################################################################
*/
module ecfg_if (/*AUTOARG*/
// Outputs
mi_mmu_en, mi_dma_en, mi_cfg_en, mi_we, mi_addr, mi_din,
access_out, packet_out,
// Inputs
clk, access_in, packet_in, mi_dout0, mi_dout1, mi_dout2, mi_dout3,
wait_in
);
parameter RX = 0; //0,1
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h810;
/********************************/
/*Clocks/reset */
/********************************/
input clk;
/********************************/
/*Incoming Packet */
/********************************/
input access_in;
input [PW-1:0] packet_in;
/********************************/
/* Register Interface */
/********************************/
output mi_mmu_en;
output mi_dma_en;
output mi_cfg_en;
output mi_we;
output [14:0] mi_addr;
output [63:0] mi_din;
input [63:0] mi_dout0;
input [63:0] mi_dout1;
input [63:0] mi_dout2;
input [63:0] mi_dout3;
/********************************/
/* Outgoing Packet */
/********************************/
output access_out;
output [PW-1:0] packet_out;
input wait_in; //incoming wait
//wires
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [63:0] mi_dout_mux;
wire mi_rd;
wire access_forward;
wire rxsel;
wire mi_en;
//regs;
reg access_out;
reg [31:0] dstaddr_reg;
reg [31:0] srcaddr_reg;
reg [1:0] datamode_reg;
reg [3:0] ctrlmode_reg;
reg write_reg;
reg readback_reg;
reg [31:0] data_reg;
wire [31:0] data_out;
//parameter didn't seem to work
assign rxsel = RX;
//splicing packet
packet2emesh p2e (.access_out (),
.write_out (write),
.datamode_out (datamode[1:0] ),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (packet_in[PW-1:0])
);
//ENABLE SIGNALS
assign mi_match = access_in & (dstaddr[31:20]==ID);
//config select (group 2 and 3)
assign mi_cfg_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]=={2'b01,rxsel});
//dma select (group 5)
assign mi_dma_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]==3'h5) &
(dstaddr[5]==rxsel);
//mmu select
assign mi_mmu_en = mi_match &
(dstaddr[19:16]==4'hE) &
(dstaddr[15]==rxsel);
//read/write indicator
assign mi_en = (mi_mmu_en | mi_cfg_en | mi_dma_en);
assign mi_rd = ~write & mi_en;
assign mi_we = write & mi_en;
//signal to carry transaction from ETX to ERX block through fifo_cdc
assign mi_rx_en = mi_match &
((dstaddr[19:16]==4'hE) | (dstaddr[19:16]==4'hF)) &
~mi_en;
//ADDR
assign mi_addr[14:0] = dstaddr[14:0];
//DIN
assign mi_din[63:0] = {srcaddr[31:0], data[31:0]};
//READBACK MUX (inputs should be zero if not used)
assign mi_dout_mux[63:0] = mi_dout0[63:0] |
mi_dout1[63:0] |
mi_dout2[63:0] |
mi_dout3[63:0];
//Access out packet
assign access_forward = (mi_rx_en | mi_rd);
always @ (posedge clk)
if(~wait_in)
access_out <= access_forward;
always @ (posedge clk)
if(~wait_in)
begin
readback_reg <= mi_rd;
write_reg <= (mi_rx_en & write) | mi_rd;
datamode_reg[1:0] <= datamode[1:0];
ctrlmode_reg[3:0] <= ctrlmode[3:0];
dstaddr_reg[31:0] <= mi_rx_en ? dstaddr[31:0] : srcaddr[31:0];
data_reg[31:0] <= data[31:0];
srcaddr_reg[31:0] <= mi_rx_en ? srcaddr[31:0] : mi_dout_mux[63:32];
end
assign data_out[31:0] = readback_reg ? mi_dout_mux[31:0] : data_reg[31:0];
//Create packet
emesh2packet e2p (.packet_out (packet_out[PW-1:0]),
.access_in (1'b1),
.write_in (write_reg),
.datamode_in (datamode_reg[1:0]),
.ctrlmode_in (ctrlmode_reg[3:0]),
.dstaddr_in (dstaddr_reg[AW-1:0]),
.data_in (data_out[31:0]),
.srcaddr_in (srcaddr_reg[AW-1:0])
);
endmodule // ecfg_if
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [15:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR
);
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h000f;
localparam GPIO_BASEADDR_DEV1 = 16'h1000;
localparam GPIO_HIGHADDR_DEV1 = 16'h100f;
localparam GPIO_BASEADDR_DEV2 = 16'h2000;
localparam GPIO_HIGHADDR_DEV2 = 16'h200f;
wire [7:0] IO;
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'b0000_1111)
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(IO)
);
wire RESETB, TCK, TMS, TDI, TDO;
assign RESETB = IO[0];
assign TCK = IO[1];
assign TMS = IO[2];
assign TDI = IO[3];
assign IO[4] = TDO;
assign IO[7:5] = 0;
wire td_int;
wire [31:0] debug_reg1, debug_reg2;
jtag_tap i_jtag_tap1(.jtag_tms_i(TMS), .jtag_tck_i(TCK), .jtag_trstn_i(1'b1), .jtag_tdi_i(TDI), .jtag_tdo_o(td_int), .debug_reg(debug_reg2));
jtag_tap i_jtag_tap2(.jtag_tms_i(TMS), .jtag_tck_i(TCK), .jtag_trstn_i(1'b1), .jtag_tdi_i(td_int), .jtag_tdo_o(TDO), .debug_reg(debug_reg1));
wire D1_F1;
wire [5:0] D1_F2;
wire [3:0] D1_F3;
wire [20:0] D1_F4;
assign {D1_F4, D1_F3, D1_F2, D1_F1} = debug_reg1;
wire D2_F1;
wire [5:0] D2_F2;
wire [3:0] D2_F3;
wire [20:0] D2_F4;
assign {D2_F4, D2_F3, D2_F2, D2_F1} = debug_reg2;
gpio #(
.BASEADDR(GPIO_BASEADDR_DEV1),
.HIGHADDR(GPIO_HIGHADDR_DEV1),
.IO_WIDTH(32),
.IO_DIRECTION(32'h00000000)
) i_gpio_dev2 (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(debug_reg2)
);
gpio #(
.BASEADDR(GPIO_BASEADDR_DEV2),
.HIGHADDR(GPIO_HIGHADDR_DEV2),
.IO_WIDTH(32),
.IO_DIRECTION(32'h00000000)
) i_gpio_dev1 (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(debug_reg1)
);
initial begin
$dumpfile("jtag_gpio.vcd");
$dumpvars(0);
end
endmodule
|
// file: Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____7.373______0.000______50.0______624.752____391.211
// CLK_OUT2____23.997______0.000______50.0______511.434____391.211
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0;
wire clkfbout_buf_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (6),
.CLKFBOUT_MULT_F (38.875),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (87.875),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (27),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.CLKIN1 (clk_in1_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0),
.I (clkfbout_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_2_V
`define SKY130_FD_SC_LS__DFXTP_2_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxtp_2 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxtp_2 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_2_V
|
module top;
reg passed;
// These should be OK
enum {zdef1_[0:1]} zdef1;
enum {zdef2_[1:0]} zdef2;
enum {zdefb_[0:0]} zdef3;
enum {zvalb_[0:0] = 1} zval1;
initial begin
passed = 1'b1;
if (zdef1_0 !== 0) begin
$display("FAILED: expected zdef1_0 to be 0, got %0d", zdef1_0);
passed = 1'b0;
end
if (zdef1_1 !== 1) begin
$display("FAILED: expected zdef1_1 to be 1, got %0d", zdef1_1);
passed = 1'b0;
end
if (zdef2_1 !== 0) begin
$display("FAILED: expected zdef2_1 to be 0, got %0d", zdef2_1);
passed = 1'b0;
end
if (zdef2_0 !== 1) begin
$display("FAILED: expected zdef2_0 to be 1, got %0d", zdef2_0);
passed = 1'b0;
end
if (zdefb_0 !== 0) begin
$display("FAILED: expected zdefb_0 to be 0, got %0d", zdefb_0);
passed = 1'b0;
end
if (zvalb_0 !== 1) begin
$display("FAILED: expected zvalb_0 to be 1, got %0d", zvalb_0);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int changed; int answer1, answer2 = 1023; int main() { cin >> n; int i; for (i = 0; i < n; i++) { char tp; cin >> tp; if (tp == | ) { int number; cin >> number; answer1 |= number; answer2 |= number; changed |= number; } else if (tp == & ) { int number; cin >> number; answer1 &= number; answer2 &= number; number = 1023 - number; changed |= number; } else { int number; cin >> number; answer1 ^= number; answer2 ^= number; } } int answer11 = 0; int answer22 = 0; int answer33 = 0; for (i = 0; i < 10; i++) { if ((answer1 & (1 << i)) && (answer2 & (1 << i))) { answer11 += 1 << i; } else { if ((answer1 & (1 << i)) && (!(answer2 & (1 << i)))) { answer33 += 1 << i; answer22 += 1 << i; } if ((!(answer1 & (1 << i))) && (answer2 & (1 << i))) { answer22 += 1 << i; } } } cout << 3 << endl; cout << & << answer22 << endl; cout << | << answer11 << endl; cout << ^ << answer33 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int lcp[25][25]; int b[25]; string s[25]; int ans = 0; void BT(int now, int n, int k) { if (now == n) { int have = 0; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) if (b[i] && b[j]) have += lcp[i][j]; ans = max(ans, have); return; } b[now] = 0; if (n - now > k) BT(now + 1, n, k); if (k) { b[now] = 1; BT(now + 1, n, k - 1); } } int main() { ios::sync_with_stdio(false); int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> s[i]; for (int j = 0; j < i; j++) { int k; for (k = 0; k < s[i].length() && k < s[j].length() && s[i][k] == s[j][k]; k++) ; lcp[i][j] = lcp[j][i] = k; } } BT(0, n, k); cout << ans << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 300005; const long long INF = 0x3f3f3f3f3f3f3f3f; long long n; long long Read() { long long x = 0, f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x * 10) + (c ^ 48); c = getchar(); } return x * f; } void Put1(long long x) { if (x > 9) Put1(x / 10); putchar(x % 10 ^ 48); } void Put(long long x, char c = -1) { if (x < 0) putchar( - ), x = -x; Put1(x); if (c >= 0) putchar(c); } template <typename T> T Max(T x, T y) { return x > y ? x : y; } template <typename T> T Min(T x, T y) { return x < y ? x : y; } template <typename T> T Abs(T x) { return x < 0 ? -x : x; } long long a, d[MAXN], c[MAXN], f[MAXN]; struct node { long long d, maxf, maxans; node() {} node(long long d1, long long maxf1, long long maxans1) { d = d1; maxf = maxf1; maxans = maxans1; } } sta[MAXN]; long long pow2(long long x) { return x * x; } void solve() { long long ans = Max(0ll, a - (c[n] - c[n - 1])), max_pref, ed = 0; sta[0].maxans = -INF; sta[++ed] = node(0, f[n], f[n]); for (long long l = n - 1; l >= 1; --l) { max_pref = -INF; while (ed > 0 && sta[ed].d <= d[l + 1] - d[l]) { max_pref = Max(max_pref, sta[ed].maxf); sta[ed--] = node(0, 0, 0); } if (max_pref != -INF) sta[++ed] = node(d[l + 1] - d[l], max_pref, Max(max_pref - pow2(d[l + 1] - d[l]), sta[ed - 1].maxans)); sta[++ed] = node(0, f[l], Max(f[l], sta[ed - 1].maxans)); ans = Max(ans, sta[ed].maxans - f[l - 1]); } Put(ans, n ); } signed main() { n = Read(), a = Read(); for (long long i = 1; i <= n; ++i) d[i] = Read(), c[i] = c[i - 1] + Read(), f[i] = a * i - c[i]; solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_1_V
`define SKY130_FD_SC_MS__HA_1_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ha_1 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m, sum; int s[200010]; vector<pair<int, int> > G[200010]; int fa[200010]; int vis[200010]; int ans[200010]; void dfs(int x, int fa, int id) { vis[x] = 1; for (int i = 0; i < G[x].size(); i++) { int to = G[x][i].first; int id = G[x][i].second; if (vis[to] == 0) dfs(to, x, id); } if (s[x] != 0) { if (id > 0) ans[id] -= s[x]; else ans[-id] += s[x]; s[fa] += s[x]; s[x] = 0; } } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> s[i], sum += s[i], s[i] = -s[i]; if (sum) return puts( Impossible ), 0; puts( Possible ); cin >> m; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; G[x].push_back(make_pair(y, i)); G[y].push_back(make_pair(x, -i)); } dfs(1, 0, 0); for (int i = 1; i <= m; i++) cout << ans[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; stack<int> s; priority_queue<int> pq; long long maxm = numeric_limits<long long>::max(); const int maxn = 10005; struct node { int l, r; } q[1001]; bool cmp(node a, node b) { return a.l < b.l; } int main() { int n, sum = 0; scanf( %d , &n); int a[maxn], l[maxn], r[maxn]; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sum += a[i]; } int m, tmp; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &q[i].l, &q[i].r); } sort(q + 1, q + 1 + m, cmp); if (sum > q[m].r) printf( -1 n ); else if (sum < q[1].l) printf( %d n , q[1].l); else { for (int i = 1; i <= m; i++) { if (sum > q[i].r && sum < q[i + 1].l) { printf( %d n , q[i + 1].l); break; } else if (sum >= q[i].l && sum <= q[i].r) { printf( %d n , sum); break; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, s; cin >> a >> b >> s; if (a < 0) a *= (-1); if (b < 0) b *= (-1); (s >= (a + b) && (s - a - b) % 2 == 0) ? cout << YES : cout << NO ; return 0; }
|
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: WSIZ Copernicus
// Engineer: Rafa³ B., Szymon S., Darek B.
//
// Create Date: 27.04.2017 18:45:34
// Design Name:
// Module Name: modul_monet
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 2.02 - wersja II - inne podejscie do problemu
// Additional Comments:
//
/*
ZASADY DZIA£ANIA MODU£U:
AUTOMAT ROZPOCZYNA PRACÊ W STANIE 'NIC' - NA LINIECH WYJÆ MAMY:
[LINIA] [STAN]
CMD_OUT -> ODP_NIC (WYJCIE DO MODU£U G£ÓWNEGO)
MON_OUT -> Z0G00 (WYJCIE DO WYRZUTNIKA BILONU)
MODU£ CZEKA NA KOMEDNÊ Z MODU£U G£ÓWNEGO OZNAJMIAJ¥C¥ CO
KLIENT WYBRA£ (JAK¥ OPCJÊ ZAKUPU). W TYM STANIE W PRZYPADKU
OTRZYMANIA SYGNA£U Z WRZUTYNIKA BILONU MONETA ZWRACANA JEST
AUTOMATYCZNIE DO WYRZYTNIKA.
W PRZYPADKU OTRZYMANIA KOMENDY WYBORU OPCJI USTAWIANY JEST STAN
ODPOWIADAJ¥CY CENIE WYBRANEJ OPCJI.
KOMENDY WYBORU TO:
CMD_OP1, CMD_OP2, CMD_OP3
W TYM MOMENCIE USTAWIANY JEST TAK¯E SYGNA£ NA LINII CMD_OUT: ODP_W_TOKU.
WRZUCANIE MONET GENERUJE SYGNALY NA LINII MON_IN, KTÓRE ZMNIEJSZAJ¥
STAN AUTOMATU DO CZASU OSI¥GNIÊCIA STANU 'NIC' - NADWY¯KA ZOSTAJE
ZWRÓCONA PRZEZ WYRZUTNIK BILONU
ZAKOÑCZENIE PROCESU POBORU OP£ATY SYGNALIZOWANE JEST ZMIAN¥ SYGNA£U
NA LINI CMD_OUT NA ODP_OK (PO CHWILI ZMIENIONY NA ODP_NIC)
W DOWOLNYM MOMENCIE OTRZYMANIE SYGNALU NA LINI CMD_IN: CMD_RESET
POWODUJE WYRZUCENIE WSZYSTKICH WRZUCONYCH (JELI TAKIE S¥) MONET PRZEZ
WYRZUTNIK BIOLONU, NA LINII CMD_OUT USTAWIANY JEST DO CZASU SKOÑCZENIA
ZWRACANIA SYGNA£ ODP_ZWROT. PO ZAKOÑCZENIU SYGNA£ ZMIANIAMY NA ODP_RESET
(PO CHWILI ZMIENIONY NA ODP_NIC) I USTAWIONY ZOSTAJE STAN
POCZ¥TKOWY AUTOMATU 'NIC'.
*/
//////////////////////////////////////////////////////////////////////////////////
module modul_monet(
input wire clk, // zegar
input wire [2:0] mon_in, // wrzut monet
output reg [2:0] mon_out, // zwrot monet
input wire [2:0] cmd_in, // komenda: 0-nic, 1- zakup opcja1, 2- zakup opcja2, 3-zakup opcja3, 4-reset (pe³en zwrot)
output reg [1:0] cmd_out, // odpowied na komendê
output wire [4:0] stan_mm // przekazujemy stan - potrzebne do obs³ugi wywietlacza
);
parameter CENA_OP1 = `m300; // cena opcji 1 (3.00z³ - expresso)
parameter CENA_OP2 = `m500; // cena opcji 2 (5.00z³ - expresso grande :P )
parameter CENA_OP3 = `m750; // cena opcji 3 (7.50z³ - cappuccino :P )
reg [4:0]stan; // aktualny stan
reg [4:0]n_stan; // nastêpny stan
reg [4:0]tmp; // zmienna tymczasowa potrzebna do obliczeñ
assign stan_mm = stan;
always @(cmd_in) // otrzymalimy komendê
begin
n_stan = stan; // przepisujemy stan do n_stan - potrzebne w przypadku, gdyby stan nie uleg³ zmianie (pêtelka)
case (cmd_in)
`CMD_OP1:
begin
n_stan <= CENA_OP1; // stan na cenê zakupou opcji 1
cmd_out <= `ODP_W_TOKU;
end
`CMD_OP2:
begin
n_stan <= CENA_OP2; // stan na cenê zakupou opcji 2
cmd_out <= `ODP_W_TOKU;
end
`CMD_OP3:
begin
n_stan <= CENA_OP3; // stan na cenê zakupou opcji 3
cmd_out <= `ODP_W_TOKU;
end
`CMD_RESET1: // rezygnujemy z zakupu opcji 3
if (cmd_out == `ODP_W_TOKU) // jeli wybralimy juz opcjê
begin
cmd_out <= `ODP_ZWROT; // rozpoczynamy zwrot
n_stan <= CENA_OP1-stan;
end
`CMD_RESET2: // rezygnujemy z zakupu opcji 2
if (cmd_out == `ODP_W_TOKU) // jeli wybralimy juz opcjê
begin
cmd_out <= `ODP_ZWROT; // rozpoczynamy zwrot
n_stan <= CENA_OP2-stan;
end
`CMD_RESET3: // rezygnujemy z zakupu opcji 3
if (cmd_out == `ODP_W_TOKU) // jeli wybralimy juz opcjê
begin
cmd_out <= `ODP_ZWROT; // rozpoczynamy zwrot
n_stan <= CENA_OP3-stan;
end
`CMD_RESET: // reset pocz¹tkowy
if (cmd_out === 2'bxx) // jeli automat nie zosta³ zresetowany wczeniej
begin
stan = `NIC;
n_stan = `NIC;
cmd_out = 2'b00;
mon_out = 3'b000;
tmp = `NIC;
end
endcase
end
always @(posedge clk)
begin
case (cmd_out)
`ODP_ZWROT: // jestemy w trybie zwrotu
if (mon_in != `z0g00) // zwracamy monety, a kto wrzuci³ dodatkow¹ monetê
begin
n_stan <= stan; // stan bez zmian
mon_out <= mon_in; // zwracamy monetê
end
else begin // w innym przypadku kontynuujemy zwrot monet
if (stan>`m500) begin // ponad 5 z³ do zwrotu
mon_out <= `z5g00; // zwracamy 5 z³
n_stan <= stan - `m500; // ustawiamy nastêpny stan
end
else if (stan==`m500) begin // równo 5 z³ do zwrotu
mon_out <= `z5g00; // zwracamy 5 z³
n_stan <= `NIC; // ustawiamy nastêpny stan
cmd_out <= `ODP_OK; // informujemy MG, ¿e wszystko OK
end
else if (stan>`m200) begin // ponad 2 z³ do zwrotu
mon_out <= `z2g00; // zwracamy 2 z³
n_stan <= stan - `m200; // ustawiamy nastêpny stan
end
else if (stan == `m200) begin // dok³adnie 2 z³ do zwrotu
mon_out <= `z2g00; // zwracamy 2 z³
n_stan <= `NIC; // ustawiamy nastêpny stan
cmd_out <= `ODP_OK; // informujemy MG, ¿e wszystko OK
end
else if (stan == `m150) begin // pozosta³o 1,50 do zwrotu
mon_out <= `z1g00; // zwracamy 1 z³
n_stan <= `m050; // ustawiamy nastêpny stan
end
else begin
case (stan)
`m050: mon_out <= `z0g50;// pozosta³o 50 gr do zwrotu - zwracamy
`m100: mon_out <= `z1g00;// pozosta³o 1 z³ do zwrotu - zwracamy
endcase
n_stan <= `NIC; // ustawiamy nastêpny stan
cmd_out <= `ODP_OK; // informujemy MG, ¿e wszystko OK
end
end
`ODP_W_TOKU: // jestemy w trybie op³aty za opcjê
begin
case (mon_in) // jak¹ monetê wrzucono ?
default: tmp = `NIC; // zerujemy w ka¿dym innym przypadku
`z0g50: tmp = `m050; // 50 groszy
`z1g00: tmp = `m100; // 1 z³
`z2g00: tmp = `m200; // 2 z³
`z5g00: tmp = `m500; // 5z³
endcase
if (stan > tmp) // moneta to za ma³o aby zakoñczyæ pobór op³aty
n_stan <= stan - tmp; // ustawiamy nastêpny stan
else if (stan == tmp) // moneta wystarczy aby zakoñczyc pobór op³aty
begin
n_stan <= `NIC; // ustawiamy nastêpny stan
cmd_out <= `ODP_OK; // informujemy MG, ¿e wszystko ok
end
else // moneta to za du¿o - trzeba zwróciæ resztê
begin
n_stan <= tmp - stan; // ustawiamy nastêpny stan
cmd_out <= `ODP_ZWROT; // ustawiamy tryb na zwrot;
end
end
`ODP_NIC:
if (mon_in != `z0g00) // modu³ nic nie robi a wrzucono monetê
begin
n_stan <= stan; // stan bez zmian
mon_out <= mon_in; // zwracamy monetê
end
endcase
end
always @(negedge clk)
begin
#10 begin
if (cmd_out == `ODP_OK) cmd_out <= `ODP_NIC; // koniec wrzutu lub zwrotu - modu³ w stanie zero
if (mon_out != `z0g00) mon_out <= `z0g00; // po 10ns zerujemy sygna³ zwrotu monety
end
end
always @(*)
#1 begin
stan = n_stan; // ustawiamy nastêpny stan
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int squ(vector<long long> &v) { for (int i = 0; i + 3 < v.size(); i++) { if (v[i] == v[i + 1] && v[i] == v[i + 2] && v[i] == v[i + 3]) return v[i]; } return -1; } vector<long long> pa(vector<long long> &v) { vector<long long> q; for (int i = 0; i + 1 < v.size(); i++) { if (i == 0 || v[i - 1] != v[i]) { if (v[i] == v[i + 1]) q.push_back(v[i]); } } return q; } bool checkv(pair<long long, long long> a, pair<long long, long long> b) { if ((a.first + a.second) * (a.first + a.second) * b.first * b.second > (b.first + b.second) * (b.first + b.second) * a.first * a.second) return true; return false; } int main() { ios_base::sync_with_stdio(0); int T; cin >> T; while (T--) { long long n; cin >> n; vector<long long> v; for (int i = 0; i < n; i++) { long long a; cin >> a; v.push_back(a); } sort(v.begin(), v.end()); long long res = squ(v); if (res > 0) { for (int i = 0; i < 4; i++) cout << res << ; cout << n ; continue; } vector<long long> u = pa(v); pair<long long, long long> cur = {u[0], u[1]}; for (int i = 0; i + 1 < u.size(); i++) { if (checkv(cur, {u[i], u[i + 1]})) { cur = {u[i], u[i + 1]}; } } cout << cur.first << << cur.first << << cur.second << << cur.second << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, a, b; set<pair<int, int> > s; set<int> sc; vector<int> ans; int main() { cin >> n >> m; for (int i = 1; i <= m; ++i) { cin >> a >> b; s.insert(make_pair(min(a, b), max(a, b))); } for (int i = 1; i <= n; ++i) { sc.insert(i); } for (int i = 1; i <= n; ++i) { if (sc.find(i) != sc.end()) { int cur = 0; queue<int> q; q.push(i); sc.erase(i); while (!q.empty()) { cur++; int v = q.front(); q.pop(); set<int>::iterator it; set<int> c = sc; for (it = c.begin(); it != c.end(); it++) { int to = *it; if (s.find(make_pair(min(v, to), max(v, to))) == s.end()) { q.push(to); sc.erase(to); } } } ans.push_back(cur); } } sort(ans.begin(), ans.end()); cout << (int)ans.size() << endl; for (int i = 0; i < (int)ans.size(); ++i) { cout << ans[i] << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a[n + 1], b[n + 1]; for (long long i = 1; i <= n; i++) { long long x; cin >> x; a[x] = i; } for (long long i = 1; i <= n; i++) { long long x; cin >> x; b[x] = i; } map<long long, long long> m; long long ans = 0; for (long long i = 1; i <= n; i++) { if (a[i] < b[i]) { m[n + a[i] - b[i]]++; ans = max(ans, m[n - b[i] + a[i]]); } else { m[a[i] - b[i]]++; ans = max(ans, m[a[i] - b[i]]); } } cout << ans << endl; }
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
wasca_nios2_gen2_0_cpu_debug_slave_tck the_wasca_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
wasca_nios2_gen2_0_cpu_debug_slave_sysclk the_wasca_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic wasca_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// wasca_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_FUNCTIONAL_PP_V
|
`timescale 1ns/1ns
module aes_tb;
reg rst;
reg clk;
reg [7:0] key_in;
reg [7:0] d_in;
wire [7:0] d_out;
wire d_vld;
parameter CP = 20;
//Two test vectors
//Simple example
//CT = 0x69c4e0d86a7b0430d8cdb78070b4c55a
parameter kin = 128'h000102030405060708090a0b0c0d0e0f;
parameter din = 128'h00112233445566778899aabbccddeeff;
//Example in FIPS-197
//CT = 0x3925841d02dc09fbdc118597196a0b32
//parameter kin = 128'h2b7e151628aed2a6abf7158809cf4f3c;
//parameter din = 128'h3243f6a8885a308d313198a2e0370734;
aes_8_bit test (rst, clk, key_in, d_in, d_out, d_vld);
always # (CP/2)
begin
clk = ~ clk;
end
initial begin
rst = 1'b1;
clk = 1'b1;
#CP
rst = 1'b0;
key_in = kin[127:120];
d_in = din[127:120];
#CP
key_in = kin[119:112];
d_in = din[119:112];
#CP
key_in = kin[111:104];
d_in = din[111:104];
#CP
key_in = kin[103:96];
d_in = din[103:96];
#CP
key_in = kin[95:88];
d_in = din[95:88];
#CP
key_in = kin[87:80];
d_in = din[87:80];
#CP
key_in = kin[79:72];
d_in = din[79:72];
#CP
key_in = kin[71:64];
d_in = din[71:64];
#CP
key_in = kin[63:56];
d_in = din[63:56];
#CP
key_in = kin[55:48];
d_in = din[55:48];
#CP
key_in = kin[47:40];
d_in = din[47:40];
#CP
key_in = kin[39:32];
d_in = din[39:32];
#CP
key_in = kin[31:24];
d_in = din[31:24];
#CP
key_in = kin[23:16];
d_in = din[23:16];
#CP
key_in = kin[15:8];
d_in = din[15:8];
#CP
key_in = kin[7:0];
d_in = din[7:0];
end
endmodule
|
module bsg_link_osdr_phy
#(parameter `BSG_INV_PARAM(width_p )
,parameter strength_p = 0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output clk_o
,output [width_p-1:0] data_o
);
`define BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(strength,name,in,out) \
begin: s``strength`` \
SC7P5T_CKBUFX``strength``_SSC14R ``name`` (.CLK(``in``),.Z(``out``)); \
end
`define BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(strength,name,in,out) \
if (strength_p >= ``strength``) \
`BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(strength,name,in,out)
`define BSG_LINK_OSDR_PHY_CKBUF_MACRO(name,in,out) \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(16,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(14,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(12,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(10,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(8,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(6,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(4,name,in,out)
wire clk_r_p, clk_r_n, clk_o_buf;
wire [width_p-1:0] data_o_buf;
SC7P5T_CKXOR2X2_SSC14R BSG_OSDR_CKXOR2_BSG_DONT_TOUCH
(.Z(clk_o_buf),.CLK(clk_r_p),.EN(clk_r_n));
`BSG_LINK_OSDR_PHY_CKBUF_MACRO(BSG_OSDR_CKBUF_BSG_DONT_TOUCH, clk_o_buf, clk_o)
SC7P5T_DFFQX2_SSC14R BSG_OSDR_DFFPOS_BSG_DONT_TOUCH
(.D(~(clk_r_p|reset_i)),.CLK(clk_i),.Q(clk_r_p));
SC7P5T_DFFNQX2_SSC14R BSG_OSDR_DFFNEG_BSG_DONT_TOUCH
(.D(~(clk_r_n|reset_i)),.CLK(clk_i),.Q(clk_r_n));
for (genvar i = 0; i < width_p; i++)
begin: data
SC7P5T_DFFQX1_SSC14R BSG_OSDR_DFFQ
(.D(data_i[i]),.CLK(clk_i),.Q(data_o_buf[i]));
`BSG_LINK_OSDR_PHY_CKBUF_MACRO(BSG_OSDR_BUF_BSG_DONT_TOUCH, data_o_buf[i], data_o[i])
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_osdr_phy)
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module logicblock_sub(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign o_dataout = dataa - datab;
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
//======================================================================
//
// sha1_w_mem_reg.v
// -----------------
// The SHA-1 W memory. This memory includes functionality to
// expand the block into 80 words.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha1_w_mem(
input wire clk,
input wire reset_n,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [6 : 0] w_ctr_reg;
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
w_mem[i] <= 32'h0;
w_ctr_reg <= 7'h0;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// W word selection logic. Returns either directly from the
// memory or the next w value calculated.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
w_tmp = w_mem[w_ctr_reg[3 : 0]];
else
w_tmp = w_new;
end // select_w
//----------------------------------------------------------------
// w_mem_update_logic
//
// Update logic for the W memory. This is where the scheduling
// based on a sliding window is implemented.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_2;
reg [31 : 0] w_8;
reg [31 : 0] w_13;
reg [31 : 0] w_16;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 1'h0;
w_0 = w_mem[0];
w_2 = w_mem[2];
w_8 = w_mem[8];
w_13 = w_mem[13];
w_16 = w_13 ^ w_8 ^ w_2 ^ w_0;
w_new = {w_16[30 : 0], w_16[31]};
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1'h1;
end
if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1'h1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
//
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 7'h0;
w_ctr_we = 1'h0;
if (init)
begin
w_ctr_new = 7'h0;
w_ctr_we = 1'h1;
end
if (next)
begin
w_ctr_new = w_ctr_reg + 7'h01;
w_ctr_we = 1'h1;
end
end // w_ctr
endmodule // sha1_w_mem
//======================================================================
// sha1_w_mem.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; template <typename T> T sqr(T x) { return x * x; } double sind(double x) { return sin(x * PI / 180); } double cosd(double x) { return cos(x * PI / 180); } double tand(double x) { return tan(x * PI / 180); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int r, c, i, j, x = 0, y = 0; cin >> r >> c; vector<string> v; bool mark[c + 1]; memset(mark, 0, sizeof(mark)); for (i = 0; i < r; i++) { string s; cin >> s; v.push_back(s); } for (auto i : v) { string s; bool f = 1; s = i; for (j = 0; j < c; j++) { if (s[j] == S ) { f = 0; mark[j] = 1; } } if (f) x++; } for (i = 0; i < c; i++) { if (mark[i] == 0) y++; } int ans = 0; ans += x * c; ans += y * (r - x); cout << ans; return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
\file "channel-source-sink-b.v"
Chain a source and sink in prsim to verilog.
$Id: channel-source-sink.v,v 1.4 2010/04/06 00:08:26 fang Exp $
*/
`timescale 1ns/1ps
`include "standard.v"
`define inv_delay 0.020
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg l0, l1, re;
wire le, r0, r1;
DELAY #(.delay(`inv_delay)) d0(l0, r0);
DELAY #(.delay(`inv_delay)) d1(l1, r1);
DELAY #(.delay(`inv_delay)) de(re, le);
// prsim stuff
initial
begin
// @haco@ channel-source-sink.haco-c
$prsim_options("-I subdir");
$prsim("channel-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
// $prsim_cmd("addpath subdir");
$from_prsim("L.d[0]","TOP.l0");
$from_prsim("L.d[1]","TOP.l1");
$to_prsim("TOP.le", "L.e");
$to_prsim("TOP.r0", "R.d[0]");
$to_prsim("TOP.r1", "R.d[1]");
$from_prsim("R.e", "TOP.re");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel L e:0 :0 d:2");
$prsim_cmd("channel R e:1 :0 d:2");
$prsim_cmd("channel-source-file-loop L channel-values-X.txt");
$prsim_cmd("channel-sink R");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-reset-all");
$prsim_cmd("channel-show-all");
$prsim_cmd("breaks");
end
initial #5 $prsim_cmd("channel-release-all");
initial #5 $prsim_cmd("channel-show-all");
initial #6 $prsim_cmd("nowatchall");
initial #9 $prsim_cmd("why-not-verbose R.e");
initial #9 $prsim_cmd("why-not-verbose R.d[0]");
initial #10 $finish;
/**
initial
$monitor("@%7.3f: l = %d,%d:%d; r = %d,%d:%d", $realtime,
l0, l1, le, r0, r1, re);
**/
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1000000 + 5]; int b[1000000 + 5]; int main() { ios_base::sync_with_stdio(false); int i, j, n, k; queue<pair<int, int> > q; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) cin >> b[i]; for (i = 1; i <= n; i++) { if (a[i] != b[i]) { for (j = i + 1; j <= n; j++) { if (a[i] == b[j]) { k = j; break; } } for (j = k; j > i; j--) { q.push(make_pair(j - 1, j)); int t = b[j]; b[j] = b[j - 1]; b[j - 1] = t; } } } cout << q.size() << endl; while (q.empty() != 1) { cout << q.front().first << << q.front().second << endl; q.pop(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_lp_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_lp_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire SLEEP_B_delayed;
wire D_delayed ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$lP_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_BEHAVIORAL_V
|
`default_nettype none
`define CLKFBOUT_MULT 2
// ============================================================================
module top
(
input wire clk,
input wire rst,
input wire [1:0] sw,
output wire [9:0] led,
);
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
wire CLK;
BUFG bufg(.I(clk), .O(CLK));
always @(posedge CLK)
if (rst)
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire RST = rst_sr[0];
// ============================================================================
// Clocks for ISERDES
wire PRE_BUFG_SYSCLK;
wire PRE_BUFG_CLKDIV;
wire PRE_BUFG_REFCLK;
wire SYSCLK;
wire CLKDIV;
wire REFCLK;
wire clk_fb_i;
wire clk_fb_o;
PLLE2_ADV #(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (`CLKFBOUT_MULT),
.CLKOUT0_DIVIDE (`CLKFBOUT_MULT / 2), // SYSCLK, 200MHz (Fast clock)
.CLKOUT1_DIVIDE ((`CLKFBOUT_MULT * 4) / 2), // CLKDIV, 50MHz (Slow clock)
.CLKOUT2_DIVIDE (`CLKFBOUT_MULT / 2), // REFCLK (IDELAYCTRL), 200 MHz
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1'd1)
)
pll
(
.CLKIN1 (CLK),
.CLKINSEL (1),
.RST (RST),
.PWRDWN (0),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (PRE_BUFG_SYSCLK),
.CLKOUT1 (PRE_BUFG_CLKDIV),
.CLKOUT2 (PRE_BUFG_REFCLK)
);
BUFG bufg_clk(.I(PRE_BUFG_SYSCLK), .O(SYSCLK));
BUFG bufg_clkdiv(.I(PRE_BUFG_CLKDIV), .O(CLKDIV));
BUFG bufg_refclk(.I(PRE_BUFG_REFCLK), .O(REFCLK));
IDELAYCTRL idelayctrl_1 (
.REFCLK(REFCLK)
);
IDELAYCTRL idelayctrl_2 (
.REFCLK(REFCLK)
);
assign led[0] = 0;
assign led[1] = 0;
wire OUTPUTS[7:0];
// ISERDES reset generator
wire i_rstdiv;
// First ISERDES/IDELAY bank
wire DDLY_1;
IDELAYE2 #
(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IDATAIN"),
.IDELAY_VALUE (5'd31)
)
idelay_1
(
.C (SYSCLK),
.CE (1'b1),
.LD (1'b1),
.INC (1'b1),
.IDATAIN (sw[0]),
.DATAOUT (DDLY_1)
);
ISERDESE2 #
(
.DATA_RATE ("SDR"),
.DATA_WIDTH (3'd4),
.INTERFACE_TYPE ("NETWORKING"),
.NUM_CE (2)
)
iserdes_1
(
.CLK (SYSCLK),
.CLKB (SYSCLK),
.CLKDIV (CLKDIV),
.CE1 (1'b1),
.CE2 (1'b1),
.RST (RST),
.DDLY (DDLY_1),
.Q1 (led[5]),
.Q2 (led[4]),
.Q3 (led[3]),
.Q4 (led[2]),
);
// Second ISERDES/IDELAY bank
wire DDLY_2;
IDELAYE2 #
(
.IDELAY_TYPE ("FIXED"),
.DELAY_SRC ("IDATAIN"),
.IDELAY_VALUE (5'd31)
)
idelay_2
(
.C (SYSCLK),
.CE (1'b1),
.LD (1'b1),
.INC (1'b1),
.IDATAIN (sw[1]),
.DATAOUT (DDLY_2)
);
ISERDESE2 #
(
.DATA_RATE ("SDR"),
.DATA_WIDTH (3'd4),
.INTERFACE_TYPE ("NETWORKING"),
.NUM_CE (2)
)
iserdes_2
(
.CLK (SYSCLK),
.CLKB (SYSCLK),
.CLKDIV (CLKDIV),
.CE1 (1'b1),
.CE2 (1'b1),
.RST (RST),
.DDLY (DDLY_2),
.Q1 (led[9]),
.Q2 (led[8]),
.Q3 (led[7]),
.Q4 (led[6]),
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[110], s[110]; int main() { int n, m; cin >> n >> m; for (int i = (1); i < (n + 1); i++) cin >> x[i]; for (int i = (1); i < (n + 1); i++) s[i] = s[i - 1] + x[i]; int v = 0; while (m--) { int l, r; cin >> l >> r; if (s[r] - s[l - 1] > 0) v += s[r] - s[l - 1]; } cout << v << n ; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: phd_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module phd_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/phd_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/phd_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL phd_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "util.v"
`include "hi_flite.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// divide subcarrier frequency by 4
wire hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
hi_sniffer he(
pck0, ck_1356meg, ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
cross_hi, cross_lo,
he_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_flite hfl(
pck0, ck_1356meg, ck_1356megb,
hfl_pwr_lo, hfl_pwr_hi, hfl_pwr_oe1, hfl_pwr_oe2, hfl_pwr_oe3, hfl_pwr_oe4,
adc_d, hfl_adc_clk,
hfl_ssp_frame, hfl_ssp_din, ssp_dout, hfl_ssp_clk,
cross_hi, cross_lo,
hfl_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 100 -- HF Snoop
// 101 -- Felica modem, reusing HF reader
// 110 -- none
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, hfl_ssp_clk, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, hfl_ssp_din, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, hfl_ssp_frame, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, hfl_pwr_oe1, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, hfl_pwr_oe2, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, hfl_pwr_oe3, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, hfl_pwr_oe4, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, hfl_pwr_lo, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, hfl_pwr_hi, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, hfl_adc_clk, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, hfl_dbg, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int keep[201]; int tt[201]; int first[201]; int main() { while (cin >> n) { n *= 2; int sum = 0, n1 = 0, n2 = 0, s1 = 0, s2 = 0; memset(keep, 0, sizeof(keep)); memset(first, 0, sizeof(first)); for (int i = 0; i < n; i++) { int a; cin >> a; keep[a]++; tt[i] = a; } for (int i = 10; i < 100; i++) { if (keep[i] > 1) { s1++; s2++; if (n1 > n2) n1 += keep[i] / 2, n2 += (keep[i] - keep[i] / 2), first[i] = 2; else n2 += keep[i] / 2, n1 += (keep[i] - keep[i] / 2), first[i] = 1; } else if (keep[i] == 1) sum++; } int turn = 1; if (s1 > s2) { turn = 2; s1 += sum / 2; s2 += (sum - sum / 2); } else { turn = 2; s2 += sum / 2; s1 += (sum - sum / 2); } cout << s1 * s2 << endl; for (int i = 0; i < n; i++) { if (keep[tt[i]] > 1) { cout << first[tt[i]]; first[tt[i]] = (first[tt[i]] == 2 ? 1 : 2); } else if (keep[tt[i]] == 1) { cout << turn; turn = (turn == 2 ? 1 : 2); } if (i < n - 1) cout << ; else cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; long long pwr(long long a, long long b, long long mod) { a %= mod; if (a < 0) a += mod; long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % mod; a = (a * a) % mod; b /= 2; } return ans; } long long pwr(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans *= a; a *= a; b /= 2; } return ans; } long long gcd(long long a, long long b) { while (b) { long long temp = a; a = b; b = temp % b; } return a; } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } long long modularInverse(long long a, long long m) { assert(false); return pwr(a, m - 2, m); } int main(int argc, char const *argv[]) { std::ios::sync_with_stdio(false); int n, m, num1, num2; cin >> n >> m; if (n > m) { num1 = n; num2 = m; } else { num1 = m; num2 = n; } long long sum = 0; while (num2 != 0 && num1 >= 2) { sum++; num2--; num1 = num1 - 2; if (num1 < num2) { swap(num1, num2); } } cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> int btf(int n) { static int num[10]; memset(num, 0, sizeof(num)); for (int i = 0; i < 4; i++) { num[n % 10]++; n /= 10; } for (int i = 0; i < 10; i++) if (num[i] > 1) return 0; return 1; } void solve(int n) { for (int i = n + 1; 1; i++) if (btf(i)) { printf( %d n , i); return; } } int main() { int n; while (scanf( %d , &n) != EOF) solve(n); return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:04:13
// Design Name:
// Module Name: pm0
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pc_ctrl_pm0 #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = 32,
parameter DCADDR_LOW_BIT_W = 8
) (
input wire [31:0] accum_low_period,
input wire [15:0] pulse_per_second,
input wire ready_to_read ,
output reg [31:0] clk_freq = 32'd100000000,
output reg [31:0] clk_subsample = 32'd0,
output reg enable = 1'd1,
output reg use_one_pps_in = 1'd0,
input wire reg_bank_rd_start, // read start strobe
output wire reg_bank_rd_done, // read done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_rd_addr, // read address bus
output reg [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_rd_data=0,// read data bus
input wire reg_bank_wr_start, // write start strobe
output wire reg_bank_wr_done, // write done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_wr_addr, // write address bus
input wire [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_wr_data, // write data bus
input wire ACLK , // Clock source
input wire ARESETn // Reset source
);
//------------------------------------------------------------------------------
// Declare registers
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// In the basic bank these are completed straight away. Recall ....XX_start is
// a registered signal.
//------------------------------------------------------------------------------
assign reg_bank_wr_done = reg_bank_wr_start;
assign reg_bank_rd_done = reg_bank_rd_start;
//------------------------------------------------------------------------------
// Write logic
//------------------------------------------------------------------------------
always @(posedge ACLK) begin
if(!ARESETn) begin
clk_freq <= 32'd100000000;
clk_subsample <= 32'd0;
enable <= 1'd1;
use_one_pps_in <= 1'd0;
end else begin
if(reg_bank_wr_start) begin
case (reg_bank_wr_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
enable <= reg_bank_wr_data[0:0];
end
1 : begin
use_one_pps_in <= reg_bank_wr_data[0:0];
end
2 : begin
clk_freq <= reg_bank_wr_data[31:0];
end
3 : begin
clk_subsample <= reg_bank_wr_data[31:0];
end
endcase
end
end
end
//------------------------------------------------------------------------------
// READ logic
//------------------------------------------------------------------------------
always @(*) begin
// Zero the complete bus. We will set specific bits in the case
reg_bank_rd_data = 'd0;
case (reg_bank_rd_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
reg_bank_rd_data[0:0] = enable;
end
1 : begin
reg_bank_rd_data[0:0] = use_one_pps_in;
end
2 : begin
reg_bank_rd_data[31:0] = clk_freq;
end
3 : begin
reg_bank_rd_data[31:0] = clk_subsample;
end
4 : begin
reg_bank_rd_data[15:0] = pulse_per_second;
end
5 : begin
reg_bank_rd_data[31:0] = accum_low_period;
end
6 : begin
reg_bank_rd_data[0:0] = ready_to_read;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e4 + 100; int n, k; struct node { int sz; int mn[15], mx[15]; void init(int a) { sz = 0; for (int i = 1; i <= k; i++) { mx[i] = mn[i] = a; } } void unit(node a) { sz += a.sz; for (int i = 1; i <= k; i++) { mn[i] = min(mn[i], a.mn[i]); mx[i] = max(mx[i], a.mx[i]); } } bool operator<(const node& p) const { for (int i = 1; i <= k; i++) { if (mx[i] > p.mn[i]) return false; } return true; } }; set<node> s; vector<set<node>::iterator> del; int main() { scanf( %d %d , &n, &k); node now; for (int i = 1; i <= n; i++) { for (int j = 1; j <= k; j++) scanf( %d , &now.mn[j]), now.mx[j] = now.mn[j]; now.sz = 1; set<node>::iterator l, r, iter; r = s.upper_bound(now); l = s.lower_bound(now); for (iter = l; iter != r; iter++) { now.unit(*iter); del.push_back(iter); } for (int j = 0; j < del.size(); j++) { s.erase(del[j]); } del.clear(); s.insert(now); iter = s.end(); iter--; printf( %d n , iter->sz); } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ddr2um_valid_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr2um_valid_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [6:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [6:0] q;
output rdempty;
output [3:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire1;
wire [3:0] sub_wire2;
wire [6:0] q = sub_wire0[6:0];
wire rdempty = sub_wire1;
wire [3:0] wrusedw = sub_wire2[3:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrusedw (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 16,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 7,
dcfifo_component.lpm_widthu = 4,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "7"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "7"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL "data[6..0]"
// Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL "q[6..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 7 0 data 0 0 7 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 7 0 @q 0 0 7 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_valid_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_valid_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_valid_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_valid_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_valid_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2um_valid_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, d[1010][101][2], ans, nf, p[1010]; int main() { cin >> n >> k >> m; p[0] = 1; for (int i = 1; i <= n; i++) p[i] = p[i - 1] * 10 % k; d[0][0][0] = 1; for (int i = 1; i <= n; i++) { for (int x = (i == n); x < 10; x++) for (int f = 0; f < k; f++) { nf = (f + p[i - 1] * x) % k; d[i][nf][1] += d[i - 1][f][1]; if (nf == 0 && x) d[i][nf][1] += d[i - 1][f][0]; else d[i][nf][0] += d[i - 1][f][0]; d[i][nf][0] %= m; d[i][nf][1] %= m; } } for (int i = 0; i < k; i++) ans = (ans + d[n][i][1]) % m; cout << ans << n ; }
|
#include <bits/stdc++.h> struct node { int v; node *next; } edge[400000 * 2 + 10], *adj[200000 + 10], *ecnt = &edge[0]; struct Edge { int u, v; Edge() {} Edge(int u, int v) : u(u), v(v) {} } e[400000 + 10], ans[400000 + 10]; int n, m, s, t, ds, dt, col[200000 + 10], cntcol, cnta, fa[200000 + 10], belong[200000 + 10]; int able[2][200000 + 10], link[2][200000 + 10]; template <class T> void Read(T &x) { char c; while (c = getchar(), c != EOF) if (c >= 0 && c <= 9 ) { x = c - 0 ; while (c = getchar(), c >= 0 && c <= 9 ) x = x * 10 + c - 0 ; ungetc(c, stdin); return; } } void read() { Read(n), Read(m); for (int i = 1; i <= m; i++) Read(e[i].u), Read(e[i].v); Read(s), Read(t), Read(ds), Read(dt); } void addedge(int u, int v) { node *p = ++ecnt; p->v = v; p->next = adj[u]; adj[u] = p; } void dfs(int u) { col[u] = cntcol; for (node *p = adj[u]; p; p = p->next) if (!col[p->v]) dfs(p->v); } int Find(int x) { return x == fa[x] ? x : fa[x] = Find(fa[x]); } void solve() { for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) { if (e[i].u == s || e[i].u == t || e[i].v == s || e[i].v == t) continue; if (Find(e[i].u) != Find(e[i].v)) { fa[Find(e[i].u)] = Find(e[i].v); ans[++cnta] = e[i]; addedge(e[i].u, e[i].v), addedge(e[i].v, e[i].u); } } for (int i = 1; i <= n; i++) if (!col[i]) { ++cntcol; dfs(i); } for (int i = 1; i <= m; i++) if (e[i].u == s || e[i].u == t || e[i].v == s || e[i].v == t) addedge(e[i].u, e[i].v), addedge(e[i].v, e[i].u); int cnts = 0, cntt = 0; belong[col[s]]++; for (node *p = adj[s]; p; p = p->next) if (!belong[col[p->v]]) belong[col[p->v]]++; belong[col[t]]++; for (node *p = adj[t]; p; p = p->next) if (!belong[col[p->v]]) { ans[++cnta] = Edge(t, p->v), cntt++; belong[col[p->v]] = -1; } else if (belong[col[p->v]] == 1) { belong[col[p->v]]++; able[1][col[p->v]] = p->v; } for (node *p = adj[s]; p; p = p->next) if (belong[col[p->v]] == 1) { ans[++cnta] = Edge(s, p->v), cnts++; belong[col[p->v]] = -1; } else if (belong[col[p->v]] == 2) able[0][col[p->v]] = p->v; if (cnts > ds || cntt > dt) puts( No ); else { ds -= cnts, dt -= cntt; bool f = false; for (node *p = adj[s]; p; p = p->next) if (belong[col[p->v]] == 2 && ds && p->v != t) { ds--; ans[++cnta] = Edge(s, p->v); link[0][col[p->v]] = p->v; belong[col[p->v]] = 0; } if (ds && dt && belong[col[t]] == 2) { f = true; ans[++cnta] = Edge(s, t); belong[col[s]] = 0; dt--; } for (node *p = adj[t]; p; p = p->next) if (belong[col[p->v]] == 2 && p->v != s) { if (!dt) { puts( No ); return; } dt--; ans[++cnta] = Edge(t, p->v); link[1][col[p->v]] = p->v; belong[col[p->v]] = 0; } if (!f && dt && ds && belong[col[s]] == 2) { f = true; ans[++cnta] = Edge(s, t); ds--; } if (!f && (ds || dt)) { if (ds) { for (int i = 1; i <= cntcol; i++) if (able[0][i] && link[1][i]) { f = true; ans[++cnta] = Edge(s, able[0][i]); break; } } if (!f && dt) { for (int i = 1; i <= cntcol; i++) if (able[1][i] && link[0][i]) { f = true; ans[++cnta] = Edge(t, able[1][i]); break; } } } if (f) { puts( Yes ); for (int i = 1; i <= cnta; i++) printf( %d %d n , ans[i].u, ans[i].v); } else puts( No ); } } int main() { read(); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; if (n < 3) { cout << -1; } else { long long a[n][n]; long long offset = n * n - 9; a[0][0] = 9 + offset; a[0][1] = 5 + offset; a[0][2] = 6 + offset; a[1][0] = 7 + offset; a[1][1] = 2 + offset; a[1][2] = 8 + offset; a[2][0] = 1 + offset; a[2][1] = 3 + offset; a[2][2] = 4 + offset; long long x = 0; for (long long j = n - 1; j > (long long)2; --j) { if (j & 1) { for (long long i = 0; i < (long long)j + 1; ++i) { a[i][j] = ++x; } for (long long i = j - 1; i > (long long)-1; --i) { a[j][i] = ++x; } } else { for (long long i = 0; i < (long long)j + 1; ++i) { a[j][i] = ++x; } for (long long i = j - 1; i > (long long)-1; --i) { a[i][j] = ++x; } } } for (long long i = 0; i < (long long)n; ++i) { for (long long j = 0; j < (long long)n; ++j) { cout << a[i][j] << ; } cout << n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long> tri(100005); void solve() { long long n; cin >> n; for (long long i = 1; i < 100005; i++) { tri[i] = (i * (i + 1)) / 2LL; } for (int i = 1; i <= 100000; i++) { long long x = n - tri[i]; if (x <= 0) { cout << NO n ; return; } auto it = lower_bound(tri.begin(), tri.end(), x) - tri.begin(); if (tri[it] == x) { cout << YES n ; return; } } cout << NO n ; return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; template <class t, class u> void chmax(t& first, u second) { if (first < second) first = second; } template <class t, class u> void chmin(t& first, u second) { if (second < first) first = second; } template <class t> using vc = vector<t>; template <class t> using vvc = vc<vc<t>>; using pi = pair<int, int>; using vi = vc<int>; template <class t, class u> ostream& operator<<(ostream& os, const pair<t, u>& p) { return os << { << p.first << , << p.second << } ; } template <class t> ostream& operator<<(ostream& os, const vc<t>& v) { os << { ; for (auto e : v) os << e << , ; return os << } ; } using uint = unsigned; using ull = unsigned long long; template <class t, size_t n> ostream& operator<<(ostream& os, const array<t, n>& first) { return os << vc<t>(first.begin(), first.end()); } template <int i, class T> void print_tuple(ostream&, const T&) {} template <int i, class T, class H, class... Args> void print_tuple(ostream& os, const T& t) { if (i) os << , ; os << get<i>(t); print_tuple<i + 1, T, Args...>(os, t); } template <class... Args> ostream& operator<<(ostream& os, const tuple<Args...>& t) { os << { ; print_tuple<0, tuple<Args...>, Args...>(os, t); return os << } ; } template <class t> void print(t x, int suc = 1) { cout << x; if (suc == 1) cout << n ; if (suc == 2) cout << ; } ll read() { ll i; cin >> i; return i; } vi readvi(int n, int off = 0) { vi v(n); for (int i = int(0); i < int(n); i++) v[i] = read() + off; return v; } template <class T> void print(const vector<T>& v, int suc = 1) { for (int i = int(0); i < int(v.size()); i++) print(v[i], i == int(v.size()) - 1 ? suc : 2); } string readString() { string s; cin >> s; return s; } template <class T> T sq(const T& t) { return t * t; } void yes(bool ex = true) { cout << Yes << n ; if (ex) exit(0); } void no(bool ex = true) { cout << No << n ; if (ex) exit(0); } void possible(bool ex = true) { cout << Possible << n ; if (ex) exit(0); } void impossible(bool ex = true) { cout << Impossible << n ; if (ex) exit(0); } constexpr ll ten(int n) { return n == 0 ? 1 : ten(n - 1) * 10; } const ll infLL = LLONG_MAX / 3; const int inf = INT_MAX / 2 - 100; int topbit(signed t) { return t == 0 ? -1 : 31 - __builtin_clz(t); } int topbit(ll t) { return t == 0 ? -1 : 63 - __builtin_clzll(t); } int botbit(signed first) { return first == 0 ? 32 : __builtin_ctz(first); } int botbit(ll first) { return first == 0 ? 64 : __builtin_ctzll(first); } int popcount(signed t) { return __builtin_popcount(t); } int popcount(ll t) { return __builtin_popcountll(t); } bool ispow2(int i) { return i && (i & -i) == i; } ll mask(int i) { return (ll(1) << i) - 1; } bool inc(int first, int second, int c) { return first <= second && second <= c; } template <class t> void mkuni(vc<t>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } ll rand_int(ll l, ll r) { static mt19937_64 gen(chrono::steady_clock::now().time_since_epoch().count()); return uniform_int_distribution<ll>(l, r)(gen); } template <class t> void myshuffle(vc<t>& first) { for (int i = int(0); i < int(int(first.size())); i++) swap(first[i], first[rand_int(0, i)]); } template <class t> int lwb(const vc<t>& v, const t& first) { return lower_bound(v.begin(), v.end(), first) - v.begin(); } using uint = unsigned; using ull = unsigned long long; struct modinfo { uint mod, root; }; template <modinfo const& ref> struct modular { static constexpr uint const& mod = ref.mod; static modular root() { return modular(ref.root); } uint v; modular(ll vv = 0) { s(vv % mod + mod); } modular& s(uint vv) { v = vv < mod ? vv : vv - mod; return *this; } modular operator-() const { return modular() - *this; } modular& operator+=(const modular& rhs) { return s(v + rhs.v); } modular& operator-=(const modular& rhs) { return s(v + mod - rhs.v); } modular& operator*=(const modular& rhs) { v = ull(v) * rhs.v % mod; return *this; } modular& operator/=(const modular& rhs) { return *this *= rhs.inv(); } modular operator+(const modular& rhs) const { return modular(*this) += rhs; } modular operator-(const modular& rhs) const { return modular(*this) -= rhs; } modular operator*(const modular& rhs) const { return modular(*this) *= rhs; } modular operator/(const modular& rhs) const { return modular(*this) /= rhs; } modular pow(int n) const { modular res(1), x(*this); while (n) { if (n & 1) res *= x; x *= x; n >>= 1; } return res; } modular inv() const { return pow(mod - 2); } friend modular operator+(int x, const modular& y) { return modular(x) + y; } friend modular operator-(int x, const modular& y) { return modular(x) - y; } friend modular operator*(int x, const modular& y) { return modular(x) * y; } friend modular operator/(int x, const modular& y) { return modular(x) / y; } friend ostream& operator<<(ostream& os, const modular& m) { return os << m.v; } friend istream& operator>>(istream& is, modular& m) { ll x; is >> x; m = modular(x); return is; } bool operator<(const modular& r) const { return v < r.v; } bool operator==(const modular& r) const { return v == r.v; } bool operator!=(const modular& r) const { return v != r.v; } explicit operator bool() const { return v; } }; extern constexpr modinfo base{998244353, 3}; using mint = modular<base>; const int vmax = (1 << 21) + 10; mint fact[vmax], finv[vmax], invs[vmax]; void initfact() { fact[0] = 1; for (int i = int(1); i < int(vmax); i++) { fact[i] = fact[i - 1] * i; } finv[vmax - 1] = fact[vmax - 1].inv(); for (int i = vmax - 2; i >= 0; i--) { finv[i] = finv[i + 1] * (i + 1); } for (int i = vmax - 1; i >= 1; i--) { invs[i] = finv[i] * fact[i - 1]; } } mint choose(int n, int k) { return fact[n] * finv[n - k] * finv[k]; } mint binom(int first, int second) { return fact[first + second] * finv[first] * finv[second]; } mint catalan(int n) { return binom(n, n) - (n - 1 >= 0 ? binom(n - 1, n + 1) : 0); } void swapbit(ll& first, int i, int j) { if (i == j) return; for (int _ = int(0); _ < int(3); _++) { ll x = (first >> i) & 1; first ^= x << j; swap(i, j); } } const int S = 17; mint dp[S + 1][1 << S]; signed main() { cin.tie(0); ios::sync_with_stdio(0); cout << fixed << setprecision(20); int n, m; cin >> n >> m; vc<ll> vs; mint w = 1; for (int _ = int(0); _ < int(n); _++) { ll first; cin >> first; for (auto v : vs) chmin(first, first ^ v); if (first == 0) w *= 2; else vs.push_back(first); } vc<mint> ans(m + 1); int s = int(vs.size()); if (int(vs.size()) <= 18) { for (int bit = int(0); bit < int(1 << s); bit++) { ll x = 0; for (int i = int(0); i < int(s); i++) if (bit & 1 << i) x ^= vs[i]; ans[popcount(x)] += 1; } } else { for (int i = int(0); i < int(s); i++) { assert(vs[i]); int j = botbit(vs[i]); assert(j >= i); for (int k = int(0); k < int(s); k++) if (k != i && vs[k] & 1LL << j) vs[k] ^= vs[i]; for (int k = int(0); k < int(s); k++) swapbit(vs[k], i, j); } int len = m - s; assert(len <= S); dp[0][0] = 1; for (int i = int(0); i < int(s); i++) { int v = vs[i] >> s; for (int j = int(i + 1) - 1; j >= int(0); j--) { for (int k = int(0); k < int(1 << len); k++) { dp[j + 1][k ^ v] += dp[j][k]; } } } for (int i = int(0); i < int(s + 1); i++) for (int j = int(0); j < int(1 << len); j++) { ans[i + popcount(j)] += dp[i][j]; } } for (auto& v : ans) v *= w; print(ans); }
|
//======================================================================
//
// tb_mkmif_core.v
// ---------------
// Testbench for the mkmif core module.
//
//
// Copyright (c) 2016, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_mkmif_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] test_ctr;
reg [31 : 0] error_ctr;
reg tb_clk;
reg tb_reset_n;
wire tb_spi_sclk;
wire tb_cs_n;
wire tb_spi_do;
wire tb_spi_di;
reg tb_read_op;
reg tb_write_op;
reg tb_init_op;
wire tb_ready;
wire tb_valid;
reg [15 : 0] tb_sclk_div;
reg [15 : 0] tb_addr;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
reg tb_display_state;
reg [31 : 0] read_data;
//----------------------------------------------------------------
// Concurrent connectivity.
//----------------------------------------------------------------
// We loop back the inverted SPI serial transmit data from
// the DUT as the data from the memory (do) to the DUT.
assign tb_spi_do = ~tb_spi_di;
//----------------------------------------------------------------
// mkmif device under test.
//----------------------------------------------------------------
mkmif_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.spi_sclk(tb_spi_sclk),
.spi_cs_n(tb_cs_n),
.spi_do(tb_spi_do),
.spi_di(tb_spi_di),
.read_op(tb_read_op),
.write_op(tb_write_op),
.init_op(tb_init_op),
.ready(tb_ready),
.valid(tb_valid),
.sclk_div(tb_sclk_div),
.addr(tb_addr),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
// Monitor for observing the inputs and outputs to the dut.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (tb_display_state)
begin
$display("cycle = %8x:", cycle_ctr);
dump_state();
end
end // dut_monitor
//----------------------------------------------------------------
// inc_test_ctr
//----------------------------------------------------------------
task inc_test_ctr;
begin
test_ctr = test_ctr +1;
end
endtask // inc_test_ctr
//----------------------------------------------------------------
// inc_error_ctr
//----------------------------------------------------------------
task inc_error_ctr;
begin
error_ctr = error_ctr +1;
end
endtask // inc_error_ctr
//----------------------------------------------------------------
// dump_state
// Dump the internal MKMIF state to std out.
//----------------------------------------------------------------
task dump_state;
begin
$display("mkmif_ctrl_reg: 0x%02x", dut.mkmif_ctrl_reg);
$display("sclk: 0x%01x, cs_n: 0x%01x, di: 0x%01x, do: 0x%01x, nxt: 0x%01x",
tb_spi_sclk, tb_cs_n, tb_spi_di, tb_spi_do, dut.spi.data_nxt);
$display("spi_ctrl_reg: 0x%01x, spi_clk_ctr: 0x%04x, spi_bit_ctr: 0x%02x",
dut.spi.spi_ctrl_reg, dut.spi.clk_ctr_reg, dut.spi.bit_ctr_reg);
$display("spi length: 0x%02x, spi divisor: 0x%04x, spi set: 0x%01x, spi start: 0x%01x, spi ready: 0x%01x",
dut.spi.length_reg, dut.spi.divisor_reg, dut.spi.set, dut.spi.start, dut.spi.ready);
$display("read data: 0x%08x, write_data: 0x%014x", dut.spi.rd_data, dut.spi.wr_data);
$display("");
end
endtask // dump_state
//----------------------------------------------------------------
// tb_init
// Initialize varibles, dut inputs at start.
//----------------------------------------------------------------
task tb_init;
begin
test_ctr = 0;
error_ctr = 0;
cycle_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_read_op = 0;
tb_write_op = 0;
tb_init_op = 0;
tb_sclk_div = 16'h0004;
tb_addr = 16'h0010;
tb_write_data = 32'haa55aa55;
tb_display_state = 1;
end
endtask // tb_init
//----------------------------------------------------------------
// wait_ready()
//
// Wait for ready word to be set in the DUT API.
//----------------------------------------------------------------
task wait_ready;
reg ready;
begin
ready = 0;
while (tb_ready == 0)
begin
#(CLK_PERIOD);
end
end
endtask // read_word
//----------------------------------------------------------------
// toggle_reset
// Toggle the reset.
//----------------------------------------------------------------
task toggle_reset;
begin
$display(" -- Toggling reset.");
dump_state();
#(2 * CLK_PERIOD);
tb_reset_n = 0;
#(10 * CLK_PERIOD);
@(negedge tb_clk)
tb_reset_n = 1;
dump_state();
$display(" -- Toggling of reset done.");
$display("");
end
endtask // toggle_reset
//----------------------------------------------------------------
// write_test
//----------------------------------------------------------------
task write_test;
begin
$display(" -- Write Test started.");
inc_test_ctr();
wait_ready();
tb_sclk_div = 16'h0004;
tb_addr = 16'h0012;
tb_write_data = 32'hdeadbeef;
tb_write_op = 1;
#(2 * CLK_PERIOD);
tb_write_op = 0;
wait_ready();
$display(" -- Write Test done.");
$display("");
end
endtask // write_test
//----------------------------------------------------------------
// mkmif_core_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : mkmif__core_test
$display(" -- Test of mkmif core started --");
tb_init();
toggle_reset();
write_test();
$display("");
$display(" -- Test of mkmif core completed --");
$display("Tests executed: %04d", test_ctr);
$display("Tests failed: %04d", error_ctr);
$finish;
end // mkmif_core_test
endmodule // tb_mkmif_core
//======================================================================
// EOF tb_mkmif_core.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<long long int> s(n); for (int i = 0; i < n; ++i) cin >> s[i]; int q; cin >> q; sort(s.begin(), s.end()); int slope0 = 1; for (int i = 1; i < n; ++i) if (s[i] != s[i - 1]) ++slope0; map<long long int, int> freq; for (int i = 1; i < n; ++i) { long long int delta = s[i] - s[i - 1]; if (delta == 0) continue; delta--; if (freq.find(delta) == freq.end()) freq[delta] = 1; else freq[delta] = freq[delta] + 1; } map<long long int, int> slope; map<long long int, long long int> obj; long long int prev = slope0; for (map<long long int, int>::iterator it = freq.begin(); it != freq.end(); ++it) { slope[it->first] = prev - it->second; prev = prev - it->second; } if (slope.find(0) == slope.end()) slope[0] = slope0; for (map<long long int, int>::iterator it = slope.begin(); it != slope.end();) { if (it->first == 0) obj[0] = slope0; long long int y0 = obj[it->first]; long long int change = it->second; long long int base = it->first; ++it; if (it != slope.end()) obj[it->first] = y0 + change * (it->first - base); } for (int i = 0; i < q; ++i) { long long int l, r; cin >> l >> r; map<long long int, long long int>::iterator it = obj.lower_bound(r - l); if (it->first == (r - l)) cout << it->second << ; else { it--; long long int ans = obj[it->first] + (r - l - it->first) * slope[it->first]; cout << ans << ; } } cout << n ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( -fdelete-null-pointer-checks,inline-functions-called-once,-funsafe-loop-optimizations,-fexpensive-optimizations,-foptimize-sibling-calls,-ftree-switch-conversion,-finline-small-functions,inline-small-functions,-frerun-cse-after-loop,-fhoist-adjacent-loads,-findirect-inlining,-freorder-functions,no-stack-protector,-fpartial-inlining,-fsched-interblock,-fcse-follow-jumps,-fcse-skip-blocks,-falign-functions,-fstrict-overflow,-fstrict-aliasing,-fschedule-insns2,-ftree-tail-merge,inline-functions,-fschedule-insns,-freorder-blocks,-fwhole-program,-funroll-loops,-fthread-jumps,-fcrossjumping,-fcaller-saves,-fdevirtualize,-falign-labels,-falign-loops,-falign-jumps,unroll-loops,-fsched-spec,-ffast-math,Ofast,inline,-fgcse,-fgcse-lm,-fipa-sra,-ftree-pre,-ftree-vrp,-fpeephole2 , 3) #pragma GCC target( avx , sse2 ) const double esp = 1e-6; const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const int inf = 1e9; using namespace std; long long read() { char ch = getchar(); long long x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int N = 6e5 + 10; const int diff = 3e5; int Q; struct node { int pos, to, h; long long cntx, cnty; node(int pos, int to, int h, long long cntx, long long cnty) { this->pos = pos, this->to = to, this->h = h, this->cntx = cntx, this->cnty = cnty; } }; struct DSU { int par[N], height[N]; long long cntx[N], cnty[N]; long long sum = 0; DSU() { for (int i = 1; i <= 6e5 + 1; i++) { par[i] = i, height[i] = 1; if (i <= 3e5) cntx[i] = 1; else cnty[i] = 1; } } int find(int x) { return x == par[x] ? x : find(par[x]); } int unit(int x, int y, stack<node> &st) { x = find(x), y = find(y); if (x == y) return 0; if (height[x] < height[y]) swap(x, y); node sttemp(y, x, height[y], cntx[y], cnty[y]); st.push(sttemp); sum -= cntx[x] * cnty[x]; sum -= cntx[y] * cnty[y]; cntx[x] += cntx[y]; cnty[x] += cnty[y]; sum += cntx[x] * cnty[x]; par[y] = x; height[x] += height[y]; return 1; } void del(stack<node> &st) { while (st.size()) { node temp = st.top(); st.pop(); par[temp.pos] = temp.pos; height[temp.to] -= temp.h; sum -= cntx[temp.to] * cnty[temp.to]; cntx[temp.to] -= temp.cntx; cnty[temp.to] -= temp.cnty; sum += cntx[temp.to] * cnty[temp.to]; sum += temp.cntx * temp.cnty; } } } dsu; struct SEG { vector<pair<int, int> > tr[N << 2]; void update(int l, int r, int root, int lf, int rt, pair<int, int> val) { if (lf <= l && r <= rt) { tr[root].push_back(val); return; } int mid = (l + r) >> 1; if (lf <= mid) update(l, mid, root << 1, lf, rt, val); if (rt > mid) update(mid + 1, r, root << 1 | 1, lf, rt, val); } void query(int l, int r, int root) { stack<node> st; for (auto k : tr[root]) { dsu.unit(k.first, k.second + diff, st); } if (l == r) { printf( %lld , dsu.sum); dsu.del(st); return; } int mid = (l + r) >> 1; query(l, mid, root << 1); query(mid + 1, r, root << 1 | 1); dsu.del(st); } } sgt; map<pair<int, int>, pair<int, int> > mp; struct nd { int x, y, st, ed; }; vector<nd> query; int main() { Q = read(); int x, y; for (int i = 1; i <= Q; i++) { x = read(), y = read(); if (mp[{x, y}].first) { query.push_back(nd{x, y, mp[{x, y}].first, i - 1}); mp[{x, y}].first = 0; } else { mp[{x, y}].first = i; } } for (auto k : mp) { if (k.second.first) query.push_back(nd{k.first.first, k.first.second, k.second.first, Q}); } for (auto k : query) { sgt.update(1, Q, 1, k.st, k.ed, make_pair(k.x, k.y)); } sgt.query(1, Q, 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const long long INF = 1e9; long long b[N]; long long ans[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> b[i]; long long sum = 0; for (int i = 1; i <= n; ++i) sum += b[i]; long long x = (long long)n * (n + 1) / 2; if (sum % x != 0) { cout << NO << n ; } else { sum /= x; bool cek = true; for (int i = 1; i <= n; ++i) { int p = (i + n - 2) % n + 1; if ((sum - b[i] + b[p]) % n != 0) cek = false; ans[i] = (sum - b[i] + b[p]) / n; } for (int i = 1; i <= n; ++i) { if (ans[i] <= 0 || ans[i] > INF) cek = false; } if (cek) { cout << YES << n ; for (int i = 1; i <= n; ++i) { cout << ans[i]; if (i < n) cout << ; } cout << n ; } else { cout << NO << n ; } } } return 0; }
|
//
// Testbench
//
// by
// David M. Koltak 05/30/2017
//
// The MIT License (MIT)
//
// Copyright (c) 2017 David M. Koltak
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
module testbench();
reg sim_rst;
reg sim_clk;
reg sim_clk_gen;
integer cycle_count;
initial
begin
sim_rst = 1;
sim_clk_gen = 0;
$dumpfile("results.vcd");
$dumpvars(0);
cycle_count = 0;
#10 sim_rst = 0;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#5 sim_rst = 1;
#5 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen; sim_rst = 0;
while (1)
begin
#10 sim_clk_gen = ~sim_clk_gen;
cycle_count = (sim_clk_gen) ? cycle_count : cycle_count + 1;
end
end
always @ (sim_clk_gen)
sim_clk <= sim_clk_gen;
integer CLOCK_LIMIT;
wire [4:0] user_leds;
reg [31:0] test_progress;
always @ (posedge sim_clk or posedge sim_rst)
if (sim_rst)
begin
CLOCK_LIMIT <= 32'd0;
test_progress <= de0_nano_soc.testregs.test_progress;
end
else
begin
CLOCK_LIMIT <= CLOCK_LIMIT + 32'd1;
if (CLOCK_LIMIT === `MAX_CLOCKS)
begin
#20;
$display(" ****** MAX CLOCKS - ENDING SIMULATION *****");
$finish();
end
if (de0_nano_soc.testregs.test_progress != test_progress)
begin
test_progress <= de0_nano_soc.testregs.test_progress;
$display(" ****** TEST PROGRESS %X *****",
de0_nano_soc.testregs.test_progress);
end
if (de0_nano_soc.testregs.test_fail != 32'd0)
begin
#20;
$display(" ****** TEST FAILED %08X *****" ,
de0_nano_soc.testregs.test_fail);
$finish();
end
if (de0_nano_soc.testregs.test_pass != 32'd0)
begin
#20;
$display(" ****** TEST PASSED %08X *****" ,
de0_nano_soc.testregs.test_pass);
$finish();
end
end
reg sim_clk_slow;
reg sim_clk_slow_gen;
initial
begin
sim_clk_slow_gen = 0;
while (1)
begin
#33 sim_clk_slow_gen = ~sim_clk_slow_gen;
end
end
always @ (sim_clk_slow_gen)
sim_clk_slow <= sim_clk_slow_gen;
wire uart_tx;
wire uart_rx;
de0_nano_soc de0_nano_soc
(
.FPGA_CLK1_50(sim_clk),
.FPGA_CLK2_50(sim_clk_slow),
.FPGA_CLK3_50(~sim_clk),
.BUTTON({1'b1, !sim_rst}),
.SW(4'd0),
.LED(),
.UART_TX(uart_tx),
.UART_RX(uart_rx),
.SPDR_TX(uart_rx),
.SPDR_RX(uart_tx)
);
endmodule
|
/*
File: fifo_empty_block.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_empty_block (/*AUTOARG*/
// Outputs
rd_fifo_empty, rd_addr, rd_gray_pointer,
// Inputs
reset, rd_clk, rd_wr_gray_pointer, rd_read
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input rd_clk;
input [AW:0] rd_wr_gray_pointer;//from other clock domain
input rd_read;
//###########
//# OUTPUTS
//###########
output rd_fifo_empty;
output [AW-1:0] rd_addr;
output [AW:0] rd_gray_pointer;
//#########
//# REGS
//#########
reg [AW:0] rd_gray_pointer;
reg [AW:0] rd_binary_pointer;
reg rd_fifo_empty;
//##########
//# WIRES
//##########
wire rd_fifo_empty_next;
wire [AW:0] rd_binary_next;
wire [AW:0] rd_gray_next;
//Counter States
always @(posedge rd_clk or posedge reset)
if(reset)
begin
rd_binary_pointer[AW:0] <= {(AW+1){1'b0}};
rd_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(rd_read)
begin
rd_binary_pointer[AW:0] <= rd_binary_next[AW:0];
rd_gray_pointer[AW:0] <= rd_gray_next[AW:0];
end
//Read Address
assign rd_addr[AW-1:0] = rd_binary_pointer[AW-1:0];
//Updating binary pointer
assign rd_binary_next[AW:0] = rd_binary_pointer[AW:0] +
{{(AW){1'b0}},rd_read};
//Gray Pointer Conversion (for more reliable synchronization)!
assign rd_gray_next[AW:0] = {1'b0,rd_binary_next[AW:1]} ^
rd_binary_next[AW:0];
//# FIFO empty indication
assign rd_fifo_empty_next = (rd_gray_next[AW:0]==rd_wr_gray_pointer[AW:0]);
always @ (posedge rd_clk or posedge reset)
if(reset)
rd_fifo_empty <= 1'b1;
else
rd_fifo_empty <= rd_fifo_empty_next;
endmodule // fifo_empty_block
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; struct data { int points; string name; data(int p, string n) { points = p; name = n; } data() { points = -1; name = ; } }; inline bool cmp(data d1, data d2) { return (d1.points > d2.points); } int main() { int n, m, r, points; cin >> n >> m; string name; vector<vector<data>> reg(m); for (auto i(0); i < n; ++i) { cin >> name >> r >> points; r--; if (reg[r].size() < 3) { reg[r].push_back(data(points, name)); sort(reg[r].begin(), reg[r].end(), cmp); } else { reg[r].push_back(data(points, name)); sort(reg[r].begin(), reg[r].end(), cmp); reg[r].resize(3); } } for (auto i(0); i < m; ++i) { if (reg[i].size() == 2) { cout << reg[i][0].name << << reg[i][1].name << endl; ; } else if (reg[i][1].points == reg[i][2].points) { cout << ? << endl; } else { cout << reg[i][0].name << << reg[i][1].name << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int c = 0, h = 0; while (n > c + h) { h++; c += h; n -= c; } cout << h << endl; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:30:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_g8_1_0 -prefix
// system_rgb888_to_g8_1_0_ system_rgb888_to_g8_1_0_stub.v
// Design : system_rgb888_to_g8_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
module system_rgb888_to_g8_1_0(clk, rgb888, g8)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb888[23:0],g8[7:0]" */;
input clk;
input [23:0]rgb888;
output [7:0]g8;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int ans = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) ans = (ans << 3) + (ans << 1) + (c ^ 48), c = getchar(); return ans; } int fa[5005], cnt[5005], sum[5005], dep[5005], bad[5005]; int main() { sum[1] = 1; for (int i = 2; i < 5005; i++) sum[i] = i + sum[i / 2] + sum[i - i / 2 - 1]; for (int i = 1; i < 5005; i++) sum[i] -= i; for (int T = read(); T; T--) { int n, d; n = read(), d = read(); int cur = n * (n - 1) / 2; if (d < sum[n] || d > cur) { puts( NO ); continue; } fa[1] = 0; for (int i = 2; i <= n; i++) fa[i] = i - 1; for (int i = 1; i < n; i++) cnt[i] = 1; cnt[n] = 0; for (int i = 1; i <= n; i++) bad[i] = 0, dep[i] = i - 1; while (cur > d) { int u; for (u = 1; u <= n; u++) if (!cnt[u] && !bad[u]) break; bad[u] = 1; for (int p = 1; p <= n; p++) if (cnt[p] < 2 && dep[u] - dep[p] == 2) { --cnt[fa[u]], fa[u] = p; dep[u] = dep[p] + 1, ++cnt[p]; bad[u] = 0, --cur; break; } } puts( YES ); for (int i = 2; i <= n; i++) printf( %d%c , fa[i], n [i == n]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const double oula = 0.57721566490153286060651209; using namespace std; map<long long, string> mp; int main() { std::ios::sync_with_stdio(false); long long n; cin >> n; long long nn = sqrt(n); string tmp; for (long long i = 2; i <= nn; i++) { long long num = i * i; int co = 2; while (num <= n) { tmp = to_string(i) + ^ + to_string(co); if (!mp.count(num)) mp[num] = to_string(num); if (mp[num].size() > tmp.size()) mp[num] = tmp; co++; num *= i; } } string ans = to_string(n); map<long long, string>::iterator it; for (it = mp.begin(); it != mp.end(); it++) { tmp = ; long long a = n / it->first, b = n % it->first; if (a > 1) { if (mp.count(a)) tmp = mp[a]; else tmp = to_string(a); tmp += * ; } tmp += it->second; if (b) tmp = tmp + + + (mp.count(b) ? mp[b] : to_string(b)); if (ans.size() > tmp.size()) ans = tmp; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long maxx = 1e5 + 20, sqr = 150, mod = 1e9 + 7; long long len, n, dp[maxx][sqr][2], q, pw25[maxx], pw26[maxx], pwmod[maxx], fac[maxx], tmp[maxx]; string s; long long pw(long long a, long long b) { if (!b) return 1ll; long long x = pw(a, b / 2); x = (x * x) % mod; if (b % 2) x = (x * a) % mod; return x; } long long sel(long long a, long long b) { long long x = 1ll; x = (x * fac[a]) % mod; x = (x * pwmod[b]) % mod; x = (x * pwmod[a - b]) % mod; return x; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); pw25[0] = pw26[0] = 1; for (long long i = 1; i < maxx; i++) pw25[i] = (pw25[i - 1] * 25) % mod, pw26[i] = (pw26[i - 1] * 26) % mod; fac[0] = 1; for (long long i = 1; i < maxx; i++) fac[i] = (fac[i - 1] * i) % mod; for (long long i = 0; i < maxx; i++) pwmod[i] = pw(fac[i], mod - 2); for (long long j = 0; j < sqr; j++) { dp[j][j][1] = dp[j][j][0] = 1; for (long long i = j + 1; i < maxx; i++) { dp[i][j][0] = (((dp[i - 1][j][0] * 26) % mod) + (j >= 1 ? dp[i - 1][j - 1][1] : 0)) % mod; dp[i][j][1] = (((dp[i - 1][j][1] * 25) % mod) + (j >= 1 ? dp[i - 1][j - 1][1] : 0)) % mod; } } long long c = 0; cin >> n >> s; len = s.length(); if (len >= sqr) { fill(tmp, tmp + maxx, 0); tmp[len - 1] = 1; for (long long j = len; j < maxx; j++) tmp[j] = (((tmp[j - 1] * 26ll) % mod) + (((long long)sel(j, len - 1) * pw25[j + 1 - len]) % mod)) % mod; } for (long long i = 0; i < n; i++) { long long type; cin >> type; if (type == 1) { cin >> s, len = s.length(); if (len >= sqr) { fill(tmp, tmp + maxx, 0); tmp[len - 1] = 1; for (long long j = len; j < maxx; j++) tmp[j] = (((tmp[j - 1] * 26ll) % mod) + (((long long)sel(j, len - 1) * pw25[j + 1 - len]) % mod)) % mod; } } else { c++; cin >> q; if (len < sqr) { if (len > q) cout << 0 << n ; else cout << dp[q][len][0] << n ; continue; } long long ans = 0ll; cout << tmp[q - 1] << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k, i, x, y, z, suma; pair<int, pair<int, int> > r1, r2, tr0, v[35]; map<pair<int, pair<int, int> >, pair<int, pair<int, int> > > mp; pair<int, pair<int, int> > make_triplet(int x, int y, int z) { return make_pair(x, make_pair(y, z)); } int getSum(int bts) { int S = 0; int j = 0; for (j = 0; j < m; j++) if ((1 << j) & bts) S += v[j + 1].first; return S; } void bck1(int pas, int s1, int s2, int s3, int bt1, int bt2, int bt3) { if (pas > m) return; if (pas == m) { int minim = min(s1, min(s2, s3)); pair<int, pair<int, int> > sum = make_triplet(s1 - minim, s2 - minim, s3 - minim); pair<int, pair<int, int> > bt = make_triplet(bt1, bt2, bt3); int S = -((1 << 30) - 1 + (1 << 30)); if (mp.count(sum)) S = getSum(mp[sum].first); if (S < s1) mp[sum] = bt; return; } int i = pas + 1; bck1(pas + 1, s1 + v[i].first, s2 + v[i].second.first, s3, bt1 + (1 << pas), bt2 + (1 << pas), bt3); bck1(pas + 1, s1 + v[i].first, s2, s3 + v[i].second.second, bt1 + (1 << pas), bt2, bt3 + (1 << pas)); bck1(pas + 1, s1, s2 + v[i].second.first, s3 + v[i].second.second, bt1, bt2 + (1 << pas), bt3 + (1 << pas)); } void bck2(int pas, int s1, int s2, int s3, int bt1, int bt2, int bt3) { if (pas > k) return; if (pas == k) { int maxim = max(s1, max(s2, s3)); pair<int, pair<int, int> > sum = make_triplet(maxim - s1, maxim - s2, maxim - s3); if (mp.count(sum)) { pair<int, pair<int, int> > sum1 = mp[sum]; int S = getSum(sum1.first); if (S + s1 > suma) { suma = S + s1; r1 = sum1; r2 = make_triplet(bt1, bt2, bt3); } } return; } int i = pas + m + 1; bck2(pas + 1, s1 + v[i].first, s2 + v[i].second.first, s3, bt1 + (1 << pas), bt2 + (1 << pas), bt3); bck2(pas + 1, s1 + v[i].first, s2, s3 + v[i].second.second, bt1 + (1 << pas), bt2, bt3 + (1 << pas)); bck2(pas + 1, s1, s2 + v[i].second.first, s3 + v[i].second.second, bt1, bt2 + (1 << pas), bt3 + (1 << pas)); } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d%d , &x, &y, &z); v[i] = make_triplet(x, y, z); } m = (n + 1) / 2; bck1(0, 0, 0, 0, 0, 0, 0); k = n - m; suma = -((1 << 30) - 1 + (1 << 30)); bck2(0, 0, 0, 0, 0, 0, 0); if (r1.first || r1.second.first || r1.second.second) { for (i = 0; i < m; i++) { if ((1 << i) & r1.first) printf( L ); if ((1 << i) & r1.second.first) printf( M ); if ((1 << i) & r1.second.second) printf( W ); printf( n ); } for (i = 0; i < k; i++) { if ((1 << i) & r2.first) printf( L ); if ((1 << i) & r2.second.first) printf( M ); if ((1 << i) & r2.second.second) printf( W ); printf( n ); } } else printf( Impossible ); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_schmitt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// DC Receiver(for boundary scan)
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_schmitt(
// Outputs
out,
// Inouts
in,
// Inputs
vddo );
output out;
input in;
inout vddo;
wire out = in;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:28 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: phase_align.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// PHASE_ALIGN
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: Phase alignment circuit for the comma alignment signal. Ensures
// that the enable comma align signal is syncronous with the MGT
// recovered clock.
//
`timescale 1 ns / 10 ps
module PHASE_ALIGN
(
//Aurora Lane Interface
ENA_COMMA_ALIGN,
//MGT Interface
RX_REC_CLK,
ENA_CALIGN_REC
);
`define DLY #1
//***********************************Port Declarations*******************************
//Aurora Lane Interface
input ENA_COMMA_ALIGN;
//MGT Interface
input RX_REC_CLK;
output ENA_CALIGN_REC;
//**************************External Register Declarations****************************
//**************************Internal Register Declarations****************************
reg [0:1] phase_align_flops_r;
//*********************************Wire Declarations**********************************
//*********************************Main Body of Code**********************************
// To phase align the signal, we sample it using a flop clocked with the recovered
// clock. We then sample the output of the first flop and pass it to the output.
// This ensures that the signal is not metastable, and prevents transitions from
// occuring except at the clock edge. The comma alignment circuit cannot tolerate
// transitions except at the recovered clock edge.
always @(posedge RX_REC_CLK)
begin
phase_align_flops_r[0] <= `DLY ENA_COMMA_ALIGN;
phase_align_flops_r[1] <= `DLY phase_align_flops_r[0];
end
assign ENA_CALIGN_REC = phase_align_flops_r[1];
endmodule
|
`ifndef _iq_
`define _iq_
// instruction queue
module iq(
input clk,
input rst,
input inst1_in_valid,
input [31:0] inst1_in,
input inst2_in_valid,
input [31:0] inst2_in,
input [31:0] inst1_in_pc4,
input [31:0] inst2_in_pc4,
input in_branch_valid,
input [31:0] in_btb_pc_predict,
input in_direct_predict,
input stall_backend,
input mispredict,
input singlemode, // single width
output logic iq_empty,
output logic iq_full,
output logic branch_valid,
output logic [31:0] btb_pc_predict,
output logic direct_predict,
output logic inst1_out_valid,
output logic [31:0] inst1_out,
output logic [31:0] inst1_out_pc4,
output logic inst2_out_valid,
output logic [31:0] inst2_out,
output logic [31:0] inst2_out_pc4
);
typedef struct packed{
logic [31:0] inst;
logic [31:0] pc4;
logic branch_valid;
logic [31:0] btb_pc_predict;
logic direct_predict;
} iqStruct;
iqStruct iq_array [15:0] ;
logic [4:0] iq_head_ext;
logic [4:0] iq_tail_ext;
logic [3:0] iq_head;
logic [3:0] iq_tail;
logic iq_near_empty;
logic iq_near_full;
logic iq_real_empty;
logic iq_real_full;
assign iq_head = iq_head_ext[3:0];
assign iq_tail = iq_tail_ext[3:0];
assign iq_real_empty = (iq_head_ext == iq_tail_ext);
assign iq_near_empty = (iq_head_ext + 1 == iq_tail_ext);
assign iq_real_full = (iq_head_ext != iq_tail_ext) && (iq_head == iq_tail);
assign iq_near_full = (iq_head_ext != iq_tail_ext + 1) && (iq_head == iq_tail + 1);
assign iq_empty = iq_real_empty || iq_near_empty;
assign iq_full = iq_real_full || iq_near_full;
always @(posedge clk, negedge rst) begin
if (!rst) begin
iq_tail_ext <= 5'b0;
iq_head_ext <= 5'b0;
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
inst1_out <= 32'h0;
inst2_out <= 32'h0;
branch_valid <= 1'b0;
btb_pc_predict <= 32'h0;
direct_predict <= 1'b0;
for ( int i = 0; i < $size(iq_array) ; i++) begin
iq_array[i] <= {$size(iqStruct){1'b0}};
end
end
else if (mispredict) begin
iq_tail_ext <= 5'b0;
iq_head_ext <= 5'b0;
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
inst1_out <= 32'h0;
inst2_out <= 32'h0;
for ( int i = 0; i < $size(iq_array) ; i++) begin
iq_array[i] <= {$size(iqStruct){1'b0}};
end
end
else begin
// enqueue 2 instructions
if (inst1_in_valid && inst2_in_valid && !iq_near_full && !iq_real_full && !singlemode) begin
iq_array[iq_tail].inst <= inst1_in;
iq_array[iq_tail+1].inst <= inst2_in;
iq_array[iq_tail].pc4 <= inst1_in_pc4;
iq_array[iq_tail+1].pc4 <= inst2_in_pc4;
//fixme:only handle sigle instruction for branch now
iq_tail_ext <= iq_tail_ext + 2;
end
// enqueue 1 instruction
else if (inst1_in_valid && !inst2_in_valid && !iq_real_full) begin
iq_array[iq_tail].inst <= inst1_in;
iq_array[iq_tail].pc4 <= inst1_in_pc4;
iq_array[iq_tail].branch_valid <= in_branch_valid;
iq_array[iq_tail].btb_pc_predict <= in_btb_pc_predict;
iq_array[iq_tail].direct_predict <= in_direct_predict;
iq_tail_ext <= iq_tail_ext + 1;
end
if (stall_backend) begin
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
end
//dequeue 2 instructions
else if (!iq_near_empty && !iq_real_empty && !singlemode) begin
iq_head_ext <= iq_head_ext + 2;
inst1_out_valid <= 1'b1;
inst1_out <= iq_array[iq_head].inst;
inst1_out_pc4 <= iq_array[iq_head].pc4;
inst2_out_valid <= 1'b1;
inst2_out <= iq_array[iq_head+1].inst;
inst2_out_pc4 <= iq_array[iq_head+1].pc4;
end
//dequeue 1 instruction
else if ((iq_near_empty && !iq_real_empty && !singlemode) ||
(!iq_real_empty && singlemode)) begin
iq_head_ext <= iq_head_ext + 1;
inst1_out_valid <= 1'b1;
inst1_out <= iq_array[iq_head].inst;
inst1_out_pc4 <= iq_array[iq_head].pc4;
inst2_out_valid <= 1'b0;
branch_valid <= iq_array[iq_head].branch_valid;
btb_pc_predict <= iq_array[iq_head].btb_pc_predict;
direct_predict <= iq_array[iq_head].direct_predict;
end
else begin
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
end
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
endmodule // iq
`endif
|
#include <bits/stdc++.h> using namespace std; vector<int> arr, hgt, res; int n; int func(int i, int j) {} int main() { int a, b, c, d, e, f, g; cin >> a; while (a--) { cin >> b; vector<int> num; for (int i = 0; i < b; i++) { cin >> c; num.push_back(c); } if (num[b - 1] < num[0]) { cout << NO << endl; } else { cout << YES << endl; } num.clear(); } }
|
#include <bits/stdc++.h> using namespace std; int n; int h[1000010], f[1000010][2]; void Work() { int ans = 0; for (int i = 1; i <= n; i++) { int l, r; l = min(h[i - 1], h[i]); r = min(h[i], h[i + 1]); if (l <= r) f[i][1] = 1LL * f[i - 1][1] * l % 1000000007; else { f[i][1] = 1LL * f[i - 1][1] * r % 1000000007; f[i][0] = 1LL * f[i - 1][1] * (l - r) % 1000000007; } f[i][1] += min(h[i], h[i + 1]); f[i][0] += h[i] - min(h[i], h[i + 1]); ans = ((long long)ans + f[i][1] + f[i][0]) % 1000000007; } printf( %d n , ans); } void Init() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &h[i]), h[i]--; h[n + 1] = 0x7f7f7f7f; } int main() { Init(); Work(); return 0; }
|
`timescale 1ns/1ps
module top;
lower dut();
endmodule
module lower;
parameter bad_name = "this_is_a_bad_name";
reg [15:0] def = "OK";
reg pass = 1'b1;
reg [1023:0] result;
real rl_res;
initial begin
#1;
/* Display the version and other information. */
$display("Testing with Icarus Verilog version: %g, subversion: %g",
$simparam("simulatorVersion"), $simparam("simulatorSubversion"));
$display("Using a CPU word size of %g bits.", $simparam("CPUWordSize"));
$display("Running in directory: %0s\n", $simparam$str("cwd"));
/*
* Check the time units and precision.
*
* Since this is double math check that the result is within a
* factor of 1e-10 of the correct value.
*/
rl_res = $simparam("timeUnit") - 1e-9;
rl_res = (rl_res < 0) ? -rl_res : rl_res;
if (rl_res > 1e-9*1e-10) begin
$display("$simparam(\"timeUnit\") failed, got %g.", rl_res);
pass = 1'b0;
end
rl_res = $simparam("timePrecision") - 1e-12;
rl_res = (rl_res < 0) ? -rl_res : rl_res;
if (rl_res >= 1e-12*1e-10) begin
$display("$simparam(\"timePrecision\") failed, got %g.", rl_res);
pass = 1'b0;
end
/* Check the string routines, see below for why this is a task. */
check_string;
/* Check that a bad parameter name with a default works. */
if ($simparam(bad_name, 1.0) != 1.0) begin
$display("$simparam with a bad name and a default value failed.");
pass = 1'b0;
end
result = $simparam$str(bad_name, def);
if (result[15:0] != "OK") begin
$display("$simparam$str with a bad name and a default value failed.");
pass = 1'b0;
end
/* These should also print an error message. */
if ($simparam(bad_name) != 0.0) begin
$display("$simparam with a bad name failed.");
pass = 1'b0;
end
result = $simparam$str(bad_name);
if (result[55:0] != "<error>") begin
$display("$simparam$str with a bad name failed.");
pass = 1'b0;
end
/* All these are currently unimplemented and just return 0.0 or N/A. */
if ($simparam("gdev") != 0.0) begin
$display("$simparam(\"gdev\") failed.");
pass = 1'b0;
end
if ($simparam("gmin") != 0.0) begin
$display("$simparam(\"gmin\") failed.");
pass = 1'b0;
end
if ($simparam("imax") != 0.0) begin
$display("$simparam(\"imax\") failed.");
pass = 1'b0;
end
if ($simparam("imelt") != 0.0) begin
$display("$simparam(\"imelt\") failed.");
pass = 1'b0;
end
if ($simparam("iteration") != 0.0) begin
$display("$simparam(\"iteration\") failed.");
pass = 1'b0;
end
if ($simparam("scale") != 0.0) begin
$display("$simparam(\"scale\") failed.");
pass = 1'b0;
end
if ($simparam("shrink") != 0.0) begin
$display("$simparam(\"shrink\") failed.");
pass = 1'b0;
end
if ($simparam("sourceScaleFactor") != 0.0) begin
$display("$simparam(\"sourceScaleFactor\") failed.");
pass = 1'b0;
end
if ($simparam("tnom") != 0.0) begin
$display("$simparam(\"tnom\") failed.");
pass = 1'b0;
end
result = $simparam$str("analysis_name");
if (result[23:0] != "N/A") begin
$display("$simparam$str(\"analysis_name\") failed.");
pass = 1'b0;
end
result = $simparam$str("analysis_type");
if (result[23:0] != "N/A") begin
$display("$simparam$str(\"analysis_type\") failed.");
pass = 1'b0;
end
if (pass) $display("\nPASSED");
end
/* We need this to make instance and path different. */
task check_string;
begin
result = $simparam$str("module");
if (result[39:0] != "lower") begin
$display("$simparam$str(\"module\") failed, got %0s.", result);
pass = 1'b0;
end
result = $simparam$str("instance");
if (result[55:0] != "top.dut") begin
$display("$simparam$str(\"instance\") failed, got %0s.", result);
pass = 1'b0;
end
result = $simparam$str("path");
if (result[159:0] != "top.dut.check_string") begin
$display("$simparam$str(\"instance\") failed, got %0s.", result);
pass = 1'b0;
end
end
endtask
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_keys (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4BB_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_SYMBOL_V
|
`timescale 1ns / 1ps
module rinse_mode
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 2)
(
input rinse_start, input start, input power, input [31:0]clk, input [2:0]weight,
output reg rinse_end_sign,
//light
output reg water_in_light, output reg rinsing_light,output reg water_out_light,
output [2:0]water_level, output reg dewatering_light, output reg [31:0]rinse_count,
output reg [2:0]state
);
reg [2:0]nextstate;
reg water_in_start, water_out_start, dewatering_start, rinsing_start; // submodules' start sign
wire [31:0]dewatering_count, rinsing_count, water_out_count, water_in_count; // count time
wire [2:0]water_level_rinse; // water level
wire water_in_end_sign, water_out_end_sign, dewatering_end_sign, rinsing_end_sign; // submodules' start sign
parameter water_out_state = 0, dewatering_state = 1, water_in_state = 2, rinsing_state = 3, rinse_end_state = 4;
initial begin
state = water_out_state;
nextstate = water_out_state;
water_out_light = 1'b0;
dewatering_light = 1'b0;
water_in_light = 1'b0;
rinsing_light = 1'b1; // light on when module start
water_in_start = 1'b0;
water_out_start = 1'b0;
dewatering_start = 1'b0;
rinsing_start = 1'b0;
end
assign water_level = (state == rinsing_state) ? weight : water_level_rinse;
// water_let mode run when start sign nd power are both true
water_let_mode #(WIDTH, CLK_CH, TIME_SCORE) WATER_IN_MODE (.water_in_end_sign(water_in_end_sign),
.water_in_start(water_in_start), // control water out
.water_out_start(water_out_start), // comtrol water in
.water_out_end_sign(water_out_end_sign),
.clk(clk),
.power(power),
.max_water_level(weight),
.start(start),
.water_level(water_level_rinse)
);
//count dewater time
timer #(WIDTH, CLK_CH, TIME_SCORE) DEWATERIGN_TIMER (.clk_src(clk),
.switch_power(power),
.switch_en(start),
.sum_count({{29{1'b0}},weight}),
.count_start_flag(dewatering_start),
.count_end_flag(dewatering_end_sign),
.count(dewatering_count)
);
//count rinse time
timer #(WIDTH, CLK_CH, TIME_SCORE) RINSING_TIMER (
.clk_src(clk),
.switch_power(power),
.switch_en(start),
.sum_count({{29{1'b0}},weight} * 2),
.count_start_flag(rinsing_start),
.count_end_flag(rinsing_end_sign),
.count(rinsing_count)
);
// change state
always @(posedge clk[0])
begin
if(rinse_start & power & start) state = nextstate;
else if(!(rinse_start & power)) state = water_out_state;
end
// control light
always @(posedge clk[CLK_CH])
if(rinse_start & power)
begin
case(state)
water_out_state: begin water_out_light = ~water_out_light; rinsing_light = 1'b1; end
dewatering_state: begin water_out_light = 1'b0; dewatering_light = ~dewatering_light; end
water_in_state: begin dewatering_light = 1'b0; water_in_light = ~water_in_light; end
rinsing_state: begin water_in_light = 1'b0; rinsing_light = ~rinsing_light; end
rinse_end_state: begin rinsing_light = 1'b0; end
endcase
end
else begin
water_out_light = 1'b0; dewatering_light = 1'b0; water_in_light = 1'b0; rinsing_light = 1'b1;
end
//control time and end sign
always @(posedge clk[0])
begin
if(rinse_start & power) begin
case(state)
water_out_state: begin rinse_count = {{29{1'b0}},weight} * 4 + {{29{1'b0}},water_level}; rinse_end_sign = 1'b0; end
dewatering_state: rinse_count = {{29{1'b0}},weight} * 3 + dewatering_count;
water_in_state: rinse_count = {{29{1'b0}},weight} * 3 - {{29{1'b0}},water_level};
rinsing_state: rinse_count = rinsing_count;
rinse_end_state: begin rinse_count = 0; rinse_end_sign = 1'b1; end
endcase
end
else begin
rinse_count = 0; rinse_end_sign = 1'b0;
end
end
// control submodules' start
always @(state or rinse_start or power or start)
if(rinse_start & power & start) begin
case(state)
water_out_state: begin water_out_start = 1'b1; water_in_start = 1'b0; dewatering_start = 1'b0; rinsing_start = 1'b0; end
dewatering_state: begin dewatering_start = 1'b1; water_out_start = 1'b0; water_in_start = 1'b0; rinsing_start = 1'b0; end
water_in_state: begin dewatering_start = 1'b0; water_in_start = 1'b1; water_out_start = 1'b0; rinsing_start = 1'b0; end
rinsing_state: begin water_in_start = 1'b0; rinsing_start = 1'b1; dewatering_start = 1'b0; water_out_start = 1'b0; end
rinse_end_state: begin water_in_start = 1'b0; rinsing_start = 1'b0; dewatering_start = 1'b0; water_out_start = 1'b0; end
endcase
end
else if(!(rinse_start & power)) begin
water_out_start = 1'b0; dewatering_start = 1'b0; water_in_start = 1'b0; rinsing_start = 1'b0;
end
// change nextstate when sign come
always @(water_in_end_sign or water_out_end_sign or dewatering_end_sign or rinsing_end_sign or rinse_start or power)
if(power & rinse_start)
begin
case(state)
water_out_state: begin
if(water_out_end_sign)
nextstate = dewatering_state;
else nextstate = water_out_state;
end
dewatering_state: begin
if(dewatering_end_sign)
nextstate = water_in_state;
else nextstate = dewatering_state;
end
water_in_state: begin
if(water_in_end_sign) nextstate = rinsing_state;
else nextstate = water_in_state;
end
rinsing_state: begin
if(rinsing_end_sign) nextstate = rinse_end_state;
else nextstate = rinsing_state;
end
rinse_end_state: begin
nextstate = rinse_end_state;
end
endcase
end else nextstate = water_out_state;
endmodule
|
// file: clk_wiz_v3_3_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_wiz_v3_3_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_3_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int mod = 1e9 + 7; int main() { int n; cin >> n; map<string, int> mp; for (int i = 0; i < n; i++) { string s; cin >> s; if (mp.find(s) != mp.end()) { cout << YES n ; continue; } else { cout << NO n ; mp[s] = 1; } } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; const int N6 = 1e6 + 6; const int N9 = 1e9 + 7; const long long INFLL = (long long)1e18 + 100; const int INF = 1e9 + 100; const long long mod = 1e9 + 9; const long long P = 31; int n, k, cur, ans; std::vector<int> g[1111]; map<pair<int, int>, bool> cnt; void solve() { cin >> n >> k; int cur; for (int i = 1; i <= n; ++i) { cur = 0; for (int j = 1; j <= n; ++j) { if (!cnt.count(make_pair(i, j)) && i != j) { ++cur; cnt[make_pair(i, j)]; cnt[make_pair(j, i)]; g[i].push_back(j); ++ans; } if (cur == k) { break; } } if (cur != k) { cout << -1; exit(0); } } cout << ans << n ; for (int i = 1; i <= n; ++i) { for (int j = 0; j < g[i].size(); ++j) { cout << i << << g[i][j] << n ; } } } int main() { int tt = 1; while (tt--) { solve(); } return 0; }
|
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