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#include <bits/stdc++.h> using namespace std; int s0, t0, t1, n, m, Next[500000 + 5]; char s[500000 + 5], t[500000 + 5]; void GetNext() { Next[0] = -1; int j = 0, k = -1; while (j < m) { if (!~k || t[j] == t[k]) Next[++j] = ++k; else k = Next[k]; } } int main() { scanf( %s%s , s, t); n = strlen(s), m = strlen(t); GetNext(); for (int i = 0; s[i]; i++) s0 += s[i] == 0 ; for (int i = 0; t[i]; i++) t0 += t[i] == 0 ; for (int i = Next[m]; t[i]; i++) t1 += t[i] == 0 ; int A = t0, B = m - t0, l = m - Next[m], step = 0; while (A + t1 <= s0 && B + l - t1 <= n - s0) A += t1, B += l - t1, step++; if (t0 <= s0 && m - t0 <= n - s0) { printf( %s , t); for (int i = 0; i < step; i++) printf( %s , t + Next[m]); for (int i = s0 - A; i; i--) putchar( 0 ); for (int i = n - s0 - B; i; i--) putchar( 1 ); puts( ); } else printf( %s n , s); return 0; }
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#include <cstdio> #include <iostream> #include <cstring> #include <queue> using namespace std; const int M = 2005; const int inf = 0x3f3f3f3f; #define int long long int read() { int x=0,f=1;char c; while((c=getchar())< 0 || c> 9 ) {if(c== - ) f=-1;} while(c>= 0 && c<= 9 ) {x=(x<<3)+(x<<1)+(c^48);c=getchar();} return x*f; } int n,m,k,t,mx,a[M],b[M],d[M],del[M]; int tot,S,T,f[M],dis[M],dp[55][55],pre[55][55]; struct edge { int v,c,next; }e[2*M]; void add(int u,int v,int c) { e[++tot]=edge{v,c,f[u]},f[u]=tot; e[++tot]=edge{u,0,f[v]},f[v]=tot; } int bfs() { for(int i=S;i<=T;i++) dis[i]=0; queue<int> q; q.push(S);dis[S]=1; while(!q.empty()) { int u=q.front();q.pop(); if(u==T) return 1; for(int i=f[u];i;i=e[i].next) { int v=e[i].v; if(e[i].c>0 && !dis[v]) { dis[v]=dis[u]+1; q.push(v); } } } return 0; } int dfs(int u,int ept) { if(u==T) return ept; int flow=0,tmp=0; for(int i=f[u];i;i=e[i].next) { int v=e[i].v; if(e[i].c>0 && dis[v]==dis[u]+1) { tmp=dfs(v,min(e[i].c,ept)); if(!tmp) continue; ept-=tmp; e[i].c-=tmp; e[i^1].c+=tmp; flow+=tmp; if(!ept) break; } } return flow; } int get() { S=0;T=2*n+1;tot=1; for(int i=S;i<=T;i++) f[i]=0; for(int i=1;i<=m;i++) { int u=a[i],v=b[i]; add(u+n,v,1);//x is in / x+n is out; } for(int i=1;i<=n;i++) { if(!del[i+n]) add(S,i+n,1); if(!del[i]) add(i,T,1); } int res=0; while(bfs()) res+=dfs(S,inf); return res; } void print(int x,int y) { if(!x) return ; print(x-1,pre[x][y]); for(int i=pre[x][y]+1;i<=y;i++) { if(d[i]>n) printf( %lld ,d[i]-n); else printf( %lld ,-d[i]); } printf( 0 ); } signed main() { n=read();m=read();k=read(); for(int i=1;i<=m;i++) a[i]=read(),b[i]=read(); mx=get(); for(int i=1;i<=mx;i++) for(int j=1;j<=2*n;j++) if(!del[j]) { del[j]=1; if(get()==mx-i)//we can delete j to reduce the maxmatch { d[++t]=j; break; } del[j]=0; } memset(dp,-0x3f,sizeof dp); dp[0][0]=0; for(int i=1;i<=k;i++) { int x=read(),y=read(); for(int j=0;j<=t;j++) { if(i-j>=n-mx) continue;//illegal for(int k=0;k<=j;k++)//we choose k now if(dp[i][j]<dp[i-1][j-k]+max(0ll,x-k*y)) { dp[i][j]=dp[i-1][j-k]+max(0ll,x-k*y); pre[i][j]=j-k; } } } int p=0; for(int i=0;i<=t;i++) if(dp[k][i]>dp[k][p]) p=i; printf( %lld n ,k+p); print(k,p); }
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#include <bits/stdc++.h> using namespace std; char s[200005]; int alph[26]; int main() { scanf( %s , &s); for (int i = 0; s[i]; i++) alph[s[i] - a ]++; for (int i = 0; i < 26; i++) for (int j = 26 - 1; j > i; j--) if (alph[i] & 1) if (alph[j] & 1) alph[i]++, alph[j]--; int odd = -1; for (int i = 0; i < 26; i++) if (alph[i] & 1) odd = i; for (int i = 0; i < 26; i++) for (int j = 1; j <= alph[i] / 2; j++) printf( %c , i + a ); if (odd != -1) printf( %c , odd + a ); for (int i = 26 - 1; i >= 0; i--) for (int j = 1; j <= alph[i] / 2; j++) printf( %c , i + a ); return 0; }
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#include <bits/stdc++.h> using namespace std; priority_queue<int> lott; int main() { long long int xm, find = 0; cin >> xm; lott.push(100); lott.push(20); lott.push(10); lott.push(5); lott.push(1); while (xm) { while (lott.top() <= xm) { find++; xm -= lott.top(); } lott.pop(); } cout << find << endl; return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 01:40:38 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/system_vga_feature_transform_0_0_stub.v
// Design : system_vga_feature_transform_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_feature_transform,Vivado 2016.4" *)
module system_vga_feature_transform_0_0(clk, clk_x2, rst, active, vsync, x_addr_0, y_addr_0,
hessian_0, x_addr_1, y_addr_1, hessian_1, rot_m00, rot_m01, rot_m10, rot_m11, t_x, t_y, state)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,rst,active,vsync,x_addr_0[9:0],y_addr_0[9:0],hessian_0[31:0],x_addr_1[9:0],y_addr_1[9:0],hessian_1[31:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],state[1:0]" */;
input clk;
input clk_x2;
input rst;
input active;
input vsync;
input [9:0]x_addr_0;
input [9:0]y_addr_0;
input [31:0]hessian_0;
input [9:0]x_addr_1;
input [9:0]y_addr_1;
input [31:0]hessian_1;
output [15:0]rot_m00;
output [15:0]rot_m01;
output [15:0]rot_m10;
output [15:0]rot_m11;
output [9:0]t_x;
output [9:0]t_y;
output [1:0]state;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x[n], y[n]; for (int i = 0; i < n; i++) cin >> x[i]; for (int i = 0; i < n; i++) cin >> y[i]; int de = 0, in = 0; for (int i = 0; i < n; i++) { if (x[i] > y[i]) de = de + x[i] - y[i]; if (y[i] > x[i]) in = in + y[i] - x[i]; } if (de >= in) cout << Yes ; else cout << No ; return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZE = 8;
integer cnt = 0;
logic [SIZE-1:0] vld_for;
logic vld_if = 1'b0;
logic vld_else = 1'b0;
genvar i;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if (cnt==SIZE) begin : if_cnt_finish
$write("*-* All Finished *-*\n");
$finish;
end : if_cnt_finish_bad
generate
for (i=0; i<SIZE; i=i+1) begin : generate_for
always @ (posedge clk)
if (cnt == i) vld_for[i] <= 1'b1;
end : generate_for_bad
endgenerate
generate
if (SIZE>0) begin : generate_if_if
always @ (posedge clk)
vld_if <= 1'b1;
end : generate_if_if_bad
else begin : generate_if_else
always @ (posedge clk)
vld_else <= 1'b1;
end : generate_if_else_bad
endgenerate
endmodule : t_bad
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#include <bits/stdc++.h> using namespace std; inline int ni() { int a; scanf( %d , &a); return a; } const int max_n = 5000; char s1[max_n + 1], s2[max_n + 1], res[max_n + 1]; int digits[26], minuses[26]; bool check(int from, int code, int n, int m) { bool ok = true, founded = false; digits[code]--; memset(minuses, 0, sizeof(minuses)); for (int i = from; i < m; i++) { int next = -1, need = s2[i] - a ; for (int j = 25; j >= 0; j--) { if (j >= need && digits[j] > 0) { next = j; break; } } if (next == -1) { ok = false; break; } else if (next > need) { founded = true; break; } else { digits[next]--; minuses[next]++; } } for (int i = 0; i < int(26); i++) digits[i] += minuses[i]; digits[code]++; if (n <= m && !founded) ok = false; return ok; } int main() { scanf( %s , s1); scanf( %s , s2); int n = strlen(s1), m = strlen(s2); bool found = true, before = false; for (int i = 0; i < int(n); i++) digits[s1[i] - a ]++; for (int i = 0; i < int(n); i++) { if (i >= m || before) { int code = -1; for (int j = 0; j < int(26); j++) { if (digits[j] > 0) { code = j; break; } } res[i] = a + code; digits[code]--; } else { int same = s2[i] - a , next = -1; for (int j = 0; j < int(26); j++) { if (j > same && digits[j] > 0) { next = j; break; } } if (digits[same] > 0 && check(i + 1, same, n, m)) { digits[same]--; res[i] = a + same; } else if (next != -1) { digits[next]--; res[i] = a + next; before = true; } else { found = false; break; } } } if (found) { res[n] = 0 ; printf( %s n , res); } else { printf( -1 n ); } return 0; }
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// $Id: channel.v 1853 2010-03-24 03:06:21Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// network channel model
module channel
(clk, reset, xmit_cal, xmit_data, recv_cal, recv_data);
// width of the channel (in bits)
parameter channel_width = 16;
// bit error rate (errors per 10000 bits)
parameter error_rate = 1;
// initial seed value for random number generation
parameter initial_seed = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// calibration enable for transmit unit
input xmit_cal;
// data to transmit over the channel
input [0:channel_width-1] xmit_data;
// calibration enable for receive unit
input recv_cal;
// data received from the channel
output [0:channel_width-1] recv_data;
wire [0:channel_width-1] recv_data;
wire [0:channel_width-1] xmit_data_s, xmit_data_q;
assign xmit_data_s = xmit_data;
c_dff
#(.width(channel_width),
.reset_type(reset_type))
xmit_dataq
(.clk(clk),
.reset(reset),
.d(xmit_data_s),
.q(xmit_data_q));
wire [0:channel_width-1] channel_data_in;
assign channel_data_in = xmit_cal ? {channel_width{1'bx}} : xmit_data_q;
integer seed = initial_seed;
integer i;
reg [0:channel_width-1] channel_errors;
always @(posedge clk)
for(i = 0; i < channel_width; i = i + 1)
channel_errors[i]
<= ($dist_uniform(seed, 0, 9999) < error_rate) ? 1'b1 : 1'b0;
wire [0:channel_width-1] channel_data_out;
assign channel_data_out = channel_data_in ^ channel_errors;
wire [0:channel_width-1] recv_data_s, recv_data_q;
assign recv_data_s = channel_data_out;
c_dff
#(.width(channel_width),
.reset_type(reset_type))
recv_dataq
(.clk(clk),
.reset(reset),
.d(recv_data_s),
.q(recv_data_q));
assign recv_data = recv_cal ? {channel_width{1'bx}} : recv_data_q;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 300 * 1000 + 13; int n; long long a[N], b[N]; void solve() { scanf( %d , &n); for (int i = 0; i < int(n); ++i) scanf( %lld%lld , &a[i], &b[i]); long long ans = 0, mn = 1e18; for (int i = 0; i < int(n); ++i) { int ni = (i + 1) % n; long long val = min(a[ni], b[i]); ans += a[ni] - val; mn = min(mn, val); } ans += mn; printf( %lld n , ans); } int main() { int T; scanf( %d , &T); for (int i = 0; i < int(T); ++i) solve(); }
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module ula_testbench();
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// contador de testes a serem feitos
integer testes;
// declaracao das input e output da ula
reg signed [OPCODE_WIDTH-1:0] opcode;
reg signed [DATA_WIDTH-1:0] data1, data2;
wire signed [DATA_WIDTH-1:0] out;
wire [4:0] rflags;
// instancia da ula
ula ula0(.opcode(opcode), .data1(data1), .data2(data2), .out(out), .rflags(rflags));
// inicializando testes em 0
initial begin
testes = 0;
end
// Gerando testes
always begin
#5;
testes <= testes+1;
end
// print dos resultados
task print_results;
begin
$write(" Teste # %2d => Opcode: %b | RFlags = %b | ", testes, opcode, rflags);
case(opcode)
ADD: begin
$write("%6d + %6d = %6d", data1, data2, out);
end
SUB: begin
$write("%6d - %6d = %6d", data1, data2, out);
end
MUL: begin
$write("%6d * %6d = %6d", data1, data2, out);
end
DIV: begin
$write("%6d / %6d = %6d", data1, data2, out);
end
AND: begin
$write("%6d & %6d = %6d", data1, data2, out);
end
OR: begin
$write("%6d | %6d = %6d", data1, data2, out);
end
NOT: begin
$write("! %6d = %6d", data1, out);
end
CMP: begin
$write("%6d cmp %6d = %6d", data1, data2, out);
end
default: begin
$write("%6d ?? %6d = %6d", data1, data2, out);
end
endcase
$write(" | RFlags (descricao) = ");
if (rflags[4] == 1) begin
$write("OVERFLOW + ");
end
if (rflags[3] == 1) begin
$write("ABOVE + ");
end
if (rflags[2] == 1) begin
$write("EQUAL + ");
end
if (rflags[1] == 1) begin
$write("BELOW + ");
end
if (rflags[0] == 1) begin
$write("ERROR");
end
$display(" ");
end
endtask
// mostre os resultados dos testes aqui
always @(out,rflags) begin
print_results();
end
// realize os testes aqui
always @(testes) begin
case(testes)
1: begin
data1 = 5;
data2 = 10;
opcode = ADD;
end
2: begin
data1 = 5;
data2 = -5;
opcode = ADD;
end
3: begin
data1 = 5;
data2 = -8;
opcode = ADD;
end
4: begin
data1 = 32767;
data2 = 1;
opcode = ADD;
end
5: begin
data1 = 5;
data2 = 3;
opcode = SUB;
end
6: begin
data1 = 5;
data2 = 9;
opcode = SUB;
end
7: begin
data1 = 5;
data2 = 5;
opcode = SUB;
end
8: begin
data1 = 0;
data2 = 32768;
opcode = SUB;
end
9: begin
data1 = -1;
data2 = 32768;
opcode = SUB;
end
10: begin
data1 = 0;
data2 = 5;
opcode = MUL;
end
11: begin
data1 = 32767;
data2 = 2;
opcode = MUL;
end
12: begin
data1 = 5;
data2 = 2;
opcode = MUL;
end
13: begin
data1 = -5;
data2 = -2;
opcode = MUL;
end
14: begin
data1 = -5;
data2 = 2;
opcode = MUL;
end
15: begin
data1 = -5;
data2 = 2;
opcode = DIV;
end
16: begin
data1 = 5;
data2 = -3;
opcode = DIV;
end
17: begin
data1 = -10;
data2 = -2;
opcode = DIV;
end
18: begin
data1 = 5;
data2 = 5;
opcode = DIV;
end
19: begin
data1 = 0;
data2 = 5;
opcode = DIV;
end
20: begin
data1 = 1;
data2 = 5;
opcode = DIV;
end
21: begin
data1 = 6;
data2 = 0;
opcode = DIV;
end
22: begin
data1 = 5;
data2 = 7;
opcode = AND;
end
23: begin
data1 = 5;
data2 = 7;
opcode = OR;
end
24: begin
data1 = 5;
data2 = 7;
opcode = NOT;
end
25: begin
data1 = 0;
data2 = 8;
opcode = NOT;
end
26: begin
data1 = -5;
data2 = 8;
opcode = CMP;
end
27: begin
data1 = 5;
data2 = -8;
opcode = CMP;
end
28: begin
data1 = 5;
data2 = 8;
opcode = CMP;
end
29: begin
data1 = -32768;
data2 = -32768;
opcode = CMP;
end
30: begin
data1 = 10;
data2 = 6;
opcode = CMP;
end
31: begin
data1 = 32767;
data2 = -1;
opcode = CMP;
end
32: begin
data1 = -32768;
data2 = 32767;
opcode = CMP;
end
33: begin
data1 = 1;
data2 = -32768;
opcode = CMP;
end
34: begin
data1 = 32767;
data2 = 32767;
opcode = CMP;
end
default: begin
// nao faca nada de proposito
end
endcase
end
endmodule
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#include<bits/stdc++.h> using namespace std; typedef long long ll; const int MAXN=1e9+1; const ll mod=1e9+7; int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n,m,k; cin>>n>>m>>k; int hori[n][m-1]; for(int i=0;i<n;i++){ for(int j=0;j<m-1;j++){ cin>>hori[i][j]; } } int verti[n-1][m]; for(int i=0;i<n-1;i++){ for(int j=0;j<m;j++){ cin>>verti[i][j]; } } if(k%2!=0){ for(int i=0;i<n;i++){ for(int j=0;j<m;j++)cout<< -1 ; cout<<endl; } return 0; } k/=2; int dp[n][m][k+1]; for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ for(int step=0;step<=k;step++)dp[i][j][step]=MAXN; } } for(int i=0;i<n;i++){ for(int j=0;j<m;j++)dp[i][j][0]=0; } for (int step = 0; step < k; step++) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (i > 0) dp[i - 1][j][step + 1] = min(dp[i - 1][j][step + 1], dp[i][j][step] + verti[i-1][j]); if (i < n - 1) dp[i + 1][j][step + 1] = min(dp[i + 1][j][step + 1], dp[i][j][step] + verti[i][j]); if (j > 0) dp[i][j - 1][step + 1] = min(dp[i][j - 1][step + 1], dp[i][j][step] + hori[i][j-1]); if (j < m - 1) dp[i][j + 1][step + 1] = min(dp[i][j + 1][step + 1], dp[i][j][step] + hori[i][j]); } } } for(int i=0;i<n;i++){ for(int j=0;j<m;j++){ cout<<(2*dp[i][j][k])<< ; } cout<<endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, l; int cnt[N]; long long sum[N]; int main() { cin >> n >> l; for (int i = 1; i < n; i++) { cin >> cnt[i]; sum[i] = sum[i - 1] + cnt[i]; } long long ans = 2e18; for (int i = l; i < n; i++) { ans = min(ans, sum[i] - sum[i - l]); } cout << ans << endl; return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h458c2de282e30f8b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output wire [31:0] out;
reg [31:0] stage [3:0];
genvar g;
generate
for (g=0; g<4; g++) begin
always_comb begin
if (g==0) stage[g] = in;
else stage[g] = {stage[g-1][30:0],1'b1};
end
end
endgenerate
assign out = stage[3];
endmodule
|
`timescale 1ns/1ns
module uart_tx#(
parameter integer WIDTH = 12
)
(
input PCLK,
input RESET,
input [7:0] DATA_TX_I,
input [11:0] WORK_FR,
input START,
output TX_O,
output reg READY_TX
);
localparam [11:0] TX_IDLE = 12'b0000_0000_0000,
TX_START = 12'b0000_0000_0001,
TX_BIT_1 = 12'b0000_0000_0010,
TX_BIT_2 = 12'b0000_0000_0100,
TX_BIT_3 = 12'b0000_0000_1000,
TX_BIT_4 = 12'b0000_0001_0000,
TX_BIT_5 = 12'b0000_0010_0000,
TX_BIT_6 = 12'b0000_0100_0000,
TX_BIT_7 = 12'b0000_1000_0000,
TX_BIT_8 = 12'b0001_0000_0000,
TX_PARITY = 12'b0010_0000_0000,
TX_STOP = 12'b0100_0000_0000;
reg [11:0] state_tx;
reg [11:0] next_state_tx;
reg [WIDTH-1:0] DELAY_COUNTER;
assign TX_O = (state_tx == TX_START)?1'b0:
(state_tx == TX_BIT_1)?DATA_TX_I[0:0]:
(state_tx == TX_BIT_2)?DATA_TX_I[1:1]:
(state_tx == TX_BIT_3)?DATA_TX_I[2:2]:
(state_tx == TX_BIT_4)?DATA_TX_I[3:3]:
(state_tx == TX_BIT_5)?DATA_TX_I[4:4]:
(state_tx == TX_BIT_6)?DATA_TX_I[5:5]:
(state_tx == TX_BIT_7)?DATA_TX_I[6:6]:
(state_tx == TX_BIT_8)?DATA_TX_I[7:7]:
(state_tx == TX_PARITY)?DATA_TX_I[0:0]^DATA_TX_I[1:1]^DATA_TX_I[2:2]^DATA_TX_I[3:3]^DATA_TX_I[4:4]^DATA_TX_I[5:5]^DATA_TX_I[6:6]^DATA_TX_I[7:7]:
(state_tx == TX_STOP)?1'b1:1'b1;
always@(*)
begin
next_state_tx = state_tx;
case(state_tx)
TX_IDLE:
begin
if(START == 1'b0)
begin
next_state_tx = TX_IDLE;
end
else
begin
next_state_tx = TX_START;
end
end
TX_START:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_START;
end
else
begin
next_state_tx = TX_BIT_1;
end
end
TX_BIT_1:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_1;
end
else
begin
next_state_tx = TX_BIT_2;
end
end
TX_BIT_2:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_2;
end
else
begin
next_state_tx = TX_BIT_3;
end
end
TX_BIT_3:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_3;
end
else
begin
next_state_tx = TX_BIT_4;
end
end
TX_BIT_4:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_4;
end
else
begin
next_state_tx = TX_BIT_5;
end
end
TX_BIT_5:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_5;
end
else
begin
next_state_tx = TX_BIT_6;
end
end
TX_BIT_6:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_6;
end
else
begin
next_state_tx = TX_BIT_7;
end
end
TX_BIT_7:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_7;
end
else
begin
next_state_tx = TX_BIT_8;
end
end
TX_BIT_8:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_8;
end
else
begin
next_state_tx = TX_PARITY;
end
end
TX_PARITY:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_PARITY;
end
else
begin
next_state_tx = TX_STOP;
end
end
TX_STOP:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_STOP;
end
else
begin
next_state_tx = TX_IDLE;
end
end
default:
begin
next_state_tx = TX_IDLE;
end
endcase
end
always@(posedge PCLK)
begin
if(RESET)
begin
READY_TX <= 1'b1;
DELAY_COUNTER<= {WIDTH{1'b0}};
state_tx <= TX_IDLE;
end
else
begin
state_tx <= next_state_tx;
case(state_tx)
TX_IDLE:
begin
if(START == 1'b0)
begin
READY_TX<= 1'b1;
DELAY_COUNTER<= {WIDTH{1'b0}};
end
else
begin
READY_TX<= 1'b0;
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
end
TX_START:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_1:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_2:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_3:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_4:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_5:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_6:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_7:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_8:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER <= {WIDTH{1'b0}};
end
end
TX_PARITY:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER <= {WIDTH{1'b0}};
end
end
TX_STOP:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
default:
begin
DELAY_COUNTER<= {WIDTH{1'b1}};
end
endcase
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module loads data into the Audio and Video chips' control *
* registers after system reset. *
* *
******************************************************************************/
module altera_up_av_config_auto_init (
// Inputs
clk,
reset,
clear_error,
ack,
transfer_complete,
rom_data,
// Bidirectionals
// Outputs
data_out,
transfer_data,
rom_address,
auto_init_complete,
auto_init_error,
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter ROM_SIZE = 50;
parameter AW = 5; // Auto Initialize ROM's address width
parameter DW = 23; // Auto Initialize ROM's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input clear_error;
input ack;
input transfer_complete;
input [DW: 0] rom_data;
// Bidirectionals
// Outputs
output reg [DW: 0] data_out;
output reg transfer_data;
output reg [AW: 0] rom_address;
output reg auto_init_complete;
output reg auto_init_error;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire toggle_next_transfer;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
data_out <= 'h0;
else
data_out <= rom_data;
end
always @(posedge clk)
begin
if (reset)
transfer_data <= 1'b0;
else if (auto_init_complete | transfer_complete)
transfer_data <= 1'b0;
else
transfer_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
rom_address <= 'h0;
else if (toggle_next_transfer)
rom_address <= rom_address + 'h1;
end
always @(posedge clk)
begin
if (reset)
auto_init_complete <= 1'b0;
else if (toggle_next_transfer & (rom_address == (ROM_SIZE - 1)))
auto_init_complete <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
auto_init_error <= 1'b0;
else if (toggle_next_transfer & ack)
auto_init_error <= 1'b1;
else if (clear_error)
auto_init_error <= 1'b0;
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign toggle_next_transfer = transfer_data & transfer_complete;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_4_V
`define SKY130_FD_SC_HS__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfstp_4 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfstp_4 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, mux_out, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_FUNCTIONAL_PP_V
|
`include "define.h"
//Feb.25.2005 Verilog2001 Style
//Jan.20.2005 implict event list
//Jun.14.2004 Initial Version
//Jul.4.2004 sensibity list bug fix
//Jul.5.2004 less area version
//Apr.14.2005 Stratix 2 workaround Quartus 4.1/4.2
module substruct (input [31:0] a,b,
output [31:0] c);
assign c=a+~b+1;//NG Quartus 4.1/4.2 a-b
endmodule
module alu (input [31:0] a,b,
output reg [31:0] alu_out,
input [3:0] alu_func);
wire [31:0] c;
parameter [3:0] alu_nop =4'b0000,
alu_add =4'b0001,
alu_sub =4'b0010,
alu_less_than_unsigned =4'b0101, //Jul.5.2004
alu_less_than_signed =4'b0100, //Jul.5.2004
alu_OR =4'b0011,
alu_AND =4'b0110,
alu_XOR =4'b0111,
alu_NOR =4'b1000;
reg [32:0] sum;
always @* begin //
case (alu_func)
alu_nop : alu_out=32'h0000;
alu_add : alu_out=a+b;
alu_sub : alu_out=c;//Apr.14.2005 NG a-b Quartus 4.1/4.2
alu_OR : alu_out=a | b;
alu_AND : alu_out=a & b;
alu_XOR : alu_out=a ^ b;
alu_NOR : alu_out=~(a | b);
alu_less_than_unsigned : alu_out=a < b;//Jun.29.2004
alu_less_than_signed: begin
sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;//Apr.14.2005 1'b1;//Important 33'h0_0000_000 :a-b $signed(a) > $signed(b);
alu_out={31'h0000_0000,sum[32]};//{31'h0000_0000,sum[32]};
end
default : alu_out=32'h0000_0000;
endcase
end
substruct sub(a,b,c);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_4_V
`define SKY130_FD_SC_HS__A311OI_4_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311oi_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 18:17:58 09/26/2015
// Design Name: Multiplication controller
// Module Name: Controller
//////////////////////////////////////////////////////////////////////////////////
module Controller(Clock, Reset, Start, Shift1, Shift0, Clear);
input Clock, Reset, Start;
output reg [2:0] Shift0;
output reg [2:0] Shift1;
output reg Clear;
parameter State0 = 4'b0000;
parameter State1 = 4'b0001;
parameter State2 = 4'b0010;
parameter State3 = 4'b0011;
parameter State4 = 4'b0100;
parameter State5 = 4'b0101;
parameter State6 = 4'b0110;
parameter State7 = 4'b0111;
parameter State8 = 4'b1000;
parameter State9 = 4'b1001;
parameter State10 = 4'b1010;
parameter State11 = 4'b1011;
reg [3:0] CurrentState;
reg [3:0] NextState;
always @ CurrentState
case (CurrentState)
State0: {Clear, Shift1, Shift0} <= 7'b1000000; // Do nothing
State1: {Clear, Shift1, Shift0} <= 7'b0000000; // Clear the registers
State2: {Clear, Shift1, Shift0} <= 7'b1101101; // Initialize registers
State3: {Clear, Shift1, Shift0} <= 7'b1010010; // Add and put in top half or product
State4: {Clear, Shift1, Shift0} <= 7'b1111000; // Shift product and multiplier
State5: {Clear, Shift1, Shift0} <= 7'b1010010; // Now we just repeat the last two
State6: {Clear, Shift1, Shift0} <= 7'b1111000;
State7: {Clear, Shift1, Shift0} <= 7'b1010010;
State8: {Clear, Shift1, Shift0} <= 7'b1111000;
State9: {Clear, Shift1, Shift0} <= 7'b1010010;
State10: {Clear, Shift1, Shift0} <= 7'b1111000;
State11: {Clear, Shift1, Shift0} <= 7'b1000000; // We're done
endcase
always @ (posedge Clock or negedge Reset)
if (Reset == 0) begin CurrentState <= State0; NextState <= State0; end
else CurrentState <= NextState;
always @ (CurrentState or Start or NextState)
case (CurrentState)
State0: if (Start == 1) NextState <= State1;
State1: NextState <= State2;
State2: NextState <= State3;
State3: NextState <= State4;
State4: NextState <= State5;
State5: NextState <= State6;
State6: NextState <= State7;
State7: NextState <= State8;
State8: NextState <= State9;
State9: NextState <= State10;
State10: NextState <= State11;
endcase
endmodule
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#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int INF = 1e9 + 7; const int N = 1010; const double pi = 3.1415926; int n; int t[110], d[110], p[110], pre[2010], now[2010], sum[2010], good[2010]; int dp[2010]; vector<int> v[2010]; struct node { int t; int d; int p; int id; } e[110]; bool cmp(node a, node b) { return a.d < b.d; } int main() { while (~scanf( %d , &n)) { for (int i = 0; i < 2010; i++) v[i].clear(); for (int i = 0; i < n; i++) { scanf( %d%d%d , &e[i].t, &e[i].d, &e[i].p); e[i].id = i + 1; } sort(e, e + n, cmp); memset(dp, 0, sizeof(dp)); ; memset(sum, 0, sizeof(sum)); ; memset(now, 0, sizeof(now)); ; memset(pre, 0, sizeof(pre)); ; int ans = 0, idx = 0, s1 = 0, s2 = 0; for (int i = 0; i < n; i++) { for (int j = e[i].d; j > e[i].t; j--) { s1 = 0; if (dp[j - e[i].t] + e[i].p > dp[j]) { dp[j] = dp[j - e[i].t] + e[i].p; sum[j] = sum[j - e[i].t] + 1; v[j] = v[j - e[i].t]; v[j].push_back(e[i].id); } if (dp[j] > ans) { idx = j; ans = dp[j]; } } } printf( %d n , ans); printf( %d n , sum[idx]); for (int i = 0; i < v[idx].size(); i++) { printf( %d , v[idx][i]); } printf( n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, mz; char tmp; bool t[51][51]; bool m[51][51]; int mel, skm; bool atr; bool state; void apstaig(int x, int y) { int i, j, z; for (i = x; i <= mz; i++) { if (t[i][y] == false) break; else { m[i][y] = !state; skm++; j = y - 1; while (j > 0) { if (t[i][j] == false) break; else { if (m[i][j] == state) { m[i][j] = !state; skm++; } } j--; } j = y + 1; while (j <= n) { if (t[i][j] == false) break; else { if (m[i][j] == state) { m[i][j] = !state; skm++; } } j++; } } } for (i = x - 1; i > 0; i--) { if (t[i][y] == false) break; else { m[i][y] = !state; skm++; j = y - 1; while (j > 0) { if (t[i][j] == false) break; else { if (m[i][j] == state) { m[i][j] = !state; skm++; } } j--; } j = y + 1; while (j <= n) { if (t[i][j] == false) break; else { if (m[i][j] == state) { m[i][j] = !state; skm++; } } j++; } } } for (i = y - 1; i > 0; i--) { if (t[x][i] == false) break; else { if (m[x][i] == state) { m[j][i] = !state; skm++; } j = x - 1; while (j > 0) { if (t[j][i] == false) break; else { if (m[j][i] == state) { m[j][i] = !state; skm++; } } j--; } j = x + 1; while (j <= mz) { if (t[j][i] == false) break; else { if (m[j][i] == state) { m[j][i] = !state; skm++; } } j++; } } } for (i = y + 1; i <= n; i++) { if (t[x][i] == false) break; else { if (m[x][i] == state) { m[j][i] = !state; skm++; } j = x - 1; while (j > 0) { if (t[j][i] == false) break; else { if (m[j][i] == state) { m[j][i] = !state; skm++; } } j--; } j = x + 1; while (j <= mz) { if (t[j][i] == false) break; else { if (m[j][i] == state) { m[j][i] = !state; skm++; } } j++; } } } } int main() { int i, j; cin >> n >> mz; mel = 0; for (i = 1; i <= n; i++) for (j = 1; j <= mz; j++) { cin >> tmp; if (tmp == B ) { t[j][i] = true; mel++; m[j][i] = false; } else t[j][i] = false; } atr = true; state = false; for (i = 1; i <= n; i++) for (j = 1; j <= mz; j++) { if (t[j][i] == true) { skm = 0; apstaig(j, i); if (skm != mel) { atr = false; break; } state = !state; } } if (atr) cout << YES ; else cout << NO ; }
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#include <bits/stdc++.h> using namespace std; int n, m, s, k, a[2010], b[2010], nxt[2010], sum[2010], dp[2010][2010]; inline int read() { int s = 0, w = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) w = -1; for (; isdigit(c); c = getchar()) s = (s << 1) + (s << 3) + (c ^ 48); return s * w; } bool check(int mid) { for (int i = 1; i <= n; ++i) sum[i] = sum[i - 1] + (a[i] <= b[mid]); memset(dp, 0, sizeof(dp)); for (int i = 1; i <= s; ++i) { for (int j = 1; j <= n; ++j) dp[i][j] = max(dp[i][j], dp[i - 1][j]); for (int j = 1; j <= n; ++j) if (nxt[j]) dp[i][nxt[j]] = max(dp[i][nxt[j]], dp[i - 1][j - 1] + sum[nxt[j]] - sum[j - 1]); for (int j = 1; j <= n; ++j) dp[i][j] = max(dp[i][j - 1], dp[i][j]); } return dp[s][n] >= k; } int main() { n = read(), m = read(), s = read(), k = read(); for (int i = 1; i <= n; ++i) a[i] = read(), b[i] = a[i]; sort(b + 1, b + 1 + n); for (int i = 1; i <= m; ++i) { int l = read(), r = read(); for (int j = l; j <= r; ++j) nxt[j] = max(nxt[j], r); } int l = 1, r = n, ans = -1; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) ans = b[mid], r = mid - 1; else l = mid + 1; } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; void _dbg(string) { cout << endl; } template <class H, class... T> void _dbg(string s, H h, T... t) { int l = s.find( , ); cout << s.substr(0, l) << = << h << , ; _dbg(s.substr(l + 1), t...); } template <class T, class U> ostream &operator<<(ostream &o, const pair<T, U> &p) { o << ( << p.first << , << p.second << ) ; return o; } template <class T> ostream &operator<<(ostream &o, const vector<T> &v) { o << [ ; for (T t : v) { o << t << , ; } o << ] ; return o; } class UnionFind { public: vector<int> par, rank; UnionFind(int sz) : par(sz, -1), rank(sz, 0) {} int find(int x) { if (par[x] < 0) return x; else return par[x] = find(par[x]); } void unite(int x, int y) { x = find(x); y = find(y); if (x == y) return; if (rank[x] < rank[y]) { par[y] += par[x]; par[x] = y; } else { par[x] += par[y]; par[y] = x; if (rank[x] == rank[y]) rank[x]++; } } inline bool same(int x, int y) { return find(x) == find(y); } inline int size(int x) { return -par[find(x)]; } }; int main() { int n; cin >> n; vector<int> v(n); for (int i = (int)(0); i < (int)(n); i++) scanf( %d , &v[i]); for (int i = (int)(0); i < (int)(n); i++) v[i]--; UnionFind uf(n + 1); vector<bool> appeared(n + 1, false); appeared[n] = true; cout << 1 ; for (int i = (int)(0); i < (int)(n); i++) { if (v[i] > 0 && appeared[v[i] - 1]) uf.unite(v[i] - 1, v[i]); if (appeared[v[i] + 1]) uf.unite(v[i], v[i] + 1); appeared[v[i]] = true; int sz = uf.size(n) - 1; printf( %d%c , (i + 2) - sz, n [i == n - 1]); } return 0; }
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#include <bits/stdc++.h> using namespace std; struct ufds { int n; vector<int> p, s; ufds(int n = 0) : n(n), p(n), s(n, 1) { for (int i = 0; i < n; i++) p[i] = i; } int findSet(int i) { return p[i] == i ? i : (p[i] = findSet(p[i])); } bool inSameSet(int i, int j) { return findSet(i) == findSet(j); } int getSizeOfSet(int i) { return s[findSet(i)]; } void unionSet(int i, int j) { i = findSet(i); j = findSet(j); if (i != j) { if (s[i] < s[j]) swap(i, j); s[i] += s[j]; p[j] = i; } } }; struct maximum_matching { int n, mm = 0, t = 0; vector<int> m, l, p, o, v; vector<vector<int>> &e; queue<int> q; maximum_matching(vector<vector<int>> &e) : n(e.size()), m(n, -1), l(n), p(n), o(n), v(n), e(e) { for (int i = 0; i < n; i++) if (m[i] == -1) mm += bfs(i); } int lca(int i, int j) { for (t++;; swap(i, j)) if (i != -1) { if (v[i] == t) return i; v[i] = t; i = m[i] == -1 ? -1 : o[p[m[i]]]; } } void blossom(int i, int j, int a) { while (o[i] != a) { p[i] = j; j = m[i]; if (l[j] == 1) l[j] = 0, q.push(j); o[i] = o[j] = a; i = p[j]; } } bool bfs(int s) { for (int i = 0; i < n; i++) l[i] = -1, o[i] = i; while (!q.empty()) q.pop(); l[s] = 0; q.push(s); while (!q.empty()) { int i = q.front(); q.pop(); for (int j : e[i]) if (l[j] == -1) { l[j] = 1; p[j] = i; if (m[j] == -1) { while (j != -1) m[j] = p[j], swap(j, m[m[j]]); return true; } l[m[j]] = 0; q.push(m[j]); } else if (l[j] == 0 && o[i] != o[j]) { int a = lca(o[i], o[j]); blossom(i, j, a); blossom(j, i, a); } } return false; } }; int n, a[300100], r[300100], value, m, rng[300100][3], c = 1, comp[700]; bool u[300100], rngu[300100]; vector<int> er[2], te[700]; void fill() { int nv = 1; for (int i = 0; i < n - 1; i++) if (r[i] == 0 && r[i + 1] == 0) { while (u[nv]) nv++; r[i] = r[i + 1] = nv, value++, u[nv] = true; } for (int i = 0; i < n; i++) if (r[i] == 0) r[i] = 1; } void fillOE(int k, int av) { int i = rng[k][0], j = rng[k][1]; if (av == a[i - 1]) r[i] = av; else r[j] = av; value++, u[av] = true; } void fillE(int k) { int i = rng[k][0], j = rng[k][1]; r[i] = r[i - 1], r[j] = r[j + 1]; u[a[i - 1]] = u[a[j + 1]] = true; value++; } void dfsTree(int i, int p = -1) { for (int k : te[i]) { int j = i ^ rng[k][2]; if (j != p) { fillOE(k, j); dfsTree(j, i); } } } void dfsComp(int i) { comp[i] = c; for (int k : te[i]) { int j = i ^ rng[k][2]; if (comp[j] == 0) dfsComp(j); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(12); cin >> n; for (int i = 0; i < n; i++) cin >> a[i], r[i] = a[i]; int s = 0; while (s < n && a[s] == 0) s++; if (s < n && s % 2 == 1) a[s - 1] = r[s - 1] = a[s], s--; int e = n - 1; while (e >= 0 && a[e] == 0) e--; if (e >= 0 && (n - e - 1) % 2 == 1) a[e + 1] = r[e + 1] = a[e], e++; if (s < e) { for (int i = s + 1; i < e; i++) if (a[i] == 0) { int j = i; while (a[j + 1] == 0) j++; rng[m][0] = i, rng[m][1] = j; rng[m][2] = a[i - 1] ^ a[j + 1]; er[(j - i + 1) & 1].push_back(m); m++; i = j; } ufds uf(700); for (int k : er[1]) { int i = rng[k][0], j = rng[k][1]; if (!uf.inSameSet(a[i - 1], a[j + 1])) { uf.unionSet(a[i - 1], a[j + 1]); te[a[i - 1]].push_back(k); te[a[j + 1]].push_back(k); rngu[k] = true; } } for (int k : er[1]) { int i = rng[k][0], j = rng[k][1]; if (!rngu[k] && uf.inSameSet(a[i - 1], a[j + 1]) && !u[a[i - 1]]) { fillOE(k, a[i - 1]); dfsTree(a[i - 1]); } } for (int i = s; i < e; i++) if (a[i] > 0 && a[i] == a[i + 1] && !u[a[i]]) value++, u[a[i]] = true, dfsTree(a[i]); for (int i = 1; i <= min(n, 600); i++) if (!u[i] && comp[i] == 0) dfsComp(i), c++; vector<vector<int>> e(c); for (int k : er[0]) { int i = rng[k][0], j = rng[k][1]; if (!u[a[i - 1]] && !u[a[j + 1]] && comp[a[i - 1]] != comp[a[j + 1]]) { e[comp[a[i - 1]]].push_back(comp[a[j + 1]]), e[comp[a[j + 1]]].push_back(comp[a[i - 1]]); } } maximum_matching mm(e); for (int k : er[0]) { int i = rng[k][0], j = rng[k][1]; if (mm.m[comp[a[i - 1]]] != -1 && mm.m[comp[a[i - 1]]] == comp[a[j + 1]]) { fillE(k); dfsTree(a[i - 1]); dfsTree(a[j + 1]); mm.m[comp[a[i - 1]]] = -1, mm.m[comp[a[j + 1]]] = -1; } } for (int i = 1; i <= min(n, 600); i++) if (!u[i]) dfsTree(i); } fill(); for (int i = 0; i < n; i++) cout << r[i] << (i < n - 1 ? : n ); }
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#include <bits/stdc++.h> using namespace std; char s[302][302]; int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); int n, p; cin >> n >> p; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); vector<int> ans; for (int i = 1; i < 2003; i++) { int cnt = 1, x = i; for (int j = 0; cnt > 0 && j < n; j++) { int y = upper_bound(a, a + n, x) - a; cnt *= (y - j); cnt %= p; x++; } if (cnt > 0) ans.push_back(i); } cout << ans.size() << n ; for (int i = 0; i < (int)ans.size(); i++) { cout << (i == 0 ? : ) << ans[i]; } cout << n ; return 0; }
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#include <bits/stdc++.h> #include <vector> #include <set> #include <string> #include <map> #include <cmath> #include <algorithm> typedef long long int ll; #define f first #define s second #define vi vector<int> #define ld long double #define pb push_back #define mp make_pair #define pii pair<int, int> #define floop(count,a, n) for(int count{a}; count < n; ++count) #define tr(c, it) for(auto it{c.begin()}; it != c.end(); ++it) #define lb lower_bound #define ub upper_bound #define bs binary_search #define newl n using namespace std; const int MOD = 1e9+7; const ld PI = acos(-1); const ld EPS = 1e-9; const ll INF = 1e18; int main(){ ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int cas;cin>>cas; while(cas--){ int n; cin>>n; int a = sqrt(n); if(a*a == n) cout<<a<< n ; else cout<<a + 1<< n ; } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int>> P; bool used[111]; int pos; bool ok(int T) { if (T == pos) return true; used[T] = true; for (int i = 0; i < P.size(); i++) { if (used[i] == false) { if (P[T].first > P[i].first && P[T].first < P[i].second || P[T].second > P[i].first && P[T].second < P[i].second) { used[i] = true; if (ok(i)) return true; } } } return false; } string ans(int l, int r) { pos = r; for (int i = 0; i < 111; i++) used[i] = false; if (ok(l)) return YES ; return NO ; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int type; cin >> type; if (type == 1) { int a, b; cin >> a >> b; P.push_back(make_pair(a, b)); } else { int l, r; cin >> l >> r; l--; r--; cout << ans(l, r) << endl; } } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_TB_V
`define SKY130_FD_SC_HDLL__NOR4BB_TB_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_TB_V
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// datamaster.v
`timescale 1ns / 100ps
`define ADDR_PTR 0
`define ADDR_LEN 1
`define ADDR_CTRL 2
`define ADDR_STAT 2
module datamaster
(
input clk,
input reset,
// control port (avalon slave)
input [3:0]ctrl_address,
input ctrl_write,
input [31:0]ctrl_writedata,
input ctrl_read,
output reg [31:0]ctrl_readdata,
// data port (avalon master)
output [31:0]data_address,
output data_write,
output [15:0]data_writedata,
input data_waitrequest,
output [1:0]data_byteenable,
// interface
input write,
input [15:0]data,
output waitrq,
output ready
);
reg [30:1]pointer; // address pointer (read/write)
reg [30:1]length; // max/actual data size (read/write)
reg enable; // DMA enable
wire lastword;
wire next;
// set registers
always @(posedge clk or posedge reset)
begin
if (reset)
begin
pointer <= 0;
length <= 0;
enable <= 0;
end
else
begin
if (ctrl_write && ctrl_address == `ADDR_CTRL)
enable <= ctrl_writedata[0];
if (enable)
begin // count
if (next)
begin
pointer <= pointer + 1;
length <= length - 1;
end
end
else if (ctrl_write)
begin
case (ctrl_address)
`ADDR_PTR: pointer <= ctrl_writedata[30:1];
`ADDR_LEN: length <= ctrl_writedata[30:1];
endcase
end
end
end
assign lastword = length == 0;
assign waitrq = !enable || data_waitrequest || lastword;
assign ready = lastword;
assign next = data_write & !data_waitrequest;
assign data_address = { 1'b0, pointer, 1'b0 };
assign data_byteenable = 2'b11;
assign data_write = enable && !lastword && write;
assign data_writedata = data;
always @(*)
begin
if (ctrl_read)
case (ctrl_address)
`ADDR_PTR: ctrl_readdata = { 1'b0, pointer, 1'b0 };
`ADDR_LEN: ctrl_readdata = { 1'b0, length, 1'b0 };
default: ctrl_readdata = { 31'b0, ready };
endcase
else ctrl_readdata = 0;
end
endmodule
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#include <bits/stdc++.h> int main() { int n, y[27] = {}, i, c = 0; char x[100001]; scanf( %d %s , &n, x); for (i = 0; i < n; i++) if (!y[x[i] - 97]) { y[x[i] - 97]++; c++; } if (n <= 26) printf( %d , n - c); else printf( -1 ); }
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#include bits/stdc++.h using namespace std; using ll = long long; using pii = pair<int,int>; vector<tuple<int,int,int>> edges; void add(int x, int y, int z) { edges.push_back({x,y,z}); } int solve(int l, int r) { if (l > 1) { int k = solve(1,r-l+1); add(k,k+1,l-1); return k+1; } if ((r&(-r)) == r) // r is a power of 2 { int k = __builtin_ctz(r); // Count Trailing Zeros add(1,2,1); for (int i = 3; i <= k+2; i++) { add(1,i,1); for (int j = 2; j < i; j++) add(j,i,1<<(j-2)); } return k+2; } int k =0; while(1<<(k+1) <= r-1) k++; solve(1,1<<k); add(1,k+3,1); for (int i = 0; i <= k; i++){ if ((r-1)>>i&1) add(i+2,k+3,1+((r-1)>>(i+1)<<(i+1))); } return k+3; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int l,r; cin >> l >> r; cout << YES n ; int n = solve(l,r); cout << n << << edges.size() << n ; for (auto [x,y,z] : edges) cout << x << << y << << z << n ; } // DAG // Good if all paths from 1 to n are between L and R // All possible distances should be represented, once each // // How many different distances can I have? n nodes an give 2^n-1 paths. Always // possible? // // Seems like we can do binary magic to solve //
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; long long int i, j, a, b, ans; for (i = 1; i <= t; i++) { cin >> a >> b; ans = 0; while ((a + b + ans * (ans + 1) / 2) % 2 != 0 || (a + b + ans * (ans + 1) / 2) < 2 * max(a, b)) { ans++; } cout << ans << endl; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg posedge_wr_clocks;
reg prev_wr_clocks;
reg [31:0] m_din;
reg [31:0] m_dout;
always @(negedge clk) begin
prev_wr_clocks = 0;
end
reg comb_pos_1;
reg comb_prev_1;
always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin
comb_pos_1 = (clk &~ prev_wr_clocks);
comb_prev_1 = comb_pos_1 | posedge_wr_clocks;
comb_pos_1 = 1'b1;
end
always @ (posedge clk) begin
posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS
prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS
if (posedge_wr_clocks) begin
//$write("[%0t] Wrclk\n", $time);
m_dout <= m_din;
end
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'hfeed;
end
if (cyc==2) begin
$write(" %x\n",comb_pos_1);
m_din <= 32'he11e;
end
if (cyc==3) begin
m_din <= 32'he22e;
$write(" %x\n",comb_pos_1);
if (m_dout!=32'hfeed) $stop;
end
if (cyc==4) begin
if (m_dout!=32'he11e) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_2_V
`define SKY130_FD_SC_LS__OR4_2_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_2_V
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <typename T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <typename T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <typename T> inline void println(T first) { print(first), putchar( n ); } template <typename T> inline void printsp(T first) { print(first), putchar( ); } template <class T, class T1> inline void print(T first, T1 second) { printsp(first), println(second); } template <class T, class T1, class T2> inline void print(T first, T1 second, T2 z) { printsp(first), printsp(second), println(z); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int main() { int a, b, p; long long first; gn(a, b, p); gn(first); long long ans = 0; long long M = (long long)p * (p - 1); int p1 = power(p - 1, p - 2, p); int p2 = p == 2 ? 1 : power(p, p - 3, p - 1); for (int r = 0; r < p - 1; r++) { int second = (long long)b * power(a, p - 1 - r, p) % p; long long rr = ((long long)r * p % M * p2 + (long long)second * (p - 1) % M * p1) % M; if (rr <= first) ans += (first - rr) / M + 1; } println(ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int n, a[maxn], deep[maxn], head[maxn], to[maxn * 2], nextt[maxn * 2], tot = 1, ans[maxn], anss; void add(int x, int y) { to[tot] = y; nextt[tot] = head[x]; head[x] = tot++; } void dfs(int u, int fa) { deep[u] = deep[fa] + 1; ans[deep[u]]--; for (int i = head[u]; i; i = nextt[i]) { int v = to[i]; if (v == fa) continue; dfs(v, u); } } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) { scanf( %d , &a[i]); add(a[i], i); } dfs(1, 0); for (int i = 1; i <= n; i++) if (ans[i] & 1) anss++; printf( %d n , anss); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, l, r, x, ans[300300], tree[4 * 300300]; void build(int node, int st, int en) { if (st == en) { tree[node] = 1; return; } build((node << 1), st, (st + en) / 2); build((node << 1) + 1, ((st + en) / 2) + 1, en); tree[node] = tree[(node << 1)] + tree[(node << 1) + 1]; } void update(int node, int st, int en, int left, int right, int val) { if (left > en || right < st) return; if (tree[node] == 0) return; if (st == en) { tree[node] = (st == x ? 1 : 0); ans[st] = val; return; } update((node << 1), st, (st + en) / 2, left, right, val); update((node << 1) + 1, ((st + en) / 2) + 1, en, left, right, val); tree[node] = tree[(node << 1)] + tree[(node << 1) + 1]; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; build(1, 1, n); while (m--) { cin >> l >> r >> x; update(1, 1, n, l, r, x); } ans[x] = 0; for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long a[n]; set<long long> s; for (long long i = 0; i < n; i++) { cin >> a[i]; s.insert(a[i]); } cout << s.size() << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long sum1 = 0, sum2 = 0; long temp; for (int i = 0; i < n; i++) { cin >> temp; sum1 += temp; } for (int i = 0; i < n - 1; i++) { cin >> temp; sum2 += temp; } cout << sum1 - sum2 << n ; for (int i = 0; i < n - 2; i++) { cin >> temp; sum2 -= temp; } cout << sum2; return (0); }
|
#include <bits/stdc++.h> using namespace std; const int M = 100010; long long MAX = 0; vector<int> maxs; vector<int> A[M]; map<pair<int, int>, int> mep; map<pair<int, int>, int> tmpmep; map<int, vector<pair<int, int> > > edges; int weight[M]; int parent[M]; int compsize[M]; int visited[M]; int dp[M]; int f(int first) { return parent[first] = parent[first] == first ? first : f(parent[first]); } void add(int a, int b) { int first = f(a), second = f(b); if (first != second) { parent[first] = second; compsize[second] += compsize[first]; } } int dfs1(int first) { visited[first] = true; int sum = 0; for (int second : A[first]) if (!visited[second]) sum += dfs1(second); return sum + compsize[first]; } int dfs2(int first, int p, int total) { visited[first] = true; int sum = compsize[first]; for (int second : A[first]) if (!visited[second]) sum += dfs2(second, first, total); long long trees = (long long)sum * (long long)(total - sum); if (trees > MAX) MAX = trees, maxs.clear(), maxs.push_back(tmpmep[make_pair(min(p, first), max(p, first))]); else if (trees == MAX) maxs.push_back(tmpmep[make_pair(min(p, first), max(p, first))]); return sum; } int main() { ios_base::sync_with_stdio(false); int i, j, k, n; scanf( %d , &n); for (int _ = 1; _ < n; _++) { scanf( %d%d%d , &i, &j, &k); mep[make_pair(min(i, j), max(i, j))] = _; edges[k].push_back(make_pair(min(i, j), max(i, j))); weight[_] = k; } for (i = 0; i <= n; i++) parent[i] = i, compsize[i] = 1; for (auto elm : edges) { set<int> nodes; tmpmep.clear(); for (auto e : elm.second) { int first = f(e.first), second = f(e.second); nodes.insert(first); nodes.insert(second); A[first].push_back(second); A[second].push_back(first); tmpmep[make_pair(min(first, second), max(first, second))] = mep[e]; } vector<pair<int, int> > roots; for (auto first : nodes) if (!visited[first]) roots.push_back(make_pair(first, dfs1(first))); for (auto first : nodes) visited[first] = false; for (auto p : roots) dfs2(p.first, -1, p.second); for (auto e : elm.second) add(e.first, e.second); for (auto first : nodes) { A[first].clear(); visited[first] = false; } } sort((maxs).begin(), (maxs).end()); printf( %lld %d n , 2 * MAX, (int)maxs.size()); for (auto m : maxs) printf( %d , m); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int get() { int x = 0; char s = getchar(); while (s < 0 || s > 9 ) s = getchar(); while (s >= 0 && s <= 9 ) x = (x << 3) + (x << 1) + (s ^ 48), s = getchar(); return x; } int Min(const int x, const int y) { if (x < y) return x; return y; } const int M = 1e5 + 5, mo = 1e9 + 7; int n, m, head[M], cntedge, vis[M], dfn[M], low[M], tot, cntscc, scc[M], siz[M], dep[M], f[M][17], w[M]; vector<int> G[M]; stack<int> st; struct edge { int to, nxt; edge() {} edge(const int T, const int NX) { to = T, nxt = NX; } } e[M << 1]; void add(const int u, const int v) { e[++cntedge] = edge(v, head[u]), head[u] = cntedge; } int pow(int x, int k) { int ans = 1; while (k) { if (k & 1) ans = 1ll * ans * x % mo; x = 1ll * x * x % mo; k >>= 1; } return ans; } void tarjan(const int u, const int fa) { dfn[u] = low[u] = ++tot; vis[u] = 1; st.push(u); int v; for (int i = head[u]; i; i = e[i].nxt) { v = e[i].to; if (v == fa || vis[v] == 2) continue; if (!vis[v]) tarjan(v, u); low[u] = Min(low[u], low[v]); } if (dfn[u] == low[u]) { ++cntscc; do { v = st.top(), st.pop(); scc[v] = cntscc; vis[v] = 2; ++siz[cntscc]; } while (v ^ u); } } void dfs(const int x, const int fa) { dep[x] = dep[fa] + 1; f[x][0] = fa; w[x] = w[fa] + (siz[x] > 1); for (int i = 1; i < 17; ++i) f[x][i] = f[f[x][i - 1]][i - 1]; for (int i = 0; i < G[x].size(); ++i) if (G[x][i] ^ fa) dfs(G[x][i], x); } void adjust(int &u, const int val) { for (int i = 16; i >= 0; --i) if (dep[f[u][i]] >= val) u = f[u][i]; } int lca(int u, int v) { if (dep[u] > dep[v]) adjust(u, dep[v]); else if (dep[u] < dep[v]) adjust(v, dep[u]); if (u == v) return u; for (int i = 16; i >= 0; --i) if (f[u][i] ^ f[v][i]) u = f[u][i], v = f[v][i]; return f[u][0]; } int main() { n = get(), m = get(); for (int u, v; m--;) { u = get(), v = get(); add(u, v), add(v, u); } for (int i = 1; i <= n; ++i) if (!dfn[i]) tarjan(i, 0); for (int i = 1; i <= n; ++i) for (int j = head[i]; j; j = e[j].nxt) if (scc[i] ^ scc[e[j].to]) G[scc[i]].push_back(scc[e[j].to]); dfs(1, 0); for (int q = get(), u, v, x, k; q--;) { u = scc[get()], v = scc[get()], x = lca(u, v); k = w[u] + w[v] - (w[x] << 1) + (siz[x] > 1); printf( %d n , pow(2, k)); } return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the addr_gen and the data_gen modules. It takes
// the user data stored in internal FIFOs and gives the data that is to be
// compared with the read data
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter ROW_WIDTH = 14
)
(
input clk,
input rst,
input wr_addr_en,
input wr_data_en,
input rd_data_valid,
output app_af_wren,
output [2:0] app_af_cmd,
output [30:0] app_af_addr,
output app_wdf_wren,
output [APPDATA_WIDTH-1:0] app_wdf_data,
output [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [APPDATA_WIDTH-1:0] app_cmp_data
);
//***************************************************************************
ddr2_tb_test_addr_gen #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
u_addr_gen
(
.clk (clk),
.rst (rst),
.wr_addr_en (wr_addr_en),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren)
);
ddr2_tb_test_data_gen #
(
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE)
)
u_data_gen
(
.clk (clk),
.rst (rst),
.wr_data_en (wr_data_en),
.rd_data_valid (rd_data_valid),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.app_cmp_data (app_cmp_data)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:ovld_reg:1.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_get_0_val_r_0 (
data_in,
vld_in,
ap_done,
clk,
data_out,
vld_out
);
input wire [31 : 0] data_in;
input wire vld_in;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done" *)
input wire ap_done;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
output wire [31 : 0] data_out;
output wire vld_out;
ovld_reg #(
.DATA_WIDTH(32)
) inst (
.data_in(data_in),
.vld_in(vld_in),
.ap_done(ap_done),
.clk(clk),
.data_out(data_out),
.vld_out(vld_out)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_CONTROL_BUS_s_axi
#(parameter
C_ADDR_WIDTH = 4,
C_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_DATA_WIDTH-1:0] WDATA,
input wire [C_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
// address bits
localparam
ADDR_BITS = 4;
// address
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc;
// axi write fsm
localparam
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2;
// axi read fsm
localparam
RDIDLE = 2'd0,
RDDATA = 2'd1;
//------------------------Local signal-------------------
// axi write
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
// axi read
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done;
reg int_ap_start;
reg int_auto_restart;
reg int_gie;
reg [1:0] int_ier;
reg [1:0] int_isr;
//------------------------Body---------------------------
//++++++++++++++++++++++++axi write++++++++++++++++++++++
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ARESET)
wstate <= WRIDLE;
else
wstate <= wnext;
end
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi read+++++++++++++++++++++++
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ARESET)
rstate <= RDIDLE;
else
rstate <= rnext;
end
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++internal registers+++++++++++++
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
|
`timescale 1 ns / 1 ps
module user_io_axi_conv #
(
parameter UIO_PORTS_WIDTH = 128,
parameter RQ_AXI_FIFO_DEPTH = 64,
parameter RS_AXI_FIFO_DEPTH = 64
)(
input clk,
input clk_per,
input reset,
input reset_per,
// AXI Connections
output [7:0] o_s_axi_tx_tkeep,
output [63:0] o_s_axi_tx_tdata,
output o_s_axi_tx_tlast,
output o_s_axi_tx_tvalid,
input i_s_axi_tx_tready,
input [7:0] i_m_axi_rx_tkeep,
input [63:0] i_m_axi_rx_tdata,
input i_m_axi_rx_tlast,
input i_m_axi_rx_tvalid,
input i_stat_chan_up,
// user-facing ports
input uio_rq_vld,
input [UIO_PORTS_WIDTH-1:0] uio_rq_data,
output uio_rq_afull,
output uio_rs_vld,
output [UIO_PORTS_WIDTH-1:0] uio_rs_data,
input uio_rs_afull
);
// Request AXI Clock Crossing FIFO
// FIXME: RATIO/SYNC???
wire r_axi_rq_pop;
wire [UIO_PORTS_WIDTH-1:0] r_axi_rq_dout;
wire r_axi_rq_empty;
wire r_uio_rq_afull;
wire fifo_reset = reset | reset_per | !i_stat_chan_up;
fifo #(.WIDTH(UIO_PORTS_WIDTH), .DEPTH(RQ_AXI_FIFO_DEPTH), .AFULLCNT(RQ_AXI_FIFO_DEPTH-6), .RATIO(3), .SYNCHRONOUS(0), .OSYNC_RESET(0))
rq_axi_fifo (
.clk(clk_per),
.reset(fifo_reset),
.push(uio_rq_vld),
.din(uio_rq_data),
.afull(r_uio_rq_afull),
.full(),
.cnt(),
.oclk(clk),
.pop(r_axi_rq_pop),
.dout(r_axi_rq_dout),
.empty(r_axi_rq_empty),
.rcnt()
);
// Request AXI Packet Formation
// Using 512b/64B packets - tlast every 8 valid cycles
reg [2:0] c_rq_axi_cyc_cnt;
wire [2:0] r_rq_axi_cyc_cnt;
wire r_rq_tx_ready = (!r_axi_rq_empty & i_s_axi_tx_tready);
wire [63:0] r_rq_tx_data = (r_rq_axi_cyc_cnt[0] == 1'd0) ? r_axi_rq_dout[63:0] : r_axi_rq_dout[127:64];
wire r_rq_tx_last = (r_rq_axi_cyc_cnt == 3'd7) ? 1'b1 : 1'b0;
always @(*) begin
c_rq_axi_cyc_cnt = r_rq_axi_cyc_cnt;
// (integer overflow expected)
if (r_rq_tx_ready) begin
c_rq_axi_cyc_cnt = r_rq_axi_cyc_cnt + 3'b1;
end
end
dffr #(.WIDTH(3)) dff_rq_axi_cyc_cnt (.clk(clk), .rst(reset), .d(c_rq_axi_cyc_cnt), .q(r_rq_axi_cyc_cnt));
// Request AXI FIFO Control
assign r_axi_rq_pop = r_rq_tx_ready && (r_rq_axi_cyc_cnt[0] == 1'd1);
// Request AXI Packet Output
assign o_s_axi_tx_tkeep = (r_rq_tx_ready) ? 8'hFF : 8'b0;
assign o_s_axi_tx_tdata = (r_rq_tx_ready) ? r_rq_tx_data : 64'h0;
assign o_s_axi_tx_tlast = (r_rq_tx_ready) ? r_rq_tx_last : 1'b0;
assign o_s_axi_tx_tvalid = r_rq_tx_ready;
// Hack: stop uio requests from coming in until channel is up?
assign uio_rq_afull = r_uio_rq_afull | !i_stat_chan_up;
// Response User IO Packet Formation
// Expecting 512b/64B packets - tlast every 8 valid cycles
// NOTE!!!
// This design does not expect to need to backpressure AXI at all,
// and therefore makes simplifcations based on this assumption.
// This also implies that we expect no backpressure from the User
// IO port interface. If your design requires flow control in
// this direction, you must account for this.
// We also expect that tkeep will always be 0xFF, and there will
// be no partial writes on the AXI bus.
reg c_rs_axi_cyc_cnt;
wire r_rs_axi_cyc_cnt;
reg [127:0] c_rs_axi_data;
wire [127:0] r_rs_axi_data;
reg c_rs_axi_push;
wire r_rs_axi_push;
always @(*) begin
c_rs_axi_cyc_cnt = r_rs_axi_cyc_cnt;
c_rs_axi_data = r_rs_axi_data;
c_rs_axi_push = 1'b0;
if (i_m_axi_rx_tvalid) begin
if (r_rs_axi_cyc_cnt == 1'b0) begin
c_rs_axi_data[63:0] = i_m_axi_rx_tdata;
end else begin
c_rs_axi_data[127:64] = i_m_axi_rx_tdata;
c_rs_axi_push = 1'b1;
end
c_rs_axi_cyc_cnt = ~r_rs_axi_cyc_cnt;
end
end
dffr #(.WIDTH(1)) dff_rs_axi_cyc_cnt (.clk(clk), .rst(reset), .d(c_rs_axi_cyc_cnt), .q(r_rs_axi_cyc_cnt));
dffr #(.WIDTH(128)) dff_rs_axi_data (.clk(clk), .rst(reset), .d(c_rs_axi_data), .q(r_rs_axi_data));
dffr #(.WIDTH(1)) dff_rs_axi_push (.clk(clk), .rst(reset), .d(c_rs_axi_push), .q(r_rs_axi_push));
// Response User IO Clock Crossing FIFO
// FIXME: RATIO/SYNC???
wire r_axi_rs_pop;
wire r_axi_rs_empty;
fifo #(.WIDTH(UIO_PORTS_WIDTH), .DEPTH(RS_AXI_FIFO_DEPTH), .RATIO(3), .SYNCHRONOUS(0), .OSYNC_RESET(0))
rs_axi_fifo (
.clk(clk),
.reset(fifo_reset),
.push(r_rs_axi_push),
.din(r_rs_axi_data),
.afull(),
.full(),
.cnt(),
.oclk(clk_per),
.pop(uio_rs_vld),
.dout(uio_rs_data),
.empty(r_axi_rs_empty),
.rcnt()
);
// Response User IO Packet Output
assign uio_rs_vld = !r_axi_rs_empty;
endmodule
|
// megafunction wizard: %ROM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: jump_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module jump_ram (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [4:0] address_a;
input [4:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "jump_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "jump_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL jump_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long mas[200100], k, s = 0, d; long long n, p = 1, del = 0, a, b, c; unsigned long long inf = (unsigned long long)1000000000 * 1000000000 * (long long)10; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) scanf( %I64d , &mas[i]); for (int i = 1; i <= n; i++, p++) { a = (p - 1); b = (n - del - p); c = mas[i]; if (a * b > (s - k) / c) { printf( %d n , i); p--; del++; } else { if (s < inf) s += (p - 1) * mas[i]; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Node { int x, y, t; Node(int x = -1, int y = -1, int t = 0) : x(x), y(y) {} }; Node a[1005]; string G[1005]; int row[1005], col[1005]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> G[i]; G[i] = + G[i]; } memset(row, 0, sizeof(row)); memset(col, 0, sizeof(col)); int cnt = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (G[i][j] == * ) { row[i]++; col[i]++; int flag = 0; for (int k = 0; k < cnt; k++) { if (a[k].x == i || a[k].y == j) { flag = 1; if (a[k].x == i) a[k].t = -a[k].x; else if (a[k].y == j) a[k].t = a[k].y; break; } } if (!flag && cnt < 10) a[cnt++] = Node(i, j); } } } int cntr = 0, cntc = 0; for (int i = 1; i <= n; i++) { if (row[i] > 1) cntr++; } for (int i = 1; i <= m; i++) { if (col[i] > 1) cntc++; } if (cnt > 2 || cntr > 1 || cntc > 1) cout << NO << endl; else { cout << YES << endl; if (cnt == 0) cout << 1 << << 1 << endl; else if (cnt == 1) cout << a[0].x << << a[0].y << endl; else { if (a[0].t != 0 && a[1].t != 0) { int x, y; if (a[0].t > 0) x = -a[1].t, y = a[0].t; else x = -a[0].t, y = a[1].t; cout << x << << y << endl; } else if (a[0].t != 0) { if (a[0].t > 0) cout << a[1].x << << a[0].y << endl; else cout << a[0].x << << a[1].y << endl; } else if (a[1].t != 0) { if (a[1].t < 0) cout << a[1].x << << a[0].y << endl; else cout << a[0].x << << a[1].y << endl; } else { cout << a[0].x << << a[1].y << endl; } } } return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 16054 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w5,
w8192,
w8187,
w160,
w8027,
w16054;
assign w1 = i_data0;
assign w160 = w5 << 5;
assign w16054 = w8027 << 1;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w8027 = w8187 - w160;
assign w8187 = w8192 - w5;
assign w8192 = w1 << 13;
assign o_data0 = w16054;
//multiplier_block area estimate = 5272.34396680147;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_TB_V
`define SKY130_FD_SC_MS__A21O_TB_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ms__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 16:03:48
// Design Name:
// Module Name: lab4_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab4_1(
input CP,M,D,C,B,A,LD,CLR,
output reg Qd,Qc,Qb,Qa,Qcc
);
reg [3:0] count;
always @(posedge CP or negedge CLR or negedge LD)
begin
if(CLR == 0)
begin
count = 0;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
else if(LD == 0)
begin
count = {D,C,B,A};
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
else if(M == 1)
begin
if(count ==15)
begin
count = 0;
{Qd,Qc,Qb,Qa} = count;
Qcc = 0;
end
else
begin
count = count + 1;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
end
else
begin
if(count == 0)
begin
count = 15;
{Qd,Qc,Qb,Qa} = count;
Qcc = 0;
end
else
begin
count =count - 1;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_1_V
`define SKY130_FD_SC_LS__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_1_V
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac2_ctlif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq_rx,
output irq_tx,
output [1:0] rx_ready,
input [1:0] rx_done,
input [10:0] rx_count_0,
input [10:0] rx_count_1,
output tx_start,
input tx_done,
output reg [10:0] tx_count,
output reg phy_mii_clk,
inout phy_mii_data,
output phy_rst_n
);
reg mii_data_oe;
reg mii_data_do;
assign phy_mii_data = mii_data_oe ? mii_data_do : 1'bz;
/* Be paranoid about metastability */
reg mii_data_di1;
reg mii_data_di;
always @(posedge sys_clk) begin
mii_data_di1 <= phy_mii_data;
mii_data_di <= mii_data_di1;
end
reg phy_rst;
assign phy_rst_n = ~(phy_rst | sys_rst);
/*
* RX Slots
*
* State:
* 00 -> slot is disabled
* 01 -> slot can receive a new packet
* 10 -> slot has received a packet (IRQ asserted)
* 11 -> invalid
*/
reg [1:0] slot0_state;
reg [1:0] slot1_state;
wire csr_selected = csr_a[13:10] == csr_addr;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
phy_rst <= 1'b1;
mii_data_oe <= 1'b0;
mii_data_do <= 1'b0;
phy_mii_clk <= 1'b0;
phy_rst <= 1'b0;
slot0_state <= 2'b00;
slot1_state <= 2'b00;
tx_count <= 11'd0;
end else begin
csr_do <= 32'd0;
if(csr_selected) begin
if(csr_we) begin
case(csr_a[2:0])
3'd0: phy_rst <= csr_di[0];
3'd1: begin
phy_mii_clk <= csr_di[3];
mii_data_oe <= csr_di[2];
mii_data_do <= csr_di[0];
end
3'd2: slot0_state <= csr_di[1:0];
// 'd3 rx_count_0 is read-only
3'd4: slot1_state <= csr_di[1:0];
// 'd5 rx_count_1 is read-only
3'd6: tx_count <= csr_di[10:0];
endcase
end
case(csr_a[2:0])
3'd0: csr_do <= phy_rst;
3'd1: csr_do <= {phy_mii_clk, mii_data_oe, mii_data_di, mii_data_do};
3'd2: csr_do <= slot0_state;
3'd3: csr_do <= rx_count_0;
3'd4: csr_do <= slot1_state;
3'd5: csr_do <= rx_count_1;
3'd6: csr_do <= tx_count;
endcase
end /* if(csr_selected) */
if(rx_done[0])
slot0_state <= 2'b10;
if(rx_done[1])
slot1_state <= 2'b10;
if(tx_done)
tx_count <= 11'd0;
end
end
wire [1:0] slots_loaded = {slot1_state[0], slot0_state[0]};
reg [1:0] slots_loaded_r;
always @(posedge sys_clk)
slots_loaded_r <= slots_loaded;
assign rx_ready = slots_loaded & ~slots_loaded_r;
wire tx_remaining = |tx_count;
reg tx_remaining_r;
always @(posedge sys_clk)
tx_remaining_r <= tx_remaining;
assign tx_start = tx_remaining & ~tx_remaining_r;
/* Interrupt logic */
assign irq_rx = slot0_state[1] | slot1_state[1];
assign irq_tx = tx_done;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A22OI_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a22oi (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 2e5 + 555; int n, m, q, z; pair<long long, int> a[N]; int qt[N]; long long ql[N], qr[N]; long long ans[N]; vector<pair<int, int> > ed[N]; long long bl[N], br[N], arin[N]; int f[N * 20]; const int iu = 18; int lg[N * 2]; long long st[N][iu], nid[N][iu]; long long sh[N][iu]; void adde(int u, int v, int t) { ed[t].push_back({u, v}); } void add(int id, int l, int r) { int duh = lg[r - l + 1]; int e = r - (1 << duh) + 1; st[l][duh] = max(st[l][duh], min(arin[id], sh[l][duh])); st[e][duh] = max(st[e][duh], min(arin[id], sh[e][duh])); adde(id, nid[l][duh], min(arin[id], sh[l][duh])); adde(id, nid[e][duh], min(arin[id], sh[e][duh])); } int find(int x) { if (f[x] != x) f[x] = find(f[x]); return f[x]; } void join(int x, int y) { x = find(x); y = find(y); f[x] = y; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> q; for (int i = 2; i < 262144; i++) lg[i] = lg[i / 2] + 1; a[++m] = {-1, -q - 1}; a[++m] = {1LL << n, q + 1}; for (int i = 1; i <= q; i++) { string s; cin >> s >> ql[i] >> qr[i]; if (s[0] == b ) qt[i] = 1; else qt[i] = 2; if (qt[i] == 1) { a[++m] = {ql[i], -i}; a[++m] = {qr[i], i}; } } sort(a + 1, a + m + 1); for (int i = 1; i < m; i++) { long long cl = a[i].first + (i % 2); long long cr = a[i + 1].first - (i % 2); int cc; if (i % 2 == 1) cc = q + 1; else cc = -a[i].second; if (cl > cr) continue; if (cl == cr) { bl[++z] = cl; br[z] = cr; arin[z] = cc; } else { long long fk = cl ^ cr; while (fk != (fk & -fk)) fk ^= fk & -fk; long long mid = cl | (fk - 1); bl[++z] = cl; br[z] = mid; arin[z] = cc; bl[++z] = mid + 1; br[z] = cr; arin[z] = cc; } } int ptr = z; for (int j = 0; j < iu; j++) { for (int i = 1; i <= z; i++) { nid[i][j] = ++ptr; if (j == 0) sh[i][j] = arin[i]; else if (i + (1 << (j - 1)) <= z) { sh[i][j] = max(sh[i][j - 1], sh[i + (1 << (j - 1))][j - 1]); } } } for (int i = 1; i <= z; i++) { for (int k = n - 1; k >= 0; k--) { long long cl, cr; bool die = false; if (br[i] - bl[i] + 1 > (1LL << k)) { cr = bl[i] | ((1LL << (k + 1)) - 1); cl = cr ^ ((1LL << (k + 1)) - 1); die = true; } else { cl = bl[i] ^ (1LL << k); cr = br[i] ^ (1LL << k); } int zl = lower_bound(br + 1, br + z + 1, cl) - br; int zr = lower_bound(bl + 1, bl + z + 1, cr + 1) - bl - 1; add(i, zl, zr); if (die) break; } adde(i, nid[i][0], arin[i]); } for (int j = iu - 2; j >= 0; j--) { for (int i = 1; i <= z; i++) { st[i][j] = max(st[i][j], st[i][j + 1]); adde(nid[i][j], nid[i][j + 1], min(st[i][j + 1], sh[i][j])); if (i > (1 << j)) { st[i][j] = max(st[i][j], st[i - (1 << j)][j + 1]); adde(nid[i][j], nid[i - (1 << j)][j + 1], min(st[i - (1 << j)][j + 1], sh[i][j])); } } } for (int i = 1; i <= ptr; i++) f[i] = i; for (int i = q + 1; i >= 1; i--) { for (auto c : ed[i]) join(c.first, c.second); if (qt[i] == 2) { int cl = lower_bound(br + 1, br + z + 1, ql[i]) - br; int cr = lower_bound(br + 1, br + z + 1, qr[i]) - br; ans[i] = find(cl) == find(cr); } } for (int i = 1; i <= q; i++) { if (qt[i] == 2) cout << ans[i] << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_2_V
`define SKY130_FD_SC_HD__DLCLKP_2_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_2 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_2 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_2_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } template <class T> inline T bpow(T p, T e) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p); p = (p * p); } return (T)ret; } int ts, kk = 1; struct D { D *l, *r; int cnt; D() { l = r = NULL; cnt = 0; } }; int n, m; pair<int, pair<int, int> > a[100005]; D *tr[10005]; void updt(D *rt, int s, int e, int p) { if (rt == NULL) return; if (p <= s && e <= p) { rt->cnt++; return; } if (rt->l == NULL) rt->l = new D(); if (rt->r == NULL) rt->r = new D(); if (p <= ((s + e) >> 1)) updt(rt->l, s, ((s + e) >> 1), p); else updt(rt->r, ((s + e) >> 1) + 1, e, p); rt->cnt++; } int qry(D *c, int s, int e, int st, int ed) { if (c == NULL) return 0; if (st <= s && e <= ed) return c->cnt; if (ed <= ((s + e) >> 1)) return qry(c->l, s, ((s + e) >> 1), st, ed); if (((s + e) >> 1) < st) return qry(c->r, ((s + e) >> 1) + 1, e, st, ed); return qry(c->l, s, ((s + e) >> 1), st, ed) + qry(c->r, ((s + e) >> 1) + 1, e, st, ed); } int main() { int t, i, j, k; scanf( %d%d , &n, &m); for (i = 0; i < m + 1; i++) tr[i] = NULL; for (i = 0; i < n; i++) { scanf( %d%d%d , &j, &k, &t); a[i] = make_pair(-k, pair<int, int>(t, j)); } sort(a, a + n); long long int rs = 0; for (i = 0; i < n; i++) { int l, r; l = a[i].second.second + a[i].first; r = a[i].second.second - a[i].first; if (l < 1) l = 1; if (r > 1000000007LL) r = 1000000007LL; k = a[i].second.first; for (j = max(1, k - m); j <= min(10005, k + m); j++) rs += qry(tr[j], 1, 1000000007LL, l, r); if (tr[k] == NULL) tr[k] = new D(); updt(tr[k], 1, 1000000007LL, a[i].second.second); } printf( %lld n , rs); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 10; int main() { ios_base ::sync_with_stdio(false), cout.tie(0), cin.tie(0); int n, cnt = 0; cin >> n; int sv = n; while (n--) { int x, y; cin >> x >> y; if (x < 0) ++cnt; } cout << (min(cnt, sv - cnt) <= 1 ? Yes n : No n ); return 0; }
|
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ()
// Stage #3: Write-back unit.
`include "const.vh"
module WriteBackStage #(
)(
input clk, reset,
input wire [2:0] s3_rdata_sel,
input wire [1:0] byte_select,
input wire [`CPU_DATA_BITS-1:0] s3_rdata,
output reg [`CPU_DATA_BITS-1:0] s3_rdata_out
);
// TODO(aryap): This is because I don't want to understand Verilog's
// signed/unsigned operator semantics. There's probably an easier way...
localparam BYTE_SIGN_BITS = `CPU_DATA_BITS - 8;
localparam HALF_WORD_SIGN_BITS = `CPU_DATA_BITS - 16;
wire [31:0] byteX =
(s3_rdata & (32'hFF << (byte_select * 8))) >> (byte_select * 8);
wire [31:0] half_word =
(s3_rdata & (32'hFFFF << (byte_select * 8))) >> (byte_select * 8);
always @(*) begin
case (s3_rdata_sel)
`S3_RDATA_SEL_PASSTHROUGH:
s3_rdata_out = s3_rdata;
`S3_RDATA_SEL_LOW_BYTE:
s3_rdata_out = {{BYTE_SIGN_BITS{1'b0}}, byteX[7:0]};
`S3_RDATA_SEL_LOW_BYTE_SIGNED:
s3_rdata_out = {{BYTE_SIGN_BITS{byteX[7]}}, byteX[7:0]};
`S3_RDATA_SEL_LOW_HALF_WORD:
s3_rdata_out = {{HALF_WORD_SIGN_BITS{1'b0}}, half_word[15:0]};
`S3_RDATA_SEL_LOW_HALF_WORD_SIGNED:
s3_rdata_out =
{{HALF_WORD_SIGN_BITS{half_word[15]}}, half_word[15:0]};
default: s3_rdata_out = s3_rdata;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> tree[300001]; int cento[300001]; int sub[300001]; int maxCh[300001]; int n, q; void dfs(int u, int p = -1) { sub[u] = 1; maxCh[u] = 0; for (int j = 0; j < tree[u].size(); ++j) { int v = tree[u][j]; if (v == p) continue; dfs(v, u); sub[u] += sub[v]; maxCh[u] = max(maxCh[u], sub[v]); } } set<pair<pair<int, int>, int> > merge(int u, int p = -1) { int sz = tree[u].size(); if (sz == 1 && u != 0) { cento[u] = u; set<pair<pair<int, int>, int> > s; s.insert(make_pair(pair<int, int>(sub[u], maxCh[u]), u)); return s; } int bigCh = -1; int maxsz = -1; for (int j = 0; j < tree[u].size(); ++j) { int v = tree[u][j]; if (v == p) continue; if (maxsz < sub[v]) { maxsz = sub[v]; bigCh = v; } } set<pair<pair<int, int>, int> > s = merge(bigCh, u); for (int j = 0; j < tree[u].size(); ++j) { int v = tree[u][j]; if (v == p || v == bigCh) continue; set<pair<pair<int, int>, int> > tmp = merge(v, u); for (set<pair<pair<int, int>, int> >::iterator it = tmp.begin(); it != tmp.end(); ++it) { s.insert(*it); } } s.insert(make_pair(pair<int, int>(sub[u], maxCh[u]), u)); int x = sub[u] >> 1; ; if (sub[u] & 1) ++x; set<pair<pair<int, int>, int> >::iterator it = s.lower_bound(make_pair(pair<int, int>(x, 0), 0)); cento[u] = it->second; return s; } int main() { scanf( %d %d , &n, &q); int v = 0; for (int i = 1; i < n; ++i) { scanf( %d , &v); --v; tree[i].push_back(v); tree[v].push_back(i); } memset(cento, -1, sizeof(cento)); dfs(0, -1); for (int i = 0; i < n; ++i) { --sub[i]; } merge(0, -1); while (q--) { int u; scanf( %d , &u); --u; printf( %d n , cento[u] + 1); } }
|
#include <bits/stdc++.h> using namespace std; int64_t n; vector<int64_t> adj[100001]; int64_t ss[100001]; void dfs(int64_t no, int64_t par = -1) { ss[no] = 1; for (auto j : adj[no]) { if (j == par) { continue; } dfs(j, no); ss[no] += ss[j]; } } vector<int64_t> ord; int64_t dfs2(int64_t no, int64_t par = -1) { for (auto j : adj[no]) { if (j == par) { continue; } if (ss[j] > n / 2) { return dfs2(j, no); } } return no; } int64_t ans = 0; void dfs3(int64_t no, int64_t par = -1, int64_t levv = 0) { ord.push_back(no); ans += levv * 2; for (auto j : adj[no]) { if (j == par) { continue; } dfs3(j, no, levv + 1); } } int64_t ans2[100001]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int64_t i = 0; i < n - 1; i++) { int64_t aa, bb; cin >> aa >> bb; aa--; bb--; adj[aa].push_back(bb); adj[bb].push_back(aa); } dfs(0); int64_t cen = dfs2(0); dfs3(cen); for (int64_t i = 0; i < n; i++) { ord.push_back(ord[i]); } int64_t x = (n / 2); cout << ans << endl; for (int64_t i = 0; i < n; i++) { ans2[ord[i]] = ord[i + x] + 1; } for (int64_t i = 0; i < n; i++) { cout << ans2[i] << ; } cout << endl; return 0; }
|
// This slightly convoluted module used to cause an argument-size
// mismatch in the call to the function extend_data
module test (c);
parameter MAX_SIZE = 32;
input c;
reg [MAX_SIZE-1:0] d,
e,
f;
reg [7:0] g;
wire h;
always @(posedge h or negedge c)
if (~c)
f <= #2 {MAX_SIZE{1'b0}};
else
case (g)
8'h18 :
f <= #2 hw(d, e);
default :
f <= #2 {MAX_SIZE{1'b0}};
endcase
parameter FALSE_RESULT = {MAX_SIZE{1'b0}},
TRUE_RESULT = FALSE_RESULT | 1'b1;
function integer sign_of;
input [2*MAX_SIZE-1:0] data;
input size;
reg [2*MAX_SIZE-1:0] data;
integer size;
if (data[size-1]===1'b1)
sign_of = -1;
else
sign_of = 1;
endfunction
function [2*MAX_SIZE-1:0] extend_data;
input [2*MAX_SIZE-1:0] data;
input size;
input new_size;
input extend;
reg [2*MAX_SIZE-1:0] data;
integer size,
new_size;
reg extend;
for (extend_data = data ; new_size-size>0 ; new_size=new_size-1)
extend_data[new_size-1] = extend & data[size-1];
endfunction
function [MAX_SIZE-1:0] hw;
input [MAX_SIZE-1:0] a;
input [MAX_SIZE-1:0] b;
reg [MAX_SIZE-1:0] a,
b;
reg [MAX_SIZE:0] diff;
begin
diff = extend_data(b, MAX_SIZE, MAX_SIZE+1, 1'b1) -
extend_data(a, MAX_SIZE, MAX_SIZE+1, 1'b1);
if (sign_of(diff, MAX_SIZE+1)==-1)
hw = TRUE_RESULT;
else
hw = FALSE_RESULT;
end
endfunction
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module sends and receives data to/from the DE2's audio and TV *
* peripherals' control registers. *
* *
******************************************************************************/
module altera_up_av_config_serial_bus_controller (
// Inputs
clk,
reset,
start_transfer,
data_in,
transfer_mask,
restart_counter,
restart_data_in,
restart_transfer_mask,
// Bidirectionals
serial_data,
// Outputs
serial_clk,
serial_en,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 26; // Datawidth
parameter CW = 4; // Counter's datawidth
parameter SCCW = 11; // Slow clock's counter's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input start_transfer;
input [DW: 0] data_in;
input [DW: 0] transfer_mask;
input [CW: 0] restart_counter;
input [DW: 0] restart_data_in;
input [DW: 0] restart_transfer_mask;
// Bidirectionals
inout serial_data; // I2C Data
// Outputs
output serial_clk; // I2C Clock
output reg serial_en;
output [DW: 0] data_out;
output reg transfer_complete;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States for finite state machines
localparam STATE_0_IDLE = 3'h0,
STATE_1_INITIALIZE = 3'h1,
STATE_2_RESTART_BIT = 3'h2,
STATE_3_START_BIT = 3'h3,
STATE_4_TRANSFER = 3'h4,
STATE_5_STOP_BIT = 3'h5;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire slow_clk;
wire toggle_data_in;
wire toggle_data_out;
// Internal Registers
reg [CW: 0] counter;
reg [DW: 0] shiftreg_data;
reg [DW: 0] shiftreg_mask;
reg new_data;
// State Machine Registers
reg [ 2: 0] ns_serial_protocol;
reg [ 2: 0] s_serial_protocol;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_serial_protocol <= STATE_0_IDLE;
else
s_serial_protocol <= ns_serial_protocol;
end
always @(*)
begin
// Defaults
ns_serial_protocol = STATE_0_IDLE;
case (s_serial_protocol)
STATE_0_IDLE:
begin
if (start_transfer & ~transfer_complete & toggle_data_in)
ns_serial_protocol = STATE_1_INITIALIZE;
else
ns_serial_protocol = STATE_0_IDLE;
end
STATE_1_INITIALIZE:
begin
ns_serial_protocol = STATE_3_START_BIT;
end
STATE_2_RESTART_BIT:
begin
if (toggle_data_in)
ns_serial_protocol = STATE_3_START_BIT;
else
ns_serial_protocol = STATE_2_RESTART_BIT;
end
STATE_3_START_BIT:
begin
if (toggle_data_out)
ns_serial_protocol = STATE_4_TRANSFER;
else
ns_serial_protocol = STATE_3_START_BIT;
end
STATE_4_TRANSFER:
begin
if (toggle_data_out & (counter == DW))
ns_serial_protocol = STATE_5_STOP_BIT;
else if (toggle_data_out & shiftreg_mask[DW] & shiftreg_data[DW])
ns_serial_protocol = STATE_2_RESTART_BIT;
else
ns_serial_protocol = STATE_4_TRANSFER;
end
STATE_5_STOP_BIT:
begin
if (toggle_data_in)
ns_serial_protocol = STATE_0_IDLE;
else
ns_serial_protocol = STATE_5_STOP_BIT;
end
default:
begin
ns_serial_protocol = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
serial_en <= 1'b1;
else if (toggle_data_out & (s_serial_protocol == STATE_3_START_BIT))
serial_en <= 1'b0;
else if (s_serial_protocol == STATE_5_STOP_BIT)
serial_en <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
transfer_complete <= 1'b0;
else if (s_serial_protocol == STATE_5_STOP_BIT)
transfer_complete <= 1'b1;
else if (~start_transfer)
transfer_complete <= 1'b0;
end
// Input Registers
always @(posedge clk)
begin
if (reset)
begin
counter <= 'h0;
shiftreg_data <= 'h0;
shiftreg_mask <= 'h0;
end
else if (s_serial_protocol == STATE_1_INITIALIZE)
begin
counter <= 'h0;
shiftreg_data <= data_in;
shiftreg_mask <= transfer_mask;
end
else if (toggle_data_in & (s_serial_protocol == STATE_2_RESTART_BIT))
begin
counter <= restart_counter;
shiftreg_data <= restart_data_in;
shiftreg_mask <= restart_transfer_mask;
end
else if (toggle_data_out & (s_serial_protocol == STATE_4_TRANSFER))
begin
counter <= counter + 'h1;
shiftreg_data <= {shiftreg_data[(DW - 1):0], new_data};
shiftreg_mask <= {shiftreg_mask[(DW - 1):0], 1'b0};
end
end
always @(posedge clk)
begin
if (reset)
new_data <= 1'b0;
else if (toggle_data_in & (s_serial_protocol == STATE_4_TRANSFER))
new_data <= serial_data;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign serial_clk = (s_serial_protocol == STATE_0_IDLE) ? 1'b1 : slow_clk;
assign serial_data = (s_serial_protocol == STATE_0_IDLE) ? 1'b1 :
(s_serial_protocol == STATE_2_RESTART_BIT) ? 1'b1 :
(s_serial_protocol == STATE_4_TRANSFER) ?
((shiftreg_mask[DW]) ? 1'bz :
shiftreg_data[DW]) :
1'b0;
assign data_out = shiftreg_data;
// Input Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_slow_clock_generator Serial_Config_Clock_Generator (
// Inputs
.clk (clk),
.reset (reset),
.enable_clk (1'b1),
// Bidirectionals
// Outputs
.new_clk (slow_clk),
.rising_edge (),
.falling_edge (),
.middle_of_high_level (toggle_data_in),
.middle_of_low_level (toggle_data_out)
);
defparam
Serial_Config_Clock_Generator.CB = SCCW;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_t_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
module fifo_address_gray_pipelined (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [C_ADDRESS_WIDTH:0] _s_axis_raddr;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [C_ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] ||
_s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
end
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Block_sin_taylor_ser (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_read,
p_read1,
ap_return
);
parameter ap_ST_fsm_state1 = 5'd1;
parameter ap_ST_fsm_state2 = 5'd2;
parameter ap_ST_fsm_state3 = 5'd4;
parameter ap_ST_fsm_state4 = 5'd8;
parameter ap_ST_fsm_state5 = 5'd16;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [63:0] p_read;
input [63:0] p_read1;
output [63:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[63:0] ap_return;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [4:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
wire [63:0] grp_fu_18_p2;
reg grp_fu_18_ce;
wire ap_CS_fsm_state5;
reg [63:0] ap_return_preg;
reg [4:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 5'd1;
#0 ap_return_preg = 64'd0;
end
sin_taylor_seriesfYi #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
sin_taylor_seriesfYi_U12(
.clk(ap_clk),
.reset(ap_rst),
.din0(p_read),
.din1(p_read1),
.ce(grp_fu_18_ce),
.dout(grp_fu_18_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((1'b1 == ap_continue)) begin
ap_done_reg <= 1'b0;
end else if ((1'b1 == ap_CS_fsm_state5)) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 64'd0;
end else begin
if ((1'b1 == ap_CS_fsm_state5)) begin
ap_return_preg <= grp_fu_18_p2;
end
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state5)) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state5)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state5)) begin
ap_return = grp_fu_18_p2;
end else begin
ap_return = ap_return_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & ((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
grp_fu_18_ce = 1'b0;
end else begin
grp_fu_18_ce = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (ap_done_reg == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
ap_NS_fsm = ap_ST_fsm_state5;
end
ap_ST_fsm_state5 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];
always @ (*) begin
ap_block_state1 = ((1'b0 == ap_start) | (ap_done_reg == 1'b1));
end
endmodule //Block_sin_taylor_ser
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for main module.
`timescale 10 ns / 1 ns
`include "registers.vh"
`include "tile_registers.vh"
module Main_Test;
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=8;
reg clk; // System clock
reg reset; // System reset
reg rd; // Read enable
reg wr; // Write enable
reg ale; // Address latch enable.
reg [ADDR_WIDTH-1:0] addr; // Address bus
reg [DATA_WIDTH-1:0] data_in; // Data in bus
reg data_valid; // Indicates data-in is valid.
wire [DATA_WIDTH-1:0] data_out; // Data out bus
wire [DATA_WIDTH-1:0] ad;
MainAVR main_avr(._reset(~reset), .clk(clk),
._mpu_rd(~rd), ._mpu_wr(~wr), .mpu_ale(ale),
.mpu_ah(addr[ADDR_WIDTH-1:DATA_WIDTH]), .mpu_ad(ad));
assign data_out = (rd & ~wr & ~ale) ? ad : 'bx;
assign ad = ale ? addr[DATA_WIDTH-1:0] : (data_valid ? data_in : 'bz);
// Generate clock.
always
#1 clk = ~clk;
integer i;
reg [4:0] stage = 0;
initial begin
clk = 0;
reset = 0;
rd = 0;
wr = 0;
addr = 0;
data_in = 0;
data_valid = 0;
// Reset
#5 stage = 1;
#1 reset = 1;
#5 reset = 0;
#1 addr = 'bx;
// Test some writes
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
// Test some reads
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
// Test some byte writes
#5 stage = 4;
for (i = 0; i < 16; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
// Test some reads
#5 stage = 5;
#1 read_test();
// Test some tile reg writes
#5 stage = 6;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 write16((`TILE_REG_ADDR_BASE + i) * 2, ~i);
end
#5 stage = 7;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 read8((`TILE_REG_ADDR_BASE + i) * 2);
#1 read8((`TILE_REG_ADDR_BASE + i) * 2 + 1);
end
// Test some palette writes
#5 stage = 8;
for (i = 0; i < 16; i = i + 1)
begin
#1 write16('h1000 + i * 2, ~i);
end
#5 stage = 9;
for (i = 0; i < 32; i = i + 1)
begin
#1 read8('h1000 + i);
end
end
// Task to write a byte.
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg;
data_in = data_arg;
#2 rd = 0; wr = 0; ale = 1; data_valid = 0;
#2 rd = 0; wr = 1; ale = 0; data_valid = 1;
#2 rd = 0; wr = 0; ale = 0; data_valid = 1;
#2 data_valid = 0;
end
endtask
// Task to write a word.
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH*2-1:0] data_arg;
begin
write8(addr_arg, data_arg[DATA_WIDTH-1:0]);
write8(addr_arg + 1, data_arg[DATA_WIDTH*2-1:DATA_WIDTH]);
end
endtask
// Task to read a byte.
task read8;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg;
#2 rd = 0; wr = 0; ale = 1;
#2 rd = 1; wr = 0; ale = 0;
#2 rd = 0; wr = 0; ale = 0;
end
endtask
// Readback test for the register
task read_test;
integer i;
begin
// Test some reads
#5
for (i = 0; i < 30; i = i + 1) begin
#1 read8(i);
end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 1000; int n; char s[MAXN + 1]; int solve() { int ret = n; for (int i = (0); i < (n); ++i) if (s[i] == 1 || s[n - i - 1] == 1 ) ret = max(ret, 2 * (n - i)); return ret; } void run() { scanf( %d , &n); scanf( %s , s); assert(strlen(s) == n); printf( %d n , solve()); } int main() { int ncase; scanf( %d , &ncase); for (int i = (1); i <= (ncase); ++i) run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, x, y, a, l, w, z, ss, t, k, e, c, total, nnn, yes, mx = 531, mn = -1, r, xx, yy, last, cas; map<string, int> wow; int main() { string s; cin >> s; wow[s] = 1; x = 1; l = s.size(); for (int i = 0; i < l; i++) { char te = s[l - 1]; for (int j = l - 1; j > 0; j--) { s[j] = s[j - 1]; } s[0] = te; if (wow[s] == 0) { x++; wow[s]++; } } cout << x; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; const int mod = 1e9 + 7; int n, m; int c[N][N], fac[N], f[N][N][2][2], dp[N], g[N]; void Init() { scanf( %d%d , &n, &m); c[0][0] = 1; for (int i = 1; i <= n; i++) { c[i][0] = 1; for (int j = 1; j <= i; j++) { c[i][j] = c[i - 1][j] + c[i - 1][j - 1]; if (c[i][j] >= mod) c[i][j] -= mod; } } fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = 1LL * fac[i - 1] * i % mod; } inline void Add(int &x, int y) { x += y; if (x >= mod) x -= mod; } int main() { Init(); f[1][0][1][0] = 1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= i; j++) { for (int a = 0; a < 2; a++) { for (int b = 0; b < 2; b++) { int t = f[i][j][a][b]; Add(f[i + 1][j][b][0], t); Add(f[i + 1][j + 1][b][1], t); if (a == 0) Add(f[i + 1][j + 1][b][0], t); } } } } for (int i = 0; i <= n; i++) { for (int j = 0; j < 2; j++) { Add(dp[i], f[n + 1][i][j][0]); } } for (int i = n; i >= 0; i--) { g[i] = 1LL * dp[i] * fac[n - i] % mod; for (int j = i + 1; j <= n; j++) { g[i] -= 1LL * c[j][i] * g[j] % mod; if (g[i] < 0) g[i] += mod; } } printf( %d n , g[m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct p { int L, R, U, D; } point[5005], pos[5005]; string g[5005]; void DEL(int x) { pos[pos[x].D].U = pos[x].U; pos[pos[x].U].D = pos[x].D; pos[pos[x].R].L = pos[x].L; pos[pos[x].L].R = pos[x].R; } int main() { int m, n, i, j, l, sx, sy; scanf( %d%d , &m, &n); for (i = 0; i < m; i++) cin >> g[i]; n = g[0].size(); for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { if (g[i][j] != . ) { for (l = i - 1; l >= 0; l--) if (g[l][j] != . ) break; if (l < 0) point[i * n + j].U = -1; else point[i * n + j].U = l * n + j; for (l = i + 1; l < m; l++) if (g[l][j] != . ) break; if (l >= m) point[i * n + j].D = -1; else point[i * n + j].D = l * n + j; for (l = j - 1; l >= 0; l--) if (g[i][l] != . ) break; if (l < 0) point[i * n + j].L = -1; else point[i * n + j].L = i * n + l; for (l = j + 1; l < n; l++) if (g[i][l] != . ) break; if (l >= n) point[i * n + j].R = -1; else point[i * n + j].R = i * n + l; } } } int r1 = 0, r2 = 0, cnt, t, x, y; for (sx = 0; sx < m; sx++) { for (sy = 0; sy < n; sy++) if (g[sx][sy] != . ) { for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { pos[i * n + j] = point[i * n + j]; } } if (g[sx][sy] == D ) t = pos[sx * n + sy].D; else if (g[sx][sy] == U ) t = pos[sx * n + sy].U; else if (g[sx][sy] == R ) t = pos[sx * n + sy].R; else if (g[sx][sy] == L ) t = pos[sx * n + sy].L; DEL(sx * n + sy); cnt = 1; while (t != -1) { cnt++; x = t / n; y = t % n; DEL(t); if (g[x][y] == D ) t = pos[t].D; else if (g[x][y] == U ) t = pos[t].U; else if (g[x][y] == R ) t = pos[t].R; else if (g[x][y] == L ) t = pos[t].L; } if (cnt > r1) { r1 = cnt; r2 = 1; } else if (cnt == r1) { r2++; } } } printf( %d %d n , r1, r2); return 0; }
|
/*
* Copyright (c) 2000 Yasuhisa Kato <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Modified my to be self-checking per the comments.
module main;
reg clk ;
initial begin clk = 0 ; forever #5 clk = ~clk ; end
initial #20 $finish;
wire w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ;
reg r, rw ;
reg error;
// z <- (z) = z
assign ww = w ; // z <- (z) = z
assign wr = r ; // x <- (z) = x
assign w1 = 'b1 ; // 1 <- (z) = 1
assign wwr = w & r ; // x <- z & x
assign ww1 = w & 'b1 ; // x <- z & 1
assign wr1 = r & 'b1 ; // x <- x & 1
assign wwro= w | r ; // x <- z | x
assign ww1o= w | 'b1 ; // 1 <- z | 1
assign wr1o= r | 'b1 ; // 1 <- x | 1
always @(posedge clk)
rw <= w ; // x <- (x) = z
always @(posedge clk)
begin
#1;
$display("%b %b %b %b %b %b %b : %b %b %b : %b %b",
w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw );
end
initial
begin
error = 0;
#19;
if(ww !== 1'bz) begin
error = 1;
$display("FAILED - ww s/b z, is %h",ww);
end
if(wr !== 1'bx) begin
error = 1;
$display("FAILED - wr s/b x, is %h",wr);
end
if(w1 !== 1'b1) begin
error = 1;
$display("FAILED - wr s/b 1, is %h",wr);
end
if(wwr !== 1'bx) begin
error = 1;
$display("FAILED - wwr s/b x, is %h",wwr);
end
if(ww1 !== 1'bx) begin
error = 1;
$display("FAILED - ww1 s/b x, is %h",ww1);
end
if(wr1 !== 1'bx) begin
error = 1;
$display("FAILED - wr1 s/b x, is %h",wr1);
end
if(wwro !== 1'bx) begin
error = 1;
$display("FAILED - wwro s/b 1, is %h",wwro);
end
if(wr1o !== 1'b1) begin
error = 1;
$display("FAILED - wr1o s/b 1, is %h",wr1o);
end
if(r !== 1'bx) begin
error = 1;
$display("FAILED - r s/b x, is %h",r);
end
if(r !== 1'bx) begin
error = 1;
$display("FAILED - r s/b x, is %h",r);
end
if(rw !== 1'bz) begin
error = 1;
$display("FAILED - rw s/b z, is %h",r);
end
if(error === 0)
$display("PASSED");
$finish;
end
endmodule
// *Initial Value Test*
// expected output - This according to XL
// z z x 1 x x x : x 1 1 : x x
// z z x 1 x x x : x 1 1 : x z
// ivl current result
// z z x 1 x z x : x 1 1 : x x
// z z x 1 x z x : x 1 1 : x z
|
#include <bits/stdc++.h> template <class T> void rd(T &x) { x = 0; int f = 1; char c; while (!isdigit(c = getchar())) if (c == - ) f = -1; do { x = (x << 3) + (x << 1) + (c ^ 48); } while (isdigit(c = getchar())); x *= f; } using namespace std; const int N = 1e5 + 5; int n, dp[N], s[N], p[N], cnt, tp; map<int, int> Map[N]; int main() { rd(n); for (int i = 1; i <= n; i++) { int v, c, l, r; rd(v), rd(c), rd(l), rd(r); if (r + c <= 1e5 && (!l || Map[l].find(r + c) != Map[l].end())) { int t = Map[l][r + c]; dp[i] = dp[t] + v; p[i] = t; if (!r && dp[i] > dp[tp]) tp = i; if (dp[i] > dp[Map[l + c][r]]) Map[l + c][r] = i; } } while (tp) s[++cnt] = tp, tp = p[tp]; printf( %d n , cnt); for (; cnt > 0; cnt--) printf( %d , s[cnt]); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool p[10000001]; long h[10000001]; struct S { long a, c; } s[1000000]; int n; int k; long a[1000001]; int binl(int x) { if (x == 2) return 0; if (x > s[k - 1].a) return -1; int mid = (0 + k - 1) / 2; int l = 0, r = k - 1; while (l <= r) { mid = (l + r) / 2; if (s[mid].a >= x && s[mid - 1].a < x && mid - 1 >= 0) return mid; else if (s[mid].a < x) l = mid + 1; else r = mid - 1; } return -1; } int binr(int x) { if (x >= s[k - 1].a) return k - 1; int mid = (0 + k - 1) / 2; int l = 0, r = k - 1; while (l <= r) { mid = (l + r) / 2; if (s[mid].a <= x && s[mid + 1].a > x && mid + 1 < k) return mid; else if (s[mid].a < x) l = mid + 1; else r = mid - 1; } return -1; } int main() { ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; h[a[i]]++; } for (int i = 2; i <= 10000000; i++) { if (p[i] == 0) { s[k].a = i; s[k].c = 0; for (int j = i; j <= 10000000; j += i) { p[j] = 1; s[k].c += h[j]; } k++; } } for (int i = 1; i < k; i++) s[i].c += s[i - 1].c; int m; long long l, r, ans; cin >> m; while (m--) { cin >> l >> r; int ll = binl(l); int rr = binr(r); if (ll == -1) { cout << 0 << endl; continue; } cout << s[rr].c - ((ll > 0) ? s[ll - 1].c : 0) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string second; cin >> second; map<string, string> mp1; for (int i = 0; i < 10; i++) { string s1; cin >> s1; mp1[s1] = to_string(i); } string p = ; string ans = ; for (int i = 0; i < second.length(); i++) { if (i % 10 == 0) { p = ; } p += second[i]; if (i % 10 == 9) if (p.length() != 0) ans += mp1[p]; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-13; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; int k = n / m; vector<int> v(n); vector<vector<int>> d(m); for (int i = 0; i < (int)(n); ++i) { cin >> v[i]; d[v[i] % m].push_back(i); } long long ans = 0; vector<pair<int, int>> free; for (int i = 0; i < (int)(2 * m); ++i) { int cur = i % m; while (d[cur].size() > k) { free.push_back(make_pair(d[cur].back(), i)); d[cur].pop_back(); } while (d[cur].size() < k && !free.empty()) { d[cur].push_back(free.back().first); v[free.back().first] += i - free.back().second; ans += i - free.back().second; free.pop_back(); } } cout << ans << n ; for (auto x : v) cout << x << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 99999997; const int mmax = 200010; const double eps = 1e-8; const double pi = acos(-1.0); const int inf = 0x3fffffff; int a[200010], b[200010]; int main() { int n, m, sa, sb; int cnt1, cnt2, df; while (cin >> n) { for (int i = 0; i < n; i++) scanf( %d , &a[i]); cin >> m; for (int i = 0; i < m; i++) scanf( %d , &b[i]); sort(a, a + n); sort(b, b + m); sa = 3 * n, sb = 3 * m; df = sa - sb; cnt1 = 0, cnt2 = 0; while (cnt1 < n && cnt2 < m) { if (a[cnt1] == b[cnt2]) cnt1++, cnt2++; else if (a[cnt1] < b[cnt2]) { df -= 1; cnt1++; } else { df += 1; if (df > sa - sb) { sa = 2 * cnt1 + 3 * (n - cnt1); sb = 2 * (cnt2 + 1) + 3 * (m - cnt2 - 1); } cnt2++; } } if (2 * n - 2 * m > sa - sb) sa = 2 * n, sb = 2 * m; cout << sa << : << sb << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void run(); int main() { ios::sync_with_stdio(0); cout.precision(10); run(); } struct vec2 { int x, y, sum; vec2 *c, *rgb; inline bool operator<(vec2 const &a) const { return x < a.x or x == a.x and y < a.y; } }; int yc[1000002], n; struct thingy { vec2 *things; int n, pivot; thingy *l, *r; thingy(vec2 *u, vec2 *v) { pivot = u[rand() % (n = (v - u))].y; auto a = u, b = v - 1, c = b; while (a <= b) if (b->y == pivot) swap(a++[0], b[0]); else --b; for (sort(u, b = a); b < c;) { while (b < c and b->y < pivot) ++b; while (b < c and c->y > pivot) --c; if (b < c) swap(*b, *c); } while (b < v and b->y < pivot) ++b; l = (a < b ? new thingy(a, b) : nullptr); r = (b < v ? new thingy(b, v) : nullptr); int sum = 0; vec2 *last[2] = {}; things = new vec2[n]; for (int i = 0, j = 0, k = 0, t = 0; t < n; ++t) { vec2 &from = (i < (a - u) and (j == b - a or u[i] < l->things[j]) and (k == v - b or u[i] < r->things[k]) ? u[i++] : j < (b - a) and (k == v - b or l->things[j] < r->things[k]) ? l->things[j++] : r->things[k++]); things[t] = {from.x, from.y, sum += (from.y <= pivot), &from, max((from.y <= pivot ? last[1] : nullptr), (from.y >= pivot ? last[0] : nullptr))}; if (things[t].y != pivot) last[pivot < things[t].y] = things + t; } } int query(int x, int y) const { vec2 *a = things - 1, *b = things + n; while (a + 1 < b) { vec2 *m = a + (b - a) / 2; (m->x <= x ? a : b) = m; } if (a < things) return 0; thingy const *on = this; int res = 0; while (a and on) { if (on->pivot <= y) res += a->sum; if (y == on->pivot) return res; while (a and (a->y == on->pivot or (a->y < on->pivot) != (y < on->pivot))) a = a->rgb; if (a) on = (y < on->pivot ? on->l : on->r), a = a->c; } return res; } ~thingy() { delete things; delete l; delete r; } }; vec2 v[100002]; void run() { int worth[9]; cin >> n; for (int i = n; i--;) cin >> v[i].x >> v[i].y, yc[i] = v[i].y; sort(yc, yc + n); yc[n] = 1 << 30; for (int i = 9; i--;) cin >> worth[i]; sort(worth, worth + 9); thingy data(v, v + n); sort(v, v + n); v[n].x = 1 << 30; do { int sx[3] = {}, sy[3] = {}, si[3] = {}, sj[3] = {}; for (int i = 9; i--;) si[i / 3] += worth[i], sj[i % 3] += worth[i]; for (int i = 0; i < 2; i++) si[i + 1] += si[i], sj[i + 1] += sj[i]; for (int i = 3; i--;) si[i]--, sj[i]--; if ((sx[0] = v[si[0]].x) == v[si[0] + 1].x) continue; if ((sx[1] = v[si[1]].x) == v[si[1] + 1].x) continue; if ((sy[0] = yc[sj[0]]) == yc[sj[0] + 1]) continue; if ((sy[1] = yc[sj[1]]) == yc[sj[1] + 1]) continue; sx[2] = sy[2] = 1 << 30; int u = data.query(sx[0], sy[0]); if (u - 0 != worth[0]) continue; int v = data.query(sx[1], sy[0]); if (v - u != worth[3]) continue; int w = data.query(sx[2], sy[0]); if (w - v != worth[6]) continue; int a = data.query(sx[0], sy[1]); if (a - 0 != worth[0] + worth[1]) continue; int b = data.query(sx[1], sy[1]); if (b - a != worth[3] + worth[4]) continue; int c = data.query(sx[2], sy[1]); if (c - b != worth[6] + worth[7]) continue; long double ra = sx[0] + 0.5, rb = sx[1] + 0.5, rc = sy[0] + 0.5, rd = sy[1] + 0.5; cout << ra << << rb << n << rc << << rd << endl; return; } while (next_permutation(worth, worth + 9)); cout << -1 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_1_V
`define SKY130_FD_SC_LP__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_1_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
//
module main ();
reg [7:0] array [7:0];
reg error ;
reg [3:0] count;
initial
begin
for(count = 0; count <= 7; count = count + 1)
begin
array[count] = 1 << count;
end
$writememh("work/writememh2.dat", array, 6, 1);
for(count = 0; count <= 7; count = count + 1)
begin
array[count] = 'bx;
end
error = 0;
$readmemh("work/writememh2.dat", array);
for(count = 0; count <= 5; count = count + 1)
begin
if(array[count] !== (1<<(6-count)))
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count], 1 << count);
end
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MAXN = 100010; int N; int A[MAXN]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> N; for (int i = 0; i < N; i++) { cin >> A[i]; } ll ans = 0; for (int i = 0; i < N; i++) { ans += ll(A[i]) * (N + 1 - A[i]); } for (int i = 0; i < N - 1; i++) { ans -= ll(min(A[i], A[i + 1])) * (N + 1 - max(A[i], A[i + 1])); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 21; int cnt, u; int sz[1 << MAXN], g[1 << MAXN], p[1 << MAXN]; long long int f[1 << MAXN], h[1 << MAXN]; inline long long int read() { register long long int num = 0, neg = 1; register char ch = getchar(); while (!isdigit(ch) && ch != - ) { ch = getchar(); } if (ch == - ) { neg = -1; ch = getchar(); } while (isdigit(ch)) { num = (num << 3) + (num << 1) + (ch - 0 ); ch = getchar(); } return num * neg; } int main() { cnt = read(); for (register int i = 0; i < cnt; i++) { if (!(f[i] = read())) { i--, cnt--; } } for (register int i = 1; i < (1 << cnt); i++) { sz[i] = sz[i >> 1] + (i & 1); for (register int j = 0; j < cnt; j++) { if ((i >> j) & 1) { h[i] += f[j]; } } if ((h[i] + sz[i] & 1)) { for (register int j = i; (j = ((j - 1) & i)) && !p[i];) { if (h[i] - sz[i] + 1 <= 2 * h[j] && 2 * h[j] <= h[i] + sz[i] - 1) { p[i] = 1; } } } } for (register int i = 1; i < (1 << cnt); i++) { if (p[i] && !g[i]) { g[i] = 1, u = (1 << cnt) - i - 1; for (register int j = u; j; j = (j - 1) & u) { g[i | j] = max(g[i | j], g[j] + 1); } } } printf( %d n , cnt - g[(1 << cnt) - 1]); }
|
#include <bits/stdc++.h> using namespace std; const int mx = 1e3 + 100, M = 1e9 + 7; long long int n, m, d[mx][mx]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; d[0][0] = 1; for (int i = 1; i < mx; i++) { d[i][0] = 1; for (int j = 1; j < i + 1; j++) d[i][j] = (d[i - 1][j - 1] + d[i - 1][j]) % M; } cout << d[(m * 2) + (n - 1)][(n - 1)] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n = 0; cin >> n; string s; cin >> s; int pos = 0; vector<int> v(n); int flag = 1; for (int i = 0; i < n; i++) { cin >> v[i]; } for (int i = 0; i < n; i++) { if (s[pos] == > ) { pos += v[pos]; } else { pos -= v[pos]; } if (pos < 0 || pos > n - 1) { cout << FINITE ; flag = 0; break; } } if (flag == 1) { cout << INFINITE ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_PP_BLACKBOX_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 1; i <= n; i++) cin >> arr[i]; int ans = 0, ct0 = 0, ct1; for (int i = 1; i <= n; i++) { if (arr[i] == 1) { ct1 = 0; for (int j = i; j <= n; j++) { if (arr[j] == 1) { ct1 += 1; } } ans = max(ans, ct0 + ct1); } else { ct0 += 1; ans = max(ans, ct0); } } cout << ans << endl; }
|
`include "defines.v"
`timescale 1ns/1ps
module openmips_min_sopc_tb();
reg CLOCK_50;
reg rst;
integer file_output;
initial begin
file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst= `RstDisable;
#100000 $stop;
end
openmips_min_sopc openmips_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
always@(posedge CLOCK_50) begin
$fdisplay(file_output,"pc = %h", openmips_min_sopc0.openmips0.id0.pc_i);
$fdisplay(file_output,"instr = %h", openmips_min_sopc0.openmips0.id0.inst_i);
$fdisplay(file_output,"regfiles0 = %h", openmips_min_sopc0.openmips0.regfile1.regs[0]);
$fdisplay(file_output,"regfiles1 = %h", openmips_min_sopc0.openmips0.regfile1.regs[1]);
$fdisplay(file_output,"regfiles2 = %h", openmips_min_sopc0.openmips0.regfile1.regs[2]);
$fdisplay(file_output,"regfiles3 = %h", openmips_min_sopc0.openmips0.regfile1.regs[3]);
$fdisplay(file_output,"regfiles4 = %h", openmips_min_sopc0.openmips0.regfile1.regs[4]);
$fdisplay(file_output,"regfiles5 = %h", openmips_min_sopc0.openmips0.regfile1.regs[5]);
$fdisplay(file_output,"regfiles6 = %h", openmips_min_sopc0.openmips0.regfile1.regs[6]);
$fdisplay(file_output,"regfiles7 = %h", openmips_min_sopc0.openmips0.regfile1.regs[7]);
$fdisplay(file_output,"regfiles8 = %h", openmips_min_sopc0.openmips0.regfile1.regs[8]);
$fdisplay(file_output,"regfiles9 = %h", openmips_min_sopc0.openmips0.regfile1.regs[9]);
$fdisplay(file_output,"regfiles10 = %h", openmips_min_sopc0.openmips0.regfile1.regs[10]);
$fdisplay(file_output,"regfiles11 = %h", openmips_min_sopc0.openmips0.regfile1.regs[11]);
$fdisplay(file_output,"regfiles12 = %h", openmips_min_sopc0.openmips0.regfile1.regs[12]);
$fdisplay(file_output,"regfiles13 = %h", openmips_min_sopc0.openmips0.regfile1.regs[13]);
$fdisplay(file_output,"regfiles14 = %h", openmips_min_sopc0.openmips0.regfile1.regs[14]);
$fdisplay(file_output,"regfiles15 = %h", openmips_min_sopc0.openmips0.regfile1.regs[15]);
$fdisplay(file_output,"regfiles16 = %h", openmips_min_sopc0.openmips0.regfile1.regs[16]);
$fdisplay(file_output,"regfiles17 = %h", openmips_min_sopc0.openmips0.regfile1.regs[17]);
$fdisplay(file_output,"regfiles18 = %h", openmips_min_sopc0.openmips0.regfile1.regs[18]);
$fdisplay(file_output,"regfiles19 = %h", openmips_min_sopc0.openmips0.regfile1.regs[19]);
$fdisplay(file_output,"regfiles20 = %h", openmips_min_sopc0.openmips0.regfile1.regs[20]);
$fdisplay(file_output,"regfiles21 = %h", openmips_min_sopc0.openmips0.regfile1.regs[21]);
$fdisplay(file_output,"regfiles22 = %h", openmips_min_sopc0.openmips0.regfile1.regs[22]);
$fdisplay(file_output,"regfiles23 = %h", openmips_min_sopc0.openmips0.regfile1.regs[23]);
$fdisplay(file_output,"regfiles24 = %h", openmips_min_sopc0.openmips0.regfile1.regs[24]);
$fdisplay(file_output,"regfiles25 = %h", openmips_min_sopc0.openmips0.regfile1.regs[25]);
$fdisplay(file_output,"regfiles26 = %h", openmips_min_sopc0.openmips0.regfile1.regs[26]);
$fdisplay(file_output,"regfiles27 = %h", openmips_min_sopc0.openmips0.regfile1.regs[27]);
$fdisplay(file_output,"regfiles28 = %h", openmips_min_sopc0.openmips0.regfile1.regs[28]);
$fdisplay(file_output,"regfiles29 = %h", openmips_min_sopc0.openmips0.regfile1.regs[29]);
$fdisplay(file_output,"regfiles30 = %h", openmips_min_sopc0.openmips0.regfile1.regs[30]);
$fdisplay(file_output,"regfiles31 = %h", openmips_min_sopc0.openmips0.regfile1.regs[31]);
end
endmodule
|
module antiDroopIIR_16 (
input clk,
input trig,
input signed [15:0] din,
input signed [6:0] tapWeight,
input accClr_en,
//input oflowClr,
(* shreg_extract = "no" *) output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15).
//`define ADDPIPEREG
(* shreg_extract = "no" *) reg signed [15:0] din_del = 16'sd0;
`ifdef ADDPIPEREG (* shreg_extract = "no" *) reg signed [15:0] din_del_b = 16'sd0;
`endif
reg signed [47:0] tap = 48'sd0;
reg signed [22:0] multreg = 23'sd0;
(* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0;
wire trig_edge = trig_a & ~trig_b;
//reg trig_edge = 1'b0;
(* shreg_extract = "no" *) reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0;
//wire oflow = (^tap[IIR_scale+16:IIR_scale+15]);
wire oflow = (~&tap[47:IIR_scale+15] && ~&(~tap[47:IIR_scale+15]));
always @(posedge clk) begin
//trig_edge <= trig_a & ~trig_b;
tapWeight_a <= tapWeight;
tapWeight_b <= tapWeight_a;
trig_a <= trig;
trig_b <= trig_a;
din_del <= din;
`ifdef ADDPIPEREG
din_del_b <= din_del;
multreg <= din_del*tapWeight_b;
//dout <= din_del_b + tap[IIR_scale+15:IIR_scale];
if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767;
else dout <= din_del_b + tap[IIR_scale+15:IIR_scale];
`else
multreg <= din*tapWeight_b;
//dout <= din_del + tap[IIR_scale+15:IIR_scale];
if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767;
else dout <= din_del + tap[IIR_scale+15:IIR_scale];
`endif
if (trig_edge && accClr_en) tap <= 48'sd0;
else tap <= multreg + tap;
//tap <= din*tapWeight + tap;
//if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
//else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if (^ tap[IIR_scale+16:IIR_scale+15]) oflowDetect <= 1'b1;
//else oflowDetect <= oflowDetect;
//oflowDetect <= (^tap[IIR_scale+16:IIR_scale+15]) ? 1'b1 : 1'b0;
oflowDetect <= oflow;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; long long int inf = -1e15; long long int seg[maxn << 2], lazy[maxn << 2]; int n, m, p; vector<long long int> espadas, armaduras; vector<pair<int, int> > monstros[maxn]; void update(int x, long long int val) { seg[x] += val; lazy[x] += val; } void propaga(int x) { if (!lazy[x]) return; update(x * 2, lazy[x]); update(x * 2 + 1, lazy[x]); lazy[x] = 0; } void add(int i, int j, int x, int l, int r, int val) { if (i >= j || l >= r || i >= r || j <= l) return; if (i >= l && j <= r) { update(x, val); return; } propaga(x); int md = (i + j) >> 1; add(i, md, x * 2, l, r, val); add(md, j, x * 2 + 1, l, r, val); seg[x] = max(seg[x * 2], seg[x * 2 + 1]); } void build(int i, int j, int no) { int l = 2 * no; int r = l + 1; if (i + 1 == j) { if (armaduras[i]) seg[no] = -armaduras[i]; else seg[no] = inf; return; } int mid = (i + j) >> 1; build(i, mid, l); build(mid, j, r); seg[no] = max(seg[l], seg[r]); } int main() { ios_base::sync_with_stdio(0), cin.tie(0); long long int ans = inf; espadas.resize(maxn); armaduras.resize(maxn); cin >> n >> m >> p; int atk, def; long long int gold; for (int i = 1; i <= n; i++) { cin >> atk >> gold; atk--; if (!espadas[atk]) espadas[atk] = gold; else espadas[atk] = min(espadas[atk], gold); } for (int i = 1; i <= m; i++) { cin >> def >> gold; if (!armaduras[def]) armaduras[def] = gold; else armaduras[def] = min(armaduras[def], gold); } build(1, maxn, 1); for (int i = 1; i <= p; i++) { cin >> def >> atk >> gold; monstros[def].push_back(pair<int, int>(atk, gold)); } for (int i = 0; i <= maxn - 1; i++) { for (auto a : monstros[i]) add(1, maxn, 1, a.first + 1, maxn, a.second); if (espadas[i]) ans = max(ans, seg[1] - espadas[i]); } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const double eps = 1e-6; int modpow(int x, int y, int md) { if (y == 0) return 1; int ret = modpow(x, y >> 1, md); ret = (long long)ret * ret % md; if (y & 1) ret = (long long)ret * x % md; return ret; } int n, q, mod; int pws[10][2000001]; long long euclid(long long x, long long y, long long &k, long long &l) { if (y == 0) { k = 1; l = 0; return x; } long long g = euclid(y, x % y, l, k); l -= k * (x / y); return g; } long long rev(long long x) { long long k, l; if (euclid(x, mod, k, l) != 1) throw; k %= mod; if (k < 0) k += mod; return k; } int pr[10], cnt = 0; struct Num { int a[10] = {}; int val = 0; Num operator*(Num b) { Num ret; ret.val = (long long)val * b.val % mod; for (int i = 0; i < cnt; i++) ret.a[i] = a[i] + b.a[i]; return ret; } Num operator+(Num b) { if (val == -1) return b; if (b.val == -1) return *this; Num ret; ret.val = 0; int v2 = val, v1 = b.val; for (int i = 0; i < cnt; i++) { ret.a[i] = min(a[i], b.a[i]); v2 = (long long)v2 * pws[i][a[i] - ret.a[i]] % mod; v1 = (long long)v1 * pws[i][b.a[i] - ret.a[i]] % mod; } ret.val = (v1 + v2) % mod; return ret; } Num inv() { Num ret; ret.val = rev(val); for (int i = 0; i < cnt; i++) { ret.a[i] = -a[i]; } return ret; } int getreallyvalue() { int ret = val; for (int i = 0; i < cnt; i++) ret = (long long)ret * pws[i][a[i]] % mod; return ret; } }; Num sjctxdy(int x) { Num ret; if (x == 0) { ret.val = 0; return ret; } for (int i = 0; i < 10; i++) ret.a[i] = 0; for (int i = 0; i < cnt; i++) { if (x % pr[i] == 0) { while (x % pr[i] == 0) { ret.a[i]++; x /= pr[i]; } } } ret.val = x; return ret; } struct mod_sjc { Num v, mul; void print() { printf( v: %d , v.val); printf( array: ); for (int i = 0; i < cnt; i++) printf( %d%c , v.a[i], i == cnt - 1 ? n : ); printf( mul: %d , mul.val); printf( array: ); for (int i = 0; i < cnt; i++) printf( %d%c , mul.a[i], i == cnt - 1 ? n : ); } } node[131072 * 2]; int sjctql[131072]; struct sjcakioi { void build() { for (int i = 131072; i < 131072 + 131072; i++) node[i] = (mod_sjc){sjctxdy(sjctql[i - 131072]), sjctxdy(1)}; for (int i = 131072 - 1; i >= 1; i--) node[i].v = node[i + i + 1].v + node[i + i].v, node[i].mul = sjctxdy(1); } void pushup(int v) { node[v].v = node[v + v].v + node[v + v + 1].v; } void pushdown(int v) { if (node[v + v + 1].v.val != -1) { node[v + v + 1].mul = node[v + v + 1].mul * node[v].mul; node[v + v + 1].v = node[v + v + 1].v * node[v].mul; } if (node[v + v].v.val != -1) { node[v + v].mul = node[v + v].mul * node[v].mul; node[v + v].v = node[v + v].v * node[v].mul; } node[v].mul = sjctxdy(1); } void AK_init(int k, int l, int r, Num v, int a = 0, int b = 131072 - 1) { if (r < a || b < l) return; if (l <= a && b <= r) { node[k].v = node[k].v * v; node[k].mul = node[k].mul * v; return; } pushdown(k); AK_init(k + k, l, r, v, a, (a + b) >> 1); AK_init(k + k + 1, l, r, v, ((a + b) >> 1) + 1, b); pushup(k); } Num AK(int k, int l, int r, int a = 0, int b = 131072 - 1) { if (r < a || b < l) return sjctxdy(-1); if (l <= a && b <= r) { return node[k].v; } pushdown(k); Num ret = AK(k + k, l, r, a, a + b >> 1) + AK(k + k + 1, l, r, (a + b >> 1) + 1, b); return ret; } } orzsjc; int main() { scanf( %d%d , &n, &mod); int t = mod; for (int i = 2; i * i <= mod; i++) { if (t % i == 0) { pr[cnt++] = i; while (t % i == 0) t /= i; } } if (t != 1) pr[cnt++] = t; for (int i = 0; i < cnt; i++) for (int j = 0; j < 2000000; j++) { pws[i][j] = (j == 0 ? 1 : (long long)pws[i][j - 1] * pr[i] % mod); } for (int i = 0; i < n; i++) scanf( %d , sjctql + i); orzsjc.build(); scanf( %d , &q); while (q--) { int type; scanf( %d , &type); if (type == 1) { int l, r, x; scanf( %d%d%d , &l, &r, &x); orzsjc.AK_init(1, l - 1, r - 1, sjctxdy(x)); } else if (type == 2) { int p, x; scanf( %d%d , &p, &x); orzsjc.AK_init(1, p - 1, p - 1, sjctxdy(x).inv()); } else if (type == 3) { int l, r; scanf( %d%d , &l, &r); printf( %d n , orzsjc.AK(1, l - 1, r - 1).getreallyvalue()); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; struct Node { int a, px, ori, c; } node[N]; int n, l, r; bool cmp_px(Node &a, Node &b) { return a.px < b.px; } bool cmp_ori(Node &a, Node &b) { return a.ori < b.ori; } int main() { cin >> n >> l >> r; int t; for (int i = 0; i < n; i++) { cin >> t; node[i].ori = i; node[i].a = t * (-1); node[i].c = l; } for (int i = 0; i < n; i++) { cin >> t; node[i].px = t; } sort(node, node + n, cmp_px); for (int i = 1; i < n; i++) { if (node[i].a > node[i - 1].a) continue; int cha = node[i - 1].a - node[i].a; node[i].a = node[i].a + cha + 1; node[i].c += cha + 1; if (node[i].c > r) { cout << -1 << endl; return 0; } } { sort(node, node + n, cmp_ori); for (int i = 0; i < n; i++) { cout << node[i].c << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 7; int a[MAXN], n, p, lim = 0; bool check(int val) { for (int i = 1; i <= n; ++i) if (val + i - 1 < a[i]) return 0; return 1; } bool valid(int val) { int sta = 0; for (int i = 0; i < n; ++i) { while (sta + 1 <= n && val + i >= a[sta + 1]) ++sta; if (sta - i >= p) return 0; } return 1; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> p; for (int i = 1; i <= n; ++i) cin >> a[i], lim = max(lim, a[i]); sort(a + 1, a + 1 + n); int l = 0, r = lim, sta = -1; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) sta = mid, r = mid - 1; else l = mid + 1; } l = sta, r = lim; int fin = sta - 1; while (l <= r) { int mid = (l + r) >> 1; if (valid(mid)) fin = mid, l = mid + 1; else r = mid - 1; } cout << fin - sta + 1 << n ; for (int i = sta; i <= fin; ++i) cout << i << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, lam, mx = 0, c = 0; cin >> n; vector<int> cand(n); for (int i = 0; i < n; i++) { cin >> cand[i]; if (mx < cand[i]) mx = cand[i]; } for (int i = 0; i < n; i++) if (mx == cand[i]) c++; int x = lam = cand[0]; if (lam == mx && c > 1) return cout << 1 , 0; if (lam == mx && c == 1) return cout << 0 , 0; sort(cand.begin(), cand.end()); while (lam <= cand[n - 1]) { lam += 1; cand[n - 1] -= 1; sort(cand.begin(), cand.end()); } cout << lam - x; }
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#include <bits/stdc++.h> using namespace std; struct point { double x, y; point operator-(point A) { return (point){x - A.x, y - A.y}; } double operator*(point A) { return x * A.y - y * A.x; } double dis() { return sqrt(x * x + y * y); } } a[1005][1005], t[1005], E[1005]; int n, vis[1005][1005]; double r[1005][1005]; point Mid(point a, point b) { return (point){(a.x + b.x) / 2, (a.y + b.y) / 2}; } double disline(int i, point A) { return abs(E[i] * (A - t[i]) / E[i].dis()); } int ch(int R) { return R % n ? R % n : n; } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %lf%lf , &t[i].x, &t[i].y); for (int i = 1; i <= 2 * n; i++) t[n + i] = t[i]; for (int i = 1; i <= 3 * n; i++) E[i] = t[i + 1] - t[i]; for (int L = 1, R = L + 1, nw = L; L <= n; L++) for (R--, nw = max(L, nw); R == L || E[L] * E[R] > 0.5; R++) { while (nw < R && disline(L, t[nw + 1]) < disline(R, t[nw + 1])) ++nw; point le = t[nw], ri = t[nw + 1]; for (int j = 1; j <= 42; j++) { point mid = Mid(le, ri); if (disline(L, mid) < disline(R, mid)) le = mid; else ri = mid; } point P = Mid(le, ri); a[L][ch(R)] = P; r[L][ch(R)] = max(disline(L, P), disline(R, P)); vis[L][ch(R)] = 1; } double ans = 1e7; point a1, a2; for (int L = 1; L <= n; L++) for (int R = L; R <= L + n; R++) if (vis[L][ch(R)] && vis[ch(R + 1)][ch(L - 1 + n)]) { double newr = max(r[L][ch(R)], r[ch(R + 1)][ch(L - 1 + n)]); if (newr < ans) ans = newr, a1 = a[L][ch(R)], a2 = a[ch(R + 1)][ch(L - 1 + n)]; } printf( %.10f n%.10f %.10f n%.10f %.10f n , ans, a1.x, a1.y, a2.x, a2.y); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_2_V
`define SKY130_FD_SC_LS__NAND4_2_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_2_V
|
#include <bits/stdc++.h> using namespace std; set<pair<int, pair<int, int> > > l, u; set<pair<int, pair<int, int> > >::iterator itu, itl; const int INF = 1000 * 1000 * 1000LL + 10; int main() { int n, q, a, b, ll, lm, lt, uu, um, ut; char c; long long ans; cin >> n >> q; for (int i = 0; i < q; i++) { scanf( %d %d %c , &a, &b, &c); ans = 0; if (c == U ) { l.insert(make_pair(b, make_pair(INF, INF))); u.insert(make_pair(a, make_pair(0, 0))); itl = l.find(make_pair(b, make_pair(INF, INF))); itu = u.find(make_pair(a, make_pair(0, 0))); itu++; if (itl == l.begin()) { ll = 0; lm = 0; lt = q; } else { itl--; ll = (*itl).first; lm = (*itl).second.first; lt = (*itl).second.second; itl++; } if (itu == u.end()) { uu = 0; um = 0; ut = q; } else { uu = n - (*itu).first + 1; um = (*itu).second.first; ut = (*itu).second.second; } itu--; l.erase(itl); u.erase(itu); if (uu > ll || (ll == uu && ut < lt)) { if (uu != b) ans += (um + b - uu); u.insert(make_pair(a, make_pair(um + b - uu, i + 1))); } else { ans += (b - ll); u.insert(make_pair(a, make_pair(b - ll, i + 1))); } } else { l.insert(make_pair(b, make_pair(0, 0))); u.insert(make_pair(a, make_pair(INF, INF))); itl = l.find(make_pair(b, make_pair(0, 0))); itu = u.find(make_pair(a, make_pair(INF, INF))); itl++; if (itl == l.end()) { ll = n + 1; lm = 0; lt = q; } else { ll = (*itl).first; lm = (*itl).second.first; lt = (*itl).second.second; } if (itu == u.begin()) { uu = n + 1; um = 0; ut = q; } else { itu--; uu = n - (*itu).first + 1; um = (*itu).second.first; ut = (*itu).second.second; itu++; } itl--; l.erase(itl); u.erase(itu); if (uu > ll || (ll == uu && ut > lt)) { if (ll != b) ans += (lm + ll - b); l.insert(make_pair(b, make_pair(lm + ll - b, i + 1))); } else { ans += (uu - b); l.insert(make_pair(b, make_pair(uu - b, i + 1))); } } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << n ; err(++it, args...); } const int MOD = 1e9 + 7, N = 2e5 + 5, B = 32; vector<int> g[N]; vector<int> inv(N); map<pair<int, int>, int> mp; map<int, vector<int>> mpans; void dfs(int u, int p) { for (auto v : g[u]) { if (v == p) continue; if (mp[{u, v}]) inv[v] += 1; dfs(v, u); inv[u] += inv[v]; } } void dfs1(int u, int p, int temp) { mpans[temp].push_back(u); for (auto v : g[u]) { if (v == p) continue; int v1; if (mp[{u, v}]) v1 = -1; else v1 = 1; dfs1(v, u, temp + v1); } } void solve() { int n; cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; mp[{x, y}] = 0; mp[{y, x}] = 1; g[x].push_back(y); g[y].push_back(x); } dfs(1, 0); dfs1(1, 0, inv[1]); auto xx = *mpans.begin(); cout << xx.first << n ; sort(xx.second.begin(), xx.second.end()); for (auto r : xx.second) cout << r << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; solve(); }
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