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/******************************************************************************
* (C) Copyright 2019 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* MODULE: BLOG
* PROJECT: How To Connect e-Language with Python
* Description: This is a code snippet from the Blog article mentioned on PROJECT
* Link: https://www.amiq.com/consulting/2019/04/25/how-to-connect-e-language-with-python/
*******************************************************************************/
module amiq_mux2_1(input clk, input sel, input in0, input in1, output reg out);
initial out=0;
always@(posedge clk) begin
out<=sel?in1:in0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 35; const int MOD = 1e9 + 7; long long n; int K, c, res; struct mat { int d[N][N]; mat() { memset(d, 0, sizeof d); } } F[N * 2][N], P[N * 2][N], Q[N * 2][N], G; int lst[N * 2]; mat operator*(mat a, mat b) { mat c; for (int i = 0; i <= K; ++i) for (int j = 0; j <= K; ++j) for (int k = 0; k <= K; ++k) c.d[i][k] = (c.d[i][k] + 1ll * a.d[i][j] * b.d[j][k]) % MOD; return c; } int main() { cin >> n >> K; while (n) lst[c++] = n % K, n /= K; for (int i = 0; i < c; ++i) { if (i == 0) { for (int j = 0; j < K; ++j) { for (int p = 0; p < K; ++p) F[i][j].d[p][p] = 1; for (int p = 0; p <= K; ++p) F[i][j].d[j][p] = 1; F[i][j].d[K][K] = 1; } } else { for (int j = 1; j < K; ++j) F[i][j] = Q[i - 1][j] * P[i - 1][j - 1]; F[i][0] = Q[i - 1][0]; } P[i][0] = F[i][0]; for (int j = 1; j < K; ++j) P[i][j] = P[i][j - 1] * F[i][j]; Q[i][K - 1] = F[i][K - 1]; for (int j = K - 2; ~j; --j) Q[i][j] = F[i][j] * Q[i][j + 1]; } for (int i = 0; i <= K; ++i) G.d[i][i] = 1; for (int i = c - 1, s = 0; ~i; --i) { for (int j = 0; j < lst[i]; ++j) G = G * F[i][(s + j) % K]; s = (s + lst[i]) % K; } res = 1; for (int i = 0; i < K; ++i) res = (res + G.d[i][K]) % MOD; cout << res << endl; }
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* in byte_num out
* 0x11223344 0 0x01000000
* 0x11223344 1 0x11010000
* 0x11223344 2 0x11220100
* 0x11223344 3 0x11223301
*/
module padder1(in, byte_num, out);
input [31:0] in;
input [1:0] byte_num;
output reg [31:0] out;
always @ (*)
case (byte_num)
0: out = 32'h1000000;
1: out = {in[31:24], 24'h010000};
2: out = {in[31:16], 16'h0100};
3: out = {in[31:8], 8'h01};
endcase
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Sat Jun 27 17:24:12 2015
//Host : debian-Miska running 64-bit Debian GNU/Linux 7.8 (wheezy)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gps_rx,
gps_tx,
gsm_rx,
gsm_tx,
ov7670_data,
ov7670_href,
ov7670_pclk,
ov7670_pwdn,
ov7670_reset,
ov7670_scl,
ov7670_sda,
ov7670_vsync,
ov7670_xclk);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input gps_rx;
output gps_tx;
input gsm_rx;
output gsm_tx;
input [7:0]ov7670_data;
input ov7670_href;
input ov7670_pclk;
output ov7670_pwdn;
output ov7670_reset;
output ov7670_scl;
inout ov7670_sda;
input ov7670_vsync;
output ov7670_xclk;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire gps_rx;
wire gps_tx;
wire gsm_rx;
wire gsm_tx;
wire [7:0]ov7670_data;
wire ov7670_href;
wire ov7670_pclk;
wire ov7670_pwdn;
wire ov7670_reset;
wire ov7670_scl;
wire ov7670_sda;
wire ov7670_vsync;
wire ov7670_xclk;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.gps_rx(gps_rx),
.gps_tx(gps_tx),
.gsm_rx(gsm_rx),
.gsm_tx(gsm_tx),
.ov7670_data(ov7670_data),
.ov7670_href(ov7670_href),
.ov7670_pclk(ov7670_pclk),
.ov7670_pwdn(ov7670_pwdn),
.ov7670_reset(ov7670_reset),
.ov7670_scl(ov7670_scl),
.ov7670_sda(ov7670_sda),
.ov7670_vsync(ov7670_vsync),
.ov7670_xclk(ov7670_xclk));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__CLKMUX2_FUNCTIONAL_PP_V
/**
* clkmux2: Clock mux.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__clkmux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_FUNCTIONAL_PP_V
|
`include "../src/registers.v"
`include "../src/reg_interface.v"
`include "../src/clock.v"
module test_registros;
wire clk;
reg reset, ir_ri0_enb, ir_ri1_enb, ir_ri2_enb;
wire [7:0] ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data;
reg [7:0] ir_ri0_in_data, ir_ri0_address, ir_ri1_in_data, ir_ri1_address, ir_ri2_in_data, ir_ri2_address;
clock c(clk);
REG_INTERFACE reg_interface(ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data, ir_ri0_address, ir_ri1_address, ir_ri2_address, ir_ri0_in_data, ir_ri1_in_data, ir_ri2_in_data, ir_ri0_enb, ir_ri1_enb, ir_ri2_enb, reset, clk);
initial
begin
$dumpfile("test_registros.vcd");
$dumpvars;
reset=1;
#`PERIODO reset=0;
ir_ri0_enb=0;
ir_ri1_enb=0;
ir_ri2_enb=1;
ir_ri0_address=8'h00;
ir_ri1_address=8'h6F;
ir_ri2_address=8'h00;
ir_ri0_in_data=8'h00;
ir_ri1_in_data=8'h3F;
ir_ri2_in_data=8'h00;
while(ir_ri0_in_data< 8'h06)
begin
ir_ri0_address=0;
ir_ri1_address=8'h30;
while(ir_ri0_address<8'h20)
begin
#`PERIODO ir_ri0_address=ir_ri0_address+1;
ir_ri1_address=ir_ri1_address-1;
end
#`PERIODO ir_ri0_in_data=ir_ri0_in_data+1;
ir_ri1_in_data=ir_ri1_in_data-1;
end
reset=1;
#`PERIODO $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<long double, long double> A[200666]; int st[200666], ind[200666]; long double val[200666]; bool comp(int i1, int i2) { return A[i1] < A[i2]; } bool eql(long double v1, long double v2) { return (v1 - v2 > -((long double)0.00000000000001) && v1 - v2 < ((long double)0.00000000000001)); } long double bs(long double vmax, pair<long double, long double> v1, pair<long double, long double> v2) { long double pos, step; for (step = 1; step <= vmax; step *= (long double)2.0) ; for (pos = 0; step > ((long double)0.0000000000000000001); step /= (long double)2.0) if (pos + step <= vmax) { long double val_1 = 1.0 / v1.first + (pos + step) / (v1.second); long double val_2 = 1.0 / v2.first + (pos + step) / (v2.second); if (val_2 < val_1 || eql(val_2, val_1)) pos += step; } return pos; } int main() { int n, i; scanf( %d , &n); for (i = 1; i <= n; ++i) { int v1, v2; scanf( %d%d , &v1, &v2); A[i].first = v1; A[i].second = v2; ind[i] = i; } sort(ind + 1, ind + n + 1, comp); int k = 1; st[1] = ind[1]; val[1] = ((long double)1000000000000000); for (i = 2; i <= n; ++i) { int l = ind[i]; while (true && k > 0) { long double v1 = 1.0 / A[st[k]].first + val[k] / (A[st[k]].second); long double v2 = 1.0 / A[l].first + val[k] / (A[l].second); if (eql(v1, v2)) break; if (v2 < v1) { --k; continue; } break; } if (k == 0) { st[++k] = l; continue; } st[++k] = l; val[k] = bs(val[k - 1], A[st[k - 1]], A[l]); } sort(st + 1, st + k + 1); for (i = 1; i <= k; ++i) cout << st[i] << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_1_V
`define SKY130_FD_SC_HS__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxbp_1 (
CLK ,
D ,
Q ,
Q_N ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dfxbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxbp_1 (
CLK,
D ,
Q ,
Q_N
);
input CLK;
input D ;
output Q ;
output Q_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfxbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_1_V
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [12:0] c;
// Output of stage 2
wire [12:0] cx;
// Output of stage 3
wire [7:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [7:0] b;
reg [7:0] r_b;
reg [12:0] e;
reg [12:0] r_e;
// 2nd stage
reg [12:0] r_c;
reg [12:0] rr_e;
reg [7:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [12:0] cx;
//reg [10:0] qx;
reg [12:0] r_qx;
reg [7:0] rb;
reg clk,reset;
reg [12:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 13'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0001000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 13'b0000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// "unpacked_packed.v"
// testing element-by-element repacking of arrays
// repacking is a workaround to some bug that prevents bus-declared
// input ports (e.g. input X [1:0]) from propagating to prsim (cosim) properly.
// Workaround is implemented in wrap_verilog_modules_to_hacprsim.awk.
// See multidimensional.v.
// @vcs-flags@ -P pli.tab -sverilog
// -sverilog to support multidimensional arrays
`timescale 1ps / 1ps
`include "clkgen.v"
//-----------------------------------------------------------------------------
module _timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module ar1(
input wire [3:0] A[1:0][2:0],
output wire [3:0] B[1:0][2:0]
);
assign B = A;
endmodule
module ar2(
input wire [2:0][3:0] A[1:0],
output wire [2:0][3:0] B[1:0]
);
// ar1 foo(A); // works? no
ar1 foo();
genvar i, j, k;
for (i=0; i<2; ++i) begin : i_loop
for (j=0; j<3; ++j) begin : j_loop
for (k=0; k<4; ++k) begin : k_loop
assign foo.A[i][j][k] = A[i][j][k];
assign B[i][j][k] = foo.B[i][j][k];
end
end
end
endmodule
module ar3(
input wire [1:0][2:0][3:0] A,
output wire [1:0][2:0][3:0] B
);
// ar1 foo(A); // works? no, mismatched arrays
ar2 foo();
genvar i, j, k;
for (i=0; i<2; ++i) begin : i_loop
for (j=0; j<3; ++j) begin : j_loop
for (k=0; k<4; ++k) begin : k_loop
assign foo.A[i][j][k] = A[i][j][k];
assign B[i][j][k] = foo.B[i][j][k];
end
end
end
endmodule
module TOP;
wire clk;
wire z;
clk_gen #(.HALF_PERIOD(50)) cg(clk);
ar3 d2();
assign d2.A[1][2][3] = clk; // works (swizzle)
assign z = d2.B[1][2][3];
initial
begin
$display("$start of simulation");
#850 $finish;
end
always @(clk)
begin
$display("at time %7.3f, observed clk = %b", $realtime, clk);
end
always @(z)
begin
$display("at time %7.3f, observed z = %b", $realtime, z);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 1; vector<int> g[maxn]; int n, m, k, num[maxn], pre[maxn], maxx = 0, flag = 0; void dfs(int u, int fa, int deep) { num[u] = deep; pre[u] = fa; for (int to : g[u]) { if (flag) return; if (to == fa) continue; if (num[to] > 0) { if (num[u] - num[to] + 1 >= k + 1) { printf( %d n , num[u] - num[to] + 1); while (u != to) { printf( %d , u); u = pre[u]; } printf( %d , to); flag = 1; return; } continue; } dfs(to, u, deep + 1); } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1, u, v; i <= m; ++i) { scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } dfs(1, 0, 1); }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module conflict_dsp_ctrl_param (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z,
);
wire [17:0] z;
always @(posedge CLK)
Z <= z;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("REGISTER")
) mult (
.A (A),
.B (B),
.Z (z)
);
endmodule
module conflict_dsp_common_param (
input wire CLK,
input wire RST,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z,
);
wire [8:0] ra;
always @(posedge CLK or posedge RST)
if (RST) ra <= 0;
else ra <= A;
wire [8:0] rb;
always @(posedge CLK)
if (RST) rb <= 0;
else rb <= B;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (rb),
.Z (Z)
);
endmodule
module conflict_ff_param (
input wire CLK,
input wire RST,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z,
);
wire [8:0] ra;
always @(posedge CLK or posedge RST)
if (RST) ra[8:4] <= 0;
else ra[8:4] <= A[8:4];
always @(posedge CLK)
if (RST) ra[3:0] <= 0;
else ra[3:0] <= A[3:0];
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07.01.2017 17:22:31
// Design Name:
// Module Name: freq_count_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module freq_count_sim();
reg clk = 0;
reg [31:0] Ncycles = 2;
reg [31:0] data_in = 0;
wire [31:0] out;
wire [31:0] data_out;
wire valid_out;
frequency_counter fc (.S_AXIS_IN_tdata(data_in),
.S_AXIS_IN_tvalid(1'b1),
.clk(clk),
.rst(1'b1),
.Ncycles(Ncycles),
.M_AXIS_OUT_tdata(data_out),
.M_AXIS_OUT_tvalid(valid_out),
.counter_output(out)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
//declare the sine ROM - 30 registers each 8 bit wide.
reg signed [31:0] sine [0:29];
//Internal signals
integer i;
//Initialize the sine rom with samples.
initial begin
i = 0;
sine[0] = 0;
sine[1] = 16;
sine[2] = 31;
sine[3] = 45;
sine[4] = 58;
sine[5] = 67;
sine[6] = 74;
sine[7] = 77;
sine[8] = 77;
sine[9] = 74;
sine[10] = 67;
sine[11] = 58;
sine[12] = 45;
sine[13] = 31;
sine[14] = 16;
sine[15] = 0;
sine[16] = -16;
sine[17] = -31;
sine[18] = -45;
sine[19] = -58;
sine[20] = -67;
sine[21] = -74;
sine[22] = -77;
sine[23] = -77;
sine[24] = -74;
sine[25] = -67;
sine[26] = -58;
sine[27] = -45;
sine[28] = -31;
sine[29] = -16;
end
//At every positive edge of the clock, output a sine wave sample.
always@ (posedge(clk))
begin
data_in = 10*sine[i];
i = i + 1;
if(i == 30)
i = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_M_V
`define SKY130_FD_SC_LP__NAND4_M_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_m (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4_m (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_M_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T abs(T a) { return ((a < 0) ? -a : a); } template <typename T> inline T sqr(T a) { return a * a; } const int INF = (int)1E9 + 7; const long double EPS = 1E-10; const long double PI = 3.1415926535897932384626433832795; int n; vector<long double> a; bool check(const vector<long double>& a) { if (int((a).size()) <= 1) return true; if (fabs(a[0]) < EPS) { for (int i = 0; i < int(int((a).size())); ++i) if (fabs(a[i]) > EPS) return false; return true; } long double b = a[1] / a[0], cur = a[0]; for (int i = 0; i < int(int((a).size())); ++i) { if (fabs(a[i] - cur) > EPS) return false; cur *= b; } return true; } vector<int> getz(const vector<long double>& a) { vector<int> z(int((a).size())); int l = 0, r = -1; for (int i = int(1); i < int(int((a).size())); ++i) { z[i] = i > r ? 0 : min(z[i - l], r - i + 1); while (i + z[i] < int((a).size()) && fabs(a[z[i]] - a[i + z[i]]) < EPS) z[i]++; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; } return z; } int main() { cin >> n; a.resize(n); for (int i = 0; i < int(n); ++i) { int x; scanf( %d , &x); a[i] = x; } if (check(a)) { puts( 0 ); exit(0); } for (int i = 0; i < int(2); ++i) { vector<long double> b = a; b.erase(b.begin() + i); if (check(b)) { puts( 1 ); exit(0); } } vector<long double> ok(n - 1, 0); if (fabs(a[0]) > EPS) { long double d = a[1] / a[0]; ok[0] = a[0], ok[1] = a[1]; for (int i = int(2); i < int(int((ok).size())); ++i) ok[i] = ok[i - 1] * d; } vector<long double> t1 = ok; t1.insert(t1.end(), (a).begin(), (a).end()); vector<int> z1 = getz(t1); reverse((ok).begin(), (ok).end()); reverse((a).begin(), (a).end()); ok.insert(ok.end(), (a).begin(), (a).end()); vector<int> z2 = getz(ok); if (z1[n - 1] + z2[n - 1] >= n - 1) puts( 1 ); else puts( 2 ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[105]; bool visited[105]; int df[1005]; int ans = 0, k = 0; void dfs(int i, int parent) { visited[i] = true; for (int j = 0; j < adj[i].size(); j++) { if (!visited[adj[i][j]]) dfs(adj[i][j], i); } } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } for (int i = 1; i <= n; i++) { if (!visited[i]) k++, dfs(i, 0); } if (n == m && k == 1) cout << FHTAGN! n ; else cout << NO n ; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
module sync_bits
(
input [NUM_OF_BITS-1:0] in,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out
);
// Number of bits to synchronize
parameter NUM_OF_BITS = 1;
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter ASYNC_CLK = 1;
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out = ASYNC_CLK ? cdc_sync_stage2 : in;
endmodule
|
//
// my_fpga_test_count_dn.v
//
`timescale 1ns/1ps
module my_fpga_test_count_dn;
reg clk = 0, n_rst = 0;
reg up = 0, dn = 0;
wire [31:0] cnt;
wire [3:0] cnt_1k;
reg in1 = 0, in2 = 0;
wire out1, out2;
my_fpga uut(clk, n_rst, up, dn, cnt, cnt_1k, in1, in2, out1, out2);
tbmsgs msgs();
always
#5 clk = ~clk;
initial
begin
msgs.testcase("my_fpga count dn", 2);
#1000
n_rst = 1;
#1000
// check count is 0xfffffff6 after 10 clocks
@(negedge clk);
dn <= 1;
repeat (10)
@(negedge clk);
msgs.check(cnt == 32'hfffffff6, "cnt should be 0xfffffff6");
msgs.tested("count down to 0xfffffff6");
// check count is 0xfffffc00 after another 1014 clocks
repeat (1014)
@(negedge clk);
msgs.check(cnt == 32'hfffffc00, "cnt should be 0xfffffc00");
msgs.tested("count down to 0xfffff400");
msgs.testcase_complete();
$finish;
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 7137 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w255,
w32,
w223,
w7136,
w7137;
assign w1 = i_data0;
assign w223 = w255 - w32;
assign w255 = w256 - w1;
assign w256 = w1 << 8;
assign w32 = w1 << 5;
assign w7136 = w223 << 5;
assign w7137 = w1 + w7136;
assign o_data0 = w7137;
//multiplier_block area estimate = 4903.11357282206;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; vector<long long> cnt(26, 0); for (auto x : s) { cnt[x - a ]++; } deque<long long> d; for (long long i = 0; i < 26; i++) { if (cnt[i]) { d.push_back(i); } } deque<long long> ans; if ((long long)d.size() == 2) { if (d[0] + 1 == d[1]) { cout << No answer << n ; return; } ans = d; } else if ((long long)d.size() == 3) { if (d[0] + 1 == d[1] && d[1] + 1 == d[2]) { cout << No answer << n ; return; } else if (d[0] + 1 == d[1]) { ans.push_back(d[0]); ans.push_back(d[2]); ans.push_back(d[1]); } else { ans.push_back(d[1]); ans.push_back(d[0]); ans.push_back(d[2]); } } else { long long fl = 1; while ((long long)d.size() > 1) { if (fl) { ans.push_back(d.front()); d.pop_front(); } else { ans.push_back(d.back()); d.pop_back(); } fl ^= 1; } ans.push_front(d[0]); } for (auto x : ans) { for (long long i = 0; i < cnt[x]; i++) { cout << (char)(x + a ); } } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tc; tc = 1; cin >> tc; for (int i = 1; i <= tc; i++) { solve(); } return 0; }
|
module tri_light_svetofor ( //Этот модуль описывает блок имитации трехцветного светофора.
//A usual tricolor traffic light. Inverter logic, 1 is off.
input wire time_signal,
input wire reset,
output wire red,
output wire yellow,
output wire green
);
//Блок параметров - аналог констант в Verilog. Описываются временные интервалы
//каждого из режимов работы светофора, для проверок в блоке always.
//Значения умножаются на два так как даются в секундах, а отсчет времени идет полусекундными интервалами.
parameter green_time = 8'd26 * 8'd2, //Multiplier is 2, because time interval is a half-second.
red_time = 8'd84 * 8'd2,
yellow_time = 8'd3 * 8'd2,
blnk_time = 8'd4 * 8'd2,
tril_time = green_time + blnk_time + red_time + yellow_time * 8'd2;
reg [7:0] timer; //Счетчик сигналов времени.
//A time keeper for this module.
reg [2:0] sel_color; //Регистр выбора цвета светофора. 0 бит - красный, 1 бит - желтый, 2 бит - зеленый.
//Активный сигнал для светодиодов - ноль.
//An output selector: 0 bit - red, 1 bit - yellow, 2 bit - green. A zero level is active.
//Соединение выходных проводов модуля с соотвествующими битами регистра выбора цвета.
//Операция assign должна выполняться всегда и поэтому не может размещаться в поведенческом блоке always.
assign red = sel_color[0];
assign yellow = sel_color[1];
assign green = sel_color[2];
//Поведенческий блок always, выполняется по сигналам (по умолчанию - фронт) перечисленным в скобках.
//Только здесь возможно использование ветвлений и циклов verilog.
always @(posedge time_signal or negedge reset)
begin
//Здесь в операциях с регистрами используется неблокирующее присваивание "<=".
//Эти операции не выполняются в месте использования, а откладываются до конца блока always.
//Зато в конце блока они выполняются все разом, одновременно. Абсолютно ПАРАЛЛЕЛЬНО.
if (!reset) //Если нажата кнопка сброса (активный сигнал - ноль), то...
begin //A zero level is active.
timer <= 8'd0;
sel_color <= 3'b110; //Произвести установку регистров в начальное состояние.
//Работа светофора начинается с красного сигнала. Активный сигнал - ноль.
end
else //Иначе, вход сброса не в нулевом состоянии (там единица, z или вообще неопределенное состояние).
begin //Ниже идет логика работы светофора.
if (timer < tril_time) //Если значение счетчика не добралось до конца одного цикла работы светофора...
//Keep time counting.
timer <= timer + 8'd1; //Увеличить его еще на единицу.
else
timer <= 8'd0; //Иначе начать отсчет заново.
//Reset timer.
if (timer <= red_time) //Если значение таймера лежит в интервале работы красного света.
//A red color time.
sel_color <= 3'b110; //Включить красный (активный - ноль), а желтый и зеленый отключить.
//A yellow color time.
if (timer > red_time && timer <= red_time + yellow_time) //Желтый свет - переход от красного к зеленому.
sel_color <= 3'b100; //Горят два светодиода.
//A green color time.
if (timer > red_time + yellow_time && timer <= red_time + yellow_time + green_time) //Зеленый свет.
sel_color <= 3'b011; //Горит один светодиод, красный и желтый выключены.
//Окончание работы зеленого света.
//На протяжении этого интервала зеленый сигнал мигает с частотой сигнала времени.
//A green blinking.
if (timer > red_time + yellow_time + green_time && timer <= red_time + yellow_time + green_time + blnk_time)
if (sel_color == 3'b011)
sel_color <= 3'b111; //Выключить зеленый.
else
sel_color <= 3'b011; //Включить зеленый.
//A yellow color time.
//End of sequence. Next - timer reset.
//Переход от зеленого сигнала к красному. Конец цикла работы светофора.
//Дальше будет сброс таймера и все заново.
if (timer > red_time + yellow_time + green_time + blnk_time)
sel_color <= 3'b101; //Горит один светодиод - желтый.
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool a[1100][26]; vector<bool> v(1100, false); int main() { int n; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; for (auto c : s) a[i][c - 97] = true; } for (int i = 0; i < n; i++) { if (v[i]) continue; for (int j = i + 1; j < n; j++) { bool b = true; for (int g = 0; g < 26; g++) if (a[i][g] != a[j][g]) b = false; if (b) { v[j] = true; } } } int ans = 0; for (int i = 0; i < n; i++) if (!v[i]) ans++; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int ma = -1, mi = 1000000000000000; inline long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } inline long long int lcm(long long int a, long long int b, long long int MOD) { return a / gcd(a, b) * b % MOD; } long long int power(long long int x, unsigned int y) { if (y == 0) return 1; else if (y % 2 == 0) return power(x, y / 2) * power(x, y / 2); else return x * power(x, y / 2) * power(x, y / 2); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int n, i, j = 1, k = 0, b; cin >> n >> k; if (k % 2 == 1) { cout << 1 << endl; return 0; } while (true) { if (k % 2 == 1) break; j++; k /= 2; } cout << j << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hd__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int T; T = 1; while (T--) { string t, s, s1, s2; cin >> t; s = t; int i, j, x, l, a = 0; for (i = 0; i < t.length(); i++) { if (t[i] == a ) a = i; } for (i = 0; i < t.length(); i++) { if (t[i] == a ) { t.erase(i, 1); i--; } } l = t.length(); s1 = t.substr(0, l / 2); s2 = t.substr(l / 2, l - l / 2); if (s1 == s2) { for (i = 0, j = 0; j < s1.length();) { if (s[i] != a ) { i++; j++; } else i++; } while (s[i] == a ) { i++; } if (i > a) { s1 = s.substr(0, i); cout << s1 << endl; } else cout << :( n ; } else { cout << :( n ; } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
#include <bits/stdc++.h> using namespace std; int w[2][2]; int kb[2], kc[2]; int size[10][10]; string s; int main() { ios_base::sync_with_stdio(0); for (int i = 0; i <= (int)(2) - 1; i++) { cin >> s; w[i][0] = s[0] - a ; w[i][1] = s[1] - 1 ; } cin >> s; kb[0] = s[0] - a ; kb[1] = s[1] - 1 ; cin >> s; kc[0] = s[0] - a ; kc[1] = s[1] - 1 ; for (int i = 0; i <= (int)(10) - 1; i++) for (int j = 0; j <= (int)(10) - 1; j++) size[i][j] = 0; int x, y; for (int ii = 0; ii <= (int)(2) - 1; ii++) { for (int i = w[ii][0] + 1; i <= 7; i++) { if (i == kb[0] && w[ii][1] == kb[1]) break; size[i][w[ii][1]] = 1; } for (int i = w[ii][0] - 1; i >= 0; i--) { if (i == kb[0] && w[ii][1] == kb[1]) break; size[i][w[ii][1]] = 1; } for (int j = w[ii][1] + 1; j <= 7; j++) { if (w[ii][0] == kb[0] && j == kb[1]) break; size[w[ii][0]][j] = 1; } for (int j = w[ii][1] - 1; j >= 0; j--) { if (w[ii][0] == kb[0] && j == kb[1]) break; size[w[ii][0]][j] = 1; } } for (int i = -1; i <= 1; i++) for (int j = -1; j <= 1; j++) { int a = i + kb[0], b = j + kb[1]; if (a >= 0 && a < 8 && b >= 0 && b < 8) { size[a][b] = 1; } } for (int i = -1; i <= 1; i++) for (int j = -1; j <= 1; j++) { int a = i + kc[0], b = j + kc[1]; if (a >= 0 && a < 8 && b >= 0 && b < 8) { if (size[a][b]) { } else { cout << OTHER n ; return 0; } } } cout << CHECKMATE n ; return 0; }
|
`timescale 1ns / 1ps
module img_delay_ctl # (
parameter integer C_STEP_NUMBER_WIDTH = 32,
parameter integer C_FRMN_WIDTH = 2,
parameter integer C_TEST = 0
) (
input clk,
input eof,
input wire [31:0] delay0_cnt,
input wire [C_FRMN_WIDTH-1:0] delay0_frm,
output reg delay0_pulse,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] cur_pos,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] movie_pos
);
reg [31:0] time_cnt;
always @ (posedge clk) begin
if (eof)
time_cnt <= 0;
else
time_cnt <= time_cnt + 1;
end
always @ (posedge clk) begin
if (eof)
delay0_pulse <= 0;
else if (time_cnt == delay0_cnt)
delay0_pulse <= 1'b1;
else
delay0_pulse <= 0;
end
localparam integer C_MAX_FRMN = 2**C_FRMN_WIDTH;
reg signed [C_STEP_NUMBER_WIDTH-1:0] history_pos[C_MAX_FRMN-1:1];
wire signed [C_STEP_NUMBER_WIDTH-1:0] hisAcur_pos[C_MAX_FRMN-1:0];
always @ (posedge clk) begin
if (delay0_pulse)
history_pos[1] <= cur_pos;
end
genvar i;
generate
for (i = 2; i < C_MAX_FRMN; i = i+1) begin
always @ (posedge clk) begin
if (delay0_pulse)
history_pos[i] <= history_pos[i-1];
end
end
for (i = 1; i < C_MAX_FRMN; i = i+1) begin
assign hisAcur_pos[i] = history_pos[i];
end
assign hisAcur_pos[0] = cur_pos;
endgenerate
always @ (posedge clk) begin
if (delay0_pulse)
movie_pos <= hisAcur_pos[delay0_frm];
end
endmodule
|
#include <bits/stdc++.h> const int N = 2e5 + 5; const int highestboolN = 1e9; const long long unsigned inf = 1234568901234567890; const long double pi = 3.141592653589793; const int md = 1e9 + 7; using namespace std; int here = 1; void force_break() { here++; if (here >= (N * 100)) { cout << n n t Infinite loop n n ; exit(1); } return; } int board[105][105]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; scanf( %d , &n); memset(board, 0, sizeof(board)); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (board[i][j]) continue; char temp; if ((i + j) % 2) { board[i][j] = 1; temp = 2; } else { board[i][j] = 2; temp = 1; } if (i + 2 < n and j + 1 < n) board[i + 2][j + 1] = temp; if (i + 1 < n and j + 2 < n) board[i + 1][j + 2] = temp; if (i + 2 < n and j - 1 >= 0) board[i + 2][j - 1] = temp; if (i + 1 < n and j - 2 >= 0) board[i + 1][j - 2] = temp; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (board[i][j] == 1) cout << B ; else if (board[i][j] == 2) cout << W ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int A[1001][1001]; int n, m, k, i, j, l, r, a, b, x, y, p, q; int main() { cin >> n >> a >> b; x = n / 2; y = n - x; p = 1; q = 2; for (i = 1; i <= a; i++) for (j = 1; j <= b; j++) { l = A[i - 1][j] % 2; r = A[i][j - 1] % 2; if (j == 1) r = l; if (i == 1) l = r; if (l != r) continue; if (l == 1 && x) A[i][j] = q, q += 2, x--; else if (l == 0 && y) A[i][j] = p, p += 2, y--; } if (x != 0 || y != 0) { cout << -1; return 0; } for (i = 1; i <= a; i++) { for (j = 1; j <= b; j++) cout << A[i][j] << ; cout << endl; } }
|
`default_nettype none
//---------------------------------------------------------------------
//-- --
//-- Company: University of Bonn --
//-- Engineer: John Bieling --
//-- --
//---------------------------------------------------------------------
//-- --
//-- Copyright (C) 2015 John Bieling --
//-- --
//-- This program is free software; you can redistribute it and/or --
//-- modify it under the terms of the GNU General Public License as --
//-- published by the Free Software Foundation; either version 3 of --
//-- the License, or (at your option) any later version. --
//-- --
//-- This program is distributed in the hope that it will be useful, --
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
//-- GNU General Public License for more details. --
//-- --
//-- You should have received a copy of the GNU General Public --
//-- License along with this program; if not, see --
//-- <http://www.gnu.org/licenses>. --
//-- --
//---------------------------------------------------------------------
module datalatch (CLK,
data,
latch,
latched_data);
parameter data_width = 32;
parameter clip_latch = 1;
parameter latch_pipe_steps = 0;
parameter input_pipe_steps = 0;
parameter keep_register_names = "YES";
input wire CLK;
input wire latch;
input wire [data_width-1:0] data;
(* KEEP = keep_register_names *) output reg [data_width-1:0] latched_data;
wire clipped_latch;
wire final_latch;
wire [data_width-1:0] final_data;
generate
if (clip_latch == 1)
begin
signal_clipper latchclip ( .sig(latch), .CLK(CLK), .clipped_sig(clipped_latch));
end else begin
assign clipped_latch = latch;
end
endgenerate
datapipe #(.data_width(1), .pipe_steps(latch_pipe_steps)) latch_pipe(.data(clipped_latch), .piped_data(final_latch), .CLK(CLK));
datapipe #(.data_width(data_width), .pipe_steps(input_pipe_steps)) input_pipe(.data(data), .piped_data(final_data), .CLK(CLK));
always@(posedge CLK)
begin
if (final_latch == 1'b1) latched_data <= final_data;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXn = 100 + 13; int n, k, t[MAXn]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> t[i]; cin >> k; sort(t, t + n); int i = 0, j = 0, d = 0, num = 0, ans = 0; while (j < n) { d = t[j++] - t[i]; while (d > k) d -= t[i++]; num = j - i; ans = max(ans, num); } cout << ans << endl; return 0; }
|
/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
integer i;
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: dmem[addr] <= asubb;
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
$display("program caused halt with value %d\n",asubb);
$display("dmem:");
for (i=0; i<16; i=i+1)
$display("%d %d", i, dmem[i]);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh("sbn.p", imem);
$readmemh("sbn.d", dmem);
PC = 0;
state = 0;
$display("imem:");
for (i=0; i<32; i=i+1)
$display("%d %h", i, imem[i]);
$display("dmem:");
for (i=0; i<16; i=i+1)
$display("%d %d", i, dmem[i]);
end
endmodule
module top;
reg clk;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
always @ (clk or state or pc or a or b)
$display ("%b %d %d %d %d", clk, state, pc, a, b);
initial
begin
clk = 0;
$display("clk state pc a b");
end
always
#10 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt_9s(long long int num); long long int power(int num, int exp); int main() { long long int num, sale, rem; cin >> num >> sale; while (1) { rem = power(10, cnt_9s(num) + 1); if (sale >= num % rem + 1) sale -= (num % rem + 1), num -= (num % rem + 1); else break; } cout << num << endl; return 0; } long long int power(int num, int exp) { long long int res = 1; while (exp != 0) res *= num, exp--; return res; } int cnt_9s(long long int num) { int cnt = 0; while (num != 0) if (num % 10 == 9) cnt++, num /= 10; else break; return cnt; }
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#include <bits/stdc++.h> using namespace std; int n, m, x; int main() { scanf( %d%d , &n, &m); x = n; for (int i = 0; i < m; i++) { int l, r; scanf( %d%d , &l, &r); x = min(x, r - l + 1); } printf( %d n , x); for (int i = 0; i < n; i++) printf( %d , i % x); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, T; double dp[5001][5001]; int p[5001], t[5001]; double quickpow(double x, int y) { double res = 1; while (y) { if (y & 1) res *= x; x *= x; y >>= 1; } return res; } int main() { cin >> n >> T; dp[0][0] = 1; for (int i = 0; i < n; i++) scanf( %d%d , &p[i], &t[i]); double ans = 0; for (int i = 0; i < n; i++) { double pp = p[i] * 0.01; double now = 0; double r = quickpow(1 - pp, t[i] - 1) * pp; double r2 = quickpow(1 - pp, t[i] - 1); for (int j = 0; j < T; j++) { now *= (1 - pp); now += dp[i][j] * pp; if (j + 1 >= t[i]) { now -= dp[i][j + 1 - t[i]] * r; dp[i + 1][j + 1] = now + dp[i][j + 1 - t[i]] * r2; } else { dp[i + 1][j + 1] = now; } } for (int j = 0; j <= T; j++) ans += dp[i + 1][j]; } printf( %.12f n , ans); return 0; }
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/* in the name of Anton */ /* Compete against Yourself. Author - Aryan (@aryanc403) Atcoder library - https://atcoder.github.io/ac-library/production/document_en/ */ #include <algorithm> #include <cassert> #include <limits> #include <queue> #include <vector> #include <algorithm> #include <utility> #include <vector> namespace atcoder { namespace internal { template <class E> struct csr { std::vector<int> start; std::vector<E> elist; csr(int n, const std::vector<std::pair<int, E>>& edges) : start(n + 1), elist(edges.size()) { for (auto e : edges) { start[e.first + 1]++; } for (int i = 1; i <= n; i++) { start[i] += start[i - 1]; } auto counter = start; for (auto e : edges) { elist[counter[e.first]++] = e.second; } } }; } // namespace internal } // namespace atcoder #include <vector> namespace atcoder { namespace internal { template <class T> struct simple_queue { std::vector<T> payload; int pos = 0; void reserve(int n) { payload.reserve(n); } int size() const { return int(payload.size()) - pos; } bool empty() const { return pos == int(payload.size()); } void push(const T& t) { payload.push_back(t); } T& front() { return payload[pos]; } void clear() { payload.clear(); pos = 0; } void pop() { pos++; } }; } // namespace internal } // namespace atcoder namespace atcoder { template <class Cap, class Cost> struct mcf_graph { public: mcf_graph() {} mcf_graph(int n) : _n(n) {} int add_edge(int from, int to, Cap cap, Cost cost) { assert(0 <= from && from < _n); assert(0 <= to && to < _n); assert(0 <= cap); assert(0 <= cost); int m = int(_edges.size()); _edges.push_back({from, to, cap, 0, cost}); return m; } struct edge { int from, to; Cap cap, flow; Cost cost; }; edge get_edge(int i) { int m = int(_edges.size()); assert(0 <= i && i < m); return _edges[i]; } std::vector<edge> edges() { return _edges; } std::pair<Cap, Cost> flow(int s, int t) { return flow(s, t, std::numeric_limits<Cap>::max()); } std::pair<Cap, Cost> flow(int s, int t, Cap flow_limit) { return slope(s, t, flow_limit).back(); } std::vector<std::pair<Cap, Cost>> slope(int s, int t) { return slope(s, t, std::numeric_limits<Cap>::max()); } std::vector<std::pair<Cap, Cost>> slope(int s, int t, Cap flow_limit) { assert(0 <= s && s < _n); assert(0 <= t && t < _n); assert(s != t); int m = int(_edges.size()); std::vector<int> edge_idx(m); auto g = [&]() { std::vector<int> degree(_n), redge_idx(m); std::vector<std::pair<int, _edge>> elist; elist.reserve(2 * m); for (int i = 0; i < m; i++) { auto e = _edges[i]; edge_idx[i] = degree[e.from]++; redge_idx[i] = degree[e.to]++; elist.push_back({e.from, {e.to, -1, e.cap - e.flow, e.cost}}); elist.push_back({e.to, {e.from, -1, e.flow, -e.cost}}); } auto _g = internal::csr<_edge>(_n, elist); for (int i = 0; i < m; i++) { auto e = _edges[i]; edge_idx[i] += _g.start[e.from]; redge_idx[i] += _g.start[e.to]; _g.elist[edge_idx[i]].rev = redge_idx[i]; _g.elist[redge_idx[i]].rev = edge_idx[i]; } return _g; }(); auto result = slope(g, s, t, flow_limit); for (int i = 0; i < m; i++) { auto e = g.elist[edge_idx[i]]; _edges[i].flow = _edges[i].cap - e.cap; } return result; } private: int _n; std::vector<edge> _edges; struct _edge { int to, rev; Cap cap; Cost cost; }; std::vector<std::pair<Cap, Cost>> slope(internal::csr<_edge>& g, int s, int t, Cap flow_limit) { std::vector<std::pair<Cost, Cost>> dual_dist(_n); std::vector<int> prev_e(_n); std::vector<bool> vis(_n); struct Q { Cost key; int to; bool operator<(Q r) const { return key > r.key; } }; std::vector<int> que_min; std::vector<Q> que; auto dual_ref = [&]() { for (int i = 0; i < _n; i++) { dual_dist[i].second = std::numeric_limits<Cost>::max(); } std::fill(vis.begin(), vis.end(), false); que_min.clear(); que.clear(); size_t heap_r = 0; dual_dist[s].second = 0; que_min.push_back(s); while (!que_min.empty() || !que.empty()) { int v; if (!que_min.empty()) { v = que_min.back(); que_min.pop_back(); } else { while (heap_r < que.size()) { heap_r++; std::push_heap(que.begin(), que.begin() + heap_r); } v = que.front().to; std::pop_heap(que.begin(), que.end()); que.pop_back(); heap_r--; } if (vis[v]) continue; vis[v] = true; if (v == t) break; Cost dual_v = dual_dist[v].first, dist_v = dual_dist[v].second; for (int i = g.start[v]; i < g.start[v + 1]; i++) { auto e = g.elist[i]; if (!e.cap) continue; Cost cost = e.cost - dual_dist[e.to].first + dual_v; if (dual_dist[e.to].second - dist_v > cost) { Cost dist_to = dist_v + cost; dual_dist[e.to].second = dist_to; prev_e[e.to] = e.rev; if (dist_to == dist_v) { que_min.push_back(e.to); } else { que.push_back(Q{dist_to, e.to}); } } } } if (!vis[t]) { return false; } for (int v = 0; v < _n; v++) { if (!vis[v]) continue; dual_dist[v].first -= dual_dist[t].second - dual_dist[v].second; } return true; }; Cap flow = 0; Cost cost = 0, prev_cost_per_flow = -1; std::vector<std::pair<Cap, Cost>> result = {{Cap(0), Cost(0)}}; while (flow < flow_limit) { if (!dual_ref()) break; Cap c = flow_limit - flow; for (int v = t; v != s; v = g.elist[prev_e[v]].to) { c = std::min(c, g.elist[g.elist[prev_e[v]].rev].cap); } for (int v = t; v != s; v = g.elist[prev_e[v]].to) { auto& e = g.elist[prev_e[v]]; e.cap += c; g.elist[e.rev].cap -= c; } Cost d = -dual_dist[s].first; flow += c; cost += c * d; if (prev_cost_per_flow == d) { result.pop_back(); } result.push_back({flow, cost}); prev_cost_per_flow = d; } return result; } }; } // namespace atcoder #ifdef ARYANC403 #include <header.h> #else #pragma GCC optimize ( Ofast ) #pragma GCC target ( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) #pragma GCC optimize ( -ffloat-store ) #include<bits/stdc++.h> #define dbg(args...) 42; #endif using namespace std; #define fo(i,n) for(i=0;i<(n);++i) #define repA(i,j,n) for(i=(j);i<=(n);++i) #define repD(i,j,n) for(i=(j);i>=(n);--i) #define all(x) begin(x), end(x) #define sz(x) ((lli)(x).size()) #define pb push_back #define mp make_pair #define X first #define Y second #define endl n typedef long long int lli; typedef long double mytype; typedef pair<lli,lli> ii; typedef vector<ii> vii; typedef vector<lli> vi; const auto start_time = std::chrono::high_resolution_clock::now(); void aryanc403() { #ifdef ARYANC403 auto end_time = std::chrono::high_resolution_clock::now(); std::chrono::duration<double> diff = end_time-start_time; cerr<< Time Taken : <<diff.count()<< n ; #endif } const lli INF = 0xFFFFFFFFFFFFFFFL; lli seed; mt19937 rng(seed=chrono::steady_clock::now().time_since_epoch().count()); inline lli rnd(lli l=0,lli r=INF) {return uniform_int_distribution<lli>(l,r)(rng);} class CMP {public: bool operator()(ii a , ii b) //For min priority_queue . { return ! ( a.X < b.X || ( a.X==b.X && a.Y <= b.Y )); }}; void add( map<lli,lli> &m, lli x,lli cnt=1) { auto jt=m.find(x); if(jt==m.end()) m.insert({x,cnt}); else jt->Y+=cnt; } void del( map<lli,lli> &m, lli x,lli cnt=1) { auto jt=m.find(x); if(jt->Y<=cnt) m.erase(jt); else jt->Y-=cnt; } bool cmp(const ii &a,const ii &b) { return a.X<b.X||(a.X==b.X&&a.Y<b.Y); } const lli mod = 1000000007L; // const lli maxN = 1000000007L; lli T,n,i,j,k,in,cnt,l,r,u,v,x,y; lli m; string s; vi a; vii b; //priority_queue < ii , vector < ii > , CMP > pq;// min priority_queue . lli countPaths(vii edges){ const int inf=1e9; atcoder::mcf_graph<lli,lli> g(2*n + 2); for(int i=0;i<n;++i){ g.add_edge(2*n,i,1,0); g.add_edge(i+n,2*n+1,1,0); } for(auto x:edges){ g.add_edge(x.X,n+x.Y,1,inf-1); } return n-g.flow(2*n,2*n+1).X; } lli removeOne(vii &edges,int curVal){ for(int i=0;i<n;++i){ vii ed; for(auto x:edges){ if(x.Y==i) continue; ed.pb(x); } if(curVal==countPaths(ed)){ edges.swap(ed); return -(i+1); } ed.clear(); for(auto x:edges){ if(x.X==i) continue; ed.pb(x); } if(curVal==countPaths(ed)){ edges.swap(ed); return (i+1); } } assert(false); } vi solve(vii edges,lli k){ vi answers(k+1,-INF); dbg(countPaths(edges)); const int st=countPaths(edges); for(int fw=st;fw<=k;++fw){ answers[fw]=removeOne(edges,fw+1); } return answers; } int main(void) { ios_base::sync_with_stdio(false);cin.tie(NULL); // freopen( txt.in , r , stdin); // freopen( txt.out , w , stdout); // cout<<std::fixed<<std::setprecision(35); // cin>>T;while(T--) { cin>>n>>m>>k; vii edges; fo(i,m) { cin>>u>>v; u--;v--; edges.pb({u,v}); } auto operations=solve(edges,k); b.resize(k+1); for(int i=1;i<=k;++i){ cin>>b[i].X>>b[i].Y; b[i].Y=min(b[i].X,b[i].Y); } b[0]={INF,1e12}; lli curVal=-INF; vector<vi> ansb(k+1); auto getBest=[&](const lli rest){ vector<vi> before(k+1); auto bb=b; auto insert=[&](const int place,const int op){ before[place].pb(op); bb[place].X-=bb[place].Y; bb[place].X=max(bb[place].X,0LL); bb[place].Y=min(bb[place].Y,bb[place].X); }; for(int i=1;i<rest&&i<=k;++i){ if(operations[i]==-INF) continue; const int op=operations[i]; int place=0; for(int j=1;j<=i;++j){ if(bb[place].Y>bb[j].Y) place=j; } insert(place,op); } for(int i=rest;i<=k;++i){ if(operations[i]==-INF) continue; const int op=operations[i]; insert(rest,op); } lli cst=0; for(int i=1;i<=k;++i) cst+=bb[i].X; dbg(bb,cst); if(cst>curVal){ curVal=cst; ansb.swap(before); } }; for(int rest=1;rest<=k+1;++rest){ getBest(rest); } dbg(curVal); vi ans; for(int i=1;i<=k;++i){ for(auto x:ansb[i]) ans.pb(x); ans.pb(0); } cout<<sz(ans)<<endl; for(auto x:ans) cout<<x<< ; cout<<endl; } aryanc403(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int k, l, m, n, d, x = 0; cin >> k; cin >> l; cin >> m; cin >> n; cin >> d; int arr[] = {k, l, m, n}; for (int i = 1; i <= d; i++) { for (int j = 0; j < 4; j++) { if (i % arr[j] == 0) { x++; break; } } } cout << x; return 0; }
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//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_io_update (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
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`timescale 1ns / 1ps
`include "../src/axis_blender.v"
module test_axis_blender_2lvl(
);
parameter integer C_CHN_WIDTH = 8;
parameter integer C_S0_CHN_NUM = 1;
parameter integer C_S1_CHN_NUM = 3;
parameter integer C_ALPHA_WIDTH = 8;
parameter integer C_S1_ENABLE = 1;
parameter integer C_IN_NEED_WIDTH = 1;
parameter integer C_OUT_NEED_WIDTH = 0; /// must be (C_IN_NEED_WIDTH - 1), min val is 0
parameter integer C_M_WIDTH = 24; /// must be max(C_S0_CHN_NUM, C_S1_CHN_NUM) * C_CHN_WIDTH
parameter integer C_TEST = 0;
reg clk;
reg resetn;
localparam integer C_MAX_STREAM_NUM = 2;
localparam integer C_IMG_BITS = 12;
reg [C_MAX_STREAM_NUM-1:0] s_random ;
reg [C_IMG_BITS-1:0] s_width;
reg [C_IMG_BITS-1:0] s_height;
reg s_valid [C_MAX_STREAM_NUM-1:0];
wire [C_M_WIDTH + C_ALPHA_WIDTH-1:0] s_data [C_MAX_STREAM_NUM-1:0];
wire [C_IN_NEED_WIDTH:0] s_user [C_MAX_STREAM_NUM-1:0];
wire s_last [C_MAX_STREAM_NUM-1:0];
wire s_ready [C_MAX_STREAM_NUM-1:0];
reg s_enable [C_MAX_STREAM_NUM-1:0];
reg m_random ;
reg m_enprint;
wire sint_valid;
wire [C_CHN_WIDTH*C_S0_CHN_NUM-1:0] sint_data ;
wire sint_user ;
wire sint_last ;
wire sint_ready;
wire m_valid ;
wire [C_M_WIDTH-1:0] m_data ;
wire [C_OUT_NEED_WIDTH:0]m_user ;
wire m_last ;
reg m_ready ;
axis_blender # (
.C_CHN_WIDTH (8 ),
.C_S0_CHN_NUM (1 ),
.C_S1_CHN_NUM (1 ),
.C_ALPHA_WIDTH (0 ),
.C_S1_ENABLE (0 ),
.C_IN_NEED_WIDTH (1 ),
.C_OUT_NEED_WIDTH (0 ),
.C_M_WIDTH (8 ),
.C_TEST (0 )
) blender1 (
.clk(clk),
.resetn(resetn),
.s0_axis_tvalid(s_valid [0]),
.s0_axis_tdata (s_data [0][7:0]),
.s0_axis_tuser (s_user [0][1:0]),
.s0_axis_tlast (s_last [0]),
.s0_axis_tready(s_ready [0]),
//.s1_enable (0),
//.s1_axis_tvalid(0),
//.s1_axis_tdata (0),
//.s1_axis_tuser (0),
//.s1_axis_tlast (0),
//.s1_axis_tready(0),
.m_axis_tvalid(sint_valid ),
.m_axis_tdata (sint_data ),
.m_axis_tuser (sint_user ),
.m_axis_tlast (sint_last ),
.m_axis_tready(sint_ready )
);
axis_blender # (
.C_CHN_WIDTH (8 ),
.C_S0_CHN_NUM (1 ),
.C_S1_CHN_NUM (3 ),
.C_ALPHA_WIDTH (8 ),
.C_S1_ENABLE (1 ),
.C_IN_NEED_WIDTH (0 ),
.C_OUT_NEED_WIDTH (0),
.C_M_WIDTH (24 ),
.C_TEST (0 )
) blender2 (
.clk(clk),
.resetn(resetn),
.s0_axis_tvalid(sint_valid ),
.s0_axis_tdata (sint_data ),
.s0_axis_tuser (sint_user ),
.s0_axis_tlast (sint_last ),
.s0_axis_tready(sint_ready ),
.s1_enable (s_enable [0]),
.s1_axis_tvalid(s_valid [1]),
.s1_axis_tdata (s_data [1]),
.s1_axis_tuser (s_user [1][0]),
.s1_axis_tlast (s_last [1]),
.s1_axis_tready(s_ready [1]),
.m_axis_tvalid(m_valid ),
.m_axis_tdata (m_data ),
.m_axis_tuser (m_user ),
.m_axis_tlast (m_last ),
.m_axis_tready(m_ready )
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
initial begin
s_enable[0] <= 1;
s_enable[1] <= 1;
s_random <= 2'b11;
m_random <= 1'b1;
m_enprint <= 1'b1;
s_width <= 3;
s_height <= 5;
end
generate
genvar i;
genvar j;
for (i = 0; i < 2; i = i + 1) begin: single_input
reg [C_IMG_BITS-1:0] s_ridx;
reg [C_IMG_BITS-1:0] s_cidx;
reg en_input;
always @ (posedge clk) begin
if (resetn == 1'b0) en_input <= 1'b0;
else en_input <= (s_random[i] ? {$random}%2 : 1);
end
always @ (posedge clk) begin
if (resetn == 1'b0)
s_valid[i] <= 1'b0;
else if (~s_valid[i]) begin
if (en_input)
s_valid[i] <= 1'b1;
end
else begin
if (s_ready[i])
s_valid[i] <= en_input;
end
end
assign s_data[i] = (s_ridx * 16 + s_cidx) + (255 << 16);
assign s_user[i] = (s_ridx == 0 && s_cidx == 0);
assign s_last[i] = (s_cidx == s_width - 1);
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_ridx <= 0;
s_cidx <= 0;
end
else if (s_valid[i] && s_ready[i]) begin
if (s_cidx != s_width - 1) begin
s_cidx <= s_cidx + 1;
s_ridx <= s_ridx;
end
else if (s_ridx != s_height - 1) begin
s_cidx <= 0;
s_ridx <= s_ridx + 1;
end
else begin
s_cidx <= 0;
s_ridx <= 0;
end
end
end
end
endgenerate
generate
reg [C_IMG_BITS-1:0] m_ridx;
reg [C_IMG_BITS-1:0] m_cidx;
reg en_output;
always @ (posedge clk) begin
if (resetn == 1'b0) en_output <= 1'b0;
else en_output <= (m_random ? {$random}%2 : 1);
end
always @(posedge clk) begin
if (resetn == 1'b0)
m_ready <= 1'b0;
else if (~m_ready)
m_ready <= en_output;
else begin
if (m_valid)
m_ready <= en_output;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_ready && m_valid) begin
if (m_user[0]) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_last) begin
m_cidx = 0;
m_ridx = m_ridx + 1;
end
else begin
m_cidx = m_cidx + 1;
m_ridx = m_ridx;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
end
else if (m_ready && m_valid && m_enprint) begin
if (m_user[0])
$write("out new frame: \n");
$write("%h ", m_data);
if (m_last)
$write("\n");
end
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); struct myHash { template <class T1, class T2> size_t operator()(const pair<T1, T2>& p) const { auto hash1 = hash<T1>{}(p.first); auto hash2 = hash<T2>{}(p.second); return hash1 ^ hash2; } }; class segTree { vector<long long int> a; vector<long long int> tree; vector<long long int> lazy; long long int sel; long long int minRange(long long int left, long long int right) { return min(left, right); } long long int maxRange(long long int left, long long int right) { return max(left, right); } long long int rangeSum(long long int left, long long int right) { return left + right; } void build(long long int index, long long int start, long long int end) { if (start > end) { return; } if (start == end) { tree[index] = a[start]; return; } long long int mid = (start + end) / 2; build(2 * index, start, mid); build(2 * index + 1, mid + 1, end); long long int left = tree[2 * index]; long long int right = tree[2 * index + 1]; if (sel == 0) { tree[index] = minRange(tree[2 * index], tree[2 * index + 1]); } else if (sel == 1) { tree[index] = maxRange(tree[2 * index], tree[2 * index + 1]); } else if (sel == 2) { tree[index] = rangeSum(tree[2 * index], tree[2 * index + 1]); } } long long int query(long long int index, long long int start, long long int end, long long int l, long long int r) { if (lazy[index] != 0) { if (sel == 0) { tree[index] += lazy[index]; } else if (sel == 1) { tree[index] += lazy[index]; } else if (sel == 2) { tree[index] += (end - start + 1) * lazy[index]; } if (start != end) { lazy[2 * index] += lazy[index]; lazy[2 * index + 1] += lazy[index]; } lazy[index] = 0; } if (l > end || r < start) { if (sel == 0) { return LLONG_MAX; } else if (sel == 1) { return LLONG_MIN; } else if (sel == 2) { return 0; } } if (start >= l && end <= r) { return tree[index]; } long long int mid = (start + end) / 2; long long int left = query(2 * index, start, mid, l, r); long long int right = query(2 * index + 1, mid + 1, end, l, r); if (sel == 0) { return minRange(left, right); } else if (sel == 1) { return maxRange(left, right); } else if (sel == 2) { return rangeSum(left, right); } } void update(long long int index, long long int start, long long int end, long long int l, long long int r, long long int inc) { if (lazy[index] != 0) { if (sel == 0) { tree[index] += lazy[index]; } else if (sel == 1) { tree[index] += lazy[index]; } else if (sel == 2) { tree[index] += (r - l + 1) * lazy[index]; } if (start != end) { lazy[2 * index] += lazy[index]; lazy[2 * index + 1] += lazy[index]; } lazy[index] = 0; } if (l <= start and end <= r) { if (sel == 0) { tree[index] += inc; } else if (sel == 1) { tree[index] += inc; } else { tree[index] += (end - start + 1) * inc; } if (start != end) { lazy[2 * index] += inc; lazy[2 * index + 1] += inc; } return; } if (r < start || l > end) { return; } if (start == end) { tree[index] += inc; return; } long long int mid = (start + end) / 2; update(2 * index, start, mid, l, r, inc); update(2 * index + 1, mid + 1, end, l, r, inc); if (sel == 0) { tree[index] = minRange(tree[2 * index], tree[2 * index + 1]); } else if (sel == 1) { tree[index] = maxRange(tree[2 * index], tree[2 * index + 1]); } else if (sel == 2) { tree[index] = rangeSum(tree[2 * index], tree[2 * index + 1]); } } public: segTree(vector<long long int> a, long long int sel) { this->a = a; tree.reserve(4 * a.size() + 1); lazy.reserve(4 * a.size() + 1); for (int i = 0; i < 4 * a.size() + 1; i++) { lazy[i] = 0; } this->sel = sel; } void build() { build(1, 0, a.size() - 1); } long long int query(long long int l, long long int r) { return query(1, 0, a.size() - 1, l, r); } void update(long long int l, long long int r, long long int inc) { update(1, 0, a.size() - 1, l, r, inc); } void update(long long int pos, long long int inc) { update(pos, pos, inc); } }; long long int power(long long int b, long long int p, long long int m = 1000000007) { long long int res = 1; while (p > 0) { if (p & 1) { res = (res * b) % m; } b = (b * b) % m; p = p >> 1; } return res; } long long int modInverse(long long int n, long long int m = 1000000007) { return power(n, m - 2, m); } bool mySort(pair<int, int> p1, pair<int, int> p2) { if (p1.first < p2.first) { return true; } else if (p1.first == p2.first and p1.second < p2.second) { return true; } return false; } long long int lis(vector<long long int>& v) { long long int n = v.size(); vector<long long int> dp(n); dp[0] = 1; long long int ans = 1; for (int i = 1; i < n; i++) { long long int m = 0; for (int j = i - 1; j >= 0; j--) { if (v[j] < v[i]) { m = max(m, dp[j]); } } dp[i] = 1 + m; if (ans < dp[i]) { ans = dp[i]; } } return ans; } vector<long long int> sieve(long long int n) { vector<bool> v(n + 1, false); v[2] = true; for (int i = 3; i <= n; i += 2) { v[i] = true; } for (int i = 3; i <= n; i += 2) { if (v[i]) { for (int j = i * i; j <= n; j += 2 * i) { v[j] = false; } } } v[1] = false; v[0] = false; vector<long long int> primes; for (int i = 0; i < v.size(); i++) { if (v[i]) { primes.push_back(i); } } return primes; } long long int gcd(long long int a, long long int b) { while (b > 0) { long long int r = a % b; a = b; b = r; } return a; } long long int lcm(long long int a, long long int b) { long long int g = gcd(a, b); return (a * b) / g; } vector<long long int> segSieve(long long int l, long long int r) { long long int lim = sqrt(r); if (l < 2) { l = 2; } vector<long long int> s = sieve(lim); vector<bool> v(r - l + 1, true); for (long long int i = 0; i < s.size(); i++) { for (long long int j = 0; j < v.size(); j++) { if ((j + l) % s[i] == 0 && (j + l) != s[i]) { v[j] = false; } } } vector<long long int> primes; for (int i = 0; i < v.size(); i++) { if (v[i]) { primes.push_back(i + l); } } return primes; } vector<pair<long long int, long long int>> primeFactors(long long int n) { vector<long long int> primes = sieve(sqrt(n)); long long int p = primes[0]; vector<pair<long long int, long long int>> f; int i = 0; while (p * p <= n) { long long int count = 0; while (n % p == 0) { count++; n /= p; } if (count > 0) { f.push_back(make_pair(p, count)); } i++; p = primes[i]; } if (n > 1) { f.push_back(make_pair(n, 1)); } return f; } vector<long long int> factors(long long int n) { long long int lim = sqrt(n); vector<long long int> f; for (int i = 2; i <= lim; i++) { if (n % i == 0) { f.push_back(i); f.push_back(n / i); } } return f; } long long int ceilAB(long long int a, long long int b) { return (a + b - 1) / b; } long long int low_bound(vector<long long int>& v, long long int start, long long int end, long long int n) { if (start > end) { return -1; } long long int mid = (start + end) / 2; if (v[mid] == n) { return mid; } else if (v[mid] > n) { long long int index = low_bound(v, start, mid - 1, n); return index; } else { long long int index = low_bound(v, mid + 1, end, n); if (index == -1) { return mid; } return index; } } void fastIO() { ios_base::sync_with_stdio(false); cin.tie(NULL); } int main(void) { long long int n; cin >> n; string s; cin >> s; cout << n + 1 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1000 * 100 + 15; int n, mark[maxn], h[maxn], d[maxn], g[2], cnt, c, w; vector<int> ad[maxn]; void dfs(int v) { mark[v] = 1; for (auto u : ad[v]) { if (mark[u] == 0) { h[u] = h[v] + 1; dfs(u); } } } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; ad[u].push_back(v); ad[v].push_back(u); d[u]++; d[v]++; } dfs(1); for (int i = 1; i <= n; i++) { cnt = 0; if (d[i] <= 1) { g[h[i] % 2] = 1; } for (auto u : ad[i]) { if (d[u] == 1) cnt++; } if (cnt > 1) { c++; w += cnt; } } if (g[0] && g[1]) cout << 3; else cout << 1; cout << ; cout << n - 1 + c - w; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_rndrob.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_rndrob
// Description:
// Round robin scheduler. Least priority to the last granted
// customer. If no requests, the priority remains the same.
*/
////////////////////////////////////////////////////////////////////////
module sparc_exu_rndrob(/*AUTOARG*/
// Outputs
grant_vec,
// Inputs
clk, reset, se, req_vec, advance
);
input clk, reset, se;
input [3:0] req_vec;
input advance;
output [3:0] grant_vec;
wire [3:0] pv,
next_pv,
park_vec;
assign next_pv = advance ? grant_vec : park_vec;
dffr_s #4 park_reg(.din (next_pv[3:0]),
.clk (clk),
.q (pv[3:0]),
.rst (reset),
.se (se), .si(), .so());
assign park_vec = pv;
// if noone requests, don't advance, otherwise we'll go back to 0
// and will not be fair to other requestors
assign grant_vec[0] = park_vec[3] & req_vec[0] |
park_vec[2] & ~req_vec[3] & req_vec[0] |
park_vec[1] & ~req_vec[2] & ~req_vec[3] & req_vec[0] |
~req_vec[1] & ~req_vec[2] & ~req_vec[3];
assign grant_vec[1] = park_vec[0] & req_vec[1] |
park_vec[3] & ~req_vec[0] & req_vec[1] |
park_vec[2] & ~req_vec[3] & ~req_vec[0] & req_vec[1] |
req_vec[1] & ~req_vec[2] & ~req_vec[3] & ~req_vec[0];
assign grant_vec[2] = park_vec[1] & req_vec[2] |
park_vec[0] & ~req_vec[1] & req_vec[2] |
park_vec[3] & ~req_vec[0] & ~req_vec[1] & req_vec[2] |
req_vec[2] & ~req_vec[3] & ~req_vec[0] & ~req_vec[1];
assign grant_vec[3] = park_vec[2] & req_vec[3] |
park_vec[1] & ~req_vec[2] & req_vec[3] |
park_vec[0] & ~req_vec[1] & ~req_vec[2] & req_vec[3] |
req_vec[3] & ~req_vec[0] & ~req_vec[1] & ~req_vec[2];
endmodule // sparc_exu_rndrob
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DFSTP_PP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_PP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; int n, p; bool prime(int num) { for (int i = 2; i <= sqrt(num); i++) { if (num % i == 0) return 0; } return 1; } int main() { cin >> n; if (prime(n)) { return cout << 1 << endl << n, 0; } p = (n - 3) / 2; cout << 3 << n << 3 << ; for (int i = 0; i < p; i++) { if (prime(p - i) && prime(p + i)) { cout << p - i << << p + i; return 0; } } return 0; }
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_arb_mux
*/
module test_ip_arb_mux_64_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT-1:0] s_ip_hdr_valid = 0;
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
reg [S_COUNT*16-1:0] s_eth_type = 0;
reg [S_COUNT*4-1:0] s_ip_version = 0;
reg [S_COUNT*4-1:0] s_ip_ihl = 0;
reg [S_COUNT*6-1:0] s_ip_dscp = 0;
reg [S_COUNT*2-1:0] s_ip_ecn = 0;
reg [S_COUNT*16-1:0] s_ip_length = 0;
reg [S_COUNT*16-1:0] s_ip_identification = 0;
reg [S_COUNT*3-1:0] s_ip_flags = 0;
reg [S_COUNT*13-1:0] s_ip_fragment_offset = 0;
reg [S_COUNT*8-1:0] s_ip_ttl = 0;
reg [S_COUNT*8-1:0] s_ip_protocol = 0;
reg [S_COUNT*16-1:0] s_ip_header_checksum = 0;
reg [S_COUNT*32-1:0] s_ip_source_ip = 0;
reg [S_COUNT*32-1:0] s_ip_dest_ip = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_ip_payload_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep = 0;
reg [S_COUNT-1:0] s_ip_payload_axis_tvalid = 0;
reg [S_COUNT-1:0] s_ip_payload_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_ip_payload_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_ip_payload_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_ip_payload_axis_tuser = 0;
reg m_ip_hdr_ready = 0;
reg m_ip_payload_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_ip_hdr_ready;
wire [S_COUNT-1:0] s_ip_payload_axis_tready;
wire m_ip_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [DATA_WIDTH-1:0] m_ip_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep;
wire m_ip_payload_axis_tvalid;
wire m_ip_payload_axis_tlast;
wire [ID_WIDTH-1:0] m_ip_payload_axis_tid;
wire [DEST_WIDTH-1:0] m_ip_payload_axis_tdest;
wire [USER_WIDTH-1:0] m_ip_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_version,
s_ip_ihl,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_header_checksum,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tkeep,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tid,
s_ip_payload_axis_tdest,
s_ip_payload_axis_tuser,
m_ip_hdr_ready,
m_ip_payload_axis_tready
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_ip_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_ip_payload_axis_tdata,
m_ip_payload_axis_tkeep,
m_ip_payload_axis_tvalid,
m_ip_payload_axis_tlast,
m_ip_payload_axis_tid,
m_ip_payload_axis_tdest,
m_ip_payload_axis_tuser
);
// dump file
$dumpfile("test_ip_arb_mux_64_4.lxt");
$dumpvars(0, test_ip_arb_mux_64_4);
end
ip_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame inputs
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tid(s_ip_payload_axis_tid),
.s_ip_payload_axis_tdest(s_ip_payload_axis_tdest),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// Ethernet frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tid(m_ip_payload_axis_tid),
.m_ip_payload_axis_tdest(m_ip_payload_axis_tdest),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int longestIncreasingSubsequenceDP(int a[], int n) { int dp[n], ans = 0; for (int k = 0; k < n; k++) { dp[k] = 1; for (int i = 0; i < k; i++) { if (a[i] <= a[k]) { dp[k] = max(dp[k], dp[i] + 1); ans = max(dp[k], ans); } } } return ans; } int gcd(int a, int b) { if (a == 0) return b; if (b == 0) return a; if (a == b) return a; if (a > b) return gcd(a - b, b); return gcd(a, b - a); } void scanArray(int arr[], int n) { for (int i = 0; i < n; i++) { cin >> arr[i]; } } int highestFromThree(int n1, int n2, int n3) { return max(max(n1, n2), n3); } int highestFromFour(int n1, int n2, int n3, int n4) { return max(max(n1, n2), max(n3, n4)); } int result[1000] = {0}; int factDP(int n) { if (n >= 0) { result[0] = 1; for (int i = 1; i <= n; ++i) { result[i] = i * result[i - 1]; } return result[n]; } } int main() { int n, m; cin >> n >> m; int l[n], r[n]; vector<pair<int, int>> v; int points[m]; for (int i = 0; i < m; i++) { points[i] = i + 1; } for (int i = 0; i < n; i++) { cin >> l[i] >> r[i]; v.push_back(make_pair(l[i], r[i])); } int count = m; for (int i = 0; i < m; i++) { for (int j = 0; j < v.size(); j++) { if (points[i] >= v[j].first && points[i] <= v[j].second) { count--; points[i] = 0; break; } } } cout << count << n ; for (int i = 0; i < m; i++) { if (points[i] != 0) { cout << points[i] << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; string s; cin >> s; vector<long long int> v(n + 1, 0); for (long long int i = 1; i <= n; i++) { if (s[i - 1] == ( ) v[i] = v[i - 1] + 1; else v[i] = v[i - 1] - 1; } if (v[n] != 0) { cout << -1 << n ; return 0; } long long int ans = 0; long long int temp = 0; for (long long int i = 1; i <= n; i++) { if (v[i] < 0) { temp++; } else if (v[i] == 0 && v[i - 1] < 0) { temp++; ans += temp; temp = 0; } } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:04:15 03/13/2015
// Design Name:
// Module Name: PreProcessX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PreProcessY(
input [31:0] z_preprocess,
input [3:0] Opcode,
input [31:0] b_adder,
input [7:0] InsTagIn,
input clock,
output [31:0] FinalSum,
output Done,
output [31:0] z_postprocess,
output [3:0] Opcode_out,
output [7:0] InsTagOut
);
reg [31:0] a_adder_reg = 32'hbf800000;
wire [31:0] a_adder;
assign a_adder = a_adder_reg;
wire idle_Special,idle_Allign,idle_AddState,idle_NormaliseSum;
wire [3:0] Opcode_Special,Opcode_Allign,Opcode_AddState,Opcode_NormaliseSum;
wire [31:0] z_postSpecial,z_postAllign,z_postAddState,z_postNormaliseSum;
wire [31:0] sout_Special,sout_Allign,sout_AddState,sout_NormaliseSum;
wire [35:0] cout_Special,cout_Allign;
wire [35:0] zout_Special,zout_Allign;
wire [7:0] difference_Special;
wire [27:0] sum_AddState,sum_NormaliseSum;
wire [31:0] FinalSum_Idle1,FinalSum_Idle2,FinalSum_Idle3;
wire [7:0] InsTagSpecial,InsTagAllign,InsTagAdder,InsTagNormaliseAdder;
SpecialAddProcess Add1 (
.z_preSpecial(z_preprocess),
.Opcode(Opcode),
.cin_Special(a_adder),
.zin_Special(b_adder),
.InsTagIn(InsTagIn),
.clock(clock),
.idle_Special(idle_Special),
.difference_Special(difference_Special),
.cout_Special(cout_Special),
.zout_Special(zout_Special),
.sout_Special(sout_Special),
.Opcode_Special(Opcode_Special),
.z_postSpecial(z_postSpecial),
.InsTagSpecial(InsTagSpecial)
);
AllignAdderProcess Add2 (
.z_postSpecial(z_postSpecial),
.Opcode_Special(Opcode_Special),
.idle_Special(idle_Special),
.cout_Special(cout_Special),
.zout_Special(zout_Special),
.sout_Special(sout_Special),
.difference_Special(difference_Special),
.InsTagSpecial(InsTagSpecial),
.clock(clock),
.idle_Allign(idle_Allign),
.cout_Allign(cout_Allign),
.zout_Allign(zout_Allign),
.sout_Allign(sout_Allign),
.Opcode_Allign(Opcode_Allign),
.z_postAllign(z_postAllign),
.InsTagAllign(InsTagAllign)
);
AddProcess Add3 (
.z_postAllign(z_postAllign),
.Opcode_Allign(Opcode_Allign),
.idle_Allign(idle_Allign),
.cout_Allign(cout_Allign),
.zout_Allign(zout_Allign),
.sout_Allign(sout_Allign),
.InsTagAllign(InsTagAllign),
.clock(clock),
.idle_AddState(idle_AddState),
.sout_AddState(sout_AddState),
.sum_AddState(sum_AddState),
.Opcode_AddState(Opcode_AddState),
.z_postAddState(z_postAddState),
.InsTagAdder(InsTagAdder)
);
NormaliseAdderProcess Add4 (
.z_postAddState(z_postAddState),
.Opcode_AddState(Opcode_AddState),
.idle_AddState(idle_AddState),
.sout_AddState(sout_AddState),
.sum_AddState(sum_AddState),
.InsTagAdder(InsTagAdder),
.clock(clock),
.idle_NormaliseSum(idle_NormaliseSum),
.sout_NormaliseSum(sout_NormaliseSum),
.sum_NormaliseSum(sum_NormaliseSum),
.Opcode_NormaliseSum(Opcode_NormaliseSum),
.z_postNormaliseSum(z_postNormaliseSum),
.InsTagNormaliseAdder(InsTagNormaliseAdder)
);
PackAdderProcess Add5 (
.z_postNormaliseSum(z_postNormaliseSum),
.Opcode_NormaliseSum(Opcode_NormaliseSum),
.idle_NormaliseSum(idle_NormaliseSum),
.sout_NormaliseSum(sout_NormaliseSum),
.sum_NormaliseSum(sum_NormaliseSum),
.InsTagNormaliseAdder(InsTagNormaliseAdder),
.clock(clock),
.sout_PackSum(FinalSum),
.Done(Done),
.z_postPack(z_postprocess),
.Opcode_Pack(Opcode_out),
.InsTagPack(InsTagOut)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int M = 2005; pair<pair<int, int>, pair<int, int> > adj[N]; int dp[M]; vector<int> way[M]; bool cmp(pair<pair<int, int>, pair<int, int> > a, pair<pair<int, int>, pair<int, int> > b) { return a.second.second < b.second.second; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; for (int i = 1; i <= n; i++) { int t, d, p; cin >> t >> d >> p; adj[i] = make_pair(make_pair(t, i), make_pair(p, d)); } sort(adj + 1, adj + 1 + n, cmp); for (int i = 1; i <= n; i++) { for (int j = adj[i].second.second - 1; j >= adj[i].first.first; j--) { if (dp[j] < dp[j - adj[i].first.first] + adj[i].second.first) { dp[j] = dp[j - adj[i].first.first] + adj[i].second.first; way[j] = way[j - adj[i].first.first]; way[j].emplace_back(adj[i].first.second); } } } int ans1 = 0; vector<int> ans2; for (int i = 0; i <= M - 1; i++) { if (dp[i] > ans1) { ans1 = dp[i]; ans2 = way[i]; } } cout << ans1 << n << ans2.size() << n ; for (auto op : ans2) { cout << op << ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__AND4B_BEHAVIORAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire D not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int in[201000]; int main() { int n; scanf( %d , &n); for (int i = 0; i < (n); i++) { scanf( %d , &in[i]); in[i] += i; } sort(in, in + n); for (int i = 0; i < (n - 1); i++) { if (in[i] == in[i + 1]) { puts( :( ); return 0; } } for (int i = 0; i < (n); i++) printf( %d%c , in[i] - i, ((i == n - 1) ? n : )); }
|
// File name : DebouncerWithoutLatch.v
// Written by : Jianjian Song
// debouncing an input switch
//if (Switch==1) delay a bit and test again. if (switch==1) output is 1
//else output is 0
//visa verse
`timescale 1ns / 1ps
module DebouncerWithoutLatch(InputPulse, DebouncedOuput, Reset, CLOCK) ;
input InputPulse, Reset, CLOCK;
output reg DebouncedOuput;
parameter State0=0, State1=1, State2=2, State3=3;
reg [1:0] State, NextState;
wire Timeout;
reg ClearTimer;
always @ (posedge CLOCK) begin
if(Reset==1) State <= 0;
else State<=NextState;
case (State)
0: begin DebouncedOuput<=0; ClearTimer<=1; end //timer cleared
1: begin DebouncedOuput<=0; ClearTimer<=0; end //timer starts running
2: begin DebouncedOuput<=0; ClearTimer<=0; end
3: begin DebouncedOuput<=1; ClearTimer<=0; end
endcase
end
always@(State or InputPulse or Timeout)
case (State)
0: if (InputPulse==0) NextState<=State0; else NextState<=State1;
1: if (Timeout==0) NextState<=State1; else NextState<=State2;
2: if (InputPulse==0) NextState<=State0; else NextState<=State3;
3: if (InputPulse==0) NextState<=State0; else NextState<=State3;
endcase
//DelayLoop(MR,Timeout,Clock) ;
DelayLoop Timer(ClearTimer,Timeout,CLOCK);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_TB_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O311AI_PP_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, num[100100]; inline int as(int u) { int a, b; if (num[u]) return num[u]; printf( ? %d n , u); fflush(stdout); scanf( %d , &a); return num[u] = a; } inline void pd(int u) { if (as(u) == as(u + m)) { printf( ! %d n , u); exit(0); } } int main() { int i, j, l, r, mid, p, q; cin >> n; m = n / 2; if (m % 2) { puts( ! -1 ); return 0; } as(1), as(m + 1), pd(1); l = 2, r = m; for (; l <= r;) { mid = ((l + r) >> 1); p = as(mid), q = as(mid + m); pd(mid); if ((p > q) ^ (num[1] > num[m + 1])) r = mid - 1; else l = mid + 1; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d, x, y, g, h, i, j, k, n, t, z = 0, l, r, u; cin >> t; while (t--) { cin >> n; for (i = 0; i < n; i++) cout << 1 << ; cout << endl; } }
|
(****************************************************************************)
(* Copyright 2020 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Vectors.Vector.
Require Import ExtLib.Structures.Monads.
Import VectorNotations MonadNotation.
Require Import Cava.Core.CavaClass.
Require Import Cava.Core.Signal.
(******************************************************************************)
(* Inductive to capture circuit's sequential structure *)
(******************************************************************************)
Section WithCava.
Context `{semantics:Cava}.
Inductive Circuit : Type -> Type -> Type :=
| Comb : forall {i o}, (i -> cava o) -> Circuit i o
| Compose : forall {i t o}, Circuit i t -> Circuit t o -> Circuit i o
| First : forall {i o t}, Circuit i o -> Circuit (i * t) (o * t)
| Second : forall {i o t}, Circuit i o -> Circuit (t * i) (t * o)
| LoopInitCE :
forall {i o : Type} {s : SignalType} (resetval : combType s),
Circuit (i * signal s) (o * signal s) ->
Circuit (i * signal Bit) o
| DelayInitCE :
forall {t} (resetval : combType t),
Circuit (signal t * signal Bit) (signal t)
.
(* Internal state of the circuit (register values) *)
Fixpoint circuit_state {i o} (c : Circuit i o) : Type :=
match c with
| Comb _ => unit
| Compose f g => circuit_state f * circuit_state g
| First f => circuit_state f
| Second f => circuit_state f
| @LoopInitCE i o s _ f => circuit_state f * combType s
| @DelayInitCE t _ => combType t
end.
(* The state of the circuit after a reset *)
Fixpoint reset_state {i o} (c : Circuit i o) : circuit_state c :=
match c as c return circuit_state c with
| Comb _ => tt
| Compose f g => (reset_state f, reset_state g)
| First f => reset_state f
| Second f => reset_state f
| LoopInitCE resetval f => (reset_state f, resetval)
| DelayInitCE resetval => resetval
end.
(* Loop with no enable; set enable to always be true *)
Definition LoopInit {i o s} (resetval : combType s)
(body : Circuit (i * signal s) (o * signal s))
: Circuit i o :=
Compose (Comb (fun i => ret (i, constant true))) (LoopInitCE resetval body).
(* Delay with no enable; set enable to always be true *)
Definition DelayInit {t} (resetval : combType t)
: Circuit (signal t) (signal t) :=
Compose (Comb (fun i => ret (i, constant true))) (DelayInitCE resetval).
(* Loop with the default signal as its reset value *)
Definition LoopCE {i o s}
: Circuit (i * signal s) (o * signal s) -> Circuit (i * signal Bit) o :=
LoopInitCE (defaultCombValue s).
(* Delay with the default signal as its reset value *)
Definition DelayCE {t}
: Circuit (signal t * signal Bit) (signal t) :=
DelayInitCE (defaultCombValue t).
(* Loop with the default signal as its reset value and no enable *)
Definition Loop {i o s}
(body : Circuit (i * signal s) (o * signal s))
: Circuit i o :=
Compose (Comb (fun i => ret (i, constant true))) (LoopInitCE (defaultCombValue s) body).
(* Delay with the default signal as its reset value and no enable *)
Definition Delay {t} : Circuit (signal t) (signal t) :=
Compose (Comb (fun i => ret (i, constant true))) (DelayInitCE (defaultCombValue t)).
End WithCava.
Module Notations.
Infix ">==>" := Compose (at level 40, left associativity).
End Notations.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_SYMBOL_V
`define SKY130_FD_SC_HVL__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int debug_ = 0; const int maxn = 200000; const long long inf = 998244353; int unum[33], dnum[33]; long long dp[33][2][2][2]; long long dfs(int pos, int u, int e, int d) { if (pos == -1) { return 2 - e; } if (dp[pos][u][e][d] != -1) { return dp[pos][u][e][d]; } long long& ret = dp[pos][u][e][d]; ret = 0; for (int i = 0; i < 3; ++i) { int x = i / 2, y = i % 2; if (x == 1 && u && unum[pos] == 0) { continue; } if (y == 1 && e) { continue; } if (y == 0 && d && dnum[pos] == 1) { continue; } int nu = (u && x == unum[pos]); int ne = (e && y == x); int nd = (d && y == dnum[pos]); ret += dfs(pos - 1, nu, ne, nd); } return ret; } int main() { int tes, u, d; cin >> tes; while (tes--) { cin >> d >> u; for (int i = 0; i < 31; ++i) { dnum[i] = (d >> i) & 1; unum[i] = (u >> i) & 1; } memset(dp, -1, sizeof(dp)); cout << dfs(32, 1, 1, 1) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100100]; int d[100100]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i <= n; i++) { d[i] = 100100; } d[0] = 0; for (int i = 0; i < n; i++) { int l = 0; int r = n - 1; while (l < r) { int m = (l + r + 1) / 2; if (d[m] > a[i]) { r = m - 1; } else { l = m; } } d[r + 1] = a[i]; } int ans = 0; for (int i = 0; i <= n; i++) { if (d[i] < 100100) { ans = i; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 2; bitset<N> equa[N], value[N]; int ans[N], hehe[N]; signed main() { ios::sync_with_stdio(0); cin.tie(0); int n, m, i, j, k, l, num = 0; cin >> n >> m; for (i = 0; i < n; i++) { value[2 * i][2 * i] = 1; value[2 * i + 1][2 * i + 1] = 1; } for (i = 0; i < m; i++) { string s; char x; cin >> s; if (s == mix ) { cin >> j; for (k = 0; k < j; k++) { cin >> l; l--; equa[num] ^= value[2 * l]; equa[num + 1] ^= value[2 * l + 1]; } cin >> x; if (x == R ) { ans[num + 1] = 1; } if (x == Y ) { ans[num] = 1; } if (x == B ) { ans[num] = ans[num + 1] = 1; } num += 2; } if (s == RB ) { cin >> j; for (k = 0; k < j; k++) { cin >> l; l--; value[2 * l] ^= value[2 * l + 1]; } } if (s == RY ) { cin >> j; for (k = 0; k < j; k++) { cin >> l; l--; swap(value[2 * n], value[2 * l]); swap(value[2 * l], value[2 * l + 1]); swap(value[2 * l + 1], value[2 * n]); } } if (s == YB ) { cin >> j; for (k = 0; k < j; k++) { cin >> l; l--; value[2 * l + 1] ^= value[2 * l]; } } } int now = -1; for (i = 0; i < 2 * n; i++) { for (j = now + 1; j < num; j++) { if (equa[j][i]) { now++; swap(equa[j], equa[now]); swap(ans[j], ans[now]); for (k = 0; k < num; k++) { if (equa[k][i] && k != now) { equa[k] ^= equa[now]; ans[k] ^= ans[now]; } } break; } } } for (i = now + 1; i < num; i++) { assert(!equa[i].count()); if (ans[i] == 1) { cout << NO ; return 0; } } for (i = now; i > -1; i--) { for (j = 2 * n - 1; j > -1; j--) { if (equa[i][j]) { if (equa[i].count() == 1) { equa[i][j] = 0; hehe[j] = ans[i]; } else { equa[i][j] = 0; for (k = j; k > -1; k--) { if (equa[i][k]) { break; } } for (l = 0; l < i; l++) { if (equa[l][k]) { equa[l] ^= equa[i]; ans[l] ^= ans[i]; } } } } } } cout << YES n ; for (i = 0; i < n; i++) { if (hehe[2 * i] && hehe[2 * i + 1]) { cout << B ; } if (hehe[2 * i] && !hehe[2 * i + 1]) { cout << Y ; } if (!hehe[2 * i] && hehe[2 * i + 1]) { cout << R ; } if (!hehe[2 * i] && !hehe[2 * i + 1]) { cout << . ; } } }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// sbram_m20k.v: Single-bit width RAM using Altera's M20K //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module sbram_m20k
#( parameter DEPTH = 16384, // read depth > 16K
parameter IZERO = 1 ) // initialize to zeros
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(DEPTH)-1:0] wAddr , // write address
input wData , // write data
input [`log2(DEPTH)-1:0] rAddr , // read address
output rData ); // read data
localparam ADDRW = `log2(DEPTH); //
localparam nM20K = DEPTH/16384;
wire [nM20K-1:0] rDataAll;
reg [nM20K-1:0] M20KSel;
// binary to one-hot
always @(*) begin
M20KSel = 0 ;
M20KSel[wAddr[ADDRW-1:14]] = wEnb;
end
// generate and instantiate mixed-width BRAMs
genvar gi;
generate
for (gi=0 ; gi<nM20K ; gi=gi+1) begin: BRAMgi
mwram_m20k #( .WR_DW( 1 ), // write width
.RD_DW( 1 ), // read width
.IZERO( IZERO )) // initialize to zeros
mwram_m20k_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( M20KSel[gi] ), // write enable
.wAddr( wAddr[13:0] ), // write address [13:0]
.wData( wData ), // write data
.rAddr( rAddr[13:0] ), // read address [ 13:0]
.rData( rDataAll[gi] )); // read data [31:0]
end
endgenerate
assign rData = rDataAll[rAddr[ADDRW-1:14]];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int a, b; cin >> a >> b; for (int i = 1; i <= a; ++i) cout << i << ; cout << a + b + 1; for (int i = a + b; i > a; --i) cout << << i; return 0; }
|
// DESCRIPTION: Verilator: Test for using DPI as general accessors
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// SPDX-License-Identifier: CC0-1.0
//
// Contributed by Jeremy Bennett and Jie Xul
//
// This test exercises the use of DPI to access signals and registers in a
// module hierarchy in a uniform fashion. See the discussion at
//
// https://github.com/verilator/verilator/issues/1750
//
// We need to test read and write access to:
// - scalars
// - vectors
// - array elements
// - slices of vectors or array elements
//
// We need to test that writing to non-writable elements generates an error.
//
// This Verilog would run forever. It will be stopped externally by the C++
// instantiating program.
// Define the width of registers and size of memory we use
`define REG_WIDTH 8
`define MEM_SIZE 256
// Top module defines the accessors and instantiates a sub-module with
// substantive content.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`include "t_dpi_accessors_macros_inc.vh"
`include "t_dpi_accessors_inc.vh"
// Put the serious stuff in a sub-module, so we can check hierarchical
// access works OK.
test_sub i_test_sub (.clk (clk));
endmodule // t
// A sub-module with all sorts of goodies we would like to access
module test_sub (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer i; // General counter
// Elements we would like to access from outside
reg a;
reg [`REG_WIDTH - 1:0] b;
reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0];
wire c;
wire [`REG_WIDTH - 1:0] d;
reg [`REG_WIDTH - 1:0] e;
reg [`REG_WIDTH - 1:0] f;
// Drive our wires from our registers
assign c = ~a;
assign d = ~b;
// Initial values for registers and array
initial begin
a = 0;
b = `REG_WIDTH'h0;
for (i = 0; i < `MEM_SIZE; i++) begin
mem[i] = i [`REG_WIDTH - 1:0];
end
e = 0;
f = 0;
end
// Wipe out one memory cell in turn on the positive clock edge, restoring
// the previous element. We toggle the wipeout value.
always @(posedge clk) begin
mem[b] <= {`REG_WIDTH {a}};
mem[b - 1] <= b - 1;
a <= ~a;
b <= b + 1;
end
endmodule // test_sub
|
module fmrv32im_mul
(
input RST_N,
input CLK,
input INST_MUL,
input INST_MULH,
input INST_MULHSU,
input INST_MULHU,
input [31:0] RS1,
input [31:0] RS2,
output WAIT,
output READY,
output [31:0] RD
);
wire inst_mul, inst_mulh;
wire inst_rs1_signed, inst_rs2_signed;
reg [32:0] w_rs1, w_rs2;
reg [63:0] rslt;
reg rslt_high, rslt_active;
assign inst_mul = INST_MUL | INST_MULH | INST_MULHSU | INST_MULHU;
assign inst_mulh = INST_MULH | INST_MULHSU | INST_MULHU;
assign inst_rs1_signed = INST_MULH | INST_MULHSU;
assign inst_rs2_signed = INST_MULH;
always @(*) begin
if(inst_rs1_signed) begin
w_rs1 <= $signed(RS1);
end else begin
w_rs1 <= $unsigned(RS1);
end
if(inst_rs2_signed) begin
w_rs2 <= $signed(RS2);
end else begin
w_rs2 <= $unsigned(RS2);
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt_high <= 0;
rslt_active <= 0;
end else begin
rslt_high <= inst_mulh;
rslt_active <= inst_mul;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt <= 0;
end else begin
rslt <= $signed(w_rs1) * $signed(w_rs2);
end
end
assign RD = (rslt_high)?rslt[63:32]:rslt[31:0];
assign READY = rslt_active;
assign WAIT = 0;
endmodule // fmrv32im_mul
|
#include <bits/stdc++.h> int scan() { int noRead = 0; char p = getchar(); for (; p < 33;) { p = getchar(); } while (p > 32) { noRead = (noRead << 3) + (noRead << 1) + (p - 0 ); p = getchar(); } return noRead; } long long int lscan() { long long int noRead = 0; char p = getchar(); for (; p < 33;) { p = getchar(); } while (p > 32) { noRead = (noRead << 3) + (noRead << 1) + (p - 0 ); p = getchar(); } return noRead; } using namespace std; int dp[501][501]; int vec[501]; int f(int l, int r) { if (l > r) return 0; if (l == r) return 1; if (dp[l][r] != -1) return dp[l][r]; int &ans = dp[l][r]; ans = 100001; ans = min(ans, 1 + f(l + 1, r)); for (int i = l + 2; i <= r; ++i) { if (vec[l] == vec[i]) { ans = min(ans, f(l + 1, i - 1) + f(i + 1, r)); } } if (vec[l] == vec[l + 1]) ans = min(ans, 1 + f(l + 2, r)); return ans; } int main(void) { int n = scan(); for (int i = 0; i < n; ++i) vec[i] = scan(); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) dp[i][j] = -1; printf( %d , f(0, n - 1)); return 0; }
|
module KeyExpansion
(
key,
expandedKey
);
localparam NR = 10;
input [127:0] key;
output [128*(NR+1)-1:0] expandedKey;
wire [31:0] w[4*(NR+1)-1:0];
wire [31:0] t[NR-1:0];
wire [7:0] RCon[NR-1:0];
wire [31:0] rotWord[NR-1:0];
wire [31:0] Q[NR-1:0];
wire [95:0] unused[NR-1:0];
assign RCon[0] = 8'h01;
assign RCon[1] = 8'h02;
assign RCon[2] = 8'h04;
assign RCon[3] = 8'h08;
assign RCon[4] = 8'h10;
assign RCon[5] = 8'h20;
assign RCon[6] = 8'h40;
assign RCon[7] = 8'h80;
assign RCon[8] = 8'h1b;
assign RCon[9] = 8'h36;
genvar i;
generate
for(i=0;i<4*(NR+1);i=i+1)
begin:EXPANDKEY
assign expandedKey[32*(i+1)-1:32*i] = w[i];
end
endgenerate
generate
for(i=0;i<4*(NR+1);i=i+1) begin:NR_W
if(i<4) begin:INITIAL
assign w[i] = key[32*(i+1)-1:32*i];
end else begin:NEXT
if(i%4==0) begin:FIRST
assign w[i] = w[i-4] ^ t[i/4-1];
end else begin:THEN
assign w[i] = w[i-1] ^ w[i-4];
end
end
end
endgenerate
generate
for(i=0;i<NR;i=i+1) begin:COREKEY
assign rotWord[i] = {w[4+4*i-1][7:0], w[4+i*4-1][31:8]};
SubBytes a(.x({rotWord[i], 96'b0}), .z({Q[i], unused[i]}));
assign t[i] = {Q[i][31:8], RCon[i] ^ Q[i][7:0]};
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$NR_pp$PKG$s (
Q ,
D ,
CLK_N ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK_N ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NR_PP_PKG_S_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
// Josh Sackos
//
// Create Date: 07/26/2012
// Module Name: slaveSelect
// Project Name: PmodACL_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: A simple module involving the switching of the slave select line
// during transmission and idle states.
//
// Inputs:
// rst User input Reset
// transmit signal from SPImaster causing ss line to go low
// ( enable )
// done signal from SPIinterface causing ss line to go
// high ( disable )
//
// Outputs:
// ss ss output to ACL
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added comments and modified code (Josh Sackos)
////////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module slaveSelect(
rst,
clk,
transmit,
done,
ss
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input rst;
input clk;
input transmit;
input done;
output ss;
reg ss = 1'b1;
// ===================================================================================
// Implementation
// ===================================================================================
//-----------------------------------------------
// Generates Slave Select Signal
//-----------------------------------------------
always @(posedge clk)
begin: ssprocess
begin
//reset state, ss goes high ( disabled )
if (rst == 1'b1)
ss <= 1'b1;
//if transmitting, then ss goes low ( enabled )
else if (transmit == 1'b1)
ss <= 1'b0;
//if done, then ss goes high ( disabled )
else if (done == 1'b1)
ss <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct comp { bool operator()(const vector<long long>& lhs, const vector<long long>& rhs) const { return lhs[0] > rhs[0] || (lhs[0] == rhs[0] && lhs[2] > rhs[2]) || (lhs[0] == rhs[0] && lhs[2] == rhs[2] && lhs[1] > rhs[1]); } }; vector<long long> t; vector<long long> ans; priority_queue<vector<long long>, vector<vector<long long> >, comp> events; queue<long long> q; set<long long> inq; priority_queue<long long, vector<long long>, greater<long long> > ready; bool clear(long long index) { auto it = inq.lower_bound(index); if (it == inq.end()) return inq.empty(); return it == inq.begin(); } int32_t main() { ios::sync_with_stdio(false); long long n, p; cin >> n >> p; t.resize(n); ans.resize(n); for (long long i = 0; i < n; i++) cin >> t[i]; for (long long i = 0; i < n; i++) events.push({t[i], i, 1}); while (!events.empty()) { vector<long long> a = events.top(); events.pop(); long long status = a[2], index = a[1], time = a[0]; if (status == 1) { if (clear(index)) { if (q.empty()) events.push({time + p, index, 2}); q.push(index); inq.insert(index); } else ready.push(index); } else { ans[index] = time; q.pop(); inq.erase(index); if (!ready.empty() && clear(ready.top())) { long long nextIndex = ready.top(); ready.pop(); q.push(nextIndex); inq.insert(nextIndex); } if (!q.empty()) { long long nextIndex = q.front(); events.push({time + p, nextIndex, 2}); } } } for (long long i = 0; i < n; i++) cout << ans[i] << ; }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: read_req_wrapper
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: A wrapper which contains a RAM with read request information
// (dualport_32x32_compram) and a small shadow RAM which qualifies the
// entries in the dualport_32x32_compram
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module read_req_wrapper(
input clk,
input rst,
input transferstart, // Jiansong: control signal for transfer recovering
input [4:0] tx_waddr,
input [31:0] tx_wdata,
input tx_we,
input [4:0] rx_waddr,
input [31:0] rx_wdata,
input rx_we,
input [4:0] rx_raddr,
output [31:0] rx_rdata,
input pending_comp_done, /// Jiansong: for what purpose?
output [31:0] completion_pending,
output comp_timeout
);
reg we;
reg [4:0] wr_addr;
reg [31:0] wr_data;
reg [4:0] wr_addr_r;
wire [4:0] wr_addr_rst;
reg pending_data;
//32x32 dual-port distributed ram built with CoreGen
//this ram holds completion information for the RX engine
//provided from the TX engine
//The tag from outgoing non-posted memory read requests is
//used as the address to the ram. The data stored in the
//32-bit data window is as follows
// bits 21 - 0 = ddr2 destination address (6 LSBs not stored)
// 31 - 22 = length in DWORDs of the request
//
//Both the RX and TX engines have write access to this ram
//The TX engine writes the initial information and the RX engine
//updates the DDR2 address as the completion packets are serviced
//In order to share the write port a simple protocol is followed
// 1. TX engine has priority over RX engine
// 2. TX engine writes are always a single-cycle and cannot occur in
// consecutive cycles
// 3. RX engine writes are always double-cycle
always@(posedge clk) begin
if (rst | (~transferstart))
wr_addr_r[4:0] <= wr_addr_r[4:0] + 5'b00001;
else
wr_addr_r[4:0] <= 5'b00000;
end
assign wr_addr_rst = wr_addr_r;
/// Jiansong: reset logic added. clear the rams
// always@(*)begin
always@(posedge clk)begin
if(rst | (~transferstart))begin
wr_addr[4:0] <= wr_addr_rst[4:0];
we <= 1'b1;
wr_data[31:0] <= 32'h0000_0000;
pending_data <= 1'b0;
end else if(tx_we)begin
wr_addr[4:0] <= tx_waddr[4:0];
we <= tx_we;
wr_data[31:0] <= tx_wdata[31:0];
pending_data <= 1'b1;
end else begin
wr_addr[4:0] <= rx_waddr[4:0];
we <= rx_we;
wr_data[31:0] <= rx_wdata[31:0];
pending_data <= ~pending_comp_done;
end
end
dualport_32x32_compram dualport_32x32_compram_inst(
.a(wr_addr[4:0]),
.d(wr_data[31:0]),
.dpra(rx_raddr[4:0]),
.clk(clk),
.we(we),
.spo(),
.dpo(rx_rdata[31:0])
);
//A small 32x1 shadow ram to qualify the entries in the dualport
//This ram has an addressable write port, the read data port is not
//addressable, i.e. all 32 bits are present. The data stored represents
//whether the dual-port ram contains a valid entry or not. The tx engine
//sets the bit when writing to the dualport ram - the rx engine clears it
//when the final completion packet has been received.
//Same protocol rules as dual-port ram for writes
pending_comp_ram_32x1 pending_comp_ram_32x1_inst(
.clk(clk),
// .d_in((tx_we)?1'b1:~pending_comp_done),
.d_in(pending_data),
.addr(wr_addr[4:0]),
.we(we),
.d_out(completion_pending[31:0])
);
completion_timeout completion_timeout_inst(
.clk(clk),
.rst(rst | (~transferstart)),
.pending_req(completion_pending[31:0]),
.comp_timeout(comp_timeout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int ans = 0; string s; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 ) ans += 10; else if (s[i] == A ) ans += 1; else ans += s[i] - 0 ; } cout << ans; return 0; }
|
#include <bits/stdc++.h> int main() { int x, y, x1 = 0, y1 = 0, n, k = 0; do { scanf( %d%d , &x, &n); } while (x < 1 || n < 1 || n > 100000 || x > 100000); y = x; if ((x == 4 && n == 2) || (x > 5 && n < 4) || x <= n || n < 4) { printf( %d n , (x == n && x != 1) ? k = 5 : n / x >= 2 ? k = 1 : x < n ? k = 3 : (x == 4 && n == 3) ? k = 9 : ((x == 5 && n == 3) || (x == 3 && n == 2)) ? k = 11 : k = -1); exit(0); } y = x -= n - 2; y1 = x1 += n - 2; k = 4; if (x <= n / 2) { y1 = x1 += x; y = x -= x; printf( %d , k + 1); exit(0); } while (y > n) { y = x -= n / 2 - 1; y1 = x1 += n / 2 - 1; k += 2; } y == n ? k += 5 : k += 3; y1 = x1 += x; y = x -= x; printf( %d , k); return 0; }
|
//==================================================================================================
// Filename : arbite.v
// Created On : 2015-04-09 10:25:59
// Last Modified : 2015-05-24 20:54:42
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Arbiter: N masters, 1 slaves.
// Priority: Master with the highest number.
// Non registered version.
//
// Based on the Wishbone arbiter module from the ORPSOC-CORE project.
// Author: Olof Kindgren,
//==================================================================================================
module arbiter #(
parameter nmasters = 2
)(
input clk,
input rst,
// Master
input [32*nmasters-1:0] master_address, // Slave's address
input [32*nmasters-1:0] master_data_i, // Data from Master
input [4*nmasters-1:0] master_wr, // Byte selector
input [nmasters-1 : 0] master_enable, // Enable operation
output [31:0] master_data_o, // Data to Master
output [nmasters-1 : 0] master_ready, // Ready signal to Master
output [nmasters-1 : 0] master_error, // Error signal
// slave
input [31:0] slave_data_i, // Data from slave
input slave_ready, // Ready signal from Slave
input slave_error, // Error signal
output [31:0] slave_address, // Address to Slave
output [31:0] slave_data_o, // Data to Slave
output [3:0] slave_wr, // Byte selector
output slave_enable // Enable operation
);
//--------------------------------------------------------------------------
// Local parameters
//--------------------------------------------------------------------------
localparam integer clog_nm = (nmasters <= 1 << 1) ? 1 :
(nmasters <= 1 << 2) ? 2 :
(nmasters <= 1 << 3) ? 3 :
(nmasters <= 1 << 4) ? 4 :
(nmasters <= 1 << 5) ? 5 :
(nmasters <= 1 << 6) ? 6 :
(nmasters <= 1 << 7) ? 7 :
(nmasters <= 1 << 8) ? 8 :
(nmasters <= 1 << 9) ? 9 :
(nmasters <= 1 << 10) ? 10 :
(nmasters <= 1 << 11) ? 11 :
(nmasters <= 1 << 12) ? 12 :
(nmasters <= 1 << 13) ? 13 :
(nmasters <= 1 << 14) ? 14 :
(nmasters <= 1 << 15) ? 15 :
(nmasters <= 1 << 16) ? 16 :
(nmasters <= 1 << 17) ? 17 :
(nmasters <= 1 << 18) ? 18 :
(nmasters <= 1 << 19) ? 19 : 20;
localparam master_sel_bits = nmasters > 1 ? clog_nm : 1;
//--------------------------------------------------------------------------
// Registers & wires
//--------------------------------------------------------------------------
wire [master_sel_bits-1:0] master_sel; // Index of the master with priority: using the master enable signals
wire [master_sel_bits-1:0] master_sel2; // Index of the selected master: using the grant signal.
reg [nmasters-1:0] grant;
reg [nmasters-1:0] selected;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign master_sel = fl1(master_enable, nmasters);
assign master_sel2 = fl1(grant, nmasters);
assign slave_address = master_address[master_sel2*32+:32];
assign slave_data_o = master_data_i[master_sel2*32+:32];
assign slave_wr = master_wr[master_sel2*4+:4];
assign slave_enable = master_enable[master_sel2];
assign master_data_o = slave_data_i;
assign master_ready = grant & {nmasters{slave_ready}};
assign master_error = grant & {nmasters{slave_error}};
//--------------------------------------------------------------------------
// Function:
// Find Last 1 - Start from LSB and count upwards, returns 0 when no bit set
//--------------------------------------------------------------------------
function integer fl1;
input integer in;
input integer width;
integer i;
begin
fl1 = 0;
for (i = 0; i < width; i=i+1) begin
if (in[i])
fl1 = i;
end
end
endfunction
//--------------------------------------------------------------------------
// Select the master
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
selected <= 0;
end
else begin
selected <= grant & master_enable;
end
end
always @(*) begin
if (selected == 0) begin
grant <= (1'b1 << master_sel);
end
else begin
grant <= selected;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_1_0 (
dout
);
output wire [1-1 : 0] dout;
xlconstant #(
.CONST_VAL(1'd1),
.CONST_WIDTH(1)
) inst (
.dout(dout)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_FUNCTIONAL_PP_V
|
/***************************************************************************
* pcx2mb_entry.v: A single buffer entry for the SPARC PCX to MicroBlaze
* FSL Fifo. This register entry will be instantiated 9 times.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: /import/bw-rainbow/rainbow_cvs/niagara/design/sys/iop/ccx2mb/rtl/pcx2mb_entry.v,v 1.2 2007/04/12 00:08:31 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_entry (
// Outputs
e_data,
e_active,
e_dest,
// Inputs
rclk,
reset_l,
any_req_pa,
spc_pcx_data_pa,
req_dest_pa,
req_atom_pa,
any_req_px,
req_dest_px,
req_atom_px,
load_data,
prev_data,
prev_active,
prev_dest,
next_active
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH = 5;
`else
parameter PCX_REQ_WIDTH = 2;
`endif
output [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
output e_active;
output [4:0] e_dest;
input rclk;
input reset_l;
input any_req_pa;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [4:0] req_dest_pa;
input req_atom_pa;
input any_req_px;
input [4:0] req_dest_px;
input req_atom_px;
input load_data;
input [`PCX_WIDTH+PCX_REQ_WIDTH:0] prev_data;
input prev_active;
input [4:0] prev_dest;
input next_active;
reg [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
reg e_active;
reg [4:0] e_dest;
// Code for entry here. If a new request is received while the next entry
// is active, and this entry is not active, it will be placed into this one.
always @(posedge rclk) begin
if (!reset_l) begin
e_data <= {`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}};
e_active <= 1'b0;
e_dest <= 5'b00000;
end
else if (load_data && prev_active) begin
e_data <= prev_data;
e_active <= prev_active;
e_dest <= prev_dest;
end
else if (any_req_pa && (
(next_active && !load_data && !e_active) ||
(next_active && load_data && e_active && !prev_active)))
begin
`ifdef PCX2MB_5_BIT_REQ
e_data <= { req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
e_data <= { req_dest_pa[4], (|req_dest_pa[3:0]), req_atom_pa,
spc_pcx_data_pa};
`endif
e_active <= 1'b1;
e_dest <= req_dest_pa;
end
else if (any_req_px && req_atom_px && (
(next_active && !load_data && !e_active) ||
(next_active && load_data && e_active && !prev_active)))
begin
`ifdef PCX2MB_5_BIT_REQ
e_data <= { req_dest_px[4:0], req_atom_px, spc_pcx_data_pa};
`else
e_data <= { req_dest_px[4], (|req_dest_px[3:0]), 1'b0,
spc_pcx_data_pa};
`endif
e_active <= 1'b1;
e_dest <= req_dest_px;
end
else begin
e_data <= e_data;
e_dest <= e_dest;
if (load_data && e_active) begin
e_active <= 1'b0;
end
else begin
e_active <= e_active;
end
end
end
endmodule
|
// $Id: c_reversor.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// module for reversing a set of bits
module c_reversor
(data_in, data_out);
// width of input word
parameter width = 32;
// input word
input [0:width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:connect
// reverse inputs data
assign data_out[i] = data_in[(width-1)-i];
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_v2
//SINGLE PRECISION PARAMETERS
//# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
RecursiveKOA #(.SW(SW+1), .Opt_FPGA_ASIC(0)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}), //Se le agrega el bit implicito
.Data_B_i({1'b1,Op_MY[SW-1:0]}), //Se le agrega el bit implicito
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
`timescale 1ns / 1ps
module water_let_mode_tb();
reg [31:0]clk;
reg water_in_start, water_out_start, power, start;
reg [2:0]weight;
wire [2:0]water_level;
wire water_in_end_sign, water_out_end_sign;
parameter DELAY = 10;
parameter TIME = 1000;
water_let_mode DUT (
.water_in_end_sign(water_in_end_sign),
.water_in_start(water_in_start),
.water_out_start(water_out_start),
.water_out_end_sign(water_out_end_sign),
.clk(clk),
.power(power),
.max_water_level(weight),
.start(start),
.water_level(water_level)
);
initial begin
power = 0;
clk[25] = 0;
clk[0] = 0;
start = 0;
weight = 5;
water_in_start = 0;
water_out_start = 0;
#TIME $finish;
end
always begin
#DELAY clk[25] = ~clk[25];
end
always begin
#(DELAY/DELAY) clk[0] = ~clk[0];
end
always begin
#DELAY water_in_start = 1;
#DELAY start = 1;
#DELAY power = 1;
#DELAY start = 1;
#(DELAY*5) water_in_start = 0;
#DELAY water_in_start = 1;
#(DELAY*50) water_in_start = 0;
#(DELAY) water_out_start = 1;
#(DELAY*46);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m; cin >> n >> m; map<int, int> a; long long x; for (long long i = 0; i < m; i++) { cin >> x; a[x]++; } long long mini = INT_MAX; for (long long i = 1; i <= n; i++) { if (mini > a[i]) { mini = a[i]; } } cout << mini << endl; return 0; }
|
// file: Clock70MHz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____70.000______0.000______50.0______485.714____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock70MHz,clk_wiz_v3_6,{component_name=Clock70MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock70MHz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (7),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2001; char a[MAXN][MAXN]; int n, v[MAXN], r[MAXN], c[MAXN]; int gao() { int ret = 0; memset(r, 0, sizeof(int) * n); memset(c, 0, sizeof(int) * n); for (int i = 0; i < n - 1; ++i) { for (int j = n - 1; j > i; --j) { if (a[i][j] ^ r[i] ^ c[j]) { ++ret; r[i] ^= 1; c[j] ^= 1; } } } for (int i = 0; i < n; ++i) v[i] ^= (r[i] ^ c[i]); memset(r, 0, sizeof(int) * n); memset(c, 0, sizeof(int) * n); for (int i = n - 1; i > 0; --i) { for (int j = 0; j < i; ++j) { if (a[i][j] ^ r[i] ^ c[j]) { ++ret; r[i] ^= 1; c[j] ^= 1; } } } for (int i = 0; i < n; ++i) v[i] ^= (r[i] ^ c[i]); for (int i = 0; i < n; ++i) ret += v[i]; return ret; } int main() { while (scanf( %d , &n) != EOF) { memset(v, 0, sizeof(int) * n); for (int i = 0; i < n; ++i) { scanf( %s , a[i]); for (int j = 0; j < n; ++j) a[i][j] -= 0 ; v[i] ^= (int)a[i][i]; } printf( %d n , gao()); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_2_V
`define SKY130_FD_SC_LP__DFSBP_2_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_2_V
|
// Check that dynamic arrays of packed array types are supported
module main;
typedef reg [3:0] T1;
typedef T1 [7:0] T2;
T2 foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
//==================================================================================================
// Filename : antares_mux_4_1.v
// Created On : Mon Aug 31 23:14:22 2015
// Last Modified : Sat Nov 07 12:14:18 2015
// Revision : 0.1
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : A 4-input multiplexer, with parameterizable width.
//==================================================================================================
module antares_mux_4_1 #(parameter WIDTH = 32)
(
input [1:0] select,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input [WIDTH-1:0] in3,
output reg [WIDTH-1:0] out
);
always @ ( /*AUTOSENSE*/in0 or in1 or in2 or in3 or select) begin
case (select)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
endcase // case (select)
end // always @ (...
endmodule // antares_mux_4_1
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_4_V
`define SKY130_FD_SC_LS__O2111AI_4_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111ai_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_4_V
|
#include <bits/stdc++.h> using namespace std; inline int gcd(int a, int b) { while (b > 0) { int t = a; a = b; b = t % b; } return a; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; { int i; for (i = 1; i < n; ++i) if (a[i] != a[i - 1]) break; if (i == n) { cout << (int64_t)n * (n - 1) << endl; return 0; } } int64_t ans = 0; for (int divisor = 1; divisor < n; ++divisor) { if (n % divisor > 0) continue; vector<int> max_of_rem(a.begin(), a.begin() + divisor); for (int i = divisor; i < n; ++i) if (a[i] > max_of_rem[i % divisor]) max_of_rem[i % divisor] = a[i]; int lim = n; for (int left = 0; left < lim;) { int offs; for (offs = 0; offs < n - 1 && a[(left + offs) % n] == max_of_rem[(left + offs) % divisor]; ++offs) ; if (offs == 0) { ++left; continue; } int goffs = offs; if (left == 0) { while (left + offs < lim && a[lim - 1] == max_of_rem[(lim - 1) % divisor]) --lim; offs += n - lim; } for (int i = divisor; i <= offs; i += divisor) { if (gcd(n, i) == divisor) { ans += offs == n ? n : offs - i + 1; } } left += goffs; } } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_4_V
`define SKY130_FD_SC_LP__O41A_4_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_4_V
|
// file: sdram_clk_gen_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module sdram_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
#(PER1*50);
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
sdram_clk_gen_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
/*
I seem to have found a problem with the $monitor task/events.
(this is probably related to bug 399)
The problem only seems to arise in vvp mode and not in vvm.
Problem: $monitor seems to lose both the first and last time steps.
A complete copy of the run follows with source appended at the end.
(The correct output from vvm is shown in the last run)
This file compiles and produces the problem.
*/
/*
bubba> uname -a
Linux bubba 2.2.15-4mdk #1 Wed May 10 15:31:30 CEST 2000 i686 unknown
bubba> iverilog -V
Icarus Verilog version 0.6
Copyright 1998-2002 Stephen Williams
$Name: $
bubba> iverilog -Wall -tvvp stim.v
bubba> a.out
Time = 1 a = 1
bubba> iverilog -Wall -tvvm stim.v
bubba> a.out
Time = 0 a = 0
Time = 1 a = 1
Time = 2 a = 0
*/
// -------------------------------------------------------------------------stim
module stim;
reg a;
initial begin
a = 0;
#1 a = 1;
#1 a = 0;
end
initial begin
$monitor("Time = %0d a = %b", $time, a);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; vector<int> a; vector<int> b; vector<int> c; vector<vector<int> > g; int n, m, k; int dp[5005][5005]; int solve(int at, int homens) { if (at == n) { return 0; } if (dp[at][homens] != -1) { return dp[at][homens]; } if (a[at] > homens) { return dp[at][homens] = -INF; } int novoHomens = homens + b[at]; int resposta = solve(at + 1, novoHomens); int valor = 0; int quant = 0; for (int viz : g[at]) { quant++; valor += viz; if (novoHomens - quant >= 0) { resposta = max(resposta, valor + solve(at + 1, novoHomens - quant)); } } return dp[at][homens] = resposta; } bool comp(int a, int b) { return c[a] > c[b]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> k; a.resize(n); b.resize(n); c.resize(n); for (int I = 0; I < n; I++) { cin >> a[I] >> b[I] >> c[I]; } g.resize(n); int x, y; vector<int> conexoes(n); for (int I = 0; I < n; I++) { conexoes[I] = I; } for (int I = 0; I < m; I++) { cin >> x >> y; x--; y--; conexoes[y] = max(conexoes[y], x); } for (int I = 0; I < n; I++) { g[conexoes[I]].push_back(c[I]); } for (int I = 0; I < n; I++) { sort(g[I].rbegin(), g[I].rend()); } memset(dp, -1, sizeof(dp)); int resposta = solve(0, k); if (resposta < 0) { cout << -1 << n ; } else { cout << resposta << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; map<long long int, long long int> mp; vector<long long int> v(n); vector<long long int> cSum(n, 0); for (long long int i = 0; i < n; i++) { cin >> v[i]; mp[v[i]]++; } cSum[0] = v[0]; for (long long int i = 1; i < n; i++) { cSum[i] = cSum[i - 1] + v[i]; } if (cSum[n - 1] % 2 != 0) { cout << NO ; } else { int flag2 = 0; set<long long int> st; for (long long int i = 0; i < n; i++) { mp[v[i]]--; long long int sum1 = cSum[i]; long long int sum2 = cSum[n - 1] - cSum[i]; long long int t = sum1 + sum2; long long int each = t / 2; if (each == sum1 && each == sum2) { flag2 = 1; break; } if (sum1 < sum2) { long long int diff = each - sum1; if (mp[diff] > 0) { flag2 = 1; break; } } if (sum1 > sum2) { long long int diff = each - sum2; if (st.find(diff) != st.end()) { flag2 = 1; break; } } st.insert(v[i]); } if (flag2 == 0) { cout << NO ; } else { cout << YES ; } } return 0; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
(* abc9_box, lib_whitebox *)
module adder_lut4(
output lut4_out,
(* abc9_carry *)
output cout,
input [0:3] in,
(* abc9_carry *)
input cin
);
parameter [0:15] LUT=0;
parameter IN2_IS_CIN = 0;
wire [0:3] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3]} : {in[0], in[1], in[2], in[3]};
// Output function
wire [0:7] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15]};
wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} :
{s1[1], s1[3], s1[5], s1[7]};
wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};
assign lut4_out = li[3] ? s3[0] : s3[1];
// Carry out function
assign cout = (s2[2]) ? cin : s2[3];
endmodule
(* abc9_lut=1, lib_whitebox *)
module frac_lut4(
input [0:3] in,
output [0:1] lut2_out,
output lut4_out
);
parameter [0:15] LUT = 0;
// Effective LUT input
wire [0:3] li = in;
// Output function
wire [0:7] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15]};
wire [0:3] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6]} :
{s1[1], s1[3], s1[5], s1[7]};
wire [0:1] s3 = li[2] ? {s2[0], s2[2]} : {s2[1], s2[3]};
assign lut2_out[0] = s2[2];
assign lut2_out[1] = s2[3];
assign lut4_out = li[3] ? s3[0] : s3[1];
endmodule
(* abc9_flop, lib_whitebox *)
module scff(
output reg Q,
input D,
input clk
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge clk)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge R)
if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module sh_dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffs(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge S)
if (!S)
Q <= 1'b1;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffn(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffnr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge R)
if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffns(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge S)
if (!S)
Q <= 1'b1;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffsr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge S or negedge R)
if (!S)
Q <= 1'b1;
else if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module dffnsr(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge S or negedge R)
if (!S)
Q <= 1'b1;
else if (!R)
Q <= 1'b0;
else
Q <= D;
endmodule
|
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