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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A31OI_BEHAVIORAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; const int nMax = 100007; int parent[nMax]; vector<int> g[nMax]; bool used[nMax]; void dfs(int root, int parent, int& cnt, int b, bool& bad) { if (root == b) { bad = true; } used[root] = true; ++cnt; for (int i = 0; i < g[root].size(); ++i) { int to = g[root][i]; if (used[to] == false && to != parent) dfs(to, root, cnt, b, bad); } } int main() { int n, pos; scanf( %d%d , &n, &pos); for (int i = 0; i < n; ++i) { int a; scanf( %d , &a); parent[i] = a - 1; if (a != 0) { g[i].push_back(a - 1); g[a - 1].push_back(i); } } --pos; int h = 1; int t = pos; while (parent[t] != -1) { ++h; t = parent[t]; } vector<int> c; for (int i = 0; i < n; ++i) { int cnt = 0; bool bad = false; if (used[i] == false) { dfs(i, -1, cnt, pos, bad); if (!bad) c.push_back(cnt); } } int to = (int)pow(2.0, (int)c.size()); set<int> s; set<int>::iterator it; for (int i = 1; i < to + 1; ++i) { int t = i, sum = 0; for (int j = 0; j < c.size(); ++j) { if (t & 1) sum += c[j]; t >>= 1; } s.insert(sum); } set<int> ans; ans.insert(h); for (it = s.begin(); it != s.end(); ++it) ans.insert(*it + h); for (it = ans.begin(); it != ans.end(); ++it) cout << *it << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long a = 1, b = 1; int n; cin >> n; for (int i = 1; i <= n; i++) { a = a * 27 % 1000000007; b = b * 7 % 1000000007; } cout << (a + 1000000007 - b) % 1000000007; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize ( O2,unroll-loops ) //#pragma GCC optimize( no-stack-protector,fast-math ) //#pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; typedef long long ll; typedef long double ld; typedef pair<int, int> pii; typedef pair<pii, int> piii; typedef pair<ll, ll> pll; #define debug(x) cerr<<#x<< = <<(x)<<endl; #define debugp(x) cerr<<#x<< = { <<(x.first)<< , <<(x.second)<< } <<endl; #define debug2(x, y) cerr<< { <<#x<< , <<#y<< } = { <<(x)<< , <<(y)<< } <<endl; #define debugv(v) {cerr<<#v<< : ;for (auto x:v) cerr<<x<< ;cerr<<endl;} #define all(x) x.begin(), x.end() #define pb push_back #define kill(x) return cout<<x<< n , 0; const int inf=1000000010; const ll INF=1000000000000001000LL; const int mod=1000000007; const int MAXN=200010, LOG=18, SGM=26; ll out, ans; int n, m, k, u, v, x, y, t, a, b; map<vector<int>, vector<string>> fuck; int TR[MAXN][SGM], ts; int par[LOG][MAXN]; int inc[MAXN], dest[MAXN]; vector<int> vec[MAXN]; string S[MAXN]; inline int Lcp(string &x, string &y){ int res=0; while (res<m && x[res]==y[res]) res++; return res; } int Count(vector<int> &vec, int l, int r){ // [l...r) return lower_bound(all(vec), r)-lower_bound(all(vec), l); } int GetPar(int v, int k){ for (int i=0; (1<<i)<=k; i++) if (k&(1<<i)) v=par[i][v]; return v; } ll Solve(){ if (m==1) return 1ll*n*(n-1)/2; sort(S, S+n); ll res=0;/* if (n<=2000){ for (int i=0; i<n; i++) for (int j=i+1; j<n; j++){ int l=Lcp(S[i], S[j]), r=m-1; if (l==m){ res++; continue ; } while (r && S[i][r]==S[j][r]) r--; int ok=1; while (l<r){ ok&=(S[i][l]<=S[i][l+1]); l++; } res+=ok; } return res; }*/ ts=0; memset(TR[0], 0, sizeof(TR[0])); vec[0].clear(); for (int i=0; i<n; i++){ vec[0].pb(i); int v=0; for (int j=m-1; ~j; j--){ int c=S[i][j]- a ; if (!TR[v][c]){ TR[v][c]=++ts; par[0][ts]=v; vec[ts].clear(); memset(TR[ts], 0, sizeof(TR[ts])); } v=TR[v][c]; vec[v].pb(i); } dest[i]=v; } for (int i=1; i<=ts; i++) sort(all(vec[i])); for (int j=1; j<LOG; ++j) for (int i=1; i<=ts; i++) par[j][i]=par[j-1][par[j-1][i]]; for (int i=0; i<n; i++){ inc[m-1]=m-1; for (int j=m-2; ~j; j--){ if (S[i][j]<=S[i][j+1]) inc[j]=inc[j+1]; else inc[j]=j; } int l=i+1; for (int lcp=m-1; ~lcp; lcp--){ int dwn=l-1, up=n; while (up-dwn>1){ int mid=(dwn+up)>>1; int tmp=Lcp(S[i], S[mid]); if (tmp<lcp) up=mid; else dwn=mid; } int r=up; if (l==r) continue ; // debug2(inc[lcp], GetPar(dest[i], inc[lcp])) res+=Count(vec[GetPar(dest[i], inc[lcp]+1)], l, r); // cerr<<S[i]<< <<lcp<< <<l<< <<r<< n ; // debug(res) // cerr<< n ; l=r; } } return res; } int main(){ ios_base::sync_with_stdio(false);cin.tie(0);cout.tie(0); //freopen( input.txt , r , stdin); //freopen( output.txt , w , stdout); cin>>n; for (int i=0; i<n; i++){ cin>>S[i]; vector<int> shit(26, 0); for (char ch:S[i]) shit[ch- a ]++; fuck[shit].pb(S[i]); } m=S[0].size(); out=1337ll*n*(n-1)/2; for (auto p:fuck){ n=0; for (string s:p.second) S[n++]=s; out-=1337ll*n*(n-1)/2; out+=2ll*n*(n-1)/2; ans+=Solve(); } debug(ans) cout<<out-ans<< n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int len = 3050; int d[len]; int ans(int n) { int sum = 0; while (true) { int i; if (!d[0]) break; for (i = 0; i < n;) { if (i == n - 1) { sum++; break; } if (i < n - 2 && d[i + 2]) i += 2; else if (i < n - 1 && d[i + 1]) i++; else return sum; } for (i = 0; i < n; i++) if (d[i] >= 1) d[i]--; } return sum; } int main() { int n; while (~scanf( %d , &n)) { for (int i = 0; i < n; i++) { scanf( %d , &d[i]); } printf( %d n , ans(n)); } return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
`ifdef VERILATOR
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
`else
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [60:0] p;
reg [60:0] a;
reg [20:0] b;
reg [60:0] shifted;
always @* begin
p = a[60:0] ** b[20:0];
shifted = 2 ** b[20:0];
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%0x %x %x\n", cyc, p, shifted);
`endif
// Constant versions
`checkh(61'h1 ** 21'h31, 61'h1);
`checkh(61'h2 ** 21'h10, 61'h10000);
`checkh(61'd10 ** 21'h3, 61'h3e8);
`checkh(61'h3 ** 21'h7, 61'h88b);
`ifndef VCS
`checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81);
`endif
if (cyc==1) begin
a <= 61'h0;
b <= 21'h0;
end
if (cyc==2) begin
a <= 61'h0;
b <= 21'h3;
end
if (cyc==3) begin
a <= 61'h1;
b <= 21'h31;
end
if (cyc==4) begin
a <= 61'h2;
b <= 21'h10;
end
if (cyc==5) begin
a <= 61'd10;
b <= 21'd3;
end
if (cyc==6) begin
a <= 61'd3;
b <= 21'd7;
end
if (cyc==7) begin
a <= 61'h7ab3811219;
b <= 21'ha6e30;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
case (cyc)
32'd00: ;
32'd01: ;
32'd02: ; // 0^x is indeterminate
32'd03: ; // 0^x is indeterminate
32'd04: `checkh(p, 61'h1);
32'd05: `checkh(p, 61'h10000);
32'd06: `checkh(p, 61'h3e8);
32'd07: `checkh(p, 61'h88b);
32'd08: `checkh(p, 61'h01ea58c703687e81);
32'd09: `checkh(p, 61'h01ea58c703687e81);
default: $stop;
endcase
case (cyc)
32'd00: ;
32'd01: ;
32'd02: `checkh(shifted, 61'h0000000000000001);
32'd03: `checkh(shifted, 61'h0000000000000008);
32'd04: `checkh(shifted, 61'h0002000000000000);
32'd05: `checkh(shifted, 61'h0000000000010000);
32'd06: `checkh(shifted, 61'h0000000000000008);
32'd07: `checkh(shifted, 61'h0000000000000080);
32'd08: `checkh(shifted, 61'h0000000000000000);
32'd09: `checkh(shifted, 61'h0000000000000000);
default: $stop;
endcase
end
endmodule
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module Computer_Datapath_FunctionUnit(
output reg [WORD_WIDTH-1:0] FU_out,
output [FLAG_WIDTH-1:0] FLAG_bus_out,
input [WORD_WIDTH-1:0] ADDR_bus_in, DATA_bus_in,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
parameter FS_WIDTH = 4;
parameter FLAG_WIDTH = 4;
wire [FS_WIDTH-1:0] FS = CNTRL_bus_in[9:6];
wire [WORD_WIDTH-2:0] V_temp = ADDR_bus_in[WORD_WIDTH-2:0]+DATA_bus_in[WORD_WIDTH-2:0];
wire V = V_temp[WORD_WIDTH-2:0];
wire N = FU_out[WORD_WIDTH-1];
wire Z = (!FU_out)?1'b1:1'b0;
reg C;
assign FLAG_bus_out = {V, C, N, Z};
always@(*) begin
case(FS)
4'b0000: {C, FU_out} = ADDR_bus_in; // Move A
4'b0001: {C, FU_out} = ADDR_bus_in+1; // Increment
4'b0010: {C, FU_out} = ADDR_bus_in+DATA_bus_in; // Add
4'b0011: {C, FU_out} = ADDR_bus_in+DATA_bus_in+1; //
4'b0100: {C, FU_out} = ADDR_bus_in+(~DATA_bus_in); //
4'b0101: {C, FU_out} = ADDR_bus_in+(~DATA_bus_in)+1; // Subtraction
4'b0110: {C, FU_out} = ADDR_bus_in-1; // Decrement
4'b0111: {C, FU_out} = ADDR_bus_in; // Move A
4'b1000: {C, FU_out} = ADDR_bus_in&DATA_bus_in; // Bitwize and
4'b1001: {C, FU_out} = ADDR_bus_in|DATA_bus_in; // Bitwize or
4'b1010: {C, FU_out} = ADDR_bus_in^DATA_bus_in; // Bitwize xor
4'b1011: {C, FU_out} = (~ADDR_bus_in); // Bitwize Invert
4'b1100: {C, FU_out} = DATA_bus_in; // Move B
4'b1101: {C, FU_out} = (DATA_bus_in>>1); // Shift Right B
4'b1110: {C, FU_out} = (DATA_bus_in<<1); // Shift Left B
4'b1111: {C, FU_out} = (~DATA_bus_in); // Ivert B
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-12; struct P { double x, y; P(double x = 0, double y = 0) : x(x), y(y){}; } a, b, c, o, p; P operator+(P a, P b) { return P(a.x + b.x, a.y + b.y); } P operator*(P a, double b) { return P(a.x * b, a.y * b); } inline double dis(P a, P b) { return sqrt(((a.x - b.x) * (a.x - b.x)) + ((a.y - b.y) * (a.y - b.y))); } inline void read(P &a) { scanf( %lf%lf , &a.x, &a.y); } double t1, t2, l, r, m, m1, m2, ab, bc, ac, ap; double Calc(double k) { p = b * (1 - k) + c * k; ap = dis(a, p); if (ap + bc * (1 + k) < t1 && ap + bc * (1 - k) < t2) return min(t1 - bc * (1 + k), t2 - bc * (1 - k)); double l = 0, r = 1; for (int i = 0; i < 100; ++i) { m = (l + r) * 0.5; o = a * (1 - m) + p * m; if (ap * m + dis(o, b) + bc < t1 && ap * m + dis(o, c) < t2) l = m; else r = m; } return (l + r) * 0.5 * ap; } int main() { scanf( %lf%lf , &t1, &t2); read(a); read(c); read(b); ab = dis(a, b); bc = dis(b, c); ac = dis(a, c); t1 += ab + bc + eps; t2 += ac + eps; if (ab + bc < t2) { printf( %.10lf n , min(t1, t2)); return 0; } l = 0, r = 1; for (int i = 0; i < 100; ++i) { m1 = (l + l + r) / 3; m2 = (l + r + r) / 3; if (Calc(m1) < Calc(m2)) l = m1; else r = m2; } printf( %.10lf n , Calc((l + r) * .5)); return 0; }
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#include <bits/stdc++.h> using namespace std; bool IsPrime(int x) { for (int i = 2; i * i <= x; i++) if (x % i == 0) return false; return true; } int modpow(int w, int p, int m) { if (p == 0) return 1; int x = modpow(w, p / 2, m); x = 1LL * x * x % m; if (p & 1) x = 1LL * x * w % m; return x; } int main() { int L, x, p; scanf( %d%d , &L, &x); p = L + 1; if ((x == 2) || !IsPrime(p)) { puts( -1 ); return 0; } if (L == 1) { printf( %d n , x - 1); return 0; } for (int b = x - 1; b > 1; b--) { if (modpow(b, L, p) != 1) continue; if (b % p == 0) continue; long long t = 0, r = 1, n = 0, x, d; while (1) { t = t + 1; x = r * b; d = x / p; r = x % p; n = n * b + d; if (r == 1) break; if (t > p / 2) { printf( %d n , b); return 0; } } if (t == L) { printf( %d n , b); return 0; } } puts( -1 ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1010; int N; pair<int, int> point[MAXN]; int cntx[MAXN], cnty[MAXN], cnt1, cnt2; map<int, vector<pair<int, int> > > samex, samey; int fa[MAXN]; int find(int x) { return (x == fa[x]) ? x : fa[x] = find(fa[x]); } void merge(int u, int v) { u = find(u); v = find(v); if (u != v) fa[u] = v; } bool check(long long dis) { for (int i = 1; i <= N; i++) fa[i] = i; for (int i = 1; i <= cnt1; i++) { for (int j = 1; j < samex[cntx[i]].size(); j++) { int id1 = samex[cntx[i]][j - 1].second; int id2 = samex[cntx[i]][j].second; if (point[id2].second - point[id1].second <= dis) merge(id1, id2); } } for (int i = 1; i <= cnt2; i++) { for (int j = 1; j < samey[cnty[i]].size(); j++) { int id1 = samey[cnty[i]][j - 1].second; int id2 = samey[cnty[i]][j].second; if (point[id2].first - point[id1].first <= dis) merge(id1, id2); } } int num = 0; for (int i = 1; i <= N; i++) num += (i == find(i)); if (num > 4) return false; if (num == 1) return true; if (num == 2) { for (int i = 1; i <= N; i++) { for (int j = i + 1; j <= N; j++) if (fa[i] != fa[j]) { if (point[i].first == point[j].first && abs(point[i].second - point[j].second) <= dis * 2) return true; if (point[i].second == point[j].second && abs(point[i].first - point[j].first) <= dis * 2) return true; if (abs(point[i].first - point[j].first) <= dis && abs(point[i].second - point[j].second) <= dis) return true; } } } else if (num == 3) { vector<pair<int, int> > seg; for (int i = 1; i <= cnt1; i++) { for (int j = 1; j < (int)samex[cntx[i]].size(); j++) { int id1 = samex[cntx[i]][j - 1].second; int id2 = samex[cntx[i]][j].second; if (fa[id1] != fa[id2]) { seg.push_back(make_pair(id1, id2)); } } } for (int i = 1; i <= cnt2; i++) { for (int j = 1; j < (int)samey[cnty[i]].size(); j++) { int id1 = samey[cnty[i]][j - 1].second; int id2 = samey[cnty[i]][j].second; if (fa[id1] != fa[id2]) { seg.push_back(make_pair(id1, id2)); } } } for (int i = 0; i < (int)seg.size(); i++) { int id1 = seg[i].first; int id2 = seg[i].second; for (int j = 1; j <= N; j++) if (fa[id1] != fa[j] && fa[id2] != fa[j]) { if (point[id1].first == point[id2].first) { if (min(point[id1].second, point[id2].second) >= point[j].second || max(point[id1].second, point[id2].second) <= point[j].second) continue; if (abs(point[j].first - point[id1].first) <= dis && abs(point[id1].second - point[j].second) <= dis && abs(point[id2].second - point[j].second) <= dis) return true; } else { if (min(point[id1].first, point[id2].first) >= point[j].first || max(point[id1].first, point[id2].first) <= point[j].first) continue; if (abs(point[j].first - point[id1].first) <= dis && abs(point[id1].second - point[j].second) <= dis && abs(point[j].first - point[id2].first) <= dis) return true; } } } } else { vector<pair<int, int> > segx, segy; for (int i = 1; i <= cnt1; i++) { for (int j = 1; j < (int)samex[cntx[i]].size(); j++) { int id1 = samex[cntx[i]][j - 1].second; int id2 = samex[cntx[i]][j].second; if (fa[id1] != fa[id2]) segx.push_back(make_pair(id1, id2)); } } for (int i = 1; i <= cnt2; i++) { for (int j = 1; j < (int)samey[cnty[i]].size(); j++) { int id1 = samey[cnty[i]][j - 1].second; int id2 = samey[cnty[i]][j].second; if (fa[id1] != fa[id2]) segy.push_back(make_pair(id1, id2)); } } for (int i = 0; i < (int)segx.size(); i++) { for (int j = 0; j < (int)segy.size(); j++) { int x1 = segx[i].first; int y1 = segx[i].second; int x2 = segy[j].first; int y2 = segy[j].second; if (fa[x1] == fa[x2] || fa[x1] == fa[y2] || fa[y1] == fa[x2] || fa[y1] == fa[y2]) continue; if (min(point[x2].first, point[y2].first) >= point[x1].first || max(point[x2].first, point[y2].first) <= point[x1].first) continue; if (min(point[x1].second, point[y1].second) >= point[x2].second || max(point[x1].second, point[y1].second) <= point[x2].second) continue; if (abs(point[x2].first - point[x1].first) <= dis && abs(point[y2].first - point[x1].first) <= dis && abs(point[x1].second - point[x2].second) <= dis && abs(point[y1].second - point[x2].second) <= dis) return true; } } } return false; } int main() { scanf( %d , &N); cnt1 = cnt2 = 0; for (int i = 1, x, y; i <= N; i++) { scanf( %d%d , &x, &y); point[i] = make_pair(x, y); cntx[++cnt1] = x; cnty[++cnt2] = y; samex[x].push_back(make_pair(y, i)); samey[y].push_back(make_pair(x, i)); } sort(cntx + 1, cntx + 1 + cnt1); sort(cnty + 1, cnty + 1 + cnt2); cnt1 = unique(cntx + 1, cntx + 1 + cnt1) - (cntx + 1); cnt2 = unique(cnty + 1, cnty + 1 + cnt2) - (cnty + 1); for (int i = 1; i <= cnt1; i++) sort(samex[cntx[i]].begin(), samex[cntx[i]].end()); for (int i = 1; i <= cnt2; i++) sort(samey[cnty[i]].begin(), samey[cnty[i]].end()); long long l = 0; long long r = 2e9; long long ans = -1; while (l <= r) { long long mid = (l + r) >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } printf( %lld , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 1000000404; const long long MOD = 1000000007ll; const long double PI = acos(-1.0); const long double EPS = 1e-9; template <typename t1, typename t2> inline void upmax(t1 &a, t2 b) { a = max(a, (t1)b); } template <typename t1, typename t2> inline void upmin(t1 &a, t2 b) { a = min(a, (t1)b); } template <typename T> inline T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T lcm(T a, T b) { return a * (b / gcd(a, b)); } template <typename T> inline T sqr(T a) { return a * a; } template <typename T> inline bool pal(T &x) { int n = (int((x.size()))); for (int i = 0; i < n / 2; i++) { if (x[i] != x[n - i - 1]) return 0; } return 1; } template <typename T> inline void rev(T &x) { int n = (int((x.size()))); for (int i = 0; i < n / 2; i++) swap(x[i], x[n - i - 1]); } int month[] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int dx[] = {1, 0, -1, 0, 1, 1, -1, -1}; int dy[] = {0, 1, 0, -1, 1, -1, 1, -1}; inline long long mp(long long a, long long b) { return (a << 31) + b; } class compare { public: bool operator()(const int a, const int b) const { return 1; } }; int SQ = 400; int l[211111]; int r[211111]; int m[211111]; int a[211111]; void solve() { int n; vector<int> st; cin >> n; for (int i = 1; i < n + 1; i++) { cin >> a[i]; } for (int i = 1; i < n + 1; i++) { while (!st.empty() && a[st.back()] >= a[i]) st.pop_back(); if (st.empty()) l[i] = 0; else l[i] = st.back(); st.push_back(i); } st.resize(0); for (int i = n + 1 - 1; i >= 1; i--) { while (!st.empty() && a[st.back()] >= a[i]) st.pop_back(); if (st.empty()) r[i] = n + 1; else r[i] = st.back(); st.push_back(i); } st.resize(0); for (int i = 1; i < n + 1; i++) upmax(m[r[i] - l[i] - 1], a[i]); for (int i = n + 1 - 1; i >= 1; i--) upmax(m[i], m[i + 1]); for (int i = 1; i < n + 1; i++) cout << m[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); }; getchar(); getchar(); return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 13464 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w3,
w48,
w51,
w1632,
w1683,
w13464;
assign w1 = i_data0;
assign w13464 = w1683 << 3;
assign w1632 = w51 << 5;
assign w1683 = w51 + w1632;
assign w3 = w4 - w1;
assign w4 = w1 << 2;
assign w48 = w3 << 4;
assign w51 = w3 + w48;
assign o_data0 = w13464;
//multiplier_block area estimate = 4330.97284268971;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; char s[105]; cin >> n; cin >> s; vector<int> v; v.clear(); int cnt = 0; for (int i = 0; i < n; i++) { if (s[i] == B ) { ++cnt; } else { if (cnt != 0) { v.push_back(cnt); cnt = 0; } } } if (cnt != 0) { v.push_back(cnt); cnt = 0; } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, u, r; vector<long long> k; vector<int> a, b, p, tmp; vector<vector<int> > v; vector<int> w; void read(); int main() { ios_base::sync_with_stdio(false); read(); v.push_back(a); w.push_back(1); long long s = 0; if (u & 1) s = -1e15; else { for (int i = 0; i < n; ++i) s += (a[i] * k[i]); } int uu = (u < 29 ? u : u - 2); for (int i = 0; i < uu; ++i) { int lim = v.size(); for (int j = 0; j < lim; ++j) { if (w[j]) { v.push_back(v[j]); w.push_back(0); for (int h = 0; h < n; ++h) v.back()[h] ^= b[h]; for (int h = 0; h < n; ++h) tmp[h] = v[j][p[h]] + r; swap(v[j], tmp); } else { w[j] = 1; for (int h = 0; h < n; ++h) tmp[h] = v[j][p[h]] + r; swap(v[j], tmp); } } if ((u - i) & 1) { for (int i = 0; i < v.size(); ++i) { long long ss = 0; for (int j = 0; j < n; ++j) ss += (v[i][j] * k[j]); s = max(s, ss); } } } if (uu < u) { for (int i = 0; i < v.size(); ++i) { long long ss = 0; for (int j = 0; j < n; ++j) tmp[j] = (v[i][p[j]] ^ b[p[j]]) + r; for (int j = 0; j < n; ++j) ss += (tmp[j] * k[j]); s = max(s, ss); ss = 0; for (int j = 0; j < n; ++j) tmp[j] = ((v[i][p[j]] + r) ^ b[j]); for (int j = 0; j < n; ++j) ss += (tmp[j] * k[j]); s = max(s, ss); ss = 0; for (int j = 0; j < n; ++j) tmp[j] = v[i][p[p[j]]] + r + r; for (int j = 0; j < n; ++j) ss += (tmp[j] * k[j]); s = max(s, ss); } } cout << s << endl; return 0; } void read() { cin >> n >> u >> r; a.resize(n); b.resize(n); k.resize(n); p.resize(n); tmp.resize(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; for (int i = 0; i < n; ++i) cin >> k[i]; for (int i = 0; i < n; ++i) cin >> p[i], --p[i]; }
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#include<bits/stdc++.h> #define ll long long int #define mk make_pair #define pb push_back #define INF (ll)1e18 #define pii pair<ll,ll> #define mod 1000000007 //998244353 #define f(i,a,b) for(ll i=a;i<b;i++) #define fb(i,a,b) for(ll i=a;i>b;i--) #define ff first #define ss second #define srt(v) if(!v.empty())sort(v.begin(),v.end()) #define rev(v) if(!v.empty())reverse(v.begin(),v.end()) #define PI 3.141592653589793238 #define pqr priority_queue<ll,vector<ll>,greater<ll>()> using namespace std; ll pow_mod(ll a,ll b) { ll res=1; while(b!=0) { if(b&1) { res=(res*a)%mod; } a=(a*a)%mod; b/=2; } return res; } ll calc(vector<ll> &a){ ll sz=a.size(); ll ans=0; for(ll i=1;i<sz;i++){ ll j=i; while(j<sz&&a[j]==a[i])++j; i=--j; ++ans; } return ans; } void solve() { ll n; cin>>n; ll a[n]; for(ll i=0;i<n;i++){ cin>>a[i]; } vector<ll>v1,v2; vector<ll>v[n+1]; for(ll i=1;i<=n;i++){ v[i].pb(INF); } for(ll i=n-1;i>=0;i--){ v[a[i]].pb(i); } v1.pb(-1); v2.pb(-1); for(ll i=0;i<n;i++){ v[a[i]].pop_back(); if(v1.back()==a[i]&&v2.back()==a[i]){ v1.pb(a[i]); } else if(v1.back()==a[i]){ v1.pb(a[i]); } else if(v2.back()==a[i]){ v2.pb(a[i]); } else if(v1.back()==-1) { v1.pb(a[i]); } else if(v2.back()==-1){ v2.pb(a[i]); } else { ll x=v[v1.back()].back(); ll y=v[v2.back()].back(); if(x<y){ v2.pb(a[i]); } else v1.pb(a[i]); } } ll ans=calc(v1)+calc(v2); cout<<ans<<endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); //Start from Here. ll t; t=1; // cin>>t; while(t--) solve(); //Good Bye! return 0; }
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#include <bits/stdc++.h> using namespace std; int n; string sherlock, moriarty; int algos(bool upper) { int res = 0; multiset<int> S; for (int i = 0; i < n; ++i) S.insert((int)moriarty[i]); for (int i = 0; i < n; ++i) { multiset<int>::iterator it; if (upper) it = S.upper_bound((int)sherlock[i]); else it = S.lower_bound((int)sherlock[i]); if (it == S.end()) continue; res++; S.erase(it); } return res; } int main() { cin >> n; cin >> sherlock >> moriarty; cout << n - algos(0) << endl << algos(1); }
|
// Implements I2C from the Zynq PS
module parallella_i2c
(/*AUTOARG*/
// Outputs
I2C_SDA_I, I2C_SCL_I,
// Inouts
I2C_SDA, I2C_SCL,
// Inputs
I2C_SDA_O, I2C_SDA_T, I2C_SCL_O, I2C_SCL_T
);
input I2C_SDA_O;
input I2C_SDA_T;
output I2C_SDA_I;
input I2C_SCL_O;
input I2C_SCL_T;
output I2C_SCL_I;
inout I2C_SDA;
inout I2C_SCL;
`ifdef PORTABLE
wire I2C_SDA = I2C_SDA_T ? 1'bZ : I2C_SDA_O;
wire I2C_SDA_I = I2C_SDA;
wire I2C_SCL = I2C_SCL_T ? 1'bZ : I2C_SCL_O;
wire I2C_SCL_I = I2C_SCL;
`else
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_sda (
.O(I2C_SDA_I), // Buffer output
.IO(I2C_SDA), // Buffer inout port (connect directly to top-level port)
.I(I2C_SDA_O), // Buffer input
.T(I2C_SDA_T) // 3-state enable input, high=input, low=output
);
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(I2C_SCL_I), // Buffer output
.IO(I2C_SCL), // Buffer inout port (connect directly to top-level port)
.I(I2C_SCL_O), // Buffer input
.T(I2C_SCL_T) // 3-state enable input, high=input, low=output
);
`endif
endmodule // parallella_i2c
/*
File: parallella_i2c
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2015 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/02/2013 10:51:56 PM
// Design Name:
// Module Name: tag_manager
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tag_manager # (
parameter TCQ = 1,
parameter RAM_ADDR_BITS = 5
)(
input clk,
input reset_n,
input tag_mang_write_en,
input [2:0] tag_mang_tc_wr, //[15:0]
input [2:0] tag_mang_attr_wr, //[15:0]
input [15:0] tag_mang_requester_id_wr, //[15:0]
input [6:0] tag_mang_lower_addr_wr, //[6:0]
input tag_mang_completer_func_wr, //[0:0]
input [7:0] tag_mang_tag_wr, //[7:0]
input [3:0] tag_mang_first_be_wr, //[2:0]
input tag_mang_read_en,
output [2:0] tag_mang_tc_rd, //[15:0]
output [2:0] tag_mang_attr_rd, //[15:0]
output [15:0] tag_mang_requester_id_rd, //[15:0]
output [6:0] tag_mang_lower_addr_rd, //[6:0]
output tag_mang_completer_func_rd, //[0:0]
output [7:0] tag_mang_tag_rd, //[7:0]
output [3:0] tag_mang_first_be_rd //[2:0]
);
reg [RAM_ADDR_BITS-1:0] tag_mang_write_id;
reg [RAM_ADDR_BITS-1:0] tag_mang_read_id;
always @( posedge clk )
if ( !reset_n )
tag_mang_write_id <= #TCQ 1;
else if ( tag_mang_write_en )
tag_mang_write_id <= #TCQ tag_mang_write_id + 1;
always @( posedge clk )
if ( !reset_n )
tag_mang_read_id <= #TCQ 0;
else if ( tag_mang_read_en )
tag_mang_read_id <= #TCQ tag_mang_read_id + 1;
localparam RAM_WIDTH = 42;
(* RAM_STYLE="distributed" *)
reg [RAM_WIDTH-1:0] tag_storage [(2**RAM_ADDR_BITS)-1:0];
wire [RAM_WIDTH-1:0] completion_data;
always @(posedge clk)
if (tag_mang_write_en)
tag_storage[tag_mang_write_id] <= #TCQ { tag_mang_attr_wr, tag_mang_tc_wr, tag_mang_requester_id_wr, tag_mang_lower_addr_wr, tag_mang_completer_func_wr, tag_mang_tag_wr, tag_mang_first_be_wr};
assign completion_data = tag_storage[tag_mang_read_id];
assign tag_mang_attr_rd = completion_data[41:39];
assign tag_mang_tc_rd = completion_data[38:36];
assign tag_mang_requester_id_rd = completion_data[35:20]; //[15:0]
assign tag_mang_lower_addr_rd = completion_data[19:13]; //[6:0]
assign tag_mang_completer_func_rd = completion_data[12]; //[0:0]
assign tag_mang_tag_rd = completion_data[11:4]; //[7:0]
assign tag_mang_first_be_rd = completion_data[3:0]; //[2:0]
endmodule
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 97 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
/* PE: processing element */
module PE(clk, reset, ctrl, d0, d1, d2, out);
input clk;
input reset;
input [10:0] ctrl;
input [197:0] d0;
input [`WIDTH:0] d1, d2;
output [`WIDTH:0] out;
reg [197:0] R0;
reg [`WIDTH:0] R1, R2, R3;
wire [1:0] e0, e1, e2; /* part of R0 */
wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
mx0, mx1, mx2, mx3, mx4, mx5, mx6, /* output of MUX */
ad0, ad1, ad2, /* output of GF(3^m) adder */
cu0, cu1, cu2, /* output of cubic */
mo0, mo1, mo2, /* output of mod_p */
t0, t1, t2;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
assign mx0 = c0 ? d1 : ad2;
assign mx1 = c2 ? d2 : ad2;
always @ (posedge clk)
if(reset) R1 <= 0;
else if (c1) R1 <= mx0;
always @ (posedge clk)
if(reset) R2 <= 0;
else if (c3) R2 <= mx1;
always @ (posedge clk)
if(reset) R0 <= 0;
else if (c4) R0 <= d0;
else if (c5) R0 <= R0 << 6;
assign {e2,e1,e0} = R0[197:192];
PPG
ppg_0 (e0, R1, ppg0),
ppg_1 (e1, R2, ppg1),
ppg_2 (e2, R1, ppg2);
v0 v0_ (ppg0, cu0);
v1 v1_ (ppg1, cu1);
v2 v2_ (ppg2, cu2);
assign mx2 = c6 ? ppg0 : cu0;
assign mx3 = c6 ? ppg1 : cu1;
assign mx4 = c6 ? mo1 : cu2;
assign mx5 = c7 ? mo2 : R3;
mod_p
mod_p_0 (mx3, mo0),
mod_p_1 (ppg2, t0),
mod_p_2 (t0, mo1),
mod_p_3 (R3, t1),
mod_p_4 (t1, t2),
mod_p_5 (t2, mo2);
assign mx6 = c9 ? mo0 : mx3;
f3m_add
f3m_add_0 (mx2, mx6, ad0),
f3m_add_1 (mx4, c8 ? mx5 : 0, ad1),
f3m_add_2 (ad0, ad1, ad2);
always @ (posedge clk)
if (reset) R3 <= 0;
else if (c10) R3 <= ad2;
else R3 <= 0; /* change */
assign out = R3;
endmodule
// C = (x*B mod p(x))
module mod_p(B, C);
input [`WIDTH:0] B;
output [`WIDTH:0] C;
wire [`WIDTH+2:0] A;
assign A = {B[`WIDTH:0], 2'd0}; // A == B*x
wire [1:0] w0;
f3_mult m0 (A[195:194], 2'd2, w0);
f3_add s0 (A[1:0], {w0[0], w0[1]}, C[1:0]); //f3_sub s0 (A[1:0], w0, C[1:0]);
assign C[23:2] = A[23:2];
wire [1:0] w12;
f3_mult m12 (A[195:194], 2'd1, w12);
f3_add s12 (A[25:24], {w12[0], w12[1]}, C[25:24]); // f3_sub s12 (A[25:24], w12, C[25:24]);
assign C[193:26] = A[193:26];
endmodule
// PPG: partial product generator, C == A*d in GF(3^m)
module PPG(d, A, C);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i=0; i < `M; i=i+1)
begin: ppg0
f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
end
endgenerate
endmodule
// f3m_add: C = A + B, in field F_{3^M}
module f3m_add(A, B, C);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for(i=0; i<`M; i=i+1) begin: aa
f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
end
endgenerate
endmodule
// f3_add: C == A+B (mod 3)
module f3_add(A, B, C);
input [1:0] A, B;
output [1:0] C;
wire a0, a1, b0, b1, c0, c1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C = {c1, c0};
assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
(~a0 & ~a1 & b0 & ~b1) |
(~a0 & a1 & ~b0 & b1) ;
assign c1 = (~a0 & a1 & ~b0 & ~b1) |
( a0 & ~a1 & b0 & ~b1) |
(~a0 & ~a1 & ~b0 & b1) ;
endmodule
// f3_mult: C = A*B (mod 3)
module f3_mult(A, B, C);
input [1:0] A;
input [1:0] B;
output [1:0] C;
wire a0, a1, b0, b1;
assign {a1, a0} = A;
assign {b1, b0} = B;
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_BLACKBOX_V
`define SKY130_FD_SC_LS__O21A_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21a (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long int n; int main() { cin >> n; long long int summ = n + (n - 1); long long int wei = 0; while (summ != 0) { summ /= 10; wei++; } long long int stdl = 9; for (int i = 1; i < wei; i++) { stdl = stdl * 10 + 9; } summ = n + (n - 1); if (summ < stdl) wei--, stdl /= 10; long long int ans, p = stdl / 2; ans = min(p, n - p); long long int qian = 1; for (int i = 1; i <= wei; i++) qian *= 10; while (stdl + qian <= summ) { stdl += qian; p = stdl / 2; ans += min(p, n - p); } if (n < 5) { if (n == 2) ans = 1; if (n == 3) ans = 3; if (n == 4) ans = 6; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int sum = 0; for (int i = 0; i < n; ++i) { int l, r; cin >> l >> r; sum += r - l + 1; } int ct = 0; while (sum % k != 0) { ct++; sum++; } cout << ct << endl; }
|
// $Id: c_reverse.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for reversing a set of bits
//==============================================================================
module c_reverse
(data_in, data_out);
// width of input word
parameter width = 32;
// input word
input [0:width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:connect
// reverse inputs data
assign data_out[i] = data_in[(width-1)-i];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool chmax(T &a, const T &b) { return b > a ? a = b, true : false; } template <class T> inline bool chmin(T &a, const T &b) { return b < a ? a = b, true : false; } template <class T> using MaxHeap = priority_queue<T>; template <class T> using MinHeap = priority_queue<T, vector<T>, greater<T>>; template <class T, class F = less<T>> void sort_uniq(vector<T> &v, F f = F()) { sort(begin(v), end(v), f); v.resize(unique(begin(v), end(v)) - begin(v)); } int main() { ios::sync_with_stdio(0); cin.tie(0); int tt; cin >> tt; while (tt--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < (int)(n); i++) cin >> a[i]; int last = a[0], alice = a[0], bob = 0; int i = 1, j = n - 1, turn = 1, moves = 1; while (i <= j) { int cnt = 0; if (turn) { while (i <= j && cnt <= last) { cnt += a[j--]; } bob += cnt; } else { while (i <= j && cnt <= last) { cnt += a[i++]; } alice += cnt; } last = cnt; moves++; turn ^= 1; } cout << moves << << alice << << bob << n ; } return 0; }
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
// CLK_OUT3___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`default_nettype wire
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
// Status and control signals
.locked(locked)
);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ADC_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ADC_ROM (
address,
clock,
q);
input [10:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "ADC.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ADC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ADC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int Distance(int x1, int y1, int x2, int y2) { return (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); } int main() { int n, m, x1, y1, x2, y2, x3, y3, x4, y4, flag, dis1, dis2; while (~scanf( %d%d , &n, &m)) { flag = 0; if (m > n) { swap(n, m), flag = 1; } if (m == 0) { x1 = 1, x2 = n; x3 = 0; x4 = n - 1; y1 = y2 = y3 = y4 = 0; } else { dis1 = Distance(0, 0, n, m) * 2 + Distance(0, 0, n, 0); dis2 = Distance(0, 0, n, m - 1) * 2 + Distance(0, 0, n, m); if (dis1 > dis2) { x1 = n; y1 = m; x2 = 0; y2 = 0; x3 = n; y3 = 0; x4 = 0; y4 = m; } else { x1 = 0; y1 = 1; x2 = n; y2 = m; x3 = 0; y3 = 0; x4 = n; y4 = m - 1; } } if (flag) { swap(x1, y1); swap(x2, y2); swap(x3, y3); swap(x4, y4); } printf( %d %d n%d %d n%d %d n%d %d n , x1, y1, x2, y2, x3, y3, x4, y4); } return 0; }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; int main() { cin >> N; cout << N / 2 << n ; for (int i = 0; i < N / 2 - 1; i++) { cout << 2 ; } if (N % 2 == 0) cout << 2 n ; else cout << 3 n ; return 0; }
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: gsu_umult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_umult (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`include "gcd2.generated.vh"
`default_nettype none
module Gcd2 (input wire CLK, input wire nRST,
input wire request$say__ENA,
input wire [31:0]request$say$va,
input wire [31:0]request$say$vb,
output wire request$say__RDY,
output wire indication$gcd__ENA,
output wire [31:0]indication$gcd$v,
input wire indication$gcd__RDY);
reg [31:0]a;
reg [31:0]b;
reg running;
wire RULE$respond_rule__ENA;
wire RULE$respond_rule__RDY;
assign indication$gcd$v = a;
assign indication$gcd__ENA = running & ( b == 32'd0 );
assign request$say__RDY = !running;
// Extra assigments, not to output wires
assign RULE$respond_rule__ENA = ( b != 32'd0 ) | indication$gcd__RDY | ( !running );
assign RULE$respond_rule__RDY = ( b != 32'd0 ) | indication$gcd__RDY | ( !running );
always @( posedge CLK) begin
if (!nRST) begin
a <= 0;
b <= 0;
running <= 0;
end // nRST
else begin
// RULE$flip_rule__ENA
if (( a < b ) & ( running != 0 )) begin
b <= a;
a <= b;
end;
// End of RULE$flip_rule__ENA
// RULE$mod_rule__ENA
if (( b != 0 ) & ( a >= b ) & ( running != 0 ))
a <= a - b;
// End of RULE$mod_rule__ENA
if (RULE$respond_rule__ENA & RULE$respond_rule__RDY) begin // RULE$respond_rule__ENA
if (( b == 0 ) & ( running != 0 ))
running <= 0;
end; // End of RULE$respond_rule__ENA
if (!( running | ( !request$say__ENA ) )) begin // request$say__ENA
a <= request$say$va;
b <= request$say$vb;
running <= 1;
end; // End of request$say__ENA
end
end // always @ (posedge CLK)
endmodule
`default_nettype wire // set back to default value
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
//
// This implements a 4096:1 mux via two stages of 64:1 muxing.
// change these two parameters to see the speed differences
//`define DATA_WIDTH 12
//`define MUX2_SIZE 32
`define DATA_WIDTH 2
`define MUX2_SIZE 8
// if you change these, then the testbench will break
`define ADDR_WIDTH 12
`define MUX1_SIZE 64
// Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v
// End of automatics
reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
reg [`ADDR_WIDTH-1:0] addr;
// Mux: takes in addr and datai and outputs datao
mux4096 mux4096 (/*AUTOINST*/
// Outputs
.datao (datao[`DATA_WIDTH-1:0]),
// Inputs
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
.addr (addr[`ADDR_WIDTH-1:0]));
// calculate what the answer should be from datai. This is bit
// tricky given the way datai gets sliced. datai is in bit
// planes where all the LSBs are contiguous and then the next bit.
reg [`DATA_WIDTH-1:0] datao_check;
integer j;
always @(datai or addr) begin
for(j=0;j<`DATA_WIDTH;j=j+1) begin
/* verilator lint_off WIDTH */
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr);
/* verilator lint_on WIDTH */
end
end
// Run the test loop. This just increments the address
integer i, result;
always @ (posedge clk) begin
// initial the input data with random values
if (addr == 0) begin
result = 1;
datai = 0;
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin
/* verilator lint_off WIDTH */
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
/* verilator lint_on WIDTH */
end
end
addr <= addr + 1;
if (datao_check != datao) begin
result = 0;
$stop;
end
`ifdef TEST_VERBOSE
$write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao);
`endif
// only run the first 10 addresses for now
if (addr > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module mux4096
(input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output [`DATA_WIDTH-1:0] datao
);
// DATA_WIDTH instantiations of mux4096_1bit
mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0]
(.addr(addr),
.datai(datai),
.datao(datao)
);
endmodule
module mux4096_1bit
(input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output datao
);
// address decoding
wire [3:0] A = (4'b1) << addr[1:0];
wire [3:0] B = (4'b1) << addr[3:2];
wire [3:0] C = (4'b1) << addr[5:4];
wire [3:0] D = (4'b1) << addr[7:6];
wire [3:0] E = (4'b1) << addr[9:8];
wire [3:0] F = (4'b1) << addr[11:10];
wire [`MUX2_SIZE-1:0] data0;
// DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64
// first stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0]
(.A(A),
.B(B),
.C(C),
.datai(datai),
.datao(data0));
// DATA_WIDTH*MUX2_SIZE instantiations of mux64
// second stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2
(.A(D),
.B(E),
.C(F),
.datai(data0),
.datao(datao));
endmodule
module mux64
#(parameter MUX_SIZE=64)
(input [3:0] A,
input [3:0] B,
input [3:0] C,
input [MUX_SIZE-1:0] datai,
output datao
);
wire [63:0] colSelA = { 16{ A[3:0] }};
wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}};
wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}};
wire [MUX_SIZE-1:0] data_bus;
// Note each of these becomes a separate wire.
//.colSelA(colSelA[MUX_SIZE-1:0]),
//.colSelB(colSelB[MUX_SIZE-1:0]),
//.colSelC(colSelC[MUX_SIZE-1:0]),
drv drv[MUX_SIZE-1:0]
(.colSelA(colSelA[MUX_SIZE-1:0]),
.colSelB(colSelB[MUX_SIZE-1:0]),
.colSelC(colSelC[MUX_SIZE-1:0]),
.datai(datai),
.datao(data_bus)
);
assign datao = |data_bus;
endmodule
module drv
(input colSelA,
input colSelB,
input colSelC,
input datai,
output datao
);
assign datao = colSelC & colSelB & colSelA & datai;
endmodule
|
module ARMAria
#(
parameter WORD_SIZE = 32,
parameter INSTRUCTION_WIDTH = 16,
parameter FLAG_COUNT = 5,
parameter IO_WIDTH = 16,
parameter SEGMENTS_COUNT = 7*8,
parameter OFFSET_WIDTH = 12
)(
input fast_clock, confirmation_button, reset_button,
input continue_button, request_os_button,
input [(IO_WIDTH - 1) : 0] sw,
output [(IO_WIDTH - 1) : 0] rled,
output [(FLAG_COUNT - 1) : 0] gled,
output [(SEGMENTS_COUNT - 1) : 0] sseg,
output slow_clock, reset,
output is_input, is_output, enable
);
/* Wire Declaration Section*/
wire alu_negative, alu_zero, alu_carry, alu_overflow;
wire bs_negative, bs_zero, bs_carry, confirmation;
wire continue_debounced, n_flag, z_flag, should_branch;
wire c_flag, v_flag, is_os, is_memory_write;
wire should_fill_b_offset, is_bios, user_request;
wire [1 : 0] interruption;
wire [2 : 0] controlMAH, b_sign_extend;
wire [2 : 0] load_sign_extend, controlRB;
wire [3 : 0] RegD, RegA, RegB, controlALU, controlBS;
wire [(OFFSET_WIDTH - 1) : 0] OffImmed;
wire [(INSTRUCTION_WIDTH -1) : 0] Instruction;
wire [(WORD_SIZE - 1) : 0] instruction_address, next_PC;
wire [(WORD_SIZE - 1) : 0] data_address, ALU_result, final_result;
wire [(WORD_SIZE - 1) : 0] PC, SP, memory_read_data, Bse;
wire [(WORD_SIZE - 1) : 0] PreMemIn, MemIn, Bbus, IData, PreB;
wire [(WORD_SIZE - 1) : 0] next_SP, Abus, MemOut, Bsh;
/* Buttons startup */
DeBounce dbc(fast_clock, confirmation_button, confirmation);
DeBounce dbr(fast_clock, reset_button, reset);
DeBounce dbco(fast_clock, continue_button, continue_debounced);
DeBounce dbur(fast_clock, request_os_button, user_request);
/*Drive slow clock */
FrequencyDivider fd(fast_clock, slow_clock);
/* Module interconnection*/
Control control_unit(
Instruction,
alu_negative, alu_carry, alu_overflow,
alu_zero, continue_debounced, bs_negative,
bs_zero, bs_carry, reset, slow_clock,
confirmation,
interruption,
OffImmed,
RegD, RegA, RegB,
controlBS, controlALU,
controlRB, controlMAH,
b_sign_extend, load_sign_extend,
is_memory_write, should_fill_b_offset,
n_flag, z_flag, c_flag, v_flag, is_os, enable,
should_branch, is_input, is_output, is_bios
);
MemoryUnit mu(
is_memory_write, slow_clock, fast_clock,
data_address, instruction_address, MemOut,
is_bios,
Instruction,
memory_read_data
);
IOmodule enterescape(
slow_clock, fast_clock,
is_output & (~is_input),
reset, enable,
MemOut, IData, sw,
n_flag, z_flag, c_flag, v_flag, is_os,
rled, gled, sseg, instruction_address
);
MemoryAddressHandler mah(
is_os, should_branch, reset,
controlMAH,
ALU_result, PC, SP,
next_SP, data_address,
final_result, next_PC,
instruction_address
);
MemoryDataHandler mdh(
(is_input && !is_output),
IData, memory_read_data,
PreMemIn
);
SignExtend load_sign_extend_unit(
PreMemIn,
load_sign_extend,
MemIn
);
RegBank ARMARIAbank(
enable, reset, slow_clock, fast_clock,
controlRB,
RegA, RegB, RegD,
final_result, MemIn,
next_SP, next_PC,
Abus, Bbus,
PC, SP, MemOut,
{n_flag, z_flag, c_flag, v_flag}
);
MUXBS muxbusb(
should_fill_b_offset,
Bbus, OffImmed,
PreB
);
SignExtend channel_B_sign_extend_unit(
PreB,
b_sign_extend,
Bse
);
BarrelShifter NiagaraFalls(
Abus, Bse,
controlBS,
Bsh,
bs_negative, bs_zero, bs_carry
);
ALU arithmeticlogicunit(
Abus, Bsh,
ALU_result,
controlALU,
c_flag,
alu_negative, alu_zero, alu_carry, alu_overflow
);
Watchdog pitbull(
slow_clock, fast_clock,
user_request,
interruption
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: shiftreg.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple, single clock, simple dual port (SCSDP) ram
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
`include "functions.vh"
module scsdpram
#(
parameter C_WIDTH = 32,
parameter C_DEPTH = 1024
)
(
input CLK,
input RD1_EN,
input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
output [C_WIDTH-1:0] RD1_DATA,
input WR1_EN,
input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
input [C_WIDTH-1:0] WR1_DATA
);
reg [C_WIDTH-1:0] rMemory [C_DEPTH-1:0];
reg [C_WIDTH-1:0] rDataOut;
assign RD1_DATA = rDataOut;
always @(posedge CLK) begin
if (WR1_EN) begin
rMemory[WR1_ADDR] <= #1 WR1_DATA;
end
if(RD1_EN) begin
rDataOut <= #1 rMemory[RD1_ADDR];
end
end
endmodule
|
//---------------------------------------------------------------------------------------
// baud rate generator for uart
//
// this module has been changed to receive the baud rate dividing counter from registers.
// the two registers should be calculated as follows:
// first register:
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
// second register:
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
//
//---------------------------------------------------------------------------------------
module baud_gen
(
clock, reset,
ce_16, baud_freq, baud_limit
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
input clock; // global clock input
input reset; // global reset input
output ce_16; // baud rate multiplyed by 16
input [11:0] baud_freq; // baud rate setting registers - see header description
input [15:0] baud_limit;
// internal registers
reg ce_16;
reg [15:0] counter;
//---------------------------------------------------------------------------------------
// module implementation
// baud divider counter
always @ (posedge clock or posedge reset)
begin
if (reset)
counter <= 16'b0;
else if (counter >= baud_limit)
counter <= counter - baud_limit;
else
counter <= counter + baud_freq;
end
// clock divider output
always @ (posedge clock or posedge reset)
begin
if (reset)
ce_16 <= 1'b0;
else if (counter >= baud_limit)
ce_16 <= 1'b1;
else
ce_16 <= 1'b0;
end
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int maxN = 100000; int main() { cin.tie(0); ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; int ok = 1; for (int i = 0; i < n; i++) { for (int k = 0; k < m; k++) { char c; cin >> c; if (c != B && c != W && c != G ) ok = 0; } } cout << (ok ? #Black&White : #Color ) << endl; return 0; }
|
`timescale 1ns/1ps
`default_nettype none
module button_debounce
#(
parameter CLK_FREQ = 10_000_000,
parameter DEBOUNCE_HZ = 2
) (
input wire clk,
input wire rst_n,
input wire btn_in,
output reg btn_out
);
localparam COUNT_MAX = CLK_FREQ / DEBOUNCE_HZ;
localparam S_WAIT = 0;
localparam S_FIRE = 1;
localparam S_COUNT = 2;
reg [$clog2(COUNT_MAX):0] count;
reg [1:0] state, next_state;
always @(posedge clk or negedge rst_n)
state <= (~rst_n) ? S_WAIT : next_state;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
btn_out <= 0;
count <= 0;
end
else begin
btn_out <= 0;
count <= 0;
case(state)
S_WAIT : begin
end
S_FIRE : begin
btn_out <= 1;
end
S_COUNT : begin
count <= count + 1;
end
endcase
end
end
always @(*) begin
case(state)
S_WAIT : next_state <= (btn_in) ? S_FIRE : state;
S_FIRE : next_state <= S_COUNT;
S_COUNT : next_state <= (count > COUNT_MAX - 1) ? S_WAIT : state;
default : next_state <= S_WAIT;
endcase
end
endmodule
`default_nettype wire
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes video input streams on the DE boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_decoder_0 (
// Inputs
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
clk27_reset,
stream_out_ready,
// Bidirectional
// Outputs
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input clk27_reset;
input stream_out_ready;
// Bidirectional
// Outputs
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire video_clk;
wire video_clk_reset;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
// Internal Registers
reg reached_start_of_frame;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
// Internal Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
// Internal Assignments
assign video_clk = TD_CLK27;
assign video_clk_reset = clk27_reset;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// NTSC Video In Decoding
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
// Inputs
.clk (video_clk),
.reset (video_clk_reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
// Bidirectionals
// Outputs
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
// Inputs
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
// .data ({1'b0, decoded_startofpacket, decoded_pixel}),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
// Bidirectionals
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_S_BLACKBOX_V
/**
* udp_dlatch$P_pp$PKG$s: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$s (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; pair<int, int> p[100005], ans[100005]; int tot, start[100005], remain, now; int f[100005]; priority_queue<pair<int, int> > Q; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { scanf( %d%d , &p[i].first, &p[i].second); if (p[i].second == 0) p[i].second = -1; p[i].second = -p[i].second; p[i].second *= i; } sort(p + 1, p + m + 1); for (int i = 1; i <= n; i++) f[i] = i, start[i] = i + 1; remain = 1; now = 1; for (int i = 1; i <= m; i++) { if (p[i].second > 0) { if (Q.empty()) { return puts( -1 ), 0; } else { int x = Q.top().first, y = Q.top().second; Q.pop(); if (-x <= remain) { ans[p[i].second] = make_pair(-x, y); if (-x != n) Q.push(make_pair(x - 1, y)); } else { return puts( -1 ); } } } else { remain++; if (remain <= n) { Q.push(make_pair(-remain - 1, remain)); ans[-p[i].second] = make_pair(1, remain); } else { return puts( -1 ), 0; } } } for (int i = 1; i <= m; i++) printf( %d %d n , ans[i].first, ans[i].second); }
|
`timescale 1ns / 1ps
module word(
output word,
input [3:0] row, col,
input [1:0] select
);
reg [15:0] line[15:0];
integer i;
always @(*)
begin
if (select == 1) begin
line[0] = 16'b0000000000000000;
line[1] = 16'b0000000000000000;
line[2] = 16'b0000111111110000;
line[3] = 16'b0001111111111000;
line[4] = 16'b0011100000011100;
line[5] = 16'b0111000000001110;
line[6] = 16'b0111000000001110;
line[7] = 16'b0111000000001110;
line[8] = 16'b0111000000001110;
line[9] = 16'b0111000000001110;
line[10] =16'b0111000000001110;
line[11] =16'b0111000000001110;
line[12] =16'b0111000000001110;
line[13] =16'b0011111111111100;
line[14] =16'b0001111111111000;
line[15] =16'b0000000000000000;
end else if (select == 2) begin
line[0] = 16'b0000000000000000;
line[1] = 16'b1110000000000111;
line[2] = 16'b0111000000001110;
line[3] = 16'b0011100000011100;
line[4] = 16'b0001110000111000;
line[5] = 16'b0000111001110000;
line[6] = 16'b0000011111100000;
line[7] = 16'b0000001111000000;
line[8] = 16'b0000001111000000;
line[9] = 16'b0000011111100000;
line[10] =16'b0000111001110000;
line[11] =16'b0001110000111000;
line[12] =16'b0011100000011100;
line[13] =16'b0111000000001110;
line[14] =16'b1110000000000111;
line[15] =16'b0000000000000000;
end else for (i=0; i<16; i=i+1)
line[i] = 16'b0;
end
assign word = (select == 0) ? 1'b0 : (line[row] >> (~col)) % 2;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct __s { __s() { if (1) { ios_base::Init i; cin.sync_with_stdio(0); cin.tie(0); } } ~__s() { if (!1) fprintf(stderr, Execution time: %.3lf s. n , (double)clock() / CLOCKS_PER_SEC); long long n; cin >> n; } } __S; long long a[1111111]; long long ai[1111111]; int main(void) { long long n; cin >> n; for (long long i = 0; i < (long long)(n); i++) { cin >> a[i]; a[i]--; ai[a[i]] = i; } long long cnt = 0; for (long long i = 0; i < (long long)(n); i++) { if (i == a[i]) continue; long long j = ai[i]; swap(a[i], a[j]); swap(ai[a[i]], ai[a[j]]); cnt++; } long long m1 = 3 * n - cnt; long long m2 = 7 * n + 1 - cnt; if (m1 % 2 == 0) cout << Petr << n ; else cout << Um_nik << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, k, j, c; while (scanf( %d%d , &n, &m) != EOF) { c = 0; char a[990][101], x; for (i = 0; i < n; i++) scanf( %s , a[i]); for (i = 0; i < n; i++) { for (k = 0; k < m; k++) { x = a[i][k]; for (j = 0; j < n; j++) { if (x >= a[j][k]) continue; else break; } if (j == n) { c = c + 1; break; } } } printf( %d n , c); } return 0; }
|
`timescale 1ns / 1ps
module jt12_test;
reg [9:0] phase;
reg rst,clk;
reg [2:0] alg;
`include "../common/dump.vh"
initial begin
clk = 0;
forever #10 clk=~clk;
end
wire signed [13:0] left, right;
wire signed [8:0] op_result;
wire clk6;
wire [9:0] eg_atten;
reg [2:0] ch;
reg [2:0] voice_fb;
always @(posedge clk)
if( rst || clk6 || ch==3'd5 ) ch <= 3'd0;
else ch <= ch + 1'b1;
always @(posedge clk)
if( rst ) phase <= 10'h3ff;
else if(clk6) phase <= phase + 1'd1;
wire s1_enters, s2_enters, s3_enters, s4_enters;
// Ch 0 attenuation gets evaluated
// on register cycle 3, which is ch 2 at the input
wire eg_ch0 = ch==3'd2;
wire eg_ch1 = ch==3'd3;
wire eg_ch2 = ch==3'd4;
wire eg_ch3 = ch==3'd5;
wire eg_ch4 = ch==3'd0;
wire eg_ch5 = ch==3'd1;
wire eg_s1 = s3_enters;
wire eg_s3 = s2_enters;
wire eg_s2 = s4_enters;
wire eg_s4 = s1_enters;
reg [7:0] eg_max;
//assign eg_atten = eg_ch0 && (eg_s3||eg_s4) ? { 2'b0, eg_max } : 10'h3ff;
//assign eg_atten = eg_ch0 && (~eg_s4) ? { 2'b0, eg_max } : 10'h3ff;
//assign eg_atten = eg_ch0 && (eg_s1||eg_s2||eg_s4) ? { 2'b0, eg_max } : 10'h3ff;
assign eg_atten = eg_ch0 ? { 2'b0, eg_max } : 10'h3ff;
initial begin
rst = 0;
alg = 3'd0;
#5 rst = 1;
#20 rst = 0;
# $finish;
end
integer clk_count;
always @(posedge clk)
if( rst ) begin
clk_count <= 0;
voice_fb <= 3'd0;
eg_max <= 8'd0;
end else begin
if( !clk_count[6:0] ) eg_max <= eg_max + 1'b1;
if( clk_count == 30000 ) begin
voice_fb <= voice_fb + 3'd1;
clk_count <= 0;
end
else clk_count <= clk_count+1;
end
jt12_opsync u_opsync(
.rst ( rst ),
.clk ( clk ),
.clk6 ( clk6 ),
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters )
);
jt12_fm u_fm(
.alg_st1 ( alg ),
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters ),
.use_prevprev1 ( use_prevprev1 ),
.use_internal_x( use_internal_x ),
.use_internal_y( use_internal_y ),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 )
);
reg s1_delayed;
always @(posedge clk)
s1_delayed <= s1_enters;
jt12_op u_op(
.rst ( rst ),
.clk ( clk ),
.pg_phase ( phase ),
.eg_atten ( eg_atten ),
.voice_fb ( voice_fb ),
.op_fb_enable ( s1_delayed ),
.test_214 ( 1'b0 ),
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters ),
.use_prevprev1 ( use_prevprev1 ),
.use_internal_x ( use_internal_x),
.use_internal_y ( use_internal_y),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 ),
.op_result ( op_result )
);
jt12_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.op_result ( op_result ),
.rl ( 2'b11 ),
// note that the order changes to deal
// with the operator pipeline delay
.s1_enters ( s2_enters ),
.s2_enters ( s1_enters ),
.s3_enters ( s4_enters ),
.s4_enters ( s3_enters ),
.alg ( alg ),
.left ( left ),
.right ( right )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; string s; cin >> s; if (n % 4 != 0) { cout << === ; return 0; } vector<long long> v(5, 0); for (long long i = 0; i < n; i++) { if (s[i] == A ) { v[0]++; } if (s[i] == C ) { v[1]++; } if (s[i] == G ) { v[2]++; } if (s[i] == T ) { v[3]++; } if (s[i] == ? ) { v[4]++; } } long long max1 = max(v[0], max(v[1], v[2])); long long maxov = max(max1, v[3]); long long reqd = 4 * maxov - v[0] - v[1] - v[2] - v[3]; bool check = false; if (v[4] >= reqd && (v[4] - reqd) % 4 == 0) { check = true; } if (check == false) { cout << === ; } else { long long reqda = maxov - v[0] + ((v[4] - reqd) / 4); long long reqdc = maxov - v[1] + ((v[4] - reqd) / 4); long long reqdg = maxov - v[2] + ((v[4] - reqd) / 4); long long reqdt = maxov - v[3] + ((v[4] - reqd) / 4); for (long long i = 0; i < n; i++) { if (s[i] != ? ) { cout << s[i]; } else { if (reqda > 0) { cout << A ; reqda--; continue; } if (reqdc > 0) { cout << C ; reqdc--; continue; } if (reqdg > 0) { cout << G ; reqdg--; continue; } if (reqdt > 0) { cout << T ; reqdt--; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long f[61 + 1], g[61 + 1], x, k; int Q, op, pos; int main() { scanf( %d , &Q); f[0] = 1; for (int i = 1; i < 61; i++) f[i] = f[i - 1] * 2; while (Q--) { scanf( %d , &op); if (op == 1) { scanf( %I64d%I64d , &x, &k); for (int i = 0; i < 61; i++) if (f[i] >= x) { pos = i; break; } else x -= f[i]; g[pos] = (g[pos] + k) % f[pos]; } if (op == 2) { scanf( %I64d%I64d , &x, &k); for (int i = 0; i < 61; i++) if (f[i] >= x) { pos = i; break; } else x -= f[i]; k %= f[pos]; for (int i = pos; i < 61; i++) { g[i] = (g[i] + k) % f[i]; k *= 2; } } if (op == 3) { scanf( %I64d , &x); printf( %I64d , x); long long tmp = x; for (int i = 0; i < 61; i++) if (f[i] >= x) { pos = i; break; } else x -= f[i]; x = tmp; while (x != 1) { long long xx = x, fa; xx += g[pos]; if (xx < f[pos]) xx += f[pos]; if (xx >= f[pos + 1]) xx -= f[pos]; fa = xx / 2; pos--; fa -= g[pos]; if (fa < f[pos]) fa += f[pos]; if (fa >= f[pos + 1]) fa -= f[pos]; x = fa; printf( %I64d , fa); } printf( n ); } } }
|
#include <iostream> #include <vector> using namespace std; int t,k,n,m; vector<int> a,b,v; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin>>t; while (t--) { cin>>k>>n>>m; a.resize(n); b.resize(m); for (int &x:a) cin>>x; for (int &x:b) cin>>x; auto solve=[&]()->vector<int> { vector<int> sequences; int l=0,r=0,cur=k; while (true) { if (l==n && r==m) break; if (l!=n && a[l]>=0 && a[l]<=cur) { if (a[l]==0) cur++; sequences.emplace_back(a[l++]); } else if (r!=m && b[r]>=0 && b[r]<=cur) { if (b[r]==0) cur++; sequences.emplace_back(b[r++]); } else return vector<int> {-1}; } return sequences; }; v=solve(); for (int i=0;i<(int)v.size();i++) cout<<v[i]<< n [i==(int)v.size()-1]; } }
|
#include <bits/stdc++.h> using namespace std; uint64_t l, r, s; set<uint64_t> S; void f(uint64_t x) { S.insert(x); if (x < r) f(x * 10 + 4), f(x * 10 + 7); } int main() { cin >> l >> r; for (f(0); l <= r;) { auto it = S.lower_bound(l); s += (min(r, *it) - l + 1) * *it; l = *it + 1; } cout << s << n ; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int dp[1001][2010]; int digit[1002], k; void init() { memset(dp, -1, sizeof dp); } int dfs(int pos, int dist, bool doing) { if (pos == -1) return dist == 0; if (!doing && dp[pos][dist] != -1) return dp[pos][dist]; int ans = 0; int end = doing ? digit[pos] : 9; for (int i = 0; i <= end; i++) { int nextdist = dist == 0 ? 0 : dist + 1; if (i == 4 || i == 7) { if (dist <= k) nextdist = 0; else nextdist = 1; } ans = (ans + dfs(pos - 1, nextdist, doing && i == end)) % MOD; } if (!doing) dp[pos][dist] = ans; return ans; } int cal(char x[]) { int pos = 0, l = strlen(x); while (pos < l) { digit[pos] = x[l - pos - 1] - 0 ; pos++; } return dfs(pos - 1, k + 2, 1); } bool check(char x[]) { int dist = k + 1; for (int i = 0; i < strlen(x); i++) { if (!dist) break; if (x[i] == 4 || x[i] == 7 ) { if (dist <= k) dist = 0; else dist = 1; } else dist++; } return dist == 0; } int main() { int T; init(); char a[1002], b[1002]; scanf( %d %d , &T, &k); while (T--) { scanf( %s %s , a, b); int ansa = cal(a); int ansb = cal(b); if (check(a)) ansa--; ansb = ((ansb - ansa) % MOD + MOD) % MOD; printf( %d n , ansb); } return 0; }
|
#include <bits/stdc++.h> const int P = 998244353; using namespace std; template <typename T> inline void ckmax(T &a, T b) { (a < b) && (a = b); } template <typename T> inline void ckmin(T &a, T b) { (a > b) && (a = b); } inline int mul(int a, int b) { return 1ll * a * b % P; } inline int add(int a, int b) { return a + b >= P ? a + b - P : a + b; } inline int sub(int a, int b) { return a - b >= 0 ? a - b : a - b + P; } inline void mulmod(int &a, int b) { a = mul(a, b); } inline void addmod(int &a, int b) { ((a += b) >= P) && (a -= P); } inline void submod(int &a, int b) { ((a -= b) < 0) && (a += P); } inline int ksm(int a, int b) { int ans = 1; for (; b; b >>= 1) { if (b & 1) ans = 1ll * ans * a % P; a = 1ll * a * a % P; } return ans; } inline int inv(int a) { return ksm(a, P - 2); } namespace FastIO { const int SIZE = 1 << 16; char buf[SIZE], obuf[SIZE], str[64]; int bi = SIZE, bn = SIZE, opt; int read(char *s) { while (bn) { for (; bi < bn && buf[bi] <= ; bi++) ; if (bi < bn) break; bn = fread(buf, 1, SIZE, stdin), bi = 0; } int sn = 0; while (bn) { for (; bi < bn && buf[bi] > ; bi++) s[sn++] = buf[bi]; if (bi < bn) break; bn = fread(buf, 1, SIZE, stdin), bi = 0; } s[sn] = 0; return sn; } bool read(int &x) { if (x) x = 0; int bf = 0, n = read(str); if (!n) return 0; int i = 0; if (str[i] == - ) bf = 1, i = 1; for (x = 0; i < n; i++) x = x * 10 + str[i] - 0 ; if (bf) x = -x; return 1; } void write(int x) { if (!x) obuf[opt++] = 0 ; else { if (x < 0) obuf[opt++] = - , x = -x; int sn = 0; while (x) str[sn++] = x % 10 + 0 , x /= 10; for (int i = sn - 1; i >= 0; i--) obuf[opt++] = str[i]; } if (opt >= (SIZE >> 1)) { fwrite(obuf, 1, opt, stdout); opt = 0; } } void write(char x) { obuf[opt++] = x; if (opt >= (SIZE >> 1)) { fwrite(obuf, 1, opt, stdout); opt = 0; } } void Fflush() { if (opt) fwrite(obuf, 1, opt, stdout); opt = 0; } }; // namespace FastIO inline int read() { int x; FastIO::read(x); return x; } const int MN = 1e5 + 5; int n, dis[MN], dx, dy; vector<pair<int, int> > e[MN]; void dfs1(int op, int u, int fa) { if (op == 0 && dis[u] > dis[dx]) dx = u; if (op == 1 && dis[u] > dis[dy]) dy = u; for (auto it : e[u]) { int v = it.first, w = it.second; if (v == fa) continue; dis[v] = dis[u] + w; dfs1(op, v, u); } } struct Tr { int f[MN][21], g[MN][21], len[MN], top[MN], rk[MN], rt, lf[MN], s[MN], cnt, sum[MN], lson[MN]; void dfs1(int u, int fa, int fr) { f[u][0] = fa, g[u][0] = fr; for (int i = 1; i <= 20; i++) f[u][i] = f[f[u][i - 1]][i - 1], g[u][i] = g[f[u][i - 1]][i - 1] + g[u][i - 1]; for (auto it : e[u]) { int v = it.first, w = it.second; if (v == fa) continue; dfs1(v, u, w); ckmax(len[u], len[v] + w); } } void dfs2(int u, int tp) { top[u] = tp; lson[u] = 0; for (auto it : e[u]) { int v = it.first, w = it.second; if (v != f[u][0] && len[v] + w == len[u]) lson[u] = v; } if (!lson[u]) return void(); dfs2(lson[u], tp); for (auto it : e[u]) { int v = it.first; if (v != f[u][0] && v != lson[u]) s[lf[++cnt] = v] = len[v] + it.second, dfs2(v, v); } } void init() { dfs1(rt, 0, 0); dfs2(rt, rt); s[lf[++cnt] = rt] = len[rt]; sort(lf + 1, lf + 1 + cnt, [&](int i, int j) { return s[i] > s[j]; }); for (int i = (1); i <= (cnt); i++) { int u = lf[i]; sum[i] = sum[i - 1] + s[u]; while (u) rk[u] = i, u = lson[u]; } } int qry(int x, int y) { y = 2 * y - 1; if (rk[x] <= y) return sum[y]; else { int z = len[x]; for (int i = 20; i >= 0; i--) { if (rk[f[x][i]] > y) z += g[x][i], x = f[x][i]; } return max(sum[y - 1] + z + g[x][0], sum[y] - len[f[x][0]] + z + g[x][0]); } } } t[2]; signed main() { int q, k = 0, s = 0; n = read(), q = read(); for (int i = (1); i <= (n - 1); i++) { int u = read(), v = read(), w = read(); e[u].push_back(make_pair(v, w)), e[v].push_back(make_pair(u, w)); s += w; } for (int i = (1); i <= (n); i++) k += e[i].size() == 1; dfs1(0, 1, 0); memset(dis, 0, sizeof(dis)); dfs1(1, dx, 0); t[0].rt = dx, t[1].rt = dy; t[0].init(); t[1].init(); int lstans = 0; while (q--) { int x = (read() + lstans - 1) % n + 1, y = (read() + lstans - 1) % n + 1; if (2 * y >= k) printf( %d n , lstans = s); else printf( %d n , lstans = max(t[0].qry(x, y), t[1].qry(x, y))); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; vector<int> arr(n); for (int i = 0; i < n; i++) cin >> arr[i]; vector<int> temp; for (int i = 1; i < n; i++) { int val = arr[i] - arr[i - 1] - 1; temp.push_back(val); } sort(temp.begin(), temp.end()); long long int ans = arr[n - 1] - arr[0] + 1; for (int i = 1; i < k; i++) { ans = ans - temp[n - 1 - i]; } cout << ans << endl; }
|
module top(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
localparam LOG2DELAY = 22;
reg [LOG2DELAY-1:0] counter0 = 0;
reg [LOG2DELAY-1:0] counter1 = 0;
reg [LOG2DELAY-1:0] counter2 = 0;
reg [LOG2DELAY-1:0] counter3 = 0;
reg [LOG2DELAY-1:0] counter4 = 0;
reg [LOG2DELAY-1:0] counter5 = 0;
reg [LOG2DELAY-1:0] counter6 = 0;
reg [LOG2DELAY-1:0] counter7 = 0;
always @(posedge clk) begin
counter0 <= counter0 + 1;
counter1 <= counter1 + 1;
counter2 <= counter2 + 1;
counter3 <= counter3 + 1;
counter4 <= counter4 + 1;
counter5 <= counter5 + 1;
counter6 <= counter6 + 1;
counter7 <= counter7 + 1;
end
assign led[0] = counter0[LOG2DELAY-1];
assign led[1] = counter1[LOG2DELAY-1];
assign led[2] = counter2[LOG2DELAY-1];
assign led[3] = counter3[LOG2DELAY-1];
assign led[4] = counter4[LOG2DELAY-1];
assign led[5] = counter5[LOG2DELAY-1];
assign led[6] = counter6[LOG2DELAY-1];
assign led[7] = counter7[LOG2DELAY-1];
endmodule
|
module xillybus_core
(
input M_AXI_ARREADY_w,
input M_AXI_AWREADY_w,
input [1:0] M_AXI_BRESP_w,
input M_AXI_BVALID_w,
input [31:0] M_AXI_RDATA_w,
input M_AXI_RLAST_w,
input [1:0] M_AXI_RRESP_w,
input M_AXI_RVALID_w,
input M_AXI_WREADY_w,
input [31:0] S_AXI_ARADDR_w,
input S_AXI_ARVALID_w,
input [31:0] S_AXI_AWADDR_w,
input S_AXI_AWVALID_w,
input S_AXI_BREADY_w,
input S_AXI_RREADY_w,
input [31:0] S_AXI_WDATA_w,
input [3:0] S_AXI_WSTRB_w,
input S_AXI_WVALID_w,
input bus_clk_w,
input bus_rst_n_w,
input [31:0] user_r_audio_data_w,
input user_r_audio_empty_w,
input user_r_audio_eof_w,
input [7:0] user_r_mem_8_data_w,
input user_r_mem_8_empty_w,
input user_r_mem_8_eof_w,
input [31:0] user_r_read_32_data_w,
input user_r_read_32_empty_w,
input user_r_read_32_eof_w,
input [7:0] user_r_read_8_data_w,
input user_r_read_8_empty_w,
input user_r_read_8_eof_w,
input [7:0] user_r_smb_data_w,
input user_r_smb_empty_w,
input user_r_smb_eof_w,
input user_w_audio_full_w,
input user_w_mem_8_full_w,
input user_w_smb_full_w,
input user_w_write_32_full_w,
input user_w_write_8_full_w,
output [3:0] GPIO_LED_w,
output [31:0] M_AXI_ARADDR_w,
output [1:0] M_AXI_ARBURST_w,
output [3:0] M_AXI_ARCACHE_w,
output [3:0] M_AXI_ARLEN_w,
output [2:0] M_AXI_ARPROT_w,
output [2:0] M_AXI_ARSIZE_w,
output M_AXI_ARVALID_w,
output [31:0] M_AXI_AWADDR_w,
output [1:0] M_AXI_AWBURST_w,
output [3:0] M_AXI_AWCACHE_w,
output [3:0] M_AXI_AWLEN_w,
output [2:0] M_AXI_AWPROT_w,
output [2:0] M_AXI_AWSIZE_w,
output M_AXI_AWVALID_w,
output M_AXI_BREADY_w,
output M_AXI_RREADY_w,
output [31:0] M_AXI_WDATA_w,
output M_AXI_WLAST_w,
output [3:0] M_AXI_WSTRB_w,
output M_AXI_WVALID_w,
output S_AXI_ARREADY_w,
output S_AXI_AWREADY_w,
output [1:0] S_AXI_BRESP_w,
output S_AXI_BVALID_w,
output [31:0] S_AXI_RDATA_w,
output [1:0] S_AXI_RRESP_w,
output S_AXI_RVALID_w,
output S_AXI_WREADY_w,
output host_interrupt_w,
output quiesce_w,
output user_mem_8_addr_update_w,
output [4:0] user_mem_8_addr_w,
output user_r_audio_open_w,
output user_r_audio_rden_w,
output user_r_mem_8_open_w,
output user_r_mem_8_rden_w,
output user_r_read_32_open_w,
output user_r_read_32_rden_w,
output user_r_read_8_open_w,
output user_r_read_8_rden_w,
output user_r_smb_open_w,
output user_r_smb_rden_w,
output [31:0] user_w_audio_data_w,
output user_w_audio_open_w,
output user_w_audio_wren_w,
output [7:0] user_w_mem_8_data_w,
output user_w_mem_8_open_w,
output user_w_mem_8_wren_w,
output [7:0] user_w_smb_data_w,
output user_w_smb_open_w,
output user_w_smb_wren_w,
output [31:0] user_w_write_32_data_w,
output user_w_write_32_open_w,
output user_w_write_32_wren_w,
output [7:0] user_w_write_8_data_w,
output user_w_write_8_open_w,
output user_w_write_8_wren_w
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O31A_FUNCTIONAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; bool prime(long long int i) { if (i == 1) return false; if ((i == 2) || (i == 3)) return true; if ((i % 2 == 0) || (i % 3 == 0)) return false; else { for (long long int j = 5; j * j <= i; j += 6) if ((i % j == 0) || (i % (j + 2) == 0)) return false; } return true; } int main() { long long p, y, ans; cin >> p >> y; int f = 0; if (p == y) { cout << -1 ; return 0; } for (long long i = y; i > p; i--) { int f1 = 0; if (prime(i)) { f = 1; ans = i; break; } for (long long j = 2; j <= p; j++) { if (i % j == 0) { f1 = 1; break; } } if (f1 == 0) { ans = i; f = 1; break; } } if (f == 1) { cout << ans; } else { cout << -1 ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int a, b, ans; cin >> a >> b; int x = (a / 4) * 4; int i = x, val = 0; while (i < a) { val = val ^ i; i++; } if (val == b) { ans = a; } else if ((val ^ a) == b) { ans = a + 2; } else { ans = a + 1; } cout << ans << endl; return; } int main() { int t; cin >> t; while (t > 0) { solve(); t--; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 100000 + 5; const int MMAX = 2000 + 5; const int INF = 1000000000; const int BS = 1000000000 + 7; const long long INFLL = 1000000000ll * 1000000000ll; const long double eps = 1e-6; int main(int argc, char** argv) { if (argc > 1 && strcmp(argv[1], seland ) == 0) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } ios::sync_with_stdio(false); cin.tie(); cout.tie(); long long ans[2] = {0}; int cnt[2][2] = {0}; string s; int index = 0; cin >> s; for (auto c : s) { c -= a ; cnt[c][index % 2]++; ans[0] += cnt[c][(index + 1) % 2]; ans[1] += cnt[c][index % 2]; index++; } cout << ans[0] << << ans[1] << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_1_V
`define SKY130_FD_SC_HS__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_1_V
|
#include <bits/stdc++.h> using namespace std; const int LIMIT = 1e7; int prime[LIMIT], palin[LIMIT]; int pr[LIMIT], pa[LIMIT]; int cnt_dig(int x) { if (x == 0) return 1; else { int ans = 0; while (x > 0) { x /= 10; ans++; } return ans; } } int main() { int n = 4 * 1e6, dg, fl, t; stack<int> st; for (int i = 0; i < n; i++) prime[i] = true; prime[0] = prime[1] = false; prime[2] = true; for (long long i = 2; i < n; i++) { if (prime[i] == true) { for (long long j = i * i; j < n; j += i) prime[j] = false; } } for (int i = 0; i < n; i++) { dg = cnt_dig(i); t = i; if (dg == 1) palin[i] = true; else { fl = 0; if (dg & 1) { for (int j = 0; j < dg / 2; j++) { st.push(t % 10); t = t / 10; } t = t / 10; for (int j = 0; j < dg / 2; j++) { if (t % 10 == st.top()) { t = t / 10; st.pop(); } else { fl = 1; break; } } st.empty(); } else { for (int j = 0; j < dg / 2; j++) { st.push(t % 10); t = t / 10; } for (int j = 0; j < dg / 2; j++) { if (t % 10 == st.top()) { t = t / 10; st.pop(); } else { fl = 1; break; } } st.empty(); } if (fl == 0) palin[i] = true; else palin[i] = false; } } for (int i = 1; i < n; i++) { pr[i] = prime[i] + pr[i - 1]; pa[i] = palin[i] + pa[i - 1]; } double p, q; cin >> p >> q; int l = 1, r = n - 1; t = 0; int ans = 0; for (int i = 1; i < n; i++) { if (pr[i] <= double(pa[i] * (p / q))) ans = i; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int x, y, z; cin >> x >> y >> z; cout << (x + y) / z << ; if (x / z + y / z < (x + y) / z) { cout << min(z - (x % z), z - (y % z)); } else { cout << 0 ; } }
|
`default_nettype none
`define CLKFBOUT_MULT 2
// ============================================================================
module top
(
input wire clk,
input wire rst,
input wire [7:0] sw,
output wire [9:0] led,
inout wire io
);
localparam DATA_WIDTH = `DATA_WIDTH_DEFINE;
localparam DATA_RATE = `DATA_RATE_DEFINE;
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
wire CLK;
BUFG bufg(.I(clk), .O(CLK));
always @(posedge CLK)
if (rst)
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire RST = rst_sr[0];
// ============================================================================
// Clocks for ISERDES
wire PRE_BUFG_SYSCLK;
wire PRE_BUFG_CLKDIV;
wire SYSCLK;
wire CLKDIV;
wire O_LOCKED;
wire clk_fb_i;
wire clk_fb_o;
localparam DIVIDE_RATE = DATA_RATE == "SDR" ? DATA_WIDTH : DATA_WIDTH / 2;
PLLE2_ADV #(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (`CLKFBOUT_MULT),
.CLKOUT0_DIVIDE (`CLKFBOUT_MULT * 4), // SYSCLK, 25MHz
.CLKOUT1_DIVIDE ((`CLKFBOUT_MULT * 4) * DIVIDE_RATE), // CLKDIV, 25MHz / DIVIDE RATE
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1'd1)
)
pll
(
.CLKIN1 (CLK),
.CLKINSEL (1),
.RST (RST),
.PWRDWN (0),
.LOCKED (O_LOCKED),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (PRE_BUFG_SYSCLK),
.CLKOUT1 (PRE_BUFG_CLKDIV)
);
BUFG bufg_clk(.I(PRE_BUFG_SYSCLK), .O(SYSCLK));
BUFG bufg_clkdiv(.I(PRE_BUFG_CLKDIV), .O(CLKDIV));
// ============================================================================
// Test uints
wire [7:0] OUTPUTS;
wire [7:0] INPUTS = sw[7:0];
localparam MASK = DATA_WIDTH == 2 ? 8'b00000011 :
DATA_WIDTH == 3 ? 8'b00000111 :
DATA_WIDTH == 4 ? 8'b00001111 :
DATA_WIDTH == 5 ? 8'b00011111 :
DATA_WIDTH == 6 ? 8'b00111111 :
DATA_WIDTH == 7 ? 8'b01111111 :
/*DATA_WIDTH == 8*/ 8'b11111111;
wire [7:0] MASKED_INPUTS = INPUTS & MASK;
wire I_DAT;
wire O_DAT;
wire T_DAT;
IOBUF iobuf(.I(O_DAT), .O(I_DAT), .T(T_DAT), .IO(io));
serdes_test #
(
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE (DATA_RATE)
)
serdes_test
(
.SYSCLK (SYSCLK),
.CLKDIV (CLKDIV),
.RST (RST),
.OUTPUTS (OUTPUTS),
.INPUTS (MASKED_INPUTS),
.I_DAT (I_DAT),
.O_DAT (O_DAT),
.T_DAT (T_DAT)
);
wire [7:0] MASKED_OUTPUTS = OUTPUTS & MASK;
// ============================================================================
// I/O connections
reg [23:0] heartbeat_cnt;
always @(posedge SYSCLK)
heartbeat_cnt <= heartbeat_cnt + 1;
assign led[0] = heartbeat_cnt[22];
assign led[8:1] = MASKED_OUTPUTS;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_4_V
`define SKY130_FD_SC_HDLL__DIODE_4_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_4 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_4 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000001; int n, kt[N], a[N], cnt, x[N]; long long k, s; long long cal(int i) { long long res = i; return res * (res + 1) / 2; } int main() { scanf( %d%lld , &n, &k); if (k < cal(n)) { printf( -1 ); return 0; } for (int i = n; i > 0; i--) { int h = n - (n - i) / 2; if (k - h < cal(i - 1)) h = k - cal(i - 1); k -= h; kt[h]++; if (kt[h] == 2) a[++cnt] = h; } for (int i = 1; i <= n; i++) s += kt[i] * i; printf( %lld n , s); for (int i = 1; i <= n; i++) { if (kt[i] == 1) x[i] = i; else if (kt[i] == 0) { x[a[cnt]] = i; x[i] = a[cnt]; cnt--; } } for (int i = 1; i <= n; i++) printf( %d , i); printf( n ); for (int i = 1; i <= n; i++) printf( %d , x[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_N_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_MUX_2TO1_N_SYMBOL_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_mux_2to1_N (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_2TO1_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> T extgcd(T a, T b, T& x, T& y) { for (T u = y = 1, v = x = 0; a;) { T q = b / a; swap(x -= q * u, u); swap(y -= q * v, v); swap(b -= q * a, a); } return b; } template <class T> T mod_inv(T a, T m) { T x, y; extgcd(a, m, x, y); return (m + x % m) % m; } long long mod_pow(long long a, long long n, long long mod) { long long ret = 1; long long p = a % mod; while (n) { if (n & 1) ret = ret * p % mod; p = p * p % mod; n >>= 1; } return ret; } template <long long mod, long long primitive_root> class NTT { public: long long get_mod() const { return mod; } void _ntt(vector<long long>& a, long long sign) { const long long n = ((long long)(a).size()); const long long g = primitive_root; long long h = (long long)mod_pow(g, (mod - 1) / n, mod); if (sign == -1) h = (long long)mod_inv(h, mod); long long i = 0; for (long long j = 1; j < n - 1; ++j) { for (long long k = n >> 1; k > (i ^= k); k >>= 1) ; if (j < i) swap(a[i], a[j]); } for (long long m = 1; m < n; m *= 2) { const long long m2 = 2 * m; const long long base = mod_pow(h, n / m2, mod); long long w = 1; for (long long x = 0; x < (m); x++) { for (long long s = x; s < n; s += m2) { long long u = a[s]; long long d = a[s + m] * w % mod; a[s] = u + d; if (a[s] >= mod) a[s] -= mod; a[s + m] = u - d; if (a[s + m] < 0) a[s + m] += mod; } w = w * base % mod; } } for (auto& x : a) if (x < 0) x += mod; } void ntt(vector<long long>& input) { _ntt(input, 1); } void intt(vector<long long>& input) { _ntt(input, -1); const long long n_inv = mod_inv(((long long)(input).size()), mod); for (auto& x : input) x = x * n_inv % mod; } vector<long long> convolution(const vector<long long>& a, const vector<long long>& b) { long long ntt_size = 1; while (ntt_size < ((long long)(a).size()) + ((long long)(b).size())) ntt_size *= 2; vector<long long> _a = a, _b = b; _a.resize(ntt_size); _b.resize(ntt_size); ntt(_a); ntt(_b); for (long long i = 0; i < (ntt_size); i++) { (_a[i] *= _b[i]) %= mod; } intt(_a); return _a; } vector<long long> powup(const vector<long long>& a, long long exponent) { long long ntt_size = 1; while (ntt_size < (((long long)(a).size()) * exponent)) ntt_size *= 2; vector<long long> _a = a; _a.resize(ntt_size); ntt(_a); for (long long i = 0; i < (ntt_size); i++) { _a[i] = mod_pow(_a[i], exponent, mod); } intt(_a); return _a; } }; vector<long long> mul(vector<long long> a, vector<long long> b, long long mod) { for (auto& x : a) x %= mod; for (auto& x : b) x %= mod; NTT<167772161, 3> ntt1; NTT<469762049, 3> ntt2; NTT<1224736769, 3> ntt3; auto x = ntt1.convolution(a, b); auto y = ntt2.convolution(a, b); auto z = ntt3.convolution(a, b); const long long m1 = ntt1.get_mod(), m2 = ntt2.get_mod(), m3 = ntt3.get_mod(); const long long m1_inv_m2 = mod_inv<long long>(m1, m2); const long long m12_inv_m3 = mod_inv<long long>(m1 * m2, m3); const long long m12_mod = m1 * m2 % mod; vector<long long> ret(((long long)(x).size())); for (long long i = 0; i < (((long long)(x).size())); i++) { long long v1 = (y[i] - x[i]) * m1_inv_m2 % m2; if (v1 < 0) v1 += m2; long long v2 = (z[i] - (x[i] + m1 * v1) % m3) * m12_inv_m3 % m3; if (v2 < 0) v2 += m3; long long constants3 = (x[i] + m1 * v1 + m12_mod * v2) % mod; if (constants3 < 0) constants3 += mod; ret[i] = constants3; } return ret; } vector<long long> exppoly(vector<long long> base, long long e, long long mod) { vector<long long> ans = {1}; while (e > 0) { if (e % 2 == 1) { ans = mul(ans, base, mod); e--; } else { base = mul(base, base, mod); e /= 2; } } return ans; } const long long MOD = 1000000007LL; int main() { ios_base::sync_with_stdio(false); long long a, b, k, t; cin >> a >> b >> k >> t; vector<long long> v; for (long long x = 0; x < 2 * k + 1; x++) v.push_back(1); vector<long long> got = exppoly(v, t, MOD); long long len = got.size(); vector<long long> suf = got; for (long long x = len - 2; x >= 0; x--) suf[x] = (suf[x] + suf[x + 1]) % MOD; long long ans = 0; for (long long x = 0; x < len; x++) { long long me = b + x; long long youneed = max(0LL, me + 1 - a); if (youneed >= len) continue; ans += (got[x] * suf[youneed]); ans %= MOD; } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; const int maxN = 200005; const int inf = 214748364; int n, m, g[21][1 << 20], f[maxN], v[maxN], s[maxN]; int cost(int a, int b) { for (int i = m; i >= 0; --i) { if ((a & ((1 << i) - 1)) == (b >> (m - i))) return m - i; } } void init() { char c[25]; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %s , c + 1); m = strlen(c + 1); for (int j = 1; j <= m; ++j) v[i] = (v[i] << 1) + c[j] - 48; } s[1] = m; for (int i = 2; i <= n; ++i) s[i] = s[i - 1] + cost(v[i - 1], v[i]); } void work() { int ans = inf; for (int i = 0; i <= m; ++i) for (int j = 0; j <= (1 << m) - 1; ++j) g[i][j] = inf; g[0][0] = 0; f[1] = m; for (int i = 2; i <= n; ++i) { f[i] = inf; for (int j = 0; j <= m; ++j) { int tmp = s[i - 1] + g[j][v[i] >> (m - j)] + m - j; f[i] = ((f[i]) < (tmp) ? (f[i]) : (tmp)); } for (int j = 0; j <= m; ++j) g[j][v[i - 1] & ((1 << j) - 1)] = ((g[j][v[i - 1] & ((1 << j) - 1)]) < (f[i] - s[i]) ? (g[j][v[i - 1] & ((1 << j) - 1)]) : (f[i] - s[i])); } for (int i = 1; i <= n; ++i) ans = ((ans) < (f[i] + s[n] - s[i]) ? (ans) : (f[i] + s[n] - s[i])); printf( %d n , ans); } int main() { init(); work(); return 0; }
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#include <bits/stdc++.h> int main() { int i, j, k, l, p, q, m = 1, a = 0, b = 0, c = 0; char s[50001]; scanf( %s , s); l = strlen(s); i = 0; if (s[i] == a && l > 1) { for (j = i + 1; j < l; j++) { if (s[j] != a ) { if (s[j] == b ) { for (p = j + 1; p < l; p++) { if (s[p] != b ) { if (s[p] == c ) { for (q = p + 1; q < l; q++) { if (s[q] != c ) { m = 0; break; } } } else { m = 0; break; } } else { if (p == l - 1) { m = 0; break; } } } } else { m = 0; } break; } else { if (j == l - 1) { m = 0; break; } } } } else { m = 0; } for (k = 0; s[k] != 0 ; k++) { if (s[k] == a ) a++; else if (s[k] == b ) b++; else c++; } if (m == 1 && (a == c || b == c)) { printf( YES ); } else { printf( NO ); } }
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#include <bits/stdc++.h> using namespace std; long long int mod = 998244353; long double eps = 1e-12; long long int dx[] = {0, 0, 1, -1, 1, 1, -1, -1}; long long int dy[] = {1, -1, 0, 0, 1, -1, 1, -1}; long long int n, res = 0, k = 0, h, ans = 0, m; long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int lcm(long long int x, long long int y) { return (x * y) / gcd(x, y); } long long int pot(long long int a, long long int b) { long long int r = 1; while (b) { if (b % 2) r = (r * a) % mod; a = (a * a) % mod; b /= 2; } return r % mod; } void pr(long long int a[], long long int n) { for (long long int i = 1; i <= n; i++) cout << a[i] << n ; cout << n ; } void read(long long int a[], long long int n) { for (long long int i = 1; i <= n; i++) cin >> a[i]; } void yes() { cout << Yes n ; } void no() { cout << No n ; } vector<long long int> v[300015]; void add_edge(long long int x, long long int y) { v[x].push_back(y); v[y].push_back(x); } string s2, ch = , s, s1 = , t; vector<pair<string, long long int> > vs; vector<pair<pair<long long int, long long int>, long long int> > vvv, vvv2; vector<pair<long long int, long long int> > vv, vv2; long long int a[300015], b[300015] = {0}; long long int bit[300015]; void update(long long int x, long long int val) { for (; x <= n; x += x & -x) bit[x] += val; } long long int query(long long int x) { long long int sum = 0; for (; x > 0; x -= x & -x) { sum += bit[x]; } return sum; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long int i = 0, x = 0, z = 0, y = 0, j = 0, q, mx = 0, mm, idx = 0, ok = 0, l = 0, r, negatif = 0, positif = 0; set<pair<long long int, long long int> >::iterator itw, ith; multiset<long long int>::iterator it; multiset<long long int> mst, mst2; cin >> n; read(a, n); for (i = 1; i <= (long long int)(n); i++) { vv.push_back({a[i], -i}); } sort(vv.rbegin(), vv.rend()); for (i = 0; i < vv.size(); i++) vv[i].second = abs(vv[i].second); cin >> q; for (i = 1; i <= (long long int)(q); i++) { long long int k, pos; cin >> k >> pos; vvv.push_back({{k, pos}, i}); } sort(vvv.begin(), vvv.end()); j = 0; for (i = 0; i < vvv.size(); i++) { long long int k = vvv[i].first.first; long long int pos = vvv[i].first.second; long long int qidx = vvv[i].second; while (j < k) { long long int val = vv[j].first; long long int idx = vv[j].second; update(idx, 1); j++; } l = 1; r = n; res = 0; while (l <= r) { long long int mid = (l + r) / 2; long long int sum = query(mid); if (sum < pos) { res = mid; l = mid + 1; } else { r = mid - 1; } } res++; b[qidx] = a[res]; } pr(b, q); return 0; }
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#include <bits/stdc++.h> int m[6]; int w[6]; int x[6] = {0, 500, 1000, 1500, 2000, 2500}; double max(int i) { double a = 0.3 * x[i]; double b = (1 - m[i] * 1.0 / 250) * x[i] - 1.0 * 50 * w[i]; if (a > b) return a; return b; } int main() { int i, u, v; while (~scanf( %d%d%d%d%d , &m[1], &m[2], &m[3], &m[4], &m[5])) { double sum = 0; for (i = 1; i <= 5; i++) { scanf( %d , &w[i]); sum += max(i); } scanf( %d%d , &u, &v); sum += 100 * u; sum -= 50 * v; printf( %.0lf n , sum); } return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
adc_clk_in,
adc_data_in,
adc_or_in,
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
delay_clk,
dma_dbg_data,
dma_dbg_trigger,
adc_clk,
adc_dbg_data,
adc_dbg_trigger,
adc_mon_valid,
adc_mon_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_CF_BUFTYPE = 0;
input adc_clk_in;
input [13:0] adc_data_in;
input adc_or_in;
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
input delay_clk;
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
output adc_clk;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_mon_valid;
output [15:0] adc_mon_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel = 'd0;
reg up_rwn = 'd0;
reg [ 4:0] up_addr = 'd0;
reg [31:0] up_wdata = 'd0;
reg IP2Bus_RdAck = 'd0;
reg IP2Bus_WrAck = 'd0;
reg [31:0] IP2Bus_Data = 'd0;
reg IP2Bus_Error = 'd0;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_ad9649 #(.C_CF_BUFTYPE(C_CF_BUFTYPE)) i_ad9649 (
.adc_clk_in (adc_clk_in),
.adc_data_in (adc_data_in),
.adc_or_in (adc_or_in),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.delay_clk (delay_clk),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_clk (adc_clk),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> using namespace std; char ch[55][55]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> ch[i][j]; int ret = 0; for (int i = 0; i < n - 1; i++) for (int j = 0; j < m - 1; j++) { bool f = 0, a = 0, c = 0, e = 0; for (int h = i; h < i + 2; h++) for (int k = j; k < j + 2; k++) if (ch[h][k] == f ) f = 1; else if (ch[h][k] == a ) a = 1; else if (ch[h][k] == c ) c = 1; else if (ch[h][k] == e ) e = 1; if (f && a && c && e) ret++; } cout << ret << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input en,
output [C_DATA_WIDTH-1:0] dout,
output reg valid,
output reg underflow,
output fifo_ready,
input fifo_valid,
input [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
assign sync_id_ret = sync_id;
wire data_enabled;
wire [C_ID_WIDTH-1:0] data_id;
wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
reg data_ready;
wire data_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
data_ready <= 1'b1;
underflow <= 1'b0;
valid <= 1'b0;
end else begin
if (enable == 1'b1) begin
valid <= data_valid & en;
data_ready <= en & data_valid;
underflow <= en & ~data_valid;
end else begin
valid <= 1'b0;
data_ready <= 1'b1;
underflow <= en;
end
end
end
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout)
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a, fut, duim; int main() { cin >> a; a += 1; fut = a / 36; duim = round((a - fut * 36) / 3); cout << fut << << duim << endl; fclose(stdin); fclose(stdout); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_1_V
`define SKY130_FD_SC_LP__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_1_V
|
#include <bits/stdc++.h> const int intINF = 999999999; const long long i64INF = 99999999999999999ll; const double doubleINF = 9999999999.; using namespace std; int abs(int a) { if (a < 0) a *= -1; return a; } int max(int a, int b) { if (a < b) a = b; return a; } int main() { int x1, y1, x2, y2, px, py; scanf( %d%d%d%d%d%d , &px, &py, &x1, &y1, &x2, &y2); int m; int p1, p2; p1 = abs(y1 - y2); p2 = abs(x1 - x2); if ((p1 >= 3 && p2 >= 4) || (p1 >= 4 && p2 >= 3) || p1 > 4 || p2 > 4) printf( Second n ); else printf( First n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; int power(int v, int u) { if (!u) return 1; int ok = power(v, u >> 1); if (u & 1) return (long long)ok * ok % mod * v % mod; return (long long)ok * ok % mod; } const int maxm = 2e5; int b[maxm + 10]; int main() { int n, m, A; scanf( %d%d%d , &n, &m, &A); for (int i = 1; i <= m; i++) scanf( %d , &b[i]); int ans = 1; int inv2 = power(2, mod - 2); for (int i = 1; i <= m; i++) ans = (long long)ans * (((long long)power(A, 2 * (b[i] - b[i - 1])) + power(A, b[i] - b[i - 1])) % mod * inv2 % mod) % mod; ans = (long long)ans * power(A, n - b[m] - b[m]) % mod; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = 1000000001; int dp[1200][1200], out[1200][5], pre[1200][1200], a[1200]; int i, j, last, n, mi; int main() { while (~scanf( %d , &n)) { for (i = 0; i < n; i++) scanf( %d , &a[i]); if (n == 1) { printf( %d n%d n , a[0], 1); continue; } if (n == 2) { printf( %d n%d %d n , max(a[0], a[1]), 1, 2); continue; } for (i = 0; i < n; i++) for (j = 0; j < n; j++) dp[i][j] = oo; dp[1][0] = max(a[1], a[2]); dp[1][1] = max(a[0], a[2]); dp[1][2] = max(a[0], a[1]); for (i = 1; 2 * i + 2 < n; i++) { for (j = 0; j <= 2 * i; j++) { if (dp[i + 1][j] - max(a[2 * i + 2], a[2 * i + 1]) > dp[i][j]) { dp[i + 1][j] = dp[i][j] + max(a[2 * i + 2], a[2 * i + 1]); pre[i + 1][j] = j; } if (dp[i + 1][2 * i + 2] - max(a[j], a[2 * i + 1]) > dp[i][j]) { dp[i + 1][2 * i + 2] = dp[i][j] + max(a[j], a[2 * i + 1]); pre[i + 1][2 * i + 2] = j; } if (dp[i + 1][2 * i + 1] - max(a[j], a[2 * i + 2]) > dp[i][j]) { dp[i + 1][2 * i + 1] = dp[i][j] + max(a[j], a[2 * i + 2]); pre[i + 1][2 * i + 1] = j; } } } if (n % 2 == 1) { mi = oo; for (i = 0; i < n; i++) { if (mi > dp[n / 2][i] + a[i]) { mi = dp[n / 2][i] + a[i]; last = i; } } printf( %d n , mi); out[n / 2][0] = last; for (i = n / 2; i > 0; i--) { int te = pre[i][last]; if (last == 2 * i - 1) { out[i - 1][0] = te; out[i - 1][1] = 2 * i; last = te; } else if (last == 2 * i) { out[i - 1][0] = te; out[i - 1][1] = 2 * i - 1; last = te; } else { out[i - 1][0] = 2 * i - 1; out[i - 1][1] = 2 * i; last = te; } } for (i = 0; i < n / 2; i++) printf( %d %d n , out[i][0] + 1, out[i][1] + 1); printf( %d n , out[n / 2][0] + 1); } else { mi = oo; for (i = 0; i < n; i++) { if (mi > dp[n / 2 - 1][i] + max(a[i], a[n - 1])) { mi = dp[n / 2 - 1][i] + max(a[i], a[n - 1]); last = i; } } printf( %d n , mi); out[n / 2 - 1][0] = last; out[n / 2 - 1][1] = n - 1; for (i = n / 2 - 1; i > 0; i--) { int te = pre[i][last]; if (last == 2 * i - 1) { out[i - 1][0] = te; out[i - 1][1] = 2 * i; last = te; } else if (last == 2 * i) { out[i - 1][0] = te; out[i - 1][1] = 2 * i - 1; last = te; } else { out[i - 1][0] = 2 * i - 1; out[i - 1][1] = 2 * i; last = te; } } for (i = 0; i < n / 2; i++) printf( %d %d n , out[i][0] + 1, out[i][1] + 1); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, i; int fi = 0, se = 0, th = 0, fo = 0; int main() { cin >> n; cout << +------------------------+ << endl; if (n >= 3) { n--; th++; } while (n) { if (n) { fi++; n--; } if (n) { se++; n--; } if (n) { fo++; n--; } } cout << | ; for (i = 11; i; i--) { if (fi) { cout << O. ; fi--; } else { cout << #. ; } } cout << |D|) << endl; cout << | ; for (i = 11; i; i--) { if (se) { cout << O. ; se--; } else { cout << #. ; } } cout << |.| << endl; cout << | ; if (th) { cout << O ; } else { cout << # ; } cout << .......................| << endl; cout << | ; for (i = 11; i; i--) { if (fo) { cout << O. ; fo--; } else { cout << #. ; } } cout << |.|) << endl; cout << +------------------------+ << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> g[50005]; vector<int> t[50005]; int T; int col[1000005]; int team[50005]; mt19937 mt(1235577); int x[100005], y[100005]; int ans[50005]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < (int)(m); ++i) { int from, to; scanf( %d%d , &from, &to), --from, --to; x[i] = from; y[i] = to; g[from].push_back(to); g[to].push_back(from); } for (int i = 0; i < (int)(n); ++i) { int cnt; scanf( %d , &cnt); for (int j = 0; j < (int)(cnt); ++j) { int x; scanf( %d , &x), --x; T = max(T, x + 1); t[i].push_back(x); } } int times = 0; while (true) { assert(times++ < 100); for (int i = 0; i < (int)(T); ++i) { col[i] = mt() & 1; } bool ok = true; bool was[2]; for (int i = 0; i < (int)(n); ++i) { was[0] = was[1] = false; for (int x : t[i]) { was[col[x]] = true; } if (!was[0] || !was[1]) { ok = false; break; } } if (ok) { break; } } while (true) { for (int i = 0; i < (int)(n); ++i) team[i] = mt() & 1; int cnt = 0; for (int i = 0; i < (int)(m); ++i) if (team[x[i]] != team[y[i]]) { ++cnt; } if (2 * cnt < m) { continue; } for (int i = 0; i < (int)(n); ++i) { for (int x : t[i]) if (col[x] == team[i]) { ans[i] = x; break; } } bool firstTime = true; for (int i = 0; i < (int)(n); ++i) { if (!firstTime) { printf( ); } firstTime = false; printf( %d , ans[i] + 1); } printf( n ); firstTime = true; for (int i = 0; i < (int)(T); ++i) { if (!firstTime) { printf( ); } firstTime = false; printf( %d , col[i] + 1); } printf( n ); break; } return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:37 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_stub.v
// Design : ip_design_lms_pcore_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "lms_pcore,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(IPCORE_CLK, IPCORE_RESETN, AXI4_Lite_ACLK,
AXI4_Lite_ARESETN, AXI4_Lite_AWADDR, AXI4_Lite_AWVALID, AXI4_Lite_WDATA, AXI4_Lite_WSTRB,
AXI4_Lite_WVALID, AXI4_Lite_BREADY, AXI4_Lite_ARADDR, AXI4_Lite_ARVALID,
AXI4_Lite_RREADY, AXI4_Lite_AWREADY, AXI4_Lite_WREADY, AXI4_Lite_BRESP, AXI4_Lite_BVALID,
AXI4_Lite_ARREADY, AXI4_Lite_RDATA, AXI4_Lite_RRESP, AXI4_Lite_RVALID)
/* synthesis syn_black_box black_box_pad_pin="IPCORE_CLK,IPCORE_RESETN,AXI4_Lite_ACLK,AXI4_Lite_ARESETN,AXI4_Lite_AWADDR[15:0],AXI4_Lite_AWVALID,AXI4_Lite_WDATA[31:0],AXI4_Lite_WSTRB[3:0],AXI4_Lite_WVALID,AXI4_Lite_BREADY,AXI4_Lite_ARADDR[15:0],AXI4_Lite_ARVALID,AXI4_Lite_RREADY,AXI4_Lite_AWREADY,AXI4_Lite_WREADY,AXI4_Lite_BRESP[1:0],AXI4_Lite_BVALID,AXI4_Lite_ARREADY,AXI4_Lite_RDATA[31:0],AXI4_Lite_RRESP[1:0],AXI4_Lite_RVALID" */;
input IPCORE_CLK;
input IPCORE_RESETN;
input AXI4_Lite_ACLK;
input AXI4_Lite_ARESETN;
input [15:0]AXI4_Lite_AWADDR;
input AXI4_Lite_AWVALID;
input [31:0]AXI4_Lite_WDATA;
input [3:0]AXI4_Lite_WSTRB;
input AXI4_Lite_WVALID;
input AXI4_Lite_BREADY;
input [15:0]AXI4_Lite_ARADDR;
input AXI4_Lite_ARVALID;
input AXI4_Lite_RREADY;
output AXI4_Lite_AWREADY;
output AXI4_Lite_WREADY;
output [1:0]AXI4_Lite_BRESP;
output AXI4_Lite_BVALID;
output AXI4_Lite_ARREADY;
output [31:0]AXI4_Lite_RDATA;
output [1:0]AXI4_Lite_RRESP;
output AXI4_Lite_RVALID;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_1_V
`define SKY130_FD_SC_LP__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int event, ghotona; cin >> event; int hired = 0, untreated = 0; for (int i = 0; i < event; i++) { cin >> ghotona; hired += ghotona; if (hired < 0) { untreated++; hired = 0; } } cout << untreated << endl; }
|
`timescale 1ns / 1ps
//Test Multiplicador de 32 bits con signo
module TestMultiplicador;
//Inputs
reg [31:0] a;
reg [31:0] b;
//Outputs
wire [31:0] Z;
wire ovf;
//Unit under test
Multiplicador uut(
.a(a),
.b(b),
.Z(Z),
.ovf(ovf)
);
initial begin
a = 32'b0;
b = 32'b0;
#100;
a = 32'h0; b = 32'h0; //0 * 0
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h0; b = 32'h80000000; //0 * -0
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h80000000; b = 32'h0; //-0 * 0
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h400; b = 32'h400; //1 * 1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h400; b = 32'h80000400; //1 * -1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h80000400; b = 32'h80000400; //-1 * -1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h200; b = 32'h400; //.1 * 1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h508; b = 32'h989680; //1. * 10011000100101.101
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'hA8D99763; b = 32'hDE6D23E4; //-10100011011001100101. * -101111001101101001000.11111001
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h28D99763; b = 32'h5E6D23E4; //10100011011001100101. * 101111001101101001000.11111001
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'hB2EF5901; b = 32'h35905D0E; //-11001011101111010110. * 11010110010000010111.010000111
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h8000AA89; b = 32'h985; //-101010. * 10.
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h7CDC; b = 32'h11D; //11111. * 00.
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h6ECABB; b = 32'hDBF; //1101110110010. * 11.
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//bug456
typedef logic signed [34:0] rc_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [34:0] rc = crc[34:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic o; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.rc (rc),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, o};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7211d24a17b25ec9
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test( output logic o,
input rc_t rc,
input logic clk);
localparam RATIO = 2;
rc_t rc_d[RATIO:1];
always_ff @(posedge clk) begin
integer k;
rc_d[1] <= rc;
for( k=2; k<RATIO+1; k++ ) begin
rc_d[k] <= rc_d[k-1];
end
end // always_ff @
assign o = rc_d[RATIO] < 0;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; struct Interval { long long a, b, ind; bool operator<(const Interval& ano) const { return b < ano.b; } } a[200010]; bool used[200010]; set<long long> st; struct SEG { long long sum[1600010], tg1[1600010], tg2[1600010]; inline void pushup(long long u) { sum[u] = (sum[u << 1] + sum[u << 1 | 1]) % mod; } inline void pushdown(long long u, long long l, long long r) { long long mid = (l + r) >> 1; if (tg1[u]) { tg1[u << 1] = tg1[u], tg2[u << 1] = 0; sum[u << 1] = tg1[u] * (mid - l + 1) % mod; tg1[u << 1 | 1] = tg1[u], tg2[u << 1 | 1] = 0; sum[u << 1 | 1] = tg1[u] * (r - mid) % mod; tg1[u] = 0; } if (tg2[u]) { tg2[u << 1] = (tg2[u << 1] + tg2[u]) % mod; sum[u << 1] = (sum[u << 1] + (mid - l + 1) * tg2[u]) % mod; tg2[u << 1 | 1] = (tg2[u << 1 | 1] + tg2[u]) % mod; sum[u << 1 | 1] = (sum[u << 1 | 1] + (r - mid) * tg2[u]) % mod; tg2[u] = 0; } } void Build(long long u, long long l, long long r) { if (l == r) { sum[u] = tg1[u] = tg2[u] = 0; return; } long long mid = (l + r) >> 1; Build(u << 1, l, mid); Build(u << 1 | 1, mid + 1, r); pushup(u); } void Add(long long u, long long l, long long r, long long L, long long R, long long ad) { if (r < L || R < l) return; if (L <= l && r <= R) { tg2[u] = (tg2[u] + ad) % mod; sum[u] = (sum[u] + (r - l + 1) * ad) % mod; return; } pushdown(u, l, r); long long mid = (l + r) >> 1; Add(u << 1, l, mid, L, R, ad); Add(u << 1 | 1, mid + 1, r, L, R, ad); pushup(u); } void Assign(long long u, long long l, long long r, long long L, long long R, long long as) { if (r < L || R < l) return; if (L <= l && r <= R) { tg1[u] = as, tg2[u] = 0; sum[u] = (r - l + 1) * as % mod; return; } pushdown(u, l, r); long long mid = (l + r) >> 1; Assign(u << 1, l, mid, L, R, as); Assign(u << 1 | 1, mid + 1, r, L, R, as); pushup(u); } long long Query(long long u, long long l, long long r, long long L, long long R) { if (r < L || R < l) return 0; if (L <= l && r <= R) return sum[u]; pushdown(u, l, r); long long mid = (l + r) >> 1, ans = 0; ans = Query(u << 1, l, mid, L, R); ans = (ans + Query(u << 1 | 1, mid + 1, r, L, R)) % mod; pushup(u); return ans; } } S1, S2; signed main() { long long n; scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld %lld , &a[i].a, &a[i].b), a[i].ind = i; sort(a + 1, a + n + 1); long long T; scanf( %lld , &T); while (T--) { long long x; scanf( %lld , &x); used[x] = true; } S1.Build(1, 1, n << 1), S2.Build(1, 1, n << 1); st.insert(2 * n); for (long long i = 1; i <= n; i++) { long long pos = *(st.lower_bound(a[i].a)); long long s1 = S1.Query(1, 1, n << 1, pos, pos), s2 = s1 - S2.Query(1, 1, n << 1, pos, pos); S1.Assign(1, 1, n << 1, a[i].a, a[i].a, (s1 * 2 + 1) % mod); if (used[a[i].ind]) S2.Assign(1, 1, n << 1, a[i].a, a[i].a, (s1 - s2 + mod) % mod); else S2.Assign(1, 1, n << 1, a[i].a, a[i].a, (s1 * 2 + 1 - s2 + mod) % mod); if (used[a[i].ind]) S2.Assign(1, 1, n << 1, 1, a[i].a - 1, mod - s2 - 1); S1.Add(1, 1, n << 1, 1, a[i].a - 1, (s1 + 1) % mod); S2.Add(1, 1, n << 1, 1, a[i].a - 1, (s1 + 1) % mod); st.insert(a[i].a); } printf( %lld n , (S1.Query(1, 1, n << 1, 1, 1) - S2.Query(1, 1, n << 1, 1, 1) + mod) % mod); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int cnt, curk; int pos[N], fa[N]; struct Wall { int z, pos; int xmin, xmax, ymin, ymax; Wall() {} bool operator<(const Wall &x) const { return z < x.z; } } w[N]; struct Queries { int x, y; int pos; Queries() {} bool operator<(const Queries &xx) const { return curk ? x < xx.x : y < xx.y; } } ask[N]; struct K_Dimensional_Tree { struct KDT { int id, minval, x, y, xmin, xmax, ymin, ymax; int lson, rson; KDT() { minval = id = xmin = xmax = ymin = ymax = lson = rson = x = y = 0; } } t[N]; void pushup(int u) { t[u].minval = t[u].id; if (t[u].lson) { t[u].minval = min(t[u].minval, t[t[u].lson].minval); t[u].xmin = min(t[u].xmin, t[t[u].lson].xmin); t[u].xmax = max(t[u].xmax, t[t[u].lson].xmax); t[u].ymin = min(t[u].ymin, t[t[u].lson].ymin); t[u].ymax = max(t[u].ymax, t[t[u].lson].ymax); } if (t[u].rson) { t[u].minval = min(t[u].minval, t[t[u].rson].minval); t[u].xmin = min(t[u].xmin, t[t[u].rson].xmin); t[u].xmax = max(t[u].xmax, t[t[u].rson].xmax); t[u].ymin = min(t[u].ymin, t[t[u].rson].ymin); t[u].ymax = max(t[u].ymax, t[t[u].rson].ymax); } } int BuildTree(int d, int l, int r) { int p = ++cnt, u = (l + r) / 2; curk = d; nth_element(ask + l, ask + u, ask + r + 1); t[p].minval = t[p].id = ask[u].pos; pos[ask[u].pos] = p; t[p].xmin = t[p].xmax = t[p].x = ask[u].x; t[p].ymin = t[p].ymax = t[p].y = ask[u].y; if (l < u) t[p].lson = BuildTree(d ^ 1, l, u - 1), fa[t[p].lson] = p; if (r > u) t[p].rson = BuildTree(d ^ 1, u + 1, r), fa[t[p].rson] = p; pushup(p); return p; } int Query(int p, int xl, int xr, int yl, int yr) { if (t[p].xmin > xr || t[p].xmax < xl || t[p].ymin > yr || t[p].ymax < yl) return 0x3f3f3f3f; if (xl <= t[p].xmin && t[p].xmax <= xr && yl <= t[p].ymin && t[p].ymax <= yr) return t[p].minval; int ans = 0x3f3f3f3f; if (t[p].id != 0x3f3f3f3f && xl <= t[p].x && t[p].x <= xr && yl <= t[p].y && t[p].y <= yr) ans = min(ans, t[p].id); if (t[p].lson) ans = min(ans, Query(t[p].lson, xl, xr, yl, yr)); if (t[p].rson) ans = min(ans, Query(t[p].rson, xl, xr, yl, yr)); return ans; } void Del(int p) { t[p].id = 0x3f3f3f3f; while (p) { pushup(p); p = fa[p]; } } } KD; int n, ANS[N], q; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return x * f; } int main() { n = read(); for (int i = 1; i <= n; i++) w[i].xmin = read(), w[i].xmax = read(), w[i].ymin = read(), w[i].ymax = read(), w[i].z = read(), w[i].pos = i; sort(w + 1, w + n + 1); q = read(); for (int i = 1; i <= q; i++) ask[i].x = read(), ask[i].y = read(), ask[i].pos = i; KD.BuildTree(0, 1, q); for (int i = 1; i <= n; i++) { int ans = KD.Query(1, w[i].xmin, w[i].xmax, w[i].ymin, w[i].ymax); if (ans == 0x3f3f3f3f) continue; ANS[ans] = w[i].pos; KD.Del(pos[ans]); } for (int i = 1; i <= q; i++) cout << ANS[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (1e9) + 7; const long double EPS = 0.0000001; int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; string t; cin >> t; int szs = s.size(); int szt = t.size(); int cur = 0; int pref[szt + 1]; int suff[szt + 1]; for (int i = 0; i < szs; i++) { if (s[i] == t[cur]) { pref[cur] = i; cur++; } if (cur == szt) break; } cur--; for (int i = szs - 1; i >= 0; i--) { if (s[i] == t[cur]) { suff[cur] = i; cur--; } if (cur == -1) break; } int ans = 0; ans = max(ans, szs - 1 - suff[szt - 1]); ans = max(ans, suff[0]); ans = max(ans, pref[0]); ans = max(ans, szs - 1 - pref[szt - 1]); for (int i = 0; i < szt - 1; i++) { ans = max(ans, suff[i + 1] - pref[i] - 1); } cout << ans << endl; return 0; }
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
input inin,
// Outputs to the 8 onboard LEDs
output[7:0]data,
output[7:0]led
// cclk input from AVR, high when AVR is ready
/*input cclk,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
*/ );
wire rst = ~rst_n; // make reset active high
/*
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
*/
wire I_STA;
wire SETWRITE;
wire CLRWRITE;
wire WRITE;
wire [15:0] MD_OUT;
wire [15:0] AC_OUT;
wire [15:0] MMO;
assign led = MMO[7:0];
dunc16 myDunc16 (
.CLK(clk),
.ININ(inin),
.I_STA( I_STA ),
.SETWRITE( SETWRITE ),
.CLRWRITE( CLRWRITE ),
.WRITE(WRITE),
.MD_OUT( MD_OUT ),
.AC_OUT( AC_OUT ),
.MMO( MMO ),
.RESET(rst)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BLACKBOX_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_decapkapwr ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int sum[51], ind[51]; int main() { for (int i = 1; i <= 50; ++i) sum[i] = i * (i + 1) / 2; for (int i = 1; i <= 50; ++i) ind[i] = i; int n, temp, reqind; cin >> n; for (int i = 1; i <= 50; ++i) { if (n <= sum[i]) { temp = sum[i]; reqind = i; break; } } int diff = temp - n; if (diff == 0) { cout << reqind << endl; for (int k = 1; k <= reqind; ++k) cout << ind[k] << ; cout << endl; return 0; } cout << reqind - 1 << endl; for (int i = 1; i <= reqind; ++i) { if (i != diff) cout << i << ; } cout << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: fifo_4x32.v
// Project: CPCI (PCI Control FPGA)
// Description: Small 4 x 32-bit FIFO
//
// Change history:
//
///////////////////////////////////////////////////////////////////////////////
module fifo_4x32(
// PCI Signals
input [31:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [31:0] dout, // Data out
output full,
output empty,
input reset,
input clk
);
parameter MAX_DEPTH_BITS = 2;
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [31:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS - 1 + 1 : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <= depth + 'h1;
if (~wr_en & rd_en) depth <= depth - 'h1;
end
end
assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // fifo_4x32
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
#include <bits/stdc++.h> using namespace std; int i, j, k, l, x, y, z, m, n, ans; string s, a; int ara[10]; int main() { cin >> a >> s; for (int i = 0; i < s.size(); i++) { int x = s[i] - 0 ; ara[x]++; } for (int i = 0; i < a.size(); i++) { int x = a[i] - 0 ; for (int j = 9; j > x; j--) { if (ara[j]) { ara[j]--; a[i] = 0 + j; break; } } } cout << a << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv3sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
|
//#############################################################################
//# Function: General Purpose Software Programmable IO #
//# (See README.md for complete documentation) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) #
//#############################################################################
`include "gpio_regmap.vh"
module gpio #( parameter integer N = 24, // number of gpio pins
parameter integer AW = 32, // architecture address width
parameter integer PW = 104 // packet width
)
(
input nreset, // asynchronous active low reset
input clk, // clock
input access_in, // register access
input [PW-1:0] packet_in, // data/address
output wait_out, // pushback from mesh
output access_out, // register access
output [PW-1:0] packet_out, // data/address
input wait_in, // pushback from mesh
output reg [N-1:0] gpio_out, // data to drive to IO pins
output reg [N-1:0] gpio_dir, // gpio direction(0=input)
input [N-1:0] gpio_in, // data from IO pins
output gpio_irq // OR of GPIO_ILAT register
);
//################################
//# wires/regs/ params
//################################
//registers
reg [N-1:0] gpio_imask;
reg [N-1:0] gpio_itype;
reg [N-1:0] gpio_ipol;
reg [N-1:0] gpio_ilat;
reg [N-1:0] gpio_in_old;
reg [N-1:0] read_data;
//wires
wire [N-1:0] ilat_clr;
wire [N-1:0] gpio_in_sync;
wire [N-1:0] reg_wdata;
wire [N-1:0] out_dmux;
wire [N-1:0] rising_edge;
wire [N-1:0] falling_edge;
wire [N-1:0] irq_event;
wire reg_write;
wire reg_read;
wire reg_double;
wire dir_write;
wire imask_write;
wire itype_write;
wire ipol_write;
wire ilatclr_write;
wire out_write;
wire outset_write;
wire outclr_write;
wire outxor_write;
wire outreg_write;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//################################
//# DECODE LOGIC
//################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e(
/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign reg_write = access_in & write_in;
assign reg_read = access_in & ~write_in;
assign reg_double = datamode_in[1:0]==2'b11;
assign reg_wdata[N-1:0] = data_in[N-1:0];
assign dir_write = reg_write & (dstaddr_in[6:3]==`GPIO_DIR);
assign outreg_write = reg_write & (dstaddr_in[6:3]==`GPIO_OUT);
assign imask_write = reg_write & (dstaddr_in[6:3]==`GPIO_IMASK);
assign itype_write = reg_write & (dstaddr_in[6:3]==`GPIO_ITYPE);
assign ipol_write = reg_write & (dstaddr_in[6:3]==`GPIO_IPOL);
assign ilatclr_write = reg_write & (dstaddr_in[6:3]==`GPIO_ILATCLR);
assign outclr_write = reg_write & (dstaddr_in[6:3]==`GPIO_OUTCLR);
assign outset_write = reg_write & (dstaddr_in[6:3]==`GPIO_OUTSET);
assign outxor_write = reg_write & (dstaddr_in[6:3]==`GPIO_OUTXOR);
assign out_write = outreg_write |
outclr_write |
outset_write |
outxor_write;
//################################
//# GPIO_DIR
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
gpio_dir[N-1:0] <= 'b0;
else if(dir_write)
gpio_dir[N-1:0] <= reg_wdata[N-1:0];
//################################
//# GPIO_IN
//################################
oh_dsync oh_dsync[N-1:0] (.dout (gpio_in_sync[N-1:0]),
.clk (clk),
.nreset (nreset),
.din (gpio_in[N-1:0]));
always @ (posedge clk)
gpio_in_old[N-1:0] <= gpio_in_sync[N-1:0];
//################################
//# GPIO_OUT
//################################
oh_mux4 #(.DW(N))
oh_mux4 (.out (out_dmux[N-1:0]),
// Inputs
.in0 (reg_wdata[N-1:0]), .sel0 (outreg_write),
.in1 (gpio_out[N-1:0] & ~reg_wdata[N-1:0]),.sel1 (outclr_write),
.in2 (gpio_out[N-1:0] | reg_wdata[N-1:0]), .sel2 (outset_write),
.in3 (gpio_out[N-1:0] ^ reg_wdata[N-1:0]), .sel3 (outxor_write));
always @ (posedge clk or negedge nreset)
if(!nreset)
gpio_out[N-1:0] <= 'b0;
else if(out_write)
gpio_out[N-1:0] <= out_dmux[N-1:0];
//################################
//# GPIO_IMASK
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
gpio_imask[N-1:0] <= {(N){1'b1}};
else if(imask_write)
gpio_imask[N-1:0] <= reg_wdata[N-1:0];
//################################
//# GPIO_ITYPE
//################################
always @ (posedge clk)
if(itype_write)
gpio_itype[N-1:0] <= reg_wdata[N-1:0];
//################################
//# GPIO_IPOL
//################################
always @ (posedge clk)
if(ipol_write)
gpio_ipol[N-1:0] <= reg_wdata[N-1:0];
//################################
//# INTERRUPT LOGIC (DEFAULT EDGE)
//################################
assign rising_edge[N-1:0] = gpio_in_sync[N-1:0] & ~gpio_in_old[N-1:0];
assign falling_edge[N-1:0] = ~gpio_in_sync[N-1:0] & gpio_in_old[N-1:0];
assign irq_event[N-1:0] = (rising_edge[N-1:0] & ~gpio_itype[N-1:0] & gpio_ipol[N-1:0]) |
(falling_edge[N-1:0] & ~gpio_itype[N-1:0] & ~gpio_ipol[N-1:0]) |
(gpio_in_sync[N-1:0] & gpio_itype[N-1:0] & gpio_ipol[N-1:0]) |
(~gpio_in_sync[N-1:0] & gpio_itype[N-1:0] & ~gpio_ipol[N-1:0]);
//################################
//# ILAT
//################################
assign ilat_clr[N-1:0] = ilatclr_write ? reg_wdata[N-1:0] : 'b0;
always @ (posedge clk or negedge nreset)
if(!nreset)
gpio_ilat[N-1:0] <= 'b0;
else
gpio_ilat[N-1:0] <= (gpio_ilat[N-1:0] & ~ilat_clr[N-1:0]) | //old values
(irq_event[N-1:0] & ~gpio_imask[N-1:0]); //new interrupts
//################################
//# ONE CYCLE IRQ PULSE
//################################
assign gpio_irq = |gpio_ilat[N-1:0];
//################################
//# READBACK
//################################
always @ (posedge clk)
if(reg_read)
case(dstaddr_in[6:3])
`GPIO_IN : read_data[N-1:0] <= gpio_in_sync[N-1:0];
`GPIO_ILAT : read_data[N-1:0] <= gpio_ilat[N-1:0];
`GPIO_DIR : read_data[N-1:0] <= gpio_dir[N-1:0];
`GPIO_IMASK: read_data[N-1:0] <= gpio_imask[N-1:0];
`GPIO_IPOL : read_data[N-1:0] <= gpio_ipol[N-1:0];
`GPIO_ITYPE: read_data[N-1:0] <= gpio_itype[N-1:0];
default : read_data[N-1:0] <='b0;
endcase // case (dstaddr_in[7:3])
emesh_readback #(.AW(AW),
.PW(PW))
emesh_readback (/*AUTOINST*/
// Outputs
.wait_out (wait_out),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.nreset (nreset),
.clk (clk),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.read_data (read_data[63:0]),
.wait_in (wait_in));
endmodule // gpio
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_SYMBOL_V
`define SKY130_FD_SC_LS__AND4BB_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const unsigned long long inf = 0x3f3f3f3f3f3f3f3f; const unsigned long long MAXN = 1e5 + 5; unsigned long long cnt[MAXN]; vector<unsigned long long> adj[MAXN]; vector<unsigned long long> vis(MAXN, 0); void dfs(unsigned long long v) { vis[v] = 1; if (adj[v].size() == 1 && v != 1) { cnt[v] = 1; return; } for (auto u : adj[v]) { if (!vis[u]) { dfs(u); cnt[v] += cnt[u]; } } ++cnt[v]; } unsigned long long nc2(unsigned long long n) { if (n < 2) return 0; return (n * (n - 1)) / 2; } long double nc3(unsigned long long n) { if (n < 3) return 0; return ((long double)n * (n - 1) * (n - 2)) / 6.0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; unsigned long long n; cin >> n; pair<pair<unsigned long long, unsigned long long>, unsigned long long> cst[n]; for (unsigned long long i = 0; i < n - 1; i++) { unsigned long long u, v, l; cin >> u >> v >> l; adj[v].push_back(u); adj[u].push_back(v); cst[i + 1] = {{u, v}, l}; } dfs(1); long double ini = 0; long double wgt[n]; fill(wgt, wgt + n, 0); long double ttl = nc3(n); for (unsigned long long i = 1; i < n; i++) { unsigned long long u = cst[i].first.first, v = cst[i].first.second; unsigned long long lft = min(cnt[u], cnt[v]); unsigned long long rgt = n - lft; wgt[i] += (long double)lft * nc2(rgt) + rgt * nc2(lft); wgt[i] *= 2; wgt[i] /= ttl; ini += wgt[i] * cst[i].second; } unsigned long long q; cin >> q; cout << fixed << setprecision(12); while (q--) { unsigned long long idx, x; cin >> idx >> x; ini -= wgt[idx] * (cst[idx].second - x); cst[idx].second = x; long double d = ini; cout << d << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; int a[510]; vector<pair<int, int> > edges; vector<int> leaf, nonleaf; int d = 0; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { if (a[i] == 1) leaf.push_back(i); else nonleaf.push_back(i); } d = nonleaf.size() - 1 + min((int)leaf.size(), 2); int reserved = -1; if (!leaf.empty()) reserved = leaf.back(), leaf.pop_back(); for (int i = 0; i < (int)nonleaf.size() - 1; i++) { int k = nonleaf[i]; while (!leaf.empty() && a[k] > 1) { edges.push_back({leaf.back(), k}); leaf.pop_back(); a[k]--; } a[k]--; a[nonleaf[i + 1]]--; edges.push_back({k, nonleaf[i + 1]}); } int tp = 501; if (!nonleaf.empty()) tp = nonleaf.back(); if (reserved != -1) leaf.push_back(reserved); while (!leaf.empty() && a[tp] > 0) { edges.push_back({leaf.back(), tp}); leaf.pop_back(); a[tp]--; } if (leaf.empty()) { printf( YES %d n , d); printf( %d n , (int)edges.size()); for (auto k : edges) { printf( %d %d n , k.first, k.second); } } else { printf( NO n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, k, tot, i; cin >> n >> k; tot = n * (n - 1) / 2; if (tot <= k) { cout << no solution ; } else { for (i = 0; i < n; i++) { cout << 0 << << i << endl; } } return 0; }
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