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// $Id: aeMB_regf.v,v 1.3 2007-11-10 16:39:38 sybreon Exp $
//
// AEMB REGISTER FILE
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <>
//
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2007/11/09 20:51:52 sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.1 2007/11/02 03:25:41 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
module aeMB_regf (/*AUTOARG*/
// Outputs
rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
// Inputs
rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
);
// INTERNAL
output [31:0] rREGA, rREGB;
output [31:0] rDWBDI;
input [5:0] rOPC;
input [4:0] rRA, rRB, rRW, rRD;
input [1:0] rMXDST;
input [31:2] rPCLNK;
input [31:0] rRESULT;
input [3:0] rDWBSEL;
input rBRA, rDLY;
// DATA WISHBONE
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
// FSL WISHBONE
output [31:0] fsl_dat_o;
input [31:0] fsl_dat_i;
// SYSTEM
input gclk, grst, gena;
// --- LOAD SIZER ----------------------------------------------
// Moves the data bytes around depending on the size of the
// operation.
wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
reg [31:0] rDWBDI;
reg [1:0] rSIZ;
always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
/* 51.2
case (rSIZ)
// FSL
2'o3: rDWBDI <= wFSLDI;
// 32'bit
2'o2: rDWBDI <= wDWBDI;
// 16'bit
2'o1: case (rRESULT[1])
1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};
endcase // case (rRESULT[1])
// 8'bit
2'o0: case (rRESULT[1:0])
2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
endcase // case (rRESULT[1:0])
endcase // case (rSIZ)
*/
/* 50.6
case ({rSIZ, rRESULT[1:0]})
// FSL
4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;
// 32'bit
4'h8: rDWBDI <= wDWBDI;
// 16'bit
4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 8'bit
4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
default: rDWBDI <= 32'hX;
endcase // case (rSIZ)
*/
// 52.0
case (rDWBSEL)
// 8'bit
4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
// 16'bit
4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 32'bit
4'hF: rDWBDI <= wDWBDI;
// FSL
4'h0: rDWBDI <= wFSLDI;
// Undefined
default: rDWBDI <= 32'hX;
endcase
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rSIZ <= 2'h0;
// End of automatics
end else if (gena) begin
rSIZ <= rOPC[1:0];
end
// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
// LUT RAM implementation is smaller and faster. R0 gets written
// during reset with 0x00 and doesn't change after.
reg [31:0] mARAM[0:31],
mBRAM[0:31],
mDRAM[0:31];
wire [31:0] rREGW = mDRAM[rRW];
wire [31:0] rREGD = mDRAM[rRD];
assign rREGA = mARAM[rRA];
assign rREGB = mBRAM[rRB];
wire fRDWE = |rRW;
reg [31:0] xWDAT;
always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
or rRESULT)
case (rMXDST)
2'o2: xWDAT <= rDWBDI;
2'o1: xWDAT <= {rPCLNK, 2'o0};
2'o0: xWDAT <= rRESULT;
2'o3: xWDAT <= rREGW; // No change
endcase // case (rMXDST)
always @(posedge gclk)
if (grst | fRDWE) begin
mARAM[rRW] <= xWDAT;
mBRAM[rRW] <= xWDAT;
mDRAM[rRW] <= xWDAT;
end
// --- STORE SIZER ---------------------------------------------
// Replicates the data bytes across depending on the size of the
// operation.
reg [31:0] rDWBDO, xDWBDO;
wire [31:0] xFSL;
wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
assign fsl_dat_o = rDWBDO;
assign xFSL = (fFFWD_M) ? rDWBDI :
(fFFWD_R) ? rRESULT :
rREGA;
wire [31:0] xDST;
wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
assign dwb_dat_o = rDWBDO;
assign xDST = (fDFWD_M) ? rDWBDI :
(fDFWD_R) ? rRESULT :
rREGD;
always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
case (rOPC[1:0])
// 8'bit
2'h0: xDWBDO <= {(4){xDST[7:0]}};
// 16'bit
2'h1: xDWBDO <= {(2){xDST[15:0]}};
// 32'bit
2'h2: xDWBDO <= xDST;
// FSL
2'h3: xDWBDO <= xFSL;
//default: xDWBDO <= 32'hX;
endcase // case (rOPC[1:0])
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDO <= 32'h0;
// End of automatics
end else if (gena) begin
rDWBDO <= #1 xDWBDO;
end
// --- SIMULATION ONLY ------------------------------------------
// Randomise memory to simulate real-world memory
// synopsys translate_off
integer i;
initial begin
for (i=0; i<32; i=i+1) begin
mARAM[i] <= $random;
mBRAM[i] <= $random;
mDRAM[i] <= $random;
end
end
// synopsys translate_on
endmodule // aeMB_regf
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9152_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
// internal registers
reg [127:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 128'd0;
end else begin
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int a[500005]; int main() { int n, b, i, ma = 0, ju, cnt, le, st, j; scanf( %d , &n); int hahaha = 1; for (i = 0; i < n; i++) { scanf( %d , &a[i]); } le = 1; ju = a[0]; for (i = 1; i < n; i++) { if (a[i] != ju) le++; else { ma = max(ma, le); st = i - le + 1; cnt = 0; if (le >= 3) { if (le % 2 == 0) { le = (le - 2) / 2; for (j = st; j < i - 1; j++) { if (cnt < le) { a[j] = a[st - 1]; } else { a[j] = a[i]; } cnt++; } } else { for (j = st; j < i - 1; j++) { a[j] = a[st - 1]; } } } le = 1; } ju = a[i]; } ma = max(ma, le); st = i - le + 1; cnt = 0; if (le >= 3) { if (le % 2 == 0) { le = (le - 2) / 2; for (j = st; j < i - 1; j++) { if (cnt < le) { a[j] = a[st - 1]; } else { a[j] = a[i - 1]; } cnt++; } } else { for (j = st; j < i - 1; j++) { a[j] = a[st - 1]; } } } le = (ma - 1) / 2; printf( %d n , le); for (i = 0; i < n; i++) { printf( %d , a[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; long long t, n, a[maxn]; int main() { scanf( %d , &t); while (t--) { long long maxx = -1e18, ans = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > maxx) maxx = a[i]; } for (int i = 0; i < n; i++) { if (maxx == a[i]) { if (i == 0 && a[0] > a[1]) { ans = 1; break; } else if (i == n - 1 && a[n - 1] > a[n - 2]) { ans = n; break; } else if (((i != 0) && a[i] > a[i - 1]) || (i != n - 1 && a[i] > a[i + 1])) { ans = i + 1; break; } } } if (ans == 0) cout << -1 << endl; else cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long int; using int64 = long long int; template <typename T> void chmax(T &a, T b) { a = max(a, b); } template <typename T> void chmin(T &a, T b) { a = min(a, b); } template <typename T> void chadd(T &a, T b) { a = a + b; } int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; const ll INF = 1001001001001001LL; const ll MOD = 1000000007LL; int main() { int N; scanf( %d , &N); vector<int> A(N); for (int i = 0; i < N; i++) scanf( %d , &A[i]); sort(A.begin(), A.end()); ll ans = INF; { for (int x = 1; x * x <= A[0]; x++) { int d = A[0] / x, m = A[0] % x; for (int k = d; k >= d - (m == 0); k--) { int mi = k, ma = k + 1; ll sum = 0; for (int i = 0; i < N; i++) { ll b = (A[i] + ma - 1) / ma; if (mi * b <= A[i]) sum += b; else sum = INF; } ans = min(ans, sum); } } } { for (int x = 1; x * x <= A[0]; x++) { int mi = x, ma = x + 1; ll sum = 0; for (int i = 0; i < N; i++) { ll b = (A[i] + ma - 1) / ma; if (mi * b <= A[i]) sum += b; else sum = INF; } ans = min(ans, sum); } } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_1_V
`define SKY130_FD_SC_HVL__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(NULL); int n; cin >> n; priority_queue<int, vector<int>, greater<int>> servers; priority_queue<pair<int, int>, vector<pair<int, int>>, greater<pair<int, int>>> pq; for (int i = 0; i < n; i++) { servers.push(i + 1); } int q, t, k, d; cin >> q; for (int i = 0; i < q; i++) { cin >> t >> k >> d; while (pq.empty() == false) { pair<int, int> top = pq.top(); if (top.first < t) { servers.push(top.second); pq.pop(); } else { break; } } if (servers.size() >= k) { int total = 0, serverId; int endTime = t + d - 1; for (int j = 0; j < k; j++) { serverId = servers.top(); servers.pop(); total += serverId; pq.push(make_pair(endTime, serverId)); } cout << total << n ; } else { cout << -1 n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, s[444], dp[444][55][444]; int main() { cin >> n >> k; s[0] = 0; for (int i = 1; i <= n; i++) cin >> s[i], s[i] += s[i - 1]; int ans = 0; for (int i = 1; i <= n; i++) for (int j = 2; j <= min(i, k); j++) for (int l = 1; l <= i - j + 1; l++) for (int h = 1; h <= i - l - j + 2; h++) dp[i][j][l] = max(dp[i][j][l], dp[i - l][j - 1][h] + abs(s[i] + s[i - l - h] - 2 * s[i - l])); for (int i = 1; i <= n; i++) for (int j = 1; j <= i - k + 1; j++) ans = max(ans, dp[i][k][j]); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, b, cnt[105] = {0}; cin >> n; vector<int> a; for (int i = 0; i < n; i++) { cin >> b; a.push_back(b); cnt[a[i]] = cnt[a[i]] + 1; } int y = 0; int x; x = *max_element(a.begin(), a.end()); for (int i = 0; i <= x; i++) { if (cnt[i] >= y) { y = cnt[i]; } } cout << y << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void FREOPEN() {} inline double Time() { return (clock() * 1.0) / CLOCKS_PER_SEC; } const int N = (int)2000, inf = (int)2e9, MOD = (int)1e9 + 7, alph = 26; char CH[N]; const long long INF = (long long)1e18; const int dx[] = {1, -1, 0, 0, -1, 1, -1, 1}; const int dy[] = {0, 0, 1, -1, -1, 1, 1, -1}; const int dp[] = {8, 9, 1, 13, 3, 12, 7, 5, 0, 2, 4, 11, 6, 10, 15, 14}; int a[N][N]; int main() { FREOPEN(); int n; cin >> n; int num = 0; for (int bi = 0; bi < n; bi += 4) { for (int bj = 0; bj < n; bj += 4) { for (int i = bi; i < bi + 4; i++) { for (int j = bj; j < bj + 4; j++) { int p = (i - bi) * 4 + (j - bj); a[i][j] = (dp[p] ^ num); } } num += 16; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) printf( %d , a[i][j]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; pair<int, int> a[200]; pair<int, int> b[200]; int pp[200]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { int aa, bb; scanf( %d%d , &aa, &bb); a[i].first = min(aa, bb), a[i].second = max(aa, bb); } for (int i = 1; i <= m; i++) { int aa, bb; scanf( %d%d , &aa, &bb); b[i].first = min(aa, bb), b[i].second = max(aa, bb); } for (int i = 1; i <= n; i++) { bool flag1 = false, flag2 = false; for (int j = 1; j <= m; j++) { if (a[i].first != b[j].first && a[i].second == b[j].second) pp[b[j].second] = 1, flag1 = true; if (a[i].second != b[j].second && a[i].first == b[j].first) pp[b[j].first] = 1, flag2 = true; if (a[i].second != b[j].first && a[i].first == b[j].second) pp[b[j].second] = 1, flag2 = true; if (a[i].first != b[j].second && a[i].second == b[j].first) pp[b[j].first] = 1, flag1 = true; if (flag1 && flag2 && a[i].first != a[i].second) { cout << -1 << endl; return 0; } } } for (int i = 1; i <= m; i++) { bool flag1 = false, flag2 = false; for (int j = 1; j <= n; j++) { if (a[j].first != b[i].first && a[j].second == b[i].second) flag2 = true; if (a[j].second != b[i].second && a[j].first == b[i].first) flag1 = true; if (a[j].second != b[i].first && a[j].first == b[i].second) flag2 = true; if (a[j].first != b[i].second && a[j].second == b[i].first) flag1 = true; if (flag1 && flag2 && b[i].first != b[i].second) { cout << -1 << endl; return 0; } } } int sum = 0; int ans; for (int i = 1; i <= 9; i++) { if (pp[i]) ans = i; sum += pp[i]; } if (sum == 1) { cout << ans << endl; return 0; } else { cout << 0 << endl; return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int a = 26; char c[10000], ans[10000]; int p[10000], ap[10000], perm[10000]; map<int, int> m; int main() { string s, st; cin >> s; int n = s.size(), x, t, last, y; x = 17576; for (int i = 0; i < 3; i++) { x /= a; t = 0; last = -1; cout << ? ; for (int j = 0; j < n; j++) { if (j % x == 0 || last != c[j]) { t = (t + 1) % a; } last = c[j]; c[j] = char(t + a ); cout << c[j]; } cout << endl; cin >> st; for (int j = 0; j < n; j++) { y = st[j] - a ; p[j] = p[j] * a + y; ap[j] = ap[j] * a + (c[j] - a ); } } cout << ! ; for (int i = 0; i < n; i++) m[ap[i]] = i; for (int i = 0; i < n; i++) perm[i] = m[p[i]]; for (int i = 0; i < n; i++) ans[perm[i]] = s[i]; for (int i = 0; i < n; i++) cout << ans[i]; cout << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_V |
// tb_rxadc_2.v: top-level testbench for rxadc v2 in Lattice iCE40-Ultra
// 07-17-2016 E. Brombaugh
module tb_rxadc_2;
// SPI slave port
reg SPI_CSL;
reg SPI_MOSI;
wire SPI_MISO;
reg SPI_SCLK;
// rxadc board interface
reg rxadc_clk;
wire rxadc_dfs;
reg rxadc_otr;
reg [9:0] rxadc_dat;
// DAC I2S output
wire dac_mclk;
wire dac_sdout;
wire dac_sclk;
wire dac_lrck;
// MCU I2S output
reg mcu_sdin;
wire mcu_sdout;
wire mcu_sclk;
wire mcu_lrck;
// RGB output
wire o_red;
wire o_green;
wire o_blue;
// ADC NCO source
real rxadc_phs;
// spi shift
reg [39:0] sr;
reg [31:0] read_data;
// spi transaction task
task spi_rxtx
(
input rw,
input [6:0] addr,
input [31:0] wdata
);
begin: spi_task
sr = {rw,addr,wdata};
SPI_CSL = 1'b0;
SPI_SCLK = 1'b0;
SPI_MOSI = sr[39];
repeat(40)
begin
#100
SPI_SCLK = 1'b1;
#100
SPI_SCLK = 1'b0;
sr = {sr[38:0],SPI_MISO};
SPI_MOSI = sr[39];
end
#100
SPI_CSL = 1'b1;
#100
read_data = sr[31:0];
end
endtask
rxadc_2
uut(
// SPI slave port
.SPI_CSL(SPI_CSL),
.SPI_MOSI(SPI_MOSI),
.SPI_MISO(SPI_MISO),
.SPI_SCLK(SPI_SCLK),
// rxadc board interface
.rxadc_clk(rxadc_clk),
.rxadc_dfs(rxadc_dfs),
.rxadc_otr(rxadc_otr),
.rxadc_dat(rxadc_dat),
// I2S DAC output
.dac_mclk(dac_mclk),
.dac_sdout(dac_sdout),
.dac_sclk(dac_sclk),
.dac_lrck(dac_lrck),
// I2S MCU interface
.mcu_sdin(mcu_sdin),
.mcu_sdout(mcu_sdout),
.mcu_sclk(mcu_sclk),
.mcu_lrck(mcu_lrck),
// RGB output
.o_red(o_red),
.o_green(o_green),
.o_blue(o_blue)
);
// test setup
initial
begin
// initial SPI setting
SPI_CSL = 1'b1;
SPI_MOSI = 1'b0;
SPI_SCLK = 1'b0;
// initialize RXADC
rxadc_clk = 1'b0;
rxadc_otr = 1'b0;
// initialize MCU SDIN
mcu_sdin = 1'b0;
// wait for chip to init
#4000
// read ID
spi_rxtx(1'b1, 7'd00, 32'd0);
// write params - assume the defaults are good
spi_rxtx(1'b0, 7'd1, 32'd1000); // cnt_reg
spi_rxtx(1'b0, 7'h10, 32'h00000800); // freq
spi_rxtx(1'b0, 7'h11, 32'd0); // DAC mux
spi_rxtx(1'b0, 7'h12, 32'd1); // noise shaping
spi_rxtx(1'b0, 7'd3, 32'd1); // trig
spi_rxtx(1'b0, 7'd3, 32'd0); // untrig
end
// ADC clock source
always
#12.5 rxadc_clk <= ~rxadc_clk;
// ADC data source
always @(posedge rxadc_clk)
begin
rxadc_phs <= rxadc_phs + 3*3.14159/64;
//rxadc_dat <= 10'd512 + 511*$sin(rxadc_phs);
rxadc_dat <= 10'd1000;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; const int inf = 1e9; vector<int> getArray(int *a, int n, int k) { vector<int> ret; for (int i = 0; i < n * k; i++) { if (i < n) ret.push_back(a[i]); else ret.push_back(a[i % n]); } return ret; } vector<int> myLIS(vector<int> a, int n) { vector<int> dp, ret; dp.resize(n + 1); dp[0] = -inf; for (int i = 1; i <= n; i++) dp[i] = 1000; for (int i = 0; i < n; i++) { int tmp = upper_bound(dp.begin(), dp.end(), a[i]) - dp.begin(); ret.push_back(tmp); dp[tmp] = a[i]; } return ret; } int main() { int n, T, a[maxn]; scanf( %d%d , &n, &T); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } int ret = 0; if (T <= 1000) { vector<int> prefix = myLIS(getArray(a, n, T), n * T); for (int i = 0; i < n * T; i++) { ret = max(ret, prefix[i]); } } else { vector<int> newA = getArray(a, n, n); vector<int> prefix = myLIS(newA, n * n); for (int i = 0; i < newA.size(); i++) { newA[i] = -newA[i]; } reverse(newA.begin(), newA.end()); vector<int> suffix = myLIS(newA, n * n); for (int i = 0; i < n; i++) { int cnt = 0; for (int j = 0; j < n; j++) if (a[i] == a[j]) cnt++; for (int j = 0; j < n; j++) { if (a[j] < a[i]) continue; ret = max(ret, prefix[(n - 1) * n + i] + cnt * (T - 2 * n) + suffix[n * n - j - 1]); } } } cout << ret << endl; return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple multiplexer
// Author: Dustin Richmond (@darichmond)
// TODO: Remove C_CLOG_NUM_INPUTS
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module mux
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32,
parameter C_MUX_TYPE = "SELECT"
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
`include "functions.vh"
generate
if(C_MUX_TYPE == "SELECT") begin
mux_select
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_select_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end else if (C_MUX_TYPE == "SHIFT") begin
mux_shift
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_shift_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end
endgenerate
endmodule
module mux_select
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH-1:0] wMuxInputs[C_NUM_INPUTS-1:0];
assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
generate
for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
end
endgenerate
endmodule
module mux_shift
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH*C_NUM_INPUTS-1:0] wMuxInputs;
assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;
assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_SYMBOL_V
|
#include <bits/stdc++.h> int a[6] = {0, 2, 3, 1, 2, 1}; int main() { int n; scanf( %d , &n); printf( %d n , a[n]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string line; int persons = 0; int data = 0; while (getline(cin, line)) { if (line[0] == + ) ++persons; else if (line[0] == - ) --persons; else data += (line.size() - line.find( : ) - 1) * persons; } cout << data << endl; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int N = 1e5 + 7, M = 1e7, OO = 0x3f3f3f3f; int main() { int n, m, array1[100][100], mini, maxi = -OO, i, j; scanf( %d %d , &n, &m); for (i = 0; i < n; ++i) { for (j = 0; j < m; ++j) { scanf( %d , &array1[i][j]); } } for (i = 0; i < n; ++i) { mini = OO; for (j = 0; j < m; ++j) { mini = min(mini, array1[i][j]); } maxi = max(maxi, mini); } printf( %d , maxi); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100005; int cnt[MAX_N]; int main() { cin.tie(0); ios::sync_with_stdio(false); int n; cin >> n; vector<int> vec(n); for (int i = 0; i < (int)(n); ++i) { cin >> vec[i]; } int m1 = -1, m2 = -2; int id1 = -1, id2 = -1; for (int i = 0; i < (int)(n); ++i) { if (vec[i] > m1) { cnt[i] -= 1; m2 = m1, id2 = id1; m1 = vec[i], id1 = i; } else if (vec[i] > m2) { cnt[id1] += 1; m2 = vec[i], id2 = i; } } vector<pair<int, int> > res; for (int i = 0; i < (int)(n); ++i) { res.push_back(pair<int, int>(cnt[i], -vec[i])); } sort((res).begin(), (res).end(), greater<pair<int, int> >()); cout << -res[0].second << n ; return 0; } |
`timescale 1ns / 1ps
// Name: WcaWriteFifo8W32R.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaWriteFifo32(
input wire reset, //Active Hi
input wire rd_clk, // Clock read input..
input wire rd_en, // Enables reading.
output wire [31:0] out, // Read Data output.
output wire empty, // Active high indicates buffer is empty.
output wire full, // Active high indicates buffer is empty.
//data Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire wr_busy = (my_addr == rbusCtrl[11:4]) & rbusCtrl[2];
wire wr_en = wr_busy & rbusCtrl[1];
FifoCore8W32R fifo8W32Rcore (
.rst(reset), // input rst
.wr_clk(rbusCtrl[0]), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(rbusData), // input [7 : 0] din
.wr_en(wr_busy), // input wr_en
.rd_en(rd_en ), // input rd_en
.dout(out), // output [31 : 0] dout
.full(full), // output full
.empty(empty), // output empty
.prog_full(),
.prog_empty()
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module vita_rx_tb;
localparam DECIM = 8'd4;
localparam MAXCHAN=1;
localparam NUMCHAN=1;
reg clk = 0;
reg reset = 1;
initial #1000 reset = 0;
always #50 clk = ~clk;
initial $dumpfile("vita_rx_tb.vcd");
initial $dumpvars(0,vita_rx_tb);
wire [(MAXCHAN*32)-1:0] sample;
wire strobe, run;
wire [35:0] data_o;
wire src_rdy;
reg dst_rdy = 1;
wire [63:0] vita_time;
reg set_stb = 0;
reg [7:0] set_addr;
reg [31:0] set_data;
wire set_stb_dsp;
wire [7:0] set_addr_dsp;
wire [31:0] set_data_dsp;
/*
settings_bus_crossclock settings_bus_xclk_dsp
(.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
.clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
*/
wire sample_dst_rdy, sample_src_rdy;
//wire [99:0] sample_data_o;
wire [64+5+(MAXCHAN*32)-1:0] sample_data_o;
vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
(.clk(clk), .reset(reset), .clear(0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time), .overrun(overrun),
.sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy),
.sample(sample), .run(run), .strobe(strobe));
vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
(.clk(clk), .reset(reset), .clear(0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
.sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
.fifo_occupied(), .fifo_full(), .fifo_empty() );
rx_dsp_model rx_dsp_model
(.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0]));
generate
if(MAXCHAN>1)
assign sample[(MAXCHAN*32)-1:32] = 0;
endgenerate
time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit
(.clk(clk), .rst(reset),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.pps(0), .vita_time(vita_time));
always @(posedge clk)
if(src_rdy & dst_rdy)
begin
if(data_o[32] & ~data_o[33])
begin
$display("RX-PKT-START %d",$time);
$display(" RX-PKT-DAT %x",data_o[31:0]);
end
else if(data_o[32] & data_o[33])
begin
$display(" RX-PKT-DAT %x -- With ERR",data_o[31:0]);
$display("RX-PKT-ERR %d",$time);
end
else if(~data_o[32] & data_o[33])
begin
$display(" RX-PKT-DAT %x",data_o[31:0]);
$display("RX-PKT-END %d",$time);
end
else
$display(" RX-PKT DAT %x",data_o[31:0]);
end
initial
begin
@(negedge reset);
@(posedge clk);
write_setting(4,32'h15F00000); // VITA header
write_setting(5,32'hF00D1234); // VITA streamid
write_setting(6,32'hE0000000); // VITA trailer
write_setting(7,8); // Samples per VITA packet
write_setting(8,NUMCHAN); // Vector length
queue_rx_cmd(1,1,0,10,32'h0,32'h0); // send imm, single packet
#10000;
queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet
//queue_rx_cmd(1,1,0,0,32'h0,32'h0); // send imm, single packet
//queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet
/*
queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet
queue_rx_cmd(1,0,0,16,32'h0,32'h0); // send imm, 2 packets worth
queue_rx_cmd(1,0,0,7,32'h0,32'h0); // send imm, 1 short packet worth
queue_rx_cmd(1,0,0,9,32'h0,32'h0); // send imm, just longer than 1 packet
queue_rx_cmd(1,1,0,16,32'h0,32'h0); // chained
queue_rx_cmd(0,0,0,8,32'h0,32'h0); // 2nd in chain
queue_rx_cmd(1,1,0,17,32'h0,32'h0); // chained, odd length
queue_rx_cmd(0,0,0,9,32'h0,32'h0); // 2nd in chain, also odd length
queue_rx_cmd(0,0,0,8,32'h0,32'h340); // send at, on time
queue_rx_cmd(0,0,0,8,32'h0,32'h100); // send at, but late
#100000;
$display("\nChained, break chain\n");
queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained, but break chain
#100000;
$display("\nSingle packet\n");
queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet
#100000;
$display("\nEnd chain with zero samples, shouldn't error\n");
queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained
queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
#100000;
$display("\nEnd chain with zero samples on odd-length, shouldn't error\n");
queue_rx_cmd(1,1,0,14,32'h0,32'h0); // chained
queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error
#100000;
$display("Should have gotten 14 samples and EOF by now\n");
queue_rx_cmd(1,1,0,9,32'h0,32'h0); // chained, but break chain, odd length
#100000;
dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun
queue_rx_cmd(1,0,0,100,32'h0,32'h0); // long enough to fill the fifos
queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent
#100000;
dst_rdy <= 1; // restart the reads so we can see what we got
#100000;
dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun
queue_rx_cmd(1,1,0,100,32'h0,32'h0); // long enough to fill the fifos
//queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent
#100000;
@(posedge clk);
dst_rdy <= 1;
*/
#100000 $finish;
end
task write_setting;
input [7:0] addr;
input [31:0] data;
begin
set_stb <= 0;
@(posedge clk);
set_addr <= addr;
set_data <= data;
set_stb <= 1;
@(posedge clk);
set_stb <= 0;
end
endtask // write_setting
task queue_rx_cmd;
input send_imm;
input chain;
input reload;
input [28:0] lines;
input [31:0] secs;
input [31:0] tics;
begin
write_setting(0,{send_imm,chain,reload,lines});
write_setting(1,secs);
write_setting(2,tics);
end
endtask // queue_rx_cmd
endmodule // rx_control_tb
module rx_dsp_model
(input clk, input reset,
input run,
input [7:0] decim,
output strobe,
output [31:0] sample);
reg [15:0] pktnum = 0;
reg [15:0] counter = 0;
reg run_d1;
always @(posedge clk) run_d1 <= run;
always @(posedge clk)
if(run & ~run_d1)
begin
counter <= 0;
pktnum <= pktnum + 1;
end
else if(run & strobe)
counter <= counter + 1;
assign sample = {pktnum,counter};
reg [7:0] stb_ctr = 0;
always @(posedge clk)
if(reset)
stb_ctr <= 0;
else if(run & ~run_d1)
stb_ctr <= 1;
else if(run)
if(stb_ctr == decim-1)
stb_ctr <= 0;
else
stb_ctr <= stb_ctr + 1;
assign strobe = stb_ctr == decim-1;
endmodule // rx_dsp_model
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_2_V
`define SKY130_FD_SC_MS__EINVP_2_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvp_2 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvp_2 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_2_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_to_ieee(clock, resetn, mantissa, exponent, sign, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input [26:0] mantissa;
input [8:0] exponent;
input sign;
output [31:0] result;
input valid_in, stall_in, enable;
output valid_out, stall_out;
parameter FINITE_MATH_ONLY = 1;
assign valid_out = valid_in;
assign stall_out = stall_in;
generate
if (FINITE_MATH_ONLY == 0)
assign result = {sign, {8{exponent[8]}} | exponent[7:0], mantissa[25:3]};
else
assign result = {sign, exponent[7:0], mantissa[25:3]};
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mn = 1000001; bool shirt(int p, int s) { int i = (s / 50) % 475; for (int j = 0; j < 25; j++) { i = (i * 96 + 42) % 475; if ((26 + i) == p) return true; } return false; } int main() { int p, x, y; cin >> p >> x >> y; int al = 0, temp = x; while (1 && temp >= y) { if (shirt(p, temp)) { cout << 0 << endl; return 0; } temp -= 50; } int ah = 0; temp = x; while (1) { if (shirt(p, temp)) break; if ((temp - 50) >= y) { if (shirt(p, temp - 50)) break; } temp += 100; ah++; } int v = temp - x; int ans = v / 100; cout << ah << endl; } |
#include <bits/stdc++.h> using namespace std; int n, a[110]; vector<int> prime; bool flag[40010]; int cnt[40010][110]; void init(int MX) { for (int i = 2; i <= MX; i++) { if (!flag[i]) prime.push_back(i); for (int j = 0; j < prime.size() && i * prime[j] <= MX; j++) { flag[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } } int ans = 0; map<int, int> sg, m; void dfs(int x) { if (sg.count(x)) return; bool vis[32]; memset(vis, 0, sizeof(vis)); for (int i = 1; x >> (i - 1); i++) { int mask = (x >> i) | (x & ((1 << (i - 1)) - 1)); dfs(mask); vis[sg[mask]] = 1; } for (int i = 0;; i++) { if (!vis[i]) { sg[x] = i; return; } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); init(40000); for (int j = 0; j < prime.size(); j++) { for (int i = 1; i <= n; i++) { while (a[i] % prime[j] == 0) { a[i] /= prime[j]; cnt[j][i]++; } if (cnt[j][i]) m[j] |= (1 << (cnt[j][i] - 1)); } } for (int i = 1; i <= n; i++) if (a[i] > 1) m[a[i]] |= 1; sg[0] = 0; for (map<int, int>::iterator it = m.begin(); it != m.end(); it++) { dfs(it->second); ans ^= sg[it->second]; } puts(ans ? Mojtaba : Arpa ); return 0; } |
#define _CRT_SECURE_NO_DEPRECATE #define _USE_MATH_DEFINES #include <array> #include <iostream> #include <fstream> #include <cstdio> #include <cstdlib> #include <cassert> #include <climits> #include <ctime> #include <numeric> #include <vector> #include <algorithm> #include <bitset> #include <cmath> #include <cstring> #include <iomanip> #include <complex> #include <deque> #include <functional> #include <list> #include <map> #include <string> #include <sstream> #include <set> #include <unordered_set> #include <unordered_map> #include <stack> #include <queue> #include <forward_list> #include <thread> #include <random> using namespace std; typedef long long LL; typedef unsigned long long ULL; typedef unsigned int uint; typedef unsigned char uchar; typedef double ld; typedef pair<int, int> pii; typedef pair<short, short> pss; typedef pair<LL, LL> pll; typedef pair<ULL, ULL> puu; typedef pair<ld, ld> pdd; template<class T> inline T sqr(T x) { return x * x; } #define left asdleft #define right asdright #define link asdlink #define unlink asdunlink #define y0 asdy0 #define y1 asdy1 #define mp make_pair #define MT make_tuple #define pb push_back #define EB emplace_back #define sz(x) ((int)(x).size()) #define all(x) (x).begin(), (x).end() #define clr(ar,val) memset(&ar, val, sizeof(ar)) #define forn(i,n) for(int i=0;i<(n);++i) #define forv(i,v) forn(i,sz(v)) #define X first #define Y second const ld EPS = 1e-11; const int INF = 1000*1000*1000; const LL LINF = INF * 1ll * INF; const ld DINF = 1e200; const ld PI = 3.1415926535897932384626433832795l; int gcd(int a,int b){return a?gcd(b%a,a):b;} LL gcd(LL a,LL b){return a?gcd(b%a,a):b;} LL gcdex(LL a,LL b,LL &x,LL &y){if(!a){x=0,y=1;return b;}LL k=b/a;LL g=gcdex(b-k*a,a,y,x);x-=k*y;return g;} LL inv(LL a,LL m){assert(m>1);LL x,y,g;g=gcdex(a,m,x,y);return (x%(m/g)+m/g)%m/g;} LL crt(LL a1,LL m1,LL a2,LL m2){LL a=(a2-a1%m2+m2)%m2;LL x,y,g;g=gcdex(m1,m2,x,y);if(a%g)return -1;LL m=m1/g*m2;assert(x+m2>=0);x=a/g*(x+m2)%m2;LL r=(a1+x*m1)%m;assert(r%m1==a1 && r%m2==a2);return r;} LL powmod(LL a,LL p,LL m){assert(p>=0);LL r=1;while(p){if(p&1)r=r*a%m;p>>=1;a=a*a%m;}return r;} LL mulmod(LL a,LL b,LL m){/*Schrage s*/assert(a>=0&&b>=0&&m>0&&a<m&&b<m);if(b<a)swap(a,b);if(m<INF*2||a<=1)return a*b%m;LL q=m/a,r=m%a;LL v=a*(b%q)-(r<q?r*(b/q):mulmod(r,b/q,m));if(v<0){v+=m;assert(v>=0);}return v;} LL powmod2(LL a,LL p,LL m){a%=m;LL r=1;while(true){if(p&1) r=mulmod(r,a,m);p>>=1;if(p)a=mulmod(a,a,m);else break;}return r;} bool isprime(LL a){if(a<=1)return false;for (LL i=2;i*i<=a;++i){if(a%i==0)return false;}return true;} LL sqrtup(LL a){if(!a)return 0;LL x=max(0ll,(LL)sqrt((ld)a));while(x*x>=a)--x;while((x+1)*(x+1)<a)++x;return x+1;} LL isqrt(LL a){if(a<=0){assert(!a);return 0;}LL x=(LL)sqrt((ld)a);while(sqr(x+1)<=a)++x;while(x*x>a)--x;return x;} LL sgn(LL x){return x<0?-1:x>0?1:0;} ld randf(){ld m=RAND_MAX+1.;return (((rand()+.5)/m+rand())/m+rand())/m;} int rand30(){assert(RAND_MAX>=(1<<15)-1); return (int)((((uint32_t)rand())*(1u+(uint32_t)RAND_MAX)+(uint32_t)rand())&((1u<<30)-1));} template<class T> void smin(T& a,T b){a=min(a,b);} template<class T> void smax(T& a,T b){a=max(a,b);} template<class T> ostream& operator<<(ostream &s, const vector<T> &v); template<class A,class B> ostream& operator<<(ostream &s, const pair<A,B> &p); template<class K,class V> ostream& operator<<(ostream &s, const map<K,V> &m); template<class T> ostream& operator<<(ostream &s, const set<T> &m); template<class T,size_t N> ostream& operator<<(ostream &s, const array<T,N> &a); template<class... T> ostream& operator<<(ostream &s, const tuple<T...> &t); template<class T> ostream& operator<<(ostream &s, const vector<T> &v){s<< [ ;forv(i,v){if(i)s<< , ;s<<v[i];}s<< ] ;return s;} template<class A,class B> ostream& operator<<(ostream &s, const pair<A,B> &p){s<< ( <<p.X<< , <<p.Y<< ) ;return s;} template<class K,class V> ostream& operator<<(ostream &s, const map<K,V> &m){s<< { ;bool f=false;for(const auto &it:m){if(f)s<< , ;f=true;s<<it.X<< : <<it.Y;}s<< } ;return s;} template<class T> ostream& operator<<(ostream &s, const set<T> &m){s<< { ;bool f=false;for(const auto &it:m){if(f)s<< , ;f=true;s<<it;}s<< } ;return s;} template<class T> ostream& operator<<(ostream &s, const multiset<T> &m){s<< { ;bool f=false;for(const auto &it:m){if(f)s<< , ;f=true;s<<it;}s<< } ;return s;} template<class T,class V,class C> ostream& operator<<(ostream &s, const priority_queue<T,V,C> &q) {auto a=q;s<< { ;bool f=false;while(!a.empty()){if(f)s<< , ;f=true;s<<a.top();a.pop();}return s<< } ;} template<class T,size_t N> ostream& operator<<(ostream &s, const array<T,N> &a){s<< [ ;forv(i,a){if(i)s<< , ;s<<a[i];}s<< ] ;return s;} template<class T> ostream& operator<<(ostream &s, const deque<T> &a){s<< [ ;forv(i,a){if(i)s<< , ;s<<a[i];}s<< ] ;return s;} template<size_t n,class... T> struct put1 { static ostream& put(ostream &s, const tuple<T...> &t){s<<get<sizeof...(T)-n>(t);if(n>1)s<< , ;return put1<n-1,T...>::put(s,t);} }; template<class... T> struct put1<0,T...> { static ostream& put(ostream &s, const tuple<T...> &t){return s;} }; template<class... T> ostream& operator<<(ostream &s, const tuple<T...> &t){s<< ( ;put1<sizeof...(T),T...>::put(s,t);s<< ) ;return s;} ostream& put3(ostream &s, const char*, bool) {return s;} template<class U,class... T> ostream& put3(ostream &s, const char *f, bool fs, U&& u, T&&... t) { while(*f== )++f;if (!fs)s<< , ;auto nf=f;int d=0;while(*nf&&(*nf!= , ||d)){if(*nf== ( )++d;else if(*nf== ) )--d;++nf;} auto nf2=nf;while(nf2>f&&*(nf2-1)== )--nf;fs=*f== ;if(!fs){s.write(f,nf2-f);s<< = ;};s<<u;if(fs)s<< ;if(*nf)++nf;return put3(s,nf,fs,forward<T>(t)...);} #ifdef __ASD__ auto qweasdt0 = chrono::steady_clock::now(); #define dbg(...) do { cerr.setf(ios::fixed,ios::floatfield);cerr.precision(6);double qweasdt = chrono::duration_cast<chrono::duration<double>>(chrono::steady_clock::now() - qweasdt0).count();cerr << [ << __LINE__ << << qweasdt << ] ; put3(cerr, #__VA_ARGS__, 1, ##__VA_ARGS__); cerr << endl; }while(false) #include draw.h #define draw(x,...) dr::get().add((new dr::x)__VA_ARGS__) #define drawc(x) dr::get().x #else #define dbg(...) do{}while(false) #define draw(...) do{}while(false) #define drawc(...) do{}while(false) #endif mt19937 mtrng; struct node{ node*l=0,*r=0; LL v=0; }; array<node,10000000> nodes; int nodecnt; node*alloc(){ assert(nodecnt<sz(nodes)); return &nodes[nodecnt++]; } node* mktree(int a,int b){ node*n=alloc(); if(b==a+1) return n; int c=(a+b)/2; n->l=mktree(a,c); n->r=mktree(c,b); return n; } node*add(int p,LL v,int a,int b,const node*n){ node*m=alloc(); *m=*n; m->v^=v; if(b==a+1) return m; int c=(a+b)/2; if(p<c) m->l=add(p,v,a,c,n->l); else m->r=add(p,v,c,b,n->r); return m; } int find(int l,int a,int b,const node*n,const node*m,int p,LL v){ if(!(n->v^m->v^((p>=a&&p<b)?v:0ll)) || l>=b) return -1; if(b==a+1) return a; int c=(a+b)/2; int t=find(l,a,c,n->l,m->l,p,v); if(t!=-1) return t; return find(l,c,b,n->r,m->r,p,v); } vector<vector<int>> G; vector<int> A; vector<int> H; vector<node*> V; vector<int> D; vector<array<int,20>> J; void dfs(int v,node*n,int d,int pr){ n=add(A[v],H[A[v]],0,sz(A),n); V[v]=n; D[v]=d; J[v][0]=pr; forn(i,sz(J[v])-1) J[v][i+1]=J[J[v][i]][i]; for(int p:G[v]){ if(p==pr) continue; dfs(p,n,d+1,v); } } int jump(int a,int d){ for(int i=sz(J[a])-1;i>=0;--i) if(D[J[a][i]]>=d) a=J[a][i]; return a; } int lca(int a,int b){ int d=min(D[a],D[b]); a=jump(a,d); b=jump(b,d); if(a==b) return a; for(int i=sz(J[0])-1;i>=0;--i) if(J[a][i]!=J[b][i]){ a=J[a][i]; b=J[b][i]; } return J[a][0]; } int main(int argc, char **argv){ ios_base::sync_with_stdio(false);cin.tie(0);cout.precision(20);srand(35964);mtrng.seed(765674737); int n,tc; cin>>n>>tc; A.resize(n); H.resize(n); forn(i,n){ cin>>A[i]; --A[i]; H[i]=(((LL)rand30())<<30)+rand30(); } G.resize(n); forn(i,n-1){ int a,b; cin>>a>>b; --a;--b; G[a].pb(b); G[b].pb(a); } V.resize(n); D.resize(n); J.resize(n); dfs(0,mktree(0,sz(A)),0,0); forn(qq,tc){ int u,v,a,b; cin>>u>>v>>a>>b; --u;--v;--a; int w=lca(u,v); int t=find(a,0,sz(A),V[u],V[v],A[w],H[A[w]]); if(t==-1||t>=b) cout<< -1 n ; else cout<<t+1<< n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> ans{1}, pr{2, 3, 5, 7, 11}; int main() { cin >> n; for (int p : pr) { if (ans.size() > n) break; for (int i = 0; i < (int)ans.size(); i++) { if (ans[i] * p <= 2 * n * n) ans.emplace_back(ans[i] * p); } } reverse(begin(ans), end(ans)); ans.resize(n); for (int x : ans) cout << x << ; } |
module main;
reg [7:0] period;
reg drive;
wire trace;
// This is the main point of the test. Non-constant delay expressions
// should work here.
assign #(period) trace = drive;
initial begin
period = 8;
// Initially, set up a period=8 and get the trace to start
// following the drive.
#1 drive <= 1;
#9 if (trace !== drive) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
// The drive should NOT change the trace before the period.
drive <= 0;
#7 if (trace !== 1'b1) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
#2 if (trace !== drive) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
// Change the period.
period = 6;
// Now check that the new delay is taken.
#1 drive <= 1;
#5 if (trace !== 1'b0) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
#2 if (trace !== drive) begin
$display("FAILED -- time=%0t, drive=%b, trace=%b",
$time, drive, trace);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, c; cin >> n >> a >> b >> c; int x, y, z, p = 0, i; i = min(a, min(b, c)); i = n / i; for (x = i; x >= 0; x--) { for (y = 0; y <= i; y++) { z = abs((n - (a * x + b * y)) / c); if ((a * x + b * y + c * z) == n) { p = max(p, x + y + z); } } } cout << p << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 40; int v[N], x[N], ct, al[N], col[N], n, lu[N], lv[N]; int read() { int sum = 0, fg = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fg = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum * fg; } inline void add(int u, int V) { v[++ct] = V; x[ct] = al[u]; al[u] = ct; } inline void dfs(int u, int tw) { col[u] = tw; for (int i = al[u]; i; i = x[i]) if (col[v[i]] == -1) dfs(v[i], tw ^ 1); } int main() { n = read(); for (int i = 1; i <= n; i++) col[i] = -1; for (register int i = 1, x, y; i <= n; i++) { x = read(); y = read(); if (lu[x]) { add(lu[x], i); add(i, lu[x]); lu[x] = 0; } else lu[x] = i; if (lv[y]) { add(lv[y], i); add(i, lv[y]); lv[y] = 0; } else lv[y] = i; } for (register int i = 1; i <= n; i++) if (col[i] == -1) dfs(i, 0); for (register int i = 1; i <= n; i++) if (col[i] == 0) cout << b ; else cout << r ; return 0; } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module scales down the frame size of video streams for the DE boards. *
* *
******************************************************************************/
module altera_up_video_scaler_shrink (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter WW = 9; // Image In: width's address width
parameter HW = 9; // Image In: height's address width
parameter WIDTH_IN = 640; // Image In's width in pixels
parameter WIDTH_DROP_MASK = 4'b0101;
parameter HEIGHT_DROP_MASK = 4'b0000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire drop;
wire capture_inputs;
wire transfer_data;
// Internal Registers
reg saved_startofpacket;
reg [DW: 0] data;
reg startofpacket;
reg endofpacket;
reg valid;
reg [WW: 0] width_counter;
reg [HW: 0] height_counter;
reg [ 3: 0] drop_pixel;
reg [ 3: 0] drop_line;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= data;
stream_out_startofpacket <= startofpacket;
stream_out_endofpacket <= endofpacket;
stream_out_valid <= valid;
end
else if (stream_out_ready & stream_out_valid)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
end
// Internal Registers
always @(posedge clk)
if (reset)
saved_startofpacket <= 1'b0;
else if (capture_inputs)
saved_startofpacket <= 1'b0;
else if (stream_in_ready)
saved_startofpacket <= saved_startofpacket | stream_in_startofpacket;
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (capture_inputs)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket | saved_startofpacket;
endofpacket <= stream_in_endofpacket;
valid <= stream_in_valid;
end
else if (stream_in_ready)
endofpacket <= endofpacket | stream_in_endofpacket;
end
always @(posedge clk)
begin
if (reset)
width_counter <= 'h0;
else if (stream_in_ready)
begin
if (stream_in_startofpacket | (width_counter == (WIDTH_IN - 1)))
width_counter <= 'h0;
else
width_counter <= width_counter + 1;
end
end
always @(posedge clk)
begin
if (reset)
height_counter <= 'h0;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
height_counter <= 'h0;
else if (width_counter == (WIDTH_IN - 1))
height_counter <= height_counter + 1;
end
end
always @(posedge clk)
begin
if (reset)
drop_pixel <= 4'b0000;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
drop_pixel <= WIDTH_DROP_MASK;
else if (width_counter == (WIDTH_IN - 1))
drop_pixel <= WIDTH_DROP_MASK;
else
drop_pixel <= {drop_pixel[2:0], drop_pixel[3]};
end
end
always @(posedge clk)
begin
if (reset)
drop_line <= 4'b0000;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
drop_line <= HEIGHT_DROP_MASK;
else if (width_counter == (WIDTH_IN - 1))
drop_line <= {drop_line[2:0], drop_line[3]};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (drop | ~valid | transfer_data);
// Internal Assignments
assign drop = drop_pixel[0] | drop_line[0];
assign capture_inputs = stream_in_ready & ~drop;
assign transfer_data = ~stream_out_valid & stream_in_valid & ~drop;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; string to_string(string s) { return + s + ; } string to_string(char s) { return string(1, s); } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A> string to_string(A); template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool f = 1; string r = { ; for (const auto& x : v) { if (!f) r += , ; f = 0; r += to_string(x); } return r + } ; } void debug_out() { cout << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cout << << to_string(H); debug_out(T...); } int main() { ios::sync_with_stdio(0); cin.tie(0); int v; cin >> v; while (v--) { int n = 250; vector<int> a(n); double m = 0; for (auto i = (0); i <= (n - 1); ++i) cin >> a[i], m += a[i]; m /= n; double var = 0; for (auto i = (0); i <= (n - 1); ++i) var += (a[i] - m) * (a[i] - m); var /= n; if (abs(var - m) > abs(var - (m * m + m) / 3)) { int mx = *max_element((a).begin(), (a).end()); cout << mx / 2 << n ; } else { cout << (int)round(m) << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int a[111][111]; char c[111]; int main() { int i, j, k; int p, q, r; int t, tt, ttt; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %s , c); for (j = 1; j <= n; j++) { if (c[j - 1] == E ) a[i][j] = 1; else a[i][j] = 0; } } for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (a[i][j] == 0) break; } if (j == n + 1) break; } if (i != n + 1) { for (j = 1; j <= n; j++) { for (i = 1; i <= n; i++) { if (a[i][j] == 0) break; } if (i == n + 1) break; } if (j != n + 1) { printf( -1 ); } else { for (j = 1; j <= n; j++) { for (i = 1; i <= n; i++) { if (a[i][j] == 0) { printf( %d %d n , i, j); break; } } } } } else { for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (a[i][j] == 0) { printf( %d %d n , i, j); break; } } } } scanf( ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira Rojas
//
// Create Date: 08/31/2016 04:06:16 PM
// Design Name: Recursive Parameterized KOA
// Module Name: RecursiveKOA
// Project Name: FPU
// Target Devices: Artix 7
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RecursiveKOA
//#(parameter SW = 24,
#(parameter SW = 56,
parameter Opt_FPGA_ASIC=0) //Se está optimizando el modulo para FPGA o para un ASIC
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//genvar precision = 1;
////////////////////WIRE DECLARATIONS
wire [2*SW-1:0] Result;
///////////////////////////INSTANCIATIONS//////////////////
/////////////////////FIRST KOA MULTIPLIER//////////////////
generate
if (Opt_FPGA_ASIC) begin //Opt_FPGA_ASIC=0 Optimizations for ASIC
KOA_FPGA #(.SW(SW)/*,.level(level1)*/) main_KOA(
.Data_A_i(Data_A_i[SW-1:0]/*P=SW*/),
.Data_B_i(Data_B_i[SW-1:0]/*P=SW*/),
.sgf_result_o(Result[2*SW-1:0]) /*P=SW*/
);
end else begin //Opt_FPGA_ASIC=1 Optimizations for FPGA
KOA_c #(.SW(SW), .precision(1)/*,.level(level1)*/) main_KOA(
.Data_A_i(Data_A_i[SW-1:0]/*P=SW*/),
.Data_B_i(Data_B_i[SW-1:0]/*P=SW*/),
.sgf_result_o(Result[2*SW-1:0]) /*P=SW*/
);
// KOA_c_2 #(.SW(SW), .precision(0)/*,.level(level1)*/) main_KOA(
// .Data_A_i(Data_A_i[SW-1:0]/*P=SW*/),
// .Data_B_i(Data_B_i[SW-1:0]/*P=SW*/),
// .sgf_result_o(Result[2*SW-1:0]) /*P=SW*/
// );
end
endgenerate
//////////////////////Following REG///////////////////
RegisterAdd #(.W(2*SW)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]/*P=2*SW*/),
.Q({sgf_result_o[2*SW-1:0]})
);
///////////////////////END OF CODE////////////////////
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, q, x, y, xx, yy; long long read() { long long x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x; } struct BIT { long long c[1005][1005]; long long ask(int x, int y) { long long ans = 0; for (; x; x -= x & -x) for (int i = y; i; i -= i & -i) ans ^= c[x][i]; return ans; } void modify(int x, int y, long long v) { for (; x <= (n + 1); x += x & -x) for (int i = y; i <= (n + 1); i += i & -i) c[x][i] ^= v; } } t[2][2]; long long v; int main() { n = read(); q = read(); while (q--) { int op = read(); x = read(); y = read(); xx = read(); yy = read(); if (op == 2) { v = read(); t[x & 1][y & 1].modify((x + 1) >> 1, (y + 1) >> 1, v); t[x & 1][(yy + 1) & 1].modify((x + 1) >> 1, (yy + 2) >> 1, v); t[(xx + 1) & 1][y & 1].modify((xx + 2) >> 1, (y + 1) >> 1, v); t[(xx + 1) & 1][(yy + 1) & 1].modify((xx + 2) >> 1, (yy + 2) >> 1, v); } else { long long v1 = t[(x - 1) & 1][(y - 1) & 1].ask(x >> 1, y >> 1); long long v2 = t[(x - 1) & 1][yy & 1].ask(x >> 1, (yy + 1) >> 1); long long v3 = t[xx & 1][(y - 1) & 1].ask((xx + 1) >> 1, y >> 1); long long v4 = t[xx & 1][yy & 1].ask((xx + 1) >> 1, (yy + 1) >> 1); printf( %lld n , v1 ^ v2 ^ v3 ^ v4); } } return 0; } |
module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
wire RW = CNTRL_bus_in[4];
wire [SA_WIDTH-1:0] DA = CNTRL_bus_in[19:17];
wire [SA_WIDTH-1:0] AA = CNTRL_bus_in[16:14];
wire [SA_WIDTH-1:0] BA = CNTRL_bus_in[13:11];
reg [WORD_WIDTH-1:0] SYNC_RAM0 [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] SYNC_RAM1 [2**DR_WIDTH-1:0];
reg [DR_WIDTH-1:0] i;
always@(posedge CLK) begin
/*
if (RST)
for (i=3'b0;i<2**DR_WIDTH-3'b1;i = i + 3'b1) begin
SYNC_RAM1[i] <= 0;
SYNC_RAM0[i] <= 0;
end
else if (RW) begin
*/
if(RW) begin
SYNC_RAM0[DA] <= D_bus_in;
SYNC_RAM1[DA] <= D_bus_in;
end
end
always@(*) begin
ADDR_bus_out <= SYNC_RAM0[AA];
B_data_out <= SYNC_RAM1[BA];
end
endmodule |
// Issue 559 - nested ifdef with generate indentation bug
module m;
`ifndef DDR_PT_GATE_SIM
generate
/***************** Assertions for DP HM signals ***************************************************************/
for (dp_id=0; dp_id <PDDR_NUM_DP; dp_id++) begin: DPConnectGen
if (PDDR_DP_HV[dp_id]) begin: VGen
`ifdef IO_DDR3
// CR?V connectivity for DP HM
DP_CRN0V15_Connection: assert property (ConnectProp(1'b1, `PHYTOP.CRN0V[dp_id+PGEN_NUM_ADR], `PHYTOP.DPBundleGen[dp_id].u_DpBundle.`DPV_INST.CRN0V15))
else begin
$display ($stime, " ERROR: CRN0V[%0d] to DP HM %0d CRN0V15 Connection Failed", dp_id+PGEN_NUM_ADR, dp_id);
postError();
end // else: !assert property
DP_CRN1V15_Connection: assert property (ConnectProp(1'b1, `PHYTOP.CRN1V[dp_id+PGEN_NUM_ADR], `PHYTOP.DPBundleGen[dp_id].u_DpBundle.`DPV_INST.CRN1V15))
else begin
$display ($stime, " ERROR: CRN1V[%0d] to DP HM %0d CRN1V15 Connection Failed", dp_id+PGEN_NUM_ADR, dp_id);
postError();
end // else: !assert property
end // block: VGen
`endif // `ifdef IO_DDR3
end // block: DPConnectGen
endgenerate
`endif
endmodule // m
|
`include "define.v"
`include "constants.vh"
module top
(
input CLK_P,
input CLK_N,
input RST_X_IN,
output TXD,
input RXD,
output reg [7:0] LED
);
//Active Low SW
wire clk;
wire reset_x;
wire [`ADDR_LEN-1:0] pc;
wire [4*`INSN_LEN-1:0] idata;
wire [8:0] imem_addr;
wire [`DATA_LEN-1:0] dmem_data;
wire [`DATA_LEN-1:0] dmem_wdata;
wire [`ADDR_LEN-1:0] dmem_addr;
wire dmem_we;
wire [`DATA_LEN-1:0] dmem_wdata_core;
wire [`ADDR_LEN-1:0] dmem_addr_core;
wire dmem_we_core;
wire utx_we;
wire finish_we;
reg finished;
wire ready_tx;
wire loaded;
reg prog_loading;
wire [4*`INSN_LEN-1:0] prog_loaddata;
wire [`ADDR_LEN-1:0] prog_loadaddr;
wire prog_dmem_we;
wire prog_imem_we;
assign utx_we = (~finished && dmem_we_core && (dmem_addr_core == 32'h0)) ? 1'b1 : 1'b0;
assign finish_we = (dmem_we_core && (dmem_addr_core == 32'h8)) ? 1'b1 : 1'b0;
always @ (posedge clk) begin
if (!reset_x) begin
LED <= 0;
end else if (utx_we) begin
LED <= {LED[7], dmem_wdata[6:0]};
end else if (finish_we) begin
LED <= {1'b1, LED[6:0]};
end
end
always @ (posedge clk) begin
if (!reset_x) begin
prog_loading <= 1'b1;
end else begin
prog_loading <= ~loaded;
end
end
always @ (posedge clk) begin
if (!reset_x) begin
finished <= 0;
end else if (finish_we) begin
finished <= 1;
end
end
GEN_MMCM_DS genmmcmds
(
.CLK_P(CLK_P),
.CLK_N(CLK_N),
.RST_X_I(~RST_X_IN),
.CLK_O(clk),
.RST_X_O(reset_x)
);
pipeline pipe
(
.clk(clk),
.reset(~reset_x | prog_loading),
.pc(pc),
.idata(idata),
.dmem_wdata(dmem_wdata_core),
.dmem_addr(dmem_addr_core),
.dmem_we(dmem_we_core),
.dmem_data(dmem_data)
);
assign dmem_addr = prog_loading ? prog_loadaddr : dmem_addr_core;
assign dmem_we = prog_loading ? prog_dmem_we : dmem_we_core;
assign dmem_wdata = prog_loading ? prog_loaddata[127:96] : dmem_wdata_core;
dmem datamemory(
.clk(clk),
.addr({2'b0, dmem_addr[`ADDR_LEN-1:2]}),
.wdata(dmem_wdata),
.we(dmem_we),
.rdata(dmem_data)
);
assign imem_addr = prog_loading ? prog_loadaddr[12:4] : pc[12:4];
imem_ld instmemory(
.clk(~clk),
.addr(imem_addr),
.rdata(idata),
.wdata(prog_loaddata),
.we(prog_imem_we)
);
SingleUartTx sutx
(
.CLK(clk),
.RST_X(reset_x),
.TXD(TXD),
.ERR(),
.DT01(dmem_wdata[7:0]),
.WE01(utx_we)
);
PLOADER loader
(
.CLK(clk),
.RST_X(reset_x),
.RXD(RXD),
.ADDR(prog_loadaddr),
.DATA(prog_loaddata),
.WE_32(prog_dmem_we),
.WE_128(prog_imem_we),
.DONE(loaded)
);
endmodule // top
|
#include <bits/stdc++.h> using namespace std; template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(long long &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const long long &x) { printf( %lld , x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.first); putchar( ); _W(x.second); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } int MOD = 1e9 + 7; void ADD(long long &x, long long v) { x = (x + v) % MOD; if (x < 0) x += MOD; } const int SIZE = 1e6 + 10; const int AA = 1000; int dp[2001]; int main() { long long target_W; R(target_W); long long sum = 0; long long cnt[9], cnt2[9] = {}; for (int i = (1); i <= (8); ++i) { R(cnt[i]); sum += cnt[i] * i; } if (sum <= target_W) W(sum); else { long long now = 0; for (int i = (1); i <= (8); ++i) { if (now + i * cnt[i] <= target_W) { now += i * cnt[i]; cnt2[i] = cnt[i]; cnt[i] = 0; } else { long long v = (target_W - now) / i; now += i * v; cnt[i] -= v; cnt2[i] += v; } } dp[(0) + AA] = 1; for (int v = (1); v <= (8); ++v) { for (int j = 0; j < (min(100LL, cnt[v])); ++j) { for (int k = 900; k >= -900; k--) { if (dp[(k) + AA]) dp[(k + v) + AA] = 1; } } for (int j = 0; j < (min(100LL, cnt2[v])); ++j) { for (int k = -900; k <= 900; k++) { if (dp[(k) + AA]) dp[(k - v) + AA] = 1; } } } long long an = 0; for (int i = (0); i <= (target_W - now); ++i) { if (dp[(i) + AA]) an = now + i; } W(an); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; char s[100005]; int day[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; map<string, int> my; void check(char* s) { if (((s[0]) >= 0 && (s[0]) <= 9 ) && ((s[1]) >= 0 && (s[1]) <= 9 ) && ((s[3]) >= 0 && (s[3]) <= 9 ) && ((s[4]) >= 0 && (s[4]) <= 9 ) && ((s[6]) >= 0 && (s[6]) <= 9 ) && ((s[7]) >= 0 && (s[7]) <= 9 ) && ((s[8]) >= 0 && (s[8]) <= 9 ) && ((s[9]) >= 0 && (s[9]) <= 9 ) && s[2] == - && s[5] == - ) { int d = atoi(s); int m = atoi(s + 3); int y = atoi(string(s + 6, s + 10).c_str()); if (m <= 12 && d > 0 && d <= day[m - 1] && y >= 2013 && y <= 2015) { ++my[string(s, s + 10)]; } } } int main() { gets(s); int n = strlen(s); for (int i = 0; i + 10 <= n; ++i) check(s + i); string res( ); int max = -1; for (typeof((my).begin()) it = (my).begin(), _e = (my).end(); it != _e; ++it) if (it->second > max) { max = it->second; res = it->first; } cout << res << endl; return 0; } |
#include <bits/stdc++.h> int main() { int a; while (scanf( %d , &a) != EOF) printf( %d %d %d n , 0, 0, a); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string q[41]; long long n, p, i, count = 1, check = 1; cin >> n >> p; for (i = 0; i < n; i++) cin >> q[i]; for (i = n - 2; i >= 0; i--) { if (q[i] == halfplus ) { count = count * 2 + 1; check++; } else count = count * 2; } cout << p * count - (p / 2) * check << endl; return 0; } |
// Listing 14.7
module textMenu_graph
(
input wire clk, reset,
input wire [2:0] item_selector,
input wire [9:0] pix_x, pix_y,
output wire graph_on,
output reg [2:0] graph_rgb
);
// costant and signal declaration
// x, y coordinates (0,0) to (639,479)
localparam MAX_X = 640;
localparam MAX_Y = 480;
//Top menu sections
localparam item1 = 4'd1;
localparam item2 = 4'd2;
localparam item3 = 4'd3;
localparam item4 = 4'd4;
localparam item5 = 4'd5;
localparam item6 = 4'd6;
//Top menu vertical limits
localparam topMenu_y_limit_top = 0;
localparam topMenu_y_limit_bottom = 80;
//Top menu horizontal limits
localparam topMenu_x_limit_left=0;
localparam topMenu_x_limit_right=640;
//Top menu items sections horizontal each region
localparam topMenu_x_open_limit_left=10;
localparam topMenu_x_open_limit_right=topMenu_x_open_limit_left+60;
localparam topMenu_x_save_limit_left=topMenu_x_open_limit_right+10;
localparam topMenu_x_save_limit_right=topMenu_x_save_limit_left+60;
localparam topMenu_x_exit_limit_left=topMenu_x_save_limit_right+10;
localparam topMenu_x_exit_limit_right=topMenu_x_exit_limit_left+60;
localparam topMenu_x_center_width=topMenu_x_exit_limit_right+210;
localparam topMenu_x_caps_limit_left=topMenu_x_center_width+10;
localparam topMenu_x_caps_limit_right=topMenu_x_caps_limit_left+60;
localparam topMenu_x_color_limit_left=topMenu_x_caps_limit_right+10;
localparam topMenu_x_color_limit_right=topMenu_x_color_limit_left+60;
localparam topMenu_x_size_limit_left=topMenu_x_color_limit_right+10;
localparam topMenu_x_size_limit_right=topMenu_x_size_limit_left+60;
//Top menu items vertical limits
localparam topMenu_y_item_top_limit=topMenu_y_limit_top+17;
localparam topMenu_y_item_bottom_limit=topMenu_y_item_top_limit+45;
wire menu_mostrar_separador;
wire menu_mostrar;
assign menu_mostrar_separador = (topMenu_x_limit_left<=pix_x) && (pix_x <= topMenu_x_limit_right) &&
(topMenu_y_limit_bottom-2<=pix_y) && (pix_y <= topMenu_y_limit_bottom);
//
reg[5:0] show_item_selector;
reg [2:0] currentItem;
always @ (*) begin
currentItem= item_selector;
case(currentItem)
item1: begin
show_item_selector[0] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_open_limit_left<=pix_x) && (pix_x <= topMenu_x_open_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_open_limit_right-1<=pix_x) && (pix_x <= topMenu_x_open_limit_right));
end
item2: begin
show_item_selector[1] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_save_limit_left<=pix_x) && (pix_x <= topMenu_x_save_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_save_limit_right-1<=pix_x) && (pix_x <= topMenu_x_save_limit_right));
end
item3: begin
show_item_selector[2] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_exit_limit_left<=pix_x) && (pix_x <= topMenu_x_exit_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_exit_limit_right-1<=pix_x) && (pix_x <= topMenu_x_exit_limit_right));
end
item4: begin
show_item_selector[3] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_caps_limit_left<=pix_x) && (pix_x <= topMenu_x_caps_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_caps_limit_right-1<=pix_x) && (pix_x <= topMenu_x_caps_limit_right));
end
item5: begin
show_item_selector[4] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_color_limit_left<=pix_x) && (pix_x <= topMenu_x_color_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_color_limit_right-1<=pix_x) && (pix_x <= topMenu_x_color_limit_right));
end
item6: begin
show_item_selector[5] = ((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_top_limit+1) &&
(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
((topMenu_y_item_bottom_limit-1<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_right)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_size_limit_left<=pix_x) && (pix_x <= topMenu_x_size_limit_left+1)) ||
((topMenu_y_item_top_limit<=pix_y) && (pix_y <= topMenu_y_item_bottom_limit) &&
(topMenu_x_size_limit_right-1<=pix_x) && (pix_x <= topMenu_x_size_limit_right));
end
default: begin
show_item_selector= 3'b000;
end
endcase
end
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @* begin
if (menu_mostrar_separador)
graph_rgb = 3'b000;
else if (show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
show_item_selector[3] || show_item_selector[4] || show_item_selector[5])
graph_rgb = 3'b100;
end
assign graph_on=show_item_selector[0] || show_item_selector[1] || show_item_selector[2] ||
show_item_selector[3] || show_item_selector[4] || show_item_selector[5] || menu_mostrar_separador;
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cout << x; } void __print(long x) { cout << x; } void __print(long long x) { cout << x; } void __print(unsigned x) { cout << x; } void __print(unsigned long x) { cout << x; } void __print(unsigned long long x) { cout << x; } void __print(float x) { cout << x; } void __print(double x) { cout << x; } void __print(long double x) { cout << x; } void __print(char x) { cout << << x << ; } void __print(const char *x) { cout << << x << ; } void __print(const string &x) { cout << << x << ; } void __print(bool x) { cout << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { __print(x.first); cout << , ; __print(x.second); } template <typename T> void __print(const T &x) { int f = 0; for (auto &i : x) cout << (f++ ? , : ), __print(i); } void _print() { cout << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cout << , ; _print(v...); } const int N = 2e5 + 7; const int MOD = 1e9 + 7; long long fastpow(long long b, long long p) { long long temp; if (p == 0) return 1; if (p == 1) return b; temp = fastpow(b, p / 2); temp = temp * temp % MOD; if (p & 1) { temp = temp * b % MOD; } return temp; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, k; cin >> n >> k; string s; cin >> s; vector<char> v(k); for (int i = 0; i < k; i++) cin >> v[i]; vector<int> temp(n); for (int i = 0; i < n; i++) { if (count(v.begin(), v.end(), s[i])) temp[i] = 1; else temp[i] = 0; } long long ans = 0; for (int i = 0; i < n; i++) { if (temp[i] == 1) { long long j = i; while (j < n && temp[j] == 1) j++; ans += ((j - i) * (j - i + 1)) / 2; i = j; } } cout << ans; return 0; } |
// issue 1698
module sub_mod
(
input [8+4-1:0][7:0] add_left,
input [8-4-1:0][7:0] substract_left,
input [8*4-1:0][7:0] multiply_left,
input [8/4-1:0][7:0] divide_left
input [7:0][8+4-1:0] add_right,
input [7:0][8-4-1:0] substract_right,
input [7:0][8*4-1:0] multiply_right,
input [7:0][8/4-1:0] divide_right,
);
endmodule : sub_mod
module top_mod
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [8+4-1:0] [7:0] add_left, // To sub_mod_i of sub_mod.v
input [7:0] [11:0] add_right, // To sub_mod_i of sub_mod.v
input [8/4-1:0] [7:0] divide_left, // To sub_mod_i of sub_mod.v
input [7:0] [1:0] divide_right, // To sub_mod_i of sub_mod.v
input [8*4-1:0] [7:0] multiply_left, // To sub_mod_i of sub_mod.v
input [7:0] [31:0] multiply_right, // To sub_mod_i of sub_mod.v
input [8-4-1:0] [7:0] substract_left, // To sub_mod_i of sub_mod.v
input [7:0] [3:0] substract_right // To sub_mod_i of sub_mod.v
// End of automatics
);
sub_mod sub_mod_i
(/*AUTOINST*/
// Inputs
.add_left (add_left/*[8+4-1:0][7:0]*/),
.substract_left (substract_left/*[8-4-1:0][7:0]*/),
.multiply_left (multiply_left/*[8*4-1:0][7:0]*/),
.divide_left (divide_left/*[8/4-1:0][7:0]*/),
.add_right (add_right/*[7:0][8+4-1:0]*/),
.substract_right (substract_right/*[7:0][8-4-1:0]*/),
.multiply_right (multiply_right/*[7:0][8*4-1:0]*/),
.divide_right (divide_right/*[7:0][8/4-1:0]*/));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { srand(time(NULL)); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.setf(ios::fixed); cout.precision(0); long long n; cin >> n; string s; char y = a ; while (n != 0) { s.push_back(y); int t = 1; while (t <= n) { s.push_back(y); n -= t; t++; } y++; } if (s.size() == 0) s.push_back( a ); cout << s; } |
// Note: when __ICARUS_UNSIZED__ is not defined, this test assumes integers
// are 32 bits wide.
module main();
reg [34:0] my_reg;
reg error;
reg [34:0] ref_val;
reg [34:0] ref_val2;
reg [7:0] count;
initial
begin
error = 0;
// Create reference value that is bigger than 32 bits...
ref_val = 0;
ref_val[0] = 1;
ref_val[34] = 1;
$display("*:%d", ref_val);
ref_val2 = 35'h7fffffffff;
$display("*:%d", ref_val2);
// Trivial test to see that small unsized integers still work.
my_reg = 100;
if (my_reg != 'h64)
begin
error = 1;
$display("Error: expected 100");
end
my_reg = 17179869185;
$display("1:%d", my_reg);
`ifdef __ICARUS_UNSIZED__
// Ordinary compilers will truncate unsized integer
// constants to 32bits. Icarus Verilog is more generous.
if (my_reg !== 35'h4_00000001) begin
error = 1;
$display("Error: expected 17179869185");
end
`else
// Unsized integers bigger than 32 bits are truncated...
// Value below has bit 34 and bit 0 set to '1'
if (my_reg != 1)
begin
error = 1;
$display("Error: expected 1");
end
`endif
// Another unsized integer, but this time 'd specifier...
my_reg = 'd17179869184;
$display("2:%d", my_reg);
`ifdef __ICARUS_UNSIZED__
// Ordinary compilers will truncate unsized integer
// constants to 32bits. Icarus Verilog is more generous.
if (my_reg !== 35'h4_00000000) begin
error = 1;
$display("Error: expected 17179869184");
end
`else
if (my_reg != 0)
begin
error = 1;
$display("Error: expected 1");
end
`endif
// This should finally work!
my_reg = 35'sd17179869185;
$display("3:%d", my_reg);
if (my_reg != ref_val)
begin
error = 1;
$display("Error: expected 17179869185");
end
// This should work too.
my_reg = 35'd 17179869185;
$display("4:%d", my_reg);
if (my_reg != ref_val)
begin
error = 1;
$display("Error: expected 17179869185");
end
// Overflow...
my_reg = 35'd 34359738369;
$display("5:%d", my_reg);
if (my_reg != 1)
begin
error = 1;
$display("Error: expected 1");
end
// Just no overflow
my_reg = 35'd 34359738367;
$display("6:%d", my_reg);
if (my_reg != ref_val2)
begin
error = 1;
$display("Error: expected 34359738367");
end
`ifdef __ICARUS_UNSIZED__
// Since Icarus Verilog doesn't truncate constant values,
// the whole idea of truncating then sign-extending the result
// to go into the wide reg does not apply. So skip this
// test.
`else
// Unsized integers bigger than 32 bits are truncated...
// Here all the bits are set. Since there is no 'd prefix,
// it will be sign extended later on.
my_reg = 17179869183;
$display("7:%d", my_reg);
if (my_reg != ref_val2)
begin
error = 1;
$display("Error: expected 34359738367");
end
`endif
// Unsized integers bigger than 32 bits are truncated...
// Here all the bits are set. Since there *IS* a 'd prefix
// it will NOT be sign extended later on.
my_reg = 'd17179869183;
$display("8:%d", my_reg);
`ifdef __ICARUS_UNSIZED__
if (my_reg != 'd17179869183)
begin
error = 1;
$display("Error: expected 'd17179869183");
end
`else
if (my_reg != 'd4294967295)
begin
error = 1;
$display("Error: expected ");
end
`endif
if (error==1)
begin
$display("FAILED");
end
else
begin
$display("PASSED");
end
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:37:07 10/25/2015
// Design Name:
// Module Name: display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HexTo8SEG(input [31:0] Hexs, //¶Ë¿Ú±äÁ¿ËµÃ÷Ó붨ÒåºÏ²¢
// input [2:0] Scan,
input [7:0] points,
input [7:0] LES,
input flash,
output[63:0] SEG_TXT
);
Hex2Seg HTS0(Hexs[31:28],LES[7],points[7],flash,SEG_TXT[7:0]);
Hex2Seg HTS1(Hexs[27:24],LES[6],points[6],flash,SEG_TXT[15:8]);
Hex2Seg HTS2(Hexs[23:20],LES[5],points[5],flash,SEG_TXT[23:16]);
Hex2Seg HTS3(Hexs[19:16],LES[4],points[4],flash,SEG_TXT[31:24]);
Hex2Seg HTS4(Hexs[15:12],LES[3],points[3],flash,SEG_TXT[39:32]);
Hex2Seg HTS5(Hexs[11:8], LES[2],points[2],flash,SEG_TXT[47:40]);
Hex2Seg HTS6(Hexs[7:4], LES[1],points[1],flash,SEG_TXT[55:48]);
Hex2Seg HTS7(Hexs[3:0], LES[0],points[0],flash,SEG_TXT[63:56]);
endmodule
module Hex2Seg(input[3:0]Hex,
input LE,
input point,
input flash,
output[7:0]Segment
);
wire en = LE & flash;
MC14495_ZJU MSEG(.D3(Hex[3]),.D2(Hex[2]),.D1(Hex[1]),.D0(Hex[0]),.LE(en),.point(point),
.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.p(p));
assign Segment = {a,b,c,d,e,f,g,p}; //p,g,f,e,d,c,b,a
endmodule
/* always @* begin //Ðźű仯´¥·¢ (×éºÏµç·²»ÓÃʱÖÓ´¥·¢)
case (Scan) //ͬ²½Êä³ö
3'b000: begin Hexo = Hexs[31:28]; SEG_TXT[7:0] = Segment;
point <= points[7]; LE <= LES[7]; end //ͬ²½Êä³ö
3'b001: begin Hexo = Hexs[27:24]; SEG_TXT[15:8] = Segment;
point <= points[6]; LE <= LES[6]; end //ͬ²½Êä³ö
3'b010: begin Hexo = Hexs[23:20]; SEG_TXT[23:16] = Segment;
point <= points[5]; LE <= LES[5]; end //ͬ²½Êä³ö
3'b011: begin Hexo = Hexs[19:16]; SEG_TXT[31:24] = Segment;
point <= points[4]; LE <= LES[4]; end //ͬ²½Êä³ö
3'b100: begin Hexo = Hexs[15:12]; SEG_TXT[39:32] = Segment;
point <= points[3]; LE <= LES[3]; end //ͬ²½Êä³ö
3'b101: begin Hexo = Hexs[11:8]; SEG_TXT[47:40] = Segment;
point <= points[2]; LE <= LES[2]; end //ͬ²½Êä³ö
3'b110: begin Hexo = Hexs[7:4]; SEG_TXT[55:48] = Segment;
point <= points[1]; LE <= LES[1]; end //ͬ²½Êä³ö
3'b111: begin Hexo = Hexs[3:0]; SEG_TXT[63:56] = Segment;
point <= points[0]; LE <= LES[0]; end //ͬ²½Êä³ö
endcase
end
*/
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000001; const int MAXN = 251; struct Person { int cnt, last; int id; Person(int id = -1) : id(id) { cnt = 0; last = 0; } bool operator<(const Person& p) const { if (cnt != p.cnt) return cnt > p.cnt; return last < p.last; } }; int n, k, m, a; vector<Person> score; vector<int> res; bool can_win(int id) { vector<Person> tmp(score); if (m - a > 0) { tmp[id].cnt += m - a; tmp[id].last = m - 1; } if (tmp[id].cnt == 0) return false; sort(tmp.begin(), tmp.end()); for (int i = 0; i < k; i++) if (tmp[i].id == score[id].id) return true; return false; } bool can_lose(int id) { if (score[id].cnt == 0) return true; int ptop = a; int better = id; for (int j = id + 1; j < n; j++) { Person cur(score[j]); while (ptop < m && score[id] < cur) { cur.cnt++; cur.last = ptop++; } if (cur < score[id]) better++; } return better >= k; } int main() { scanf( %d%d%d%d , &n, &k, &m, &a); score.resize(n); res.resize(n); for (int i = 0; i < n; i++) score[i].id = i; for (int i = 0; i < a; i++) { int id; scanf( %d , &id); id--; score[id].cnt++; score[id].last = i; } sort(score.begin(), score.end()); for (int i = 0; i < n; i++) { int val = 0; bool w = can_win(i); bool l = can_lose(i); if (w && l) val = 2; else if (w && !l) val = 1; else if (!w && l) val = 3; else throw; res[score[i].id] = val; } for (int i = 0; i < n; i++) printf( %d , res[i]); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); map<long long, long long> mp; deque<long long> a; long long n, k, d, m = 0; cin >> n >> k; for (auto i = 0; i < n; i++) { cin >> d; if (!mp[d]) { mp[d] = 1; a.push_front(d); if (a.size() > k) { mp[a.back()] = 0; a.pop_back(); } } } cout << a.size() << n ; for (const auto val : a) cout << val << ; return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'pipeline' primitive
//
//===----------------------------------------------------------------------===//
module acl_pipeline (
clock,
resetn,
data_in,
valid_out,
stall_in,
stall_out,
valid_in,
data_out,
initeration_in,
initeration_stall_out,
initeration_valid_in,
not_exitcond_in,
not_exitcond_stall_out,
not_exitcond_valid_in,
pipeline_valid_out,
pipeline_stall_in,
exiting_valid_out
);
parameter FIFO_DEPTH = 1;
parameter string STYLE = "SPECULATIVE"; // "NON_SPECULATIVE"/"SPECULATIVE"
input clock, resetn, stall_in, valid_in, initeration_valid_in, not_exitcond_valid_in, pipeline_stall_in;
output stall_out, valid_out, initeration_stall_out, not_exitcond_stall_out, pipeline_valid_out;
input data_in, initeration_in, not_exitcond_in;
output data_out;
output exiting_valid_out;
generate
// Instantiate 2 pops and 1 push
if (STYLE == "SPECULATIVE")
begin
wire valid_pop1, valid_pop2;
wire stall_push, stall_pop2;
wire data_pop2, data_push;
acl_pop pop1(
.clock(clock),
.resetn(resetn),
.dir(data_in),
.predicate(1'b0),
.data_in(1'b1),
.valid_out(valid_pop1),
.stall_in(stall_pop2),
.stall_out(stall_out),
.valid_in(valid_in),
.data_out(data_pop2),
.feedback_in(initeration_in),
.feedback_valid_in(initeration_valid_in),
.feedback_stall_out(initeration_stall_out)
);
defparam pop1.DATA_WIDTH = 1;
acl_pop pop2(
.clock(clock),
.resetn(resetn),
.dir(data_pop2),
.predicate(1'b0),
.data_in(1'b0),
.valid_out(valid_pop2),
.stall_in(stall_push),
.stall_out(stall_pop2),
.valid_in(valid_pop1),
.data_out(data_push),
.feedback_in(~not_exitcond_in),
.feedback_valid_in(not_exitcond_valid_in),
.feedback_stall_out(not_exitcond_stall_out)
);
defparam pop2.DATA_WIDTH = 1;
wire p_out, p_valid_out, p_stall_in;
acl_push push(
.clock(clock),
.resetn(resetn),
.dir(1'b1),
.predicate(1'b0),
.data_in(~data_push),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_push),
.valid_in(valid_pop2),
.data_out(data_out),
.feedback_out(p_out),
.feedback_valid_out(p_valid_out),
.feedback_stall_in(p_stall_in)
);
// signal when to spawn a new iteration
assign pipeline_valid_out = p_out & p_valid_out;
assign p_stall_in = pipeline_stall_in;
// signal when the last iteration is exiting
assign exiting_valid_out = ~p_out & p_valid_out & ~pipeline_stall_in;
defparam push.DATA_WIDTH = 1;
defparam push.FIFO_DEPTH = FIFO_DEPTH;
end
// Instantiate 1 pop and 1 push
else
begin
//////////////////////////////////////////////////////
// If there is no speculation, directly connect
// exit condition to valid
wire valid_pop2;
wire stall_push;
wire data_push;
wire p_out, p_valid_out, p_stall_in;
assign p_out = not_exitcond_in;
assign p_valid_out = not_exitcond_valid_in ;
assign not_exitcond_stall_out = p_stall_in;
acl_staging_reg asr(
.clk(clock), .reset(~resetn),
.i_valid( valid_in ), .o_stall(stall_out),
.o_valid( valid_out), .i_stall(stall_in)
);
// signal when to spawn a new iteration
assign pipeline_valid_out = p_out & p_valid_out;
assign p_stall_in = pipeline_stall_in;
// signal when the last iteration is exiting
assign exiting_valid_out = ~p_out & p_valid_out & ~pipeline_stall_in;
assign initeration_stall_out = 1'b0; // never stall
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, ans, spe, a[100100], b[100100], c[100100], fa[100100 << 1]; char str[2]; map<pair<long long, long long>, bool> mm; long long ff(long long u) { return u == fa[u] ? u : fa[u] = ff(fa[u]); } inline long long po(long long u, long long v) { long long res = 1; for (; v;) { if (v & 1) res = res * u % 1000000007; u = u * u % 1000000007; v >>= 1; } return res; } inline void GG() { puts( 0 ); exit(0); } inline pair<long long, long long> zh(long long p, long long q) { if (p > q) swap(p, q); if (p + q > n + 1) swap(p, q), p = n - p + 1, q = n - q + 1; return make_pair(p, q); } int main() { long long i, j, k, p, q; cin >> n >> m; if (n == 10007 || m == 98765) spe = 1; for (i = 1; i <= m; i++) { scanf( %lld%lld%s , &p, &q, str); if (i == 1 && p != 8145) spe = 0; a[i] = zh(p, q).first; b[i] = zh(p, q).second; c[i] = (str[0] == x ? 0 : 1); if (mm.count(make_pair(a[i], b[i]))) if (mm[make_pair(a[i], b[i])] != c[i]) GG(); else mm[make_pair(a[i], b[i])] = c[i]; } for (i = 0; i <= n * 2 + 1; i++) fa[i] = i; for (i = 1; i <= m; i++) { p = b[i] - a[i] - 1, q = a[i] + b[i] - 1; if (c[i]) { if (p < 1) fa[ff(q)] = ff(n * 2 + 1), fa[ff(q + n)] = ff(0); else fa[ff(p)] = ff(q + n), fa[ff(p + n)] = ff(q); } else { if (p < 1) fa[ff(q)] = ff(0), fa[ff(q + n)] = ff(n * 2 + 1); else fa[ff(p)] = ff(q), fa[ff(p + n)] = ff(q + n); } } for (i = 1; i <= n; i++) if (ff(i) == ff(i + n)) GG(); if (ff(0) == ff(n * 2 + 1)) GG(); for (i = 0; i <= n * 2 + 1; i++) if (i == fa[i]) ans++; cout << po(2, (ans - 1) / 2); } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cout << x; } void __print(long x) { cout << x; } void __print(long long x) { cout << x; } void __print(unsigned x) { cout << x; } void __print(unsigned long x) { cout << x; } void __print(unsigned long long x) { cout << x; } void __print(float x) { cout << x; } void __print(double x) { cout << x; } void __print(long double x) { cerr << x; } void __print(char x) { cout << << x << ; } void __print(const char *x) { cout << << x << ; } void __print(const string &x) { cout << << x << ; } void __print(bool x) { cout << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cout << { ; __print(x.first); cout << , ; __print(x.second); cout << } ; } template <typename T> void __print(const T &x) { int f = 0; cout << { ; for (auto &i : x) cout << (f++ ? , : ), __print(i); cout << } ; } void _print() { cout << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cout << , ; _print(v...); } void c_p_c(); int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int testcase = 1; while (testcase--) c_p_c(); return 0; } void c_p_c() { long long int n, m; cin >> n >> m; vector<vector<long long int>> a(n, vector<long long int>(m, 0)); ; vector<vector<long long int>> b(n, vector<long long int>(m, 1)); ; for (long long int i = 0; i < n; ++i) { for (long long int j = 0; j < m; ++j) { cin >> a[i][j]; if (!a[i][j]) { for (long long int k = 0; k < n; ++k) { b[k][j] = 0; } for (long long int k = 0; k < m; ++k) { b[i][k] = 0; } } } } for (long long int i = 0; i < n; ++i) { for (long long int j = 0; j < m; ++j) { if (a[i][j]) { long long int ans = 0; for (long long int k = 0; k < n; ++k) { ans += b[k][j]; } for (long long int k = 0; k < m; ++k) { ans += b[i][k]; } if ((bool)(ans) == 0) { cout << NO ; return; } } } } cout << YES n ; for (long long int i = 0; i < n; ++i) { for (long long int j = 0; j < m; ++j) { cout << (bool)(b[i][j]) << ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int w, h; cin >> w >> h; char char1[100][100], char2[100][100]; string char3[200]; for (int i(0); i < h; ++i) cin >> char1[i]; for (int i(0); i < w; ++i) { for (int j(0); j < h; ++j) { char2[i][j] = char1[abs(j - h + 1)][i]; } } for (int i(0); i < w; ++i) { for (int j(0); j < h / 2; ++j) { char tmp = char2[i][j]; char2[i][j] = char2[i][abs(j - h + 1)]; char2[i][abs(j - h + 1)] = tmp; } } for (int i(0); i < 2 * w; i += 2) { for (int j(0); j < h; ++j) { char3[i].insert(char3[i].end(), char2[i / 2][j]); char3[i].insert(char3[i].end(), char2[i / 2][j]); } char3[i + 1] = char3[i]; } for (int i(0); i < 2 * w; ++i) cout << char3[i] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T = 1; cin >> T; while (T--) { string s; int x; cin >> s >> x; string ans; int n = s.size(); for (int i = 0; i < n; i++) ans.push_back( 1 ); for (int i = 0; i < n; i++) { if (s[i] == 0 ) { if (i - x >= 0) ans[i - x] = 0 ; if (i + x < n) ans[i + x] = 0 ; } } bool f = 1; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { bool t = 0; if (i + x < n && ans[i + x] == 1 ) t = 1; if (i - x >= 0 && ans[i - x] == 1 ) t = 1; if (!t) f = 0; } } if (f) cout << ans << endl; else cout << -1 n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int t; int n; struct node { long long id, val; bool flag; friend bool operator<(node a, node b) { if (a.val == b.val) return a.flag == false; return a.val > b.val; } }; int main() { while (~scanf( %d , &n)) { priority_queue<node> q; long long num; scanf( %lld , &num); node nxt; nxt.id = 1, nxt.val = num, nxt.flag = false; q.push(nxt); long long ans = 0; for (int i = 2; i <= n; ++i) { scanf( %lld , &num); nxt.flag = false; if (q.top().val < num) { node now = q.top(); q.pop(); ans = ans + num - now.val; if (now.flag) { now.flag = false; q.push(now); } nxt.flag = true; } nxt.id = i; nxt.val = num; q.push(nxt); } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 2e9; struct point { int x, y, id; point operator-(const point &a) const { point res; res.x = x - a.x; res.y = y - a.y; return res; } int operator*(const point &a) const { return x * a.y - y * a.x; } } p[100010], o; int dis(point x, point y) { return (x.x - y.x) * (x.x - y.x) + (x.y - y.y) * (x.y - y.y); } int qua(point x) { if (x.x > 0 && x.y >= 0) { return 1; } if (x.x <= 0 && x.y > 0) { return 2; } if (x.x < 0 && x.y <= 0) { return 3; } if (x.x >= 0 && x.y < 0) { return 4; } } bool cmp(point x, point y) { if (fabs(atan2(x.y, x.x) - atan2(y.y, y.x)) > 0.1) { return atan2(x.y, x.x) < atan2(y.y, y.x); } int tmp = (x - o) * (y - o); if (tmp == 0) { return dis(x, o) < dis(y, o); } else { return tmp > 0; } } point Div(point x, point y) { point res; res.x = x.x * y.x + x.y * y.y; res.y = x.y * y.x - x.x * y.y; return res; } int n, ans, ansa = 1, ansb = -inf; bool upd(int a, int b) { if (1LL * a * ansb < 1LL * ansa * b) { ansa = a; ansb = b; return true; } else { return false; } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d , &p[i].x, &p[i].y); p[i].id = i + 1; } sort(p, p + n, cmp); p[n] = p[0]; for (int i = 0; i < n; i++) { point x = Div(p[i], p[i + 1]); if (x.y < 0) { x.y = -x.y; } if (upd(x.y, x.x)) { ans = i; } } printf( %d %d n , p[ans].id, p[ans + 1].id); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module crypt_cycle_salt(
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [31:0] Ltmp [14:0];
wire [31:0] Rtmp [14:0];
wire [67:0] Ktmp [14:0];
crypt_shift_salt_1 crypt_shift_salt_instance1 (L, R, K, Ktmp[0], CLK, Ltmp[0], Rtmp[0]);
crypt_shift_salt_1 crypt_shift_salt_instance2 (Ltmp[0], Rtmp[0], Ktmp[0], Ktmp[1], CLK, Ltmp[1], Rtmp[1]);
crypt_shift_salt_2 crypt_shift_salt_instance3 (Ltmp[1], Rtmp[1], Ktmp[1], Ktmp[2], CLK, Ltmp[2], Rtmp[2]);
crypt_shift_salt_2 crypt_shift_salt_instance4 (Ltmp[2], Rtmp[2], Ktmp[2], Ktmp[3], CLK, Ltmp[3], Rtmp[3]);
crypt_shift_salt_2 crypt_shift_salt_instance5 (Ltmp[3], Rtmp[3], Ktmp[3], Ktmp[4], CLK, Ltmp[4], Rtmp[4]);
crypt_shift_salt_2 crypt_shift_salt_instance6 (Ltmp[4], Rtmp[4], Ktmp[4], Ktmp[5], CLK, Ltmp[5], Rtmp[5]);
crypt_shift_salt_2 crypt_shift_salt_instance7 (Ltmp[5], Rtmp[5], Ktmp[5], Ktmp[6], CLK, Ltmp[6], Rtmp[6]);
crypt_shift_salt_2 crypt_shift_salt_instance8 (Ltmp[6], Rtmp[6], Ktmp[6], Ktmp[7], CLK, Ltmp[7], Rtmp[7]);
crypt_shift_salt_1 crypt_shift_salt_instance9 (Ltmp[7], Rtmp[7], Ktmp[7], Ktmp[8], CLK, Ltmp[8], Rtmp[8]);
crypt_shift_salt_2 crypt_shift_salt_instance10(Ltmp[8], Rtmp[8], Ktmp[8], Ktmp[9], CLK, Ltmp[9], Rtmp[9]);
crypt_shift_salt_2 crypt_shift_salt_instance11(Ltmp[9], Rtmp[9], Ktmp[9], Ktmp[10], CLK, Ltmp[10], Rtmp[10]);
crypt_shift_salt_2 crypt_shift_salt_instance12(Ltmp[10], Rtmp[10], Ktmp[10], Ktmp[11], CLK, Ltmp[11], Rtmp[11]);
crypt_shift_salt_2 crypt_shift_salt_instance13(Ltmp[11], Rtmp[11], Ktmp[11], Ktmp[12], CLK, Ltmp[12], Rtmp[12]);
crypt_shift_salt_2 crypt_shift_salt_instance14(Ltmp[12], Rtmp[12], Ktmp[12], Ktmp[13], CLK, Ltmp[13], Rtmp[13]);
crypt_shift_salt_2 crypt_shift_salt_instance15(Ltmp[13], Rtmp[13], Ktmp[13], Ktmp[14], CLK, Ltmp[14], Rtmp[14]);
crypt_shift_salt_1 crypt_shift_salt_instance16(Ltmp[14], Rtmp[14], Ktmp[14], Kout, CLK, R_out, L_out);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: moon.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module moon (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/moon.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/moon.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL moon_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, b; cin >> n >> b; long long int a[n], i, j, k, l, t1, t2, sum = 0, ad[n]; for (i = 0; i < n; i++) { cin >> a[i]; ad[i] = a[i]; } vector<pair<long long int, long long int>> v; map<long long int, long long int> mp; for (i = 0; i < b; i++) { cin >> t1 >> t2; v.push_back(make_pair(t1, t2)); } sort(v.begin(), v.end()); sort(a, a + n); i = j = sum = 0; for (i = 0; i < n; i++) { while (a[i] >= v[j].first && j < b) { sum = sum + v[j].second; j++; } mp[a[i]] = sum; } for (i = 0; i < n; i++) { cout << mp[ad[i]] << ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:27:23 11/11/2015
// Design Name:
// Module Name: PongWithSound
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PongWithSound(
input Clock, Reset, rota, rotb, partyMode, growSquares, shiftX, shiftY,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync, vsync,
output Speaker
);
wire [9:0] xpos;
wire [9:0] ypos;
parameter [9:0] NumberofPixels=10'd640, NumberofLines=10'd480;
parameter [9:0] SystemClockFreq=10'd100, CRTClockFreq=10'd25; //MHz
CRTcontroller2015fall VGAdisplay(NumberofPixels, NumberofLines, SystemClockFreq, CRTClockFreq, hsync, vsync, xpos, ypos, Reset, Clock);
GameWithSound game_inst(Clock, Reset, xpos, ypos, rota, rotb, partyMode, growSquares, shiftX, shiftY, red, green, blue, Speaker);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, d, a, b, p[100005], x[100005], y[100005], c, ans[100005]; long long cmp(long long A, long long B) { return x[A] * a + y[A] * b < x[B] * a + y[B] * b; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> d; cin >> a >> b; for (long long i = 1; i <= n; i++) cin >> x[i] >> y[i], p[i] = i; sort(p + 1, p + 1 + n, cmp); for (long long i = 1; i <= n; i++) if (d >= x[p[i]] * a + y[p[i]] * b) d -= x[p[i]] * a + y[p[i]] * b, ans[++c] = p[i]; cout << c << endl; for (int i = 1; i <= c; i++) cout << ans[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; cout << (a + b); return 0; } |
// $Id: c_rr_arbiter.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// round-robin arbiter
//==============================================================================
module c_rr_arbiter
(clk, reset, active, req_pr, gnt_pr, gnt, update);
`include "c_constants.v"
`include "c_functions.v"
// number of input ports
parameter num_ports = 32;
// number of priority levels
parameter num_priorities = 1;
// store priorities in encoded form
parameter encode_state = 1;
// width of encoded arbiter state
localparam state_width = clogb(num_ports);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// vector of requests
input [0:num_priorities*num_ports-1] req_pr;
// vector of grants
output [0:num_priorities*num_ports-1] gnt_pr;
wire [0:num_priorities*num_ports-1] gnt_pr;
// merged vector of grants
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
// update port priorities
input update;
wire [0:num_priorities*num_ports-1] gnt_intm_pr;
wire [0:num_ports-1] mask;
genvar prio;
generate
for(prio = 0; prio < num_priorities; prio = prio + 1)
begin:prios
wire [0:num_ports-1] req;
assign req = req_pr[prio*num_ports:(prio+1)*num_ports-1];
wire [0:num_ports-1] gnt;
c_rr_arbiter_base
#(.num_ports(num_ports))
gnt_ab
(.mask(mask),
.req(req),
.gnt(gnt));
assign gnt_intm_pr[prio*num_ports:(prio+1)*num_ports-1] = gnt;
end
if(encode_state)
begin
wire [0:state_width-1] next_state;
c_encode
#(.num_ports(num_ports),
.offset(1))
next_state_enc
(.data_in(gnt),
.data_out(next_state));
wire [0:state_width-1] state_s, state_q;
assign state_s = update ? next_state : state_q;
c_dff
#(.width(state_width),
.reset_type(reset_type))
stateq
(.clk(clk),
.reset(reset),
.active(active),
.d(state_s),
.q(state_q));
wire [0:num_ports-1] state_therm;
c_decode
#(.num_ports(num_ports),
.therm_enc(1))
state_therm_dec
(.data_in(state_q),
.data_out(state_therm));
assign mask = {1'b0, state_therm[0:num_ports-2]};
end
else
begin
wire [0:num_ports-2] gnt_shifted;
assign gnt_shifted = gnt[1:num_ports-1];
wire [0:num_ports-2] next_mask;
c_one_hot_therm_conv
#(.width(num_ports-1))
next_mask_ohtc
(.data_in(gnt_shifted),
.data_out(next_mask));
wire [0:num_ports-2] mask_s, mask_q;
assign mask_s = update ? next_mask : mask_q;
c_dff
#(.width(num_ports-1),
.reset_type(reset_type))
maskq
(.clk(clk),
.reset(reset),
.active(active),
.d(mask_s),
.q(mask_q));
assign mask = {1'b0, mask_q};
end
if(num_priorities == 1)
begin
assign gnt_pr = gnt_intm_pr;
assign gnt = gnt_intm_pr;
end
else if(num_priorities > 1)
begin
wire [0:num_priorities-1] any_req_pr;
c_reduce_bits
#(.num_ports(num_priorities),
.width(num_ports),
.op(`BINARY_OP_OR))
any_req_pr_rb
(.data_in(req_pr),
.data_out(any_req_pr));
wire [0:num_priorities-1] any_req_mod_pr;
assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
wire [0:num_priorities-1] sel_pr;
c_lod
#(.width(num_priorities))
sel_pr_lod
(.data_in(any_req_mod_pr),
.data_out(sel_pr));
c_gate_bits
#(.num_ports(num_priorities),
.width(num_ports),
.op(`BINARY_OP_AND))
gnt_pr_gb
(.select(sel_pr),
.data_in(gnt_intm_pr),
.data_out(gnt_pr));
c_select_1ofn
#(.num_ports(num_priorities),
.width(num_ports))
gnt_sel
(.select(sel_pr),
.data_in(gnt_intm_pr),
.data_out(gnt));
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int maxn = 3e3 + 4; struct Node { int la, nx; } nodes[maxn]; int X[maxn], Y[maxn]; std::vector<int> yp[maxn]; int R, C, N, K; int ordX[maxn], ord[maxn]; int ans[maxn], xans = 0; inline void update(int x) { int c = x; for (int k = 1; k < K && c; ++k) c = nodes[c].nx; xans -= ans[x]; if (!nodes[x].la) ans[x] = X[c] * (R + 1 - X[x]); else ans[x] = X[c] * (X[nodes[x].la] - X[x]); xans += ans[x]; } int main() { cin >> R >> C >> N >> K; for (int i = 1; i <= N; ++i) { cin >> X[i] >> Y[i]; yp[Y[i]].push_back(i); } iota(ordX + 1, ordX + N + 1, 1); sort(ordX + 1, ordX + N + 1, [&](int a, int b) { return X[a] > X[b]; }); long long rans = 0; for (int ups = 1; ups <= C; ++ups) { xans = 0; memset(ans, 0, sizeof(ans)); int cn = 0; for (int i = 1; i <= N; ++i) { if (Y[ordX[i]] >= ups) ord[++cn] = ordX[i]; } memset(nodes, 0, sizeof(nodes)); for (int i = 1; i <= cn; ++i) { nodes[ord[i]].la = ord[i - 1]; nodes[ord[i - 1]].nx = ord[i]; } for (int i = 1; i <= cn; ++i) update(ord[i]); rans += xans; for (int i = C; i > ups; --i) { for (int j : yp[i]) { nodes[nodes[j].la].nx = nodes[j].nx; nodes[nodes[j].nx].la = nodes[j].la; } for (int j : yp[i]) { for (int k = 1, c = nodes[j].la; k < K && c; ++k, c = nodes[c].la) update(c); if (nodes[j].nx) update(nodes[j].nx); xans -= ans[j]; } rans += xans; } } cout << rans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; string s, h1, m1; int h[10000], m[10000]; bool a[10000]; int main() { int n; cin >> n; cin.ignore(); for (__typeof(n) i = (1); i <= (n); i++) { getline(cin, s); h1 = s.substr(1, 2); m1 = s.substr(4, 2); if (s[7] == a ) a[i] = true; else a[i] = false; stringstream sh, sm; sh.flush(); sm.flush(); sh.clear(); sm.clear(); sh << h1; sm << m1; sh >> h[i]; sm >> m[i]; h[i] %= 12; if (!a[i]) h[i] += 12; } int ans = 1; int k = 0; for (__typeof(n - 1) i = (1); i <= (n - 1); i++) { int t1 = h[i] * 10000 + m[i]; int t2 = h[i + 1] * 10000 + m[i + 1]; if (t1 == t2) k++; else k = 0; if (k == 10) { k = 0; ans++; continue; } if (!(a[i]) && a[i + 1]) { ans++; continue; } if (t1 > t2) { ans++; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class T> inline void RST(T &A) { memset(A, 0, sizeof(A)); } template <class T> inline void FLC(T &A, int x) { memset(A, x, sizeof(A)); } template <class T> inline void CLR(T &A) { A.clear(); } const int dx4[] = {-1, 0, 1, 0}; const int dy4[] = {0, 1, 0, -1}; const int dx8[] = {-1, 0, 1, 0, -1, -1, 1, 1}; const int dy8[] = {0, 1, 0, -1, -1, 1, -1, 1}; const int dxhorse[] = {-2, -2, -1, -1, 1, 1, 2, 2}; const int dyhorse[] = {1, -1, 2, -2, 2, -2, 1, -1}; const int mod = 1000000007; const int inf = 0x3f3f3f3f; const long long inff = 1LL << 60; const double eps = 1e-9; const double oo = 1e25; const double pi = acos(-1.0); template <class T> inline void checkMin(T &a, const T b) { if (b < a) a = b; } template <class T> inline void checkMax(T &a, const T b) { if (a < b) a = b; } template <class T> inline void checkMin(T &a, T &b, const T x) { checkMin(a, x), checkMin(b, x); } template <class T> inline void checkMax(T &a, T &b, const T x) { checkMax(a, x), checkMax(b, x); } template <class T, class C> inline void checkMin(T &a, const T b, C c) { if (c(b, a)) a = b; } template <class T, class C> inline void checkMax(T &a, const T b, C c) { if (c(a, b)) a = b; } template <class T> inline T min(T a, T b, T c) { return min(min(a, b), c); } template <class T> inline T max(T a, T b, T c) { return max(max(a, b), c); } template <class T> inline T min(T a, T b, T c, T d) { return min(min(a, b), min(c, d)); } template <class T> inline T max(T a, T b, T c, T d) { return max(max(a, b), max(c, d)); } template <class T> inline T sqr(T a) { return a * a; } template <class T> inline T cub(T a) { return a * a * a; } template <class T> inline T ceil(T x, T y) { return (x - 1 + y) / y; } inline int sgn(double x) { return x < -eps ? -1 : x > eps; } inline int sgn(double x, double y) { return sgn(x - y); } inline double cot(double x) { return 1. / tan(x); }; inline double sec(double x) { return 1. / cos(x); }; inline double csc(double x) { return 1. / sin(x); }; namespace BO { inline bool _1(int x, int i) { return bool(x & 1 << i); } inline bool _1(long long x, int i) { return bool(x & 1LL << i); } inline long long _1(int i) { return 1LL << i; } inline long long _U(int i) { return _1(i) - 1; }; inline int reverse_bits(int x) { x = ((x >> 1) & 0x55555555) | ((x << 1) & 0xaaaaaaaa); x = ((x >> 2) & 0x33333333) | ((x << 2) & 0xcccccccc); x = ((x >> 4) & 0x0f0f0f0f) | ((x << 4) & 0xf0f0f0f0); x = ((x >> 8) & 0x00ff00ff) | ((x << 8) & 0xff00ff00); x = ((x >> 16) & 0x0000ffff) | ((x << 16) & 0xffff0000); return x; } inline long long reverse_bits(long long x) { x = ((x >> 1) & 0x5555555555555555LL) | ((x << 1) & 0xaaaaaaaaaaaaaaaaLL); x = ((x >> 2) & 0x3333333333333333LL) | ((x << 2) & 0xccccccccccccccccLL); x = ((x >> 4) & 0x0f0f0f0f0f0f0f0fLL) | ((x << 4) & 0xf0f0f0f0f0f0f0f0LL); x = ((x >> 8) & 0x00ff00ff00ff00ffLL) | ((x << 8) & 0xff00ff00ff00ff00LL); x = ((x >> 16) & 0x0000ffff0000ffffLL) | ((x << 16) & 0xffff0000ffff0000LL); x = ((x >> 32) & 0x00000000ffffffffLL) | ((x << 32) & 0xffffffff00000000LL); return x; } template <class T> inline bool odd(T x) { return x & 1; } template <class T> inline bool even(T x) { return !odd(x); } template <class T> inline T low_bit(T x) { return x & -x; } template <class T> inline T high_bit(T x) { T p = low_bit(x); while (p != x) x -= p, p = low_bit(x); return p; } template <class T> inline T cover_bit(T x) { T p = 1; while (p < x) p <<= 1; return p; } template <class T> inline int cover_idx(T x) { int p = 0; while (_1(p) < x) ++p; return p; } inline int clz(int x) { return __builtin_clz(x); } inline int clz(long long x) { return __builtin_clzll(x); } inline int ctz(int x) { return __builtin_ctz(x); } inline int ctz(long long x) { return __builtin_ctzll(x); } inline int lg2(int x) { return !x ? -1 : 31 - clz(x); } inline int lg2(long long x) { return !x ? -1 : 63 - clz(x); } inline int low_idx(int x) { return !x ? -1 : ctz(x); } inline int low_idx(long long x) { return !x ? -1 : ctz(x); } inline int high_idx(int x) { return lg2(x); } inline int high_idx(long long x) { return lg2(x); } inline int parity(int x) { return __builtin_parity(x); } inline int parity(long long x) { return __builtin_parityll(x); } inline int count_bits(int x) { return __builtin_popcount(x); } inline int count_bits(long long x) { return __builtin_popcountll(x); } } // namespace BO using namespace BO; namespace NT { template <class T> inline T lowbit(T x) { return x & -x; } template <class T> inline T GCD(T A, T B) { T C; while (B != 0) C = B, B = A % B, A = C; return A; } template <class T> inline T LCM(T A, T B) { return A * (B / GCD(A, B)); } template <class T> inline T Mod(T a, T b) { a %= b; return a < 0 ? a + b : a; } template <class T> inline T MulMod(T a, T b, T c) { if (c == 1) return 0; if (c <= 0) return -1; T ret = 0, tmp; tmp = a = Mod(a, c); b = Mod(b, c); while (b) { if (b & 0x1) if ((ret += tmp) >= c) ret -= c; if ((tmp <<= 1) >= c) tmp -= c; b >>= 1; } return ret; } template <class T, class Tb> inline T PowMod(Tb a, T b, T c) { if (c == 1) return 0; if (c <= 0) return -1; a = Mod(a, (Tb)c); Tb ret(1L % c); while (b) { if (b & 0x1) ret = ret * a % c; a = a * a % c; b >>= 1; } return (T)ret; } template <class T> inline T HPowMod(T a, T b, T c) { if (c == 1) return 0; if (c <= 0) return -1; a = Mod(a, c); T ret(1L % c); while (b) { if (b & 0x1) ret = MulMod(ret, a, c); a = MulMod(a, a, c); b >>= 1; } return ret; } template <class T, class Tb> inline T Pow(T a, Tb b) { T c(1); while (b) { if (b & 1) c *= a; a *= a, b >>= 1; } return c; } template <class T> inline T EXT_GCD(T a, T b, T &x, T &y) { T t, ret; if (!b) { x = 1, y = 0; return a; } ret = EXT_GCD(b, a % b, x, y); t = x, x = y, y = t - a / b * y; return ret; } template <class T> inline T Inv(T a, T n) { if (n <= 0) return -1; T d, x, y; d = EXT_GCD(a, n, x, y); if (d != 1) return -1; return Mod(x, n); } template <class T, int MAXN, T MOD = -1> class Matrix { public: T m[MAXN][MAXN]; Matrix() {} void init(T num[MAXN][MAXN]) { for (int i = 0; i < MAXN; i++) { for (int j = 0; j < MAXN; j++) { m[i][j] = num[i][j]; if (MOD != -1) m[i][j] %= MOD; } } } friend Matrix operator*(const Matrix &m1, const Matrix &m2) { int i, j, k; Matrix ret; memset(ret.m, 0, sizeof(ret.m)); for (i = 0; i < MAXN; i++) { for (j = 0; j < MAXN; j++) if (m1.m[i][j]) { for (k = 0; k < MAXN; k++) { ret.m[i][k] += m1.m[i][j] * m2.m[j][k]; if (MOD != -1) ret.m[i][k] %= MOD; } } } return ret; } friend Matrix operator+(const Matrix &m1, const Matrix &m2) { int i, j; Matrix ret; for (i = 0; i < MAXN; i++) { for (j = 0; j < MAXN; j++) { ret.m[i][j] = 0; ret.m[i][j] = m1.m[i][j] + m2.m[i][j]; if (MOD != -1) ret.m[i][j] %= MOD; } } return ret; } friend Matrix operator^(const Matrix &_M, long long nx) { Matrix ret, M(_M); for (int i = 0; i < MAXN; i++) { for (int j = 0; j < MAXN; j++) { if (i == j) ret.m[i][j] = 1; else ret.m[i][j] = 0; } } while (nx) { if (nx & 1) ret = ret * M; nx = nx >> 1; M = M * M; } return ret; } }; } // namespace NT using namespace NT; namespace Date { int days[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; struct date { int year, month, day; }; inline int leap(int year) { return (year % 4 == 0 && year % 100 != 0) || year % 400 == 0; } inline int legal(date a) { if (a.month < 0 || a.month > 12) return 0; if (a.month == 2) return a.day > 0 && a.day <= 28 + leap(a.year); return a.day > 0 && a.day <= days[a.month - 1]; } inline int datecmp(date a, date b) { if (a.year != b.year) return a.year - b.year; if (a.month != b.month) return a.month - b.month; return a.day - b.day; } int weekday(date a) { int tm = a.month >= 3 ? (a.month - 2) : (a.month + 10); int ty = a.month >= 3 ? a.year : (a.year - 1); return (ty + ty / 4 - ty / 100 + ty / 400 + (int)(2.6 * tm - 0.2) + a.day) % 7; } int date2int(date a) { int ret = a.year * 365 + (a.year - 1) / 4 - (a.year - 1) / 100 + (a.year - 1) / 400, i; days[1] += leap(a.year); for (i = 0; i < a.month - 1; ret += days[i++]) ; days[1] = 28; return ret + a.day; } date int2date(int a) { date ret; ret.year = a / 146097 * 400; for (a %= 146097; a >= 365 + leap(ret.year); a -= 365 + leap(ret.year), ret.year++) ; days[1] += leap(ret.year); for (ret.month = 1; a >= days[ret.month - 1]; a -= days[ret.month - 1], ret.month++) ; days[1] = 28; ret.day = a + 1; return ret; } } // namespace Date namespace IO { template <class T> inline T RD(T &x) { char c; for (c = getchar(); c < - ; c = getchar()) ; if (c == - ) { x = 0 - getchar(); for (c = getchar(); 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + 0 - c; } else { x = c - 0 ; for (c = getchar(); 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; } return x; } inline long long RD() { long long x; return RD(x); } } // namespace IO using namespace IO; const int N = 3e5 + 7; int a[N], b[N], d[N], e[N]; struct pii { int fi, se; pii(int fi = 0, int se = 0) : fi(fi), se(se) {} bool operator<(const pii &t) const { if (fi != t.fi) return fi < t.fi; else return se < t.se; } bool operator==(const pii &t) const { return (fi == t.fi) && (se == t.se); } }; pii q[N], qq[N]; int main() { int n, p; n = RD(), p = RD(); for (int i = 0; i < n; i++) { int a, b; a = RD(), b = RD(); if (a > b) swap(a, b); d[a]++, d[b]++; e[a]++, e[b]++; q[i] = pii(a, b); qq[i] = pii(a, b); } sort(e + 1, e + 1 + n); long long sum = 0; for (int i = 1; i <= n; i++) { int u = d[i], v = p - d[i]; sum += e + n + 1 - lower_bound(e + 1, e + 1 + n, v); if (u + u >= p) sum--; } assert(even(sum)); sum /= 2LL; sort(q, q + n); sort(qq, qq + n); int m = unique(qq, qq + n) - qq; for (int i = 0; i < m; i++) { int a = qq[i].fi, b = qq[i].se; assert(a != b); int cnt = upper_bound(q, q + n, pii(a, b)) - lower_bound(q, q + n, pii(a, b)); if (d[a] + d[b] >= p && d[a] + d[b] - cnt < p) sum--; } cout << sum << endl; return 0; } |
#include<bits/stdc++.h> using namespace std; const int N=3e5+10; int n,m,mx; int dif[N],b[N]; vector <int> a[N]; void end(){ puts( No ); exit(0); } int main(){ scanf( %d%d ,&n,&m); for(int i=1;i<=n;i++){ a[i].push_back(0); for(int j=1;j<=m;j++){ int x; scanf( %d ,&x); a[i].push_back(x); } } for(int i=2;i<=n;i++){ for(int j=1;j<=m;j++) if(a[1][j]!=a[i][j]) dif[i]++; mx=max(mx,dif[i]); } if(mx>4) end(); if(mx<=2){ puts( Yes ); for(int i=1;i<=m;i++) printf( %d ,a[1][i]); exit(0); } if(mx==4){ int ps=0,now=0,cur[4]={}; for(int i=2;i<=n;i++) if(dif[i]==4){ ps=i; break; } for(int i=1;i<=m;i++) if(a[1][i]!=a[ps][i]) cur[now++]=i; for(int i=0;i<4;i++) for(int j=i+1;j<4;j++){ for(int k=1;k<=m;k++) b[k]=a[1][k]; for(int k=0;k<4;k++){ if(k!=i && k!=j) b[cur[k]]=a[ps][cur[k]]; } int pd=0; for(int k=1;k<=n;k++){ int sum=0; for(int p=1;p<=m;p++) if(a[k][p]!=b[p]) sum++; if(sum>2){ pd=1; break; } } if(!pd){ puts( Yes ); for(int k=1;k<=m;k++) printf( %d ,b[k]); exit(0); } } end(); } else if(mx==3){ int ps=0,now=0,cur[3]={}; for(int i=2;i<=n;i++) if(dif[i]==3){ ps=i; break; } for(int i=1;i<=m;i++) if(a[1][i]!=a[ps][i]) cur[now++]=i; for(int p=0;p<3;p++) for(int q=p+1;q<3;q++){ for(int d=0;d<2;d++){ for(int i=1;i<=m;i++) b[i]=a[1][i]; if(d==0){ b[cur[q]]=a[ps][cur[q]]; } else{ b[cur[p]]=a[ps][cur[p]]; } int pd=0,vis=0,at=0; for(int i=2;i<=n;i++){ int sum=0; for(int j=1;j<=m;j++) if(a[i][j]!=b[j]) sum++; if(sum>=3){ vis=1; at=i; break; } } if(!vis){ puts( Yes ); for(int i=1;i<=m;i++) printf( %d ,b[i]); exit(0); } else{ b[cur[3-p-q]]=a[at][cur[3-p-q]]; for(int i=2;i<=n;i++){ int sum=0; for(int j=1;j<=m;j++) if(a[i][j]!=b[j]) sum++; if(sum==3){ pd=1; break; } } if(!pd){ puts( Yes ); for(int i=1;i<=m;i++) printf( %d ,b[i]); exit(0); } } } } end(); } } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007; const long long int mymax = 1e18; const long long int mymin = -1e18; const double PIE = 3.1415926536; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t, n, m, d, k, ti, lef, rit; bool ans; vector<pair<int, int> > cent; cin >> t; while (t--) { cin >> n >> m >> k; char a[n][m]; int vis[n][m]; cent.clear(); ans = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; vis[i][j] = 0; } } for (int i = n - 1; i >= 1; i--) { for (int j = 1; j <= (m - 2); j++) { if ((a[i][j] == * ) && (a[i - 1][j - 1] == * ) && (a[i - 1][j + 1] == * )) { d = 0; ti = i - 1; lef = j - 1; rit = j + 1; while ((ti >= 0) && (lef >= 0) && (rit < m) && (a[ti][lef] == * ) && (a[ti][rit] == * )) { d++; ti--; lef--; rit++; } if (d >= k) { cent.push_back({i, j}); } } } } for (auto it : cent) { vis[it.first][it.second] = 1; ti = it.first - 1; lef = it.second - 1; rit = it.second + 1; while ((ti >= 0) && (lef >= 0) && (rit < m) && (a[ti][lef] == * ) && (a[ti][rit] == * )) { vis[ti][lef] = vis[ti][rit] = 1; ti--; lef--; rit++; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if ((a[i][j] == * ) && !vis[i][j]) { ans = false; break; } } } cout << ((ans) ? YES : NO ) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long t, a, b, c, d; long long divide(long long x, long long y) { return (x + y - 1) / y; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> a >> b >> c >> d; if (b >= a) cout << b << n ; else if (d >= c) cout << -1 n ; else cout << divide(a - b, c - d) * c + b << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_BLACKBOX_V
`define SKY130_FD_SC_HVL__PROBE_P_BLACKBOX_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__probe_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module mem (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 5;
localparam DW = DATA_WIDTH - 1;
localparam AW = ADDR_WIDTH - 1;
input clka;
input wea;
input [AW:0] addra;
input [DW:0] dina;
input clkb;
input [AW:0] addrb;
output [DW:0] doutb;
reg [DW:0] m_ram[0:((2**ADDR_WIDTH)-1)];
reg [DW:0] doutb;
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
doutb <= m_ram[addrb];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<vector<ll>> a(n + 1, vector<ll>(m + 1)); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> a[i][j]; } } const ll I = 1e18; ll b = I; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { vector<vector<ll>> c(n + 1, vector<ll>(m + 1, I)); c[0][1] = c[1][0] = 0; for (int g = 1; g <= n; ++g) { for (int h = 1; h <= m; ++h) { ll y = a[g][h] - (a[i][j] - (i - g) - (j - h)); if (y >= 0) { c[g][h] = min(c[g - 1][h] + y, c[g][h - 1] + y); } } } b = min(b, c[n][m]); } } cout << b << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUF_PP_BLACKBOX_V
/**
* lsbuf: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbuf (
X ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
output X ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T checkmin(T &a, T b) { return (a < b) ? a : a = b; } template <class T> inline T checkmax(T &a, T b) { return (a > b) ? a : a = b; } template <class T> T GCD(T a, T b) { if (a < 0) return GCD(-a, b); if (b < 0) return GCD(a, -b); return (a == 0) ? b : GCD(b % a, a); } template <class T> T LCM(T a, T b) { if (a < 0) return LCM(-a, b); if (b < 0) return LCM(a, -b); return (a == 0 || b == 0) ? 0 : a / GCD(a, b) * b; } template <class T> inline T sqr(T X) { return X * X; } namespace Poor { const int MaxiN = 100005; const int LogMaxiN = 18; const int CharSet = 256; int N; char St[MaxiN]; long long Ra[CharSet]; long long X[LogMaxiN][MaxiN]; int SA[MaxiN], H[MaxiN]; int LCP(int A, int B) { int Rec = A; for (int j = LogMaxiN - 1; j >= 0; --j) if (A + (1 << j) <= N && B + (1 << j) <= N && X[j][A] == X[j][B]) { A += (1 << j); B += (1 << j); } return A - Rec; } bool Cmp(int A, int B) { int L = LCP(A, B); return A + L == N || (B + L < N && St[A + L] < St[B + L]); } long long Solve(int L, int R, int C) { int Len = LCP(SA[L], SA[R]); long long res = (long long)(R - L + 1) * (R - L + 2) / 2LL * (long long)(Len - C); if (L == R) return res; if (LCP(SA[L], SA[L]) == Len) return res + Solve(L + 1, R, Len); if (LCP(SA[R], SA[R]) == Len) return res + Solve(L, R - 1, Len); int l = L, r = R; while (l < r) { int mid = (l + r + 1) >> 1; if (LCP(SA[L], SA[mid]) > Len) l = mid; else r = mid - 1; } res += Solve(L, l, Len) + Solve(l + 1, R, Len); return res; } void Run() { srand(time(NULL)); gets(St); N = strlen(St); for (int i = 0; i < CharSet; ++i) Ra[i] = (long long)rand() + (((long long)rand()) << 32LL); for (int i = 0; i < N; ++i) X[0][i] = Ra[(int)St[i]]; for (int j = 0; j < LogMaxiN - 1; ++j) for (int i = 0; i < N - (1 << j); ++i) X[j + 1][i] = (X[j][i] * Ra[j + 1]) ^ (X[j][i + (1 << j)]); for (int i = 0; i < N; ++i) SA[i] = i; sort(SA, SA + N, Cmp); cout << Solve(0, N - 1, 0) << endl; } } // namespace Poor int main() { Poor::Run(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int x, y, k; cin >> x >> y >> k; long long int tot = y * k + k; if (x >= tot) { cout << 1 + k << endl; continue; } else if (x == 2) { cout << tot - 1 + k << endl; } else { if ((tot - x) % (x - 1) != 0) { cout << ((tot - x) / (x - 1)) + 2 + k << endl; } else { cout << ((tot - x) / (x - 1)) + 1 + k << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; class Triplet { public: long long x; long long y; long long gcd; }; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } Triplet extendedEuclid(long long a, long long b) { if (b == 0) { Triplet ans; ans.gcd = a; ans.x = 1; ans.y = 0; return ans; } Triplet smallAns = extendedEuclid(b, a % b); Triplet ans; ans.gcd = smallAns.gcd; ans.x = smallAns.y; ans.y = smallAns.x - (a / b) * smallAns.y; return ans; } long long modulo(long long a, long long m) { Triplet ans = extendedEuclid(a, m); return ans.x; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n, a; cin >> n >> a; long long arr[n]; long long maxi = 0; bool found = false; for (long long i = 0; i < n; i++) { cin >> arr[i]; if (found) continue; if (a % arr[i] == 0) { if (a / arr[i] == 1) { found = true; maxi = arr[i]; } } maxi = max(maxi, arr[i]); } if (found) { cout << 1 n ; continue; } else { if (maxi > a) { cout << 2 n ; continue; } else { long long ans = (a / maxi); if (a % maxi != 0) ans++; cout << ans << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int l = n - k; int max_1 = 0; for (int i = 0; i < (n - k); i++) { max_1 = max(max_1, a[i] + a[2 * (n - k) - i - 1]); } max_1 = max(max_1, a[n - 1]); cout << max_1 << endl; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Dual Data Rate Output D Flip-Flop
// /___/ /\ Filename : ODDR2.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 08/20/08 - CR 478850 added pulldown on R/S and pullup on CE.
// 01/12/09 - IR 503207 Reworked C0/C1 alignments
// 06/24/09 - CR 525390 Fixed delta cycle race condition using generate statements
// End Revision
`timescale 1 ps / 1 ps
module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
output Q;
input C0;
input C1;
input CE;
input D0;
input D1;
tri0 GSR = glbl.GSR;
input R;
input S;
parameter DDR_ALIGNMENT = "NONE";
parameter INIT = 1'b0;
parameter SRTYPE = "SYNC";
pullup P1 (CE);
pulldown P2 (R);
pulldown P3 (S);
reg q_out, q_d1_c0_out_int;
// wire PC0, PC1;
buf buf_q (Q, q_out);
initial begin
if ((INIT != 1'b0) && (INIT != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);
$finish;
end
if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin
$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
always @(GSR or R or S) begin
if (GSR == 1) begin
assign q_out = INIT;
assign q_d1_c0_out_int = INIT;
end
else begin
deassign q_out;
deassign q_d1_c0_out_int;
if (SRTYPE == "ASYNC") begin
if (R == 1) begin
assign q_out = 0;
assign q_d1_c0_out_int = 0;
end
else if (R == 0 && S == 1) begin
assign q_out = 1;
assign q_d1_c0_out_int = 1;
end
end // if (SRTYPE == "ASYNC")
end // if (GSR == 1'b0)
end // always @ (GSR or R or S)
// assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1;
// assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0;
generate if((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))
begin
always @(posedge C0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
q_d1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
q_d1_c0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q_out <= D0;
q_d1_c0_out_int <= D1 ;
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (posedge C0)
always @(posedge C1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
if (DDR_ALIGNMENT == "NONE")
q_out <= D1;
else
q_out <= q_d1_c0_out_int;
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (posedge C1)
end
else
begin
always @(posedge C1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
q_d1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
q_d1_c0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q_out <= D0;
q_d1_c0_out_int <= D1 ;
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (posedge C1)
always @(posedge C0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q_out <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q_out <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
if (DDR_ALIGNMENT == "NONE")
q_out <= D1;
else
q_out <= q_d1_c0_out_int;
end // if (CE == 1 && R == 0 && S == 0)
end // always @ (posedge C0)
end
endgenerate
specify
if (C0) (C0 => Q) = (100, 100);
if (C1) (C1 => Q) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODDR2
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_xor.v: Multiported-RAM based on XOR implementation //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_xor
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter nRP = 2 , // number of reading ports
parameter nWP = 2 , // number of writing ports
parameter WAWB = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAWB = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDWB = 0 , // new data for Read-During-Write
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input [nWP-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports
input [DATW *nWP-1:0] WData, // write data - packed from nWP read ports
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output reg [DATW *nRP-1:0] RData); // read data - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
// Register write addresses, data and enables
reg [ADRW*nWP-1:0] WAddr_r; // registered write addresses - packed from nWP write ports
reg [DATW*nWP-1:0] WData_r; // registered write data - packed from nWP read ports
reg [ nWP-1:0] WEnb_r ; // registered write enable for each writing port
always @(posedge clk) begin
WAddr_r <= WAddr;
WData_r <= WData;
WEnb_r <= WEnb ;
end
// unpacked/pack addresses/data
reg [ADRW -1:0] WAddr2D [nWP-1:0] ; // write addresses / 2D
reg [ADRW -1:0] WAddr2D_r [nWP-1:0] ; // registered write addresses / 2D
reg [DATW -1:0] WData2D [nWP-1:0] ; // write data / 2D
reg [DATW -1:0] WData2D_r [nWP-1:0] ; // registered write data / 2D
wire [DATW* nRP -1:0] RDataOut2D [nWP-1:0] ; // read data out / 2D
reg [DATW -1:0] RDataOut3D [nWP-1:0][nRP-1:0]; // read data out / 3D
reg [ADRW*(nWP-1)-1:0] RAddrFB2D [nWP-1:0] ; // read address fb / 2D
reg [ADRW -1:0] RAddrFB3D [nWP-1:0][nWP-2:0]; // read address fb / 3D
wire [DATW*(nWP-1)-1:0] RDataFB2D [nWP-1:0] ; // read data fb / 2D
reg [DATW -1:0] RDataFB3D [nWP-1:0][nWP-2:0]; // read data fb / 3D
reg [DATW -1:0] WDataFB2D [nWP-1:0] ; // write data / 2D
reg [DATW -1:0] RData2D [nRP-1:0] ; // read data / 2D
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nWP, ADRW,WAddr ,WAddr2D );
`ARR1D2D(nWP, ADRW,WAddr_r ,WAddr2D_r );
`ARR1D2D(nWP, DATW,WData ,WData2D );
`ARR1D2D(nWP, DATW,WData_r ,WData2D_r );
`ARR2D1D(nRP, DATW,RData2D ,RData );
`ARR2D3D(nWP,nRP ,DATW,RDataOut2D,RDataOut3D);
`ARR3D2D(nWP,nWP-1,ADRW,RAddrFB3D ,RAddrFB2D );
`ARR2D3D(nWP,nWP-1,DATW,RDataFB2D ,RDataFB3D );
end
// generate and instantiate mulriread RAM blocks
genvar wpi;
generate
for (wpi=0 ; wpi<nWP ; wpi=wpi+1) begin: RPORTwpi
// feedback multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.nRP (nWP-1 ), // number of reading ports
.BYPS (WAWB || RDWB || RAWB), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO ((wpi>0)&&(FILE!="") ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_fdb ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [DATW -1:0]
.RAddr (RAddrFB2D[wpi] ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataFB2D[wpi] )); // read data - packed from nRP read ports - out: [DATW *nRP-1:0]
// output multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.nRP (nRP ), // number of reading ports
.BYPS (RDWB ? 2 : RAWB ), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO ((wpi>0)&&(FILE!="") ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_out ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [DATW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataOut2D[wpi] )); // read data - packed from nRP read ports - out: [DATW *nRP-1:0]
end
endgenerate
// combinatorial logic for output and feedback functions
integer i,j,k;
always @* begin
// generate output read functions
for(i=0;i<nRP;i=i+1) begin
RData2D[i] = RDataOut3D[0][i];
for(j=1;j<nWP;j=j+1) RData2D[i] = RData2D[i] ^ RDataOut3D[j][i];
end
// generate feedback functions
for(i=0;i<nWP;i=i+1) WDataFB2D[i] = WData2D_r[i];
for(i=0;i<nWP;i=i+1) begin
k = 0;
for(j=0;j<nWP-1;j=j+1) begin
k=k+(j==i);
RAddrFB3D[i][j] = WAddr2D[k];
WDataFB2D[k] = WDataFB2D[k] ^ RDataFB3D[i][j];
k=k+1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 1; string s[N]; vector<int> v[N]; bool cmp(string s1, string s2) { return (s1.length() > s2.length() || (s1.length() == s2.length() && s1 >= s2)); } bool solve(int n) { for (int i = 1; i <= n; i++) { if (cmp(s[i - 1], s[i])) return false; if (!v[i].empty()) { int sz = v[i].size(); for (int j = 0; j < sz; j++) { char lim = (v[i][j] == 0) ? 1 : 0 ; while (s[i][v[i][j]] > lim) { s[i][v[i][j]]--; if (cmp(s[i - 1], s[i])) { s[i][v[i][j]]++; break; } } } } } return true; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> s[i]; int len = s[i].length(); for (int j = 0; j < len; j++) { if (s[i][j] == ? ) { s[i][j] = 9 ; v[i].push_back(j); } } } if (!solve(n)) cout << NO ; else { cout << YES << endl; for (int i = 1; i <= n; i++) cout << s[i] << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_SYMBOL_V
`define SKY130_FD_SC_LS__MUX2I_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_SYMBOL_V
|
#include <bits/stdc++.h> const int N = 1000005; using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } int a[N]; int main() { long long n; cin >> n; long long d, d1, ans; for (long long i = 0; i < n; i++) cin >> a[i]; d1 = gcd(a[0], a[1]); ans = a[0] / d1 * a[1]; for (long long i = 2; i < n; i++) { ans = gcd(ans, a[i]); long long gg = gcd(d1, ans); ans = d1 / gg * ans; d1 = gg; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int MaxN = 1010; const int INF = 1000000000; int n; int x[MaxN], y[MaxN], tx[MaxN], ty[MaxN]; long double L, R; long double det(long double x1, long double y1, long double x2, long double y2, long double x3, long double y3) { return x1 * y2 - x2 * y1 + x2 * y3 - x3 * y2 + x3 * y1 - x1 * y3; } void line(long double x1, long double y1, long double x2, long double y2, long double y0, long double& x0) { long double A = y1 - y2; long double B = x2 - x1; long double C = A * x1 + B * y1; x0 = (C - B * y0) / A; } int main() { cin >> n; for (int i = 1; i <= n; ++i) cin >> x[i] >> y[i]; L = x[1], R = x[2]; if (L > R) { for (int i = 1, j = 2; i <= n; ++i) { tx[i] = x[j]; ty[i] = -y[j]; --j; if (!j) j = n; } for (int i = 1; i <= n; ++i) { x[i] = tx[i]; y[i] = ty[i]; } swap(L, R); } for (int i = 3; i <= n; ++i) { int px = x[1], py = y[1]; for (int j = i + 1; j <= n; ++j) if (det(x[i], y[i], x[j], y[j], px, py) > 0) { px = x[j]; py = y[j]; } long double tmp; line(x[i], y[i], px, py, y[1], tmp); L = max(L, tmp); px = x[2], py = y[2]; for (int j = 3; j < i; ++j) if (det(x[i], y[i], px, py, x[j], y[j]) > 0) { px = x[j]; py = y[j]; } line(x[i], y[i], px, py, y[1], tmp); R = min(R, tmp); } int ans = 0; for (int i = L - 1; i <= R + 1; ++i) if (L <= i && i <= R) ++ans; cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/29 20:46:17
// Design Name:
// Module Name: _4bit_mod8_counter_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _4bit_mod8_counter_tb(
);
parameter COUNT = 100;
parameter DELAY = 10;
parameter TIME = COUNT*DELAY;
reg CP,reset,M;
wire [3:0] Q;
wire Qcc_n;
integer i;
_4bit_mod8_counter DUT (.CP(CP), .reset(reset), .M(M), .Q(Q), .Qcc_n(Qcc_n));
initial begin
#TIME $finish;
end
initial begin
CP = 0;
for (i = 0; i < COUNT; i = i + 1) begin
#DELAY CP = ~CP;
end
end
initial begin
reset = 1;
#(2*DELAY) reset = 0;
#(COUNT*DELAY/5) reset = 1;
#(COUNT*DELAY/5) reset = 0;
#(COUNT*DELAY/4) reset = 1;
#(2*DELAY) reset = 0;
end
initial begin
M = 1;
#(COUNT*DELAY/2) M = 0;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_SYMBOL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, N = 1e5 + 10; template <class T> inline bool chkmin(T &A, T B) { return B < A ? A = B, 1 : 0; } template <class T> inline bool chkmax(T &A, T B) { return A < B ? A = B, 1 : 0; } int n, m, A[N], cnt[N], L = 1, R, cur; long long tot, dp[2][N]; void get(int l, int r) { while (l < L) tot += cnt[A[--L]]++; while (R < r) tot += cnt[A[++R]]++; while (L < l) tot -= --cnt[A[L++]]; while (r < R) tot -= --cnt[A[R--]]; } void Solve(int l, int r, int lim1, int lim2) { if (l > r) return; int mid = (l + r) >> 1, t = l; for (int i = (lim1), i_end = (min(lim2, mid)); i <= i_end; ++i) { get(i, mid); if (chkmin(dp[!cur][mid], dp[cur][i - 1] + tot)) t = i; } Solve(l, mid - 1, lim1, t); Solve(mid + 1, r, t, lim2); } int main() { scanf( %d%d , &n, &m); for (int i = (1), i_end = (n); i <= i_end; ++i) { scanf( %d , &A[i]); get(1, i); dp[0][i] = tot; } for (int i = (2), i_end = (m); i <= i_end; ++i) { memset(dp[!cur], 63, sizeof(dp[!cur])); Solve(1, n, 1, n); cur = !cur; } printf( %lld n , dp[cur][n]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 10; long long a[maxn]; int main() { long long n, k, x; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> x; a[i] = a[i - 1] + x; } long long ans = a[n] * k; sort(a + 1, a + n); for (int i = 1; i < k; i++) ans -= a[i]; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a; b = a; long long int x = 0, y = 0, z = 0; long long int i; for (i = 0; i < a.size(); i++) { if (a[i] == a ) { x++; } if (a[i] == b ) { y++; } if (a[i] == c ) { z++; } } sort(b.begin(), b.end()); if (b == a && (z == x || z == y) && x != 0 && y != 0 && z != 0) { cout << YES << endl; } else { cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100004; long long int a[MAXN]; long long int k, n; vector<long long int> b(MAXN, 0); long long int f(double num) { long long int res = 0; for (int i = 0; i < n; i++) { if (num > a[i] + 0.25) { b[i] = 0; continue; } double tem = sqrt(12 * (a[i] - num) - 3); b[i] = (long long int)(tem / 6 + 0.5); if (b[i] > a[i]) b[i] = a[i]; res += b[i]; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; double mid; double lo = -3e18, hi = 1e9; for (int i = 0; i < 200; i++) { mid = (lo + hi) / 2; if (f(mid) >= k) lo = mid; else hi = mid; } long long int tot = 0; priority_queue<pair<long long int, int>, vector<pair<long long int, int> >, greater<pair<long long int, int> > > pq; priority_queue<pair<long long int, int> > pq1; for (int i = 0; i < n; i++) { double tem = sqrt(12 * (a[i] - lo) - 3); b[i] = min((long long int)(tem / 6 + 0.5), a[i]); tot += b[i]; if (b[i]) pq.push({a[i] - 3 * b[i] * b[i] + 3 * b[i] - 1, i}); if (b[i] != a[i]) pq1.push({a[i] - 3 * b[i] * b[i] - 3 * b[i] - 1, i}); } while (tot - k > 0) { pair<long long int, int> tem = pq.top(); pq.pop(); int i = tem.second; b[i]--; tem.first = a[i] - 3 * b[i] * b[i] + 3 * b[i] - 1; pq.push(tem); tot--; } for (int i = 0; i < n; i++) { int bu = b[i]; printf( %d , bu); } return 0; } |
#include <bits/stdc++.h> using namespace std; int N; long long a[100013]; long long mpow(long long x, int k) { long long res = 1; while (k) { if (k & 1) { res *= x; res %= 1000000007; } x *= x; x %= 1000000007; k >>= 1; } return res; } int main() { scanf( %d , &N); long long a = 1, b = -1; for (int i = int(0); i < int(N); i++) { long long x; scanf( %I64d , &x); a *= x % (1000000007 - 1); a %= (1000000007 - 1); if ((x & 1) == 0) { b = 1; } } if (a == 0ll) { a = 1000000007 - 1; } a--; a = mpow(2, a); long long x = a + b; x *= mpow(3, 1000000007 - 2); x %= 1000000007; printf( %I64d/%I64d n , x, a); return 0; } |
#include <bits/stdc++.h> using namespace std; struct elem { int le, num, ri; elem() {} elem(int inle, int innum, int inri) { le = inle; num = innum; ri = inri; } }; elem operator+(elem e1, elem e2) { return elem(e1.le, e1.num + e2.num + (e1.ri and e2.le ? 1 : 0), e2.ri); } vector<elem> genera(int n) { vector<elem> v; for (int i = 0; i + i <= n; i++) v.push_back(elem(0, i, 0)); for (int i = 0; i + i + 1 <= n; i++) { v.push_back(elem(0, i, 1)); v.push_back(elem(1, i, 0)); } for (int i = 0; i + i + 2 <= n; i++) v.push_back(elem(1, i, 1)); return v; } bool puede(elem e1, elem e2, int k, int x) { for (int i = 3; i <= k; i++) { elem nexte1 = e2; elem nexte2 = e1 + e2; e1 = nexte1; e2 = nexte2; if (e2.num > x) return false; } return e2.num == x; } void escribe(elem e, int n) { if (e.le) cout << C ; for (int i = 0; i < e.num; i++) cout << AC ; for (int i = e.le + e.ri + 2 * e.num; i < n; i++) cout << B ; if (e.ri) cout << A ; cout << endl; } int main() { int k, x, n, m; cin >> k >> x >> n >> m; vector<elem> v1 = genera(n); vector<elem> v2 = genera(m); for (int i = 0; i < int(v1.size()); i++) { for (int j = 0; j < int(v2.size()); j++) { if (puede(v1[i], v2[j], k, x)) { escribe(v1[i], n); escribe(v2[j], m); exit(0); } } } cout << Happy new year! << endl; } |
#include <bits/stdc++.h> using namespace std; string s, c; vector<string> v, s1, s2; bool b1(string &d) { if (d.size()) { if (d[0] == 0 && d.size() == 1) { return true; } else if (d[0] == 0 ) { return false; } else { bool ans = true; for (int i = 0; i < d.size(); ++i) { if (!( 0 <= d[i] && d[i] <= 9 )) { ans = false; break; } } return ans; } } else { return false; } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.precision(11); cout.setf(ios::fixed); getline(cin, s); c = ; for (int i = 0; i < s.size(); ++i) { if (s[i] == , || s[i] == ; ) { if (b1(c)) { s1.push_back(c); c = ; } else { s2.push_back(c); c = ; } } else { c.append(1, s[i]); } } if (b1(c)) { s1.push_back(c); c = ; } else { s2.push_back(c); c = ; } if (s1.size()) { cout << << s1[0]; for (int i = 1; i < s1.size(); ++i) { cout << , << s1[i]; } cout << << endl; } else { cout << - << endl; } if (s2.size()) { cout << << s2[0]; for (int i = 1; i < s2.size(); ++i) { cout << , << s2[i]; } cout << << endl; } else { cout << - << endl; } return 0; } |
#include <bits/stdc++.h> int main() { int n; int x, y; int k; int l; scanf( %d , &n); for (x = 4; 2 * x < n; x++) { y = n - x; k = 0; l = 0; for (int i = 2; i < x; i++) { if (x % i == 0) k = 1; } for (int j = 2; j < y; j++) { if (y % j == 0) l = 1; } if (k && l) { printf( %d %d , x, y); break; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_TB_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_TB_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlymetal6s6s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A2111OI_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_BLACKBOX_V
|
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