text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; using ll = long long; int const N = 200 * 1000 + 16; int const M = 1000 * 1000 * 1000 + 7; int n; int a[320]; int f[616]; int ncr[616][616]; int dp[616][616]; struct dsu { int fa[500]; dsu(int n) { iota(fa, fa + n + 10, 0); } int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } void unite(int x, int y) { fa[find(x)] = find(y); } }; int main() { cin.tie(0); cin.sync_with_stdio(0); cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; dsu u(n); for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) { ll x = 1ll * a[i] * a[j]; ll s = sqrt(x) + 0.5; if (s * s == x) u.unite(i, j); } memset(a, 0, sizeof a); for (int i = 0; i < n; ++i) a[u.find(i)]++; sort(a, a + n, greater<int>()); int m = find(a, a + n, 0) - a; for (int i = 0; i < 616; ++i) ncr[i][0] = ncr[i][i] = 1; for (int i = 1; i < 616; ++i) for (int j = 1; j < i; ++j) ncr[i][j] = (ncr[i - 1][j] + ncr[i - 1][j - 1]) % M; f[0] = 1; for (int i = 1; i < 616; ++i) f[i] = 1ll * i * f[i - 1] % M; dp[0][a[0] - 1] = 1; int k = a[0]; for (int i = 1; i < m; ++i) { int len = a[i]; for (int p = 0; p < k; ++p) { int x = dp[i - 1][p]; if (not x) continue; for (int g = 1; g <= len; ++g) { for (int u = min({len, p, g}); u >= 0; --u) { ll y = 1ll * ncr[k - p + 1][g - u] * ncr[p][u] % M; y *= ncr[len - 1][g - 1]; y %= M; dp[i][p - u + len - g] += x * y % M; dp[i][p - u + len - g] %= M; } } } k += len; } int ans = dp[m - 1][0]; for (int i = 0; i < m; ++i) ans = 1ll * ans * f[a[i]] % M; cout << ans; } |
// This module compares two bitstreams and automatically determines their
// offset. This is done by iteratively changing bit delay for I_DAT_REF
// every time the number of errors exceeds ERROR_COUNT. The output O_ERROR
// signal is high for at least ERROR_HOLD cycles.
`default_nettype none
// ============================================================================
module comparator #
(
parameter ERROR_COUNT = 8,
parameter ERROR_HOLD =
)
(
input wire CLK,
input wire RST,
input wire I_DAT_REF,
input wire I_DAT_IOB,
output wire O_ERROR
);
// ============================================================================
// Data latch
reg [2:0] i_dat_ref_sr;
reg [2:0] i_dat_iob_sr;
always @(posedge CLK)
i_dat_ref_sr <= (i_dat_ref_sr << 1) | I_DAT_REF;
always @(posedge CLK)
i_dat_iob_sr <= (i_dat_iob_sr << 1) | I_DAT_IOB;
wire i_dat_ref = i_dat_ref_sr[2];
wire i_dat_iob = i_dat_iob_sr[2];
// ============================================================================
// Shift register for reference data, shift strobe generator.
reg [31:0] sreg;
reg [ 4:0] sreg_sel;
wire sreg_dat;
reg sreg_sh;
always @(posedge CLK)
sreg <= (sreg << 1) | i_dat_ref;
always @(posedge CLK)
if (RST)
sreg_sel <= 0;
else if(sreg_sh)
sreg_sel <= sreg_sel + 1;
assign sreg_dat = sreg[sreg_sel];
// ============================================================================
// Comparator and error counter
wire cmp_err;
reg [31:0] err_cnt;
assign cmp_err = sreg_dat ^ i_dat_iob;
always @(posedge CLK)
if (RST)
err_cnt <= 0;
else if(sreg_sh)
err_cnt <= 0;
else if(cmp_err)
err_cnt <= err_cnt + 1;
always @(posedge CLK)
if (RST)
sreg_sh <= 0;
else if(~sreg_sh && (err_cnt == ERROR_COUNT))
sreg_sh <= 1;
else
sreg_sh <= 0;
// ============================================================================
// Output generator
reg [24:0] o_cnt;
always @(posedge CLK)
if (RST)
o_cnt <= -1;
else if (cmp_err)
o_cnt <= ERROR_HOLD - 2;
else if (~o_cnt[24])
o_cnt <= o_cnt - 1;
assign O_ERROR = !o_cnt[24];
endmodule
|
#include <bits/stdc++.h> int a[100][100]; int d[2][100]; long long c[2][100]; int main() { int n, m, i, j, k; double max = 1; scanf( %d %d , &n, &m); for (i = 0; i < m; i++) { int x, y; scanf( %d %d , &x, &y); x--; y--; a[x][y] = a[y][x] = 1; } for (i = 0; i < n; i++) d[0][i] = d[1][i] = 1e9; d[0][0] = d[1][n - 1] = 0; c[0][0] = c[1][n - 1] = 1; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (d[0][j] == i) { for (k = 0; k < n; k++) { if (a[j][k] == 1 && d[0][k] >= i + 1) { d[0][k] = i + 1; c[0][k] += c[0][j]; } } } if (d[1][j] == i) { for (k = 0; k < n; k++) { if (a[j][k] == 1 && d[1][k] >= i + 1) { d[1][k] = i + 1; c[1][k] += c[1][j]; } } } } } for (i = 1; i < n - 1; i++) { double tmp; if (d[0][i] + d[1][i] > d[0][n - 1]) continue; tmp = 2.0 * c[0][i] * c[1][i] / c[0][n - 1]; if (tmp > max) max = tmp; } printf( %.12lf n , max); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5001; long long x11[10]; long long y11[10]; long long x22[10]; long long y22[10]; long long deltax[10]; long long deltay[10]; int main() { bool flag1 = 0; bool flag2 = 0; bool flag3 = 0; for (int i = 0; i < 4; i++) { scanf( %lld %lld %lld %lld , &x11[i], &y11[i], &x22[i], &y22[i]); if (x11[i] == x22[i] && y11[i] == y22[i]) flag3 = 1; deltax[i] = x11[i] - x22[i]; deltay[i] = y11[i] - y22[i]; if (deltax[i] == 0) flag1 = 1; if (deltay[i] == 0) flag2 = 1; } if (!flag1 || !flag2 || flag3) { printf( NO n ); return 0; } for (int i = 0; i < 4; i++) { if (deltax[i] != 0 && deltay[i] != 0) { printf( NO n ); return 0; } } vector<long long> vx; vector<long long> vy; map<long long, int> mp1; map<long long, int> mp2; for (int i = 0; i < 4; i++) { vx.push_back(x11[i]); vx.push_back(x22[i]); vy.push_back(y11[i]); vy.push_back(y22[i]); mp1[x11[i]]++; mp1[x22[i]]++; mp2[y11[i]]++; mp2[y22[i]]++; } if (mp1.size() != 2 || mp2.size() != 2) { printf( NO n ); } else { bool tempflag = 0; for (auto it : mp1) { if (it.second != 4) tempflag = 1; } for (auto it : mp2) { if (it.second != 4) tempflag = 1; } if (!tempflag) printf( YES n ); else printf( NO n ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_PP_BLACKBOX_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<int> g1[2111]; vector<int> g2[2111]; vector<int> v1, v2; int s1[1111][1111]; int s2[1111][1111]; int N; pair<int, int> dfs1(int v) { pair<int, int> p = {1000, 0}; if (v1[v]) p = {v1[v], v1[v]}; for (auto to : g1[v]) { auto cur = dfs1(to); p.first = min(cur.first, p.first); p.second = max(cur.second, p.second); } for (int i = 1; i <= p.first; ++i) for (int j = p.second; j <= N; ++j) s1[i][j]++; return p; } pair<int, int> dfs2(int v) { pair<int, int> p = {1000, 0}; if (v2[v]) p = {v2[v], v2[v]}; for (auto to : g2[v]) { auto cur = dfs2(to); p.first = min(cur.first, p.first); p.second = max(cur.second, p.second); } for (int i = 1; i <= p.first; ++i) for (int j = p.second; j <= N; ++j) s2[i][j]++; return p; } int dp[1111]; int main() { cin >> N; int n1; cin >> n1; for (int i = 2; i <= n1; ++i) { int t; cin >> t; g1[t].push_back(i); } v1.assign(n1 + 1, 0); for (int i = 1; i <= N; ++i) { int t; cin >> t; v1[t] = i; } int n2; cin >> n2; for (int i = 2; i <= n2; ++i) { int t; cin >> t; g2[t].push_back(i); } v2.assign(n2 + 1, 0); for (int i = 1; i <= N; ++i) { int t; cin >> t; v2[t] = i; } dfs1(1); dfs2(1); for (int i = 1; i <= N; ++i) { for (int j = 1; j <= N; ++j) { s1[i][j] = min(s1[i][j], n1 - 1); s2[i][j] = min(s2[i][j], n2 - 1); } } for (int i = 1; i <= N; ++i) { int mx1 = s1[1][i]; int mx2 = s2[1][i]; dp[i] = max(mx1, mx2); for (int j = i; j >= 2; --j) { { int cur = s1[j][i]; dp[i] = max(dp[i], dp[j - 1] + cur); } { int cur = s2[j][i]; dp[i] = max(dp[i], dp[j - 1] + cur); } } } cout << dp[N] << endl; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; const int mod = 1e9 + 7; int v[200005]; int n, k; bool guess(int x) { ll spent = x - v[n / 2]; for (int i = n / 2 + 1; i < n; i++) { spent += max(0, x - v[i]); if (spent > (ll)k) return false; } return spent <= (ll)k; } int solve() { int x = -1; for (int b = v[n - 1] + k; b >= 1; b /= 2) while (guess(x + b)) x += b; return x; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) cin >> v[i]; sort(v, v + n); cout << solve() << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 1005; int parent[2 * M]; vector<pair<pair<int, int>, pair<int, int> > > edges; void init() { for (int i = 0; i < 2 * M; i++) parent[i] = i; } int find(int u) { if (u == parent[u]) return u; return parent[u] = find(parent[u]); } void un(int u, int v) { u = find(u); v = find(v); parent[u] = v; } int main() { int n, m, q; scanf( %d %d %d , &n, &m, &q); for (int i = 1; i <= m; i++) { int a, b, c; scanf( %d %d %d , &a, &b, &c); edges.push_back(make_pair(make_pair(c, i), make_pair(a, b))); } sort(edges.begin(), edges.end(), greater<pair<pair<int, int>, pair<int, int> > >()); while (q--) { int l, r; scanf( %d %d , &l, &r); int ans = -1; init(); for (int i = 0; i < edges.size(); i++) { int c = edges[i].first.first; int id = edges[i].first.second; int u = edges[i].second.first; int v = edges[i].second.second; if (id < l || id > r) continue; if (find(u) == find(v)) { ans = c; break; } un(u, v + n); un(u + n, v); } printf( %d n , ans); } return 0; } |
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
cpu_0_jtag_debug_module_tck the_cpu_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
cpu_0_jtag_debug_module_sysclk the_cpu_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic cpu_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam cpu_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// cpu_0_jtag_debug_module_phy.sld_instance_index = 0,
// cpu_0_jtag_debug_module_phy.sld_ir_width = 2,
// cpu_0_jtag_debug_module_phy.sld_mfg_id = 70,
// cpu_0_jtag_debug_module_phy.sld_sim_action = "",
// cpu_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// cpu_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// cpu_0_jtag_debug_module_phy.sld_type_id = 34,
// cpu_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//mac_queue.v
// Derived from NetFPGA Project.
///////////////////////////////////////////////////////////////////////////////
module dma_queue
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter ENABLE_HEADER = 0,
parameter STAGE_NUMBER = 'hff,
parameter PORT_NUMBER = 0
)(// --- register interface
/*input mac_grp_reg_req,
input mac_grp_reg_rd_wr_L,
input [31:0] mac_grp_reg_addr,
input [31:0] mac_grp_reg_wr_data,
output [31:0] mac_grp_reg_rd_data,
output mac_grp_reg_ack,*/
// --- output to data path interface
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
// --- input from data path interface
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- input from mac interface
input [31:0] s_rx_axis_tdata,
input s_rx_axis_tvalid,
input s_rx_axis_tlast,
output s_rx_axis_tready,
input [3:0] s_rx_axis_tkeep,
// --- output to mac interface
output m_tx_axis_tvalid,
output [31:0] m_tx_axis_tdata,
output m_tx_axis_tlast,
output [3:0] m_tx_axis_tkeep,
input m_tx_axis_tready,
//--- misc
output [11:0] tx_pkt_byte_cnt,
output tx_pkt_byte_cnt_vld,
input axis_aclk,
input clk,
input reset
);
//wire [11:0] tx_pkt_byte_cnt;
wire [9:0] tx_pkt_word_cnt;
wire [11:0] rx_pkt_byte_cnt;
wire [9:0] rx_pkt_word_cnt;
rx_queue
#(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_HEADER(ENABLE_HEADER),
.STAGE_NUMBER(STAGE_NUMBER),
.PORT_NUMBER(PORT_NUMBER)
) rx_queue
( // user data path interface
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_data (out_data),
.out_rdy (out_rdy),
// gmac interface
.s_rx_axis_aclk (axis_aclk),
.s_rx_axis_tdata (s_rx_axis_tdata),
.s_rx_axis_tvalid (s_rx_axis_tvalid),
.s_rx_axis_tlast (s_rx_axis_tlast),
.s_rx_axis_tkeep (s_rx_axis_tkeep),
.s_rx_axis_tready (s_rx_axis_tready),
// reg signals
.rx_pkt_good (rx_pkt_good),
.rx_pkt_bad (rx_pkt_bad),
.rx_pkt_dropped (rx_pkt_dropped),
.rx_pkt_byte_cnt (rx_pkt_byte_cnt),
.rx_pkt_word_cnt (rx_pkt_word_cnt),
.rx_pkt_pulled (rx_pkt_pulled),
//.rx_queue_en (rx_queue_en),
// misc
.reset (reset),
.clk (clk)
);
dma_tx_queue
#(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_HEADER(ENABLE_HEADER),
.STAGE_NUMBER(STAGE_NUMBER)
) tx_queue
(// data path interface
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_data (in_data),
.in_rdy (in_rdy),
// gmac interface
.m_tx_axis_aclk (axis_aclk),
.m_tx_axis_tdata (m_tx_axis_tdata),
.m_tx_axis_tvalid (m_tx_axis_tvalid),
.m_tx_axis_tlast (m_tx_axis_tlast),
.m_tx_axis_tkeep (m_tx_axis_tkeep),
.m_tx_axis_tready (m_tx_axis_tready),
// reg signals
//.tx_queue_en (tx_queue_en),
//.tx_pkt_sent (tx_pkt_sent),
.tx_pkt_stored (tx_pkt_stored),
.tx_pkt_byte_cnt (tx_pkt_byte_cnt),
.tx_pkt_byte_cnt_vld (tx_pkt_byte_cnt_vld),
.tx_pkt_word_cnt (tx_pkt_word_cnt),
// misc
.reset (reset),
.clk (clk)
);
/*
eth_queue_regs
#(
.CTRL_WIDTH(CTRL_WIDTH)
) eth_queue_regs
(
.mac_grp_reg_req (mac_grp_reg_req),
.mac_grp_reg_rd_wr_L (mac_grp_reg_rd_wr_L),
.mac_grp_reg_addr (mac_grp_reg_addr),
.mac_grp_reg_wr_data (mac_grp_reg_wr_data),
.mac_grp_reg_rd_data (mac_grp_reg_rd_data),
.mac_grp_reg_ack (mac_grp_reg_ack),
// interface to rx queue
.rx_pkt_good (rx_pkt_good),
.rx_pkt_bad (rx_pkt_bad),
.rx_pkt_dropped (rx_pkt_dropped),
.rx_pkt_byte_cnt (rx_pkt_byte_cnt),
.rx_pkt_word_cnt (rx_pkt_word_cnt),
.rx_pkt_pulled (rx_pkt_pulled),
.rx_queue_en (rx_queue_en),
// interface to tx queue
.tx_queue_en (tx_queue_en),
.tx_pkt_sent (tx_pkt_sent),
.tx_pkt_stored (tx_pkt_stored),
.tx_pkt_byte_cnt (tx_pkt_byte_cnt),
.tx_pkt_word_cnt (tx_pkt_word_cnt),
.clk (clk),
.reset (reset)
);*/
endmodule // nf2_mac_grp
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; int main() { ios::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int t; cin >> t; for (int hh = 1; hh <= t; hh++) { int a, b, c, r, aa, bb; cin >> aa >> bb >> c >> r; int r1, r2; r1 = c - r; r2 = c + r; a = min(aa, bb); b = max(aa, bb); if (a >= r2) { cout << b - a << endl; continue; } if (b <= r1) { cout << b - a << endl; continue; } if (a >= r1 && b <= r2) { cout << 0 << endl; continue; } if (a < r1 && b > r2) { cout << r1 - a + b - r2 << endl; continue; } if (a < r1 && b <= r2) { cout << r1 - a << endl; continue; } if (a >= r1 && b > r2) { cout << b - r2 << endl; continue; } } return 0; } |
#include <bits/stdc++.h> using namespace std; map<long long, long long> bismarck, dp; long long n; void factorization(long long x) { for (long long i = 2; i * i <= x; i++) { if (x % i == 0) { long long c = 0; while (x % i == 0) { c++; x /= i; } dp[i] |= 1 << (c - 1); } } if (x > 1) { dp[x] |= 1; } } long long grundy(long long x) { if (x == 0) return 0; if (bismarck.count(x)) return bismarck[x]; unordered_set<long long> s; for (long long i = 0; x >> i; i++) { s.insert(grundy(x >> i + 1 | (x & (1 << i) - 1))); } long long mex = 0; while (s.count(mex)) mex++; return bismarck[x] = mex; } int main() { long long x, ans = 0; cin >> n; while (n--) { cin >> x; factorization(x); } for (auto t : dp) { ans ^= grundy(t.second); } if (ans) cout << Mojtaba ; else cout << Arpa ; } |
#include <bits/stdc++.h> using namespace std; int main() { long n, t; cin >> n >> t; string s1, s2; getline(cin, s1); getline(cin, s1, . ); getline(cin, s2); long a = -1, count = 0; for (int i = 0; i < s2.length(); i++) if (s2[i] >= 5 ) { a = i; break; } if (a == -1) { cout << s1 << . << s2; return 0; } if (a == 0) { int c = s1.length() - 1; while (s1[c] == 9 && c >= 0) c--; if (c == -1) { cout << 1 ; for (int i = 0; i < s1.length(); i++) cout << 0 ; return 0; } s1[c]++; for (c++; c < s1.length(); c++) s1[c] = 0 ; cout << s1; return 0; } long b = a - 1; while (s2[b] == 4 && b >= 0 && b >= a - t + 1) { b--; } if (b == -1) { int c = s1.length() - 1; while (s1[c] == 9 && c >= 0) c--; if (c == -1) { cout << 1 ; for (int i = 0; i < s1.length(); i++) cout << 0 ; return 0; } s1[c]++; for (c++; c < s1.length(); c++) s1[c] = 0 ; cout << s1; return 0; } else { s2[b]++; cout << s1 << . ; for (int i = 0; i <= b; i++) cout << s2[i]; return 0; } return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module m26_rx
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter HEADER = 0,
parameter IDENTYFIER = 0
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK_RX,
input wire MKD_RX,
input wire [1:0] DATA_RX,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire [31:0] TIMESTAMP,
output wire LOST_ERROR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
m26_rx_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTYFIER(IDENTYFIER),
.HEADER(HEADER)
) i_m26_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_RX(CLK_RX),
.MKD_RX(MKD_RX),
.DATA_RX(DATA_RX),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.TIMESTAMP(TIMESTAMP),
.LOST_ERROR(LOST_ERROR)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int md = 1e9 + 7; int n; char s[111]; int f[111][3333]; int main() { int t; f[0][0] = 1; for (int i = 1; i <= 100; ++i) { for (int j = 0; j <= 3000; ++j) { for (int c = 0; c <= min(j, 25); ++c) { f[i][j] += f[i - 1][j - c]; f[i][j] %= md; } } } scanf( %d , &t); while (t--) { scanf( %s , s); int sum = 0; for (int i = 0; i < strlen(s); ++i) sum += s[i] - a ; printf( %d n , (f[strlen(s)][sum] + md - 1) % md); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ceilVal(long long a, long long b) { long long sum = a / b; if (a % b) return ++sum; return sum; } int main() { long long a, n, m; scanf( %lld%lld%lld , &n, &m, &a); long long sum = 0; sum = ceilVal(n, a) * ceilVal(m, a); printf( %lld , sum); return 0; } |
module spi_wrapper(
input clk,
input reset,
// SPI signals
input mosi,
input ss,
input sck,
output miso,
// Input stream
input [31:0] data_in,
output data_in_rdy, // When ready to send data
output data_in_ack, // data_in was consumed
input data_in_rq, // Data send requested
// Output stream
output reg [31:0] data_out,
output reg data_out_rdy, // Word received
input data_out_ack, // consumed
output reg spi_led
);
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], sck};
wire SCK_risingedge = (SCKr[2:1]==3'b01);
wire SCK_fallingedge = (SCKr[2:1]==2'b10);
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], ss};
wire SSEL_active = ~SSELr[1];
wire SSEL_startmessage = (SSELr[2:1]==2'b10);
wire SSEL_endmessage = (SSELr[2:1]==2'b01);
reg [1:0] MOSIr;
always @(posedge clk) MOSIr <= {MOSIr[0], mosi};
wire MOSI_data = MOSIr[1];
reg [4:0] bitcnt;
reg [3:0] bitcnt_b;
reg [31:0] word_data_received;
reg [2:0] bytecnt;
reg [4:0] started;
reg [31:0] echo;
// Receiving
always @(posedge clk)
if (!reset) begin
started <= 0;
echo <= 0;
data_out <= 0;
data_out_rdy <= 0;
bitcnt <= 0;
bytecnt <= 0;
bitcnt_b <= 0;
end else
begin
if (data_out_ack) data_out_rdy <= 0;
if(~SSEL_active) begin
spi_led <= 1;
bitcnt_b <= 0;
started <= 5'b10101;
if (started != 5'b10101) begin
bitcnt <= 0;
word_data_sent <= data_in;
end else
if (bitcnt == 5'b11111) word_data_sent <= data_in;
end else
if(SCK_risingedge)
begin
word_data_received <= {word_data_received[30:0], MOSI_data};
if(bitcnt==5'b11111) begin
data_out <= {word_data_received[30:0], MOSI_data};
data_out_rdy <= 1;
end
end else // if (SCK_risingedge)
if (SCK_fallingedge) begin
if(bitcnt==5'b11111) begin
word_data_sent <= data_in;
end else begin
spi_led <= ~spi_led;
word_data_sent <= {word_data_sent[30:0], 1'b0};
end
bitcnt <= bitcnt + 1;
bitcnt_b <= bitcnt_b + 1;
end
end // always @ (posedge clk)
always @(posedge clk)
if(SSEL_active && SCK_fallingedge && bitcnt == 0) bytecnt <= 0;
else
if(SSEL_active && SCK_fallingedge && bitcnt_b == 3'b111) bytecnt <= bytecnt + 1;
// Sending
reg [31:0] cnt;
always @(posedge clk) if(SSEL_startmessage) cnt<=cnt+1;
reg [31:0] word_data_sent;
assign data_in_rdy = bitcnt == 5'b00000; // ready to send a new word
assign data_in_ack = bitcnt == 5'b11111; // done sending
assign miso = word_data_sent[31];
endmodule // spi_wrapper
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int b[8]; for (int i = 1; i <= 7; ++i) cin >> b[i]; int first = b[7] - b[6]; int last = b[7] - b[5]; cout << first << << b[7] - (first + last) << << last << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { int a; cin >> a; if (i == j || i + j == n - 1 || i == n / 2 || j == n / 2) ans += a; } cout << ans; } |
#include<bits/stdc++.h> #define lowbit(x) ((x)&(-(x))) #define DEBUG fprintf(stderr, Running on Line %d in Function %s n ,__LINE__,__FUNCTION__) #define SZ(x) ((int)x.size()) #define mkpr std::make_pair #define pb push_back typedef long long ll; typedef unsigned int uint; typedef unsigned long long ull; typedef std::pair<int,int> pi; typedef std::pair<ll,ll> pl; using std::min; using std::max; const int inf=0x3f3f3f3f,Inf=0x7fffffff; const ll INF=0x3f3f3f3f3f3f3f3f; std::mt19937 rnd(std::chrono::steady_clock::now().time_since_epoch().count()); template <typename _Tp>_Tp gcd(const _Tp &a,const _Tp &b){return !b?a:gcd(b,a%b);} template <typename _Tp>inline _Tp abs(const _Tp &a){return a>=0?a:-a;} template <typename _Tp>inline void chmax(_Tp &a,const _Tp &b){a=a<b?b:a;} template <typename _Tp>inline void chmin(_Tp &a,const _Tp &b){a=a<b?a:b;} template <typename _Tp>inline void read(_Tp &x) { char ch(getchar());bool f(false);while(!isdigit(ch)) f|=ch==45,ch=getchar(); x=ch&15,ch=getchar();while(isdigit(ch)) x=(((x<<2)+x)<<1)+(ch&15),ch=getchar(); f&&(x=-x); } template <typename _Tp,typename... Args>void read(_Tp &t,Args &...args){read(t);read(args...);} inline int read_str(char *s) { char ch(getchar());while(ch== ||ch== r ||ch== n ) ch=getchar(); char *tar=s;*tar++=ch,ch=getchar();while(ch!= &&ch!= r &&ch!= n &&ch!=EOF) *tar++=ch,ch=getchar(); return *tar=0,tar-s; } const int max_len=1<<16,N=max_len+5,mod=998244353; template<typename _Tp1,typename _Tp2>inline void add(_Tp1 &a,_Tp2 b){(a+=b)>=mod&&(a-=mod);} template<typename _Tp1,typename _Tp2>inline void sub(_Tp1 &a,_Tp2 b){(a-=b)<0&&(a+=mod);} template<typename _Tp>inline _Tp _sub(_Tp a,const _Tp &b){(a+=mod-b)>=mod&&(a-=mod);return a;} ll ksm(ll a,ll b=mod-2){ll res=1;while(b){if(b&1)res=res*a%mod;a=a*a%mod,b>>=1;}return res;} typedef std::vector<int> poly; void print(const poly &a) { for(auto it:a) printf( %d ,it); printf( n ); } poly operator << (const poly &a,uint b) { poly o(a.size()+b); for(uint i=0;i<b;++i) o[i]=0; for(uint i=0;i<a.size();++i) o[i+b]=a[i]; return o; } inline poly operator <<= (poly &a,uint b){return a=a<<b;} inline poly operator >> (const poly &a,uint b){return b>=a.size()?poly():poly{a.begin()+b,a.end()};} inline poly operator >>= (poly &a,uint b){return a=b>=a.size()?poly():poly{a.begin()+b,a.end()};} poly operator += (poly &a,const poly &b) { if(SZ(b)>SZ(a)) a.resize(SZ(b)); for(uint i=0;i<b.size();++i) add(a[i],b[i]); return a; } inline poly operator + (const poly &a,const poly &b){poly tmp(a);tmp+=b;return tmp;} poly operator -= (poly &a,const poly &b) { if(SZ(b)>SZ(a)) a.resize(SZ(b)); for(uint i=0;i<b.size();++i) sub(a[i],b[i]); return a; } inline poly operator - (const poly &a,const poly &b){poly tmp(a);tmp-=b;return tmp;} ull Omgs[N]; int r[N]; const ull Omg=ksm(3,(mod-1)/max_len); int getlen(int len) { int limit=1;while(limit<len)limit<<=1; for(int i=0;i<limit;++i)r[i]=(r[i>>1]>>1)|(i&1?limit>>1:0); return limit; } void setup() { Omgs[max_len>>1]=1; for(int i=(max_len>>1)+1;i<max_len;++i) Omgs[i]=Omgs[i-1]*Omg%mod; for(int i=(max_len>>1)-1;i>0;--i) Omgs[i]=Omgs[i<<1]; } void dft(ull *A,int limit) { for(int i=0;i<limit;++i)if(i<r[i])std::swap(A[i],A[r[i]]); for(int len=1;len<limit;len<<=1) { if(len==262144)for(int i=0;i<limit;++i)A[i]%=mod; for(int i=0;i<limit;i+=len<<1) { ull *p=A+i,*q=A+i+len,*w=Omgs+len; for(int _=0;_<len;++_,++p,++q,++w){ull tmp=*q**w%mod;*q=*p+mod-tmp,*p+=tmp;} } } for(int i=0;i<limit;++i)A[i]%=mod; } void idft(ull *A,int limit) { std::reverse(A+1,A+limit),dft(A,limit); ull inv=mod-(mod-1)/limit;for(int i=0;i<limit;++i) A[i]=inv*A[i]%mod; } ull _f[N],_g[N]; poly operator * (const poly &a,const poly &b) { uint len=a.size()+b.size()-1; if(a.size()<=64u||b.size()<=64u) { poly c(len); for(uint i=0;i<a.size();++i) for(uint j=0;j<b.size();++j) add(c[i+j],1ull*a[i]*b[j]%mod); return c; } int limit=getlen(len); memset(_f,0,limit<<3);for(uint i=0;i<a.size();++i)_f[i]=a[i]; memset(_g,0,limit<<3);for(uint i=0;i<b.size();++i)_g[i]=b[i]; dft(_f,limit),dft(_g,limit); for(int i=0;i<limit;++i)_f[i]=1ULL*_f[i]*_g[i]%mod; idft(_f,limit); poly ans(len);for(uint i=0;i<len;++i)ans[i]=_f[i]; return ans; } poly mul(const poly &a,const poly &b,uint len,bool need=true) { if(a.size()<=64u||b.size()<=64u) { poly c(SZ(a)+SZ(b)-1); for(uint i=0;i<a.size();++i) for(uint j=0;j<b.size();++j) add(c[i+j],1ull*a[i]*b[j]%mod); return c.resize(len),c; } int limit=getlen(len); memset(_f,0,limit<<3);for(uint i=0;i<a.size();++i)_f[i]=a[i]; dft(_f,limit); if(need) { memset(_g,0,limit<<3);for(uint i=0;i<b.size();++i)_g[i]=b[i]; dft(_g,limit); } for(int i=0;i<limit;++i)_f[i]=1ULL*_f[i]*_g[i]%mod; idft(_f,limit); poly ans(len);for(uint i=0;i<len;++i)ans[i]=_f[i]; return ans; } inline poly operator *= (poly &a,const poly &b){return a=a*b;} template<typename _Tp>inline poly operator *= (poly &a,const _Tp &b) { for(auto &&it:a) it=1ll*it*b%mod; return a; } template<typename _Tp>inline poly operator * (poly a,const _Tp &b){return a*=b;} template<typename _Tp>inline poly operator * (const _Tp &b,poly a){return a*=b;} template<typename _Tp>inline poly operator /= (poly &a,const _Tp &b) { ull inv=ksm(b);for(auto &&it:a) it=1ll*it*inv%mod; return a; } template<typename _Tp>inline poly operator / (poly a,const _Tp &b){return a/=b;} template<typename _Tp>inline poly operator / (const _Tp &b,poly a){return a/=b;} ll fac[N],ifac[N],inv[N]; poly getcoef(poly h,ll m,int c) { static int I[N],P[N]; int d=SZ(h)-1; for(int i=0;i<=d;++i)h[i]=1LL*h[i]*ifac[d-i]%mod*((d-i)&1?mod-ifac[i]:ifac[i])%mod; for(int i=0;i<c+d;++i)I[i]=m-d+i; P[0]=I[0];for(int i=1;i<c+d;++i)P[i]=1LL*I[i]*P[i-1]%mod; ll tp=ksm(P[c+d-1]); for(int i=c+d-1;i>=0;--i)P[i]=1LL*tp*(i?P[i-1]:1)%mod,tp=tp*I[i]%mod; poly a=mul(poly{P,P+c+d},h,c+d); ll cur=1;for(int i=1;i<=d;++i)cur=cur*(m-i)%mod; poly ans(c); for(int k=0;k<c;++k) cur=cur*(m+k)%mod,ans[k]=cur*a[d+k]%mod,cur=cur*P[k]%mod; return ans; } int f[N],S; void init(int n) { S=(int)sqrt(n); int cur=0; while(1LL*S*S<n)++S; while(1LL*S*S>n)--S; memset(f,0,(S+1)<<2),f[0]=1; for(int i=16;i>=0;--i) { if(cur) { poly h={f,f+cur+1},a=getcoef(h,cur+1,cur); h.resize(SZ(a)+SZ(h));for(int i=0;i<cur;++i)h[i+cur+1]=a[i]; poly b=getcoef(h,1LL*cur*ksm(S)%mod,cur+cur+1); cur<<=1;for(int i=0;i<=cur;++i)f[i]=1LL*h[i]*b[i]%mod; } if((S>>i)&1) { f[++cur]=1; for(int j=0;j<cur;++j)f[j]=1LL*f[j]*(j*S+cur)%mod; for(int i=1;i<=cur;++i)f[cur]=1LL*f[cur]*(cur*S+i)%mod; } } } ll getfac(int n) { int i,ans=1; for(i=0;(i+1)*S<=n;++i)ans=1LL*ans*f[i]%mod; for(int j=i*S+1;j<=n;++j)ans=1LL*ans*j%mod; return ans; } int a[1005],s; inline ll getF(int a){return (getfac(s+s-1)*ksm(getfac(s+s-a-1))%mod*ksm(getfac(s))%mod*getfac(s-a)+mod-1)%mod;} int main() { setup(); fac[0]=fac[1]=inv[0]=inv[1]=ifac[0]=ifac[1]=1;for(int i=2;i<N;++i)fac[i]=fac[i-1]*i%mod,inv[i]=inv[mod%i]*(mod-mod/i)%mod,ifac[i]=ifac[i-1]*inv[i]%mod; int n;read(n); for(int i=1;i<=n;++i)read(a[i]),s+=a[i]; init(s+s); int ans=mod-getF(s); for(int i=1;i<=n;++i)add(ans,getF(a[i])); ans=1LL*(mod-2)*s%mod*ksm(s-1)%mod*ans%mod; printf( %d n ,ans); return 0; } |
#include <bits/stdc++.h> using namespace std; typedef struct node { struct node* b[3]; int flag[3]; } node; node* root; vector<int> ans; int bit[32], bit_n[32]; void calc(int u) { memset(bit_n, 0, sizeof(bit_n)); memset(bit, 0, sizeof(bit)); int j = 0, num; for (num = u; num > 0; num = num / 2) bit_n[j++] = num % 2; for (int i = 0; i < 32; i++) bit[i] = bit_n[31 - i]; } void insert(int u) { node* head; head = root; calc(u); for (int i = 0; i < 32; i++) { if (head->b[bit[i]] == NULL) { node* temp; temp = (node*)malloc(sizeof(node)); for (int j = 0; j < 3; j++) temp->b[j] = NULL, temp->flag[j] = 0; head->b[bit[i]] = temp; } head->flag[bit[i]]++; head = head->b[bit[i]]; } return; } void del(int u) { node* head; head = root; calc(u); for (int i = 0; i < 32; i++) { head->flag[bit[i]]--; head = head->b[bit[i]]; } return; } void search(int u) { calc(u); node* head; head = root; for (int i = 0; i < 32; i++) { if (bit[i] == 1) { if (head->flag[0]) ans.push_back(1), head = head->b[0]; else ans.push_back(0), head = head->b[1]; } else { if (head->flag[1]) ans.push_back(1), head = head->b[1]; else ans.push_back(0), head = head->b[0]; } } } int main() { root = (node*)malloc(sizeof(node)); for (int i = 0; i < 3; i++) root->b[i] = NULL, root->flag[i] = 0; int n; cin >> n; insert(0); char a; int num; for (int i = 0; i < n; i++) { int calc = 0; cin >> a >> num; if (a == + ) insert(num); else if (a == - ) del(num); else { ans.clear(); search(num); for (int i = 0; i < ans.size(); i++) calc += (pow(2, 31 - i) * ans[i]); cout << calc << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int count = 0; char k[4]; cin >> k; int a[5]; for (int i = 0; i < 4; i++) { a[i] = k[i] - 0 ; } int b[5]; for (int i = 0; i < 4; i++) { b[i] = a[i]; } while (1) { if (b[3] == 9) { b[3] = 0; if (b[2] == 9) { b[2] = 0; if (b[1] == 9) { b[1] = 0; b[0] = b[0] + 1; } else b[1] = b[1] + 1; } else b[2] = b[2] + 1; } else b[3] = b[3] + 1; int i = 0; for (int v = 0; v < 4; v++) for (int z = v + 1; z < 4; z++) { if (b[v] == b[z]) count++; } if (count == 0) break; else count = 0; } for (int m = 0; m < 4; m++) { cout << b[m]; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
wire Overflow_flag;
wire Underflow_flag;
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
// Collects data from pfl1monitor and pfl2monitor and generated prefeches
// accordingly
//
`include "scmem.vh"
`include "logfunc.h"
module pfmonitor(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
,input I_coretopfm_dec_type coretopfm_dec
,input coretopfm_dec_valid
,output coretopfm_dec_retry
,output I_pfmtocore_pred_type pfmtocore_pred
,output pfmtocore_pred_valid
,input pfmtocore_pred_retry
,input I_coretopfm_retire_type coretopfm_retire
,input coretopfm_retire_valid
,output coretopfm_retire_retry
// /* verilator lint_on UNUSED */
);
logic coretopfm_dec_next_valid;
logic coretopfm_dec_next_retry;
I_coretopfm_dec_type coretopfm_dec_next;
//fflop between coretopfm_decode stage stats and pfmonitor
fflop #(.Size($bits(I_coretopfm_dec_type))) ff_coretopfm_dec (
.clk (clk),
.reset (reset),
.din (coretopfm_dec),
.dinValid (coretopfm_dec_valid),
.dinRetry (coretopfm_dec_retry),
.q (coretopfm_dec_next),
.qValid (coretopfm_dec_next_valid),
.qRetry (coretopfm_dec_next_retry)
);
logic coretopfm_retire_next_valid;
logic coretopfm_retire_next_retry;
I_coretopfm_retire_type coretopfm_retire_next;
//fflop between coretopfm_retire stage stats and pfmonitor
fflop #(.Size($bits(I_coretopfm_retire_type))) ff_coretopfm_retire (
.clk (clk),
.reset (reset),
.din (coretopfm_retire),
.dinValid (coretopfm_retire_valid),
.dinRetry (coretopfm_retire_retry),
.q (coretopfm_retire_next),
.qValid (coretopfm_retire_next_valid),
.qRetry (coretopfm_retire_next_retry)
);
logic pfmtocore_pred_prev_retry;
logic pfmtocore_pred_prev_valid;
I_pfmtocore_pred_type pfmtocore_pred_prev;
//fflop between pfmonitor(pfm predictions) and core
fflop #(.Size($bits(I_pfmtocore_pred_type))) ff_pfmtocore_pred (
.clk (clk),
.reset (reset),
.din (pfmtocore_pred_prev),
.dinValid (pfmtocore_pred_prev_valid),
.dinRetry (pfmtocore_pred_prev_retry),
.q (pfmtocore_pred),
.qValid (pfmtocore_pred_valid),
.qRetry (pfmtocore_pred_retry)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase w/ null_statement as default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000,3'b001: result = 0;
3'b11x: result = 2;
3'b001: result = 1;
default result = 3;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b010
val2 = 3'b010;
if(result !=3)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function
//SINGLE PRECISION PARAMETERS
# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
//# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
Sgf_Multiplication #(.SW(SW+1)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}),
.Data_B_i({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
`timescale 1ns/1ns
module testbench();
localparam APB_DWIDTH = 32;
reg SYSCLK;
reg SYSRSTN;
wire PCLK;
wire PRESETN;
wire [31:0] PADDR;
wire PENABLE;
wire PWRITE;
wire [APB_DWIDTH-1:0] PWDATA;
wire [APB_DWIDTH-1:0] PRDATA;
wire [APB_DWIDTH-1:0] PRDATA_0;
wire [APB_DWIDTH-1:0] PRDATA_1;
wire [15:0] PSEL;
wire [255:0] INTERRUPT;
wire [31:0] GP_OUT;
wire [31:0] GP_IN;
wire FINISHED;
wire FAILED;
wire Logic0 = 1'b0;
wire Logic1 = 1'b1;
// ********************************************************************************
// Clocks and Reset
initial
begin
SYSRSTN <= 1'b0;
#100;
SYSRSTN <= 1'b1;
end
// Clock is 100MHz
always
begin
SYSCLK <= 1'b0;
#5;
SYSCLK <= 1'b1;
#5;
end
// ********************************************************************************
// APB Master
BFM_APB #(.VECTFILE ("user_tb.vec") )
UBFM (.SYSCLK (SYSCLK),
.SYSRSTN (SYSRSTN),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA),
.PREADY (Logic1),
.PSLVERR (Logic0),
.PSEL (PSEL),
.INTERRUPT (INTERRUPT),
.GP_OUT (GP_OUT),
.GP_IN (GP_IN),
.EXT_WR (),
.EXT_RD (),
.EXT_ADDR (),
.EXT_DATA (),
.EXT_WAIT (Logic0),
.CON_ADDR (),
.CON_DATA (),
.CON_RD (Logic0),
.CON_WR (Logic0),
.CON_BUSY (),
.FINISHED (FINISHED),
.FAILED (FAILED)
);
assign PRDATA = ( PSEL[1] ? PRDATA_1 : PRDATA_0) ;
/* #############################################################################
SPIINT Output interrupt
SPISDO Output serial data out (generated by SPI as master)
SPISS[7:0] Output slave select (generated by SPI as master)
SPISCLKO Output shift clock out (generated by SPI as master)
SPISDI Input shift data in (master or slave)
SPIRXAVAIL Output request for data to be read - rx data available
SPITXRFM Output indicates transmit done - ready for more
SPISSI Input slave select (when SPI in slave mode)
SPIOEN Output output enable (when de-asserted output pad for SPISDO tri-stated). This is active when the SPI is writing output data and deactivated when there is not data to write. This signal is active high.
SPIMode Output mode: (when 1, SPI is master, when 0, SPI is slave)
*/
// ********************************************************************************
// SPI Core - Master
wire [7:0] M_SPISS;
CORESPI # (
.APB_DWIDTH (APB_DWIDTH),
.CFG_FRAME_SIZE (4),
.FIFO_DEPTH (4),
.CFG_CLK (2),
.CFG_SPO (1),
.CFG_SPH (1),
.CFG_SPS (0),
.CFG_MODE (0)
)USPIM ( //.TESTMODE (1'b0),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR[6:0]),
.PSEL (PSEL[0]),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA_0),
.SPISSI (M_SPISSI),
.SPISDI (M_SPISDI),
.SPICLKI (M_SPICLKI),
.SPISS (M_SPISS),
.SPISCLKO (M_SPISCLKO),
.SPIOEN (M_SPIOEN),
.SPISDO (M_SPISDO),
.SPIINT (GP_IN[0]),
.SPIRXAVAIL (GP_IN[1]),
.SPITXRFM (GP_IN[2]),
.SPIMODE (GP_IN[3]),
.PREADY (),
.PSLVERR ()
);
// ********************************************************************************
// SPI Core - Master
wire [7:0] S_SPISS;
CORESPI # (
.APB_DWIDTH (APB_DWIDTH),
.CFG_FRAME_SIZE (4),
.FIFO_DEPTH (4),
.CFG_CLK (2),
.CFG_SPO (1),
.CFG_SPH (1),
.CFG_SPS (0),
.CFG_MODE (0)
) USPIS ( //.TESTMODE (1'b0),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR[6:0]),
.PSEL (PSEL[1]),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA_1),
.SPISSI (S_SPISSI),
.SPISDI (S_SPISDI),
.SPICLKI (S_SPICLKI),
.SPISS (S_SPISS),
.SPISCLKO (S_SPISCLKO),
.SPIOEN (S_SPIOEN),
.SPISDO (S_SPISDO),
.SPIINT (GP_IN[8]),
.SPIRXAVAIL (GP_IN[9]),
.SPITXRFM (GP_IN[10]),
.SPIMODE (GP_IN[11]),
.PREADY (),
.PSLVERR ()
);
// *************************************************************************************
// SPI Connectivity
reg [31:0] shiftreg = 32'b000;
always @(posedge M_SPISCLKO)
begin
shiftreg <= { shiftreg[30:0] , (M_SPISDO & M_SPIOEN)};
end
reg nscdata;
always @(negedge M_SPISCLKO)
begin
nscdata <= shiftreg[8];
end
reg mux;
always @(*)
begin
case (GP_OUT[10:8])
3'b000 : mux = M_SPISDO & M_SPIOEN;
3'b001 : mux = M_SPISDO & M_SPIOEN;
3'b010 : mux = nscdata; // 9 clock delay
3'b100 : mux = S_SPISDO & S_SPIOEN;
3'b101 : mux = S_SPISDO & S_SPIOEN;
3'b110 : mux = S_SPISDO & S_SPIOEN;
endcase
end
assign M_SPISDI = mux;
assign S_SPICLKI = M_SPISCLKO;
assign S_SPISSI = M_SPISS[0];
assign S_SPISDI = M_SPISDO & M_SPIOEN;
// For Waveform trace
wire SPICLK = M_SPISCLKO;
wire SPISEL = M_SPISS[0];
wire SPIDATAM = M_SPISDO & M_SPIOEN;
wire SPIDATAS = M_SPISDI;
// *************************************************************************************
// Simple Spy Capture Model
// AS: removed
//reg [7:0] capture = 8'b00;
//reg [7:0] capnext = 8'b00;
//integer bit = 0;
/*
always @(posedge SPICLK)
begin
if (SPISEL==1)
begin
capture <= 8'b00;
bit = 0;
end
else
begin
capnext = { capture[6:0], M_SPISDO };
capture <= capnext;
bit = bit +1;
if (bit==8)
begin
$display("Captured %02d %02x",bit,capnext);
capture <= 8'b00;
bit = 0;
end
end
end
*/
// *************************************************************************************
// PCLK Width Check
// AS: removed, not needed for USER TB
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the encoder
// Import the modules that will be tested for in this testbench
`include "encoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_encoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [14:0] cout;
// Declare "reg" signals: inputs to the DUT
reg [10:0] b;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
ham_15_11_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
b,cout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
b = 11'b11010110000;
$display(b[1]," << b1 b2 >>",b[2]);
$display(b[3]," << b1 b2 >>",b[4]);
// @ t=0,
#1;
b = 11'b11100011100;
#1;
b = 11'b11001110101;
#1;
b = 11'b11110111001;
#1;
b = 11'b11111000010;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
interface my_interface ();
logic [2:0] out2;
logic [2:0] out3;
endinterface: my_interface
module foobar (input [2:0] in2, output [2:0] out2);
endmodule
module foo_autowire_fails (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out2 = out2; // perhaps a namespace collision?
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
module foo_autowire_works (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out3 = out2;
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_BLACKBOX_V
`define SKY130_FD_SC_MS__AND2B_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[100010]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); int ans = 0; int re = 0; for (int i = 0; i < n; i++) { int t = 1; while (a[i + 1] == a[i] && (i < n - 1)) { t += 1; i += 1; } if (i == n - 1) { cout << ans; return 0; } else if (i == n - 2) { cout << ans + 1; return 0; } re = max(re, i + 1); if (t < (n - re)) { re += t; ans += t; } else if (t == n - re) { ans += t; cout << ans; return 0; } else { ans += (n - re); cout << ans; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cin.tie(0), cout.tie(0), cout.precision(15); int t; cin >> t; while (t--) { int n, x; set<int> s; cin >> n; for (int i = int(0); i < int(n); i++) { cin >> x; s.insert(x); } cout << s.size() << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_BLACKBOX_V
|
//==================================================================================================
// Filename : Testbench_simpleAdders.v
// Created On : 2016-11-18 02:54:20
// Last Modified : 2016-11-20 19:46:34
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : Testbench for different approximate
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Testbench_Multiplier();
parameter PERIOD = 10;
parameter W = 24;
reg clk;
reg rst;
reg enable;
//Oper_Start_in signals
reg [W-1:0] in1;
reg [W-1:0] in2;
wire [2*W-1:0] res;
Simple_KOA_STAGE_1_approx #(
.SW(W)
) inst_Simple_KOA_STAGE_1 (
.clk (clk),
.rst (rst),
.load_b_i (enable),
.Data_A_i (in1),
.Data_B_i (in2),
.sgf_result_o (res)
);
`ifdef ACAIN8Q5
localparam STRINGHEX = "ResultadosACAIN8Q5HEX.txt";
localparam STRINGDEC = "ResultadosACAIN8Q5DEC.txt";
`endif
`ifdef ACAIIN8Q4
localparam STRINGHEX = "ResultadosACAIIN8Q4HEX.txt";
localparam STRINGDEC = "ResultadosACAIIN8Q4DEC.txt";
`endif
`ifdef GDAN8M8P1
localparam STRINGHEX = "ResultadosGDAN8M8P1HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P1DEC.txt";
`endif
`ifdef GDAN8M8P2
localparam STRINGHEX = "ResultadosGDAN8M8P2HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P2DEC.txt";
`endif
`ifdef GDAN8M8P3
localparam STRINGHEX = "ResultadosGDAN8M8P3HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P3DEC.txt";
`endif
`ifdef GDAN8M8P4
localparam STRINGHEX = "ResultadosGDAN8M8P4HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P4DEC.txt";
`endif
`ifdef GDAN8M8P5
localparam STRINGHEX = "ResultadosGDAN8M8P5HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P5DEC.txt";
`endif
`ifdef GDAN8M8P6
localparam STRINGHEX = "ResultadosGDAN8M8P6HEX.txt";
localparam STRINGDEC = "ResultadosGDAN8M8P6DEC.txt";
`endif
`ifdef GeArN8R1P1
localparam STRINGHEX = "ResultadosGeArN8R1P1HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P1DEC.txt";
`endif
`ifdef GeArN8R1P2
localparam STRINGHEX = "ResultadosGeArN8R1P2HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P2DEC.txt";
`endif
`ifdef GeArN8R1P3
localparam STRINGHEX = "ResultadosGeArN8R1P3HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P3DEC.txt";
`endif
`ifdef GeArN8R1P4
localparam STRINGHEX = "ResultadosGeArN8R1P4HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P4DEC.txt";
`endif
`ifdef GeArN8R1P5
localparam STRINGHEX = "ResultadosGeArN8R1P5HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P5DEC.txt";
`endif
`ifdef GeArN8R1P6
localparam STRINGHEX = "ResultadosGeArN8R1P6HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R1P6DEC.txt";
`endif
`ifdef GeArN8R2P2
localparam STRINGHEX = "ResultadosGeArN8R2P2HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R2P2DEC.txt";
`endif
`ifdef GeArN8R2P4
localparam STRINGHEX = "ResultadosGeArN8R2P4HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R2P4DEC.txt";
`endif
`ifdef GeArN8R4P1
localparam STRINGHEX = "ResultadosGeArN8R4P1HEX.txt";
localparam STRINGDEC = "ResultadosGeArN8R4P1DEC.txt";
`endif
`ifdef LOALPL4
localparam STRINGHEX = "ResultadosLOALPL4HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL4DEC.txt";
`endif
`ifdef LOALPL5
localparam STRINGHEX = "ResultadosLOALPL5HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL5DEC.txt";
`endif
`ifdef LOALPL6
localparam STRINGHEX = "ResultadosLOALPL6HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL6DEC.txt";
`endif
`ifdef LOALPL7
localparam STRINGHEX = "ResultadosLOALPL7HEX.txt";
localparam STRINGDEC = "ResultadosLOALPL7DEC.txt";
`endif
`ifdef NADA
localparam STRINGHEX = "ResultadosNADAHEX.txt";
localparam STRINGDEC = "ResultadosNADADEC.txt";
`endif
integer FileResHex;
integer FileResDec;
reg [63:0] ValTeorico;
reg [63:0] Error = 0;
reg [63:0] RESULT;
real floatERROR = 0;
real sumErrors = 0;
initial begin
// Initialize Inputs
// $vcdpluson;
clk = 0;
in1 = 0;
in2 = 0;
rst = 1;
enable = 0;
#10;
rst = 0;
enable = 1;
#100;
FileResHex = $fopen(STRINGHEX,"w");
FileResDec = $fopen(STRINGDEC,"w");
runMultiplier(FileResHex,FileResDec,(200000));
$finish;
// $vcdplusclose;
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task runMultiplier;
input integer ResultsFileH;
input integer ResultsFileD;
input integer Vector_size;
begin
$fwrite(ResultsFileH, "Entrada 1, Entrada 2, Resultado, Teorico, Diff\n");
$fwrite(ResultsFileD, "Entrada 1, Entrada 2, Resultado, Teorico , Diff , Reltiv Error\n");
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
#4;
in1 = $random;
in2 = $random;
#2;
ValTeorico = in1 * in2;
RESULT = res;
if (RESULT > ValTeorico) begin
Error = (RESULT - ValTeorico);
end else begin
Error = (ValTeorico - RESULT);
end
floatERROR = ($bitstoreal(Error)*$itor(100))/$bitstoreal(ValTeorico);
sumErrors = sumErrors + floatERROR;
$fwrite(ResultsFileH, "%h, %h, %h, %h, %h\n", in1, in2, res, ValTeorico, Error);
$fwrite(ResultsFileD, "%d, %d, %d, %d, %d, %f\n", in1, in2, res, ValTeorico, Error, floatERROR);
end
$fwrite(ResultsFileD, "La suma de los errores es > %f\n", sumErrors);
$fwrite(ResultsFileD, "El numero de elementos es > %f\n", $itor(Vector_size));
$fwrite(ResultsFileD, "La media del error es> %f\n", sumErrors/$itor(Vector_size));
$fclose(ResultsFileH);
$fclose(ResultsFileD);
end
endtask
endmodule
|
`include "defines.v"
module mem(
//input
//MemControl
input wire[31:0] memData_i,
//MEM-WB
input wire[31:0] writeData_i,
//MEM
input wire[31:0] storeData_i,
input wire[2:0] memOp_i,
//Exception
input wire insValid_i,
input wire[31:0] insAddr_i,
input wire inDelaySlot_i,
input wire[3:0] exception_i,
input wire[31:0] badVAddr_i,
input wire[3:0] exceptionMC_i,
input wire timeInt_i,
input wire serialInt_i,
//WB
input wire writeReg_i,
input wire[4:0] writeRegAddr_i,
input wire[31:0] writeDataHi_i,
input wire[31:0] writeDataLo_i,
input wire writeRegHiLo_i,
input wire writeCP0_i,
input wire[4:0] writeCP0Addr_i,
//CP0
input wire[31:0] cp0_Status_i,
input wire[31:0] cp0_EntryHi_i,
input wire[31:0] cp0_Ebase_i,
input wire[31:0] cp0_EPC_i,
//output
//MemControl
output reg[2:0] memOp_o,
output reg[31:0] storeData_o,
output reg[31:0] memAddr_o,
//WB
output reg writeReg_o,
output reg[4:0] writeRegAddr_o,
output reg[31:0] writeData_o,
output reg[31:0] writeDataHi_o,
output reg[31:0] writeDataLo_o,
output reg writeRegHiLo_o,
output reg writeCP0_o,
output reg[4:0] writeCP0Addr_o,
//Exception Control
output reg flush_o,
output reg[31:0] excAddr_o,
//Exception
output reg[3:0] exception_o,
output reg inDelaySlot_o,
output reg[31:0] insAddr_o,
output reg[31:0] badVAddr_o
);
wire EXL = cp0_Status_i[`Status_EXL];
wire ERL = cp0_Status_i[`Status_ERL];
wire UM = cp0_Status_i[`Status_UM];
wire BEV = cp0_Status_i[`Status_BEV];
wire IE = cp0_Status_i[`Status_IE];
wire[7:0] IM = cp0_Status_i[`Status_IM];
wire isUserMode = (UM == 1'b1 && EXL == 1'b0 && ERL == 1'b0);
wire[7:0] pendingInt = {timeInt_i, 2'h0, serialInt_i, 4'h0};
wire[7:0] intVector = IM & pendingInt;
wire isIntEnable = (IE == 1'b1 && EXL == 1'b0 && ERL == 1'b0 && (|intVector) == 1'b1 && insValid_i == `Enable);
//Data Pass
always @(*) begin
//Exception
inDelaySlot_o = inDelaySlot_i;
insAddr_o = insAddr_i;
//WB
writeRegAddr_o = writeRegAddr_i;
writeDataHi_o = writeDataHi_i;
writeDataLo_o = writeDataLo_i;
writeCP0Addr_o = writeCP0Addr_i;
end
//Pre Exception
reg[3:0] preException;
always @(*) begin
if (isIntEnable == `Enable) begin
//INT
preException = `EXC_INT;
end else if (isUserMode == `Enable && (exception_i == `EXC_ERET || exception_i == `EXC_TLBWI || exception_i == `EXC_MC0)) begin
//CpU
preException = `EXC_CPU;
end else begin
preException = exception_i;
end
end
//Memory Operation
//memOp
reg[2:0] memOp;
always @(*) begin
if (preException == `EXC_NONE) begin
memOp = memOp_i;
end else begin
memOp = `MEM_NOP_OP;
end
end
//Data Fetch
wire[31:0] signData = {{24{memData_i[7]}}, memData_i[7:0]};
wire[31:0] zeroData = {24'h0, memData_i[7:0]};
reg[31:0] writeData;
always @(*) begin
//MMU
memOp_o = memOp;
storeData_o = `ZeroWord;
memAddr_o = `ZeroWord;
//Data
writeData = `ZeroWord;
case (memOp)
`MEM_NOP_OP: begin
//Data
writeData = writeData_i;
end
`MEM_LB_OP: begin
//MMU
memAddr_o = writeData_i;
//Data
writeData = signData;
end
`MEM_LBU_OP: begin
//MMU
memAddr_o = writeData_i;
//Data
writeData = zeroData;
end
`MEM_LW_OP: begin
//MMU
memAddr_o = writeData_i;
//Data
writeData = memData_i;
end
`MEM_SB_OP: begin
//MMU
storeData_o = storeData_i;
memAddr_o = writeData_i;
end
`MEM_SW_OP: begin
//MMU
storeData_o = storeData_i;
memAddr_o = writeData_i;
end
default: begin
end
endcase
end
//Post Exception
always @(*) begin
if (preException != `EXC_NONE) begin
exception_o = preException;
badVAddr_o = badVAddr_i;
end else begin
//Use MC Exception
//ADE, TLB, MCHECK
exception_o = exceptionMC_i;
badVAddr_o = writeData_i;
end
end
//Control-signal
always @(*) begin
if (exception_o == `EXC_NONE || exception_o == `EXC_MC0 || exception_o == `EXC_TLBWI) begin
//WB
writeReg_o = writeReg_i;
writeData_o = writeData;
writeRegHiLo_o = writeRegHiLo_i;
writeCP0_o = writeCP0_i;
//Exception Control
flush_o = `Disable;
excAddr_o = `ZeroWord;
end else begin
//Exception happeded
//WB
writeReg_o = `Disable;
writeData_o = {24'h0, intVector};
writeRegHiLo_o = `Disable;
writeCP0_o = `Disable;
//WB
flush_o = `Enable;
if (exception_o == `EXC_ERET) begin
excAddr_o = cp0_EPC_i;
end else begin
excAddr_o = cp0_Ebase_i;
end
end
end
endmodule
|
`timescale 1 ns / 1 ps
module testbench;
reg clk = 1;
always #5 clk = ~clk;
wire LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8;
wire [7:0] LEDS;
assign LEDS = {LED8, LED7, LED6, LED5, LED4, LED3, LED2, LED1};
wire [7:0] PCdebug;
wire dummy;
reg rdummy;
reg rst;
always @(posedge clk) rdummy <= dummy;
reg [31:0] clkcounter;
reg [7:0] prev_LED;
always @(posedge clk)
if (rst) clkcounter <= clkcounter + 1; else clkcounter <= 0;
top soc ( .sys_clk_in(clk),
.LED1(LED1),
.LED2(LED2),
.LED3(LED3),
.LED4(LED4),
.LED5(LED5),
.LED6(LED6),
.LED7(LED7),
.LED8(LED8),
.RX(1'b0),
.TX(dummy),
.PCdebug1(PCdebug[0]),
.PCdebug2(PCdebug[1]),
.PCdebug3(PCdebug[2]),
.PCdebug4(PCdebug[3]),
.PCdebug5(PCdebug[4]),
.PCdebug6(PCdebug[5]),
.PCdebug7(PCdebug[6]),
.PCdebug8(PCdebug[7]),
.sys_reset(rst)
);
initial begin
rst <= 0;
prev_LED <= 0;
repeat (50) @(posedge clk);
rst <= 1;
end
always @(posedge clk)
if (rst) begin
$display(">>> PC=%d", PCdebug);
if (LEDS != prev_LED) begin
$display("LED=%b @ %d", LEDS, clkcounter);
prev_LED <= LEDS;
end
if (clkcounter > 1000) $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_TB_V
`define SKY130_FD_SC_HDLL__A31O_TB_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_TB_V
|
timeunit 10us / 10us;
module fast_g (out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast_g
`timescale 100us / 1us
// These will be ignored since a `timescale was already given.
timeunit 10us/10us;
module slow (out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // slow
module fast (out);
timeunit 10us/1us;
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast
module saf(out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // saf
`timescale 1us / 1us
module main;
reg pass;
wire slow, fast, fast_g, saf;
slow m1 (slow);
fast_g m2 (fast_g);
fast m3 (fast);
saf m4 (saf);
initial begin
pass = 1'b1;
#9;
if (slow !== 1'b0) begin
$display("FAILED: slow at 9us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 9us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b0) begin
$display("FAILED: fast at 9us, expected 1'b0, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b0) begin
$display("FAILED: fast_g at 9us, expected 1'b0, got %b.", fast_g);
pass = 1'b0;
end
#2 // 11us
if (slow !== 1'b0) begin
$display("FAILED: slow at 11us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 11us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 11us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 11us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
#88 // 99 us
if (slow !== 1'b0) begin
$display("FAILED: slow at 99us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 99us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 99us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 99us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
#2 // 101 us
if (slow !== 1'b1) begin
$display("FAILED: slow at 101us, expected 1'b1, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b1) begin
$display("FAILED: saf at 101us, expected 1'b1, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 101us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 101us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
if (pass) $display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 100010, LOG = 20; long long n, m, k, u, v, x, y, t, l, r, ans; long long S[MAXN], M[MAXN], R[MAXN], D[MAXN]; int Mn[MAXN << 2], Mx[MAXN << 2], lazy[MAXN << 2]; vector<pair<int, int> > seg[MAXN << 2]; vector<long long> ps1[MAXN << 2], ps2[MAXN << 2]; void Build(int id, int tl, int tr) { if (tr - tl == 1) { seg[id].push_back({D[tl], tl}); ps1[id].push_back(0); ps1[id].push_back(R[tl]); ps2[id].push_back(M[tl]); ps2[id].push_back(0); return; } int mid = (tl + tr) >> 1; Build(id << 1, tl, mid); Build(id << 1 | 1, mid, tr); seg[id].resize(tr - tl); ps1[id].resize(tr - tl + 1, 0); ps2[id].resize(tr - tl + 1, 0); merge(seg[id << 1].begin(), seg[id << 1].end(), seg[id << 1 | 1].begin(), seg[id << 1 | 1].end(), seg[id].begin()); ps1[id][0] = ps2[id][tr - tl] = 0; for (int i = 0; i < tr - tl; i++) ps1[id][i + 1] = ps1[id][i] + M[seg[id][i].second]; for (int i = tr - tl; i; i--) ps2[id][i - 1] = ps2[id][i] + R[seg[id][i - 1].second]; } void add_lazy(int id, int val) { lazy[id] = Mn[id] = Mx[id] = val; } void shift(int id) { if (!lazy[id]) return; add_lazy(id << 1, lazy[id]); add_lazy(id << 1 | 1, lazy[id]); lazy[id] = 0; } void query(int id, int tl, int tr, int l, int r, int t) { if (tr <= l || r <= tl) return; if (l <= tl && tr <= r && Mn[id] == Mx[id] && (Mn[id] != -1 || tr - tl == 1)) { long long time = t - Mn[id]; int shit = (Mn[id] == -1); add_lazy(id, t); if (tr - tl == 1) { time -= shit; ans += min(M[tl], S[tl] + R[tl] * time); S[tl] = 0; return; } int pos = upper_bound(seg[id].begin(), seg[id].end(), pair<int, int>(time, inf + 1)) - seg[id].begin(); ans += ps1[id][pos]; ans += ps2[id][pos] * time; return; } shift(id); int mid = (tl + tr) >> 1; query(id << 1, tl, mid, l, r, t); query(id << 1 | 1, mid, tr, l, r, t); Mn[id] = min(Mn[id << 1], Mn[id << 1 | 1]); Mx[id] = max(Mx[id << 1], Mx[id << 1 | 1]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(Mn, -1, sizeof(Mn)); memset(Mx, -1, sizeof(Mx)); cin >> n; for (int i = 1; i <= n; i++) cin >> S[i] >> M[i] >> R[i], D[i] = (R[i] ? (M[i] + R[i] - 1) / R[i] : inf); Build(1, 1, n + 1); cin >> m; while (m--) { cin >> t >> l >> r; ans = 0; query(1, 1, n + 1, l, r + 1, t); cout << ans << n ; } return 0; } |
// hps_design_SMP_CORE.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_SMP_CORE #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [7:0] mem_dq, // .mem_dq
inout wire mem_dqs, // .mem_dqs
inout wire mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
hps_design_SMP_CORE_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY) // .rready
);
hps_design_SMP_CORE_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string presidents[41] = { , Washington , Adams , Jefferson , Madison , Monroe , Adams , Jackson , Van Buren , Harrison , Tyler , Polk , Taylor , Fillmore , Pierce , Buchanan , Lincoln , Johnson , Grant , Hayes , Garfield , Arthur , Cleveland , Harrison , Cleveland , McKinley , Roosevelt , Taft , Wilson , Harding , Coolidge , Hoover , Roosevelt , Truman , Eisenhower , Kennedy , Johnson , Nixon , Ford , Carter , Reagan , }; int main() { int n; cin >> n; cout << presidents[n] << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_1_V
`define SKY130_FD_SC_LP__O2BB2A_1_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_SYMBOL_V
`define SKY130_FD_SC_LS__HA_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_SYMBOL_V
|
//======================================================================
//
// fltcpu_alu.v
// ----------------
// Arithmetic and Logic Unit (ALU) in the cpu. This is where the
// operations are performed.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fltcpu_alu(
input wire clk,
input wire reset_n,
input wire [5 : 0] opcode,
input wire [31 : 0] src0_data,
input wire [31 : 0] src1_data,
output wire [31 : 0] dst_data,
output wire eq_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam OPCODE_AND = 6'h04;
localparam OPCODE_OR = 6'h05;
localparam OPCODE_XOR = 6'h06;
localparam OPCODE_NOT = 6'h07;
localparam OPCODE_ADD = 6'h08;
localparam OPCODE_ADDI = 6'h09;
localparam OPCODE_SUB = 6'h0a;
localparam OPCODE_SUBI = 6'h0b;
localparam OPCODE_MUL = 6'h0c;
localparam OPCODE_MULI = 6'h0d;
localparam OPCODE_ASL = 6'h10;
localparam OPCODE_ROL = 6'h11;
localparam OPCODE_ASR = 6'h12;
localparam OPCODE_ROR = 6'h13;
localparam OPCODE_CMP = 6'h30;
localparam OPCODE_CMPI = 6'h31;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_dst_data;
reg tmp_eq_data;
wire [4 : 0] shamt;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign dst_data = tmp_dst_data;
assign eq_data = tmp_eq_data;
assign shamt = src1_data[4 : 0];
//----------------------------------------------------------------
// alu
//
// The alu logic.
//----------------------------------------------------------------
always @*
begin : alu
// Default assignments
tmp_dst_data = 32'h0;
tmp_eq_data = 0;
case (opcode)
OPCODE_AND:
tmp_dst_data = src0_data & src1_data;
OPCODE_OR:
tmp_dst_data = src0_data | src1_data;
OPCODE_XOR:
tmp_dst_data = src0_data ^ src1_data;
OPCODE_NOT:
tmp_dst_data = ~src0_data;
OPCODE_ADD, OPCODE_ADDI:
tmp_dst_data = src0_data + src1_data;
OPCODE_SUB, OPCODE_SUBI:
tmp_dst_data = src0_data - src1_data;
OPCODE_MUL:
tmp_dst_data = src0_data * src1_data;
OPCODE_ASL:
tmp_dst_data = src0_data <<< shamt;
OPCODE_ROL:
tmp_dst_data = {(src0_data <<< shamt),
(src0_data >>> (32 - shamt))};
OPCODE_ASR:
tmp_dst_data = src0_data >>> shamt;
OPCODE_ROR:
tmp_dst_data = {(src0_data >>> shamt),
(src0_data <<< (32 - shamt))};
OPCODE_CMP, OPCODE_CMPI:
tmp_eq_data = src0_data == src1_data;
default:
begin
end
endcase // case (opcode)
end // alu
endmodule // fltcpu_alu
//======================================================================
// EOF fltcpu_alu.v
//======================================================================
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_mask_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* CLOCK_SIGNAL = "yes", PERIOD = "10", WAVEFORM = "bad value" *)
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int expo(long long int base, long long int exponent, long long int mod) { long long int ans = 1; while (exponent != 0) { if (exponent & 1) ans = (1LL * ans * base) % mod; base = (1LL * base * base) % mod; exponent >>= 1; } return ans % mod; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { long long int x, n; cin >> x >> n; long long int sx = sqrt(x) + 10; map<long long int, long long int> ma; for (long long int i = 2; i <= sx; i++) { while (x % i == 0) { x = x / i; ma[i]++; } } if (x != 1) ma[x]++; vector<long long int> v; for (auto i : ma) v.push_back(i.first); long long int ans = 1; for (auto i : v) { long long int p = i; long long int e = 0; long long int nn = n; for (long long int j = 1; true; j++) { e += nn / p; e = e % (1000000007 - 1); nn = nn / p; if (nn == 0) break; } long long int tmp = expo(i, e % (1000000007 - 1), 1000000007); ans = (ans * tmp) % 1000000007; } cout << ans; } return 0; } |
`define ADDER_WIDTH 004
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/02/2013 08:41:31 PM
// Design Name:
// Module Name: maxi_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module maxi_controller # (
parameter M_AXI_TDATA_WIDTH = 32,
parameter M_AXI_ADDR_WIDTH = 32,
parameter OUTSTANDING_READS = 5,
parameter RELAXED_ORDERING = 1'b0,
parameter BAR0AXI = 64'h00000000,
parameter BAR1AXI = 64'h00000000,
parameter BAR2AXI = 64'h00000000,
parameter BAR3AXI = 64'h00000000,
parameter BAR4AXI = 64'h00000000,
parameter BAR5AXI = 64'h00000000,
parameter BAR0SIZE = 12,
parameter BAR1SIZE = 12,
parameter BAR2SIZE = 12,
parameter BAR3SIZE = 12,
parameter BAR4SIZE = 12,
parameter BAR5SIZE = 12
) (
input m_axi_aclk,
input m_axi_aresetn,
output [M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output [2 : 0] m_axi_awprot,
output m_axi_awvalid,
input m_axi_awready,
output [M_AXI_TDATA_WIDTH-1 : 0] m_axi_wdata,
output [M_AXI_TDATA_WIDTH/8-1 : 0] m_axi_wstrb,
output m_axi_wvalid,
input m_axi_wready,
input [1 : 0] m_axi_bresp,
input m_axi_bvalid,
output m_axi_bready,
output [M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr,
output [2 : 0] m_axi_arprot,
output m_axi_arvalid,
input m_axi_arready,
input [M_AXI_TDATA_WIDTH-1 : 0] m_axi_rdata,
input [1 : 0] m_axi_rresp,
input m_axi_rvalid,
output m_axi_rready,
//Memory Request TLP Info
input mem_req_valid,
output mem_req_ready,
input [2:0] mem_req_bar_hit,
input [31:0] mem_req_pcie_address,
input [3:0] mem_req_byte_enable,
input mem_req_write_readn,
input mem_req_phys_func,
input [31:0] mem_req_write_data,
//Completion Data Coming back
output axi_cpld_valid,
input axi_cpld_ready,
output [31:0] axi_cpld_data
);
wire mem_req_ready_r;
wire mem_req_ready_w;
wire mem_req_valid_wr;
generate
if ( RELAXED_ORDERING == 1'b1 ) begin: RELAXED_ORDERING_ENABLED
assign mem_req_ready = mem_req_write_readn ? mem_req_ready_w : mem_req_ready_r;
assign mem_req_valid_wr = mem_req_valid ;
end else begin: RELAXED_ORDERING_DISABLED
assign mem_req_ready = mem_req_ready_w & mem_req_ready_r;
assign mem_req_valid_wr = (mem_req_ready_w & mem_req_ready_r) ? mem_req_valid: 1'b0 ;
end
endgenerate
axi_read_controller # (
.M_AXI_TDATA_WIDTH ( M_AXI_TDATA_WIDTH ),
.OUTSTANDING_READS ( OUTSTANDING_READS ),
.BAR0AXI ( BAR0AXI ),
.BAR1AXI ( BAR1AXI ),
.BAR2AXI ( BAR2AXI ),
.BAR3AXI ( BAR3AXI ),
.BAR4AXI ( BAR4AXI ),
.BAR5AXI ( BAR5AXI ),
.BAR0SIZE ( BAR0SIZE ),
.BAR1SIZE ( BAR1SIZE ),
.BAR2SIZE ( BAR2SIZE ),
.BAR3SIZE ( BAR3SIZE ),
.BAR4SIZE ( BAR4SIZE ),
.BAR5SIZE ( BAR5SIZE )
) axi_read_controller (
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready),
//Memory Request TLP Info
.mem_req_valid ( mem_req_valid_wr ),
.mem_req_ready ( mem_req_ready_r ),
.mem_req_bar_hit ( mem_req_bar_hit ),
.mem_req_pcie_address ( mem_req_pcie_address ),
.mem_req_byte_enable ( mem_req_byte_enable ),
.mem_req_write_readn ( mem_req_write_readn ),
.mem_req_phys_func ( mem_req_phys_func ),
.mem_req_write_data ( mem_req_write_data ),
//Completion TLP Info
.axi_cpld_valid ( axi_cpld_valid ),
.axi_cpld_ready ( axi_cpld_ready ),
.axi_cpld_data ( axi_cpld_data )
);
axi_write_controller #(
.M_AXI_TDATA_WIDTH ( M_AXI_TDATA_WIDTH ),
.BAR0AXI ( BAR0AXI ),
.BAR1AXI ( BAR1AXI ),
.BAR2AXI ( BAR2AXI ),
.BAR3AXI ( BAR3AXI ),
.BAR4AXI ( BAR4AXI ),
.BAR5AXI ( BAR5AXI ),
.BAR0SIZE ( BAR0SIZE ),
.BAR1SIZE ( BAR1SIZE ),
.BAR2SIZE ( BAR2SIZE ),
.BAR3SIZE ( BAR3SIZE ),
.BAR4SIZE ( BAR4SIZE ),
.BAR5SIZE ( BAR5SIZE )
) axi_write_controller (
.m_axi_aclk ( m_axi_aclk ),
.m_axi_aresetn ( m_axi_aresetn ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awprot ( m_axi_awprot ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awready ( m_axi_awready ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wready ( m_axi_wready ),
.m_axi_bresp ( m_axi_bresp ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_bready ( m_axi_bready ),
//Memory Request TLP Info
.mem_req_valid ( mem_req_valid_wr ),
.mem_req_ready ( mem_req_ready_w ),
.mem_req_bar_hit ( mem_req_bar_hit ),
.mem_req_pcie_address ( mem_req_pcie_address ),
.mem_req_byte_enable ( mem_req_byte_enable ),
.mem_req_write_readn ( mem_req_write_readn ),
.mem_req_phys_func ( mem_req_phys_func ),
.mem_req_write_data ( mem_req_write_data )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int maxN = 131079; inline int pls(int x, int y) { return (x + y) % mod; } inline int mns(int x, int y) { return pls(x, mod - y); } inline int mul(int x, int y) { return 1LL * x * y % mod; } inline void Add(int &x, int y) { x = pls(x, y); } inline void Mul(int &x, int y) { x = mul(x, y); } inline void Minus(int &x, int y) { x = mns(x, y); } inline int pwr(int x, int tms) { int res = 1; for (; tms > 0; tms >>= 1) { if (tms & 1) Mul(res, x); Mul(x, x); } return res; } inline int inv(int x) { return pwr(x, mod - 2); } template <class T> inline T rd() { bool f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = 0; T x = 0; for (; isdigit(c); c = getchar()) x = x * 10 + c - 48; return f ? x : -x; } int n; int g[maxN]; int f[2][2][maxN]; int h[2][2][maxN]; namespace poly { int g[2], pwg[2][maxN]; int L, ivL, rev[maxN]; void init() { g[1] = inv(g[0] = 3); for (int i = 2; i < maxN; i <<= 1) { pwg[0][i] = pwr(g[0], (mod - 1) / i); pwg[1][i] = pwr(g[1], (mod - 1) / i); } } void getL(int len) { for (L = 2; L <= len; L <<= 1) ; ivL = inv(L); for (int i = (0), _ = (L); i < _; ++i) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) ? (L >> 1) : 0); } inline void cpy(int *a, int *b, int len) { for (int i = (0), _ = (len); i <= _; ++i) a[i] = b[i]; } inline void clr(int *a, int l, int r) { for (int i = (l), _ = (r); i <= _; ++i) a[i] = 0; } inline void mov(int *a, int *b, int len) { for (int i = (0), _ = (L); i < _; ++i) a[i] = (i <= len) ? b[i] : 0; } void NTT(int *a, int kd) { int i, j, k, u, v, W, Wn; for (int i = (0), _ = (L); i < _; ++i) if (i < rev[i]) swap(a[i], a[rev[i]]); for (i = 2; i <= L; i <<= 1) for (Wn = pwg[kd][i], j = 0; j < L; j += i) for (W = 1, k = j; k < j + i / 2; ++k, Mul(W, Wn)) u = a[k], v = mul(a[k + i / 2], W), a[k] = pls(u, v), a[k + i / 2] = mns(u, v); if (kd) for (int i = (0), _ = (L); i < _; ++i) Mul(a[i], ivL); } void conv(int *A, int *B, int *C, int n, int m, int lim) { static int a[maxN], b[maxN]; getL(n + m); mov(a, A, n), mov(b, B, m); NTT(a, 0), NTT(b, 0); for (int i = (0), _ = (L); i < _; ++i) Mul(a[i], b[i]); NTT(a, 1); cpy(C, a, lim); } void conv2(int *A, int *C, int n, int lim) { static int a[maxN]; getL(n + n); mov(a, A, n); NTT(a, 0); for (int i = (0), _ = (L); i < _; ++i) Mul(a[i], a[i]); NTT(a, 1); cpy(C, a, lim); } void Inv(int *A, int *X, int n) { static int a[maxN], b[maxN]; if (n == 0) { X[0] = inv(A[0]); return; } int mid = n >> 1; Inv(A, a, mid), clr(a, mid + 1, n); conv2(a, b, mid, n); conv(b, A, b, n, n, n); for (int i = (0), _ = (n); i <= _; ++i) X[i] = mns(pls(a[i], a[i]), b[i]); } } // namespace poly int calc(int a, int b) { return pls(pls(pls(mul(f[0][0][a], h[0][0][b]), mul(f[0][1][a], h[1][0][b])), mul(f[1][0][a], h[0][1][b])), mul(f[1][1][a], h[1][1][b])); } void calc_h(int L, int R) { static int a[maxN], b[maxN]; if (L == R) { for (int l = (0), _ = (1); l <= _; ++l) for (int r = (0), _ = (1); r <= _; ++r) Add(h[l][r][L], f[l][r][L]); return; } int M = (L + R) >> 1; calc_h(L, M); for (int l = (0), _ = (1); l <= _; ++l) for (int m = (0), _ = (1); m <= _; ++m) for (int r = (0), _ = (1); r <= _; ++r) { for (int i = (L), _ = (M); i <= _; ++i) a[i - L] = h[l][m][i]; for (int i = (1), _ = (R - L); i <= _; ++i) b[i] = f[m][r][i - 1]; b[0] = 0; poly::conv(a, b, a, M - L, R - L, R - L); for (int i = (M + 1), _ = (R); i <= _; ++i) Add(h[l][r][i], a[i - L]); } calc_h(M + 1, R); } int main() { poly::init(); n = rd<int>(); g[0] = 1, g[2] = g[4] = mod - 1; poly::Inv(g, g, n); for (int i = (0), _ = (n); i <= _; ++i) { Add(f[0][0][i], g[i]); Add(f[0][1][i + 1], g[i]); Add(f[1][0][i + 1], g[i]); Add(f[1][1][i + 2], g[i]); } for (int i = (0), _ = (n); i <= _; ++i) for (int l = (0), _ = (1); l <= _; ++l) for (int r = (0), _ = (1); r <= _; ++r) Mul(f[l][r][i], mul(i, i)); calc_h(0, n); int res = 0; for (int i = (2), _ = (n); i <= _; ++i) Add(res, mul(i - 1, calc(i - 2, n - i))); Add(res, mul(n, pls(f[0][0][n - 1], f[1][1][n - 1]))); printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; #define SPEED ios::sync_with_stdio(false); cin.tie(0); cout.tie(0) #define fileio freopen( in.in , r , stdin),freopen( out.out , w , stdout); #define ll long long #define int long long #define FF first #define SS second #define mp make_pair #define pb push_back #define pii pair<ll,ll> #define pll pair<long long,long long> #define sd(x) scanf( %d ,&x) #define slld(x) scanf( %lld ,&x) #define pd(x) prllf( %d n ,x) #define plld(x) prllf( %lld n ,x) #define pss prllf #define MOD 1000000007 #define eps 0.00001 #define endl n #define debug(n1) cout<<n1<<endl ll n,k,s[1005],e[1005],c[1005]; bool y[1005]; const ll INF = 1e17+5; int mm[100005]; vector<int>temp[100005]; struct MinimumCostMaximumFlow { typedef ll Index; typedef ll Flow; typedef ll Cost; static const Flow InfCapacity = INF; struct Edge { Index to; Index rev; Flow capacity; Cost cost; }; vector<vector<Edge> > g; void init(Index n) { g.assign(n, vector<Edge>()); } void addEdge(bool inv,Index i, Index j, Flow capacity = InfCapacity, Cost cost = Cost() ) { Edge e, f; e.to = j, f.to = i; e.capacity = capacity, f.capacity = 0; e.cost = cost, f.cost = -cost; if(inv) { temp[i].push_back(mm[i]); } mm[i]++; mm[j]++; g[i].push_back(e); g[j].push_back(f); g[i].back().rev = (Index)g[j].size() - 1; g[j].back().rev = (Index)g[i].size() - 1; } void addB(Index i, Index j, Flow capacity = InfCapacity, Cost cost = Cost()) { addEdge(0,i, j, capacity, cost); addEdge(0,j, i, capacity, cost); } pair<Cost, Flow> minimumCostMaximumFlow(Index s, Index t, Flow f = InfCapacity, bool useSPFA = false) { ll n = g.size(); vector<Cost> dist(n); vector<Index> prev(n); vector<Index> prevEdge(n); pair<Cost, Flow> total = make_pair(0, 0); vector<Cost> potential(n); while(f > 0) { fill(dist.begin(), dist.end(), INF); if(useSPFA || total.second == 0) { deque<Index> q; q.push_back(s); dist[s] = 0; vector<bool> inqueue(n); while(!q.empty()) { Index i = q.front(); q.pop_front(); inqueue[i] = false; for(Index ei = 0; ei < (Index)g[i].size(); ei ++) { const Edge &e = g[i][ei]; Index j = e.to; Cost d = dist[i] + e.cost; if(e.capacity > 0 && d < dist[j]) { if(!inqueue[j]) { inqueue[j] = true; q.push_back(j); } dist[j] = d; prev[j] = i; prevEdge[j] = ei; } } } } else { vector<bool> vis(n); priority_queue<pair<Cost, Index> > q; q.push(make_pair(-0, s)); dist[s] = 0; while(!q.empty()) { Index i = q.top().second; q.pop(); if(vis[i]) continue; vis[i] = true; for(Index ei = 0; ei < (Index)g[i].size(); ei ++) { const Edge &e = g[i][ei]; if(e.capacity <= 0) continue; Index j = e.to; Cost d = dist[i] + e.cost + potential[i] - potential[j]; if(dist[j] > d) { dist[j] = d; prev[j] = i; prevEdge[j] = ei; q.push(make_pair(-d, j)); } } } } if(dist[t] == INF) break; if(!useSPFA) for(Index i = 0; i < n; i ++) potential[i] += dist[i]; Flow d = f; Cost distt = 0; for(Index v = t; v != s; ) { Index u = prev[v]; const Edge &e = g[u][prevEdge[v]]; d = min(d, e.capacity); distt += e.cost; v = u; } f -= d; total.first += d * distt; total.second += d; for(Index v = t; v != s; v = prev[v]) { Edge &e = g[prev[v]][prevEdge[v]]; e.capacity -= d; g[e.to][e.rev].capacity += d; } } return total; } }; int find_num(string ss) { int ans=0; int tt=1; reverse(ss.begin(),ss.end()); for(auto i:ss) { ans+=(i- 0 )*tt; tt*=2; } return ans; } vector<vector<int> >adj; int sz[1000005]; int vis[1000005]; int a[100005]; vector<string>fi; int d; void print(int yy) { for(int i=0;i<10;i++) { if(((1<<i)&yy)) { fi.push_back(to_string(d-i-1)); } } } void dfs(int ver,int x) { vis[ver]=1; print(a[ver]^x); int cnt=0; for(auto i:adj[ver]) { if(vis[i]==0) { if(cnt) { fi.push_back( R ); print(a[ver]); dfs(i,a[ver]); } else { dfs(i,a[ver]); } cnt++; } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); #ifndef ONLINE_JUDGE if(fopen( INPUT.txt , r )) { freopen( INPUT.txt , r ,stdin); freopen( OUTPUT.txt , w ,stdout); } #endif int n; cin>>d>>n; string se[n]; for(int i=0;i<n;i++) { cin>>se[i]; a[i+1]=find_num(se[i]); } adj.resize(n+1); MinimumCostMaximumFlow kad; int source=0; int sink=2*n+5; kad.init(2*n+10); for(int i=1;i<=n;i++) { for(int j=1;j<=n;j++) { if(i!=j) { if((a[i]&a[j])==a[j]) { kad.addEdge(1,n+j,i,1,-(__builtin_popcount(a[j])+1)); } } } kad.addEdge(0,i,n+i,1,0); kad.addEdge(0,source,i,1,0); kad.addEdge(0,n+i,sink,1,-(__builtin_popcount(a[i])+1)); } kad.addEdge(0,source,sink,n,0); pair<int,int> ans=kad.minimumCostMaximumFlow(source,sink,n,0); for(int i=n+1;i<=2*n;i++) { for(auto j:temp[i]) { if(kad.g[i][j].capacity==0) { adj[i-n].push_back(kad.g[i][j].to); } } } set<pair<int,int> >ss; int cc=0; for(int i=1;i<=n;i++) { ss.insert({a[i],i}); } while(!ss.empty()) { auto j=ss.begin(); if(vis[j->second]) { ss.erase(j); continue; } if(cc) fi.push_back( R ); cc++; dfs(j->second,0); } cout<<fi.size()<< n ; for(auto i:fi) cout<<i<< ; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, mx, a[100][100], dp[100][100], me[100], inf = -1e15; int sub(int a, int b) { return (((a - b) % k) + k); } signed main(void) { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> k; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j]; memset(dp, -1, sizeof dp); dp[0][0] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { for (int u = min(m / 2, j); u >= 1; u--) { for (int t = 0; t < k; t++) { int x = sub(t, a[i][j]) % k; if (dp[u - 1][x] != -1) dp[u][t] = max(dp[u][t], dp[u - 1][x] + a[i][j]); } } } for (int u = 1; u <= m / 2; u++) { for (int t = 0; t < k; t++) { dp[0][t] = max(dp[0][t], dp[u][t]); if (n != i) dp[u][t] = -1; } } } int mx = 0; for (int i = 0; i <= m / 2; i++) mx = max(mx, dp[i][0]); cout << mx << n ; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); string s; cin >> s; long long i = 0; while (i + 1 < s.size() && s[i] == s[i + 1]) { if (s[i] == 0 ) { cout << 3 << << 1 << n ; cout << 1 << << 1 << n ; } else { cout << 1 << << 1 << n ; cout << 1 << << 3 << n ; } i += 2; } bool r = 0, c = 0; while (i < s.size()) { if (s[i] == 0 ) { if (r) { cout << 1 << << 1 << n ; r = 0; } else { cout << 3 << << 1 << n ; r = 1; } } else { if (c) { cout << 1 << << 1 << n ; c = 0; } else { cout << 1 << << 3 << n ; c = 1; } } i++; } return 0; } |
//
// usb 3.0 rx descrambling and alignment
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_descramble (
input wire clock,
input wire local_clk,
input wire reset_n,
input wire enable,
input wire [1:0] raw_valid,
input wire [5:0] raw_status,
input wire [1:0] raw_phy_status,
input wire [3:0] raw_datak,
input wire [31:0] raw_data,
//output reg [1:0] proc_valid,
//output reg [5:0] proc_status,
//output reg [1:0] proc_phy_status,
output reg [3:0] proc_datak,
output reg [31:0] proc_data,
output reg proc_active,
output reg err_skp_unexpected
);
`include "usb3_const.v"
// what this module does is filtering of the input symbol stream
// to remove everything that >PHY layer is not interested in.
//
// example: scrambled stream with skip padding
// BE40A73C3C3CE62CD3E2B20702772A (D)
// 000000111111000000000000000000 (K)
// >
// 000000000000000000000000 (D)
// 000000000000000000000000 (K)
//
// this would be fairly trivial if we could clock this module at 500mhz
// and only process 1 symbol at a time. however, due to timing constraints
// it's working at 125mhz instead, and on 4 symbols at once. this is where
// symbol alignment gets sticky, and why there are so many cases.
//
// 10/08/13 - edge case discovered where SKP immediately following the end of a
// packet on the next cycle will cause a 1 cycle deassertion of ACTIVE, and
// push the last word of the packet onto the following cycle where ACTIVE
// is asserted again.
// indicates presence of SKP at any symbol position
wire [3:0] skip = { (raw_data[31:24] == 8'h3C) & raw_datak[3], (raw_data[23:16] == 8'h3C) & raw_datak[2],
(raw_data[15:8] == 8'h3C) & raw_datak[1], (raw_data[7:0] == 8'h3C) & raw_datak[0] };
// indicates presence of COM at any symbol position (K28.5)
wire [3:0] comma = { (coll_data[31:24] == 8'hBC) & coll_datak[3], (coll_data[23:16] == 8'hBC) & coll_datak[2],
(coll_data[15:8] == 8'hBC) & coll_datak[1], (coll_data[7:0] == 8'hBC) & coll_datak[0] };
// step 1.
// collapse incoming stream to remove all SKP symbols.
// these may be sent as 0x3C, 0x3C3C, 0x3C3C3C and so on.
//reg [5:0] skr_status;
reg [31:0] skr_data;
reg [3:0] skr_datak;
reg [2:0] skr_num;
reg [1:0] skr_valid;
always @(posedge local_clk) begin
case(skip)
4'b0000: begin
skr_data <= raw_data;
skr_datak <= raw_datak; end
4'b0001: begin
skr_data <= raw_data[31:8];
skr_datak <= raw_datak[3:1]; end
4'b0010: begin
skr_data <= {raw_data[31:16], raw_data[7:0]};
skr_datak <= {raw_datak[3:2], raw_datak[0]}; end
4'b0011: begin
skr_data <= raw_data[31:16];
skr_datak <= raw_datak[3:2]; end
4'b0100: begin
skr_data <= {raw_data[31:24], raw_data[15:0]};
skr_datak <= {raw_datak[3], raw_datak[1:0]}; end
4'b0110: begin
skr_data <= {raw_data[31:24], raw_data[7:0]};
skr_datak <= {raw_datak[3], raw_datak[0]}; end
4'b0111: begin
skr_data <= raw_data[31:24];
skr_datak <= raw_datak[3]; end
4'b1110: begin
skr_data <= raw_data[7:0];
skr_datak <= raw_datak[0]; end
4'b1100: begin
skr_data <= raw_data[15:0];
skr_datak <= raw_datak[1:0]; end
4'b1000: begin
skr_data <= raw_data[23:0];
skr_datak <= raw_datak[2:0]; end
4'b1111: begin
skr_data <= 0;
skr_datak <= 0; end
default: begin
//{skr_status, skr_data, skr_datak} <= 0;
{skr_data, skr_datak} <= 0;
err_skp_unexpected <= 1;
end
endcase
// count valid symbols
skr_num <= 3'h4 - (skip[3] + skip[2] + skip[1] + skip[0]);
//skr_status <= raw_status;
skr_valid <= raw_valid;
if(~reset_n) begin
err_skp_unexpected <= 0;
end
end
// step 2.
// accumulate these fragments and then squeeze them out
// 32bits at a time.
reg [5:0] acc_status;
reg [63:0] acc_data;
reg [7:0] acc_datak;
reg [2:0] acc_depth;
always @(posedge local_clk) begin
// take in either 8, 16, 24, or 32 bits of data from the prior stage
case(skr_num)
0: begin end
1: begin
acc_data <= {acc_data[55:0], skr_data[7:0]};
acc_datak <= {acc_datak[6:0], skr_datak[0:0]};
acc_depth <= acc_depth + 3'd1;
end
2: begin
acc_data <= {acc_data[47:0], skr_data[15:0]};
acc_datak <= {acc_datak[5:0], skr_datak[1:0]};
acc_depth <= acc_depth + 3'd2;
end
3: begin
acc_data <= {acc_data[39:0], skr_data[23:0]};
acc_datak <= {acc_datak[4:0], skr_datak[2:0]};
acc_depth <= acc_depth + 3'd3;
end
4: begin
acc_data <= {acc_data[31:0], skr_data[31:0]};
acc_datak <= {acc_datak[3:0], skr_datak[3:0]};
acc_depth <= acc_depth + 3'd4;
end
endcase
// pick off 32bits and decrement the accumulator
coll_valid <= skr_valid;
coll_active <= (acc_depth > 3);
case(acc_depth)
4: begin
{coll_data, coll_datak} <= {acc_data[31:0], acc_datak[3:0]};
acc_depth <= 3'd0 + skr_num;
end
5: begin
{coll_data, coll_datak} <= {acc_data[39:8], acc_datak[4:1]};
acc_depth <= 3'd1 + skr_num;
end
6: begin
{coll_data, coll_datak} <= {acc_data[47:16], acc_datak[5:2]};
acc_depth <= 3'd2 + skr_num;
end
7: begin
{coll_data, coll_datak} <= {acc_data[55:24], acc_datak[6:3]};
acc_depth <= 3'd3 + skr_num;
end
endcase
if(~reset_n) begin
acc_depth <= 0;
end
end
// step 3.
// handle descrambling LFSR, resetting upon COM with
// proper symbol alignment.
reg [31:0] coll_data ;
reg [3:0] coll_datak;
reg coll_active;
reg [1:0] coll_valid;
reg [2:0] ds_align;
reg [2:0] scr_defer;
always @(posedge local_clk) begin
if(scr_defer < 3) scr_defer <= scr_defer + 1'b1;
if(|comma) scr_defer <= 0;
case(comma)
4'b1111: begin
ds_align <= 0;
end
4'b1110: begin
ds_align <= 1;
end
4'b1100: begin
ds_align <= 2;
end
4'b1000: begin
ds_align <= 3;
end
endcase
if(coll_active) begin
// only apply descrambling to data, not K-symbols
next_data[31:24] <= coll_data[31:24] ^ (coll_datak[3] ? 8'h0 : ds_delay[31:24]);
next_data[23:16] <= coll_data[23:16] ^ (coll_datak[2] ? 8'h0 : ds_delay[23:16]);
next_data[15:8] <= coll_data[15:8] ^ (coll_datak[1] ? 8'h0 : ds_delay[15:8]);
next_data[7:0] <= coll_data[7:0] ^ (coll_datak[0] ? 8'h0 : ds_delay[7:0]);
next_datak <= coll_datak;
// match incoming alignment
case(ds_align)
0: ds_delay <= {ds_last};
1: ds_delay <= {ds_last[23:0], ds_out[31:24]};
2: ds_delay <= {ds_last[15:0], ds_out[31:16]};
3: ds_delay <= {ds_last[7:0], ds_out[31:8]};
endcase
ds_last <= ds_out;
end
next_active <= coll_active;
// squelch invalids
if(~coll_valid || ~coll_active) begin
next_data <= 32'h0;
next_datak <= 4'b0;
next_active <= 0;
end
end
// step 4.
// pipeline data to relax timing
reg [31:0] next_data;
reg [3:0] next_datak;
reg next_active;
always @(posedge local_clk) begin
proc_data <= next_data;
proc_datak <= next_datak;
proc_active <= next_active;
end
//
// data de-scrambling for RX
//
reg [31:0] ds_delay;
reg [31:0] ds_last;
wire ds_suppress = |comma || (scr_defer < 3);
wire ds_enable = enable && !ds_suppress;
wire [31:0] ds_out_swap;
wire [31:0] ds_out = ds_enable ?
{ds_out_swap[7:0], ds_out_swap[15:8], ds_out_swap[23:16], ds_out_swap[31:24]}
: 0;
usb3_lfsr iu3srx(
.clock ( local_clk ),
.reset_n ( reset_n ),
.data_in ( 32'h0 ),
.scram_en ( coll_active ),
.scram_rst ( |comma ),
.scram_init ( 16'h7DBD ), // reset to FFFF + 3 cycles
.data_out_reg ( ds_out_swap )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; long long a[maxn], b[maxn]; long long dp[maxn]; int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); a[i] -= i; b[i] = a[i]; } sort(b + 1, b + 1 + n); memset(dp, (0), sizeof(dp)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (j == 1) dp[j] += abs(a[i] - b[j]); else { dp[j] = min(dp[j - 1], dp[j] + abs(a[i] - b[j])); } } } printf( %lld n , (dp[n])); return 0; } |
#include <bits/stdc++.h> using namespace std; int ans = 0; vector<vector<int> > data; void relax(int &a, int &b, int c) { if (c > a) { b = a; a = c; } else b = max(b, c); } pair<int, int> dfs(int vertex, int last) { int take = 0, take2 = 0, non = 0, non2 = 0; for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (to == last) continue; pair<int, int> res = dfs(to, vertex); relax(take, take2, res.second); relax(non, non2, max(res.second, res.first)); } ans = max(ans, take2 + take + 1); ans = max(ans, non2 + non + max(0, (int)data[vertex].size() - 2)); ans = max(ans, non + max(0, (int)data[vertex].size() - 1)); non += data[vertex].size() - 2; return {take + 1, non}; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; data.assign(n, {}); for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; data[u - 1].push_back(v - 1); data[v - 1].push_back(u - 1); } dfs(0, -1); cout << ans; } |
//---------------------------------------------------------------------
//
// Company: UNSW
// Original Author: Lingkan Gong
// Project Name: State_Migration
//
// Create Date: 12/06/2010
// Design Name: xbus_masterif
//
//---------------------------------------------------------------------
`timescale 1ns/1ns
module xbus_masterif # (
parameter C_DWIDTH = 128
)
(
//-- to/form ipif ----
input Bus2IP_Mst_Clk,
input Bus2IP_Mst_Reset,
output IP2Bus_MstRd_Req,
output IP2Bus_MstWr_Req,
output [31:0] IP2Bus_Mst_Addr,
output [C_DWIDTH/8-1:0] IP2Bus_Mst_BE,
output [11:0] IP2Bus_Mst_Length,
output IP2Bus_Mst_Type,
output IP2Bus_Mst_Lock,
output IP2Bus_Mst_Reset,
input Bus2IP_Mst_CmdAck,
input Bus2IP_Mst_Cmplt,
input Bus2IP_Mst_Error,
input Bus2IP_Mst_Rearbitrate,
input Bus2IP_Mst_Cmd_Timeout,
input [C_DWIDTH-1:0] Bus2IP_MstRd_d,
input [C_DWIDTH/8-1:0] Bus2IP_MstRd_rem,
input Bus2IP_MstRd_sof_n,
input Bus2IP_MstRd_eof_n,
input Bus2IP_MstRd_src_rdy_n,
input Bus2IP_MstRd_src_dsc_n,
output IP2Bus_MstRd_dst_rdy_n,
output IP2Bus_MstRd_dst_dsc_n,
output [C_DWIDTH-1:0] IP2Bus_MstWr_d,
output [C_DWIDTH/8-1:0] IP2Bus_MstWr_rem,
output IP2Bus_MstWr_sof_n,
output IP2Bus_MstWr_eof_n,
output IP2Bus_MstWr_src_rdy_n,
output IP2Bus_MstWr_src_dsc_n,
input Bus2IP_MstWr_dst_rdy_n,
input Bus2IP_MstWr_dst_dsc_n,
//-- to/from xbus (xbus master interface)----
input ma_req ,
output xbm_gnt ,
input ma_select ,
input [31:0] ma_addr ,
input [31:0] ma_data ,
input ma_rnw ,
input [3:0] ma_be ,
output xbm_ack ,
output [31:0] xbm_data
);
`define IDLE 8'h0
`define ADDR 8'h1
`define ADDR_DATA 8'h2
`define DATA_ADDR 8'h3
`define COMP 8'h4
//-------------------------------------------------------------------
// Request & Ack
//-------------------------------------------------------------------
wire master_rd_req, master_wr_req; // Internal request
wire master_rd_ack, master_wr_ack; // Internal acknowledge
wire [31:0] master_address;
reg [31:0] master_rd_data;
wire [C_DWIDTH-1:0] master_wr_data;
reg [C_DWIDTH/8-1:0] master_byte_enable;
reg [7:0] state_c, state_n;
assign master_rd_req = ma_select & ma_rnw;
assign master_wr_req = ma_select & ~ma_rnw;
assign master_rd_ack = (~Bus2IP_MstRd_src_rdy_n & ~IP2Bus_MstRd_dst_rdy_n & ~Bus2IP_MstRd_sof_n & ~Bus2IP_MstRd_eof_n);
assign master_wr_ack = (~IP2Bus_MstWr_src_rdy_n & ~Bus2IP_MstWr_dst_rdy_n & ~IP2Bus_MstWr_sof_n & ~IP2Bus_MstWr_eof_n);
generate begin : gen_master_wr_data
genvar i;
for (i = 0; i < C_DWIDTH/32; i = i + 1) begin : mirror_j
assign master_wr_data[C_DWIDTH-1-32*i:C_DWIDTH-32-32*i] = ma_data;
end
end endgenerate
always @(*) begin
case (ma_addr[1:0])
0: begin master_byte_enable = 16'hf000; end
1: begin master_byte_enable = 16'h0f00; end
2: begin master_byte_enable = 16'h00f0; end
3: begin master_byte_enable = 16'h000f; end
default: begin master_byte_enable = 16'h0000; end
endcase
end
always @(posedge Bus2IP_Mst_Clk or posedge Bus2IP_Mst_Reset) begin
if (Bus2IP_Mst_Reset)
master_rd_data <= 32'h0;
else begin
if (master_rd_ack) begin
case (Bus2IP_MstRd_rem)
16'h0fff: begin master_rd_data <= Bus2IP_MstRd_d[127:96]; end
16'hf0ff: begin master_rd_data <= Bus2IP_MstRd_d[95:64]; end
16'hff0f: begin master_rd_data <= Bus2IP_MstRd_d[63:32]; end
16'hfff0: begin master_rd_data <= Bus2IP_MstRd_d[31:0]; end
default: begin master_rd_data <= 32'h0; end
endcase
end
end
end
assign master_address = {ma_addr[29:0],2'b0}; // IP use address in WORDS
//-------------------------------------------------------------------
// Main FSM
//-------------------------------------------------------------------
always @(posedge Bus2IP_Mst_Clk or posedge Bus2IP_Mst_Reset) begin
if (Bus2IP_Mst_Reset)
state_c <= `IDLE;
else
state_c <= state_n;
end
always @(*) begin
case (state_c)
`IDLE: begin state_n = (master_rd_req || master_wr_req)? `ADDR: `IDLE; end
`ADDR: begin
state_n = `ADDR;
if (Bus2IP_Mst_CmdAck) state_n = `ADDR_DATA;
if (master_rd_ack || master_wr_ack) state_n = `DATA_ADDR;
end
`ADDR_DATA: begin state_n = (master_rd_ack || master_wr_ack)?`COMP: `ADDR_DATA; end
`DATA_ADDR: begin state_n = (Bus2IP_Mst_CmdAck)?`COMP: `DATA_ADDR; end
`COMP: begin state_n = (Bus2IP_Mst_Cmplt)? `IDLE: `COMP; end
default: begin state_n = `IDLE; end
endcase
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(*) begin
if (state_c==`IDLE) state_ascii <= "IDLE";
else if (state_c==`ADDR) state_ascii <= "ADDR";
else if (state_c==`ADDR_DATA) state_ascii <= "ADDR_DATA";
else if (state_c==`DATA_ADDR) state_ascii <= "DATA_ADDR";
else if (state_c==`COMP) state_ascii <= "COMP";
else state_ascii <= "ERROR";
end
// synthesis translate_on
//-------------------------------------------------------------------
// IPIF <-> XBUS_IF
//-------------------------------------------------------------------
assign IP2Bus_MstRd_Req = master_rd_req && ((state_c == `ADDR) || (state_c == `DATA_ADDR));
assign IP2Bus_MstWr_Req = master_wr_req && ((state_c == `ADDR) || (state_c == `DATA_ADDR));
assign IP2Bus_Mst_Addr = master_address;
assign IP2Bus_Mst_BE = master_byte_enable;
assign IP2Bus_Mst_Length = 'h0; // Always C_DWIDTH/8 bytes
assign IP2Bus_Mst_Type = 'h0; // Always single beat transfer
assign IP2Bus_Mst_Lock = 'h0;
assign IP2Bus_Mst_Reset = 'h0;
assign IP2Bus_MstRd_dst_rdy_n = ~(master_rd_req && ((state_c == `ADDR)||(state_c == `ADDR_DATA)||(state_c == `DATA_ADDR)));
assign IP2Bus_MstRd_dst_dsc_n = 1'b1;
assign IP2Bus_MstWr_d = master_wr_data; // IP Write Bus
assign IP2Bus_MstWr_rem = ~master_byte_enable; // IP Write Bus
assign IP2Bus_MstWr_sof_n = ~ma_select;
assign IP2Bus_MstWr_eof_n = ~ma_select;
assign IP2Bus_MstWr_src_rdy_n = ~(master_wr_req && ((state_c == `ADDR)||(state_c == `ADDR_DATA)||(state_c == `DATA_ADDR)));
assign IP2Bus_MstWr_src_dsc_n = 1'b1;
assign xbm_gnt = 1'b1; // Point-to-point connection: ma_req not used + always grant
assign xbm_data = master_rd_data; // IP Read Bus
assign xbm_ack = Bus2IP_Mst_Cmplt; // Acknowledge XBUS_IF at the very last cycle
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk (
clk_in_p,
clk_in_n,
clk);
parameter BUFTYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
input clk_in_p;
input clk_in_n;
output clk;
// wires
wire clk_ibuf_s;
// instantiations
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
generate
if (BUFTYPE == VIRTEX6) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_ibuf_s),
.O (clk));
end else begin
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> int len, rest; int space[10][110] = {0}; int num = 0; int ans[21000][3] = {0}; void Check() { for (int i = 1; i <= len; i++) if (space[1][i] != 0 && space[1][i] == space[2][i]) { num++; rest--; ans[num][0] = space[2][i]; ans[num][1] = 1; ans[num][2] = i; space[2][i] = 0; } for (int i = 1; i <= len; i++) if (space[4][i] != 0 && space[3][i] == space[4][i]) { num++; rest--; ans[num][0] = space[3][i]; ans[num][1] = 4; ans[num][2] = i; space[3][i] = 0; } return; } void Rotate() { int px = 0, py = 0; for (int k = 2; k <= 3 && !px; k++) for (int i = 1; i <= len && !px; i++) if (space[k][i] == 0) { px = k; py = i; } for (int time = 1; time < len * 2; time++) { int nx, ny; if (px == 2) if (py < len) { nx = 2; ny = py + 1; } else { nx = 3; ny = len; } else if (py > 1) { nx = 3; ny = py - 1; } else { nx = 2; ny = 1; } if (space[nx][ny] != 0) { num++; ans[num][0] = space[nx][ny]; ans[num][1] = px; ans[num][2] = py; space[px][py] = space[nx][ny]; space[nx][ny] = 0; } px = nx; py = ny; } return; } int main() { int num_car; scanf( %d%d , &len, &num_car); rest = num_car; for (int k = 1; k <= 4; k++) for (int i = 1; i <= len; i++) scanf( %d , &space[k][i]); Check(); if (rest == num_car && num_car == len * 2) { printf( -1 n ); return 0; } while (rest) { Rotate(); Check(); } printf( %d n , num); for (int i = 1; i <= num; i++) printf( %d %d %d n , ans[i][0], ans[i][1], ans[i][2]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX / 2; int main() { int n, k, q; scanf( %d%d%d , &n, &k, &q); vector<int> vec(n); for (int i = 0; i < n; i++) { scanf( %d , &vec[i]); } set<pair<int, int> > st; map<int, int> mp; for (int i = 0; i < q; i++) { int type, id; scanf( %d%d , &type, &id); id--; if (type == 1) { if (st.size() < k) { st.insert(make_pair(vec[id], id)); mp[id] = 1; } else { set<pair<int, int> >::iterator it = st.begin(); if ((*it).first < vec[id]) { mp.erase((*it).second); st.erase(it); st.insert(make_pair(vec[id], id)); mp[id] = 1; } } } else { if (mp.count(id)) printf( YES n ); else printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename S, typename T> ostream& operator<<(ostream& out, pair<S, T> const& p) { out << ( << p.first << , << p.second << ) ; return out; } template <typename T> ostream& operator<<(ostream& out, vector<T> const& v) { int l = v.size(); for (int i = 0; i < l - 1; i++) out << v[i] << ; if (l > 0) out << v[l - 1]; return out; } template <typename T> void trace(const char* name, T&& arg1) { cout << name << : << arg1 << endl; } template <typename T, typename... Args> void trace(const char* names, T&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; trace(comma + 1, args...); } const int N = 100100; int pt; bool cmp(const int& i, const int& j) { if (i < pt and j < pt) { return i < j; } else if (i > pt and j > pt) { return i < j; } else { return i > j; } } vector<int> nxt[N]; int a[N]; int b[N]; int lft[N]; int rgt[N]; pair<int, int> tosort[N]; bool importance(const int& i, const int& j) { return tosort[i] < tosort[j]; } vector<int> face[N]; vector<int> g[N]; map<pair<int, int>, int> id; set<pair<int, int> > used; void buildFace(int from, int to, int f) { face[f].push_back(to); used.insert(make_pair(from, to)); pt = to; vector<int>& v = nxt[to]; int nxt = *upper_bound(v.begin(), v.end(), from, cmp); if (used.count(make_pair(to, nxt))) return; buildFace(to, nxt, f); } int vis[N]; int usd[N]; int sz[N]; int lvl[N]; void dfs(int x, int h) { sz[x] = 1; vis[x] = h; for (auto it = (g[x]).begin(); it != (g[x]).end(); ++it) { if (usd[*it]) continue; if (vis[*it] == h) continue; dfs(*it, h); sz[x] += sz[*it]; } } int findCentroid(int x, int n, int prev) { for (auto it = (g[x]).begin(); it != (g[x]).end(); ++it) { if (vis[*it] != vis[x] or *it == prev) continue; if (sz[*it] > n / 2) return findCentroid(*it, n, x); } return x; } void decompose(int x, int h) { dfs(x, h); int c = findCentroid(x, sz[x], -1); lvl[c] = h; usd[c] = 1; for (auto it = (g[c]).begin(); it != (g[c]).end(); ++it) { if (!usd[*it]) decompose(*it, h + 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; if (m == 0) { cout << 1 << endl; return 0; } if (m == 1) { cout << 1 2 << endl; return 0; } nxt[1].push_back(n); nxt[n].push_back(1); for (int i = 2; i <= n; i++) { nxt[i].push_back(i - 1); nxt[i - 1].push_back(i); } for (int i = 0; i < m; i++) { cin >> a[i] >> b[i]; if (a[i] < b[i]) swap(a[i], b[i]); id[make_pair(a[i], b[i])] = id[make_pair(b[i], a[i])] = i; nxt[a[i]].push_back(b[i]); nxt[b[i]].push_back(a[i]); } for (int i = 1; i <= n; i++) { pt = i; sort(nxt[i].begin(), nxt[i].end(), cmp); } int cur = 0; for (int i = 0; i < m; i++) { if (!used.count(make_pair(a[i], b[i]))) { face[++cur].push_back(a[i]); buildFace(a[i], b[i], cur); for (int j = 1; j < face[cur].size(); j++) { int x = face[cur][j - 1], y = face[cur][j]; if (x - 1 != y and !(x == 1 and y == n)) { int k = id[make_pair(x, y)]; if (x > y) lft[k] = cur; else rgt[k] = cur; } } } if (!used.count(make_pair(b[i], a[i]))) { face[++cur].push_back(b[i]); buildFace(b[i], a[i], cur); for (int j = 1; j < face[cur].size(); j++) { int x = face[cur][j - 1], y = face[cur][j]; if (x - 1 != y and !(x == 1 and y == n)) { int k = id[make_pair(x, y)]; if (x > y) lft[k] = cur; else rgt[k] = cur; } } } int x = lft[i], y = rgt[i]; assert(x > 0 and y > 0); g[x].push_back(y); g[y].push_back(x); } for (int i = 1; i <= cur; i++) { int mx = 0, smx = 0; for (int j = 1; j < face[i].size(); j++) { int x = face[i][j]; if (x > mx) { smx = mx; mx = x; } else if (x > smx) smx = x; } tosort[i] = make_pair(mx, smx); } vector<int> faces; for (int i = 1; i <= cur; i++) faces.push_back(i); sort(faces.begin(), faces.end(), importance); decompose(1, 1); for (int x : faces) { cout << lvl[x] << ; } cout << endl; return 0; } |
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: xgmii_loopback.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module xgmii_loopback (
data0x,
data1x,
sel,
result);
input [65:0] data0x;
input [65:0] data1x;
input sel;
output [65:0] result;
wire [65:0] sub_wire0;
wire [65:0] sub_wire3 = data1x[65:0];
wire [65:0] result = sub_wire0[65:0];
wire [65:0] sub_wire1 = data0x[65:0];
wire [131:0] sub_wire2 = {sub_wire3, sub_wire1};
wire sub_wire4 = sel;
wire sub_wire5 = sub_wire4;
lpm_mux LPM_MUX_component (
.data (sub_wire2),
.sel (sub_wire5),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 66,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "66"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 66 0 INPUT NODEFVAL "data0x[65..0]"
// Retrieval info: USED_PORT: data1x 0 0 66 0 INPUT NODEFVAL "data1x[65..0]"
// Retrieval info: USED_PORT: result 0 0 66 0 OUTPUT NODEFVAL "result[65..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 66 0 data0x 0 0 66 0
// Retrieval info: CONNECT: @data 0 0 66 66 data1x 0 0 66 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 66 0 @result 0 0 66 0
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
//Verilog testbench template generated by SCUBA Diamond_1.4_Production (87)
`timescale 1 ns / 1 ps
module tb;
reg [8:0] Data = 9'b0;
reg WrClock = 0;
reg RdClock = 0;
reg WrEn = 0;
reg RdEn = 0;
reg Reset = 0;
reg RPReset = 0;
wire [8:0] Q;
wire Empty;
wire Full;
integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0;
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
asfifo9_4 u1 (.Data(Data), .WrClock(WrClock), .RdClock(RdClock), .WrEn(WrEn),
.RdEn(RdEn), .Reset(Reset), .RPReset(RPReset), .Q(Q), .Empty(Empty),
.Full(Full)
);
initial
begin
Data <= 0;
#100;
@(Reset == 1'b0);
for (i1 = 0; i1 < 19; i1 = i1 + 1) begin
@(posedge WrClock);
#1 Data <= Data + 1'b1;
end
end
always
#5.00 WrClock <= ~ WrClock;
always
#5.00 RdClock <= ~ RdClock;
initial
begin
WrEn <= 1'b0;
#100;
@(Reset == 1'b0);
for (i4 = 0; i4 < 19; i4 = i4 + 1) begin
@(posedge WrClock);
#1 WrEn <= 1'b1;
end
WrEn <= 1'b0;
end
initial
begin
RdEn <= 1'b0;
@(Reset == 1'b0);
@(WrEn == 1'b1);
@(WrEn == 1'b0);
for (i5 = 0; i5 < 19; i5 = i5 + 1) begin
@(posedge RdClock);
#1 RdEn <= 1'b1;
end
RdEn <= 1'b0;
end
initial
begin
Reset <= 1'b1;
#100;
Reset <= 1'b0;
end
initial
begin
RPReset <= 1'b1;
#100;
RPReset <= 1'b0;
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 1004; int cnk[N][N] = {0}; int mod = 1000000007; void init_cnk() { for (int i = 0; i < N; ++i) { cnk[i][0] = 1; cnk[i][i] = 1; } for (int i = 1; i < N; ++i) { for (int j = 1; j < N; ++j) { cnk[i][j] = (cnk[i - 1][j - 1] + cnk[i - 1][j]) % mod; } } } int main() { ios_base::sync_with_stdio(false); cout.precision(10); cout << fixed; int k; cin >> k; vector<int> c(k, 0); for (int i = 0; i < k; ++i) cin >> c[i]; init_cnk(); int n = c.size(); vector<int> res(n, 0); res[0] = 1; int acc = c[0]; for (int i = 1; i < n; ++i) { int cur = c[i]; for (int j = 0; j < cur; ++j) { res[i] += (1LL * cnk[acc - 1 + j][j] * res[i - 1]) % (1LL * mod); res[i] %= mod; } acc += cur; } cout << res[n - 1] << endl; return 0; } |
module x (/*AUTOARG*/);
// Which Internal Bank
`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
command address
always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
begin : PeelIntBnkAddr
case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
2'b01: // 2-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
end
2'b10: // 4-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
end
default: // 8-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
#include <bits/stdc++.h> using namespace std; const long long mod = 811287553; long long powmod(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } int n, m, s, t, a, b, d; vector<long long> dist, dist1; vector<pair<int, int> > grh[2][100000]; vector<pair<pair<int, int>, int> > queries; set<pair<int, int> > absEdges; map<pair<int, int>, int> minEdges; long long reachableCnt[2][100000]; const long long INF = 1000000000000; void dijkstra(int src, vector<long long>& d, int mode) { d.resize(n, INF); d[src] = 0; priority_queue<pair<long long, int> > pq; pq.push(make_pair(0, src)); while (!pq.empty()) { long long topD = -pq.top().first; int topIdx = pq.top().second; pq.pop(); if (d[topIdx] < topD) continue; int sz = grh[mode][topIdx].size(); for (int i = 0; i < (int)sz; i++) { int nIdx = grh[mode][topIdx][i].first; int nD = grh[mode][topIdx][i].second; long long nD1 = topD + nD; if (d[nIdx] > nD1) { d[nIdx] = nD1; pq.push(make_pair(-nD1, nIdx)); } } } } int calReachable(int idx, vector<long long>& d, bool rev) { if (rev && idx == s) { reachableCnt[!rev][idx] = 1; return 1; } if (!rev && idx == t) { reachableCnt[!rev][idx] = 1; return 1; } long long& ret = reachableCnt[!rev][idx]; if (ret != -1) return ret; int ret1 = 0; int sz = grh[rev][idx].size(); for (int i = 0; i < (int)sz; i++) { int nIdx = grh[rev][idx][i].first; int nD = grh[rev][idx][i].second; if (d[nIdx] == d[idx] + nD) { ret1 += calReachable(nIdx, d, rev); ret1 %= mod; } } return ret = (ret1 % mod); } int main() { cin >> n >> m >> s >> t; s--, t--; for (int i = 0; i < (int)m; i++) { cin >> a >> b >> d; a--, b--; grh[0][a].push_back(make_pair(b, d)); grh[1][b].push_back(make_pair(a, d)); queries.push_back(make_pair(make_pair(a, b), d)); if (minEdges.count(make_pair(a, b))) minEdges[make_pair(a, b)] = min(minEdges[make_pair(a, b)], d); else minEdges[make_pair(a, b)] = d; } memset(reachableCnt, -1, sizeof(reachableCnt)); dijkstra(s, dist, 0); dijkstra(t, dist1, 1); calReachable(t, dist1, 1); calReachable(s, dist, 0); for (int i = 0; i < (int)m; i++) { int x = queries[i].first.first, y = queries[i].first.second, d = queries[i].second; if ((((reachableCnt[0][x] * reachableCnt[1][y]) % mod) == reachableCnt[0][t]) && minEdges[make_pair(x, y)] < d) { if (minEdges[make_pair(x, y)] == 1) cout << NO << endl; else cout << CAN << d - minEdges[make_pair(x, y)] + 1 << endl; } else { long long d1 = dist[x] + dist1[y]; if ((((reachableCnt[0][x] * reachableCnt[1][y]) % mod) == reachableCnt[0][t])) { if (d1 + d == dist[t]) cout << YES << endl; else { if (d > 1 && d1 + 1 < dist[t]) cout << CAN << d + d1 - (dist[t] - 1) << endl; else cout << NO << endl; } } else { if (d > 1 && d1 + 1 < dist[t]) cout << CAN << d + d1 - (dist[t] - 1) << endl; else cout << NO << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int num = 0; bool f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { f = (ch == - ); ch = getchar(); } while (ch >= 0 && ch <= 9 ) { num = (num << 1) + (num << 3) + ch - 0 ; ch = getchar(); } return f ? -num : num; } int n, m; int deg[111]; vector<int> vec[111]; int topsort() { int res = 0, fl = 1; queue<int> Q; while (fl) { fl = 0; for (int i = 1; i <= n; i++) if (deg[i] == 1) Q.push(i), fl = 1; while (!Q.empty()) { int u = Q.front(); Q.pop(); deg[u]--; for (int v : vec[u]) deg[v]--; } if (fl) res++; } return res; } int main() { n = read(), m = read(); for (int i = 1; i <= m; i++) { int x = read(), y = read(); deg[x]++, deg[y]++; vec[x].push_back(y); vec[y].push_back(x); } printf( %d n , topsort()); return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } bool Check(int x, int y) { if (gcd(x, y) > 1) return false; if (gcd(x + 1, y) > 1) return false; if (gcd(x + 2, y) > 1) return false; return true; } vector<int> ans[10010]; int main() { int n, k; cin >> n >> k; int x = 1; for (int i = 0; i < (n); i++) { ans[i].push_back(x * k); ans[i].push_back((x + 1) * k); ans[i].push_back((x + 2) * k); int y = x + 4; while (!Check(x, y)) y += 2; ans[i].push_back(y * k); x = y + 2; } cout << (x - 2) * k << endl; for (int i = 0; i < (n); i++) cout << ans[i][0] << << ans[i][1] << << ans[i][2] << << ans[i][3] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; namespace NTT { const int P=998244353,g=3; const int W=22,S=1<<W; const int J=86583718; inline int add(int a,int b) {int r=a+b; return r<P?r:r-P;} inline int sub(int a,int b) {int r=a-b; return r<0?r+P:r;} inline int mul(long long a,long long b) {return (a*b)%P;} inline int inv(int a) {return a==1?a:mul(inv(P%a),P-P/a);} inline int qpow(int a,long long k) { int r=1; while (k) { if (k&1) r=mul(r,a); k>>=1; a=mul(a,a); } return r; } int r[S],w[2][S]; void init(int lim) { int w0=qpow(g,(P-1)/lim); w[0][0]=w[1][0]=1; for (int i=1;i<lim;i++) w[0][i]=w[1][lim-i]=mul(w[0][i-1],w0); for (int i=0;i<lim;i++) r[i]=(r[i>>1]>>1)|((i&1)*(lim>>1)); } void ntt(int *a,int lim,int o) { for (int i=0;i<lim;i++) if (i<r[i]) swap(a[i],a[r[i]]); for (int i=1;i<lim;i<<=1) { for (int j=0,t=lim/(i<<1);j<lim;j+=i<<1) { for (int k=j,l=0;k<j+i;k++,l+=t) { int x=a[k],y=mul(w[o][l],a[k+i]); a[k]=add(x,y); a[k+i]=sub(x,y); } } } if (o) { int tmp=NTT::inv(lim); for (int i=0;i<lim;i++) a[i]=mul(a[i],tmp); } } vector<int> poly_add(const vector<int> &a,const vector<int> &b) { int n=a.size(),m=b.size(); vector<int> c; for (int i=0;i<max(n,m);i++) c.push_back(add((i<n?a[i]:0),(i<m?b[i]:0))); return c; } vector<int> poly_sub(const vector<int> &a,const vector<int> &b) { int n=a.size(),m=b.size(); vector<int> c; for (int i=0;i<max(n,m);i++) c.push_back(sub((i<n?a[i]:0),(i<m?b[i]:0))); return c; } vector<int> poly_d(const vector<int> &a) { int n=a.size(); vector<int> b; for (int i=1;i<n;i++) b.push_back(mul(a[i],i)); return b; } vector<int> poly_s(const vector<int> &a) { int n=a.size(); vector<int> b{0}; for (int i=0;i<n;i++) b.push_back(mul(a[i],inv(i+1))); return b; } int p1[S],p2[S]; vector<int> poly_mul(const vector<int> &a,const vector<int> &b) { int n=a.size(),m=b.size(); int lim=1; while (lim<(n<<1)) lim<<=1; while (lim<(m<<1)) lim<<=1; init(lim); for (int i=0;i<lim;i++) r[i]=(i&1)*(lim>>1)+(r[i>>1]>>1); copy_n(a.begin(),n,p1); fill(p1+n,p1+lim,0); copy_n(b.begin(),m,p2); fill(p2+m,p2+lim,0); ntt(p1,lim,0); ntt(p2,lim,0); for (int i=0;i<lim;i++) p1[i]=mul(p1[i],p2[i]); ntt(p1,lim,1); return vector<int>(p1,p1+n+m-1); } vector<int> poly_inv(const vector<int> &a) { int n=a.size(); if (n==1) return {inv(a[0])}; auto b=a; b.resize((n+1)>>1); b=poly_inv(b); int m=b.size(); int lim=1; while (lim<(n<<1)) lim<<=1; while (lim<(m<<1)) lim<<=1; init(lim); copy_n(a.begin(),n,p1); fill(p1+n,p1+lim,0); copy_n(b.begin(),m,p2); fill(p2+m,p2+lim,0); ntt(p1,lim,1); ntt(p2,lim,1); for (int i=0;i<lim;i++) p1[i]=mul(p2[i],sub(2,mul(p1[i],p2[i]))); ntt(p1,lim,-1); return vector<int>(p1,p1+n); } vector<int> poly_div(const vector<int> &a,const vector<int> &b) { int n=a.size(),m=b.size(); if (m>n) return {0}; auto ar=a,br=b; reverse(ar.begin(),ar.end()); reverse(br.begin(),br.end()); ar.resize(n-m+1); br.resize(n-m+1); br=poly_inv(br); auto q=poly_mul(ar,br); q.resize(n-m+1); reverse(q.begin(),q.end()); return q; } vector<int> poly_mod(const vector<int> &a,const vector<int> &b) { int m=b.size(); auto c=poly_div(a,b); c=poly_mul(b,c); c=poly_sub(a,c); c.resize(m-1); return c; } vector<int> poly_sqrt(const vector<int> &a) { int n=a.size(); if (n==1) return {1}; auto b=a; b.resize((n+1)>>1); b=poly_sqrt(b); b.resize(n); auto c=poly_add(b,poly_mul(poly_inv(b),a)); c.resize(n); int i2=inv(2); for (int &i:c) i=mul(i,i2); return c; } vector<int> poly_ln(const vector<int> &a) { int n=a.size(); auto b=poly_mul(poly_inv(a),poly_d(a)); b.resize(n-1); b=poly_s(b); return b; } vector<int> poly_exp(const vector<int> &a) { int n=a.size(); if (n==1) return {1}; auto b=a; b.resize((n+1)>>1); b=poly_exp(b); b.resize(n); auto c=poly_sub(a,poly_ln(b)); c[0]=add(c[0],1); c=poly_mul(b,c); c.resize(n); return c; } vector<int> poly_sin(const vector<int> &a) { auto b=a; for (int &i:b) i=mul(i,J); auto c=poly_exp(b); c=poly_sub(c,poly_inv(c)); int i2=inv(2),ij=inv(J); for (int &i:c) i=mul(i,mul(i2,ij)); return c; } vector<int> poly_cos(const vector<int> &a) { auto b=a; for (int &i:b) i=mul(i,J); auto c=poly_exp(b); c=poly_add(c,poly_inv(c)); int i2=inv(2); for (int &i:c) i=mul(i,i2); return c; } vector<int> poly_asin(const vector<int> &a) { int n=a.size(); auto b=poly_d(a),c=poly_mul(a,a); c.resize(n); c=poly_inv(poly_sqrt(poly_sub({1},c))); b=poly_mul(b,c); b.resize(n-1); return poly_s(b); } vector<int> poly_atan(const vector<int> &a) { int n=a.size(); auto b=poly_d(a),c=poly_mul(a,a); c.resize(n); c=poly_inv(poly_add({1},c)); b=poly_mul(b,c); b.resize(n-1); return poly_s(b); } } const int N=200010; int n,a,b; long long inv[N]; long long fac[N],invf[N]; void linear_inv(long long n,long long p) { inv[1]=1; for (long long i=2;i<=n;i++) inv[i]=(p-p/i)*inv[p%i]%p; fac[0]=1; for (long long i=1;i<=n;i++) fac[i]=fac[i-1]*i%p; invf[n]=NTT::inv(fac[n]); for (long long i=n-1;i>=0;i--) invf[i]=invf[i+1]*(i+1)%p; } long long C(long long n,long long m) { if (m>n) return 0; return NTT::mul(fac[n],NTT::mul(invf[m],invf[n-m])); } int main() { linear_inv(200000,NTT::P); scanf( %d ,&n); vector<int> ans={1}; int l=1; for (int i=1;i<=n;i++) { scanf( %d%d ,&a,&b); vector<int> f; int sz=min(l+l+a-b-1,a+b+1); for (int j=(a+b+1-sz)/2;j<=a+b-(a+b+1-sz)/2;j++) { f.push_back(C(a+b,j)); } ans=NTT::poly_mul(ans,f); l+=a-b; int now=ans.size(); ans.erase(ans.begin(),ans.begin()+(now-l)/2); ans.erase(ans.end()-(now-l)/2,ans.end()); } int sum=0; for (int i:ans) { sum=NTT::add(sum,i); } printf( %d ,sum); getchar(); getchar(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; vector<set<int> > v(26); for (int i = 0; i < s.size(); i++) v[s[i] - a ].insert(i); int q = 0, op = 0; cin >> q; while (q--) { cin >> op; if (op == 1) { int pos = 0; char x; cin >> pos >> x; v[s[pos - 1] - a ].erase(pos - 1); s[pos - 1] = x; v[s[pos - 1] - a ].insert(pos - 1); } else { int l = 0, r = 0, ans = 0; cin >> l >> r; for (int i = 0; i < 26; i++) { auto it = v[i].lower_bound(l - 1); if (it != v[i].end() && *it <= r - 1) ans++; } cout << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; while (a--) { int b, c; cin >> b >> c; int n = abs(b - c); n = n / 5 + (n % 5) / 2 + (n % 5) % 2; cout << n << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[1000005] = {0}; long long b[1000005] = {0}; long long c[1000005] = {0}; long long d[1000005] = {0}; long long s; long long i, j = 0, l; long long count1 = 0; long long count2 = 0; long long count3 = 0; long long count4 = 0; long long ans = 0; bool cmp(long long aa, long long bb) { return aa > bb; } int main() { long long n; scanf( %lld n , &n); for (i = 0; i < n; i++) { cin >> s >> j; if (s == 11) { a[count1++] = j; ans += j; } else if (s == 10) { b[count2++] = j; } else if (s == 1) { c[count3++] = j; } else { d[count4++] = j; } } sort(b, b + count2, cmp); sort(c, c + count3, cmp); for (i = 0; i < min(count2, count3); i++) ans += (b[i] + c[i]); for (i = 0; i < abs(count2 - count3); i++) { if (count3 > count2) d[count4 + i] = c[min(count2, count3) + i]; else if (count3 < count2) d[count4 + i] = b[min(count2, count3) + i]; } count4 += abs(count2 - count3); sort(d, d + count4, cmp); for (i = 0; i < count1 && i < count4; i++) ans += d[i]; cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int in(char &c) { return scanf( %c , &c); } int in(char s[]) { return scanf( %s , s); } int in(int &x) { return scanf( %d , &x); } int in(long long &x) { return scanf( %lld , &x); } int in(double &x) { return scanf( %lf , &x); } int in(pair<int, int> &p) { return scanf( %d%d , &p.first, &p.second); } int in(pair<long long, long long> &p) { return scanf( %lld%lld , &p.first, &p.second); } int in(pair<double, double> &p) { return scanf( %lf%lf , &p.first, &p.second); } int in(long double &a) { return scanf( %Lf , &a); } int in(int &x, long long &y) { return scanf( %d%lld , &x, &y); } int in(long long &x, int &y) { return scanf( %lld%d , &x, &y); } int in(int &x, int &y) { return scanf( %d%d , &x, &y); } int in(long long &x, long long &y) { return scanf( %lld%lld , &x, &y); } int in(int &n, char s[]) { return scanf( %d%d , &n, s); } int in(char a[], char b[]) { return scanf( %s%s , a, b); } int in(double &x, double &y) { return scanf( %lf%lf , &x, &y); } int in(int &x, int &y, int &z) { return scanf( %d%d%d , &x, &y, &z); } int in(long long &x, long long &y, long long &z) { return scanf( %lld%lld%lld , &x, &y, &z); } int in(double &x, double &y, double &z) { return scanf( %lf%lf%lf , &x, &y, &z); } int in(int &x, int &y, int &z, int &k) { return scanf( %d%d%d%d , &x, &y, &z, &k); } int in(long long &x, long long &y, long long &z, long long &k) { return scanf( %lld%lld%lld%lld , &x, &y, &z, &k); } int in(double &x, double &y, double &z, double &k) { return scanf( %lf%lf%lf%lf , &x, &y, &z, &k); } const int N = 3e5 + 10, M = 1e3 + 10, mod = 1e9 + 7; const double eps = 1e-6, Pi = acos(-1.0); int a[N], b[N], L[N], R[N], s[N]; vector<int> vc[N]; int check(int x, int y) { return (L[y] > R[x]); } int query(int x, int p) { x = max(0, x); p = max(0, p); int pos = upper_bound(vc[x].begin(), vc[x].end(), p) - vc[x].begin(); return pos; } int main() { int T, t; in(T); t = T; while (T--) { int n; in(n); for (int i = 1; i <= n; i++) { in(a[i]); b[i] = a[i]; } sort(b + 1, b + 1 + n); int m = unique(b + 1, b + 1 + n) - b; for (int i = 1; i <= n; i++) a[i] = lower_bound(b + 1, b + m, a[i]) - b, s[a[i]]++, vc[a[i]].push_back(i); for (int i = n; i >= 1; i--) L[a[i]] = i; for (int i = 1; i <= n; i++) s[i] += s[i - 1], R[a[i]] = i; m--; int l, r, ans = 0; l = r = 1; L[m + 1] = L[m]; R[m + 1] = R[m]; for (int i = 1; i <= m; i++) { while (r <= m && check(r, r + 1)) r++; int t = query(l - 1, L[l]) + (int)vc[r + 1].size() - query(r + 1, R[r]); ans = max(ans, s[r] - s[l - 1] + t); if (l == r) { for (int j = 0; j < vc[l].size(); j++) { ans = max(ans, (int)vc[l].size() + query(l - 1, vc[l][j]) - j); } } ans = max(ans, s[r] - s[l - 1] + query(l - 1, L[l])); if (r == m) break; l = r + 1; r++; } printf( %d n , n - ans); for (int i = 1; i <= n; i++) s[i] = 0, vc[i].clear(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int a = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) { a = a * 10 + c - 48; c = getchar(); } return a; } const int _ = 3e5 + 7, __ = _ * 19; vector<int> nxt[_]; int N, M, dep[_]; void qdep(int x, int p) { dep[x] = dep[p] + 1; for (auto &t : nxt[x]) if (t != p) qdep(t, x); } long long mrk[__], mn[__]; int ch[__][2], cnode; void mark(int x, long long v) { if (x) { mrk[x] = min(mrk[x] + v, mn[0]); mn[x] = min(mn[x] + v, mn[0]); } } void down(int x) { if (x && mrk[x]) { mark((ch[x][0]), mrk[x]); mark((ch[x][1]), mrk[x]); mrk[x] = 0; } } void mdf(int &x, int l, int r, int t, long long v, bool type) { if (!type && !x) { x = ++cnode; } if (l == r) { mn[x] = type ? v : min(mn[x], v); return; } down(x); ((l + r) >> 1) >= t ? mdf((ch[x][0]), l, ((l + r) >> 1), t, v, type) : mdf((ch[x][1]), ((l + r) >> 1) + 1, r, t, v, type); mn[x] = min(mn[(ch[x][0])], mn[(ch[x][1])]); } int merge(int p, int q) { if (!p || !q) { return p + q; } mn[p] = min(mn[p], mn[q]); down(p); down(q); ch[p][0] = merge(ch[p][0], ch[q][0]); ch[p][1] = merge(ch[p][1], ch[q][1]); return p; } vector<pair<int, int> > route[_]; int dfs(int x, int p) { long long vlsum = 0; int rt = 0; for (auto t : nxt[x]) if (t != p) { int R = dfs(t, x); mdf(R, 1, N, dep[x] + 1, mn[0], 1); long long v = mn[R]; mark(rt, v); mark(R, vlsum); vlsum = min(mn[0], vlsum + v); rt = merge(rt, R); } for (auto t : route[x]) mdf(rt, 1, N, t.first, vlsum + t.second, 0); if (x == 1) cout << (vlsum <= 1e16 ? vlsum : -1); return rt; } int main() { N = read(); M = read(); for (int i = 1; i < N; ++i) { int x = read(), y = read(); nxt[x].push_back(y); nxt[y].push_back(x); } qdep(1, 0); for (int i = 1; i <= M; ++i) { int x = read(), y = read(), w = read(); route[x].push_back(pair<int, int>(dep[y], w)); } memset(mn, 0x3f, sizeof(mn)); dfs(1, 0); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i, o = 0, z = 0; cin >> n; string s; cin >> s; for (i = 0; i < n; i++) { if (s[i] == 1 ) o++; else z++; } if (z != o) { cout << 1 << endl << s; } else { cout << 2 << endl; for (i = 0; i < n - 1; i++) cout << s[i]; cout << << s[n - 1]; } } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long gcd(long long x, long long y) { return y == 0 ? x : gcd(y, x % y); } long long logg(long long x, long long y) { if (x == 0) return -1; return logg(x / y, y) + 1; } long long poww(long long a, long long b, long long m) { if (b == 0) return 1; long long ans = 1; ans = poww(a, b >> 1, m); ans = (ans * ans) % m; if (b & 1) ans = (ans * a) % m; return ans; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n, k; cin >> n >> k; long long a[n], b[n]; for (long long i = 0; i < n; i++) cin >> a[i], b[i] = a[i]; sort(b, b + n, greater<long long>()); long long sum = 0; map<long long, long long> mp; for (long long i = 0; i < k; i++) sum += b[i], mp[b[i]]++; long long count = 0; vector<long long> ans; for (long long i = 0; i < n; i++) { if (k == 1) { ans.push_back(n - i); break; } if (mp.count(a[i])) count++, ans.push_back(count), count = 0, mp[a[i]]--, k--; else count++; if (mp[a[i]] == 0) mp.erase(a[i]); } cout << sum << n ; for (auto i : ans) cout << i << ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_TB_V
`define SKY130_FD_SC_LS__DECAPHETAP_TB_V
/**
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphetap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPB = 1'b0;
#60 VPWR = 1'b0;
#80 VGND = 1'b1;
#100 VPB = 1'b1;
#120 VPWR = 1'b1;
#140 VGND = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VPB = 1'b1;
#240 VGND = 1'b1;
#260 VPWR = 1'bx;
#280 VPB = 1'bx;
#300 VGND = 1'bx;
end
sky130_fd_sc_ls__decaphetap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, t, u, v; vector<long long> b; vector<pair<long long, long long> > a; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &x, &t); a.push_back(make_pair(x, t)); } scanf( %d , &v); a.push_back(make_pair(0, 0)); for (int i = 0; i < a.size(); ++i) a[i] = make_pair(a[i].first + v * a[i].second, -(a[i].first - v * a[i].second)); sort(a.rbegin(), a.rend()); u = v = 0; for (int i = 0; i < a.size(); ++i) { x = -a[i].second; t = upper_bound(b.begin(), b.end(), x) - b.begin(); if (t == b.size()) b.push_back(x); else b[t] = x; if (a[i] == make_pair(0ll, 0ll)) u = max(u, t); else v = max(v, t + 1); } printf( %d %d n , u, v); return 0; } |
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/05/2009
This FIFO module behaves similar to scfifo in legacy mode. It has an
output latency of 1 or 2 clock cycles and does not support look ahead
mode. Unlike scfifo this FIFO allows you to write to any of the byte
lanes before committing the word. This allows you to write the full
word in multiple clock cycles and then you assert the "push" signal to
commit the data. To read data out of the FIFO assert "pop" and wait
1 or 2 clock cycles for valid data to arrive.
Version 1.1
1.0 - Uses 'altsyncram' which will not be optimized away if the
FIFO inputs are grounded. This will need to be replaced
with inferred memory once Quartus II supports inferred
with byte enables (currently it instantiates multiple
seperate memories.
1.1 - Seperated the asynchronous reset into seperate async. and sync.
resets.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_with_byteenables (
clk,
areset,
sreset,
write_data,
write_byteenables,
write,
push,
read_data,
pop,
used,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // this impacts the width of the used port so it can't be local
parameter LATENCY = 1; // number of clock cycles after asserting 'pop' that valid data comes out
input clk;
input areset;
input sreset;
input [DATA_WIDTH-1:0] write_data;
input [(DATA_WIDTH/8)-1:0] write_byteenables;
input write;
input push; // when you have written to all the byte lanes assert this to commit the word (you can use it at the same time as the byte enables)
output wire [DATA_WIDTH-1:0] read_data;
input pop; // use this to read a word out of the FIFO
output wire [FIFO_DEPTH_LOG2:0] used;
output wire full;
output wire empty;
reg [FIFO_DEPTH_LOG2-1:0] write_address;
reg [FIFO_DEPTH_LOG2-1:0] read_address;
reg [FIFO_DEPTH_LOG2:0] internal_used;
wire internal_full;
wire internal_empty;
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
write_address <= 0;
end
else
begin
if (sreset)
begin
write_address <= 0;
end
else if (push == 1)
begin
write_address <= write_address + 1'b1;
end
end
end
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
read_address <= 0;
end
else
begin
if (sreset)
begin
read_address <= 0;
end
else if (pop == 1)
begin
read_address <= read_address + 1'b1;
end
end
end
// TODO: Change this to an inferrered RAM when Quartus II supports byte enables for inferred RAM
altsyncram the_dp_ram (
.clock0 (clk),
.wren_a (write),
.byteena_a (write_byteenables),
.data_a (write_data),
.address_a (write_address),
.q_b (read_data),
.address_b (read_address)
);
defparam the_dp_ram.operation_mode = "DUAL_PORT"; // simple dual port (one read, one write port)
defparam the_dp_ram.lpm_type = "altsyncram";
defparam the_dp_ram.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam the_dp_ram.power_up_uninitialized = "TRUE";
defparam the_dp_ram.byte_size = 8;
defparam the_dp_ram.width_a = DATA_WIDTH;
defparam the_dp_ram.width_b = DATA_WIDTH;
defparam the_dp_ram.widthad_a = FIFO_DEPTH_LOG2;
defparam the_dp_ram.widthad_b = FIFO_DEPTH_LOG2;
defparam the_dp_ram.width_byteena_a = (DATA_WIDTH/8);
defparam the_dp_ram.numwords_a = FIFO_DEPTH;
defparam the_dp_ram.numwords_b = FIFO_DEPTH;
defparam the_dp_ram.address_reg_b = "CLOCK0";
defparam the_dp_ram.outdata_reg_b = (LATENCY == 2)? "CLOCK0" : "UNREGISTERED";
always @ (posedge clk or posedge areset)
begin
if (areset)
begin
internal_used <= 0;
end
else
begin
if (sreset)
begin
internal_used <= 0;
end
else
begin
case ({push, pop})
2'b01: internal_used <= internal_used - 1'b1;
2'b10: internal_used <= internal_used + 1'b1;
default: internal_used <= internal_used;
endcase
end
end
end
assign internal_empty = (read_address == write_address) & (internal_used == 0);
assign internal_full = (write_address == read_address) & (internal_used != 0);
assign used = internal_used; // this signal reflects the number of words in the FIFO
assign empty = internal_empty; // combinational so it'll glitch a little bit
assign full = internal_full; // dito
endmodule
|
#include <bits/stdc++.h> using namespace std; struct B { int p, id; }; priority_queue<B> q; bool operator<(const B &a, const B &b) { return a.p < b.p; } int main() { string s; long long a, b, l, len, cost, i; B tmp; cin >> s; l = 0; len = s.size(); cost = 0; for (i = 0; i < len; i++) { if (s[i] == ( ) l++; else if (s[i] == ) ) l--; else { cin >> a >> b; tmp.p = b - a; tmp.id = i; q.push(tmp); s[i] = ) ; l--; cost += b; } if (l < 0) { if (q.empty()) break; tmp = q.top(); q.pop(); cost -= tmp.p; s[tmp.id] = ( ; l += 2; } } if (l != 0) cout << -1 << endl; else { cout << cost << endl; cout << s << endl; } while (!q.empty()) q.pop(); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int m, n, t, ans; pair<int, int> a[N]; vector<pair<int, int>> v; int main() { scanf( %d , &t); while (t--) { scanf( %d%d , &n, &m); ans = 0; v.clear(); for (int i = 1; i <= n; i++) scanf( %d , &a[i].first), a[i].second = i; sort(a + 1, a + n + 1); for (int i = 1; i < n; i++) { v.push_back(make_pair(a[i].second, a[i + 1].second)); ans += a[i].first + a[i + 1].first; } v.push_back(make_pair(a[n].second, a[1].second)); ans += a[n].first + a[1].first; if (v.size() > m || n == 2) { puts( -1 ); continue; } for (int i = v.size() + 1; i <= m; i++) { v.push_back(make_pair(a[1].second, a[2].second)); ans += a[1].first + a[2].first; } printf( %d n , ans); for (int i = 0; i < v.size(); i++) printf( %d %d n , v[i].first, v[i].second); } } |
#include <bits/stdc++.h> using namespace std; vector<int> e[3001], u; int v[3001], d[3001]; bool dfs(int x, int from) { if (v[x]++) { for (v[x] = -1; u.back() != x; u.pop_back()) v[u.back()] = -1; return true; } u.push_back(x); for (size_t i = 0; i < e[x].size(); i++) if (e[x][i] != from && dfs(e[x][i], x)) return true; u.pop_back(); return false; } int main() { int n, x, y; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } dfs(1, -1); u.clear(); for (int i = 1; i <= n; i++) if (v[i] < 0) u.push_back(i); for (size_t o = 0; o < u.size(); o++) { for (size_t i = 0; i < e[u[o]].size(); i++) { int t = e[u[o]][i]; if (~v[t]) { v[t] = -1; d[t] = d[u[o]] + 1; u.push_back(t); } } } for (int i = 1; i <= n; i++) printf( %d , d[i]); } |
#include <bits/stdc++.h> using namespace std; const long long N = 100010; inline long long read() { long long p = 0; long long f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { p = p * 10 + ch - 0 ; ch = getchar(); } return p * f; } long long a[N]; long long R[N << 1], L[N << 1]; int main() { long long n = read(); long long m = read(); if (n == 1) { printf( 0 n ); return 0; } for (long long i = 1; i <= m; i++) a[i] = read(); long long ans = 0; long long l = 1; long long r = n; for (long long i = 1; i <= n; i++) R[i] = i; for (long long i = 1; i <= m; i++) { long long x = a[i]; l++; r++; R[r] = R[r - 1]; R[l + x - 1] = R[l + x - 2]; } l++; r++; R[r] = R[r - 1]; for (long long i = l; i <= r; i++) ans += R[i] + 1; l = m + 2; r = n + m + 1; for (long long i = 1; i <= n; i++) L[i + m + 1] = i; for (long long i = 1; i <= m; i++) { long long x = a[i]; l--; r--; L[l] = L[l + 1]; L[l + x - 1] = L[l + x]; } l--; r--; L[l] = L[l + 1]; for (long long i = l; i <= r; i++) ans -= L[i]; return printf( %lld n , ans), 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_2_V
`define SKY130_FD_SC_MS__O22A_2_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22a_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, c, x, ans; cin >> t; while (t--) { ans = 0; x = -1; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { if (a[i] == 1) { if (x == -1) { x = i; } else { ans = ans + (i - x - 1); x = i; } } } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int vis[110000]; int st[110000], top; int main() { int n, m, i, j, k, x; scanf( %d , &n); if (n & 1) { puts( -1 ); return 0; } st[++top] = 0; x = n / 2; while (x) { st[++top] = x; vis[x] = 1; if (x + n >> 1 < n && !vis[x + n >> 1]) x = x + n >> 1; else x = x >> 1; } st[++top] = 0; while (top) printf( %d , st[top--]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, cnt = 0; cin >> n; long long ar[n]; for (i = 0; i < n; i++) cin >> ar[i]; for (i = 0; i < n; i++) { if (ar[i] % 2 != 0) cnt++; } cout << min(cnt, n - cnt); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */;
integer i, status;
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
for (i = 16; i > 0; i--)
if (mem0[i] !== i) begin
$write("%%Error: %d : GOT = %d EXP = %d\n", i, mem0[i], i);
status = 1;
end
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:26:28 AM
// Design Name:
// Module Name: Sgf_Multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sgf_Multiplication
// #(parameter SW = 24)
#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin : K1
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(SW)) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
/*RegisterAdd #(.W(SW)) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult[2*(SW/2)-1:0]),
.Q(Q_right[2*(SW/2)-1:0])
);//*/
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : K2
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
`ifdef PRESTO
always $display("Instanciacion: Mult de Francis, SW: %d",SW);
`endif
endmodule
|
#include <bits/stdc++.h> const int N = 2e5; using namespace std; const int SIZE = 26; int tot = 0, sub = 0; struct node { node* next[SIZE]; int strings; int tin, tout; node() { for (int i = 0; i < SIZE; i++) { next[i] = nullptr; } tin = 0; tout = 0; strings = 0; } }; void add(struct node* root, string key) { struct node* cur_v = root; for (size_t i = 0; i < key.length(); i++) { char c = key[i]; if (cur_v->next[c - a ] == nullptr) { cur_v->next[c - a ] = new node(); } cur_v = cur_v->next[c - a ]; } cur_v->strings++; } int t[4 * N + 1], mx_id[4 * N + 1]; void pull(int v) { if (t[2 * v] > t[2 * v + 1]) { t[v] = t[2 * v]; mx_id[v] = mx_id[2 * v]; } else { t[v] = t[2 * v + 1]; mx_id[v] = mx_id[2 * v + 1]; } } void upd(int v, int tl, int tr, int id, int x) { if (tl == tr) { t[v] = x; mx_id[v] = id; return; } int tm = (tl + tr) >> 1; if (id <= tm) { upd(2 * v, tl, tm, id, x); } else { upd(2 * v + 1, tm + 1, tr, id, x); } pull(v); } int pos = -1; int mx = 0; void calc(int v, int tl, int tr, int L, int R) { if (tl == L && tr == R) { if (mx < t[v]) { mx = t[v]; pos = mx_id[v]; } return; } int tm = (tl + tr) >> 1; if (R <= tm) { calc(2 * v, tl, tm, L, R); } else if (L > tm) { calc(2 * v + 1, tm + 1, tr, L, R); } else { calc(2 * v, tl, tm, L, tm); calc(2 * v + 1, tm + 1, tr, tm + 1, R); } } int t1, t2; void dfs(struct node* v, int d = 0) { t1++; v->tin = t1; if (v->strings > 0) { upd(1, 1, N, t1, d); } for (int i = 0; i < SIZE; i++) { if (v->next[i] == nullptr) { continue; } dfs(v->next[i], d + 1); } if (d < 1) { return; } v->tout = t1; if (v->strings == 0) { mx = 0; pos = 0; calc(1, 1, N, v->tin, v->tout); upd(1, 1, N, pos, 0); upd(1, 1, N, v->tin, d); sub += mx - d; } } char buf[N]; int main() { int n; scanf( %d , &n); string s; node* t = new node(); for (int i = 1; i <= n; i++) { scanf( %s , buf); s = buf; int sz = s.size(); tot += sz; add(t, s); } dfs(t); printf( %d n , tot - sub); } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:54 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title2_1/title2_stub.v
// Design : title2
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module title2(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [13:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, a[105][105]; int sum[2][105]; bool inv[2][105]; int main() { while (scanf( %d%d , &n, &m) == 2) { memset(inv, false, sizeof(inv)); memset(sum, 0, sizeof(sum)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %d , a[i] + j); sum[0][i] += a[i][j]; sum[1][j] += a[i][j]; } } while (1) { int idx = -1; for (int i = 0; i < n; i++) { if (sum[0][i] < 0) { idx = i; break; } } if (idx != -1) { inv[0][idx] ^= 1; sum[0][idx] = -sum[0][idx]; for (int i = 0; i < m; i++) { sum[1][i] -= a[idx][i]; a[idx][i] = -a[idx][i]; sum[1][i] += a[idx][i]; } continue; } for (int i = 0; i < m; i++) { if (sum[1][i] < 0) { idx = i; break; } } if (idx != -1) { inv[1][idx] ^= 1; sum[1][idx] = -sum[1][idx]; for (int i = 0; i < n; i++) { sum[0][i] -= a[i][idx]; a[i][idx] = -a[i][idx]; sum[0][i] += a[i][idx]; } continue; } break; } int cnt = 0; for (int i = 0; i < n; i++) if (inv[0][i]) cnt++; printf( %d , cnt); for (int i = 0; i < n; i++) if (inv[0][i]) printf( %d , i + 1); printf( n ); cnt = 0; for (int i = 0; i < m; i++) if (inv[1][i]) cnt++; printf( %d , cnt); for (int i = 0; i < m; i++) if (inv[1][i]) printf( %d , i + 1); printf( n ); } return 0; } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is used to create a reset from the clock locked signal. *
* *
******************************************************************************/
module altera_up_avalon_reset_from_locked_signal (
// Inputs
locked,
// Bidirectional
// Outputs
reset
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input locked;
// Bidirectionals
// Outputs
output reset;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset = ~locked;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
module AA(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input wire clock,
input wire reset,
input wire test_enable,
input wire afe_ctrl,
input wire cpu_wr,
input wire [4:0] cpu_addr,
input wire [7:0] cpu_wdata,
output wire [7:0] core_data,
output wire core_code_error,
output wire core_code_idle,
output wire [7:0] cpu_rdata
);
endmodule
module BB(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
input wire clock,
input wire reset,
input wire test_enable,
input wire core_code_idle,
input wire core_code_error,
input wire [7:0] core_data,
input wire [8:0] mbist_done,
input wire [8:0] mbist_fail,
output wire mbist_rst,
output reg mbist_test
);
endmodule
module TOP(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input afe_ctrl, // To AA_U of AA.v
input clock, // To AA_U of AA.v, ...
input [4:0] cpu_addr, // To AA_U of AA.v
input [7:0] cpu_wdata, // To AA_U of AA.v
input cpu_wr, // To AA_U of AA.v
input [8:0] mbist_done, // To BB_U of BB.v
input [8:0] mbist_fail, // To BB_U of BB.v
input reset, // To AA_U of AA.v, ...
input test_enable, // To AA_U of AA.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] cpu_rdata, // From AA_U of AA.v
output mbist_rst, // From BB_U of BB.v
output mbist_test // From BB_U of BB.v
// End of automatics
);
AA AA_U(/*AUTOINST*/
// Outputs
.core_data (core_data[7:0]),
.core_code_error (core_code_error),
.core_code_idle (core_code_idle),
.cpu_rdata (cpu_rdata[7:0]),
// Inputs
.clock (clock),
.reset (reset),
.test_enable (test_enable),
.afe_ctrl (afe_ctrl),
.cpu_wr (cpu_wr),
.cpu_addr (cpu_addr[4:0]),
.cpu_wdata (cpu_wdata[7:0]));
BB BB_U(/*AUTOINST*/
// Outputs
.mbist_rst (mbist_rst),
.mbist_test (mbist_test),
// Inputs
.clock (clock),
.reset (reset),
.test_enable (test_enable),
.core_code_idle (core_code_idle),
.core_code_error (core_code_error),
.core_data (core_data[7:0]),
.mbist_done (mbist_done[8:0]),
.mbist_fail (mbist_fail[8:0]));
// Local Variables:
// verilog-library-directories:(".")
// End:
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; cin >> n >> m >> k; if (n <= m && n <= k) { cout << YES ; } else cout << NO ; return 0; } |
/*******************************************************
* File Name : hdl/ks16.v
* Module Name : Karatsuba Multiplier
* Author : Chester Rebeiro
* Institute : Indian Institute of Technology, Madras
* Creation Time :
* Comment : Automatically generated from ks.c
********************************************************/
`ifndef __KS_16_V__
`define __KS_16_V__
//`include "ks8.v"
module Bks16(a, b, d);
input wire [15:0] a;
input wire [15:0] b;
output wire [30:0] d;
wire [14:0] m1;
wire [14:0] m2;
wire [14:0] m3;
wire [7:0] ahl;
wire [7:0] bhl;
Bks8 ksm1(a[7:0], b[7:0], m2);
Bks8 ksm2(a[15:8], b[15:8], m1);
assign ahl[7:0] = a[15:8] ^ a[7:0];
assign bhl[7:0] = b[15:8] ^ b[7:0];
Bks8 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[09] = m2[09] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[10] = m2[10] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[11] = m2[11] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[12] = m2[12] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[13] = m2[13] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[14] = m2[14] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[15] = m1[07] ^ m2[07] ^ m3[07];
assign d[16] = m1[08] ^ m2[08] ^ m3[08] ^ m1[00];
assign d[17] = m1[09] ^ m2[09] ^ m3[09] ^ m1[01];
assign d[18] = m1[10] ^ m2[10] ^ m3[10] ^ m1[02];
assign d[19] = m1[11] ^ m2[11] ^ m3[11] ^ m1[03];
assign d[20] = m1[12] ^ m2[12] ^ m3[12] ^ m1[04];
assign d[21] = m1[13] ^ m2[13] ^ m3[13] ^ m1[05];
assign d[22] = m1[14] ^ m2[14] ^ m3[14] ^ m1[06];
assign d[23] = m1[07];
assign d[24] = m1[08];
assign d[25] = m1[09];
assign d[26] = m1[10];
assign d[27] = m1[11];
assign d[28] = m1[12];
assign d[29] = m1[13];
assign d[30] = m1[14];
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 4e5 + 10; const int M = 22; class SegmentTree { public: int ql, qr, qx; int xorv[N]; int sumv[N]; void init() { memset((xorv), (0), sizeof(xorv)); memset((sumv), (0), sizeof(sumv)); } void set(int ql, int qr, int qx) { this->ql = ql; this->qr = qr; this->qx = qx; } void pushdown(int o, int len) { if (xorv[o]) { xorv[o << 1] ^= 1; xorv[o << 1 | 1] ^= 1; sumv[o << 1] = (len - len / 2) - sumv[o << 1]; sumv[o << 1 | 1] = len / 2 - sumv[o << 1 | 1]; xorv[o] = 0; } } void maintain(int o) { sumv[o] = sumv[o << 1] + sumv[o << 1 | 1]; } int query(int l, int r, int o = 1) { if (ql <= l && qr >= r) { return sumv[o]; } int mid = (l + r) >> 1; pushdown(o, r - l + 1); int ans = 0; if (ql <= mid) ans += query(l, mid, o << 1); if (qr > mid) ans += query(mid + 1, r, o << 1 | 1); return ans; } void update(int l, int r, int o = 1) { if (ql <= l && qr >= r) { xorv[o] ^= 1; sumv[o] = r - l + 1 - sumv[o]; return; } int mid = (l + r) >> 1; pushdown(o, r - l + 1); if (ql <= mid) update(l, mid, o << 1); if (qr > mid) update(mid + 1, r, o << 1 | 1); maintain(o); } } st[M]; int main() { for (int i = 0; i < M; i++) st[i].init(); int n; cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; for (int j = 0; j < M; j++) { if (x >> j & 1) st[j].set(i, i, 1), st[j].update(1, n); } } int q; cin >> q; while (q--) { int op; cin >> op; if (op == 1) { int l, r; cin >> l >> r; long long ans = 0; for (int i = 0; i < M; i++) { st[i].set(l, r, 0); ans += (1LL << i) * st[i].query(1, n); } cout << ans << n ; } else { int l, r, x; cin >> l >> r >> x; for (int i = 0; i < M; i++) { if (x >> i & 1) st[i].set(l, r, 1), st[i].update(1, n); } } } return 0; } |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); char arr[n][n + 1]; int i, j, k; int sum = 0; int count; for (i = 0; i < n; i++) scanf( %s , arr[i]); for (i = 0; i < n; i++) { count = 0; for (j = 0; j < n; j++) { if (arr[i][j] == C ) count++; } sum += ((count * (count - 1)) / 2); } for (i = 0; i < n; i++) { count = 0; for (j = 0; j < n; j++) { if (arr[j][i] == C ) count++; } sum += ((count * (count - 1)) / 2); } printf( %d , sum); return 0; } |
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