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#include <bits/stdc++.h> using namespace std; namespace mincostflow { struct edge { int to, cap, cost, rev; edge(int to = 0, int cap = 0, int cost = 0, int rev = 0) : to(to), cap(cap), cost(cost), rev(rev) {} }; vector<edge> g[7000]; int dist[7000], q[7000 * 2]; int frome[7000], fromv[7000]; bool inq[7000]; int s, t; void add_edge(int from, int to, int cap, int cost) { g[from].push_back(edge(to, cap, cost, g[to].size())); g[to].push_back(edge(from, 0, -cost, g[from].size() - 1)); } bool dij() { for (int i = 0; i <= t; i++) dist[i] = 1000000000; dist[s] = 0; q[0] = s; inq[s] = 1; int head = 0, tail = 1; while (head != tail) { int now = q[head++]; if (head == 7000 + 1) head = 0; for (int i = 0; i < g[now].size(); i++) { edge &e = g[now][i]; if (e.cap && dist[e.to] > dist[now] + e.cost) { dist[e.to] = dist[now] + e.cost; frome[e.to] = i; fromv[e.to] = now; if (!inq[e.to]) { if (dist[e.to] < dist[q[head]]) { head--; if (head == -1) head = 7000; q[head] = e.to; } else { q[tail++] = e.to; if (tail == 7000 + 1) tail = 0; } } } } inq[now] = 0; } return dist[t] != 1000000000; } int augment() { int c = 1000000000, ret = 0; for (int i = t; i != s; i = fromv[i]) c = min(c, g[fromv[i]][frome[i]].cap); for (int i = t; i != s; i = fromv[i]) { edge &e = g[fromv[i]][frome[i]]; ret += c * e.cost; e.cap -= c; g[e.to][e.rev].cap += c; } return ret; } int mcf() { int ans = 0; while (dij()) ans += augment(); return ans; } }; // namespace mincostflow int a[100][100]; int id[100][100]; int n, m, cnt; int main() { using namespace mincostflow; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); id[i][j] = ++cnt; } } s = ++cnt; t = ++cnt; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if ((i + j) & 1) add_edge(s, id[i][j], 1, 0); else add_edge(id[i][j], t, 1, 0); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if ((i + j) % 2 == 0) continue; if (id[i][j - 1]) add_edge(id[i][j], id[i][j - 1], 1, (a[i][j] != a[i][j - 1])); if (id[i][j + 1]) add_edge(id[i][j], id[i][j + 1], 1, (a[i][j] != a[i][j + 1])); if (id[i - 1][j]) add_edge(id[i][j], id[i - 1][j], 1, (a[i][j] != a[i - 1][j])); if (id[i + 1][j]) add_edge(id[i][j], id[i + 1][j], 1, (a[i][j] != a[i + 1][j])); } } printf( %d n , mcf()); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <class T> inline T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <class T> inline T sqr(T x) { return x * x; } template <class T> T power(T N, T P) { return (P == 0) ? 1 : N * power(N, P - 1); } long long toInt64(string s) { long long r = 0; istringstream sin(s); sin >> r; return r; } double LOG(long long N, long long B) { return (log10l(N)) / (log10l(B)); } string itoa(long long a) { if (a == 0) return 0 ; string ret; for (long long i = a; i > 0; i = i / 10) ret.push_back((i % 10) + 48); reverse(ret.begin(), ret.end()); return ret; } vector<string> token(string a, string b) { const char *q = a.c_str(); while (count(b.begin(), b.end(), *q)) q++; vector<string> oot; while (*q) { const char *e = q; while (*e && !count(b.begin(), b.end(), *e)) e++; oot.push_back(string(q, e)); q = e; while (count(b.begin(), b.end(), *q)) q++; } return oot; } template <class T> inline T __cin() { T ret; cin >> ret; return ret; } int isvowel(char s) { s = tolower(s); if (s == a || s == e || s == i || s == o || s == u ) return 1; return 0; } int isupper(char s) { if (s >= A and s <= Z ) return 1; return 0; } int Set(int N, int pos) { return N = N | (1 << pos); } int reset(int N, int pos) { return N = N & ~(1 << pos); } int check(int N, int pos) { return (N & (1 << pos)); } int toggle(int N, int pos) { if (check(N, pos)) return N = reset(N, pos); return N = Set(N, pos); } void pbit(int N) { printf( ( ); for (int i = 10; i >= 0; i--) { bool x = check(N, i); cout << x; } puts( ) ); } int main() { int n = 9; cin >> n; long long ans = -1; for (int i = max(n - 100, 1); i <= n; i++) { for (int j = max(n - 100, 1); j <= n; j++) { for (int k = max(n - 100, 1); k <= n; k++) { long long lc = lcm((long long)i, lcm((long long)j, (long long)k)); ans = max(ans, lc); } } } cout << ans << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Sun Jun 18 18:41:14 2017
// Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/MartjnMirandaMe/clkdiv/clkdiv.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_out1, reset, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */;
output clk_out1;
input reset;
output locked;
input clk_in1;
endmodule
|
module SimpleRam
#(parameter BUS_WIDTH = 8, parameter SIZE = 512, parameter ADDRESS_WIDTH = 32)
(
input wire clk,
input wire reset,
input wire [ADDRESS_WIDTH-1:0] addrA,
input wire [BUS_WIDTH-1:0] dataIn,
input wire writeEnable,
input wire [ADDRESS_WIDTH-1:0] addrB,
output reg [BUS_WIDTH-1:0] outA,
output reg [BUS_WIDTH-1:0] outB,
output reg busyA,
output reg busyB
);
reg [BUS_WIDTH-1:0] memory[0:SIZE-1];
reg [BUS_WIDTH-1:0] lastAddrA = 0;
reg [BUS_WIDTH-1:0] lastAddrB = 0;
// Counter variable for initialization
integer i;
// For debugging
always @(posedge reset) $writememh("ram.hex", memory);
always @(clk)
begin
if(writeEnable)
begin
outA <= dataIn;
memory[addrA] <= dataIn;
end
if(addrA != lastAddrA)
busyA <= 1;
if(addrB != lastAddrB)
busyA <= 1;
if(~writeEnable)
begin
busyA <= 0;
outA <= memory[addrA];
busyB <= 0;
outB <= memory[addrB];
end
lastAddrA = addrA;
lastAddrB = addrB;
if(reset)
begin
busyA <= 1;
busyB <= 1;
outA <= 0;
outB <= 0;
for(i = 0; i < SIZE; i=i+1)
memory[i] <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[100100][102]; int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin.tie(0); long long n; cin >> n; int ans = 0; while (n) { ans += (n % 10 == 7 || n % 10 == 4); n /= 10; } cout << (ans == 4 || ans == 7 ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long A, B, C, D, X, Y; inline long long gcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long res = gcd(b, a % b, x, y); long long t = x; x = y; y = t - (a / b) * y; return res; } int main() { scanf( %lld %lld %lld , &A, &B, &C); C = -C; D = gcd(A, B, X, Y); if (C % D) puts( -1 ); else { C /= D; printf( %lld %lld n , X * C, Y * C); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; k++; vector<int> v; for (int i = 0, x; i < n; i++) { cin >> x; v.push_back(x); } int lo = 1; int hi = 1000000000; while (lo < hi) { int me = (lo + hi) / 2; bool can = 0; for (int i = 0; i + k - 1 < n; i++) { if (v[i + k - 1] - v[i] <= me) can = 1; } if (!can) lo = me + 1; else hi = me; } int x = -10; for (int i = 0; i + k - 1 < n; i++) { if (v[i + k - 1] - v[i] <= lo) x = (v[i] + v[i + k - 1]) / 2; } cout << x << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_PP_BLACKBOX_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Sun Oct 2 14:00:21 2016
// Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/rmaratos/private/f16/545/camera_demo/camera_demo.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v
// Design : blk_mem_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module blk_mem_gen_0(clka, wea, addra, dina, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[18:0],dina[11:0],clkb,addrb[18:0],doutb[11:0]" */;
input clka;
input [0:0]wea;
input [18:0]addra;
input [11:0]dina;
input clkb;
input [18:0]addrb;
output [11:0]doutb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_PP_V
/**
* isolatch: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__isolatch (
Q ,
D ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_isolatch_pp$PKG$sN isolatch_pp0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, KAPWR, VGND, VPWR);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const int INF = 1034567890; const long long LL_INF = 1234567890123456789ll; const double PI = acos(-1); const long double ERR = 1E-10; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int cnt = 1; int place{}; int ph; for (auto i{0}; i < 9; i++) { if (n >= cnt) { place = cnt; } cnt *= 3; } place *= 3; ph = place; int res = 0; if (n > place / 2) { res = place; } else { place /= 3; res += place; n -= place; while (n && place) { place /= 3; if (n > place / 2) { n -= place; res += place; } } } cout << res << endl; } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_wdq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Write Decomposition Queue Buffer
// Top level Module: jbi_min_wdq_buf
// Where Instantiated: jbi_min_wdq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_wdq_buf(/*AUTOARG*/
// Outputs
wdq_rdata,
// Inputs
clk, arst_l, testmux_sel, hold, rst_tri_en, wdq_wr_en, wdq_rd_en,
wdq_waddr, wdq_raddr, wdq_wdata, wdq_wdata_ecc0, wdq_wdata_ecc1,
wdq_wdata_ecc2, wdq_wdata_ecc3
);
input clk;
input arst_l;
input testmux_sel;
input hold;
input rst_tri_en;
input wdq_wr_en;
input wdq_rd_en;
input [`JBI_WDQ_ADDR_WIDTH-1:0] wdq_waddr;
input [`JBI_WDQ_ADDR_WIDTH-1:0] wdq_raddr;
input [127:0] wdq_wdata;
input [6:0] wdq_wdata_ecc0;
input [6:0] wdq_wdata_ecc1;
input [6:0] wdq_wdata_ecc2;
input [6:0] wdq_wdata_ecc3;
output [`JBI_WDQ_WIDTH-1:0] wdq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_WDQ_WIDTH-1:0] wdq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [3:0] dangle;
//
// Code start here
//
jbi_1r1w_16x160 u_wdq_buf
(// outputs
.dout ( {dangle[3:0],
wdq_rdata} ),
// read inputs
.rdclk (clk),
.read_en (wdq_rd_en),
.rd_adr (wdq_raddr),
// write inputs
.wrclk (clk),
.wr_en (wdq_wr_en),
.wr_adr (wdq_waddr),
.din ( {4'b0000,
wdq_wdata_ecc3,
wdq_wdata_ecc2,
wdq_wdata_ecc1,
wdq_wdata_ecc0,
wdq_wdata} ),
// other inputs
.rst_l (arst_l),
.hold (hold),
.testmux_sel (testmux_sel),
.rst_tri_en (rst_tri_en)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/mem/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:53:59 05/06/2015
// Design Name:
// Module Name: plaintext_ip
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module plaintext_ip(
plaintxt,
left_out,
right_out,
select
);
input [64:1] plaintxt;
output [32:1] left_out;
output [32:1] right_out;
input select;
reg [64:1] ip;
assign right_out= ip[32:1] ; // right part
assign left_out= ip[64:33]; // left part
always@(select)
begin
if(select ==1)
begin
ip[1]<= plaintxt[58];
ip[2]<= plaintxt[50];
ip[3]<= plaintxt[42];
ip[4]<= plaintxt[34];
ip[5]<= plaintxt[26];
ip[6]<= plaintxt[18];
ip[7]<= plaintxt[10];
ip[8]<= plaintxt[2];
ip[9]<= plaintxt[60];
ip[10]<= plaintxt[52];
ip[11]<= plaintxt[44];
ip[12]<= plaintxt[36];
ip[13]<= plaintxt[28];
ip[14]<= plaintxt[20];
ip[15]<= plaintxt[12];
ip[16]<= plaintxt[4];
ip[17]<= plaintxt[62];
ip[18]<= plaintxt[54];
ip[19]<= plaintxt[46];
ip[20]<= plaintxt[38];
ip[21]<= plaintxt[30];
ip[22]<= plaintxt[22];
ip[23]<= plaintxt[14];
ip[24]<= plaintxt[6];
ip[25]<= plaintxt[64];
ip[26]<= plaintxt[56];
ip[27]<= plaintxt[48];
ip[28]<= plaintxt[40];
ip[29]<= plaintxt[32];
ip[30]<= plaintxt[24];
ip[31]<= plaintxt[16];
ip[32]<= plaintxt[8];
ip[33]<= plaintxt[57];
ip[34]<= plaintxt[49];
ip[35]<= plaintxt[41];
ip[36]<= plaintxt[33];
ip[37]<= plaintxt[25];
ip[38]<= plaintxt[17];
ip[39]<= plaintxt[9];
ip[40]<= plaintxt[1];
ip[41]<= plaintxt[59];
ip[42]<= plaintxt[51];
ip[43]<= plaintxt[43];
ip[44]<= plaintxt[35];
ip[45]<= plaintxt[27];
ip[46]<= plaintxt[19];
ip[47]<= plaintxt[11];
ip[48]<= plaintxt[3];
ip[49]<= plaintxt[61];
ip[50]<= plaintxt[53];
ip[51]<= plaintxt[45];
ip[52]<= plaintxt[37];
ip[53]<= plaintxt[29];
ip[54]<= plaintxt[21];
ip[55]<= plaintxt[13];
ip[56]<= plaintxt[5];
ip[57]<= plaintxt[63];
ip[58]<= plaintxt[55];
ip[59]<= plaintxt[47];
ip[60]<= plaintxt[39];
ip[61]<= plaintxt[31];
ip[62]<= plaintxt[23];
ip[63]<= plaintxt[15];
ip[64]<= plaintxt[7];
end
else
ip[64:1] <= 64'bx;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e5 + 10; const int LG = 20; int power(int a, int b) { int res = 1; while (b > 0) { if (b & 1) { res = 1LL * res * a % mod; } a = 1LL * a * a % mod; b >>= 1; } return res; } int seg[4 * N], lazy[4 * N]; void update(int node, int start, int end, int l, int r, int val) { if (lazy[node]) { seg[node] += lazy[node]; if (start != end) { lazy[node << 1] += lazy[node]; lazy[node << 1 | 1] += lazy[node]; } lazy[node] = 0; } if (start > end || r < start || end < l) return; if (l <= start && end <= r) { seg[node] += val; if (start != end) { lazy[node << 1] += val; lazy[node << 1 | 1] += val; } return; } int mid = (start + end) >> 1; update(node << 1, start, mid, l, r, val); update(node << 1 | 1, mid + 1, end, l, r, val); seg[node] = min(seg[node << 1], seg[node << 1 | 1]); } int query(int node, int start, int end, int l, int r) { if (lazy[node]) { seg[node] += lazy[node]; if (start != end) { lazy[node << 1] += lazy[node]; lazy[node << 1 | 1] += lazy[node]; } lazy[node] = 0; } if (start > end || r < start || end < l) return 1e9; if (l <= start && end <= r) { return seg[node]; } int mid = (start + end) >> 1; return min(query(node << 1, start, mid, l, r), query(node << 1 | 1, mid + 1, end, l, r)); } int main() { int n, m, a[N], ans = 0, idx = 0; vector<pair<int, int> > lft[N], rght[N]; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); update(1, 1, n, i, i, a[i]); } for (int i = 1; i <= m; i++) { int l, r; scanf( %d %d , &l, &r); lft[r].push_back({l, i}); rght[l].push_back({r, i}); } for (int i = 1; i <= n; i++) { int val = a[i] - query(1, 1, n, 1, i - 1); if (val > ans) { idx = i; ans = val; } for (auto l : lft[i]) { update(1, 1, n, l.first, i, -1); } } memset(seg, 0, sizeof(seg)); memset(lazy, 0, sizeof(lazy)); for (int i = 1; i <= n; i++) { update(1, 1, n, i, i, a[i]); } for (int i = n; i >= 1; i--) { int val = a[i] - query(1, 1, n, i + 1, n); if (val > ans) { idx = -i; ans = val; } for (auto r : rght[i]) { update(1, 1, n, i, r.first, -1); } } printf( %d n , ans); vector<int> res; if (idx > 0) { for (int i = 1; i < idx; i++) { for (auto j : lft[i]) { res.push_back(j.second); } } } else if (idx < 0) { for (int i = n; i > abs(idx); i--) { for (auto j : rght[i]) { res.push_back(j.second); } } } printf( %d n , res.size()); for (int pp : res) { printf( %d , pp); } return 0; } |
#include <bits/stdc++.h> int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); int flag; if (n & 1) { flag = 2; for (int i = 1, tmp; i <= n; i++) { scanf( %1d , &tmp); if ((i & 1) && (tmp & 1)) flag = 1; } printf( %d n , flag); } else { flag = 1; for (int i = 1, tmp; i <= n; i++) { scanf( %1d , &tmp); if (!(i & 1) && !(tmp & 1)) flag = 2; } printf( %d n , flag); } } } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, n, i, t, r = 0; while (cin >> t) { for (i = 0; i < t; i++) { cin >> a >> b >> n; if (n % 3 == 1) cout << b << endl; else if (n % 3 == 0) cout << a << endl; else { r = a ^ b; cout << r << endl; r = 0; } } } return 0; } |
//axi_sdb.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:axi_sdb
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/12/23
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
/*
Log
5/14/2013
-Initial Commit
*/
`timescale 1 ns/1 ps
`include "axi_defines.v"
`include "project_defines.v"
`define SDB_ROM_SIZE_OF_HEADER 16
`define SDB_ROM_SIZE_OF_DEV 16
module axi_sdb #(
input clk,
input rst_n,
//Write Address Channel
input i_awvalid,
output reg o_awready,
input [31:0] i_awaddr,
input [2:0] i_awprot, //Protection data not used
//Write Data Channel
input i_wvalid,
output reg o_wready,
input [31:0] i_wdata,
input [3:0] i_wstrb, //Strobe Data Ignored now
//Write Response Channel
output reg o_bvalid,
input i_bready,
output reg [1:0] o_bresp,
//Read Address Channel
input i_arvalid,
output reg o_arready,
input [31:0] i_araddr,
input [2:0] i_arprot, //Protection data not used
//Read Data Channel
output reg o_rvalid,
input i_rready,
output [31:0] o_rdata,
output reg [2:0] o_rresp
);
//Local Parameters
localparam IDLE = 0;
localparam WRITE = 1;
localparam WRITE_RESP = 2;
localparam READ = 1;
localparam READ_RESP = 2;
parameter SDB_ROM_SIZE = `SDB_ROM_SIZE_OF_HEADER + (`SDB_NRECS * `SDB_ROM_SIZE_OF_DEV);
reg [31:0] sdb [(SDB_ROM_SIZE - 1):0];
initial begin
$readmemh(`SDB_INPUT_FILE, sdb, 0, SDB_ROM_SIZE - 1);
end
//Registers/Wires
reg [3:0] r_wr_state;
reg [3:0] r_rd_state;
reg r_wr_ready;
wire w_wr_request;
reg r_wr_data_ready;
reg r_wr_ack;
reg r_wr_illegal;
reg r_rd_ready;
wire w_rd_request;
reg r_rd_illegal;
//Submodules
//Asynchronous Logic
//request for when the master would like to write
assign w_wr_request = (((r_wr_state == WRITE) && (i_wvalid || r_wr_data_ready)) ||
(i_wvalid && i_awvalid));
//request for when the master would like a read
assign w_rd_request = ((r_rd_state == READ) || (i_arvalid && o_arready));
//Synchronous Logic
//Write Path
always @ (posedge clk) begin
if (!rst_n) begin
o_awready <= 0;
r_wr_ready <= 0;
r_wr_data_ready <= 0;
o_wready <= 0;
o_bvalid <= 0;
o_bresp <= 0;
r_wr_state <= IDLE;
end
else begin
//Strobes
o_awready <= 0;
o_wready <= 0;
o_bvalid <= 0;
if (r_wr_ack) begin
o_wr_data_ready <= 0;
o_wr_ready <= 0;
end
case (r_wr_state)
IDLE: begin
//both of the ready's are high
o_bresp <= AXI_RESP_OKAY;
o_awready <= 1;
o_wready <= 1;
o_wr_data_ready <= 0;
o_wr_ready <= 0;
//Three conditions
//1: both i_awready and i_wready goes high -> WRITE, (kicks off a write)
if (i_awvalid && i_wvalid) begin
o_wr_data_ready <= 1;
o_wr_ready <= 1;
r_wr_state <= WRITE;
end
//2: i_awready goes high with a new address -> WRITE
else if (i_awvalid) begin
r_wr_state <= WRITE;
end
//3: i_wready goe high with a new peice of data -> WAIT_FOR_ADDRESS
else if (i_wvalid) begin
o_wr_data_ready <= 1;
r_wr_state <= WAIT_FOR_ADDRESS;
end
end
WAIT_FOR_ADDRESS: begin
o_awready <= 1;
if (i_awvalid) begin
o_wr_ready <= 1;
r_wr_state <= WRITE;
end
end
WRITE: begin
o_bresp <= AXI_RESP_OKAY;
if (r_wr_ack) begin
if (r_wr_illegal) begin
o_bresp <= AXI_RESP_SLVERR;
end
r_wr_state <= WRITE_RESP;
end
end
WRITE_RESP: begin
o_bvalid <= 1;
if (i_bready) begin
r_wr_state <= IDLE;
end
end
default: begin
r_wr_state <= IDLE;
end
endcase
end
end
//Read Path
always @ (posedge clk) begin
if (!rst_n) begin
o_arready <= 0;
o_rvalid <= 0;
o_rdata <= 0;
o_rresp <= 0;
end
else begin
//Strobes
o_arready <= 0;
o_rvalid <= 0;
case (r_rd_state)
IDLE: begin
//This is already high so it responds to request faster
o_arready <= 1;
if (i_arvalid) begin
//Host has requested a read
r_rd_state <= READ;
end
end
READ: begin
if (r_rd_ready) begin
r_rd_state <= READ_RESP;
o_rresp <= AXI_RESP_OKAY;
if (r_rd_illegal) begin
//There was an error (most likey address out of range)
o_rresp <= AXI_RESP_SLVERR;
end
end
end
READ_RESP: begin
o_rvalid <= 1;
if (i_rready) begin
r_rd_state <= IDLE;
end
end
default: begin
r_rd_state <= IDLE;
end
endcase
end
end
//----------------------------------------------------------------------------
//User Spcific Code Here
//----------------------------------------------------------------------------
//Local Parameters
localparam ADDR0 = 0;
localparam ADDR1 = 1;
localparam ADDR2 = 2;
//Registers/Wires
reg [31:0] r_data0;
reg [31:0] r_data1;
reg [31:0] r_data2;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Custom Code here
always @ (posedge clk) begin
if (!rst_n) begin
//Axi Write Bus Interface
r_wr_ready <= 0;
r_wr_illegal <= 0;
r_wr_ack <= 0;
//Axi Read Bus Interface
r_rd_ready <= 0;
r_rd_illegal <= 0;
o_rdata <= 0;
//Initialize Data
r_data0 <= 32'h00000000;
r_data1 <= 32'h00000000;
r_data2 <= 32'h00000000;
end
else begin
//Strobes
r_wr_illegal <= 0;
r_wr_ack <= 0;
r_rd_ready <= 0;
r_rd_illegal <= 0;
/*Note: Write ready can be held low indefinetly when the user SM is
not ready to read new data
*/
r_wr_ready <= 1;
//Write Data
if (w_wr_request) begin
$display ("ALS: User Writing to addr: %h data: %h",
i_awaddr,
i_wdata);
case (i_awaddr) begin
ADDR0: begin
r_data0 <= i_wdata;
end
ADDR1: begin
r_data1 <= i_wdata;
end
ADDR2: begin
r_data2 <= i_wdata;
end
default: begin
$display ("\tALS: Illegal Address!");
r_wr_illegal <= 1;
end
endcase
r_wr_ack <= 1;
end
//Read Data
if (w_rd_request) begin
$display ("ALS: Read from addres: %h", i_awaddr);
case (i_araddr)
ADDR0: begin
o_rdata <= r_data0;
end
ADDR1: begin
o_rdata <= r_data1;
end
ADDR2: begin
o_rdata <= r_data2;
end
default: begin
$display ("\tALS: Illegal Address!");
o_rdata <= 32'h00000000;
r_rd_illegal <= 1;
end
endcase
/*Note: r_rd_ready can be held low indefinetly when the data is not
ready to send to the host*/
r_rd_ready <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; multiset<int> ms; const int MAXN = 1000000; int pos[MAXN], a[MAXN], b[MAXN], st[MAXN]; int n, i, j, k, ans; int main() { scanf( %d , &n); for (i = 1; i <= n; ++i) { scanf( %d , &a[i]); pos[a[i]] = i; } for (j = 1; j <= n; ++j) { scanf( %d , &b[j]); int diff = j - pos[b[j]]; st[j] = diff; ms.insert(diff); } for (i = 0; i < n; ++i) { ans = n; multiset<int>::iterator it = ms.lower_bound(i); if (it != ms.end()) ans = min(ans, abs(*(it)-i)); if (it != ms.begin()) ans = min(ans, abs(*(--it) - i)); cout << ans << endl; ms.erase(ms.find(st[i + 1])); int num = b[i + 1]; ms.insert((i + n + 1) - pos[num]); } } |
#include <bits/stdc++.h> using namespace std; int a[8]; int main() { int n, m; cin >> n >> m; int xx = n; int kk = m; int ans = 0; int len1 = 1, len2 = 1; for (int b = 7; b < n; b *= 7) len1++; for (int b = 7; b < m; b *= 7) len2++; if (len2 + len1 > 7) { cout << 0; return 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int z = i, f = 0; f != len1; f++, z /= 7) { int x = z % 7; a[x]++; } for (int z = j, f = 0; f != len2; f++, z /= 7) { int x = z % 7; a[x]++; } bool ok = false; for (int d = 0; d < 8; d++) if (a[d] > 1) ok = true; if (ok == false) ans++; for (int d = 0; d < 8; d++) a[d] = 0; } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { int a; cin >> a; if (a < 4) { cout << 1 << endl; } else { if (a % 2 == 0) { cout << (a / 2) << endl; } else { cout << ((a - 1) / 2) << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int T; cin >> T; for (int t = 0; t < T; ++t) { long long int n; long long int a, b; cin >> n >> a >> b; string s; cin >> s; long long int bc = n * (a + b) + b; bool ftram = true; bool ztram = true; long long int fzero = -1; long long int nc = 0; for (int i = 0; i < n; ++i) { if (s[i] == 0 ) { if (!ztram) { fzero = i; ztram = true; } } else { if (ztram) { if (ftram) { nc += a; ftram = false; } else { nc += min(2 * a, (i - fzero - 1) * b); } ztram = false; nc += b; } nc += b; } } if (!ftram) nc += a; cout << bc + nc << endl; } } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module daq2_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio,
spi_dir);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
output spi_dir;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
assign spi_miso = spi_sdio;
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[200001]; bool vis[200001]; int en = -1; int a[200005], b[200005]; void dfs(int x) { vis[x] = 1; for (auto it = adj[x].begin(); it != adj[x].end(); ++it) { if (!vis[*it]) { dfs(*it); } } if (en == -1) en = x; } int main() { int n, m, i, k, l = 0, ans = 0; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; adj[i].push_back(a[i]); } int flag = 0; for (i = 1; i <= n; i++) { cin >> b[i]; if (b[i]) flag++; } if (!flag) ans++; else if (flag % 2 == 0) ans++; int temp = -1; for (i = 1; i <= n; i++) { if (!vis[i]) { temp = en; en = -1; dfs(i); adj[en].clear(); if (temp > 0) { ans++; adj[temp].push_back(i); } } } if (temp != -1) { adj[en].push_back(1); ans++; } cout << ans; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( -O2 ) using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } const int LIM = 1e5 + 5, MOD = 1e9 + 7; int t, n, m, k, x, y; int is_com[LIM]; vector<int> pr; void sieve() { for (int i = 2; i < LIM; i++) { if (!is_com[i]) pr.push_back(i); for (auto &it : pr) { if (it * i >= n) break; is_com[i * it] = 1; if (i % it == 0) { break; } } } } long long int powm(long long int x, long long int pw, long long int MOD) { long long int res = 1; while (pw) { if (pw & 1LL) res = ((res * x)) % MOD; pw >>= 1; x = ((x * x)) % MOD; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); sieve(); long long int x, y; cin >> x >> y; long long int ans = 0; if (y % x == 0) { map<int, int> fac; y /= x; long long int cp = y; for (auto &it : pr) { if (cp == 1) break; while (cp % it == 0) fac[it]++, cp /= it; } if (cp > 1) fac[cp]++; for (long long int i = 1; i < (long long int)1e5; ++i) { if (i * i > y) break; if (y % i == 0) { map<int, int> f; cp = i; for (auto &it : fac) { if (cp == 1) break; while (cp % it.first == 0) f[it.first]++, cp /= it.first; } int mu = 1; for (auto &it : f) { if (it.second > 1) mu = 0; else mu *= -1; } ans += mu * powm(2, y / i - 1, MOD); if (y / i != i) { map<int, int> f; cp = y / i; for (auto &it : fac) { if (cp == 1) break; while (cp % it.first == 0) f[it.first]++, cp /= it.first; } int mu = 1; for (auto &it : f) { if (it.second > 1) mu = 0; else mu *= -1; } ans += mu * powm(2, i - 1, MOD); } ans %= MOD; } } cout << (ans + MOD) % MOD << n ; } else cout << 0 << n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:45 03/31/2015
// Design Name:
// Module Name: Adder64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder64(
input [63:0] A,
input [63:0] B,
input C0,
output [3:0] P,
output [3:0] G,
output [63:0] sum,
output SF,
output CF,
output OF,
output PF,
output ZF
);
wire[15:0] p,g;
wire[4:0] C;
wire[3:0] sf,cf,of,pf,zf;
pg_to_PG pgtoPG(p,g,P,G);
ParallelCarry4 PC(P,G,C0,C);
Adder16 a1(A[15:0],B[15:0],C[0],p[3:0],g[3:0],sum[15:0],sf[0],cf[0],of[0],pf[0],zf[0]),
a2(A[31:16],B[31:16],C[1],p[7:4],g[7:4],sum[31:16],sf[1],cf[1],of[1],pf[1],zf[1]),
a3(A[47:32],B[47:32],C[2],p[11:8],g[11:8],sum[47:32],sf[2],cf[2],of[2],pf[2],zf[2]),
a4(A[63:48],B[63:48],C[3],p[15:12],g[15:12],sum[63:48],sf[3],cf[3],of[3],pf[3],zf[3]);
assign SF=sf[3],
CF=C[4],
OF=of[3],
PF=^pf[3:0],
ZF= ~|(~zf[3:0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int m = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; string s; cin >> s; for (int i = 0; i <= 25; i++) { for (int j = 0; j < n and k > 0; j++) { if (s[j] == a + i) { k--; s[j] = 0 ; } } } for (auto &x : s) { if (x != 0 ) { cout << x; } } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; const int N = 200111; struct node { int i, j; long long mn, ad = 0; node *l, *r; node(long long *a, int i, int j) : i(i), j(j) { if (j - i == 1) { l = r = NULL; mn = a[i]; } else { int k = i + j >> 1; l = new node(a, i, k); r = new node(a, k, j); combine(); } } inline void combine() { mn = min(l->mn, r->mn); } void visit() { if (ad) { mn += ad; if (l) l->ad += ad, r->ad += ad; ad = 0; } } void inc(int I, int J, long long a) { if (I <= i && j <= J) { ad += a; visit(); } else { visit(); if (!(J <= i || j <= I)) { l->inc(I, J, a); r->inc(I, J, a); combine(); } } } int find() { visit(); if (mn > 0) return INF; if (!l) { return mn == 0 ? i : INF; } else { int ans = INF; if (ans >= INF) ans = l->find(); if (ans >= INF) ans = r->find(); return ans; } } }; long long a[N], s[N]; int main() { int n, q; scanf( %d%d , &n, &q); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); s[i + 1] = s[i] + a[i]; } for (int i = 0; i < n; i++) { s[i] -= a[i]; } node *t = new node(s, 0, n); while (q--) { int i; long long v; scanf( %d%lld , &i, &v); long long d = v - a[--i]; t->inc(i, i + 1, -d); t->inc(i + 1, n, +d); t->visit(); a[i] += d; int ans = t->find(); printf( %d n , ans >= INF ? -1 : ans + 1); } } |
/*
* File: demo_clk.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* clock module for FPGA demo on XUP board
*
*/
module demo_clk (
CLK_IN,
RST,
CLK1X,
CLK2X,
LOCK
);
input CLK_IN;
input RST;
output CLK1X;
output CLK2X;
output LOCK;
wire CLK_INW;
wire CLK1X_W;
wire CLK2X_W;
wire GND;
assign GND = 1'b0;
//
// IBUFG
//
IBUFG IBUFG_inst (
.I(CLK_IN),
.O(CLK_INW)
);
//
// BUFG
//
BUFG U_BUFG (
.I(CLK2X_W),
.O(CLK2X)
);
BUFG U2_BUFG (
.I(CLK1X_W),
.O(CLK1X)
);
// Attributes for functional simulation//
// synopsys translate_off
defparam U_DCM.DLL_FREQUENCY_MODE = "LOW";
defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
defparam U_DCM.STARTUP_WAIT = "TRUE";
// synopsys translate_on
// Instantiate the DCM primitive//
DCM U_DCM (
.CLKFB(CLK1X),
.CLKIN(CLK_INW),
.DSSEN(GND),
.PSCLK(GND),
.PSEN(GND),
.PSINCDEC(GND),
.RST(RST),
.CLK0(CLK1X_W),
.CLK2X(CLK2X_W),
.LOCKED(LOCK)
);
// synthesis attribute declarations
/* synopsys attribute
DLL_FREQUENCY_MODE "LOW"
DUTY_CYCLE_CORRECTION "TRUE"
STARTUP_WAIT "TRUE"
*/
endmodule |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module ad_dcfilter (
// data interface
clk,
valid,
data,
valid_out,
data_out,
// control interface
dcfilt_enb,
dcfilt_coeff,
dcfilt_offset);
// data interface
input clk;
input valid;
input [15:0] data;
output valid_out;
output [15:0] data_out;
// control interface
input dcfilt_enb;
input [15:0] dcfilt_coeff;
input [15:0] dcfilt_offset;
// internal registers
reg [15:0] dc_offset = 'd0;
reg [32:0] dc_offset_33 = 'd0;
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [32:0] dc_offset_33_s;
// cancelling the dc offset
always @(posedge clk) begin
dc_offset <= dc_offset_33_s[32:17];
dc_offset_33 <= dc_offset_33_s;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
if (dcfilt_enb == 1'b1) begin
valid_out <= valid_d;
data_out <= data_d - dc_offset;
end else begin
valid_out <= valid_d;
data_out <= data_d;
end
end
ad_dcfilter_1 i_dcfilter_1 (
.clk (clk),
.d (data_d),
.b (dcfilt_coeff),
.a (dc_offset_33[32:17]),
.c (dc_offset_33[32:17]),
.p (dc_offset_33_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, k1, k2, u[1001], q[1001], start, x, y; vector<int> vec[1001]; int a, b; int f(int v, int pr) { if (u[v] == 1) { return v; } int yy = 0; for (int i = 0; i < vec[v].size(); i++) { if (vec[v][i] != pr) { yy = max(yy, f(vec[v][i], v)); } } return yy; } pair<int, int> get(int v, int pr) { pair<int, int> ans = make_pair(0, 0); if (v == y) { ans.first = 1; return ans; } if (u[v] == 1) { ans.second = v; } pair<int, int> yy = make_pair(0, 0); for (int i = 0; i < vec[v].size(); i++) { if (vec[v][i] != pr) { yy = max(yy, get(vec[v][i], v)); } } if (yy.first != 0) { ans.first = 1; } if (yy.first != 0 && yy.second != 0) { ans = yy; } return ans; } void solve() { for (int i = 0; i < 1001; i++) { vec[i].clear(); u[i] = 0; q[i] = 0; } cin >> n; for (int i = 1; i < n; i++) { scanf( %d%d , &a, &b); vec[a].push_back(b); vec[b].push_back(a); } cin >> k1; for (int i = 0; i < k1; i++) { scanf( %d , &x); u[x] = 1; } cin >> k2; for (int i = 0; i < k2; i++) { scanf( %d , &x); q[x] = 1; } start = f(1, -1); cout << A << start << endl; fflush(stdout); cin >> y; if (q[y] == 1) { cout << C << start << endl; fflush(stdout); return; } else { cout << B << x << endl; fflush(stdout); cin >> y; if (u[y] == 1) { cout << C << y << endl; fflush(stdout); return; } else { pair<int, int> ppp = get(1, -1); if (ppp.second == 0) { cout << C -1 << endl; fflush(stdout); return; } start = ppp.second; cout << A << start << endl; fflush(stdout); cin >> y; if (q[y] == 1) { cout << C << start << endl; fflush(stdout); return; } else { cout << C -1 << endl; fflush(stdout); return; } } } } int main() { int test; cin >> test; while (test--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e14; const long long TE3 = 1005; const long long TE5 = 300005; const string YN[2] = { NO , YES }; using namespace std; long long f(long long n, vector<long long>& q1, vector<long long>& q2) { unordered_map<long long, long long> e; long long c = 0; e[0] = -1; long long i = 0, j = 0; long long ans = 0; while (i < q1.size() || j < q2.size()) { long long g; long long q1t = (i >= q1.size()) ? INF : q1[i]; long long q2t = (j >= q2.size()) ? INF : q2[j]; if (q1t < q2t) { g = q1t; ++c; ++i; } else { g = q2t; --c; ++j; } if (e.find(c) == e.end()) { e[c] = g; } else { q2t = (j >= q2.size()) ? INF : q2[j]; q1t = (i >= q1.size()) ? INF : q1[i]; long long tmp = min(q1t, q2t); long long cur = (tmp == INF ? n : tmp) - e[c] - 1; ans = max(ans, cur); } } return ans; } int main() { ios::sync_with_stdio(false); long long n; cin >> n; long long x; unordered_map<long long, vector<long long> > mpq; for (long long i = (0); i < (n); ++i) { cin >> x; mpq[x].push_back(i); } if (mpq.size() == 1) { cout << 0 << endl; return 0; } unordered_map<long long, long long> rev; long long ma = -INF, mo = 0; for (auto it : mpq) { rev[it.second.size()]++; if (it.second.size() > mo) { ma = it.first; mo = it.second.size(); } } if (rev[mo] >= 2) { cout << n << endl; return 0; } long long ans = 0; for (auto it : mpq) { if (it.first == ma) continue; ans = max(ans, f(n, mpq[ma], it.second)); } cout << ans << endl; return 0; } |
//
// Copyright (c) 2000 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// for3.16A - Template 1 - for(val1=0; val1 <= expr ; val1 = val1 + 1) some_action
//
module pr1120 ();
wire [31:0] foo;
reg [31:0] bar;
// FAIL
assign foo[31:16] = (bar & 32'hffffffff) >> 16;
// PASS
//assign foo[31:16] = bar >> 16;
initial
begin
bar = 32'ha5a5_3f3f;
#100;
$display("foo[31:16] = %x bar = %x",foo[31:16],bar);
//if(foo[31:16]==((bar & 32'hffffffff) >> 16))
if(foo[31:16] === 16'ha5a5)
$display("PASS (%x)",foo[31:16]);
else
$display("FAIL (%x vs %x)",foo[31:16],((bar & 32'hffffffff) >> 16));
$finish;
end
endmodule
|
/*
zybo_top.v -- Top level entity for ION demo on Zybo board.
As of right now this does not actually work. All I want for the time being
is to make sure I can synthesize the demo entity without the whole thing
being optimized away.
So all I do here is connect the MCU module to the very few I/O available on
the board.
In other wordS: SYNTHESIS DUMMY -- DOES NOT WORK!
*/
module zybo_top
(
// Main clock. See @note1.
input CLK_125MHZ_I,
// Various I/O ports connected to board devices.
input [3:0] BUTTONS_I,
input [3:0] SWITCHES_I,
output reg [3:0] LEDS_O,
// PMOD E (Std) connector -- PMOD UART (Digilent).
output reg PMOD_E_2_TXD_O,
input PMOD_E_3_RXD_I
);
//==== MCU instantiation ===================================================
reg [31:0] bogoinput;
wire [31:0] dbg_out;
reg [31:0] dbg_in;
reg reset;
mcu # (
// Size of Code TCM in 32-bit words.
.OPTION_CTCM_NUM_WORDS(1024)
)
mcu (
.CLK (CLK_125MHZ_I),
.RESET_I (reset),
.DEBUG_I (dbg_in),
.DEBUG_O (dbg_out)
);
// Bogus logic to keep all MCU outputs relevant.
always @(*) begin
LEDS_O =
dbg_out[31:28] ^ dbg_out[27:24] ^ dbg_out[23:20] ^ dbg_out[19:16] ^
dbg_out[15:12] ^ dbg_out[11: 8] ^ dbg_out[ 7: 4] ^ dbg_out[ 3: 0];
reset = |BUTTONS_I;
PMOD_E_2_TXD_O = PMOD_E_3_RXD_I;
end
// Bogus logic to keep all MCU inputs relevant.
always @(posedge CLK_125MHZ_I) begin
if (reset) begin // TODO Async input used as sync reset...
bogoinput <= 32'h0;
dbg_in <= 32'h0;
end
else begin
bogoinput <= {8{SWITCHES_I}};
dbg_in <= dbg_out + bogoinput;
end
end
endmodule
// @note1: Clock active if PHYRSTB is high. PHYRSTB pin unused, pulled high.
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int k, a[N], b[N]; char s[N], t[N]; int main() { cin >> k; scanf( %s , s + 1); scanf( %s , t + 1); for (int i = k; i; i--) { a[i] = t[i] - s[i]; if (a[i] < 0) { a[i] += 26; t[i - 1]--; } } for (int i = 1; i <= k; i++) { a[i + 1] += (a[i] % 2) * 26; a[i] /= 2; } for (int i = k; i; i--) { b[i] += s[i] - a + a[i]; b[i - 1] += b[i] / 26; b[i] %= 26; } for (int i = 1; i <= k; i++) printf( %c , a + b[i]); return 0; } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; string a; cin >> n >> a; stack<char> q; int m = 1; int len = 0; int he = -1; for (int i = 0; i < n; i++) { if (q.empty() || q.top() == a[i]) { q.push(a[i]); len++; m += 2; } else { if (a[i] != a[i - 1]) len += 3; if (a[i] == [ && a[i - 1] == ] ) len += 4; q.pop(); len++; m -= 2; } he = max(he, m); } vector<vector<char>> res(len, vector<char>(he, )); m = 0; int cur = 0; for (int i = 0; i < n; i++) { if (i != 0 && a[i] == a[i - 1] && a[i] == [ ) m++; else if (i != 0 && a[i] == a[i - 1] && a[i] == ] ) m--; if (a[i] == [ ) { res[cur][m] = + ; res[cur][he - m - 1] = + ; res[cur + 1][m] = - ; res[cur + 1][he - m - 1] = - ; for (int j = m + 1; j < he - m - 1; j++) res[cur][j] = | ; } else { if (a[i] == ] && a[i - 1] == [ ) cur += 3; res[cur - 1][m] = - ; res[cur - 1][he - m - 1] = - ; res[cur][m] = + ; res[cur][he - m - 1] = + ; for (int j = m + 1; j < he - m - 1; j++) res[cur][j] = | ; } cur++; } for (int i = 0; i < he; i++) { for (int j = 0; j < len; j++) cout << res[j][i]; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; int g, t, n; int main() { cin >> n >> n; cin >> s; int l = s.size(); for (int i = 0; i < l; i++) { if (s[i] == T ) t = i; else if (s[i] == G ) g = i; } if (g < t) swap(g, t); int i; if ((g - t) % n != 0) { cout << NO ; return 0; } for (i = t; i <= g; i += n) { if (s[i] == # ) { cout << NO ; return 0; } } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; void yes() { cout << YES << n ; } void no() { cout << NO << n ; } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } void main_() { string s; cin >> s; int n; n = s.size(); int a, b, c; a = b = c = 0; for (int i = 0; i < n; i++) { if (s[i] <= z && s[i] >= a ) a++; else if (s[i] <= Z && s[i] >= A ) b++; else c++; } if (a > 0 && b > 0 && c > 0) { cout << s << n ; return; } if (a * b || b * c || c * a) { if (a * b) { if (a > 1) { for (int i = 0; i < n; i++) { if (s[i] <= z && s[i] >= a ) { s[i] = 1 ; cout << s << n ; return; } } } else { for (int i = 0; i < n; i++) { if (s[i] <= Z && s[i] >= A ) { s[i] = 1 ; cout << s << n ; return; } } } } else if (b * c) { if (b > 1) { for (int i = 0; i < n; i++) { if (s[i] <= Z && s[i] >= A ) { s[i] = a ; cout << s << n ; return; } } } else { for (int i = 0; i < n; i++) { if (s[i] <= 9 && s[i] >= 0 ) { s[i] = a ; cout << s << n ; return; } } } } else { if (a > 1) { for (int i = 0; i < n; i++) { if (s[i] <= z && s[i] >= a ) { s[i] = A ; cout << s << n ; return; } } } else { for (int i = 0; i < n; i++) { if (s[i] <= 9 && s[i] >= 0 ) { s[i] = A ; cout << s << n ; return; } } } } } else { if (a) { s[0] = A ; s[1] = 1 ; cout << s << n ; return; } if (b) { s[0] = a ; s[1] = 1 ; cout << s << n ; return; } else { s[0] = a ; s[1] = B ; cout << s << n ; return; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int test = 1; cin >> test; while (test--) { main_(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n; cin >> n; int count = 0; for (int a = 1; a <= n; a++) { for (int b = a; b <= n; b++) { int k = a * a + b * b; int c = sqrt(k); if (c * c == k && c <= n) count++; } } cout << count; return 0; } |
module HazardCheckUnit(IDEXMemRead,IDEXRt,IFIDRs,IFIDRt,PCWrite,IFIDWrite,ctrlSetZero,IDEXRd,IDEXRegWrite,opcode,EXMEMRead,EXMEMRt,clk);
input[4:0] IDEXRt,IFIDRt,IFIDRs,IDEXRd,EXMEMRt;
input IDEXMemRead,IDEXRegWrite,EXMEMRead;
input[5:0] opcode;
input clk;
output PCWrite,IFIDWrite,ctrlSetZero;
reg PCWrite,IFIDWrite,ctrlSetZero;
initial
begin
PCWrite<=1;
IFIDWrite<=1;
ctrlSetZero<=0;
end
always @(opcode or IDEXMemRead or IDEXRt or IFIDRs or IFIDRt or IDEXRd or IDEXRegWrite or clk) begin
if(opcode==6'b000100)begin
if(IDEXMemRead && ((IDEXRt==IFIDRs) || (IDEXRt==IFIDRt))) begin//beq,lw,stall 2 clks
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
else if(IDEXRegWrite && ((IDEXRd==IFIDRs) || (IDEXRd==IFIDRt)))begin//beq,R,stall 1 clk
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
else begin
PCWrite<=1;
IFIDWrite<=1;
ctrlSetZero<=0;
end
if(EXMEMRead && ((EXMEMRt==IFIDRs) || (EXMEMRt==IFIDRt)))begin
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
end
else begin
if(IDEXMemRead && ((IDEXRt==IFIDRs) || (IDEXRt==IFIDRt))) begin//R,lw,stall 1 clk
PCWrite<=0;
IFIDWrite<=0;
ctrlSetZero<=1;
end
else begin
PCWrite<=1;
IFIDWrite<=1;
ctrlSetZero<=0;
end
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_2_V
`define SKY130_FD_SC_LS__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_2_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: txuart.v
//
// Project: Verilog Tutorial Example file
//
// Purpose: Transmit outputs over a single UART line. This particular UART
// implementation has been extremely simplified: it does not handle
// generating break conditions, nor does it handle anything other than the
// 8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol.
//
// To interface with this module, connect it to your system clock, and
// pass it the byte of data you wish to transmit. Strobe the i_wr line
// high for one cycle, and your data will be off. Wait until the 'o_busy'
// line is low before strobing the i_wr line again--this implementation
// has NO BUFFER, so strobing i_wr while the core is busy will just
// get ignored. The output will be placed on the o_txuart output line.
//
// There are known deficiencies in the formal proof found within this
// module. These have been left behind for you (the student) to fix.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Written and distributed by Gisselquist Technology, LLC
//
// This program is hereby granted to the public domain.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
//
//
module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
input wire i_clk;
input wire i_wr;
input wire [7:0] i_data;
// And the UART output line itself
output wire o_uart_tx;
// A line to tell others when we are ready to accept data. If
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
// for transmission.
output reg o_busy;
// Define several states
localparam [3:0] START = 4'h0,
BIT_ZERO = 4'h1,
BIT_ONE = 4'h2,
BIT_TWO = 4'h3,
BIT_THREE = 4'h4,
BIT_FOUR = 4'h5,
BIT_FIVE = 4'h6,
BIT_SIX = 4'h7,
BIT_SEVEN = 4'h8,
LAST = 4'h8,
IDLE = 4'hf;
reg [23:0] counter;
reg [3:0] state;
reg [8:0] lcl_data;
reg baud_stb;
// o_busy
//
// This is a register, designed to be true is we are ever busy above.
// originally, this was going to be true if we were ever not in the
// idle state. The logic has since become more complex, hence we have
// a register dedicated to this and just copy out that registers value.
initial o_busy = 1'b0;
initial state = IDLE;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
// Immediately start us off with a start bit
{ o_busy, state } <= { 1'b1, START };
else if (baud_stb)
begin
if (state == IDLE) // Stay in IDLE
{ o_busy, state } <= { 1'b0, IDLE };
else if (state < LAST) begin
o_busy <= 1'b1;
state <= state + 1'b1;
end else // Wait for IDLE
{ o_busy, state } <= { 1'b1, IDLE };
end
// lcl_data
//
// This is our working copy of the i_data register which we use
// when transmitting. It is only of interest during transmit, and is
// allowed to be whatever at any other time. Hence, if o_busy isn't
// true, we can always set it. On the one clock where o_busy isn't
// true and i_wr is, we set it and o_busy is true thereafter.
// Then, on any baud_stb (i.e. change between baud intervals)
// we simple logically shift the register right to grab the next bit.
initial lcl_data = 9'h1ff;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
lcl_data <= { i_data, 1'b0 };
else if (baud_stb)
lcl_data <= { 1'b1, lcl_data[8:1] };
// o_uart_tx
//
// This is the final result/output desired of this core. It's all
// centered about o_uart_tx. This is what finally needs to follow
// the UART protocol.
//
assign o_uart_tx = lcl_data[0];
// All of the above logic is driven by the baud counter. Bits must last
// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
// make certain of that.
//
// The basic logic is this: at the beginning of a bit interval, start
// the baud counter and set it to count CLOCKS_PER_BAUD. When it gets
// to zero, restart it.
//
// However, comparing a 28'bit number to zero can be rather complex--
// especially if we wish to do anything else on that same clock. For
// that reason, we create "baud_stb". baud_stb is
// nothing more than a flag that is true anytime baud_counter is zero.
// It's true when the logic (above) needs to step to the next bit.
// Simple enough?
//
// I wish we could stop there, but there are some other (ugly)
// conditions to deal with that offer exceptions to this basic logic.
//
// 1. When the user has commanded a BREAK across the line, we need to
// wait several baud intervals following the break before we start
// transmitting, to give any receiver a chance to recognize that we are
// out of the break condition, and to know that the next bit will be
// a stop bit.
//
// 2. A reset is similar to a break condition--on both we wait several
// baud intervals before allowing a start bit.
//
// 3. In the idle state, we stop our counter--so that upon a request
// to transmit when idle we can start transmitting immediately, rather
// than waiting for the end of the next (fictitious and arbitrary) baud
// interval.
//
// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
// the idle state, but we also just accepted a command to start writing
// the next word. At this point, the baud counter needs to be reset
// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
//
// The logic is a bit twisted here, in that it will only check for the
// above condition when baud_stb is false--so as to make
// certain the STOP bit is complete.
initial baud_stb = 1'b1;
initial counter = 0;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
begin
counter <= CLOCKS_PER_BAUD - 1'b1;
baud_stb <= 1'b0;
end else if (!baud_stb)
begin
baud_stb <= (counter == 24'h01);
counter <= counter - 1'b1;
end else if (state != IDLE)
begin
counter <= CLOCKS_PER_BAUD - 24'h01;
baud_stb <= 1'b0;
end
//
//
// FORMAL METHODS
//
//
//
`ifdef FORMAL
`ifdef TXUART
`define ASSUME assume
`else
`define ASSUME assert
`endif
// Setup
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
// Any outstanding request that was busy on the last cycle,
// should remain busy on this cycle
initial `ASSUME(!i_wr);
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wr))&&($past(o_busy)))
begin
`ASSUME(i_wr == $past(i_wr));
`ASSUME(i_data == $past(i_data));
end
//////////////////////////////////
//
// The contract
//
//////////////////////////////////
reg [7:0] fv_data;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
fv_data <= i_data;
always @(posedge i_clk)
case(state)
IDLE: assert(o_uart_tx == 1'b1);
START: assert(o_uart_tx == 1'b0);
BIT_ZERO: assert(o_uart_tx == fv_data[0]);
BIT_ONE: assert(o_uart_tx == fv_data[1]);
BIT_TWO: assert(o_uart_tx == fv_data[2]);
BIT_THREE: assert(o_uart_tx == fv_data[3]);
BIT_FOUR: assert(o_uart_tx == fv_data[4]);
BIT_FIVE: assert(o_uart_tx == fv_data[5]);
BIT_SIX: assert(o_uart_tx == fv_data[6]);
BIT_SEVEN: assert(o_uart_tx == fv_data[7]);
default: assert(0);
endcase
//////////////////////////////////
//
// Internal state checks
//
//////////////////////////////////
//
// Check the baud counter
//
// The baud_stb needs to be identical to our counter being zero
always @(posedge i_clk)
assert(baud_stb == (counter == 0));
always @(posedge i_clk)
if ((f_past_valid)&&($past(counter != 0)))
assert(counter == $past(counter - 1'b1));
always @(posedge i_clk)
assert(counter < CLOCKS_PER_BAUD);
always @(posedge i_clk)
if (!baud_stb)
assert(o_busy);
`endif // FORMAL
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
// Reported by Julian Gorfajn <>
module autoinst_multitemplate ();
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input Boo1; // To suba1 of SubA.v
input Boo2; // To suba2 of SubB.v
input Boo3; // To suba3 of SubC.v
input b; // To suba2 of SubB.v
input c; // To suba3 of SubC.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
wire [3:0] f4_dotnamed;
/*
SubA AUTO_TEMPLATE
SubB AUTO_TEMPLATE
SubC AUTO_TEMPLATE (
.a (Boo@),
);*/
SubA suba1 (/*AUTOINST*/
// Inputs
.a (Boo1)); // Templated
SubB suba2 (/*AUTOINST*/
// Inputs
.a (Boo2), // Templated
.b (b));
SubC suba3 (/*AUTOINST*/
// Inputs
.a (Boo3), // Templated
.c (c));
endmodule
module SubA (input a);
endmodule
module SubB (input a,input b);
endmodule
module SubC (input a,input c );
endmodule
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination;
wire [15:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
//////////////////////////
// Señales del pipeline //
wire [7:0] wDestinationPrev;
wire [15:0] wSourceData0_RAM,wSourceData1_RAM,wResultPrev;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate;
///////////////////////////////
// Señales de multiplicacion //
wire signed [15:0] wSignedData1, wSignedData0;
reg signed [31:0] rResultMult;
wire [31:0] wMultResult0;
assign wSignedData0 = wSourceData0;
assign wSignedData1 = wSourceData1;
///////////////////////////////
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
//////////////////////////////////
// MUL //
Mult16x16 MUL_LUT
(
.A(wSourceData0),
.B(wSourceData1),
.Result(wMultResult0)
);
// //
//////////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rResultMult <= wSignedData1*wSignedData0;
end
//-------------------------------------
`IMUL2:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rResultMult <= wMultResult0;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_2_V
`define SKY130_FD_SC_HS__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__buf_2 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_2_V
|
#include <bits/stdc++.h> using namespace std; const long long M = 51123987; long long C[151][151]; int dp[2][3][51][51][51] = {}; int main() { int n; string s; cin >> n >> s; auto cur = dp[0]; auto nex = dp[1]; int u = (n - 1) / 3 + 1; int t[3] = {}; for (int i = 0; i < n; i++) { memset(nex, 0, sizeof(dp) / 2); t[s[i] - a ]++; for (int j = 0; j < 3; j++) { bool col = s[i] - a == j; int c[3]; for (c[0] = 0; c[0] <= t[0] && c[0] <= u; c[0]++) { for (c[1] = 0; c[1] <= t[1] && c[1] <= u; c[1]++) { for (c[2] = 0; c[2] <= t[2] && c[2] <= u; c[2]++) { long long v = 0; if (col) { if (c[j]) { if (c[0] + c[1] + c[2] == 1) { v = 1; } int p[3] = {c[0], c[1], c[2]}; p[j]--; for (int k = 1; k <= 2; k++) { v += cur[(j + k) % 3][p[0]][p[1]][p[2]]; v %= M; } } } else { v = cur[j][c[0]][c[1]][c[2]]; } nex[j][c[0]][c[1]][c[2]] = v; } } } } swap(nex, cur); } for (int i = 0; i <= u; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) { C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; C[i][j] %= M; } } long long ret = 0; for (int i = max(0, u - 1); i <= u; i++) { for (int j = max(0, u - 1); j <= u; j++) { for (int k = max(0, u - 1); k <= u; k++) { if (i + j + k != n) continue; for (int p = min(i, 1); p <= i; p++) { for (int q = min(j, 1); q <= j; q++) { for (int r = min(k, 1); r <= k; r++) { long long s = 0; for (int v = 0; v < 3; v++) { s += cur[v][p][q][r]; s %= M; } if (i != p) { s *= C[i - 1][p - 1]; s %= M; } if (j != q) { s *= C[j - 1][q - 1]; s %= M; } if (k != r) { s *= C[k - 1][r - 1]; s %= M; } ret += s; ret %= M; } } } } } } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; while (test--) { int n, m; cin >> n >> m; vector<int> a(n), b(m); for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { cin >> b[i]; } vector<int> idx(100001); for (int i = 0; i < n; i++) { idx[a[i]] = i; } long long ans = 0; int mxDepth = 0; for (int i = 0; i < m; i++) { if (idx[b[i]] < mxDepth) { ans++; } else { mxDepth = idx[b[i]]; ans += 2 * (idx[b[i]] - i) + 1; } } cout << ans << n ; } return 0; } |
/*================================================
Thomas Gorham
ECE 441 Spring 2017
Project 2 - Main
Description: This module instantiates all the
component modules used in this design.
================================================*/
`timescale 100 ns / 1 ns
module tld(clock, ar, button, a1, b1, c1, d1, e1, f1, g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3, led);
input wire clock, ar, button;
output wire a1, b1, c1, d1, e1, f1, g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3, led;
wire fast_clock, slow_clock, random_bit, ctr_en, ctr_ar;
wire [3:0] dig1, dig2, dig3;
// Clock divider takes in 50MHz clock and outputs 2Hz and 1kHz clocks
clock_divider clkdiv ( .clk(clock), .ar(ar), .x(slow_clock), .y(fast_clock));
lfsr shiftreg ( .clk(slow_clock), .ar(ar), .sr( ), .q(random_bit));
ctr_fsm fsm (.clk(fast_clock), .ar(ar), .start(random_bit), .stop(button), .ctr_en(ctr_en), .ctr_ar(ctr_ar));
bcd_ctr bcd (.clk(fast_clock), .en(ctr_en), .ar(ctr_ar), .dig1(dig1), .dig2(dig2), .dig3(dig3));
sevseg_decoder decoder1 (.val(dig1), .a(a1), .b(b1), .c(c1), .d(d1), .e(e1), .f(f1), .g(g1));
sevseg_decoder decoder2 (.val(dig2), .a(a2), .b(b2), .c(c2), .d(d2), .e(e2), .f(f2), .g(g2));
sevseg_decoder decoder3 (.val(dig3), .a(a3), .b(b3), .c(c3), .d(d3), .e(e3), .f(f3), .g(g3));
assign led = ctr_en;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_HS__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__buf (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; namespace Quick_Function { template <typename Temp> void Read(Temp &x) { x = 0; char ch = getchar(); bool op = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) op = 1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } if (op) x = -x; } template <typename T, typename... Args> void Read(T &t, Args &...args) { Read(t); Read(args...); } template <typename Temp> Temp Max(Temp x, Temp y) { return x > y ? x : y; } template <typename Temp> Temp Min(Temp x, Temp y) { return x < y ? x : y; } template <typename Temp> Temp Abs(Temp x) { return x < 0 ? (-x) : x; } template <typename Temp> void Swap(Temp &x, Temp &y) { x ^= y ^= x ^= y; } } // namespace Quick_Function using namespace Quick_Function; const int MAXN = 5e6 + 5; bool vis[MAXN]; int n, ans; struct Splay_Node { int son[2], fa, val, tag; }; struct Splay_Tree { Splay_Node t[MAXN]; int root, tot, Top, stk[MAXN]; int Ident(int pos) { return t[t[pos].fa].son[1] == pos ? 1 : 0; } void Connect(int pos, int fa, int flag) { t[fa].son[flag] = pos, t[pos].fa = fa; } void Push_Down(int pos) { if (!t[pos].tag) return; if (t[pos].son[0]) { t[t[pos].son[0]].val += t[pos].tag, t[t[pos].son[0]].tag += t[pos].tag; } if (t[pos].son[1]) { t[t[pos].son[1]].val += t[pos].tag, t[t[pos].son[1]].tag += t[pos].tag; } t[pos].tag = 0; } int New(int val, int fa) { t[++tot].fa = fa, t[tot].val = val; return tot; } void Build() { root = New(-0x3f3f3f3f, 0); t[root].son[1] = New(0x3f3f3f3f, root); } void Rotate(int pos) { int fa = t[pos].fa, grand = t[fa].fa; int flag1 = Ident(pos), flag2 = Ident(fa); Connect(pos, grand, flag2); Connect(t[pos].son[flag1 ^ 1], fa, flag1); Connect(fa, pos, flag1 ^ 1); } void Splay(int pos, int to) { int tmp = pos; Top = 0; stk[++Top] = tmp; while (tmp) stk[++Top] = tmp = t[tmp].fa; while (Top) Push_Down(stk[Top--]); for (int fa = t[pos].fa; t[pos].fa != to; Rotate(pos), fa = t[pos].fa) if (t[fa].fa != to) Ident(pos) == Ident(fa) ? Rotate(fa) : Rotate(pos); if (!to) root = pos; } void Insert(int &pos, int val, int fa) { if (!pos) { ++ans; pos = New(val, fa); Splay(pos, 0); return; } Push_Down(pos); if (val < t[pos].val) Insert(t[pos].son[0], val, pos); else Insert(t[pos].son[1], val, pos); } void Erase(int pos) { Splay(pos, 0); vis[pos] = 1; int l = t[pos].son[0], r = t[pos].son[1]; while (t[l].son[1]) l = t[l].son[1]; while (t[r].son[0]) r = t[r].son[0]; Splay(l, 0); Splay(r, l); t[r].son[0] = 0; --ans; } int Get_Pre(int val) { int pos, res, newroot; pos = newroot = root; while (pos) { Push_Down(pos); if (t[pos].val < val) { res = pos; pos = t[pos].son[1]; } else pos = t[pos].son[0]; } Splay(newroot, 0); return res; } int Get_Nxt(int val) { int pos, res, newroot; pos = newroot = root; while (pos) { Push_Down(pos); if (t[pos].val > val) { res = pos; pos = t[pos].son[0]; } else pos = t[pos].son[1]; } Splay(newroot, 0); return res; } void Move(int l, int r) { int u = Get_Nxt(l - 1), v = Get_Pre(r); if (t[u].val > t[v].val) return; if (u == v) t[u].val++; else if (t[u].val < t[v].val) { Splay(u, 0); Splay(v, u); int rson = t[v].son[0]; ++t[u].val; ++t[v].val, t[rson].val++; if (rson) ++t[rson].tag; } } void Body() { int pos = rand() % tot + 1; if (!vis[pos]) { Splay(pos, 0); return; } pos = rand() % tot + 1; if (!vis[pos]) { Splay(pos, 0); return; } pos = rand() % tot + 1; if (!vis[pos]) { Splay(pos, 0); return; } pos = rand() % tot + 1; if (!vis[pos]) { Splay(pos, 0); return; } pos = rand() % tot + 1; if (!vis[pos]) { Splay(pos, 0); return; } } }; Splay_Tree tree; int main() { srand(time(0)); Read(n); tree.Build(); tree.Insert(tree.root, 0, 0); ans = 0; for (int i = 1, l, r; i <= n; i++) { Read(l, r); int pos = tree.Get_Nxt(r - 1); if (pos && pos != 1 && pos != 2) tree.Erase(pos); tree.Move(l, r); tree.Insert(tree.root, l, 0); tree.Body(); } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; string s, t; bool B1[1000001]; bool B2[1000001]; vector<int> R; int main() { int n; getline(cin, s); getline(cin, t); int i = 0; bool b = true; while (i < t.size()) { if (t[i] != s[i]) b = false; B1[i] = b; i++; } i = 0; b = true; while (i < t.size()) { if (t[t.size() - i - 1] != s[s.size() - i - 1]) b = false; B2[s.size() - i - 1] = b; i++; } for (int i = 0; i < s.size() + 1; i++) { bool b1 = true, b2 = true; if (i > 0) b1 = B1[i - 1]; if (i + 1 < s.size()) b2 = B2[i + 1]; if (b1 && b2) R.push_back(i); } cout << R.size() << endl; for (int i = 0; i < R.size(); i++) cout << R[i] + 1 << ; cin >> n; } |
#include <bits/stdc++.h> using namespace std; int ex, ey; bool a[207][207]; bool vis[207][207]; int dx[4] = {0, 0, 1, -1}; int dy[4] = {-1, 1, 0, 0}; int bfs() { queue<pair<int, int>> q; vis[100][100] = true; q.push(make_pair(100, 100)); int dep = 0; while (int(q.size())) { int size = int(q.size()); while (size--) { pair<int, int> top = q.front(); q.pop(); vis[top.first][top.second] = true; if (top.first == ex && top.second == ey) return dep; for (int i = 0; i < int(4); i++) { int nx = top.first + dx[i]; int ny = top.second + dy[i]; if (a[nx][ny] && !vis[nx][ny]) { q.push(make_pair(nx, ny)); } } } dep++; } return -1; } int main() { string second; cin >> second; ex = ey = 100; for (int i = 0; i < int(int(second.size())); i++) { a[ex][ey] = true; if (second[i] == R ) ex++; if (second[i] == L ) ex--; if (second[i] == U ) ey--; if (second[i] == D ) ey++; if (a[ex][ey]) { puts( BUG ); return 0; } } a[ex][ey] = true; int ans = bfs(); ans < int(second.size()) ? puts( BUG ) : puts( OK ); } |
module wb_ram
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output [dw-1:0] wb_dat_o);
reg [aw-1:0] adr_r;
wire [aw-1:0] next_adr;
wire valid = wb_cyc_i & wb_stb_i;
reg valid_r;
wire new_cycle = valid & !valid_r;
wb_next_adr #(.aw(aw)) wb_next_adr0(adr_r, wb_cti_i, wb_bte_i, next_adr);
wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
always@(posedge wb_clk_i) begin
adr_r <= adr;
valid_r <= valid;
//Ack generation
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst_i) begin
adr_r <= {aw{1'b0}};
valid_r <= 1'b0;
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
//TODO:ck for burst address errors
assign wb_err_o = 1'b0;
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (wb_clk_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr(adr_r[aw-1:2]),
.raddr (adr[aw-1:2]),
.dout (wb_dat_o));
endmodule
|
//
// lfsr128.v -- a linear feedback shift register with 128 bits
// (actually constructed from 4 instances of a 32-bit lfsr)
//
module lfsr128(clk, reset_in_n, s, rs232_txd);
input clk;
input reset_in_n;
output [3:0] s;
output rs232_txd;
wire reset;
reg [23:0] reset_counter;
reg [31:0] lfsr0;
reg [31:0] lfsr1;
reg [31:0] lfsr2;
reg [31:0] lfsr3;
wire trigger;
wire sample;
wire [127:0] log_data;
assign reset = (reset_counter == 24'hFFFFFF) ? 0 : 1;
always @(posedge clk) begin
if (reset_in_n == 0) begin
reset_counter <= 24'h000000;
end else begin
if (reset_counter != 24'hFFFFFF) begin
reset_counter <= reset_counter + 1;
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
lfsr0 <= 32'hC70337DB;
lfsr1 <= 32'h7F4D514F;
lfsr2 <= 32'h75377599;
lfsr3 <= 32'h7D5937A3;
end else begin
if (lfsr0[0] == 0) begin
lfsr0 <= lfsr0 >> 1;
end else begin
lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
end
if (lfsr1[0] == 0) begin
lfsr1 <= lfsr1 >> 1;
end else begin
lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
end
if (lfsr2[0] == 0) begin
lfsr2 <= lfsr2 >> 1;
end else begin
lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
end
if (lfsr3[0] == 0) begin
lfsr3 <= lfsr3 >> 1;
end else begin
lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
end
end
end
assign s[3] = lfsr0[27];
assign s[2] = lfsr1[13];
assign s[1] = lfsr2[23];
assign s[0] = lfsr3[11];
assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
assign sample = 1;
assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
endmodule
|
/**
* bsg_mesh_router_decoder_dor.v
*
* Dimension ordered routing decoder
*
* depopulated ruche router.
*/
module bsg_mesh_router_decoder_dor
import bsg_noc_pkg::*;
import bsg_mesh_router_pkg::*;
#(parameter `BSG_INV_PARAM(x_cord_width_p )
, parameter `BSG_INV_PARAM(y_cord_width_p )
, parameter dims_p = 2
, parameter dirs_lp = (2*dims_p)+1
, parameter ruche_factor_X_p=0
, parameter ruche_factor_Y_p=0
// XY_order_p = 1 : X then Y
// XY_order_p = 0 : Y then X
, parameter XY_order_p = 1
, parameter from_p = {dirs_lp{1'b0}} // one-hot, indicates which direction is the input coming from.
, parameter debug_p = 0
)
(
input clk_i // debug only
, input reset_i // debug only
//, input v_i
, input [x_cord_width_p-1:0] x_dirs_i
, input [y_cord_width_p-1:0] y_dirs_i
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, output [dirs_lp-1:0] req_o
);
// check parameters
// synopsys translate_off
initial begin
if (ruche_factor_X_p > 0) begin
assert(dims_p > 2) else $fatal(1, "ruche in X direction requires dims_p greater than 2.");
end
if (ruche_factor_Y_p > 0) begin
assert(dims_p > 3) else $fatal(1, "ruche in Y direction requires dims_p greater than 3.");
end
assert($countones(from_p) == 1) else $fatal(1, "Must define from_p as one-hot value.");
assert(ruche_factor_X_p < (1<<x_cord_width_p)) else $fatal(1, "ruche factor in X direction is too large");
assert(ruche_factor_Y_p < (1<<y_cord_width_p)) else $fatal(1, "ruche factor in Y direction is too large");
end
// synopsys translate_on
// compare coordinates
wire x_eq = (x_dirs_i == my_x_i);
wire y_eq = (y_dirs_i == my_y_i);
wire x_gt = x_dirs_i > my_x_i;
wire y_gt = y_dirs_i > my_y_i;
wire x_lt = ~x_gt & ~x_eq;
wire y_lt = ~y_gt & ~y_eq;
// valid signal
logic [dirs_lp-1:0] req;
assign req_o = req;
// P-port
assign req[P] = x_eq & y_eq;
if (ruche_factor_X_p > 0) begin
if (XY_order_p) begin
// make sure there is no under/overflow.
wire [x_cord_width_p:0] re_cord = (x_cord_width_p+1)'(my_x_i + ruche_factor_X_p);
wire send_rw = (my_x_i > (x_cord_width_p)'(ruche_factor_X_p)) & (x_dirs_i < (my_x_i - (x_cord_width_p)'(ruche_factor_X_p)));
wire send_re = ~re_cord[x_cord_width_p] & (x_dirs_i > re_cord[0+:x_cord_width_p]);
assign req[W] = x_lt & ~send_rw;
assign req[RW] = send_rw;
assign req[E] = x_gt & ~send_re;
assign req[RE] = send_re;
end
else begin
if (from_p[S] | from_p[N] | from_p[P]) begin
assign req[W] = y_eq & x_lt;
assign req[RW] = 1'b0;
assign req[E] = y_eq & x_gt;
assign req[RE] = 1'b0;
end
else if(from_p[W]) begin
wire [x_cord_width_p-1:0] dx = (x_cord_width_p)'((x_dirs_i - my_x_i) % ruche_factor_X_p);
assign req[RE] = y_eq & x_gt & (dx == '0);
assign req[E] = y_eq & x_gt & (dx != '0);
assign req[RW] = 1'b0;
assign req[W] = 1'b0;
end
else if (from_p[E]) begin
wire [x_cord_width_p-1:0] dx = (x_cord_width_p)'((my_x_i - x_dirs_i) % ruche_factor_X_p);
assign req[RE] = 1'b0;
assign req[E] = 1'b0;
assign req[RW] = y_eq & x_lt & (dx == '0);
assign req[W] = y_eq & x_lt & (dx != '0);
end
else if (from_p[RW]) begin
assign req[RE] = y_eq & x_gt;
assign req[E] = 1'b0;
assign req[RW] = 1'b0;
assign req[W] = 1'b0;
end
else if (from_p[RE]) begin
assign req[RE] = 1'b0;
assign req[E] = 1'b0;
assign req[RW] = y_eq & x_lt;
assign req[W] = 1'b0;
end
end
end
else begin
if (XY_order_p) begin
assign req[W] = x_lt;
assign req[E] = x_gt;
end
else begin
assign req[W] = y_eq & x_lt;
assign req[E] = y_eq & x_gt;
end
end
if (ruche_factor_Y_p > 0) begin
if (XY_order_p == 0) begin
// make sure there is no under/overflow.
wire [y_cord_width_p:0] rs_cord = (y_cord_width_p+1)'(my_y_i + ruche_factor_Y_p);
wire send_rn = (my_y_i > (y_cord_width_p)'(ruche_factor_Y_p)) & (y_dirs_i < (my_y_i - (y_cord_width_p)'(ruche_factor_Y_p)));
wire send_rs = ~rs_cord[y_cord_width_p] & (y_dirs_i > rs_cord[0+:y_cord_width_p]);
assign req[N] = y_lt & ~send_rn;
assign req[RN] = send_rn;
assign req[S] = y_gt & ~send_rs;
assign req[RS] = send_rs;
end
else begin
if (from_p[E] | from_p[W] | from_p[P]) begin
assign req[N] = x_eq & y_lt;
assign req[RN] = 1'b0;
assign req[S] = x_eq & y_gt;
assign req[RS] = 1'b0;
end
else if (from_p[N]) begin
wire [y_cord_width_p-1:0] dy = (y_cord_width_p)'((y_dirs_i - my_y_i) % ruche_factor_Y_p);
assign req[RS] = x_eq & y_gt & (dy == '0);
assign req[S] = x_eq & y_gt & (dy != '0);
assign req[RN] = 1'b0;
assign req[N] = 1'b0;
end
else if (from_p[S]) begin
wire [y_cord_width_p-1:0] dy = (y_cord_width_p)'((my_y_i - y_dirs_i) % ruche_factor_Y_p);
assign req[RS] = 1'b0;
assign req[S] = 1'b0;
assign req[RN] = x_eq & y_lt & (dy == '0);
assign req[N] = x_eq & y_lt & (dy != '0);
end
else if (from_p[RN]) begin
assign req[RS] = x_eq & y_gt;
assign req[S] = 1'b0;
assign req[RN] = 1'b0;
assign req[N] = 1'b0;
end
else if (from_p[RS]) begin
assign req[RS] = 1'b0;
assign req[S] = 1'b0;
assign req[RN] = x_eq & y_lt;
assign req[N] = 1'b0;
end
end
end
else begin
if (XY_order_p == 0) begin
assign req[N] = y_lt;
assign req[S] = y_gt;
end
else begin
assign req[N] = x_eq & y_lt;
assign req[S] = x_eq & y_gt;
end
end
// synopsys translate_off
if (debug_p) begin
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
assert($countones(req_o) < 2)
else $fatal(1, "multiple req_o detected. %b", req_o);
end
end
end
else begin
wire unused0 = clk_i;
wire unused1 = reset_i;
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesh_router_decoder_dor)
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, ans = 0, odd = 0, ev = 0; cin >> n; int a[n + 1]; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] & 1) odd++; else ev++; } if (n == 1) { if (odd) cout << Yes ; else cout << No ; return 0; } if (a[0] % 2 == 0 || a[n - 1] % 2 == 0) { cout << No ; } else { if (n & 1) { if (odd >= 2) cout << Yes ; else cout << No ; } else { cout << No ; } } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// software programmable clock generator (still needs a reference input!)
`timescale 1ns/100ps
module axi_clkgen #(
parameter ID = 0,
parameter DEVICE_TYPE = 0,
parameter CLKSEL_EN = 0,
parameter real CLKIN_PERIOD = 5.000,
parameter real CLKIN2_PERIOD = 5.000,
parameter integer VCO_DIV = 11,
parameter real VCO_MUL = 49.000,
parameter real CLK0_DIV = 6.000,
parameter real CLK0_PHASE = 0.000,
parameter integer CLK1_DIV = 6,
parameter real CLK1_PHASE = 0.000) (
// clocks
input clk,
input clk2,
output clk_0,
output clk_1,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// reset and clocks
wire mmcm_rst;
wire clk_sel_s;
wire up_clk_sel_s;
wire up_rstn;
wire up_clk;
// internal signals
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_clkgen #(
.ID(ID)
) i_up_clkgen (
.mmcm_rst (mmcm_rst),
.clk_sel (up_clk_sel_s),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// If CLKSEL_EN is not active, the clk0 port of the MMCM is used, this
// should be used when the MMCM has only one active clock source
generate if (CLKSEL_EN == 1) begin
assign clk_sel_s = up_clk_sel_s;
end else begin
assign clk_sel_s = 1'b1;
end
endgenerate
// mmcm instantiations
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (CLKIN_PERIOD),
.MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD),
.MMCM_VCO_DIV (VCO_DIV),
.MMCM_VCO_MUL (VCO_MUL),
.MMCM_CLK0_DIV (CLK0_DIV),
.MMCM_CLK0_PHASE (CLK0_PHASE),
.MMCM_CLK1_DIV (CLK1_DIV),
.MMCM_CLK1_PHASE (CLK1_PHASE))
i_mmcm_drp (
.clk (clk),
.clk2 (clk2),
.clk_sel(clk_sel_s),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk_0),
.mmcm_clk_1 (clk_1),
.mmcm_clk_2 (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; string board[8]; int main() { for (int i = 0; i < 8; ++i) cin >> board[i]; const char* s = WB ; for (int i = 0; i < 8; ++i) { int c = board[i][0] == B ; for (int j = 1; j < 8; ++j) { if (board[i][j] != s[(c + j) % 2]) { cout << NO n ; return 0; } } } cout << YES n ; return 0; } |
module usb_sequencer
(
input clk,
input reset_n,
input rxf_n,
input txe_n,
input panel_select_request,
input [15:0] panel_switches,
output reg [7:0] data_out,
output rd_n,
output wr_n,
output data_out_enable,
output command_write_enable,
output clear_psr,
output [4:0] state_out
);
reg [4:0] state, next_state, output_bits;
assign state_out = state;
assign rd_n = output_bits[4];
assign wr_n = output_bits[3];
assign data_out_enable = output_bits[2];
assign command_write_enable = output_bits[1];
assign clear_psr = output_bits[0];
// Labeled states
localparam [4:0]
start_read = 5'd0,
end_read = 5'd7,
start_write = 5'd8,
write_p1 = 5'd13,
write_p2 = 5'd18,
write_p3 = 5'd23,
end_write = 5'd28;
// State register
always @(posedge clk, negedge reset_n)
if (!reset_n)
state <= start_read;
else
state <= next_state;
// Next state logic
always @(*)
case (state)
start_read:
if (panel_select_request)
next_state = start_write;
else
if (rxf_n)
next_state = start_read;
else
next_state = state + 1'b1;
end_read:
if (panel_select_request)
next_state = start_write;
else
next_state = start_read;
start_write:
if (txe_n)
next_state = start_write;
else
next_state = state + 1'b1;
write_p1:
if (txe_n)
next_state = write_p1;
else
next_state = state + 1'b1;
write_p2:
if (txe_n)
next_state = write_p2;
else
next_state = state + 1'b1;
write_p3:
if (txe_n)
next_state = write_p3;
else
next_state = state + 1'b1;
end_write:
next_state = start_read;
default:
next_state = state + 1'b1;
endcase // case (state)
// Output logic
always @(*)
if (!reset_n)
begin
data_out = 8'hzz;
output_bits = 4'b1100;
end
else
case (state)
0: // start_read
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
1: //
begin
data_out = 8'hzz;
output_bits = 5'b01000;
end
2: //
begin
data_out = 8'hzz;
output_bits = 5'b01000;
end
3: //
begin
data_out = 8'hzz;
output_bits = 5'b01000;
end
4: //
begin
data_out = 8'hzz;
output_bits = 5'b11010;
end
5: //
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
6: //
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
7: // end_read
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
8: // start_write
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
9: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b11100;
end
10: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b10100;
end
11: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b10100;
end
12: //
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b11100;
end
13: // write_p1
begin
data_out = {4'h1, panel_switches[3:0]};
output_bits = 5'b11100;
end
14: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b11100;
end
15: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b10100;
end
16: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b10100;
end
17: //
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b11100;
end
18: // write_p2
begin
data_out = {4'h2, panel_switches[7:4]};
output_bits = 5'b11100;
end
19: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b11100;
end
20: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b10100;
end
21: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b10100;
end
22: //
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b11100;
end
23: // write_p3
begin
data_out = {4'h3, panel_switches[11:8]};
output_bits = 5'b11100;
end
24: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b11100;
end
25: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b10100;
end
26: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b10100;
end
27: //
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b11101;
end
28: // end_write
begin
data_out = {4'h4, panel_switches[15:12]};
output_bits = 5'b11100;
end
default: // default
begin
data_out = 8'hzz;
output_bits = 5'b11000;
end
endcase // case (state)
endmodule // usb_sequencer
|
#include <bits/stdc++.h> using namespace std; long long a[200100], sum[200100], qs[200100]; bool bad(pair<long long, long long> &a, pair<long long, long long> &b, pair<long long, long long> second) { return (a.second - second.second) * (b.first - a.first) > (a.second - b.second) * (second.first - a.first); } long long at(pair<long long, long long> a, long long x) { return a.first * x + a.second; } int back = 0; pair<long long, long long> l[200100]; void add(long long first, long long second) { if (back >= 2 and bad(l[back - 2], l[back - 1], {first, second})) back--; l[back++] = {first, second}; } long long query(long long x, int L = 0, int R = back - 1) { if (L + 1 == R) return max(at(l[L], x), at(l[R], x)); if (L == R) return at(l[L], x); int mid = (L + R) / 2; if (at(l[mid], x) < at(l[mid - 1], x)) return query(x, L, mid - 1); if (at(l[mid], x) < at(l[mid + 1], x)) return query(x, mid + 1, R); return at(l[mid], x); } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]), qs[i] = a[i] + qs[i - 1], sum[i] = a[i] * i + sum[i - 1]; long long ans = 0; add(0, 0); for (int i = 1; i <= n; i++) { ans = max(ans, sum[i] + query(qs[i])); add(-i, -sum[i] + i * qs[i]); } printf( %lld , ans); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_gt_rx_valid_filter_7x.v
// Version : 1.10
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
module pcie_core_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100000 + 10; int a[MAXN], n; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); if (a[n - 1] == 1) { puts( NO ); return 0; } if (n == 1 && a[0] == 0) { puts( YES n0 ); return 0; } int cnt(0), c1(0); for (int i = 0; i < n && a[i]; ++i) ++c1; for (int i = n - 1; i >= 0 && !a[i]; --i) ++cnt; if (c1 + cnt == n && cnt == 2) { puts( NO ); return 0; } puts( YES ); if (cnt == 1) { printf( %d , a[0]); for (int i = 1; i < n; ++i) printf( ->%d , a[i]); puts( ); return 0; } if (cnt >= 3) { for (int i = 0; i < n - 3; ++i) { printf( %d-> , a[i]); } printf( (0->0)->0 n ); return 0; } int x; for (x = n - 3; x >= 0 && a[x]; --x) ; for (int i = 0; i < x; ++i) printf( %d-> , a[i]); printf( (0->( ); for (int i = x + 1; i < n - 2; ++i) printf( 1-> ); printf( 0))->0 n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 19:42:00 09/01/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: TF_EECS301_Lab3_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: EECS301 Lab3 Top Level Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_EECS301_Lab3_TopLevel();
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
reg CLOCK_50;
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: CLS_LED_Output_Fader
//
wire [9:0] LEDR;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
wire [6:0] HEX4;
wire [6:0] HEX5;
reg [3:0] KEY;
reg [1:0] SW;
EECS301_Lab3_TopLevel
#(
// Shorten the delay times for simulation
.KEY_LOCK_DELAY( 100000 ), // 100 uS
.SW_DEBOUNCE_TIME( 100 ), // 100 nS
.PWM_DUTY_RATE( 100000 ), // 100 kHz
.FADE_RATE_HZ( 10000 ) // 10 kHz
)
uut
(
// Clock Signals
.CLOCK_50( CLOCK_50 ),
// LED Signals
.LEDR( LEDR ),
// 7-Segment Display Signals (Active-Low)
.HEX0( HEX0 ),
.HEX1( HEX1 ),
.HEX2( HEX2 ),
.HEX3( HEX3 ),
.HEX4( HEX4 ),
.HEX5( HEX5 ),
// Button Signals (Active-Low)
.KEY( KEY ),
// Switch Signals
.SW( SW )
);
//
// Test Stimulus
//
initial
begin
// Initialize Signals
KEY = 4'hF; // Active-Low
SW = 2'h3;
#1000;
//
// Begin Testing
//
KEY[0] = 1'b0; // Press LED1 Right Button
KEY[3] = 1'b0; // Press LED2 Left Button
// Wait 5 ms
#;
KEY[0] = 1'b1; // Release LED1 Right Button
KEY[1] = 1'b0; // Press LED1 Left Button
KEY[3] = 1'b0; // Press LED2 Left Button
// Wait 5 ms
#;
KEY[3] = 1'b1; // Release LED2 Left Button
KEY[1] = 1'b0; // Press LED1 Left Button
KEY[2] = 1'b0; // Press LED2 Right Button
// Run simulation for 15 mS
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1505; const int MOD = 1000000007; inline int add(int x, int y) { return x + y >= MOD ? x + y - MOD : x + y; } inline int sub(int x, int y) { return x - y < 0 ? x - y + MOD : x - y; } inline int mul(int x, int y) { return 1ll * x * y % MOD; } inline void inc(int &x, int y) { x = add(x, y); } inline void dec(int &x, int y) { x = sub(x, y); } inline void grow(int &x, int y) { x = mul(x, y); } int bpow(int a, int b) { int res = 1; while (b) { if (b & 1) grow(res, a); grow(a, a); b >>= 1; } return res; } int inv(int x) { return bpow(x, MOD - 2); } int n, m, p, k; int f[N], dp[N][N], sdp[N][N], sf[N], sfdp[N], fact[100005]; int comb(int a, int b) { return mul(fact[a], mul(inv(fact[b]), inv(fact[a - b]))); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; int _a, _b; cin >> _a >> _b; p = mul(_a, inv(_b)); cin >> k; fact[0] = 1; for (int i = 1; i <= k; i++) fact[i] = mul(fact[i - 1], i); for (int i = 0; i <= min(k, m); i++) f[i] = mul(comb(k, i), mul(bpow(p, i), bpow(sub(1, p), k - i))); sf[0] = f[0]; for (int i = 1; i <= m; i++) sf[i] = add(sf[i - 1], f[i]); dp[0][m] = sdp[0][m] = 1; for (int i = 1; i <= n; i++) { memset(sfdp, 0, sizeof sfdp); for (int r = 1; r <= m; r++) sfdp[r] = add(sfdp[r - 1], mul(f[r], sdp[i - 1][r])); for (int r = 1; r <= m; r++) dp[i][r] = mul(f[m - r], sub(mul(sf[r - 1], sub(sdp[i - 1][m], sdp[i - 1][m - r])), sfdp[r - 1])); for (int r = 1; r <= m; r++) sdp[i][r] = add(sdp[i][r - 1], dp[i][r]); } cout << sdp[n][m] << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; int a, b, q; cin >> q; for (int i = 0; i < q; i++) { cin >> n >> a >> b; if (a * 2 <= b) cout << n * a << endl; else { { if (n % 2 == 0) cout << b * n / 2 << endl; else cout << b * (n / 2) + a << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { register int num = 0; register char ch = getchar(); while (ch > 9 || ch < 0 ) ch = getchar(); while (ch <= 9 && ch >= 0 ) num = num * 10 + ch - 0 , ch = getchar(); return num; } int num[10]; inline void write(int x) { register int cnt = 0; if (!x) { printf( 0 ); return; } while (x) num[++cnt] = x % 10, x /= 10; while (cnt) putchar(num[cnt--] + 0 ); } struct node { int next, to, w; } e[300020 * 2]; int n, m; int head[300020], cnt; int sz[300020], fa[300020], tag[300020], a[300020], tot, flag; long long dth[300020], ans, mx[300020], dis[300020]; inline void adde(int x, int y, int w) { e[++cnt].to = y; e[cnt].next = head[x]; e[cnt].w = w; head[x] = cnt; } void dfs(int x) { for (int i = head[x]; i; i = e[i].next) { if (e[i].to == fa[x]) continue; dth[e[i].to] = dth[x] + e[i].w; fa[e[i].to] = x; dfs(e[i].to); } } void dfs2(int x) { sz[x] = 1; for (int i = head[x]; i; i = e[i].next) { if (e[i].to == fa[x] || tag[e[i].to]) continue; dis[x] = max(dis[x], dis[e[i].to] + e[i].w); dfs2(e[i].to); sz[x] += sz[e[i].to]; } } void init() { dfs(1); int x = n; while (x) tag[x] = 1, a[++tot] = x, x = fa[x]; for (register int i = 1; i <= tot + 1; i++) mx[i] = -1e16; for (register int i = tot; i >= 1; i--) { int x = a[i]; dfs2(x); if (sz[x] > 1) mx[i] = max(mx[i + 1], dis[x] + dth[x]); if (i < tot) { ans = max(ans, dth[n] + dis[x] - dth[x] + mx[i + 1]); if (sz[x] > 1) ans = max(ans, dth[n] + dis[x] - dth[x] + dth[a[i + 1]]); else if (i < tot - 1) ans = max(ans, dth[n] + dis[x] - dth[x] + dth[a[i + 2]]); } if (sz[x] > 2) flag = 1; } } int main() { scanf( %d %d , &n, &m); for (register int i = 1; i <= n - 1; i++) { int x, y, w; scanf( %d %d %d , &x, &y, &w); adde(x, y, w), adde(y, x, w); } init(); while (m--) { int l = read(); long long cur = min(dth[n], ans + l); if (flag) cur = max(cur, dth[n]); printf( %I64d n , cur); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const int inf = -INF; const int N = 100005; const int M = 2005; const int mod = 1000000007; const double pi = acos(-1.0); int mp1[N], mp2[N]; int main() { int n, m; int d, p; char s[2]; scanf( %d %d , &n, &m); memset(mp1, 0, sizeof(mp1)); memset(mp2, 0, sizeof(mp2)); for (int i = 1; i <= n; i++) { scanf( %s %d %d , &s, &p, &d); if (s[0] == S ) mp1[p] += d; else mp2[p] += d; } int k = 0, t = 0; for (int it = 0; it < N, t < m; it++) { if (it > 100000) break; if (mp1[it] > 0) t++, k = it; } for (int j = k; j >= 0; j--) if (mp1[j] > 0) printf( S %d %d n , j, mp1[j]); t = 0; for (int it = N; it >= 0 && t < m; it--) { if (mp2[it] > 0) printf( B %d %d n , it, mp2[it]), t++; } } |
#include <bits/stdc++.h> const int ms = 500500; std::string str[ms], ans[ms]; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); int n; std::cin >> n; for (int i = 0; i < n; i++) std::cin >> str[i]; ans[n - 1] = str[n - 1]; for (int i = n - 2; i >= 0; i--) { int type = 0; int to = 0; for (; to < str[i].size() && to < ans[i + 1].size(); to++) { if (str[i][to] < ans[i + 1][to]) type = 1; else if (str[i][to] > ans[i + 1][to]) type = 2; if (type) break; } if (type == 0 || type == 2) { for (int j = 0; j < to; j++) ans[i] += str[i][j]; } else if (type == 1) { ans[i] = str[i]; } } for (int i = 0; i < n; i++) std::cout << ans[i] << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, q, num; cin >> n >> q; vector<int> a(n), b(n), c(n); for (int i = 0; i < n; ++i) cin >> a[i]; b[0] = a[0]; for (int i = 1; i < n; ++i) { b[i] = max(a[i], b[i - 1]); if (b[i] == a[i]) c[i - 1] = b[i - 1]; else c[i - 1] = a[i]; } while (q--) { cin >> num; if (num < n) cout << b[num - 1] << << a[num] << endl; else cout << b[n - 1] << << c[(num - 1) % (n - 1)] << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, count = 0; for (int i = 0; i < 5; i++) { for (int j = 0; j < 5; j++) { cin >> n; if (n == 1) { count = abs(2 - i) + abs(2 - j); cout << count << endl; return 0; } } } cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[1001], x; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d , &x); a[x]++; } sort(a + 1, a + n + 1); printf( %d n , a[1]); return 0; } |
/**********************************************************************************
* *
* This verilog file is a part of the Boundary Scan Implementation and comes in *
* a pack with several other files. It is fully IEEE 1149.1 compliant. *
* For details check www.opencores.org (pdf files, bsdl file, etc.) *
* *
* Copyright (C) 2000 Igor Mohor () and OPENCORES.ORG *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* See the file COPYING for the full details of the license. *
* *
* OPENCORES.ORG is looking for new open source IP cores and developers that *
* would like to help in our mission. *
* *
**********************************************************************************/
/**********************************************************************************
* *
* Input Cell: *
* *
* InputPin: Value that comes from on-chip logic and goes to pin *
* FromPreviousBSCell: Value from previous boundary scan cell *
* ToNextBSCell: Value for next boundary scan cell *
* CaptureDR, ShiftDR: TAP states *
* TCK: Test Clock *
* *
**********************************************************************************/
// This is not a top module
module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell);
input InputPin;
input FromPreviousBSCell;
input CaptureDR;
input ShiftDR;
input TCK;
reg Latch;
output ToNextBSCell;
reg ToNextBSCell;
wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell;
always @ (posedge TCK)
begin
if(CaptureDR | ShiftDR)
Latch<=SelectedInput;
end
always @ (negedge TCK)
begin
ToNextBSCell<=Latch;
end
endmodule // InputCell |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_SYMBOL_V
`define SKY130_FD_SC_LP__A32O_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a32o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_1_V
`define SKY130_FD_SC_HS__SDFBBN_1_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_1_V
|
#include <bits/stdc++.h> using namespace std; const int N(1e5 + 5), M(1e5 + 5); struct edge { int u, v, nt, type, flag; } E[M << 1]; int head[N]; int d[N]; queue<int> que; void bfs(int s, int *d) { memset(d, -1, sizeof(int[N])); que.push(s), d[s] = 0; while (!que.empty()) { int u = que.front(); que.pop(); for (int i = head[u]; ~i; i = E[i].nt) { int &v = E[i].v; if (~d[v]) continue; d[v] = d[u] + 1, que.push(v); } } } int ans; void find_path(int u, int t, int cnt) { if (u == t) { ans = min(ans, cnt); return; } for (int i = head[u]; ~i; i = E[i].nt) { int &v = E[i].v; if (d[v] != d[u] + 1) continue; find_path(v, t, cnt + !E[i].type); } } bool label_path(int u, int t, int cnt) { if (u == t) return ans == cnt; for (int i = head[u]; ~i; i = E[i].nt) { int &v = E[i].v; if (d[v] != d[u] + 1) continue; if (label_path(v, t, cnt + !E[i].type)) { E[i].flag = E[i ^ 1].flag = 1; return true; } } return false; } int main() { int n, m, good = 0; scanf( %d%d , &n, &m); memset(head, -1, sizeof(head)); for (int u, v, type, id = 0, _ = m; _--;) { scanf( %d%d%d , &u, &v, &type); E[id] = {u, v, head[u], type, 0}, head[u] = id++; E[id] = {v, u, head[v], type, 0}, head[v] = id++; good += type; } bfs(1, d); ans = INT_MAX; find_path(1, n, 0); label_path(1, n, 0); printf( %d n , 2 * ans + good - d[n]); for (int i = 0; i < 2 * m; i += 2) { if (E[i].type ^ E[i].flag) printf( %d %d %d n , E[i].u, E[i].v, !E[i].type); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10, mod = 1e9 + 7; const long long inf = 1e18; int x[maxn], frs[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, z; cin >> n >> z; for (int i = 0; i < n; i++) { cin >> x[i]; } sort(x, x + n); int pt = 0; for (int i = 0; i < n; i++) { pt = max(pt, i + 1); while (pt < n && x[pt] - x[i] < z) pt++; frs[i] = pt; } int l = 0, r = (n / 2) + 1; while (r - l > 1) { int mid = (l + r) >> 1; int pt = mid - 1; for (int i = 0; i < mid; i++) { pt = max(pt + 1, frs[i]); } if (pt >= n) r = mid; else l = mid; } return cout << l << endl, 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<pair<long long, int>> xs(n); for (int i = 0; i < xs.size(); ++i) { cin >> xs[i].first; xs[i].second = i + 1; } sort(xs.begin(), xs.end()); int k; cin >> k; vector<long long> sums1(n), sums2(n); int qk = 2; long long sumsl = 0; int jl = 0; long long cur_sum = 0; long long min_sum = -1; int min_pos = -1; for (int i = 1; i < k; ++i) { sumsl += xs[i].first - xs[0].first; } for (int i = 1; i < xs.size(); ++i) { sums1[i] = sums1[i - 1] + (xs[i].first - xs[i - 1].first) * (qk - 1); if (qk <= k) { qk++; cur_sum += sums1[i]; } else { sums1[i] -= xs[i].first - xs[jl].first; ++jl; cur_sum = cur_sum + sums1[i] - sumsl; sumsl = sumsl - (xs[jl].first - xs[jl - 1].first) * (k - 1) + (xs[i].first - xs[jl].first); } if (qk > k) { if (min_sum == -1 || cur_sum < min_sum) { min_sum = cur_sum; min_pos = i; } } } for (int i = 0; i < k; ++i) { cout << xs[min_pos - i].second << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using lint = long long; int n, x, y; bool ask_1y(const vector<int>& a) { if (a.empty()) { return false; } cout << ? << a.size(); for (int i : a) { cout << << i + 1; } cout << endl; int r; cin >> r; return r == y || r == (x ^ y); } bool same[11]; void solve(istream& cin, ostream& cout) { cin >> n >> x >> y; int hb = -1; for (int i = 0; i < 10; i++) { vector<int> a; for (int j = (0); j < int(n); ++j) { if ((((j) >> (i)) & 1)) { a.push_back(j); } } if (ask_1y(a)) { hb = i; } else { same[i] = true; } } int a = 0; int b = 0; for (int i = 0; i < 10; i++) { if (i == hb) { b |= (1 << (hb)); continue; } vector<int> v; for (int j = (0); j < int(n); ++j) { if (!(((j) >> (i)) & 1) && !(((j) >> (hb)) & 1)) { v.push_back(j); } } if (ask_1y(v)) { if (!same[i]) { b |= (1 << (i)); } } else { a |= (1 << (i)); if (same[i]) { b |= (1 << (i)); } } } cout << ! << a + 1 << << b + 1 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(cin, cout); return 0; } |
#include <bits/stdc++.h> using namespace std; void fileio() {} vector<vector<long long int>> g; vector<long long int> bit; long long int n; void add(long long int i, long long int x) { while (i <= n) { bit[i] += x; i += (i & (-i)); } } long long int query(long long int i) { long long int sum = 0; while (i > 0) { sum += bit[i]; i -= (i & (-i)); } return sum; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); fileio(); cin >> n; bit = vector<long long int>(n + 1, 0); vector<long long int> p(n, 0), candi(n + 1, 0), contri(n + 1, 0); set<long long int> s; for (long long int i = 0; i < n; i++) { cin >> p[i]; long long int more = query(n) - query(p[i]); add(p[i], 1); if (more == 1) { long long int x = (*s.rbegin()); candi[x]++; } if (more == 0) { contri[p[i]]++; } s.insert(p[i]); } long long int res = 1; for (long long int i = 1; i <= n; i++) if (candi[i] - contri[i] > candi[res] - contri[res]) res = i; cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const long long MOD = 998244353; const long long N = (long long)1e4 + 9; const long long inf = 1 << 30; template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } template <typename T> T exp(T b, T p) { T x = 1; while (p) { if (p & 1) x = (x * b); b = (b * b); p = p >> 1; } return x; } inline long long ones(long long n) { long long res = 0; while (n && ++res) n -= n & (-n); return res; } inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } long long mem[109][3]; long long n, arr[109]; long long go(long long idx, long long last) { if (idx == n) return 0; long long &ret = mem[idx][last]; if (ret != -1) return ret; ret = -inf; if (arr[idx] == 0) ret = go(idx + 1, 0); if (arr[idx] == 3) { if (last != 1) ret = max(ret, 1 + go(idx + 1, 1)); if (last != 2) ret = max(ret, 1 + go(idx + 1, 2)); } if (arr[idx] == 1) { if (last != 1) ret = 1 + go(idx + 1, 1); else ret = go(idx + 1, 0); } if (arr[idx] == 2) { if (last != 2) ret = 1 + go(idx + 1, 2); else ret = go(idx + 1, 0); } return ret; } int32_t main() { ios::sync_with_stdio(0); cin.tie(nullptr); cout.tie(0); cin >> n; for (long long i = 0; i < n; ++i) { cin >> arr[i]; } memset(mem, -1, sizeof(mem)); long long ans = go(0, 0); cout << n - ans; } |
#include <bits/stdc++.h> using namespace std; double v[1000006], t[1000006]; int main() { int n, i; double a, d; scanf( %d , &n); scanf( %lf , &a); scanf( %lf , &d); for (i = 0; i < n; i++) { scanf( %lf , &t[i]); scanf( %lf , &v[i]); } double t0 = sqrt(2 * d / a); double v0 = a * t0; double prevt = -1, curt; for (i = 0; i < n; i++) { if (v[i] >= v0) { curt = t[i] + t0; } else { double t1 = v[i] / a; double d1 = 0.5 * a * t1 * t1; double t2 = (d - d1) / v[i]; curt = t[i] + t1 + t2; } curt = max(curt, prevt); printf( %.9lf n , curt); prevt = curt; } return 0; } |
// part of NeoGS project (c) 2007-2008 NedoPC
//
// interrupt controller for Z80
module interrupts(
clk_24mhz,
clk_z80,
m1_n,
iorq_n,
int_n
);
parameter MAX_INT_LEN = 100;
input clk_24mhz;
input clk_z80;
input m1_n;
input iorq_n;
output reg int_n;
reg [9:0] ctr640;
reg int_24;
reg int_sync1,int_sync2,int_sync3;
reg int_ack_sync,int_ack;
reg int_gen;
// generate int signal
always @(posedge clk_24mhz)
begin
if( ctr640 == 10'd639 )
ctr640 <= 10'd0;
else
ctr640 <= ctr640 + 10'd1;
if( ctr640 == 10'd0 )
int_24 <= 1'b1;
else if( ctr640 == MAX_INT_LEN )
int_24 <= 1'b0;
end
// generate interrupt signal in clk_z80 domain
always @(negedge clk_z80)
begin
int_sync3 <= int_sync2;
int_sync2 <= int_sync1;
int_sync1 <= int_24; // sync in from 24mhz, allow for edge detection (int_sync3!=int_sync2)
int_ack_sync <= ~(m1_n | iorq_n);
int_ack <= int_ack_sync; // interrupt acknowledge from Z80
// control interrupt generation signal
if( int_ack || ( int_sync3 && (!int_sync2) ) )
int_gen <= 1'b0;
else if( (!int_sync3) && int_sync2 )
int_gen <= 1'b1;
end
always @(posedge clk_z80)
begin
int_n <= ~int_gen;
end
endmodule
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'h0;
else begin
if(byte_received)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b001)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule |
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
// Linear feedback shift register.
//
// Useful as a simple psuedo-random number generator.
module LFSR #(
parameter WIDTH = 16,
parameter POLY = 16'hD008
) (
input rst,
input clk,
input [WIDTH-1:0] seed,
output reg [WIDTH-1:0] r
);
wire feedback = ^(r & POLY);
always @(posedge clk) begin
if(rst) begin
r <= seed;
end else begin
r <= {r[WIDTH-2:0], feedback};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 150, M = 65; int n; int dist[N][N], g[N][N]; vector<long long> v[M]; map<long long, int> mp; int main() { memset(g, 0x3f, sizeof g); memset(dist, 0x3f, sizeof dist); cin >> n; for (int i = 0; i < n; i++) { long long t, x; cin >> x; t = x; int cnt = 0; while (t) { if (t & 1) v[cnt].push_back(x); t >>= 1; cnt++; } } int cnt = 0; bool flag = false; for (int i = 0; i <= 64; i++) { int m = v[i].size(); if (!m) continue; else if (m > 2) { flag = true; break; } else if (m == 2) { long long x = v[i][0], y = v[i][1]; if (!mp[x]) mp[x] = ++cnt; if (!mp[y]) mp[y] = ++cnt; x = mp[x], y = mp[y]; g[x][y] = g[y][x] = 1; dist[x][y] = dist[y][x] = 1; } } if (flag) cout << 3 << endl; else { int res = 0x3f3f3f3f; for (int k = 1; k <= cnt; k++) { for (int i = 1; i < k; i++) if (g[k][i] == 1) for (int j = i + 1; j < k; j++) if (g[k][j] == 1) if (dist[i][j] != 0x3f3f3f3f) res = min(res, dist[i][j] + g[i][k] + g[j][k]); for (int i = 1; i <= cnt; i++) if (dist[i][k] != 0x3f3f3f3f) for (int j = 1; j <= cnt; j++) if (dist[k][j] != 0x3f3f3f3f) dist[i][j] = min(dist[i][j], dist[i][k] + dist[k][j]); } if (res != 0x3f3f3f3f) cout << res << endl; else cout << -1 << endl; } } |
#include <bits/stdc++.h> using namespace std; const int maxm = 1e5 + 5; vector<int> g[maxm]; int n, q; int sz[maxm]; int d[maxm]; int f[maxm][25]; const int maxd = 20; void dfs(int x, int fa) { sz[x] = 1; for (int j = 1; j <= maxd; j++) { f[x][j] = f[f[x][j - 1]][j - 1]; } for (int v : g[x]) { if (v == fa) continue; d[v] = d[x] + 1; f[v][0] = x; dfs(v, x); sz[x] += sz[v]; } } int lca(int a, int b) { if (d[a] < d[b]) swap(a, b); for (int i = maxd; i >= 0; i--) { if (d[f[a][i]] >= d[b]) { a = f[a][i]; } } if (a == b) return a; for (int i = maxd; i >= 0; i--) { if (f[a][i] != f[b][i]) { a = f[a][i]; b = f[b][i]; } } return f[a][0]; } signed main() { ios::sync_with_stdio(0); cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } d[1] = 1; f[1][0] = 1; dfs(1, 1); cin >> q; while (q--) { int a, b; cin >> a >> b; if (a == b) { cout << n << endl; continue; } int lc = lca(a, b); int dab = d[a] + d[b] - 2 * d[lc]; if (dab % 2) { cout << 0 << endl; continue; } if (d[a] < d[b]) swap(a, b); int dist = dab / 2; for (int i = maxd; i >= 0; i--) { if (dist - (1 << i) > 0) { a = f[a][i]; b = f[b][i]; dist -= (1 << i); } } if (d[a] == d[b]) { cout << n - sz[a] - sz[b] << endl; continue; } cout << sz[f[a][0]] - sz[a] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 10000; const long long INFFLUJO = 1e14; const double INFCOSTO = 1e14; struct edge { int u, v; long long cap, flow; double cost; long long rem() { return cap - flow; } }; int nodes; vector<int> G[MAXN]; vector<edge> e; void addEdge(int u, int v, long long cap, double cost) { G[u].push_back(((int)e.size())); e.push_back((edge){u, v, cap, 0, cost}); G[v].push_back(((int)e.size())); e.push_back((edge){v, u, 0, 0, -cost}); } double dist[MAXN], mnCost; int pre[MAXN]; long long cap[MAXN], mxFlow; bool in_queue[MAXN]; void flow(int s, int t) { memset(in_queue, 0, sizeof(in_queue)); mxFlow = mnCost = 0; while (1) { fill(dist, dist + nodes, INFCOSTO); dist[s] = 0; memset(pre, -1, sizeof(pre)); pre[s] = 0; memset(cap, 0, sizeof(cap)); cap[s] = INFFLUJO; queue<int> q; q.push(s); in_queue[s] = 1; while (((int)q.size())) { int u = q.front(); q.pop(); in_queue[u] = 0; for (auto it : G[u]) { edge &E = e[it]; if (E.rem() && dist[E.v] > dist[u] + E.cost + 1e-9) { dist[E.v] = dist[u] + E.cost; pre[E.v] = it; cap[E.v] = min(cap[u], E.rem()); if (!in_queue[E.v]) q.push(E.v), in_queue[E.v] = 1; } } } if (pre[t] == -1) break; mxFlow += cap[t]; mnCost += cap[t] * dist[t]; for (int v = t; v != s; v = e[pre[v]].u) { e[pre[v]].flow += cap[t]; e[pre[v] ^ 1].flow -= cap[t]; } } } int x[500], y[500]; int main() { int n; scanf( %d , &n); int mx = -1100000; for (int i = 0; i < int(n); i++) { scanf( %d %d , x + i, y + i); mx = max(mx, y[i]); } int cnt = 0; for (int i = 0; i < int(n); i++) if (y[i] == mx) cnt++; if (cnt > 1) printf( -1 n ); else { nodes = 2 * n + 2; for (int i = 0; i < int(n); i++) for (int j = 0; j < int(n); j++) if (y[i] > y[j]) { addEdge(i, n + j, 1, sqrt(1ll * (x[i] - x[j]) * (x[i] - x[j]) + 1ll * (y[i] - y[j]) * (y[i] - y[j]))); } for (int i = 0; i < int(n); i++) addEdge(2 * n, i, 2, 0); for (int i = 0; i < int(n); i++) if (y[i] != mx) addEdge(n + i, 2 * n + 1, 1, 0); flow(2 * n, 2 * n + 1); if (mxFlow != n - 1) printf( -1 n ); else printf( %.10lf n , mnCost); } } |
//--------------------------------------------------------------------------------
// core.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// The core contains all "platform independent" modules and provides a
// simple interface to those components. The core makes the analyzer
// memory type and computer interface independent.
//
// This module also provides a better target for test benches as commands can
// be sent to the core easily.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
//`define HEARTBEAT
//`define SLOW_EXTCLK
module core(
clock, extReset,
extClock, extTriggerIn,
opcode, config_data, execute, indata, outputBusy,
// outputs...
sampleReady50, outputSend, stableInput,
memoryWrData, memoryRead, memoryWrite, memoryLastWrite,
extTriggerOut, extClockOut, armLEDnn,
triggerLEDnn, wrFlags, extTestMode);
parameter [31:0] MEMORY_DEPTH=6;
input clock;
input extReset; // External reset
input [7:0] opcode; // Configuration command from serial/SPI interface
input [31:0] config_data;
input execute; // opcode & config_data valid
input [31:0] indata; // Input sample data
input extClock;
input outputBusy;
input extTriggerIn;
output sampleReady50;
output outputSend;
output [31:0] stableInput;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
output extTriggerOut;
output extClockOut;
output armLEDnn;
output triggerLEDnn;
output wrFlags;
output extTestMode;
//
// Interconnect...
//
wire [31:0] syncedInput;
wire [3:0] wrtrigmask;
wire [3:0] wrtrigval;
wire [3:0] wrtrigcfg;
wire wrDivider;
wire wrsize;
wire sample_valid;
wire [31:0] sample_data;
wire dly_sample_valid;
wire [31:0] dly_sample_data;
wire aligned_data_valid;
wire [31:0] aligned_data;
wire rle_data_valid;
wire [31:0] rle_data;
wire arm_basic, arm_adv;
wire arm = arm_basic | arm_adv;
wire sampleClock;
//
// Generate external clock reference...
//
`ifdef SLOW_EXTCLK
reg [1:0] scount, next_scount;
assign extClockOut = scount[1];
initial scount=0;
always @ (posedge sampleClock)
begin
scount = next_scount;
end
always @*
begin
next_scount = scount+1'b1;
end
`else
wire extClockOut = sampleClock;
`endif
//
// Reset...
//
wire resetCmd;
wire reset = extReset | resetCmd;
reset_sync reset_sync_core (clock, reset, reset_core);
reset_sync reset_sync_sample (sampleClock, reset_core, reset_sample);
//
// Decode flags register...
//
wire [31:0] flags_reg;
wire demux_mode = flags_reg[0]; // DDR sample the input data
wire filter_mode = flags_reg[1]; // Apply half-clock glitch noise filter to input data
wire [3:0] disabledGroups = flags_reg[5:2]; // Which channel groups should -not- be captured.
wire extClock_mode = flags_reg[6]; // Use external clock for sampling.
wire falling_edge = flags_reg[7]; // Capture on falling edge of sample clock.
wire rleEnable = flags_reg[8]; // RLE compress samples
wire numberScheme = flags_reg[9]; // Swap upper/lower 16 bits
wire extTestMode = flags_reg[10] && !numberScheme; // Generate external test pattern on upper 16 bits of indata
wire intTestMode = flags_reg[11]; // Sample internal test pattern instead of indata[31:0]
wire [1:0] rle_mode = flags_reg[15:14]; // Change how RLE logic issues <value> & <counts>
//
// Sample external trigger signals...
//
wire run_basic, run_adv, run;
dly_signal extTriggerIn_reg (clock, extTriggerIn, sampled_extTriggerIn);
dly_signal extTriggerOut_reg (clock, run, extTriggerOut);
assign run = run_basic | run_adv | sampled_extTriggerIn;
//
// Logic Sniffers LEDs are connected to 3.3V so a logic 0 turns the LED on.
//
reg armLEDnn, next_armLEDnn;
reg triggerLEDnn, next_triggerLEDnn;
`ifdef HEARTBEAT
reg [31:0] hcount, next_hcount;
initial hcount=0;
always @ (posedge clock)
begin
hcount = next_hcount;
end
`endif
always @(posedge clock)
begin
armLEDnn = next_armLEDnn;
triggerLEDnn = next_triggerLEDnn;
end
always @*
begin
#1;
next_armLEDnn = armLEDnn;
next_triggerLEDnn = triggerLEDnn;
if (arm)
begin
next_armLEDnn = ~1'b1;
next_triggerLEDnn = ~1'b0;
end
else if (run)
begin
next_armLEDnn = ~1'b0;
next_triggerLEDnn = ~1'b1;
end
`ifdef HEARTBEAT
next_hcount = (~|hcount) ? 100000000 : (hcount-1'b1);
next_armLEDnn = armLEDnn;
if (~|hcount) next_armLEDnn = !armLEDnn;
`endif
end
//
// Select between internal and external sampling clock...
//
BUFGMUX BUFGMUX_intex(
.O(sampleClock), // Clock MUX output
.I0(clock), // Clock0 input
.I1(extClock), // Clock1 input
.S(extClock_mode));
//
// Decode commands & config registers...
//
decoder decoder(
.clock(clock),
.execute(execute),
.opcode(opcode),
// outputs...
.wrtrigmask(wrtrigmask),
.wrtrigval(wrtrigval),
.wrtrigcfg(wrtrigcfg),
.wrspeed(wrDivider),
.wrsize(wrsize),
.wrFlags(wrFlags),
.wrTrigSelect(wrTrigSelect),
.wrTrigChain(wrTrigChain),
.finish_now(finish_now),
.arm_basic(arm_basic),
.arm_adv(arm_adv),
.resetCmd(resetCmd));
//
// Configuration flags register...
//
flags flags(
.clock(clock),
.wrFlags(wrFlags),
.config_data(config_data),
.finish_now(finish_now),
// outputs...
.flags_reg(flags_reg));
//
// Capture input relative to sampleClock...
//
sync sync(
.clock(sampleClock),
.indata(indata),
.intTestMode(intTestMode),
.numberScheme(numberScheme),
.filter_mode(filter_mode),
.demux_mode(demux_mode),
.falling_edge(falling_edge),
// outputs...
.outdata(syncedInput));
//
// Transfer from input clock (whatever it may be) to the core clock
// (used for everything else, including RLE counts)...
//
async_fifo async_fifo(
.wrclk(sampleClock), .wrreset(reset_sample),
.rdclk(clock), .rdreset(reset_core),
.space_avail(), .wrenb(1'b1), .wrdata(syncedInput),
.read_req(1'b1), .data_avail(),
.data_valid(stableValid), .data_out(stableInput));
//
// Capture data at programmed intervals...
//
sampler sampler(
.clock(clock),
.extClock_mode(extClock_mode),
.wrDivider(wrDivider),
.config_data(config_data[23:0]),
.validIn(stableValid),
.dataIn(stableInput),
// outputs...
.validOut(sample_valid),
.dataOut(sample_data),
.ready50(sampleReady50));
//
// Evaluate standard triggers...
//
trigger trigger(
.clock(clock),
.reset(reset_core),
.validIn(sample_valid),
.dataIn(sample_data),
.wrMask(wrtrigmask),
.wrValue(wrtrigval),
.wrConfig(wrtrigcfg),
.config_data(config_data),
.arm(arm_basic),
.demux_mode(demux_mode),
// outputs...
.run(run_basic),
.capture(capture_basic));
//
// Evaluate advanced triggers...
//
trigger_adv trigger_adv(
.clock(clock),
.reset(reset_core),
.validIn(sample_valid),
.dataIn(sample_data),
.wrSelect(wrTrigSelect),
.wrChain(wrTrigChain),
.config_data(config_data),
.arm(arm_adv),
.finish_now(finish_now),
// outputs...
.run(run_adv),
.capture(capture_adv));
wire capture = capture_basic || capture_adv;
//
// Delay samples so they're in phase with trigger "capture" outputs.
//
delay_fifo delay_fifo (
.clock(clock),
.validIn(sample_valid),
.dataIn(sample_data),
// outputs
.validOut(dly_sample_valid),
.dataOut(dly_sample_data));
defparam delay_fifo.DELAY = 3; // 3 clks to match advanced trigger
//
// Align data so gaps from disabled groups removed...
//
data_align data_align (
.clock(clock),
.disabledGroups(disabledGroups),
.validIn(dly_sample_valid && capture),
.dataIn(dly_sample_data),
// outputs...
.validOut(aligned_data_valid),
.dataOut(aligned_data));
//
// Detect duplicate data & insert RLE counts (if enabled)...
// Requires client software support to decode.
//
rle_enc rle_enc (
.clock(clock),
.reset(reset_core),
.enable(rleEnable),
.arm(arm),
.rle_mode(rle_mode),
.disabledGroups(disabledGroups),
.validIn(aligned_data_valid),
.dataIn(aligned_data),
// outputs...
.validOut(rle_data_valid),
.dataOut(rle_data));
//
// Delay run (trigger) pulse to complensate for
// data_align & rle_enc delay...
//
pipeline_stall dly_arm_reg (
.clk(clock),
.reset(reset_core),
.datain(arm),
.dataout(dly_arm));
defparam dly_arm_reg.DELAY = 2;
pipeline_stall dly_run_reg (
.clk(clock),
.reset(reset_core),
.datain(run),
.dataout(dly_run));
defparam dly_run_reg.DELAY = 1;
//
// The brain's... mmm... brains...
//
controller controller(
.clock(clock),
.reset(reset_core),
.run(dly_run),
.wrSize(wrsize),
.config_data(config_data),
.validIn(rle_data_valid),
.dataIn(rle_data),
.arm(dly_arm),
.busy(outputBusy),
// outputs...
.send(outputSend),
.memoryWrData(memoryWrData),
.memoryRead(memoryRead),
.memoryWrite(memoryWrite),
.memoryLastWrite(memoryLastWrite));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long vis[80]; long long prime[80] = {0}; long long a[200000]; long long fc[80][200000] = {{0}}; int n; int pnum; int get_primes(int m) { memset(vis, 0, sizeof(vis)); int cnt = 1; for (int i = 2; i < m; i++) { if (!vis[i]) { prime[cnt++] = i; for (int j = i * i; j < m; j += i) vis[j] = 1; } } return cnt; } void change(long long k, long long g) { for (int i = 1; i <= pnum;) { if (k % prime[i] == 0) { fc[i][g] ^= 1; k /= prime[i]; } else i++; } return; } long long gauss() { long long g = 0; int i, j; for (j = 1; j <= n && g < pnum; j++) { for (i = g + 1; i <= pnum; i++) if (fc[i][j] == 1) break; if (i <= pnum) { g++; for (int p = j; p <= n; p++) swap(fc[g][p], fc[i][p]); for (int p = g + 1; p <= pnum; p++) { if (fc[p][j] == 1) { for (int q = j; q <= n; q++) fc[p][q] ^= fc[g][q]; } } } } return g; } long long qpow(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) { ans = (ans * a) % m; b--; } b /= 2; a = a * a % m; } return ans; } int main() { int cas = 1; int t = 1; get_primes(70); pnum = 19; { memset(fc, 0, sizeof(fc)); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], change(a[i], i); int r = gauss(); long long ans = qpow(2, (long long)(n - r), 1000000007) - 1; printf( %lld n , ans); } } |
// Driver for an LCD TFT display. Specifically, this was written to drive
// the AdaFruit YX700WV03, which is an 800x480 7" display. It's driven
// like a VGA monitor, but with digital color values, separate horizontal and
// vertical sync signals, a data enable signal, a clock, and with different
// timings.
module LCD_control(
// Host Side
input [7:0] iRed,
input [7:0] iGreen,
input [7:0] iBlue,
output [9:0] oCurrent_X, // Max horizontal pixels: 1023.
output [9:0] oCurrent_Y, // Max vertical pixels: 1023.
output [21:0] oAddress, // [0..(w*h))
output oRequest, // Whether we need a pixel right now.
output reg oTopOfScreen, // 1 when at the very top of screen.
// LCD Side
output [7:0] oLCD_R,
output [7:0] oLCD_G,
output [7:0] oLCD_B,
output reg oLCD_HS, // Active low.
output reg oLCD_VS, // Active low.
output oLCD_DE, // Active high.
// Control Signal
input iCLK,
input iRST_N
);
// LK: There are two internal registers, H_Cont and V_Cont. They are 0-based. The
// H_Cont value has these ranges:
//
// H_Cont oLCD_HS
// [0, H_FRONT) 1 (front porch)
// [H_FRONT, H_FRONT + H_SYNC) 0 (sync pulse)
// [H_FRONT + H_SYNC, H_BLANK) 1 (back porch, V_Cont is incremented)
// [H_BLANK, H_TOTAL) 1 (pixels are visible)
//
// V_Cont value has these ranges:
//
// V_Cont oLCD_VS
// [0, V_FRONT) 1 (front porch)
// [V_FRONT, V_FRONT + V_SYNC) 0 (sync pulse)
// [V_FRONT + V_SYNC, V_BLANK) 1 (back porch)
// [V_BLANK, V_TOTAL) 1 (pixels are visible)
//
// Note that V_Cont is incremented on the positive edge of oLCD_HS, which means
// that its values are offset from the normal 0-799 range of H_Cont.
//
// oTopOfScreen is the first pixel of the second row, since that's where
// both are zero.
//
// The LCD clock is 25.175 MHz. With 992x500 pixels (800x480 visible),
// that's about 50 FPS.
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 24;
parameter H_SYNC = 72;
parameter H_BACK = 96;
parameter H_ACT = 800;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 3;
parameter V_SYNC = 10;
parameter V_BACK = 7;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
assign oLCD_R = oRequest ? iRed : 8'b0 ;
assign oLCD_G = oRequest ? iGreen : 8'b0 ;
assign oLCD_B = oRequest ? iBlue : 8'b0 ;
assign oAddress = oCurrent_Y*H_ACT + oCurrent_X;
assign oRequest = H_Cont >= H_BLANK && V_Cont >= V_BLANK;
assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0;
assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0;
assign oLCD_DE = oRequest;
// Latch the top-of-screen register. That means that it's one clock late,
// but that's okay since it's nowhere near the visible portion of the screen.
wire oTopOfScreenNext = H_Cont == 0 && V_Cont == 0;
always @(posedge iCLK)
begin
oTopOfScreen <= oTopOfScreenNext;
end
// Horizontal Generator: Refers to the pixel clock.
always @(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N) begin
H_Cont <= 0;
oLCD_HS <= 1;
end else begin
// Advance pixel.
if (H_Cont < H_TOTAL - 1) begin
H_Cont <= H_Cont + 1'b1;
end else begin
H_Cont <= 0;
end
// Horizontal Sync
if (H_Cont == H_FRONT - 1) begin
// Front porch end
oLCD_HS <= 1'b0;
end
if (H_Cont == H_FRONT + H_SYNC - 1) begin
// Sync pulse end
oLCD_HS <= 1'b1;
end
end
end
// Vertical Generator: Refers to the horizontal sync.
always @(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N) begin
V_Cont <= 0;
oLCD_VS <= 1;
end else if (H_Cont == 0) begin
// Advance line.
if (V_Cont < V_TOTAL-1) begin
V_Cont <= V_Cont+1'b1;
end else begin
V_Cont <= 0;
end
// Vertical Sync
if (V_Cont == V_FRONT - 1) begin
// Front porch end
oLCD_VS <= 1'b0;
end
if (V_Cont == V_FRONT + V_SYNC - 1) begin
// Sync pulse end
oLCD_VS <= 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long Pow(int a, int b) { long long ans = 1; for (int i = 0; i < b; i++) { ans = (ans * a) % 1000000007; } return ans; } int main() { long long n, k; cin >> n >> k; cout << (Pow(n - k, n - k) * Pow(k, k - 1)) % 1000000007 << endl; return 0; } |
//----------------------------------------------------------------------
// Title : Gigabit Media Independent Interface (GMII) Physical I/F
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : gmii_if.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This module creates a Gigabit Media Independent
// Interface (GMII) by instantiating Input/Output buffers
// and Input/Output flip-flops as required.
//
// This interface is used to connect the Ethernet MAC to
// an external 1000Mb/s (or Tri-speed) Ethernet PHY.
//----------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gmii_if (
RESET,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
// MAC Interface
TXD_FROM_MAC,
TX_EN_FROM_MAC,
TX_ER_FROM_MAC,
TX_CLK,
RXD_TO_MAC,
RX_DV_TO_MAC,
RX_ER_TO_MAC,
RX_CLK
);
input RESET;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input [7:0] TXD_FROM_MAC;
input TX_EN_FROM_MAC;
input TX_ER_FROM_MAC;
input TX_CLK;
output [7:0] RXD_TO_MAC;
output RX_DV_TO_MAC;
output RX_ER_TO_MAC;
input RX_CLK;
reg [7:0] RXD_TO_MAC;
reg RX_DV_TO_MAC;
reg RX_ER_TO_MAC;
reg [7:0] GMII_TXD;
reg GMII_TX_EN;
reg GMII_TX_ER;
wire [7:0] GMII_RXD_DLY;
wire GMII_RX_DV_DLY;
wire GMII_RX_ER_DLY;
//------------------------------------------------------------------------
// GMII Transmitter Clock Management
//------------------------------------------------------------------------
// Instantiate a DDR output register. This is a good way to drive
// GMII_TX_CLK since the clock-to-pad delay will be the same as that for
// data driven from IOB Ouput flip-flops, eg. GMII_TXD[7:0].
ODDR gmii_tx_clk_oddr (
.Q (GMII_TX_CLK),
.C (TX_CLK),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (RESET),
.S (1'b0)
);
//------------------------------------------------------------------------
// GMII Transmitter Logic : Drive TX signals through IOBs onto the
// GMII interface
//------------------------------------------------------------------------
// Infer IOB Output flip-flops
always @(posedge TX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
GMII_TX_EN <= 1'b0;
GMII_TX_ER <= 1'b0;
GMII_TXD <= 8'h00;
end
else
begin
GMII_TX_EN <= TX_EN_FROM_MAC;
GMII_TX_ER <= TX_ER_FROM_MAC;
GMII_TXD <= TXD_FROM_MAC;
end
end
//------------------------------------------------------------------------
// Route GMII inputs through IODELAY blocks, using IDELAY function
//------------------------------------------------------------------------
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld0 (
.IDATAIN(GMII_RXD[0]),
.DATAOUT(GMII_RXD_DLY[0]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld1 (
.IDATAIN(GMII_RXD[1]),
.DATAOUT(GMII_RXD_DLY[1]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld2 (
.IDATAIN(GMII_RXD[2]),
.DATAOUT(GMII_RXD_DLY[2]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld3 (
.IDATAIN(GMII_RXD[3]),
.DATAOUT(GMII_RXD_DLY[3]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld4 (
.IDATAIN(GMII_RXD[4]),
.DATAOUT(GMII_RXD_DLY[4]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld5 (
.IDATAIN(GMII_RXD[5]),
.DATAOUT(GMII_RXD_DLY[5]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld6 (
.IDATAIN(GMII_RXD[6]),
.DATAOUT(GMII_RXD_DLY[6]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld7 (
.IDATAIN(GMII_RXD[7]),
.DATAOUT(GMII_RXD_DLY[7]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideldv(
.IDATAIN(GMII_RX_DV),
.DATAOUT(GMII_RX_DV_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideler(
.IDATAIN(GMII_RX_ER),
.DATAOUT(GMII_RX_ER_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
//------------------------------------------------------------------------
// GMII Receiver Logic : Receive RX signals through IOBs from the
// GMII interface
//------------------------------------------------------------------------
// Infer IOB Input flip-flops
always @(posedge RX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
RX_DV_TO_MAC <= 1'b0;
RX_ER_TO_MAC <= 1'b0;
RXD_TO_MAC <= 8'h00;
end
else
begin
RX_DV_TO_MAC <= GMII_RX_DV_DLY;
RX_ER_TO_MAC <= GMII_RX_ER_DLY;
RXD_TO_MAC <= GMII_RXD_DLY;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int get_index(int i, int j, int k) { return i * 4 + j * 2 + k; } int diff(int i, int j) { return i != j; } pair<int, string> input() { int n; cin >> n; string s; cin >> s; return make_pair(n, s); } int work2(int n, string s) { int first_diff = 1; for (; first_diff < n; first_diff++) { if (s[first_diff - 1] != s[first_diff]) break; } if (first_diff == n) return (n + 2) / 3; s = s.substr(first_diff, n - first_diff) + s.substr(0, first_diff); int start = 0; int ans = 0; for (int i = 1; i < n; i++) { if (s[i] != s[i - 1]) { ans += (i - start) / 3; start = i; } } ans += (n - start) / 3; return ans; } void work() { pair<int, string> in = input(); int n = in.first; string s = in.second; cout << work2(n, s) << endl; } int main() { int t; cin >> t; while (t--) { work(); } return 0; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_ocmc(
rstn,
sw_clk,
/* Goes to port 0 of OCM */
ocm_wr_ack_port0,
ocm_wr_dv_port0,
ocm_rd_req_port0,
ocm_rd_dv_port0,
ocm_wr_addr_port0,
ocm_wr_data_port0,
ocm_wr_bytes_port0,
ocm_rd_addr_port0,
ocm_rd_data_port0,
ocm_rd_bytes_port0,
ocm_wr_qos_port0,
ocm_rd_qos_port0,
/* Goes to port 1 of OCM */
ocm_wr_ack_port1,
ocm_wr_dv_port1,
ocm_rd_req_port1,
ocm_rd_dv_port1,
ocm_wr_addr_port1,
ocm_wr_data_port1,
ocm_wr_bytes_port1,
ocm_rd_addr_port1,
ocm_rd_data_port1,
ocm_rd_bytes_port1,
ocm_wr_qos_port1,
ocm_rd_qos_port1
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ocm_wr_ack_port0;
input ocm_wr_dv_port0;
input ocm_rd_req_port0;
output ocm_rd_dv_port0;
input[addr_width-1:0] ocm_wr_addr_port0;
input[max_burst_bits-1:0] ocm_wr_data_port0;
input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
input[addr_width-1:0] ocm_rd_addr_port0;
output[max_burst_bits-1:0] ocm_rd_data_port0;
input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
input [axi_qos_width-1:0] ocm_wr_qos_port0;
input [axi_qos_width-1:0] ocm_rd_qos_port0;
output ocm_wr_ack_port1;
input ocm_wr_dv_port1;
input ocm_rd_req_port1;
output ocm_rd_dv_port1;
input[addr_width-1:0] ocm_wr_addr_port1;
input[max_burst_bits-1:0] ocm_wr_data_port1;
input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bits-1:0] ocm_rd_data_port1;
input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
input[axi_qos_width-1:0] ocm_wr_qos_port1;
input[axi_qos_width-1:0] ocm_rd_qos_port1;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr ocm_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_port0),
.qos2(ocm_wr_qos_port1),
.prt_dv1(ocm_wr_dv_port0),
.prt_dv2(ocm_wr_dv_port1),
.prt_data1(ocm_wr_data_port0),
.prt_data2(ocm_wr_data_port1),
.prt_addr1(ocm_wr_addr_port0),
.prt_addr2(ocm_wr_addr_port1),
.prt_bytes1(ocm_wr_bytes_port0),
.prt_bytes2(ocm_wr_bytes_port1),
.prt_ack1(ocm_wr_ack_port0),
.prt_ack2(ocm_wr_ack_port1),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ocm_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_port0),
.qos2(ocm_rd_qos_port1),
.prt_req1(ocm_rd_req_port0),
.prt_req2(ocm_rd_req_port1),
.prt_data1(ocm_rd_data_port0),
.prt_data2(ocm_rd_data_port1),
.prt_addr1(ocm_rd_addr_port0),
.prt_addr2(ocm_rd_addr_port1),
.prt_bytes1(ocm_rd_bytes_port0),
.prt_bytes2(ocm_rd_bytes_port1),
.prt_dv1(ocm_rd_dv_port0),
.prt_dv2(ocm_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_ocm_mem ocm();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ocm.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ocm.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
#include <bits/stdc++.h> int grid[1001][1001]; int start[100000]; int main(void) { int n, m, k; scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &grid[i][j]); } } for (int i = 0; i < k; i++) { scanf( %d , &start[i]); } for (int i = 0; i < k; i++) { int r = 1; int c = start[i]; while (r <= n) { int rr, cc; switch (grid[r][c]) { case 1: rr = r; cc = c + 1; break; case 2: rr = r + 1; cc = c; break; case 3: rr = r; cc = c - 1; break; } grid[r][c] = 2; r = rr; c = cc; } printf( %d , c); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> int a[5000], b[5000], n, m, i, j, k = 0; int main() { scanf( %d%d , &n, &m); for (i = 0; i < n; i++) { scanf( %d , &a[i]); b[i] = a[i]; } for (i = 0; i < n; i++) if (a[i] == b[i]) for (j = 0; j < n; j++) if (a[j] != b[i] && a[i] != b[j]) { int z = b[i]; b[i] = b[j]; b[j] = z; break; } for (i = 0; i < n; i++) if (a[i] != b[i]) ++k; printf( %d n , k); for (i = 0; i < n; i++) printf( %d %d n , a[i], b[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, l, r; inline long long query(long long l, long long r) { for (long long i = 62; i >= 1; i--) { if ((1ll << i) - 1 >= l && (1ll << i) - 1 <= r) return (1ll << i) - 1; } for (long long i = 62; i >= 0; i--) if (((1ll << i) & l) > 0 && ((1ll << i) & r) > 0) return (1ll << i) + query(l - (1ll << i), r - (1ll << i)); } int main() { scanf( %lld , &n); while (n--) { scanf( %lld%lld , &l, &r); if (l > r) { long long t = l; l = r; r = t; } if (l == r) { printf( %lld n , l); continue; } printf( %lld n , query(l, r)); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_2_V
`define SKY130_FD_SC_HDLL__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_2_V
|
#include <bits/stdc++.h> using namespace std; map<int, int> mm; map<int, int>::iterator it; int x[100005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> v; for (int i = 1; i <= n; i++) cin >> x[i]; for (int i = n; i >= 1; i--) { if (mm[x[i]] == 0) { mm[x[i]]++; v.push_back(x[i]); } } cout << endl; cout << v.size() << n ; for (int i = v.size() - 1; i >= 0; i--) { cout << v[i] << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { char ar[100]; int len, count = 0, i, j; gets(ar); len = strlen(ar); if (isupper(ar[0]) && islower(ar[1])) { cout << ar; } else { for (i = 0; ar[i] != 0 ; i++) { if (isupper(ar[i])) { count++; } } if (len == 1) { if (islower(ar[0])) { ar[0] = toupper(ar[0]); } else if (isupper(ar[0])) { ar[0] = tolower(ar[0]); } } else if (count == len) { for (i = 0; ar[i] != 0 ; i++) { ar[i] = tolower(ar[i]); } } else if (count == len - 1) { if (islower(ar[0])) { for (i = 1; ar[i] != 0 ; i++) { ar[i] = tolower(ar[i]); ar[0] = toupper(ar[0]); } } } cout << ar; } return 0; } |
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