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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); ; string s; int flag = 0; cin >> s; string at = at , dot = dot ; for (int i = 1; i < s.size() - 3; i++) { if (s.substr(i, 2) == at && flag == 0) { s.replace(i, 2, @ ); flag = 1; } if (s.substr(i, 3) == dot) { s.replace(i, 3, . ); } } int j = s.size() - 3; if (s.substr(j, 2) == at && flag == 0) s.replace(j, 2, @ ); cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MAX_N = 200002; int n; int a[MAX_N], t[MAX_N]; void solve() { vector<pair<int, int>> v; for (int i = 0; i < n; ++i) v.emplace_back(a[i], t[i]); sort(v.begin(), v.end()); ll cur = -1; int idx = 0; multiset<ll> eq; ll ans = 0, sum = 0; while (idx < n || !eq.empty()) { if (eq.empty()) cur = v[idx].first; while (idx < n && v[idx].first == cur) { sum += v[idx].second; eq.insert(-v[idx].second); idx++; } sum += *eq.begin(); eq.erase(eq.begin()); ans += sum; cur++; } cout << ans << n ; } int main() { cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> t[i]; solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long isPrime(long long x) { long long i, flag = 1; if (x == 0 || x == 1) { flag = 0; } for (i = 2; i <= sqrt(x); i++) { if (x % i == 0) { flag = 0; break; } } return flag; } long long fact(long long n) { long long ans = 1; for (long long i = 2; i <= n; i++) { ans *= i; } return ans; } const long long INF = 1e18; const long long N = 2 * 1e5; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); { long long n; cin >> n; if (n == 0) { cout << 1 << n ; return 0; } if (n % 4 == 1) { cout << 8 << n ; } else if (n % 4 == 2) { cout << 4 << n ; } else if (n % 4 == 3) { cout << 2 << n ; } else if (n % 4 == 0) { cout << 6 << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, c = 0, f = 0; cin >> n >> k; int y[n]; for (int i = 0; i < n; i++) cin >> y[i]; if (k == 5) { for (int i = 0; i < n; i++) { if (y[i] == 0) c++; } if (c >= 3) { if (c == 6) f = 2; else f = (int)(c / 3); } } else if (k == 4) { for (int i = 0; i < n; i++) { if (y[i] == 0 || y[i] == 1) c++; } if (c == 6) f = 2; else f = (int)(c / 3); } else if (k == 3) { for (int i = 0; i < n; i++) { if (y[i] == 0 || y[i] == 1 || y[i] == 2) c++; } if (c == 6) f = 2; else f = (int)(c / 3); } else if (k == 2) { for (int i = 0; i < n; i++) { if (y[i] == 0 || y[i] == 1 || y[i] == 2 || y[i] == 3) c++; } if (c == 6) f = 2; else f = (int)(c / 3); } else if (k == 1) { for (int i = 0; i < n; i++) { if (y[i] == 4 || y[i] == 0 || y[i] == 1 || y[i] == 2 || y[i] == 3) c++; } if (c == 6) f = 2; else f = (int)(c / 3); } cout << f; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void read(long long &x) { x = 0; long long f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -f; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; x *= f; } void print(long long x) { if (x < 0) putchar( - ), x = -x; if (!x) return; print(x / 10), putchar(x % 10 + 48); } void write(long long x) { if (!x) putchar( 0 ); else print(x); putchar( n ); } const long long maxn = 2e5 + 10; const long long inf = 1e9; const long double eps = 1e-12; const long long mod = 1e9 + 7; long long add(long long x, long long y) { return x + y >= mod ? x + y - mod : x + y; } long long del(long long x, long long y) { return x - y < 0 ? x - y + mod : x - y; } long long mul(long long x, long long y) { return 1ll * x * y - 1ll * x * y / mod * mod; } void inc(long long &x, long long y) { x += y; x %= mod; } long long n, k, a[maxn], res, c; long long qpow(long long a, long long x) { long long res = 1; for (; x; x >>= 1, a = 1ll * a * a % mod) if (x & 1) res = 1ll * res * a % mod; return res; } struct Matrix { long long a, b, r[110][110]; Matrix() { a = b = 0, memset(r, 0, sizeof r); } Matrix operator*(const Matrix &t) const { Matrix res; res.a = a, res.b = t.b; for (long long i = 0; i <= a; i++) for (long long j = 0; j <= t.b; j++) for (long long k = 0; k <= b; k++) res.r[i][j] = add(res.r[i][j], mul(r[i][k], t.r[k][j])); return res; } } tr, ans; signed main() { read(n), read(k); for (long long i = 1; i <= n; i++) read(a[i]), res += !(a[i] & 1); for (long long i = 1; i <= res; i++) c += !a[i]; ans.a = 0, ans.b = res; ans.r[0][c] = 1; tr.a = tr.b = res; for (long long i = 0; i <= res; i++) { long long lw = i, lb = res - i, rw = res - lw, rb = n - res - lb; if (i != res) inc(tr.r[i][i + 1], lb * rw % mod); if (i != 0) inc(tr.r[i][i - 1], lw * rb % mod); inc(tr.r[i][i], (res * (res - 1) + (n - res) * (n - res - 1)) % mod * qpow(2, mod - 2) % mod); inc(tr.r[i][i], (lw * lb + rw * rb) % mod); } long long x = k, f = 0; for (; x; x >>= 1, tr = tr * tr) if (x & 1) ans = ans * tr; for (long long i = 0, i_r = res; i <= i_r; i++) f = (f + ans.r[0][i]) % mod; write(ans.r[0][res] * qpow(f, mod - 2) % mod); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, k; cin >> n >> k; vector<long long int> a(n); for (long long int i = 0; i < a.size(); i++) cin >> a[i]; long long int ans(0); for (long long int i = 0; i < n; i++) { long long int t; cin >> t; if (t) ans += a[i], a[i] = 0; } long long int s(0); long long int tot(0); for (long long int i = 0; i < k; i++) { s = s + a[i]; } tot = s; for (long long int i = k; i < n; i++) { s += (a[i] - a[i - k]); tot = max(tot, s); } cout << ans + tot << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long double PI = 4 * atan((long double)1); const long long int INF = 1e18; const long long int NINF = -1e18; long long int get_hash(string s) { long long int N = 1000001; long long int base[N], A = 11, MD = 1110111110111; base[0] = 1; for (long long int i = (1); i < (N); ++i) base[i] = (base[i - 1] * A) % MD; long long int hs = 0; for (long long int i = (0); i < (s.size()); ++i) { hs += (s[i] * base[i]); hs %= MD; } return hs; } long long power(long long a, long long n) { long long res = 1; while (n) { if (n % 2) res *= a; a *= a; n /= 2; } return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, m; cin >> n >> m; map<int, int> mpc; long long int a[n], b[m]; for (long long int i = (0); i < (n); ++i) cin >> a[i]; int arr[n]; map<int, int> mpa, mpb; int k = 0; for (long long int i = (0); i < (m); ++i) { cin >> b[i]; if (mpa[b[i]] != 1) { arr[k] = b[i]; k++; mpa[b[i]] = 1; } } if (k != n) { for (long long int i = (1); i < (n + 1); ++i) { if (mpa[i] != 1) { mpa[i] = 1; arr[k] = i; k++; } } } stack<int> st, st1; for (int i = n - 1; i >= 0; i--) st.push(arr[i]); long long int ans = 0; for (long long int i = (0); i < (m); ++i) { int x = b[i]; while (st.top() != x) { st1.push(st.top()); ans += a[st.top() - 1]; st.pop(); } st.pop(); while (!st1.empty()) { st.push(st1.top()); st1.pop(); } st.push(x); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n, count = 1, ans = 0, a, b, freq[N] = {0}, pf, v; cin >> n; for (int i = 0; i < n; i++) { cin >> a; v = 0; for (int j = 0; j < a; j++) { cin >> b; if (j < count && !v) { if (!freq[b]) { v = 1; freq[b]++; } } } if (!v) { pf = i + 1; } count++; } v = 0; for (int i = 1; i <= n; i++) { if (!freq[i]) { v = i; break; } } if (v) { cout << IMPROVE n << pf << << v << n ; } else { cout << OPTIMAL n ; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_0_V
`define SKY130_FD_SC_LP__OR4_0_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_0 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_0 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_0_V
|
//wishbone_arbiter.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module ${ARBITER_NAME} (
//control signals
input clk,
input rst,
//wishbone master ports
${PORTS}
//wishbone slave signals
output o_s_we,
output o_s_stb,
output o_s_cyc,
output [3:0] o_s_sel,
output [31:0] o_s_adr,
output [31:0] o_s_dat,
input [31:0] i_s_dat,
input i_s_ack,
input i_s_int
);
localparam MASTER_COUNT = ${NUM_MASTERS};
//registers/wires
//this should be parameterized
reg [7:0] master_select;
reg [7:0] priority_select;
wire o_master_we [MASTER_COUNT - 1:0];
wire o_master_stb [MASTER_COUNT - 1:0];
wire o_master_cyc [MASTER_COUNT - 1:0];
wire [3:0] o_master_sel [MASTER_COUNT - 1:0];
wire [31:0] o_master_adr [MASTER_COUNT - 1:0];
wire [31:0] o_master_dat [MASTER_COUNT - 1:0];
${MASTER_SELECT}
//priority select
${PRIORITY_SELECT}
//slave assignments
assign o_s_we = (master_select != MASTER_NO_SEL) ? o_master_we[master_select] : 0;
assign o_s_stb = (master_select != MASTER_NO_SEL) ? o_master_stb[master_select] : 0;
assign o_s_cyc = (master_select != MASTER_NO_SEL) ? o_master_cyc[master_select] : 0;
assign o_s_sel = (master_select != MASTER_NO_SEL) ? o_master_sel[master_select] : 0;
assign o_s_adr = (master_select != MASTER_NO_SEL) ? o_master_adr[master_select] : 0;
assign o_s_dat = (master_select != MASTER_NO_SEL) ? o_master_dat[master_select] : 0;
${WRITE}
${STROBE}
${CYCLE}
${SELECT}
${ADDRESS}
${DATA}
${ASSIGN}
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX_A = 1e7; const int N = 500000; bool sieve[MX_A + 1]; pair<int, int> pr[MX_A + 1]; int a1[N], a2[N], arr[N]; void handleven(int i) { int num = arr[i]; while (num % 2 == 0) num /= 2; if (num != 1) { a1[i] = 2; a2[i] = num; } else { a1[i] = a2[i] = -1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); for (int i = 2; i <= MX_A; i++) { if (sieve[i]) continue; for (int j = i; j <= MX_A; j += i) { if (!pr[j].second) { if (!pr[j].first) { pr[j].first = i; } else { pr[j].second = i; } } sieve[j] = true; } } int n; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i < n; i++) { int num = arr[i]; if (arr[i] % 2 == 0) { while (num % 2 == 0) num /= 2; if (num != 1) { a1[i] = 2; a2[i] = num; } else { a1[i] = a2[i] = -1; } } else if (pr[arr[i]].second) { a1[i] = pr[arr[i]].first; a2[i] = pr[arr[i]].second; } else { a1[i] = a2[i] = -1; } } for (int i = 0; i < n; i++) { cout << a1[i] << ; } cout << n ; for (int i = 0; i < n; i++) { cout << a2[i] << ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] out1;
wire [31:0] out2;
sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'he396068aba3898a2) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in1, in2
);
input [15:0] in1;
input [15:0] in2;
output reg signed [31:0] out1;
output reg unsigned [31:0] out2;
always @* begin
// verilator lint_off WIDTH
out1 = $signed(in1) * $signed(in2);
out2 = $unsigned(in1) * $unsigned(in2);
// verilator lint_on WIDTH
end
endmodule
|
module linked_list_fifo(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full, count, almost_full, free_count, empty_check_fifo, empty_check2);
parameter WIDTH = 8;
parameter DEPTH = 32;
parameter FIFOS = 8;
parameter GEN_COUNTERS = 1;
parameter GEN_EMPTY_CHECK = 1;
parameter GEN_OVERFLOW_PROTECTION = 1;
parameter GEN_UNDERFLOW_PROTECTION = 1;
parameter LOG2_FIFOS = log2(FIFOS-1);
parameter LOG2_DEPTH = log2(DEPTH-1);
parameter FIFO_COUNT = FIFOS;
input rst;
input clk;
input push;
input [LOG2_FIFOS-1:0] push_fifo;
input pop;
input [LOG2_FIFOS-1:0] pop_fifo;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output empty;
output full;
//output [(LOG2_DEPTH+1)*(2**FIFOS)-1:0] count;
output [(LOG2_DEPTH)*(FIFOS)-1:0] count;
output reg almost_full;
output reg [LOG2_DEPTH:0] free_count;
input [LOG2_FIFOS - 1:0] empty_check_fifo;
output empty_check2;
wire pop_internal;
wire push_internal;
generate if(GEN_UNDERFLOW_PROTECTION) begin: gen_underflow_protection
assign pop_internal = pop && !empty;
end else begin
assign pop_internal = pop;
end endgenerate
generate if(GEN_OVERFLOW_PROTECTION) begin: gen_overflow_protection
assign push_internal = push && !full;
end else begin
assign push_internal = push;
end endgenerate
reg [LOG2_DEPTH - 1:0] count_internal [0:FIFOS - 1];
genvar g;
integer i;
generate if(GEN_COUNTERS) begin: assign_count0
for(g = 0; g < FIFOS; g = g + 1) begin: assign_count
assign count[(g+1)*LOG2_DEPTH - 1 -:LOG2_DEPTH] = count_internal[g];
end
initial for(i = 0; i < FIFOS; i = i + 1)
count_internal[i] = 0;
always @(posedge clk) begin
if(pop_internal && push_internal && push_fifo == pop_fifo) begin
end else begin
if(pop_internal)
count_internal[pop_fifo] = count_internal[pop_fifo] - 1;
if(push_internal)
count_internal[push_fifo] = count_internal[push_fifo] + 1;
end
end
end else begin
assign count = 0;
end endgenerate
reg [WIDTH-1:0] ram [DEPTH - 1:0];
reg [LOG2_DEPTH:0] linked_ram [DEPTH - 1:0];
reg ram_we;
reg [LOG2_DEPTH-1:0] ram_addr_a, ram_addr_b;
reg [WIDTH-1:0] ram_d, ram_q;
reg [LOG2_DEPTH:0] linked_ram_d;
reg [WIDTH-1:0] r_q;
reg [LOG2_DEPTH-1:0] r_beg [FIFOS-1:0];
reg [LOG2_DEPTH-1:0] r_end [FIFOS-1:0];
reg [LOG2_DEPTH-1:0] beg_next, end_next;
reg c_empty;
reg [LOG2_FIFOS-1:0] beg_ptr, end_ptr;
reg [LOG2_DEPTH:0] free, next_free;
reg beg_we, end_we;
initial for(i = 0; i < DEPTH; i = i + 1) begin
linked_ram[i] = i + 1;
end
initial for(i = 0; i < FIFOS; i = i + 1) begin
r_beg[i] = i;
r_end[i] = i;
end
initial free = FIFOS;
initial free_count = DEPTH - FIFOS;
always @(posedge clk) begin
if(pop_internal & push_internal) begin
end else if(pop_internal) begin
free_count <= free_count + 1;
end else if(push_internal) begin
free_count <= free_count - 1;
end
end
always @*
if(free_count < 2)
almost_full = 1;
else
almost_full = 0;
always @(posedge clk) begin
if(ram_we) begin
ram[ram_addr_a] <= ram_d;
end
ram_q <= ram[ram_addr_b];
end
assign q = ram_q;
always @*
ram_d = d;
always @(posedge clk) begin
if(ram_we) begin
linked_ram[ram_addr_a] <= linked_ram_d;
end
end
wire [LOG2_DEPTH:0] linked_ram_q = linked_ram[ram_addr_b];
always @(posedge clk) begin
if(beg_we)
r_beg[beg_ptr] <= beg_next;
if(end_we)
r_end[end_ptr] <= end_next;
end
wire [LOG2_DEPTH-1:0] beg_curr = r_beg[beg_ptr];
wire [LOG2_DEPTH-1:0] end_curr = r_end[end_ptr];
wire [LOG2_DEPTH-1:0] empty_check = r_end[beg_ptr];
always @* begin
if(empty_check == beg_curr)
c_empty = 1;
else
c_empty = 0;
end
assign empty = c_empty;
always @(posedge clk) begin
free <= next_free;
end
generate if(GEN_EMPTY_CHECK) begin: gen_empty_check
wire [LOG2_DEPTH-1:0] empty_check_2_beg = r_beg[empty_check_fifo];
wire [LOG2_DEPTH-1:0] empty_check_2_end = r_end[empty_check_fifo];
assign empty_check2 = empty_check_2_beg == empty_check_2_end;
end endgenerate
always @* begin
ram_we = 0;
beg_next = 0;
beg_we = 0;
end_we = 0;
end_next = 0;
beg_ptr = pop_fifo;
end_ptr = push_fifo;
next_free = free;
ram_addr_a = end_curr;
ram_addr_b = beg_curr;
linked_ram_d = 0;
if(push_internal && pop_internal) begin
ram_we = 1;
beg_we = 1;
end_we = 1;
ram_addr_a = end_curr;
linked_ram_d = beg_curr;
end_ptr = push_fifo;
beg_ptr = pop_fifo;
end_next = beg_curr;
beg_next = linked_ram_q;
ram_addr_b = beg_curr;
end else if(push_internal) begin
ram_we = 1;
end_we = 1;
ram_addr_a = end_curr;
linked_ram_d = free;
end_ptr = push_fifo;
end_next = free;
ram_addr_b = free;
next_free = linked_ram_q;
end else if(pop_internal) begin
beg_we = 1;
beg_next = linked_ram_q;
ram_addr_b = beg_curr;
ram_addr_a = beg_curr;
next_free = beg_curr;
ram_we = 1;
linked_ram_d = free;
end
end
integer error;
initial error = 0;
assign full = free[LOG2_DEPTH];
`include "log2.vh"
always @(posedge clk) begin
if(push && full) begin
$display("ERROR: Overflow at %m");
//$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 5; int n; long long int a[MAX], BIT[MAX]; void update(int idx, long long int val) { for (; idx <= n; idx += (idx & (-idx))) { BIT[idx] += val; } } long long int sum(int idx) { idx--; long long int sumi = 0; for (; idx > 0; idx -= (idx & (-idx))) { sumi += BIT[idx]; } return sumi; } int main() { scanf( %d , &n); int l[n], r[n]; map<long long int, int> make_pair; for (int i = 0; i < n; i++) { scanf( %I64d , &a[i]); make_pair[a[i]]++; l[i] = make_pair[a[i]]; } make_pair.clear(); for (int i = n - 1; i >= 0; i--) { make_pair[a[i]]++; r[i] = make_pair[a[i]]; } long long int ans = 0; for (int i = n - 1; i >= 0; i--) { ans += sum(l[i]); update(r[i], 1); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; a[0] = 1; a[1] = 5; a[2] = 13; a[3] = 25; for (int i = 4; i < n; i++) { a[i] = a[i - 1] + 4 * (i); } cout << a[n - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; struct particle { int x, v; } particles[500002]; bool possible(long double time) { long double maxRightyX = -1e19; for (int i = 1; i <= n; i++) { if (particles[i].v > 0) { maxRightyX = max(particles[i].x + particles[i].v * time, maxRightyX); } else if (maxRightyX >= particles[i].x + particles[i].v * time) { return true; } } return false; } void bin() { long double l = 0, r = 1000000000; while (l + 0.0000000001 < r) { long double mid = (l + r) / 2; if (possible(mid)) r = mid; else l = mid + 0.0000000001; } cout << fixed << setprecision(10); if (possible(l)) { cout << l; } else if (possible(r)) { cout << r; } else { cout << -1 ; } cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> particles[i].x >> particles[i].v; bin(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long md = 1e9 + 7; int t; int dp[52][1005][1005]; int dp2[52][1005]; int c[1501][60]; long long f[100]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> t; dp[0][0][1] = 1; f[0] = 1; for (long long i = 1; i <= 50; ++i) f[i] = (f[i - 1] * i) % md; for (int i = 0; i <= 50; ++i) { for (int j = 0; j <= 1001; ++j) { long long sum = 0; for (int k = 0; k <= 1001; ++k) { sum = sum + dp[i][j][k]; if (sum > md) sum -= md; if (j + k <= 1000) { dp[i + 1][j + k][k + 1] = dp[i + 1][j + k][k + 1] + sum; if (dp[i + 1][j + k][k + 1] > md) dp[i + 1][j + k][k + 1] -= md; } } for (int k = 1; k <= 1001; ++k) { dp2[i][j] = (dp2[i][j] + dp[i][j][k]); if (dp2[i][j] > md) dp2[i][j] -= md; } dp2[i][j] = (dp2[i][j] * f[i]) % md; } } c[0][0] = 1; for (int i = 1; i <= 1500; ++i) for (int j = 0; j <= min(55, i); ++j) { c[i][j] = c[i - 1][j]; if (j) c[i][j] += c[i - 1][j - 1]; if (c[i][j] >= md) c[i][j] -= md; } for (int i = 1; i <= t; ++i) { int x, y; cin >> x >> y; long long res = 0; if (y > 50) { cout << 0 << n ; continue; } for (int i = 0; i <= x; ++i) res = (res + (long long)((long long)dp2[y][i] * (long long)c[x - i + y][y]) % md) % md; cout << res << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<int, vector<int> > ps; set<int> xs; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; ps[y].push_back(x); xs.insert(x); } map<int, int> rk; const int INF = 1 << 30; for (int x : xs) { int i = rk.size(); rk[x] = i + 1; } rk[INF] = xs.size() + 1; int bit[200100] = {}; long long ans = 0; xs.clear(); for (auto it = ps.rbegin(); it != ps.rend(); it++) { int y = it->first; sort(it->second.begin(), it->second.end()); for (int i = 0; i < it->second.size(); i++) { int l = it->second[i], r = (i + 1 == it->second.size() ? INF : it->second[i + 1]); long long sum1 = 0, sum2 = 0; if (xs.find(l) == xs.end()) { xs.insert(l); for (int j = rk[l]; j <= rk.size() + 1; j += j & -j) bit[j]++; } for (int j = rk[l]; j > 0; j -= j & -j) sum1 += bit[j]; for (int j = rk[r] - 1; j > 0; j -= j & -j) sum2 += bit[j]; ans += sum1 * (sum2 - sum1 + 1); } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; using vi = vector<int>; const int MAXN = 5 + 100000; vector<int> g[MAXN], s; bitset<MAXN> vis; int k, pos[MAXN]; void dfs(int u) { assert(int(g[u].size()) >= k); vis[u] = true; pos[u] = s.size(); s.push_back(u); int minp = 1e6; for (const int& v : g[u]) { if (!vis[v]) { dfs(v); return; } minp = min(minp, pos[v]); } cout << int(s.size()) - minp << n ; for (int i = minp; i < (int)s.size(); ++i) { cout << 1 + s[i] << ; } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, m; cin >> n >> m >> k; while (m--) { int u, v; cin >> u >> v; g[--u].push_back(--v); g[v].push_back(u); } vis.reset(); s.reserve(1 + k); dfs(0); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; template <typename T> void MACRO_VAR_Scan(T& t) { cin >> t; } template <typename First, typename... Rest> void MACRO_VAR_Scan(First& first, Rest&... rest) { cin >> first; MACRO_VAR_Scan(rest...); } template <typename T> void MACRO_VEC_ROW_Init(int n, T& t) { t.resize(n); } template <typename First, typename... Rest> void MACRO_VEC_ROW_Init(int n, First& first, Rest&... rest) { first.resize(n); MACRO_VEC_ROW_Init(n, rest...); } template <typename T> void MACRO_VEC_ROW_Scan(int p, T& t) { cin >> t[p]; } template <typename First, typename... Rest> void MACRO_VEC_ROW_Scan(int p, First& first, Rest&... rest) { cin >> first[p]; MACRO_VEC_ROW_Scan(p, rest...); } void _main(); signed main() { cin.tie(0); ios::sync_with_stdio(false); _main(); } inline long long toInt(std::string s) { long long v; std::istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } template <class T> inline T sqr(T x) { return x * x; } template <typename A, typename B> inline void chmin(A& a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A& a, B b) { if (a < b) a = b; } long long qp(long long a, long long b) { long long ans = 1ll; do { if (b & 1) ans = 1ll * ans * a; a = 1ll * a * a; } while (b >>= 1); return ans; } long long qpmod(long long a, long long b, long long mo) { long long ans = 1ll; do { if (b & 1) ans = 1ll * ans * a % mo; a = 1ll * a * a % mo; } while (b >>= 1); return ans; } inline long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline bool valid(int x, int h) { return 0 <= x && x < h; } const double EPS = 1e-8; const double PI = acos(-1.0); const int INF = (int)(1e9) + 7; const long long MOD = (long long)(1e9) + 7; const long long MOD2 = (long long)(1e18) + 9; const long long INF2 = (long long)(1e18); const long long INTMAX = (0x7FFFFFFFL); const long long LLMAX = (0x7FFFFFFFFFFFFFFFL); const int N4 = (int)1e4 + 10; const int N5 = (int)1e5 + 10; const int N9 = (int)1e9; int dx[8] = {1, 0, -1, 0, 1, -1, -1, 1}; int dy[8] = {0, 1, 0, -1, -1, -1, 1, 1}; struct uf_tree { std::vector<int> parent; int __size; uf_tree(int size_) : parent(size_, -1), __size(size_) {} void unite(int x, int y) { if ((x = find(x)) != (y = find(y))) { if (parent[y] < parent[x]) std::swap(x, y); parent[x] += parent[y]; parent[y] = x; __size--; } } bool is_same(int x, int y) { return find(x) == find(y); } int find(int x) { return parent[x] < 0 ? x : parent[x] = find(parent[x]); } int size(int x) { return -parent[find(x)]; } int size() { return __size; } }; long long digitsum(long long x) { long long dig; long long summ = 0; while (x) { dig = x % 10; summ = summ + dig; x = x / 10; } return summ; } long long ret, cnt, cur, ans, f; void an(long long x, long long y) { cout << x << << y << endl; } void _main() { long long n, m, k; MACRO_VAR_Scan(n, m, k); ; if (k < n) { an(k + 1, 1); return; } long long ok = 0, ng = n / 2; while (ng - ok > 1) { long long mi = (ng + ok) / 2; if (n + mi * 2 * (m - 1) <= k) ok = mi; else ng = mi; } k -= n - 1 + ok * 2 * (m - 1); int x = n - ok * 2, y = 2; if (k <= m - 1) { an(x, k + 1); return; } else { an(x - 1, m - (k - (m - 1)) + 1); return; } } |
#include <bits/stdc++.h> using namespace std; const int max_n = 300000; int a[max_n], b[max_n], p[max_n]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); a[i]--; } for (int i = 0; i < n; i++) { int t; scanf( %d , &t); t--; b[t] = i; } int res = n; for (int i = 0; i < n; i++, res--) { p[i] = b[a[i]]; if (i && p[i - 1] > p[i]) { break; } } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Value> class feque { protected: vector<Value> data; public: feque() {} feque(const feque &f) { data = f.data; } feque(feque &&f) { this->data = move(f.data); } feque(initializer_list<Value> list) { data = list; } feque &operator=(const feque &f) { data = f.data; return *this; } feque &operator=(feque &&f) { this->data = move(f.data); return *this; } feque &operator=(initializer_list<Value> list) { data = list; return *this; } bool empty() const { return data.empty(); } size_t size() { return data.size(); } Value &front() { return data.back(); } const Value &front() const { return data.back(); } Value &back() { return data.front(); } const Value &back() const { return data.front(); } void push(const Value &value) { data.push_back(value); } void pop() { data.pop_back(); } typename vector<int>::reverse_iterator begin() { return data.rbegin(); } typename vector<int>::reverse_iterator end() { return data.rend(); } Value &operator[](const int &index) { return data[data.size() - 1 - index]; } }; const int MAX_N = 1e6; const int ROOT = 1; int n; array<vector<int>, MAX_N + 1> adjacency_list; array<feque<int>, MAX_N + 1> depth_array; array<int, MAX_N + 1> dominant_index; void make_adjacent(const int &v, const int &u) { adjacency_list[v].push_back(u); adjacency_list[u].push_back(v); } bool has_child(const int &vertex) { return (vertex != ROOT and adjacency_list[vertex].size() > 1) or (vertex == ROOT and not adjacency_list[ROOT].empty()); } void compute_depth_array(const int &vertex, const int &parent = -1) { int deepest_child; if (has_child(vertex)) { deepest_child = -1; for (const int &adjacent : adjacency_list[vertex]) { if (adjacent != parent) { compute_depth_array(adjacent, vertex); if (deepest_child == -1 or depth_array[deepest_child].size() < depth_array[adjacent].size()) deepest_child = adjacent; } } dominant_index[vertex] = (depth_array[deepest_child][dominant_index[deepest_child]] > 1 ? dominant_index[deepest_child] + 1 : 0); swap(depth_array[vertex], depth_array[deepest_child]); depth_array[vertex].push(1); for (const int &adjacent : adjacency_list[vertex]) { if (adjacent != parent and adjacent != deepest_child) { for (int depth = 1; depth <= depth_array[adjacent].size(); ++depth) { depth_array[vertex][depth] += depth_array[adjacent][depth - 1]; if (depth_array[vertex][depth] > depth_array[vertex][dominant_index[vertex]] or (depth_array[vertex][depth] == depth_array[vertex][dominant_index[vertex]] and depth < dominant_index[vertex])) { dominant_index[vertex] = depth; } } } } } else { depth_array[vertex] = {1}; dominant_index[vertex] = 0; } } void optimize_IO() { ios_base::sync_with_stdio(false); cin.tie(nullptr); } int main() { optimize_IO(); cin >> n; for (int i = 1; i <= n - 1; ++i) { int x, y; cin >> x >> y; make_adjacent(x, y); } compute_depth_array(ROOT); for (int vertex = 1; vertex <= n; ++vertex) cout << dominant_index[vertex] << ; cout << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long int pow(long long int a, long long int b) { long long int ans = 1; while (b) { if (b & 1) ans *= a; a *= a; b >>= 1; } return ans; } long long int powmod(long long int a, long long int b) { long long int ans = 1; while (b) { if (b & 1) ans = (ans * a) % 10000000007; a = (a * a) % 10000000007; b >>= 1; } return ans; } bool ispal(string &a) { for (int i = 0; i < a.size() / 2; i++) if (a[i] != a[a.size() - i - 1]) return false; return true; } unsigned long long int sum(unsigned long long int n) { unsigned long long int x = 0; while (n) { x += n % 10; n /= 10; } return x; } int main() { { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); }; unsigned long long int n, m; cin >> n >> m; unsigned long long int ans = 0, p = 1; for (int i = 0; i < m; i++) { unsigned long long int x; cin >> x; ans += (p > x) ? n - p + x : x - p; p = x; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> int valid(char prev, char next) { char s[] = aeioun ; for (int i = 0; i < 6; i++) if (prev == s[i]) return 1; for (int i = 0; i < 5; i++) if (next == s[i]) return 1; return 0; } int main() { char s[300]; scanf( %s , s); int v = 1; for (int i = 0; s[i] != 0 ; i++) v &= valid(s[i], s[i + 1]); printf( %s n , v ? Yes : No ); } |
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 9; const double error = 1e-7; const double PI = acos(-1); mt19937 rng( (unsigned int)chrono::system_clock::now().time_since_epoch().count()); inline long long int MOD(long long int x, long long int m = mod) { long long int y = x % m; return (y >= 0) ? y : y + m; } const int inf = 1e9 + 2; const long long int infl = 1e18 + 1; const int nmax = 1e6 + 10; int master[nmax]; void init(int n) { for (int i = 1; i <= n; i++) master[i] = i; } int fnd(int u) { if (master[u] == u) return u; return master[u] = fnd(master[u]); } int unite(int a, int b) { a = fnd(a), b = fnd(b); if (rng() & 1) swap(a, b); master[b] = a; return a; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int n, m; cin >> n >> m; init(n); long long int two = 1; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; if (fnd(a) == fnd(b)) { two *= 2; two %= mod; } else unite(a, b); cout << MOD(two - 1) << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_8_V
`define SKY130_FD_SC_LP__CLKINV_8_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_8_V
|
#include <bits/stdc++.h> using namespace std; int n, m, sol[1000005]; struct ell { int dr, cnt, poz; bool operator<(const ell &A) const { return dr < A.dr; } }; multiset<ell> Q; struct el { int x, y, flag, cnt, poz; bool operator<(const el &A) const { if (x == A.x) { if (y == A.y) return flag > A.flag; return y > A.y; } return x < A.x; } }; el a[1000005], b[1000005]; int main() { int i, j, cn; ell w; cin.sync_with_stdio(0); cin >> n; cn = n; for (i = 1; i <= n; ++i) { cin >> a[i].x >> a[i].y; a[i].poz = i; b[i] = a[i]; } cin >> m; for (i = 1; i <= m; ++i) { cin >> a[n + i].x >> a[n + i].y >> a[n + i].cnt; a[n + i].flag = 1; a[n + i].poz = i; b[n + i] = a[n + i]; } n += m; sort(a + 1, a + n + 1); for (i = 1; i <= n; ++i) { if (a[i].flag) { w.dr = a[i].y; w.cnt = a[i].cnt; w.poz = a[i].poz; Q.insert(w); } else { ell w; w.dr = a[i].y; multiset<ell>::iterator it = Q.lower_bound(w); if (it == Q.end()) { printf( NO n ); return 0; } sol[a[i].poz] = it->poz; --b[it->poz + cn].cnt; if (!b[it->poz + cn].cnt) Q.erase(it); } } cout << YES n ; for (i = 1; i <= n - m; ++i) cout << sol[i] << ; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tlu_prencoder16.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: Datapath Priority Encoder 16b
// - 15b multihot vector as input
// - 15b 1-hit vector as output
// - Can use some std length such as 16b
// - msb is given highest priority
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module tlu_prencoder16 (din, dout);
input [14:0] din ;
output [3:0] dout ;
wire [14:0] onehot ;
assign onehot[14] = din[14] ;
assign onehot[13] = din[13] & ~din[14] ;
assign onehot[12] = din[12] & ~(|din[14:13]) ;
assign onehot[11] = din[11] & ~(|din[14:12]) ;
assign onehot[10] = din[10] & ~(|din[14:11]) ;
assign onehot[9] = din[9] & ~(|din[14:10]) ;
assign onehot[8] = din[8] & ~(|din[14:9]) ;
assign onehot[7] = din[7] & ~(|din[14:8]) ;
assign onehot[6] = din[6] & ~(|din[14:7]) ;
assign onehot[5] = din[5] & ~(|din[14:6]) ;
assign onehot[4] = din[4] & ~(|din[14:5]) ;
assign onehot[3] = din[3] & ~(|din[14:4]) ;
assign onehot[2] = din[2] & ~(|din[14:3]) ;
assign onehot[1] = din[1] & ~(|din[14:2]) ;
assign onehot[0] = din[0] & ~(|din[14:1]) ;
//assign onehot[0] = din[0] & ~(|din[15:1]) ;
assign dout[3] = |onehot[14:7] ;
assign dout[2] = (|onehot[6:3]) | (|onehot[14:11]) ;
assign dout[1] = (|onehot[2:1]) | (|onehot[6:5]) |
(|onehot[10:9]) | (|onehot[14:13]) ;
assign dout[0] = onehot[0] | onehot[2] | onehot[4] | onehot[6] |
onehot[8] | onehot[10] | onehot[12] | onehot[14] ;
endmodule
|
`timescale 10ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:28:21 02/28/2016
// Design Name: i2c_master_v4
// Module Name: C:/Users/matt/Documents/mojo/i2c_master/test_i2c_master_v4.v
// Project Name: i2c_master
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: i2c_master_v4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench;
// Inputs
reg clk;
reg reset;
reg i2c_reset;
reg [15:0] mem_addr;
reg [6:0] slave_addr;
reg [7:0] read_nbytes;
reg data_ready;
reg start;
// Outputs
wire scl;
wire [7:0] data_out;
// Bidirs
wire sda_w;
wire i2c_clk;
wire [7:0] i2c_nbytes;
wire [6:0] i2c_slave_addr;
wire i2c_rw;
wire [7:0] i2c_write_data;
wire [7:0] i2c_read_data;
wire i2c_tx_data_req;
wire i2c_rx_data_ready;
wire i2c_start;
wire byte_ready;
// Instantiate the Unit Under Test (UUT)
i2c_master uut2 (
.clk(i2c_clk),
.reset(i2c_reset),
.start(i2c_start),
.nbytes_in(i2c_nbytes),
.addr_in(i2c_slave_addr),
.rw_in(i2c_rw),
.write_data(i2c_write_data),
.read_data(i2c_read_data),
.tx_data_req(i2c_tx_data_req),
.rx_data_ready(i2c_rx_data_ready),
.sda_w(sda_w),
.scl(scl)
);
clk_divider #(.DIVIDER(500)) i2c_clk_divider (
.reset(reset),
.clk_in(clk),
.clk_out(i2c_clk)
);
read_eeprom uut (
.clk(clk),
.reset(reset),
.slave_addr_w(slave_addr),
.mem_addr_w(mem_addr),
.read_nbytes_w(read_nbytes),
.start(start),
.i2c_slave_addr(i2c_slave_addr),
.i2c_rw(i2c_rw),
.i2c_write_data(i2c_write_data),
.i2c_nbytes(i2c_nbytes),
.i2c_read_data(i2c_read_data),
.i2c_tx_data_req(i2c_tx_data_req),
.i2c_rx_data_ready(i2c_rx_data_ready),
.i2c_start(i2c_start),
.data_out(data_out),
.byte_ready(byte_ready)
);
initial begin
// Initialize Inputs
clk = 0;
forever begin
clk = #1 ~clk;
end
end
initial begin
// Initialize Inputs
reset = 1;
i2c_reset = 1;
// Wait 100 ns for global reset to finish
#5000;
//start up the clocks
reset = 0;
#5000;
// Add stimulus here
i2c_reset = 0;
slave_addr = 8'haa;
mem_addr = 16'hF0F0;
read_nbytes = 2;
#10000;
//set the start bit
start = 1;
#10000
start = 0;
#100000;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long sol[200000]; long long solve(int in, vector<int> v[], int visited[], int a[]) { if (sol[in] != -2e16) { return sol[in]; } long long ans = a[in]; visited[in] = 1; for (int i = 0; i < v[in].size(); i++) { if (visited[v[in][i]] == 0) { ans += solve(v[in][i], v, visited, a); } } visited[in] = 0; sol[in] = ans; return ans; } long long max1[200000]; long long maxx(int in, vector<int> v[], int visited[], long long sol[]) { if (max1[in] != -2e16) { return max1[in]; } long long ans = sol[in]; visited[in] = 1; for (int i = 0; i < v[in].size(); i++) { if (visited[v[in][i]] == 0) { long long xx = maxx(v[in][i], v, visited, sol); if (xx > ans) { ans = xx; } } } visited[in] = 0; max1[in] = ans; return ans; } int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } vector<int> v[n]; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; v[x - 1].push_back(y - 1); v[y - 1].push_back(x - 1); } int vis[n]; for (int i = 0; i < n; i++) { vis[i] = 0; } for (int i = 0; i < 200000; i++) { sol[i] = -2e16; max1[i] = -2e16; } long long xx = solve(0, v, vis, a); long long xy = maxx(0, v, vis, sol); queue<int> q; q.push(0); long long ans = -2e16; while (!q.empty()) { int p = q.front(); q.pop(); vis[p] = 1; priority_queue<long long> pq; for (int i = 0; i < v[p].size(); i++) { if (vis[v[p][i]] == 0) { pq.push(max1[v[p][i]]); q.push(v[p][i]); } } if (pq.size() < 2) { continue; } else { long long val = pq.top(); pq.pop(); val += pq.top(); if (val > ans) { ans = val; } } } if (ans == -2e16) { cout << Impossible << endl; return 0; } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; for (int i = 0; i < s.size(); i++) { for (char a = a ; a <= z ; a++) { string t = ; for (int j = 0; j < i; j++) { t += s[j]; } t += a; for (int j = i; j < s.size(); j++) { t += s[j]; } string r = t; reverse(t.begin(), t.end()); if (r == t) { cout << r; return 0; } } } for (char a = a ; a <= z ; a++) { string t = s; t += a; string r = t; reverse(t.begin(), t.end()); if (r == t) { cout << r; return 0; } } cout << NA ; } |
#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; const int maxN = n; int r[maxN]; int c[maxN]; int a[maxN][maxN]; for (int i = 0; i < n; i++) { r[i] = 0; for (int j = 0; j < n; j++) { cin >> a[i][j]; r[i] = r[i] + a[i][j]; } } for (int i = 0; i < n; i++) { c[i] = 0; for (int j = 0; j < n; j++) { c[i] = c[i] + a[j][i]; } } int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (c[j] > r[i]) { ans++; } } } cout << ans; return 0; } |
`define MAX_SLAVE 16
module user_dma_req_arbitrator #(
parameter NUM_SLAVES = 'd4,
parameter ADDR_WIDTH = 'd32,
parameter LEN_WIDTH = 'd12,
parameter TAG_WIDTH = 'd8,
parameter DATA_WIDTH = 'd64,
parameter DMA_LEN = 'd5
)
(
input i_clk,
input i_rst_n,
//To PSG slaves
input [NUM_SLAVES-1:0] i_slave_dma_req,
input [ADDR_WIDTH*NUM_SLAVES-1:0] i_slave_dma_addr,
input [LEN_WIDTH*NUM_SLAVES-1:0] i_slave_dma_len,
input [TAG_WIDTH*NUM_SLAVES-1 :0] i_slave_dma_tag,
output reg [NUM_SLAVES-1:0] o_slave_dma_ack,
input [NUM_SLAVES-1:0] i_slave_dma_data_avail,
input [ADDR_WIDTH*NUM_SLAVES-1:0] i_slave_dma_wr_addr,
output reg [NUM_SLAVES-1:0] o_slave_dma_data_rd,
input [NUM_SLAVES*DATA_WIDTH-1:0] i_slave_dma_data,
input [NUM_SLAVES*DMA_LEN-1:0] i_slave_dma_wr_len,
output reg [NUM_SLAVES-1:0] o_slave_dma_done,
//To PCIe Tx engine
output reg o_dma_req,
input i_dma_ack,
output reg [ADDR_WIDTH-1:0] o_dma_req_addr,
output reg [LEN_WIDTH-1:0] o_dma_req_len,
output reg [TAG_WIDTH-1:0] o_dma_req_tag,
output reg o_dma_data_avail,
output reg [ADDR_WIDTH-1:0] o_dma_wr_addr,
input i_dma_data_rd,
output reg [DATA_WIDTH-1:0] o_dma_data,
output reg [DMA_LEN-1:0] o_dma_len,
input i_dma_done
);
reg [$clog2(NUM_SLAVES)-1:0] current_req_slave_served;
reg [$clog2(NUM_SLAVES)-1:0] current_dma_slave_served;
localparam IDLE = 'd0,
DMA_REQ = 'd1;
reg rd_state;
reg wr_state;
wire some_other_wr_req;
wire some_other_rd_req;
assign some_other_wr_req = |i_slave_dma_data_avail[NUM_SLAVES-1:0];
assign some_other_rd_req = |i_slave_dma_req[NUM_SLAVES-1:0];
always@(*)
begin
o_slave_dma_data_rd <= {NUM_SLAVES{1'b0}};
o_slave_dma_data_rd[current_dma_slave_served] <= i_dma_data_rd;
o_dma_data <= i_slave_dma_data[current_dma_slave_served*DATA_WIDTH+:DATA_WIDTH];
o_dma_req_addr <= i_slave_dma_addr[current_req_slave_served*ADDR_WIDTH+:ADDR_WIDTH];
o_dma_req_len <= i_slave_dma_len[current_req_slave_served*LEN_WIDTH+:LEN_WIDTH];
o_dma_req_tag <= i_slave_dma_tag[current_req_slave_served*TAG_WIDTH+:TAG_WIDTH];
o_dma_wr_addr <= i_slave_dma_wr_addr[current_dma_slave_served*ADDR_WIDTH+:ADDR_WIDTH];
o_dma_len <= i_slave_dma_wr_len[current_dma_slave_served*DMA_LEN+:DMA_LEN];
o_slave_dma_done <= {NUM_SLAVES{1'b0}};
o_slave_dma_done[current_dma_slave_served] <= i_dma_done;
o_dma_req <= i_slave_dma_req[current_req_slave_served];
o_slave_dma_ack <= {NUM_SLAVES{1'b0}};
o_slave_dma_ack[current_req_slave_served] <= i_dma_ack;
o_dma_data_avail <= i_slave_dma_data_avail[current_dma_slave_served];
end
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
rd_state <= IDLE;
current_req_slave_served <= 0;
end
else
begin
case(rd_state)
IDLE:begin
if(i_slave_dma_req[current_req_slave_served])
begin
rd_state <= DMA_REQ;
end
else if(some_other_rd_req)
current_req_slave_served <= current_req_slave_served + 1'b1;
end
DMA_REQ:begin
if(i_dma_ack)
begin
rd_state <= IDLE;
end
end
endcase
end
end
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
wr_state <= IDLE;
current_dma_slave_served <= 0;
end
else
begin
case(wr_state)
IDLE:begin
if(i_slave_dma_data_avail[current_dma_slave_served])
begin
wr_state <= DMA_REQ;
end
else if(some_other_wr_req)
current_dma_slave_served <= current_dma_slave_served + 1'b1;
end
DMA_REQ:begin
if(i_dma_done)
begin
wr_state <= IDLE;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int qq = 3e5 + 10; vector<int> G[qq]; multiset<int, greater<int> > myset; int num[qq]; void Del(int x) { auto t = myset.find(x); myset.erase(t); } int main() { int ans = 2e9 + 10; int n; scanf( %d , &n); int a, b; for (int i = 1; i <= n; ++i) { scanf( %d , num + i); myset.insert(num[i]); } for (int i = 1; i <= n - 1; ++i) { scanf( %d%d , &a, &b); G[a].push_back(b), G[b].push_back(a); } for (int i = 1; i <= n; ++i) { Del(num[i]); int ma = num[i]; for (int y : G[i]) { Del(num[y]); ma = max(ma, num[y] + 1); } if (!myset.empty()) { ma = max(ma, *myset.begin() + 2); } for (int y : G[i]) { myset.insert(num[y]); } myset.insert(num[i]); ans = min(ans, ma); } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int OHT = 100100; const int MAXINF = (2 << 26); const int MININF = (~(2 << 26)); int vis1[110], vis2[110]; int main() { int n, m, i, j; cin >> n >> m; vector<pair<int, int> > v; for (i = 2; i <= n; i++) v.push_back(make_pair(i, 1)); for (j = 1; j <= m; j++) v.push_back(make_pair(1, j)); cout << v.size() << endl; for (i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long sol(long long n, long long t) { long long ret = n * (n + 1) * (2 * n + 3 * t + 1); ret /= 6; return ret; } int main() { ios_base::sync_with_stdio(0); long long x; cin >> x; long long ans = 0; vector<pair<long long, long long> > aa; for (long long n = 1;; n++) { long long z = sol(n, 0); if (z > x) { break; } long long r = 6 * x - 2 * n * n * n - 3 * n * n - n; long long d = 3 * n * n + 3 * n; if (r % d == 0) { ans++; aa.push_back(make_pair(n, n + r / d)); } } long long xx = aa.size(); for (int i = 0; i < xx; i++) { if (aa[i].first != aa[i].second) aa.push_back(make_pair(aa[i].second, aa[i].first)); } cout << aa.size() << n ; sort(aa.begin(), aa.end()); for (int i = 0; i < aa.size(); i++) { cout << aa[i].first << << aa[i].second << n ; } return 0; } |
// MBT 7-2-2016
//
// takes N channels and tunnels them, with credit flow control.
// will work even if you have only a single channel.
//
// SV_gripe "output parameters" would make this implementation nicer
// vector parameters would be very useful as well
`include "bsg_defines.v"
module bsg_channel_tunnel_in #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(num_in_p)
, parameter `BSG_INV_PARAM(remote_credits_p)
, use_pseudo_large_fifo_p = 0
, harden_small_fifo_p = 0
// determines when we send out credits remotely
// and consequently how much bandwidth is used on credits
, lg_credit_decimation_p = 4
, tag_width_lp = $clog2(num_in_p+1)
, tagged_width_lp = tag_width_lp+width_p
, lg_remote_credits_lp = $clog2(remote_credits_p+1)
)
(input clk_i
, input reset_i
// to downstream
, input [tagged_width_lp-1:0] data_i
, input v_i
, output yumi_o
// to outgoing channels (v/r)
, output [num_in_p-1:0][width_p-1:0] data_o
, output [num_in_p-1:0] v_o
, input [num_in_p-1:0] yumi_i
// to bsg_channel_tunnel_out; returning credits to them; they always accept
, output [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_o
, output credit_local_return_v_o
// to bsg_channel_tunnel_out; return credits to remote side
// always v
, output [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_o
// bsg_channel_tunnel sent all of the pending credits out
, input credit_remote_return_yumi_i
);
// always ready to deque credit_ready
logic credit_v_lo;
logic [width_p-1:0] credit_data_lo;
// demultiplex the packets.
bsg_1_to_n_tagged_fifo #(.width_p (width_p)
,.num_out_p (num_in_p+1 )
,.els_p (remote_credits_p)
// credit fifo is unbuffered
,.unbuffered_mask_p (1 << num_in_p )
,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p)
,.harden_small_fifo_p(harden_small_fifo_p)
)
b1_ntf
(.clk_i
,.reset_i
,.v_i (v_i)
,.tag_i (data_i[width_p+:tag_width_lp])
,.data_i(data_i[0+:width_p])
,.yumi_o
// v / ready
,.v_o ( {credit_v_lo, v_o} )
,.data_o ( {credit_data_lo , data_o } )
// credit fifo is unbuffered, so no yumi signal
,.yumi_i ( { 1'b0, yumi_i } )
);
// route local credit return to bsg_channel_tunnel_out module
assign credit_local_return_data_o = credit_data_lo[0+:num_in_p*lg_remote_credits_lp];
assign credit_local_return_v_o = credit_v_lo;
// compute remote credit arithmetic
wire [num_in_p-1:0] sent = v_o & yumi_i;
genvar i;
// keep track of how many credits need to be send back
for (i = 0; i < num_in_p; i=i+1)
begin: rof
bsg_counter_clear_up #(.max_val_p (remote_credits_p)
,.init_val_p(0)
) ctr
(.clk_i
,.reset_i
,.clear_i (credit_remote_return_yumi_i )
,.up_i (sent[i] )
,.count_o (credit_remote_return_data_o[i])
);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_channel_tunnel_in)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N=2e5+10; int a[N],tt; int cnt[N]; int pre[N]; int main(){ int t; scanf( %d ,&t); while(t--){ int n; tt=0; scanf( %d ,&n); for(int i=1;i<=n;i++) scanf( %d ,&a[i]); sort(a+1,a+n+1); for(int i=1;i<=n;i++){ if(a[i]==a[i-1]) cnt[tt]++; else{ tt++; cnt[tt]++; } } priority_queue<int>s; for(int i=1;i<=tt;i++) { s.push(cnt[i]); cnt[i]=0; } int sh=0; int ans; while(1){ if(s.size()==1) { ans = s.top(); break; } if(s.empty()){ ans=0; break; } int a=s.top(); s.pop(); int b=s.top(); s.pop(); a--; b--; if(a!=0) s.push(a); if(b!=0) s.push(b); } printf( %d n ,ans); } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
// by: wig
// on: Sat Mar 3 09:45:57 2007
// cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.1 2007/03/03 11:17:34 wig Exp $
// $Date: 2007/03/03 11:17:34 $
// $Log: inst_b_e.v,v $
// Revision 1.1 2007/03/03 11:17:34 wig
// Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./03/01 16:28:38 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
HOOK: global verilog head hook text
//
//
// Start of Generated Module rtl of inst_b_e
//
// No user `defines in this module
module inst_b_e
//
// Generated Module inst_b_i
//
(
p_mix_signal_aa_ba_gi,
p_mix_signal_bb_ab_go
);
// Generated Module Inputs:
input p_mix_signal_aa_ba_gi;
// Generated Module Outputs:
output [7:0] p_mix_signal_bb_ab_go;
// Generated Wires:
wire p_mix_signal_aa_ba_gi;
wire [7:0] p_mix_signal_bb_ab_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire signal_aa_ba; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] signal_bb_ab; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign signal_aa_ba = p_mix_signal_aa_ba_gi; // __I_I_BIT_PORT
assign p_mix_signal_bb_ab_go = signal_bb_ab; // __I_O_BUS_PORT
udc: THIS ARE TWO LINES in BODY of inst_b_i
SECOND LINE
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ba_i
inst_xa_e inst_ba_i ( // mulitple instantiated
.port_xa_i(signal_aa_ba), // signal test aa to ba
.port_xa_o() // open signal to create port
);
// End of Generated Instance Port Map for inst_ba_i
// Generated Instance Port Map for inst_bb_i
inst_bb_e inst_bb_i ( // bb instance
.port_bb_o(signal_bb_ab) // vector test bb to ab
);
// End of Generated Instance Port Map for inst_bb_i
// Generated Instance Port Map for inst_bc1_i
inst_vb_e inst_bc1_i ( // verilog udc inst_bc2_i
);
// End of Generated Instance Port Map for inst_bc1_i
udc: preinst_udc for inst_bc2_i
// Generated Instance Port Map for inst_bc2_i
inst_vb_e inst_bc2_i ( // verilog udc inst_bc2_i
);
// End of Generated Instance Port Map for inst_bc2_i
udc: post_inst_udc for inst_bc2_i
// Generated Instance Port Map for inst_be_i
inst_be_i inst_be_i ( // no verilog udc here
);
// End of Generated Instance Port Map for inst_be_i
// Generated Instance Port Map for inst_bf_i
inst_be_i inst_bf_i ( // no verilog udc here
);
// End of Generated Instance Port Map for inst_bf_i
endmodule
//
// End of Generated Module rtl of inst_b_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int maxp = 22; const long double EPS = 1e-18; const long long INF = 2e18; const int MOD = 1e9 + 7; const int N = 2e5 + 1; string s, t = hard ; long long dp[N][4]; long long arr[N]; int n; long long solve(int x, int idx) { if (idx == 4) return INF; if (x == n) return 0; if (dp[x][idx] != -1) return dp[x][idx]; int nxt = idx; if (s[x] == t[idx]) nxt++; return dp[x][idx] = min(solve(x + 1, idx) + arr[x], solve(x + 1, nxt)); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> s; int i, j; for (i = 0; i < n; i++) cin >> arr[i]; for (i = 0; i < n; i++) for (j = 0; j < 4; j++) dp[i][j] = -1; cout << solve(0, 0) << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, temp = 0; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int i; for (i = 1; i <= n; i++) { temp += i; if (temp >= k) break; } int gap = temp - k; cout << a[i - gap - 1]; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == W && s[i + 1] == U && s[i + 2] == B ) { i += 2; cout << ; } else { cout << s[i]; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_LP2_V
`define SKY130_FD_SC_LP__NOR2_LP2_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_lp2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_lp2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_LP2_V
|
#include <bits/stdc++.h> using namespace std; const bool debug = true; const int MAXN = 100010; int dp[MAXN], t[MAXN]; const int inf = 2000000010; int n; int first_lower(int x) { if (x < 0) return 0; return upper_bound(t + 1, t + n + 1, x) - t - 1; } struct node { int mx; int lazy; node() {} node(int _mx, int _lazy) { mx = _mx; lazy = _lazy; } node operator+(const node &a) const { return *(new node(max(mx, a.mx), 0)); } } st[4 * MAXN]; int value[MAXN]; void propagate(int idx, int left, int right) { if (st[idx].lazy == 0) return; st[idx].mx += st[idx].lazy; if (left != right) { st[2 * idx].lazy += st[idx].lazy; st[2 * idx + 1].lazy += st[idx].lazy; } st[idx].lazy = 0; } void update(int idx, int left, int right, int l, int r, int val) { if (l <= left && right <= r) { st[idx].lazy += val; return; } propagate(idx, left, right); if (r > (left + right) / 2) update(2 * idx + 1, (left + right) / 2 + 1, right, l, r, val); if (l <= (left + right) / 2) update(2 * idx, left, (left + right) / 2, l, r, val); propagate(2 * idx, left, (left + right) / 2); propagate(2 * idx + 1, (left + right) / 2 + 1, right); st[idx] = st[2 * idx] + st[2 * idx + 1]; } int get(int idx, int left, int right) { propagate(idx, left, right); if (left != right) { propagate(2 * idx, left, (left + right) / 2); propagate(2 * idx + 1, (left + right) / 2 + 1, right); } if (left == right) if (st[idx].mx > 0) return value[left]; else return -1; if (st[2 * idx + 1].mx > 0) return get(2 * idx + 1, (left + right) / 2 + 1, right); else if (st[2 * idx].mx > 0) return get(2 * idx, left, (left + right) / 2); else return -1; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int p, type; scanf( %d %d , &p, &type); if (type == 1) { int val; scanf( %d , &val); value[p] = val; update(1, 1, n, 1, p, 1); } else update(1, 1, n, 1, p, -1); printf( %d n , get(1, 1, n)); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:13:46 07/24/2014
// Design Name: EMU Device
// Module Name: DM_TLV5619_DAC_Interface
//////////////////////////////////////////////////////////////////////////////////
module DM_TLV5619_DAC_Interface_Module(
DACDataInput,
DACCS,
CLK,
SampleDelayZero,
DACLDAC,
DACPD,
DACWE,
IFFTOutput,
DMLocationWritingTo,
IFFTOutputWE,
IFFTOutputIndex
);
input CLK, SampleDelayZero, IFFTOutputWE;
input [9:0] DMLocationWritingTo;
input [11:0] IFFTOutput;
input [8:0] IFFTOutputIndex;
output DACCS, DACLDAC, DACPD, DACWE;
output [11:0] DACDataInput;
reg [11:0] DACDataInput;
reg [14:0] DACDelayCount; //Could be 12:0, but 2 bits added to avoid off-by one errors
wire SampleDelayZero, DACCS, IFFTOutputWE;
wire [11:0] IFFTOutput;
wire [8:0] IFFTOutputIndex;
(* RAM_STYLE="{auto | block | block_power1 | block_power2}" *)
reg [11:0] StoredDACValues [0:1023];
assign DACCS = 0;
assign DACLDAC = 0;
assign DACPD = 1;
assign DACWE = (~| DACDelayCount[12:4]) && ( DACDelayCount[3]);
assign DACMemWE = IFFTOutputWE; //############################### IFFT based ##############################//
always @(posedge CLK)
begin
if (DACMemWE)
begin
StoredDACValues [ {!DMLocationWritingTo[9], IFFTOutputIndex} ] <= IFFTOutput[11:0]; //IFFT Index, really
end
DACDataInput[11:0] <= StoredDACValues[DMLocationWritingTo + 4];
end
always @(posedge CLK)
begin
if ( SampleDelayZero ) // Counts from 0 to 8191 (1111111111111)
begin
DACDelayCount <= 0;
end
else
begin
DACDelayCount <= DACDelayCount + 1;
end
end
endmodule |
module rnd_vec_gen(
clk,
init,
save,
restore,
next,
out
);
parameter OUT_SIZE = 16; // size of output port, independent of LFSR register size
parameter LFSR_LENGTH = 55; // LFSR
parameter LFSR_FEEDBACK = 24; // definition
input clk;
input init; // positive initialization strobe, synchronous to clock, its length will determine initial state
input save,restore,next; // strobes for required events: positive, one clock cycle long
reg init2;
output [OUT_SIZE-1:0] out;
wire [OUT_SIZE-1:0] out;
reg [OUT_SIZE-1:0] rndbase_main [0:LFSR_LENGTH-1];
reg [OUT_SIZE-1:0] rndbase_store [0:LFSR_LENGTH-1];
assign out = rndbase_main[0];
always @(posedge clk)
begin
init2 <= init;
if( init && !init2 ) // begin of initialization
begin
rndbase_main[0][0] <= 1'b1; // any non-zero init possible
end
else if( init && init2 ) // continue of initialization
begin
shift_lfsr;
end
else // no init, normal work
begin
if( restore ) // restore event: higher priority
begin
integer i;
for(i=0;i<LFSR_LENGTH;i=i+1)
rndbase_main[i] <= rndbase_store[i];
end
else
begin
if( next ) // step to next value
begin
shift_lfsr;
end
if( save ) // save current state
begin
integer j;
for(j=0;j<LFSR_LENGTH;j=j+1)
rndbase_store[j] <= rndbase_main[j];
end
end
end
end
/* function [LFSR_LENGTH-1:0] shift_lfsr;
input [LFSR_LENGTH-1:0] old_lfsr;
begin
if( |old_lfsr ) // prevent spurious stalls if all LFSR is zeros
shift_lfsr[LFSR_LENGTH-1:0] = { old_lfsr[LFSR_LENGTH-2:0], old_lfsr[LFSR_LENGTH-1]^old_lfsr[LFSR_FEEDBACK-1] };
else
shift_lfsr[LFSR_LENGTH-1:0] = 2'd1;
end
endfunction
*/
task shift_lfsr;
begin
reg [OUT_SIZE-1:0] sum;
reg [LFSR_LENGTH-1:0] lsbs;
integer i;
for(i=0;i<LFSR_LENGTH;i=i+1)
lsbs[i] = rndbase_main[i][0];
sum = rndbase_main[LFSR_LENGTH-1] + rndbase_main[LFSR_FEEDBACK-1];
// integer j;
for(i=1;i<LFSR_LENGTH;i=i+1)
rndbase_main[i] <= rndbase_main[i-1];
rndbase_main[0] <= { sum[OUT_SIZE-1:1], (|lsbs)?sum[0]:1'b1 };
end
endtask
endmodule
|
// soc_system_mm_interconnect_1_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_1_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_1_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
`timescale 1ns / 1ps
`include "defs.vh"
`define STATE_IDLE 0
`define STATE_RDID 1
`define STATE_WAIT 2
`define STATE_WREN 3
`define STATE_BE 4
`define STATE_POLL_RFSR 5
`define STATE_PP 6
`define STATE_SE 7
`define STATE_WRVECR 8
`define STATE_RDVECR 9
`define STATE_RDSR 10
`define STATE_MIORDID 11
module qspi_mem_controller(
input clk,
input reset,
input trigger,
input quad_mode,
input [7:0] cmd,
input [(3+256)*8-1:0] data_send, // max: 256B page data + 3B address
output reg [7:0] readout,
output reg busy,
output reg error,
inout [3:0] DQio,
output S
);
reg spi_trigger;
wire spi_busy;
reg [260*8-1:0] data_in;
reg [8:0] data_in_count;
wire [7:0] data_out;
reg data_out_count;
reg [35:0] delay_counter;
reg [5:0] state;
reg [5:0] nextstate;
spi_cmd sc (
.clk(clk),
.reset(reset),
.trigger(spi_trigger),
.busy(spi_busy),
.quad_mode(quad_mode),
.data_in_count(data_in_count),
.data_out_count(data_out_count),
.data_in(data_in),
.data_out(data_out),
.DQio(DQio[3:0]),
.S(S)
);
always @(posedge clk) begin
if (reset) begin
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
spi_trigger <= 0;
busy <= 1;
error <= 0;
readout <= 0;
end
else
case (state)
`STATE_IDLE: begin
if (trigger) begin
busy <= 1;
error <= 0;
case (cmd)
`CMD_RDID:
state <= `STATE_RDID;
`CMD_MIORDID:
state <= `STATE_MIORDID;
`CMD_WREN:
state <= `STATE_WREN;
`CMD_BE:
state <= `STATE_BE;
`CMD_SE:
state <= `STATE_SE;
`CMD_PP:
state <= `STATE_PP;
`CMD_WRVECR:
state <= `STATE_WRVECR;
`CMD_RDVECR:
state <= `STATE_RDVECR;
`CMD_RDSR:
state <= `STATE_RDSR;
default: begin
$display("ERROR: unknown command!");
$stop;
end
endcase
end else
busy <= 0;
end
`STATE_RDID: begin
data_in <= `CMD_RDID;
data_in_count <= 1;
data_out_count <= 1;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
if (quad_mode == 1) begin
$display("ERROR: RDID is not available in quad mode!");
$stop;
end
end
`STATE_MIORDID: begin
data_in <= `CMD_MIORDID;
data_in_count <= 1;
data_out_count <= 1;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
if (quad_mode == 0) begin
$display("ERROR: MIORDID is only available in quad mode!");
$stop;
end
end
`STATE_RDSR: begin
data_in <= `CMD_RDSR;
data_in_count <= 1;
data_out_count <= 1;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
end
`STATE_WRVECR: begin
data_in <= {`CMD_WRVECR, data_send[7:0]};
data_in_count <= 2;
data_out_count <= 0;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
end
`STATE_RDVECR: begin
data_in <= `CMD_RDVECR;
data_in_count <= 1;
data_out_count <= 1;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
end
`STATE_WREN: begin
data_in <= `CMD_WREN;
data_in_count <= 1;
data_out_count <= 0;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_IDLE;
end
`STATE_BE: begin
data_in <= `CMD_BE;
data_in_count <= 1;
data_out_count <= 0;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_POLL_RFSR;
delay_counter <= `tBEmax*`input_freq;
end
`STATE_POLL_RFSR: begin
if (delay_counter == 0) begin // max delay timeout
state <= `STATE_IDLE;
error <= 1;
end else begin
if (readout[7] == 1) begin // operation finished successfully
state <= `STATE_IDLE;
end else begin // go on polling
data_in <= `CMD_RFSR;
data_in_count <= 1;
data_out_count <= 1;
spi_trigger <= 1;
delay_counter <= delay_counter - 1;
state <= `STATE_WAIT;
nextstate <= `STATE_POLL_RFSR;
end
end
end
`STATE_WAIT: begin
spi_trigger <= 0;
if (!spi_trigger && !spi_busy) begin
state <= nextstate;
readout <= data_out;
end
end
`STATE_PP: begin
data_in <= {`CMD_PP, data_send};
data_in_count <= 260; // 256 bytes for data + 1 for command + 3 for address
data_out_count <= 0;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_POLL_RFSR;
delay_counter <= `tPPmax * `input_freq;
end
`STATE_SE: begin
data_in <= {`CMD_SE, data_send[23:0]};
data_in_count <= 4; // 1 byte command + 3 bytes address
data_out_count <= 0;
spi_trigger <= 1;
state <= `STATE_WAIT;
nextstate <= `STATE_POLL_RFSR;
delay_counter <= `tSEmax * `input_freq;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> const int N = 3003; const long long mod = 998244353; using namespace std; int n; int c; int a[N]; int p[N]; int res[N]; int d[N][N]; int g[N][N]; int f1[N][1 << 12]; void upd(int &x, int y) { x += y; if (x >= mod) { x -= mod; } else if (x < 0) { x += mod; } } void solve1() { int nj, nk, last = (1 << c) - 1; for (int i = 1; i <= n; i++) { for (int j = (i - 1) / c; j >= 0; j--) { for (int k = last - 1; k >= 0; k--) { nj = j; nk = k | (1 << a[i]); if (nk == last) { nj += 1; nk = 0; upd(d[i][nj], f1[j][k]); } upd(f1[nj][nk], f1[j][k]); } } if (c == 1) { upd(d[i][1], 1); upd(f1[1][0], 1); } else { upd(f1[0][1 << a[i]], 1); } } } long long pw(long long x, long long n) { long long res = 1; while (n) { if (n & 1) { res = res * x % mod; } x = x * x % mod; n /= 2; } return res; } int t[N]; int inv[N]; void solve2() { for (int i = 1; i < n; i++) { inv[i] = pw(p[i] - 1, mod - 2); } for (int i = 1; i <= n; i++) { for (int j = 0; j < c; j++) { t[j] = 0; } int j = i - 1; int sad = c; while (j < n && sad) { j += 1; t[a[j]] += 1; sad -= t[a[j]] == 1; } if (sad) { break; } long long res = 1; for (int h = 0; h < c; h++) { res = res * (p[t[h]] - 1) % mod; } sad = 1; for (; j <= n; j++) { res = res * inv[t[a[j]]] % mod; g[i][j] = res; if (sad) { sad = 0; } else { t[a[j]] += 1; } res = res * (p[t[a[j]]] - 1) % mod; } } d[0][0] = 1; int k = n / c; d[0][0] = 1; long long sum, MOD = mod, MOD2 = mod * mod; for (int r = 1; r <= k; r++) { d[0][r] = 0; for (int i = r * c - 1; i < n; i++) { sum = 0; for (int j = i; j >= (r - 1) * c; j--) { sum += 1LL * g[j + 1][i + 1] * d[j][r - 1]; if (sum >= MOD2) sum -= MOD2; } d[i + 1][r] = (sum % MOD); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> c; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] -= 1; } p[0] = 1; for (int i = 1; i <= n; i++) { p[i] = p[i - 1]; upd(p[i], p[i]); } if (c <= 10) { solve1(); } else { solve2(); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { upd(res[j], 1ll * d[i][j] * p[n - i] % mod); } } res[0] = p[n]; upd(res[0], -1); for (int i = 0; i <= n; i++) { upd(res[i], -res[i + 1]); cout << res[i] << ; } } |
#include <bits/stdc++.h> using namespace std; bool life[1000005]; int main() { long long a, b; int l, r, mid; int ans, cnt = 0; scanf( %lld%lld , &a, &b); l = 0; r = 1000000007; while (l != r) { mid = (r + l + 1) / 2; if (((mid + 1LL) * mid) / 2 > a + b) r = mid - 1; else l = mid; } ans = l; for (int i = l; i > 0; i--) { if (a >= i) { a -= i; life[i] = 1; cnt++; } } printf( %d n , cnt); if (cnt) { for (int i = 1; i <= l; i++) { if (life[i]) printf( %d , i); } printf( n ); } printf( %d n , ans - cnt); if (ans - cnt) { for (int i = 1; i <= l; i++) { if (!life[i]) printf( %d , i); } printf( n ); } return 0; } |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF7.v,v 1.11 2007/08/23 23:00:26 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Lookup Table Multiplexer with General Output
// /___/ /\ Filename : MUXF7.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXF7 (O, I0, I1, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, S;
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int N = 1234567; int pref[N], a[N], b[N]; char c[N]; int solve(vector<pair<int, int> > z, int b) { sort(z.begin(), z.end()); int cnt = z.size(); if (cnt < 2) { return 0; } pref[0] = 0; for (int i = 0; i < cnt; i++) { pref[i + 1] = max(pref[i], z[i].second); } int i = 0; int res = 0; for (int j = cnt - 1; j >= 0; j--) { while (i < j && z[i].first + z[j].first <= b) { i++; } i = min(i, j); if (i > 0) { res = max(res, pref[i] + z[j].second); } } return res; } int same(vector<pair<int, int> > &v, int b) { if (v.size() < 2) return 0; sort(v.begin(), v.end()); vector<int> pre(v.size() + 1, 0); for (int i = 0; i < v.size(); i++) pre[i + 1] = max(pre[i], v[i].second); int i = 0, ans = 0; for (int j = v.size() - 1; j >= 0; j--) { while (i < j && v[i].first + v[j].first <= b) i++; i = min(i, j); if (i > 0) { ans = max(ans, v[j].second + pre[i]); } } return ans; } int main() { int n, C, D; scanf( %d %d %d , &n, &C, &D); for (int i = 0; i < n; i++) { scanf( %d %d , a + i, b + i); c[i] = getchar(); while (c[i] != C && c[i] != D ) { c[i] = getchar(); } } int ans = 0; { int x = 0, y = 0; for (int i = 0; i < n; i++) { if (c[i] == C && b[i] <= C) { x = max(x, a[i]); } } for (int i = 0; i < n; i++) { if (c[i] == D && b[i] <= D) { y = max(y, a[i]); } } if (x > 0 && y > 0) { ans = max(ans, x + y); } } { vector<pair<int, int> > z; for (int i = 0; i < n; i++) { if (c[i] == C ) { z.push_back(make_pair(b[i], a[i])); } } ans = max(ans, same(z, C)); } { vector<pair<int, int> > z; for (int i = 0; i < n; i++) { if (c[i] == D ) { z.push_back(make_pair(b[i], a[i])); } } ans = max(ans, same(z, D)); } printf( %d n , ans); return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: demux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple demultiplexer
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module demux
#(
parameter C_OUTPUTS = 12,
parameter C_WIDTH = 1
)
(
input [C_WIDTH-1:0] WR_DATA,// Inputs
input [clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector
output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs
);
`include "functions.vh"
genvar i;
reg [C_OUTPUTS*C_WIDTH-1:0] _rOut;
assign RD_DATA = _rOut;
always @(*) begin
_rOut = 0;
_rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N, M, K, R, l, r, A, B, X, Y, Z, C, D, Q, a, b, c, d, i, j, k, first, mx, ans, cnt, T, P; void solve() { cin >> N >> K; long long A[N]; long long lar = INT_MIN, sma = INT_MAX; for (long long int i = 0; i < N; i++) { cin >> A[i]; lar = max(lar, A[i]); sma = min(sma, A[i]); } for (long long int i = 0; i < N; i++) { A[i] = lar - A[i]; } if (K % 2 == 0) { for (long long int i = 0; i < N; i++) { A[i] = lar - sma - A[i]; } } for (long long int i = 0; i < N; i++) { cout << A[i] << ; } cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21A_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21a (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_BLACKBOX_V
|
module q_mul8
(
input CLK,
input RESET_X,
input INPUT_EN,
input [7:0] A_IN,
input [7:0] B_IN,
input [7:0] A_IN_INV,
input [7:0] B_IN_INV,
input A_SEL_INV,
input B_SEL_INV,
output OUTPUT_EN,
output [7:0] C_OUT,
input [31:0] MLC_GAGB,
// MULL ADD1
input [31:0] ML1_GAIN,
input [31:0] ML1_QPARAM,
input [31:0] ML2_GAIN,
input [31:0] ML2_QPARAM,
output [15:0] MIN,
output [15:0] MAX
);
// # vector
// AdBd_qt, AdBd_min, AdBd_max = q_mul_core(a_qt, Adash_min, Adash_max, b_qt, Bdash_min, Bdash_max, debug=debug)
// C_qt_0, C_qt_0_min, C_qt_0_max = q_add(qt_A_bmin, A_bmin_min, A_bmin_max, qt_B_amin, B_amin_min, B_amin_max, debug=debug)
// C_qt, c_min, c_max = q_add(AdBd_qt, AdBd_min, AdBd_max, C_qt_0, C_qt_0_min, C_qt_0_max, debug=debug)
wire [7:0] AdBd_qt;
wire mul_core_en;
wire [7:0] C_qt_0;
wire [7:0] qt_A_bmin;
wire [7:0] qt_B_amin;
wire add_1st_en;
assign qt_A_bmin = A_SEL_INV ? A_IN_INV : A_IN;
assign qt_B_amin = B_SEL_INV ? B_IN_INV : B_IN;
reg [7:0] AdBd_qt_1t;
q_mul_core8 mul_core
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(INPUT_EN),
.A_IN(A_IN),
.B_IN(B_IN),
.OUTPUT_EN(mul_core_en),
.C_OUT(AdBd_qt),
.MLC_GAGB(MLC_GAGB)
);
q_add8 add_1st
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(INPUT_EN),
.A_IN(qt_A_bmin),
.B_IN(qt_B_amin),
.OUTPUT_EN(add_1st_en),
.C_OUT(C_qt_0),
.GAIN(ML1_GAIN),
.Q_PARAM(ML1_QPARAM),
.MIN(),
.MAX()
);
q_add8 add_2nd
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(add_1st_en),
.A_IN(AdBd_qt_1t),
.B_IN(C_qt_0),
.OUTPUT_EN(OUTPUT_EN),
.C_OUT(C_OUT),
.GAIN(ML2_GAIN),
.Q_PARAM(ML2_QPARAM),
.MIN(MIN),
.MAX(MAX)
);
always @ (posedge CLK or negedge RESET_X)begin
if (RESET_X == 0)begin
AdBd_qt_1t <= 8'h00;
end else begin
AdBd_qt_1t <= AdBd_qt;
end
end
endmodule // q_mul8
|
#include <bits/stdc++.h> using namespace std; const int MX = (1 << 20); priority_queue<pair<int, int> > Q[MX]; string str; int n, K; int main() { cin >> str >> K; n = str.size(); int cur = 0; for (int j = 0; j < n; j++) Q[0].push(make_pair( z - str[j], j)); while (1) { while (cur > -1 && Q[cur].empty()) cur--; if (cur == -1) break; int let = Q[cur].top().first; while (!Q[cur].empty() && Q[cur].top().first == let) { int pos = Q[cur].top().second; if (pos + cur + 1 < n) Q[cur + 1].push(make_pair( z - str[pos + cur + 1], pos)); K--; if (K == 0) { cout << str.substr(pos, cur + 1); return 0; } Q[cur].pop(); } cur++; } puts( No such line. ); } |
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:16:16 02/06/2014
// Design Name:
// Module Name: zxuno
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module zxuno(
input wire clk,
input wire wssclk,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync
);
wire [8:0] h;
wire [8:0] v;
reg [2:0] rojo;
reg [2:0] verde;
reg [2:0] azul;
always @* begin
if (h>=0 && h<256 && v>=0 && v<192) begin
if (v>=0 && v<64) begin
rojo = h[7:5];
verde = 3'b000;
azul = 3'b000;
end
else if (v>=64 && v<128) begin
rojo = 3'b000;
verde = h[7:5];
azul = 3'b000;
end
else begin
rojo = 3'b000;
verde = 3'b000;
azul = h[7:5];
end
end
else begin
rojo = 3'b100;
verde = 3'b100;
azul = 3'b100;
end
end
pal_sync_generator_progressive syncs (
.clk(clk),
.wssclk(wssclk),
.ri(rojo),
.gi(verde),
.bi(azul),
.hcnt(h),
.vcnt(v),
.ro(r),
.go(g),
.bo(b),
.csync(csync)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_TB_V
`define SKY130_FD_SC_HS__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 C1 = 1'b1;
#280 C2 = 1'b1;
#300 VGND = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 C1 = 1'b0;
#440 C2 = 1'b0;
#460 VGND = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VGND = 1'b1;
#540 C2 = 1'b1;
#560 C1 = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VGND = 1'bx;
#700 C2 = 1'bx;
#720 C1 = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hs__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_TB_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { while (a != 0 && b != 0) { if (a > b) a %= b; else b = b % a; } return a + b; } int main() { int k, l, m, n, d; cin >> k >> l >> m >> n >> d; int ans = 0; for (int i = (1); i < (d + 1); i++) if (i % k == 0 || i % l == 0 || i % m == 0 || i % n == 0) ans++; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N (
Q ,
SET ,
RESET ,
CLK_N ,
D ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input SET ;
input RESET ;
input CLK_N ;
input D ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> int read() { int ans = 0, c, f = 1; while (!isdigit(c = getchar())) if (c == - ) f *= -1; do ans = ans * 10 + c - 0 ; while (isdigit(c = getchar())); return ans * f; } const int N = 1000050; int n, a[N]; long long S; long long calc(long long p) { long long ans = 0, t = 0; for (int i = 0; i < n; ++i) { t = (t + a[i]) % p; ans += std::min(t, p - t); } return ans; } int main() { n = read(); for (int i = 0; i < n; ++i) S += a[i] = read(); if (S == 1) { puts( -1 ); return 0; } long long ans = 0x7fffffffffffffffLL; for (long long i = 2; i * i <= S; ++i) if (S % i == 0) { ans = std::min(ans, calc(i)); while (S % i == 0) S /= i; } if (S != 1) ans = std::min(ans, calc(S)); printf( %lld n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_BEHAVIORAL_PP_V |
``
#this file is not meant to be used directly, the entry point is hamming_code.tgpp
proc hammingCodeVerilogFunction { inputWidth {code_extention 0} {userOutputWidth 0} } {
set parameters [hammingCodeFunctionParams $inputWidth $code_extention $userOutputWidth]
dictToVars $parameters
set hammingCodeDict [hammingCode $inputWidth $extended $userOutputWidth]
if {$ecc} {
#compute the corrector part
hammingCodeCorrectionPattern hammingCodeDict
}
#do a bit of self checking
checkHammingCode $hammingCodeDict
return [hammingCodeVerilogFunction2 $hammingCodeDict $ecc]
}
proc hammingCodeVerilogModule { name inputWidth {code_extention 0} {userOutputWidth 0} } {
set parameters [hammingCodeFunctionParams $inputWidth $code_extention $userOutputWidth]
dictToVars $parameters
puts "compute hamming code"
set hammingCodeDict [hammingCode $inputWidth $code_extention $userOutputWidth]
if {$ecc} {
#compute the corrector part
puts "compute ecc corrector part"
hammingCodeCorrectionPattern hammingCodeDict
}
#do a bit of self checking
puts "self check"
checkHammingCode $hammingCodeDict
puts "generating verilog code"
``
module `$name` (
input wire [`$inputWidth`-1:0] i_write_data, // Data to write to storage
output reg [`$r`-1:0] o_write_edc, // EDC bits to write to storage
input wire [`$inputWidth`-1:0] i_stored_data, // Data read from storage, may contain error(s)
input wire [`$r`-1:0] i_stored_edc, // EDC bits read from storage, may conatin error(s)
``if {$ecc} {``
output reg [`$inputWidth`-1:0] o_read_data, // Error free read data (as long as error was correctable)
output reg o_correction, //indication that an error is corrected
``}``
output reg o_detection //indication that an error is detected``if {$ecc} {``, this happens only if the error is not correctable``}``
);
`hammingCodeVerilogFunction2 $hammingCodeDict $ecc`
wire [`$r`-1:0] stored_data_edc = `$funcName`(i_stored_data);
wire [`$r`-1:0] syndroms = i_stored_edc ^ stored_data_edc;
``if {$ecc} {``
reg uncorrectable_error;
reg [`$inputWidth`-1:0] correction_pattern;
always @* begin
{o_detection,o_correction,correction_pattern} = `$eccFuncName`(syndroms,CORRECT_EDC_SINGLE_BIT_ERRORS);
o_read_data = i_stored_data ^ correction_pattern;
end
``} else {``
always @* o_detection = |syndroms;
``}``
endmodule
``
#return all except the last new line character
return [string range [::tgpp::getProcOutput] 0 end-1]
}
proc hammingCodeVerilogFunction2 { hammingCodeDict {ecc 0} } {
dictToVars $hammingCodeDict
``
`hammingCodeCommentsC $hammingCodeDict`
function [`$r`-1:0] `$funcName`;
input [`$k`-1:0] in;
reg [`$r`-1:0] syndrom;
begin
``for {set syndromBit 0} {$syndromBit<[llength [dict keys $bits]]} {incr syndromBit} {
set inBits [list]
foreach b [dict get $bits $syndromBit] {
lappend inBits in\[[format %${indexesWidth}s $b]\]
dict lappend loads $b $syndromBit
}
``
syndrom[`format %${syndromIndexesWidth}s $syndromBit`] = `listToString $inBits "^"`;//`dict get $bitsInputs $syndromBit` inputs
``}``
`$funcName` = syndrom;
end
endfunction
``if {$ecc} {``
function [2+`$k`-1:0] `$eccFuncName`;
input [`$r`-1:0] syndrom;
input correctEdcSingleBitErrors;
reg uncorrectable_error;
reg correctable_error;
reg [`$k`-1:0] correction_pattern;
reg edcSingleBitErrorFillValue;
begin
edcSingleBitErrorFillValue = correctEdcSingleBitErrors ? 1'b0 : 1'bx;
correction_pattern = {`$k`{1'bx}};
correctable_error = 1'b1;
uncorrectable_error = 1'b0;
case(syndrom)
`$r`'b`string map {" " ""} [valToBits 0 $r]`: begin
correctable_error = 1'b0;
correction_pattern = {`$k`{1'b0}};
end
``for {set inputBit 0} {$inputBit<[llength [dict keys $eccPatterns]]} {incr inputBit} {``
`$r`'b`string reverse [dict get $eccPatterns $inputBit]`: begin
correction_pattern = {`$k`{1'b0}};correction_pattern[`format %${indexesWidth}s $inputBit`]=1'b1;
end
``}``
``for {set inputBit 0} {$inputBit<[llength [dict keys $eccEdcSingleBitErrorPatterns]]} {incr inputBit} {``
`$r`'b`string reverse [dict get $eccEdcSingleBitErrorPatterns $inputBit]`: begin
uncorrectable_error = ~correctEdcSingleBitErrors;//if we don't correct it, count it as a detected error
correction_pattern = {`$k`{edcSingleBitErrorFillValue}};//single bit error on EDC bits -> nothing to correct!
end
``}``
default: begin
uncorrectable_error = 1'b1;
correctable_error = 1'b0;
end
endcase
`$eccFuncName` = {uncorrectable_error,correctable_error,correction_pattern};
end
endfunction
``}
#return all except the last new line character
return [string range [::tgpp::getProcOutput] 0 end-1]
}
#end of hammingCodeFunction
`` |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg a; initial a = 1'b1;
reg b_fc; initial b_fc = 1'b0;
reg b_pc; initial b_pc = 1'b0;
reg b_oh; initial b_oh = 1'b0;
reg b_oc; initial b_oc = 1'b0;
wire a_l = ~a;
wire b_oc_l = ~b_oc;
// Note we must insure that full, parallel, etc, only fire during
// edges (not mid-cycle), and must provide a way to turn them off.
// SystemVerilog provides: $asserton and $assertoff.
// verilator lint_off CASEINCOMPLETE
always @* begin
// Note not all tools support directives on casez's
case ({a,b_fc}) // synopsys full_case
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
priority case ({a,b_fc})
2'b0_0: ;
2'b0_1: ;
2'b1_0: ;
// Note no default
endcase
end
always @* begin
case (1'b1) // synopsys full_case parallel_case
a: ;
b_pc: ;
endcase
end
`ifdef NOT_YET_VERILATOR // Unsupported
// ambit synthesis one_hot "a, b_oh"
// cadence one_cold "a_l, b_oc_l"
`endif
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==2) begin
a <= 1'b0;
b_fc <= 1'b1;
b_pc <= 1'b1;
b_oh <= 1'b1;
b_oc <= 1'b1;
end
if (cyc==3) begin
a <= 1'b1;
b_fc <= 1'b0;
b_pc <= 1'b0;
b_oh <= 1'b0;
b_oc <= 1'b0;
end
if (cyc==4) begin
`ifdef FAILING_FULL
b_fc <= 1'b1;
`endif
`ifdef FAILING_PARALLEL
b_pc <= 1'b1;
`endif
`ifdef FAILING_OH
b_oh <= 1'b1;
`endif
`ifdef FAILING_OC
b_oc <= 1'b1;
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//PROYECTO ELECTRICO
//Autor : Jose Johel Rodriguez Pineda
//DbC maquina de estados
//
`include "Defintions.v"
//`timescale 1ns / 1ps
//------------------------------------------------
module DbCPortStatMachine
(
input wire clock ,
input wire DCI ,
input wire CSC ,
input wire PLC ,
input wire PRC ,
input wire DCE ,
input wire PED ,
input wire CEC ,
input wire Reset_rcvd,
input wire set_config_succesful,
input wire EnumError,
input wire Deconfigure
);
reg [4:0] rstate;
reg [4:0] rNew_state;
always @ (posedge clock)
begin : FSM_SEQ
if (DCE == 1'b0) begin
rstate = #1 `DBC_OFF;
end else begin
rstate = #1 rNew_state;
end
end
always @ (posedge clock)
begin
if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else
case(rstate)
`DBC_OFF : if (DCE == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else begin
rNew_state = `DBC_OFF;
end
`DBC_DISCONNECTED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_DISCONNECTED;
end
`DBC_DISABLED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_DISABLED;
end
`DBC_ENABLED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (CEC == 1'b1 || PLC == 1'b1) begin
rNew_state = `DBC_DISABLED;
end else if (EnumError == 1'b1) begin
rNew_state = `DBC_ERROR;
end else if (Reset_rcvd == 1'b1) begin
rNew_state = `DBC_RESETTING;
end else if (set_config_succesful == 1'b1) begin
rNew_state = `DBC_CONFIURED;
end else begin
rNew_state = `DBC_ENABLED;
end
`DBC_RESETTING : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (PRC == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_OFF;
end
`DBC_ERROR : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (Reset_rcvd == 1'b1) begin
rNew_state = `DBC_RESETTING;
end else begin
rNew_state = `DBC_ERROR;
end
`DBC_CONFIURED : if (DCE == 1'b0) begin
rNew_state = `DBC_OFF;
end else if (CSC == 1'b1) begin
rNew_state = `DBC_DISCONNECTED;
end else if (PED == 1'b0) begin
rNew_state = `DBC_DISABLED;
end else if (Reset_rcvd == 1'b1) begin
rNew_state = `DBC_RESETTING;
end else if (Deconfigure == 1'b1) begin
rNew_state = `DBC_ENABLED;
end else begin
rNew_state = `DBC_CONFIURED;
end
default : rNew_state = `DBC_OFF;
endcase
end
endmodule
/*`define DBC_DISABLED 5'b11000
`define DBC_OFF 5'b00000
`define DBC_DISCONNECTED 5'b10000
`define DBC_ERROR 5'b11000
`define DBC_RESETTING 5'b11010
`define DBC_CONFIURED 5'b11101
*/ |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
// Graphics mux part (CT0) was written by Kyuusaku
`timescale 1ns/1ns
module neo_zmc2(
input CLK_12M,
input EVEN,
input LOAD,
input H,
input [31:0] CR,
output [3:0] GAD, GBD,
output DOTA, DOTB
// Not used here
/*input SDRD0,
input [1:0] SDA_L,
input [15:8] SDA_U,
output [21:11] MA*/
);
// Not used here
//zmc2_zmc ZMC2ZMC(SDRD0, SDA_L, SDA_U, MA);
zmc2_dot ZMC2DOT(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, DOTA, DOTB);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; string In; vector<char> Que; cin >> n >> t >> In; for (char x : In) { Que.push_back(x); } for (int i = 0; i < t; i++) { for (int x = 0; x < n; x++) { if (Que[x] == B && Que[x + 1] == G ) { Que[x] = G ; Que[x + 1] = B ; x++; } } } for (char x : Que) { cout << x; } return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int mod = (int)1e+9 + 7; const double pi = acos(-1.); const int maxn = 1000100; long long a[maxn]; int main() { { srand(time(0)); const string file = ; if (!file.empty()) { freopen((file + .in ).c_str(), r , stdin); freopen((file + .out ).c_str(), w , stdout); } } int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); } long long ans = 0, pref = 0; for (int i = 0; i < n; i++) { ans += pref * (min(a[i], i ? a[i - 1] : mod) - 1) + a[i] - 1; ans %= mod; long long h = min(i ? a[i - 1] : mod, i + 1 == n ? mod : a[i + 1]); h = min(h, a[i]); h--; pref *= h; pref += min(a[i], i + 1 < n ? a[i + 1] : mod) - 1; pref %= mod; } printf( %lld , ans); return (0); } |
#include <bits/stdc++.h> using namespace std; const int SIZE = 1e2 + 5; int main() { int n, m, c; string s[SIZE], extract, f; c = 0, f = acef ; cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { extract.push_back(s[i][j]); extract.push_back(s[i + 1][j]); extract.push_back(s[i][j + 1]); extract.push_back(s[i + 1][j + 1]); sort(extract.begin(), extract.end()); if (extract == f) c++; extract.clear(); } } cout << c << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXM = 100100; const int MAXN = 500; const int INF = (1 << 30); char s[100100]; struct Edge { int next, from, to, cap, cost; }; struct MCMF { Edge edge[MAXM]; int head[MAXN], countedge; void Init(int N) { this->N = N; memset(head, -1, sizeof(head)); countedge = 0; } int N; int inq[MAXN], dis[MAXN], pre[MAXN], ad[MAXN]; void AddEdge(const int& start, const int& end, const int& cap, const int& cost) { edge[countedge].to = end; edge[countedge].from = start; edge[countedge].next = head[start]; edge[countedge].cap = cap; edge[countedge].cost = cost; head[start] = countedge++; edge[countedge].to = start; edge[countedge].from = end; edge[countedge].next = head[end]; edge[countedge].cap = 0; edge[countedge].cost = -cost; head[end] = countedge++; } bool BF(int s, int t, int& flow, int& cost) { int i; for (i = 0; i < N; i++) dis[i] = INF; memset(inq, 0, sizeof(inq)); dis[s] = 0; inq[s] = 1; pre[s] = -1; ad[s] = INF; queue<int> que; que.push(s); int u, v, temp; while (!que.empty()) { u = que.front(); que.pop(); inq[u] = 0; for (temp = head[u]; temp != -1; temp = edge[temp].next) { v = edge[temp].to; if (edge[temp].cap && dis[v] > dis[u] + edge[temp].cost) { dis[v] = dis[u] + edge[temp].cost; pre[v] = temp; ad[v] = min(ad[u], edge[temp].cap); if (!inq[v]) { inq[v] = 1; que.push(v); } } } } if (dis[t] == INF) return false; flow += ad[t]; cost += dis[t] * ad[t]; u = t; while (u != s) { edge[pre[u]].cap -= ad[t]; edge[pre[u] ^ 1].cap += ad[t]; u = edge[pre[u]].from; } return true; } pair<int, int> MinC(int s, int t) { pair<int, int> ret; while (BF(s, t, ret.first, ret.second)) ; return ret; } } f; int cc[30]; int main() { scanf( %s , s); int limit = strlen(s); int n; scanf( %d , &n); f.Init(n + 26 + 2); int ss = 0, tt = n + 26 + 1; for (int i = 0; s[i]; i++) { cc[s[i] - a ]++; } for (int i = 0; i < 26; i++) { f.AddEdge(i + 1 + n, tt, cc[i], 0); } for (int i = 0; i < n; i++) { scanf( %s , &s); memset(cc, 0, sizeof(cc)); for (int j = 0; s[j]; j++) { cc[s[j] - a ]++; } for (int j = 0; j < 26; j++) { f.AddEdge(i + 1, j + 1 + n, cc[j], i + 1); } int x; scanf( %d , &x); f.AddEdge(ss, i + 1, x, 0); } pair<int, int> ans = f.MinC(ss, tt); if (ans.first < limit) ans.second = -1; printf( %d n , ans.second); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { double i, j, h, l, num; cin >> h >> l; num = (l * l - h * h) / (2 * h); cout << (fixed) << setprecision(12) << num; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if (a == b) cout << a << 0 << << b << 1 << endl; else if (a + 1 == b) { cout << a << 9 << << b << 0 << endl; } else if (a == 9 && b == 1) { cout << 9 10 << endl; } else { cout << -1; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long M = 1e9 + 7; const long long N = 1e6 + 7; long long a[N]; long long n; long long res = 0; long long par[N]; long long sz[N]; long long findpar(long long v) { if (par[v] == v) return v; return par[v] = findpar(par[v]); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; par[i] = i; sz[i] = 1; } vector<pair<long long, pair<long long, long long> > > vec; for (long long i = 1; i < n; i++) { long long v, u; cin >> v >> u; vec.push_back({max(a[v], a[u]), {v, u}}); } sort(vec.begin(), vec.end()); for (auto pr : vec) { long long x = pr.first; long long v = findpar(pr.second.first); long long u = findpar(pr.second.second); res += sz[v] * sz[u] * x; par[v] = u; sz[u] += sz[v]; } for (long long i = 0; i < vec.size(); i++) vec[i].first = -1 * (min(a[vec[i].second.first], a[vec[i].second.second])); sort(vec.begin(), vec.end()); for (long long i = 1; i <= n; i++) { par[i] = i; sz[i] = 1; } for (auto pr : vec) { long long x = pr.first; long long v = findpar(pr.second.first); long long u = findpar(pr.second.second); res += sz[v] * sz[u] * x; par[v] = u; sz[u] += sz[v]; } cout << res; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_2_V
`define SKY130_FD_SC_LP__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_2_V
|
module rmii
(
input wire reset,
// PHY Interface
input wire phy_ref_clk,
output reg [1:0] phy_txd,
output wire phy_tx_en,
input wire [1:0] phy_rxd,
input wire phy_rx_er,
input wire phy_crs_dv,
// MAC Interface
input wire mac_tx_er,
input wire [7:0] mac_txd,
input wire mac_tx_en,
output wire mac_tx_clk,
output wire mac_col,
output reg [7:0] mac_rxd,
output wire mac_rx_er,
output wire mac_rx_clk,
output wire mac_crs,
output wire mac_rx_dv
);
reg [1:0] tx_index;
reg [1:0] rx_index;
assign phy_tx_er = mac_tx_er;
assign phy_tx_en = mac_tx_en;
assign mac_col = phy_crs_dv & mac_tx_en;
assign mac_rx_er = phy_rx_er;
assign mac_crs = phy_crs_dv;
assign mac_rx_dv = phy_crs_dv;
clock_divider #(.DIVIDER(4)) clk_div
(
.reset(reset),
.clock_in(phy_ref_clk),
.clock_out(mac_tx_clk)
);
assign mac_rx_clk = mac_tx_clk;
always @(posedge phy_ref_clk)
begin
if (reset)
begin
tx_index <= 0;
end
else if (mac_tx_en && tx_index < 3)
begin
tx_index <= tx_index + 1;
end
else
begin
tx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
phy_txd <= 0;
end
else
begin
phy_txd <= mac_txd[tx_index*2+:2];
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
rx_index <= 0;
end
else if (phy_crs_dv && rx_index < 3)
begin
rx_index <= rx_index + 1;
end
else
begin
rx_index <= 0;
end
end
always @(posedge phy_ref_clk)
begin
if (reset)
begin
mac_rxd <= 0;
end
else
begin
mac_rxd[rx_index*2+:2] <= phy_rxd;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND4B_PP_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_PP_SYMBOL_V
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; const int Max = 35010; const ll INF = 1e17 + 10; bool sw; ll dp[2][Max]; int A[Max]; int L , R , F; deque<int> dq[Max]; void moveto(int l , int r) { //cout << to << l << , << r << n ; while(L > l) { L--; if(dq[A[L]].size() > 0) F += dq[A[L]].front(); dq[A[L]].push_front(L); if(dq[A[L]].size() > 1) F -= dq[A[L]].front(); } while(R < r) { R++; if(dq[A[R]].size() > 0) F -= dq[A[R]].back(); dq[A[R]].push_back(R); if(dq[A[R]].size() > 1) F += dq[A[R]].back(); } while(R > r) { if(dq[A[R]].size() > 1) F -= dq[A[R]].back(); dq[A[R]].pop_back(); if(dq[A[R]].size() > 0) F += dq[A[R]].back(); R--; } while(L < l) { if(dq[A[L]].size() > 1) F += dq[A[L]].front(); dq[A[L]].pop_front(); if(dq[A[L]].size() > 0) F -= dq[A[L]].front(); L++; } } void solve(int l , int r , int tl , int tr) { if(r < l) return; int mid = (l + r) >> 1; int opt = -1; ll ans = INF; for(int i = min(tr , mid - 1) ; i >= tl ; i--) { //cout << res << i + 1 << , << mid << = ; moveto(i + 1 , mid); //cout << F << n ; ll nans = F + dp[!sw][i]; if(nans <= ans) opt = i , ans = nans; } dp[sw][mid] = ans; moveto(opt + 1 , mid); solve(l , mid - 1 , tl , opt); moveto(opt + 1 , mid); solve(mid + 1 , r , opt , tr); } int main() { int n , k; cin >> n >> k; for(int i = 1 ; i <= n ; i++) cin >> A[i]; //for(int i = 1 ; i <= n ; i++) dp[sw][i] = INF; L = 1 , R = 1 , F = 0 , dq[A[1]].push_back(1); for(int i = 1 ; i <= n ; i++) { moveto(1 , i); dp[sw][i] = F; } //cout << n ; for(int i = 1 ; i < k ; i++) { moveto(1 , n); sw = !sw; solve(1 , n , 0 , n - 1); //for(int i = 1 ; i <= n ; i++) cout << dp[sw][i] << ; cout << n ; } cout << dp[sw][n] << n ; } |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g_fifo
*/
module test_eth_mac_1g_fifo;
// Parameters
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg [7:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg rx_clk_enable = 1;
reg tx_clk_enable = 1;
reg rx_mii_select = 0;
reg tx_mii_select = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
rx_clk_enable,
tx_clk_enable,
rx_mii_select,
tx_mii_select,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_1g_fifo.lxt");
$dumpvars(0, test_eth_mac_1g_fifo);
end
eth_mac_1g_fifo #(
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.rx_clk_enable(rx_clk_enable),
.tx_clk_enable(tx_clk_enable),
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay)
);
endmodule
|
// file: dcm_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module dcm_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
dcm clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_switch
*/
module test_axis_switch_4x4;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT+1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_switch_4x4.lxt");
$dumpvars(0, test_axis_switch_4x4);
end
axis_switch #(
.M_COUNT(M_COUNT),
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool compare(const pair<long long, long long> &a, const pair<long long, long long> &b) { return a.second > b.second; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); long long i, j; string s; cin >> s; long long n = s.length(); long long f = 1; if (n < 4) { cout << 0; } else { long long sm = 0; long long fsm = 0; for (i = 0; i < n - 3; i++) { if (s[i] == b && s[i + 1] == e && s[i + 2] == a && s[i + 3] == r ) { sm = i + 1; } fsm += sm; } cout << fsm; } } |
// Problem: A. Puzzle From the Future // Contest: Codeforces - Codeforces Round #696 (Div. 2) // URL: https://codeforces.ml/contest/1474/problem/A // Memory Limit: 256 MB // Time Limit: 1000 ms // // Powered by CP Editor (https://cpeditor.org) #define _CRT_SECURE_NO_WARNINGS #include <bits/stdc++.h> using namespace std; typedef long long ll; #define forn(i,x,n) for(int i = x;i <= n;++i) const int N = 1e5+7; char s[N],ans[N]; int main() { int T;scanf( %d ,&T); while(T--) { int n;scanf( %d ,&n); scanf( %s ,s + 1); int last = -1; forn(i,1,n) { int c = s[i] - 0 ; if(c + 1 == last) ans[i] = 0 ,last = c; else ans[i] = 1 ,last = c + 1; } forn(i,1,n) printf( %c ,ans[i]); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int t; long long int a, b, n, S; int main() { cin >> t; while (t--) { cin >> a >> b >> n >> S; if (b >= S) { cout << YES << endl; continue; } if (a * n + b < S) { cout << NO << endl; continue; } long long int x = S / n; x = min(x, a); long long int res = (S - x * n); if (res <= b) { cout << YES << endl; continue; } if (res > b) { cout << NO << endl; continue; } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rstn, dval0, dval1, dbgsel_w
);
input clk;
input rstn;
input [7:0] dval0;
input [7:0] dval1;
input [7:0] dbgsel_w;
output [7:0] dout;
wire [7:0] dout = dout0 | dout1;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] dout0; // From sub0 of sub0.v
wire [7:0] dout1; // From sub1 of sub1.v
// End of automatics
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
reg [7:0] dbgsel_msk;
always_comb begin
reg [7:0] mask;
mask = 8'hff;
dbgsel_msk = (dbgsel_w & mask);
end
reg [7:0] dbgsel;
always @(posedge clk) begin
if ((rstn == 0)) begin
dbgsel <= 0;
end
else begin
dbgsel <= dbgsel_msk;
end
end
sub0 sub0 (/*AUTOINST*/
// Outputs
.dout0 (dout0[7:0]),
// Inputs
.rstn (rstn),
.clk (clk),
.dval1 (dval1[7:0]),
.dbgsel (dbgsel[7:0]));
sub1 sub1 (/*AUTOINST*/
// Outputs
.dout1 (dout1[7:0]),
// Inputs
.rstn (rstn),
.clk (clk),
.dval1 (dval1[7:0]),
.dbgsel (dbgsel[7:0]));
endmodule
module sub0
(
/*AUTOARG*/
// Outputs
dout0,
// Inputs
rstn, clk, dval1, dbgsel
);
input rstn;
input clk;
input [7:0] dval1;
input [7:0] dbgsel;
output reg [7:0] dout0;
reg [7:0] dbgsel_d1r;
always_comb begin
// verilator lint_off WIDTH
if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin
// verilator lint_on WIDTH
dout0 = dval1;
end
else begin
dout0 = 0;
end
end
always @(posedge clk) begin
if ((rstn == 0)) begin
dbgsel_d1r <= 0;
end
else begin
dbgsel_d1r <= dbgsel;
end
end
endmodule
module sub1
(
/*AUTOARG*/
// Outputs
dout1,
// Inputs
rstn, clk, dval1, dbgsel
);
input rstn;
input clk;
input [7:0] dval1;
input [7:0] dbgsel;
output reg [7:0] dout1;
reg [7:0] dbgsel_d1r;
always_comb begin
// verilator lint_off WIDTH
if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin
// verilator lint_on WIDTH
dout1 = dval1;
end
else begin
dout1 = 0;
end
end
always @(posedge clk) begin
if ((rstn == 0)) begin
dbgsel_d1r <= 0;
end
else begin
dbgsel_d1r <= dbgsel;
end
end
endmodule
|
/*
* Test case showing the failure of the 'less than or equal' operator (note
* that the 'greather than or equal' comparison also fails) on two signed
* values. The 'foo' module defines inputs 'a' and 'b' as signed inputs,
* then performs a LTE comparison of those two values in order to select the
* smaller of the two as the result (via a mux). The generated output for
* this test (via the display call) for icarus and a well known commercial
* Verilog simulator are shown here. It is my belief that the commercial
* simulator results reflect the correct behavior for a simulator.
* Specifically, with signed numbers the value 32'h7fffffff represents the
* maximum positive value while 32'h80000000 represents the minimum negative
* value. Thus for Less Than or Equal comparison any negative value (ie
* 32'h80000000) should evaluate to less than any positive value
* (ie 32'h7fffffff). Note the difference in the last 4 comparisons between
* the icarus results and the commercial results. The commercial results show
* that the 32'h8000000? values are less than the 32'h7ffffff? values as is
* expected.
*
* icarus commercial simulator
* 7ffffff5 7ffffffa = 7ffffff5 # 7ffffff5 7ffffffa = 7ffffff5
* 7ffffff6 7ffffffb = 7ffffff6 # 7ffffff6 7ffffffb = 7ffffff6
* 7ffffff7 7ffffffc = 7ffffff7 # 7ffffff7 7ffffffc = 7ffffff7
* 7ffffff8 7ffffffd = 7ffffff8 # 7ffffff8 7ffffffd = 7ffffff8
* 7ffffff9 7ffffffe = 7ffffff9 # 7ffffff9 7ffffffe = 7ffffff9
* 7ffffffa 7fffffff = 7ffffffa # 7ffffffa 7fffffff = 7ffffffa
* 7ffffffb 80000000 = 7ffffffb # 7ffffffb 80000000 = 80000000
* 7ffffffc 80000001 = 7ffffffc # 7ffffffc 80000001 = 80000001
* 7ffffffd 80000002 = 7ffffffd # 7ffffffd 80000002 = 80000002
* 7ffffffe 80000003 = 7ffffffe # 7ffffffe 80000003 = 80000003
*
* iverilog -version:
* Icarus Verilog version 0.7 ($Name: $)
*
* Compilation
* iverilog -o iverilog.out
* vvp iverilog.out
*/
module test ();
reg clk;
reg [31:0] a_dat;
reg [31:0] b_dat;
wire [31:0] result;
initial begin
clk <= 0;
a_dat <= 32'h7fffFFF5;
b_dat <= 32'h7fffFFFA;
#500 $finish;
end
always #25 clk <= ~clk;
always @(posedge clk)
begin
a_dat <= a_dat + 1;
b_dat <= b_dat + 1;
$display("%x %x = %x", a_dat, b_dat, result);
end
foo foo_test(.a(a_dat), .b(b_dat), .RESULT(result));
endmodule // test
module foo(a, b, RESULT);
input signed [31:0] a;
input signed [31:0] b;
output [31:0] RESULT;
wire lessThanEqualTo;
wire [31:0] mux;
assign lessThanEqualTo=a<=b;
assign mux=(lessThanEqualTo)?a:b;
assign RESULT=mux;
endmodule // foo
|
// debounce debounces signals to prevent oscillation by providing
// a hold time threshold such that if the signal oscillates too quickly
// it will get ignored, the signal has to be stable before the debouncer
// will allow it to transition to a new level
module debounce
(
input wire clk,
input wire sw,
output reg db_level,
output reg db_tick
);
localparam N = 21; // filter of 2^N * 20ns = 40ms
localparam ZERO = 0;
localparam WAIT1 = 1;
localparam ONE = 2;
localparam WAIT0 = 3;
reg [1:0] state_reg, state_next;
reg [N-1:0] q_reg, q_next;
always @ (posedge clk) begin
state_reg <= state_next;
q_reg <= q_next;
end
// state machine outputs level and edge trigger changes
// it outputs the same level as long as the input signal
// changes too quickly or not changing at all. If it changes
// to quickly, it will fail the threshold value for the counter
// and get resetted back to the original level state that it
// was in.
always @ (state_reg, q_reg, sw, q_next) begin
state_next <= state_reg;
q_next <= q_reg;
db_tick <= 0;
case (state_reg)
ZERO: begin
db_level <= 0;
if (sw) begin
state_next <= WAIT1;
q_next <= ~0;
end
end
WAIT1: begin
db_level <= 0;
if (sw) begin
q_next <= q_reg - 1;
if (q_next == 0) begin
state_next <= ONE;
db_tick <= 1;
end
end
else
state_next <= ZERO;
end
ONE: begin
db_level <= 1;
if (!sw) begin
state_next <= WAIT0;
q_next <= ~0;
end
end
WAIT0: begin
db_level <= 1;
if (!sw) begin
q_next <= q_reg - 1;
if (q_next == 0)
state_next <= ZERO;
end
else
state_next <= ONE;
end
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfstp (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int i, j, n, k, m, t, x = 0, y, c = 0, sum = 0, maxx, t1, t2, x1, x2, y1, y2, m1, m2; double ans1, ans2, ans = 1000000000000000000; cin >> t2 >> t1 >> x2 >> x1 >> t; if (t1 == t2 && t == t1) cout << x2 << << x1; else if (t >= t1) cout << 0 << x1; else if (t <= t2) cout << x2 << 0 ; else { for (i = 1; i < x1 + 1; i++) { y1 = i; y2 = min(y1 * (t1 - t) / (t - t2), x2); ans1 = (t1 * y1 + t2 * y2) * 1.0 / (y1 + y2); if (ans1 >= t && ((ans1 - t) <= ans || abs(ans1 - t - ans) <= 0.0000001)) { m1 = y1; m2 = y2; ans = ans1 - t; } if (y2 < x2) { y2++; ans2 = (t1 * y1 + t2 * y2) * 1.0 / (y1 + y2); if (ans2 >= t && ((ans2 - t) <= ans || abs(ans2 - t - ans) <= 0.0000001)) { m1 = y1; m2 = y2; ans = ans2 - t; } } } cout << m2 << << m1; } } |
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
// Major Functions: This function is used for configuring si570 register value via
// i2c_bus_controller .
//
//
// ============================================================================
// Design Description:
//
//
//
//
// ===========================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 11/09/30 :| Initial Version
// ============================================================================
`define REG_NUM 9
module i2c_reg_controller(
iCLK, // system clock 50mhz
iRST_n, // system reset
iENABLE, // i2c reg contorl enable signale , high for enable
iI2C_CONTROLLER_STATE, // i2c controller state , high for i2c controller state not in idel
iI2C_CONTROLLER_CONFIG_DONE,
oController_Ready,
iFREQ_MODE,
oSLAVE_ADDR,
oBYTE_ADDR,
oBYTE_DATA,
oWR_CMD, // write or read commnad for i2c controller , 1 for write command
oStart, // i2c controller start control signal, high for start to send signal
HS_DIV_reg,
N1_reg,
RFREG_reg,
oSI570_ONE_CLK_CONFIG_DONE,
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
parameter write_cmd = 1'b1;
parameter read_cmd = 1'b0;
//===========================================================================
// PORT declarations
//===========================================================================
input iCLK;
input iRST_n;
input iENABLE;
input iI2C_CONTROLLER_STATE;
input iI2C_CONTROLLER_CONFIG_DONE;
input [2:0] iFREQ_MODE;
output [6:0] oSLAVE_ADDR;
output [7:0] oBYTE_ADDR;
output [7:0] oBYTE_DATA ;
output oWR_CMD;
output oStart;
output oSI570_ONE_CLK_CONFIG_DONE;
output [2:0] HS_DIV_reg;
output [6:0] N1_reg;
output [37:0] RFREG_reg;
output oController_Ready;
//=============================================================================
// REG/WIRE declarations
//=============================================================================
wire [2:0] iFREQ_MODE;
reg [2:0] HS_DIV_reg;
reg [6:0] N1_reg;
reg [37:0] RFREG_reg;
////////////// write data ////
//wire [7:0] regx_data = 8'h01; // RECALL
wire [7:0] reg0_data = 8'h10; // free DCO
wire [7:0] reg1_data = {HS_DIV_reg,N1_reg[6:2]};
wire [7:0] reg2_data = {N1_reg[1:0],RFREG_reg[37:32]};
wire [7:0] reg3_data = RFREG_reg[31:24];
wire [7:0] reg4_data = RFREG_reg[23:16];
wire [7:0] reg5_data = RFREG_reg[15:8];
wire [7:0] reg6_data = RFREG_reg[7:0];
wire [7:0] reg7_data = 8'h00; // unfree DCO
wire [7:0] reg8_data = 8'h40; //New Freq
////////////// ctrl addr ////
//wire [7:0] byte_addrx = 8'd135;
wire [7:0] byte_addr0 = 8'd137;
wire [7:0] byte_addr1 = 8'd7;
wire [7:0] byte_addr2 = 8'd8;
wire [7:0] byte_addr3 = 8'd9;
wire [7:0] byte_addr4 = 8'd10;
wire [7:0] byte_addr5 = 8'd11;
wire [7:0] byte_addr6 = 8'd12;
wire [7:0] byte_addr7 = 8'd137;
wire [7:0] byte_addr8 = 8'd135;
wire [6:0] slave_addr = 0;
reg [`REG_NUM/2:0] i2c_reg_state;
wire [6:0] oSLAVE_ADDR = i2c_ctrl_data[23:17];
wire [7:0] oBYTE_ADDR = i2c_ctrl_data[16:9];
wire [7:0] oBYTE_DATA = i2c_ctrl_data[8:1];
wire oWR_CMD = i2c_ctrl_data[0];
wire oStart = access_next_i2c_reg_cmd;
wire i2c_controller_config_done;
reg [23:0] i2c_ctrl_data;// slave_addr(7bit) + byte_addr(8bit) + byte_data(8bit)+ wr_cmd (1bit) = 24bit
wire access_next_i2c_reg_cmd ;
wire access_i2c_reg_start;
wire oSI570_ONE_CLK_CONFIG_DONE;
reg oController_Ready;
//=============================================================================
// Structural coding
//=============================================================================
//=====================================
// Write & Read reg flow control
//=====================================
always@(iFREQ_MODE or HS_DIV_reg or N1_reg or RFREG_reg)
begin
case (iFREQ_MODE)
0: //100Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000101;
RFREG_reg <= 38'h2F40135A9;
end
1: //125Mhz
begin
HS_DIV_reg <= 3'b111;
N1_reg <= 7'b0000011;
RFREG_reg <= 38'h302013B65;
end
2: //156.25Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000011;
RFREG_reg <= 38'h313814290;
end
3: //250Mhz
begin
HS_DIV_reg <= 3'b111;
N1_reg <= 7'b0000001;
RFREG_reg <= 38'h302013B65;
end
4: //312.5Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000001;
RFREG_reg <= 38'h313814290;
end
5: //322.265625Mhz
begin
HS_DIV_reg <= 3'b000;
N1_reg <= 7'b000011;
RFREG_reg <= 38'h2D1E127AF;
end
6: //644.53125Mhz
begin
HS_DIV_reg <= 3'b000;
N1_reg <= 7'b000001;
RFREG_reg <= 38'h2D1E127AF;
end
7: //100Mhz
begin
HS_DIV_reg <= 3'b101;
N1_reg <= 7'b0000101;
RFREG_reg <= 38'h2F40135A9;
end
endcase
end
//=====================================
// State control
//=====================================
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
i2c_reg_state <= 0;
end
else
begin
if (access_i2c_reg_start)
i2c_reg_state <= 1'b1;
else if (i2c_controller_config_done)
i2c_reg_state <= i2c_reg_state+1;
else if (i2c_reg_state == (`REG_NUM+1))
i2c_reg_state <= 0;
end
end
//=====================================
// i2c bus address & data control
//=====================================
always@(i2c_reg_state or i2c_ctrl_data)
begin
i2c_ctrl_data = 0;
case (i2c_reg_state)
0: i2c_ctrl_data = 0; // don't forget to change REG_NUM value
1: i2c_ctrl_data = {slave_addr,byte_addr0,reg0_data,write_cmd};
2: i2c_ctrl_data = {slave_addr,byte_addr1,reg1_data,write_cmd};
3: i2c_ctrl_data = {slave_addr,byte_addr2,reg2_data,write_cmd};
4: i2c_ctrl_data = {slave_addr,byte_addr3,reg3_data,write_cmd};
5: i2c_ctrl_data = {slave_addr,byte_addr4,reg4_data,write_cmd};
6: i2c_ctrl_data = {slave_addr,byte_addr5,reg5_data,write_cmd};
7: i2c_ctrl_data = {slave_addr,byte_addr6,reg6_data,write_cmd};
8: i2c_ctrl_data = {slave_addr,byte_addr7,reg7_data,write_cmd};
9: i2c_ctrl_data = {slave_addr,byte_addr8,reg8_data,write_cmd};
// 10: i2c_ctrl_data = {slave_addr,byte_addr8,reg8_data,write_cmd};
endcase
end
edge_detector u1(
.iCLK(iCLK),
.iRST_n(iRST_n),
.iTrigger_in(iI2C_CONTROLLER_CONFIG_DONE),
.oFalling_edge(i2c_controller_config_done),
.oRising_edge()
);
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oController_Ready <= 1'b1;
end
else if (i2c_reg_state == `REG_NUM+1)
begin
oController_Ready <= 1'b1;
end
else if (i2c_reg_state >0)
begin
oController_Ready <= 1'b0;
end
end
assign oSI570_ONE_CLK_CONFIG_DONE = ((i2c_reg_state == `REG_NUM) &&(i2c_controller_config_done)) ? 1'b1 : 1'b0;
assign access_next_i2c_reg_cmd = ((iI2C_CONTROLLER_STATE == 1'b0)&&(i2c_reg_state <= `REG_NUM)&&(i2c_reg_state >0)) ? 1'b1 : 1'b0;
assign access_i2c_reg_start = ((iENABLE == 1'b1)&&(iI2C_CONTROLLER_STATE == 1'b0)) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool SR(int &x) { return scanf( %d , &x) == 1; } bool SR(long long &x) { return scanf( %lld , &x) == 1; } bool SR(double &x) { return scanf( %lf , &x) == 1; } bool SR(char *s) { return scanf( %s , s) == 1; } bool RI() { return true; } template <typename I, typename... T> bool RI(I &x, T &...tail) { return SR(x) && RI(tail...); } void SP(const int x) { printf( %d , x); } void SP(const long long x) { printf( %lld , x); } void SP(const double x) { printf( %.16lf , x); } void SP(const char *s) { printf( %s , s); } void PL() { puts( ); } template <typename I, typename... T> void PL(const I x, const T... tail) { SP(x); if (sizeof...(tail)) putchar( ); PL(tail...); } const int maxn = 3e5 + 5; int n, m, k; vector<int> edge[maxn]; vector<int> vol; int src, tar; void read() { RI(n, m, k); vol.resize(k); for (int i = 0; i < int(k); i++) RI(vol[i]); for (int i = (1); i <= int(m); i++) { int a, b; RI(a, b); edge[a].push_back(n + i); edge[n + i].push_back(a); edge[b].push_back(n + i); edge[n + i].push_back(b); } RI(src, tar); } struct Dsu { int par[maxn]; void init() { for (int i = (1); i <= int(n); i++) par[i] = i; } int find(int x) { return x == par[x] ? x : par[x] = find(par[x]); } void merge(int a, int b) { par[find(a)] = find(b); } } dsu; void build() { n += m; dsu.init(); if (find((vol).begin(), (vol).end(), tar) == vol.end()) vol.push_back(tar), k++; } bitset<maxn> vis; void sol() { vector<int> prv, cur; cur = vol; for (int ans = (1); ans <= int(maxn); ans++) { prv.swap(cur); cur.clear(); for (auto u : prv) if (!vis[u]) { vis[u] = 1; for (auto v : edge[u]) dsu.merge(u, v); cur.insert(cur.end(), (edge[u]).begin(), (edge[u]).end()); } if (dsu.find(src) == dsu.find(tar)) { PL(ans); return; } } PL(-1); } int main() { read(); build(); sol(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000010; char kol[6]; set<vector<int> > zb; bool used[6]; int rozw[6]; int obr[][6] = {{1, 2, 3, 4, 5, 6}, {1, 5, 3, 6, 4, 2}, {1, 6, 3, 5, 2, 4}, {1, 4, 3, 2, 6, 5}, {2, 3, 4, 1, 5, 6}, {2, 6, 4, 5, 3, 1}, {2, 1, 4, 3, 6, 5}, {2, 5, 4, 6, 1, 3}, {3, 4, 1, 2, 5, 6}, {3, 6, 1, 5, 4, 2}, {3, 2, 1, 4, 6, 5}, {3, 5, 1, 6, 2, 4}, {4, 1, 2, 3, 5, 6}, {4, 6, 2, 5, 1, 3}, {4, 3, 2, 1, 6, 5}, {4, 5, 2, 6, 3, 1}, {5, 1, 6, 3, 2, 4}, {5, 4, 6, 2, 1, 3}, {5, 3, 6, 1, 4, 2}, {5, 2, 6, 4, 3, 1}, {6, 1, 5, 3, 4, 2}, {6, 2, 5, 4, 1, 3}, {6, 3, 5, 1, 2, 4}, {6, 4, 5, 2, 3, 1}}; void gogo(int kt) { if (kt == 6) { vector<int> pom[24]; for (int i = 0; i < (24); ++i) { for (int j = 0; j < (6); ++j) pom[i].push_back(rozw[obr[i][j] - 1]); } bool only = 1; for (int i = 0; i < (24); ++i) if (zb.find(pom[i]) != zb.end()) only = false; if (only) zb.insert(pom[0]); return; } for (int i = 0; i < (6); ++i) { if (!used[i]) { used[i] = true; rozw[kt] = kol[i]; gogo(kt + 1); used[i] = false; } } } int main() { scanf( %s , kol); for (int i = 0; i < (6); ++i) used[i] = 0; gogo(0); printf( %d n , zb.size()); } |
#include <bits/stdc++.h> using namespace std; char s[300005]; int ans[300005]; int main() { int n, m; while (cin >> n >> m) { int cnt = 0; for (int i = 1; i <= n; i++) cin >> s[i]; for (int i = 1; i < n; i++) if (s[i] == s[i + 1] && s[i] == . ) cnt++; for (int i = 0; i < m; i++) { int x; char y; cin >> x >> y; if (s[x] == . && s[x - 1] == . ) cnt--; if (s[x] == . && s[x + 1] == . ) cnt--; s[x] = y; if (s[x] == . && s[x - 1] == . ) cnt++; if (s[x] == . && s[x + 1] == . ) cnt++; ans[i] = cnt; } for (int i = 0; i < m; i++) cout << ans[i] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; s[0] = toupper(s[0]); cout << s; } |
#include <bits/stdc++.h> using namespace std; template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(long long &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const long long &x) { printf( %lld , x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.first); putchar( ); _W(x.second); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } int MOD = 1e9 + 7; void ADD(long long &x, long long v) { x = (x + v) % MOD; if (x < 0) x += MOD; } const int SIZE = 1e6 + 10; string s[SIZE]; int row[SIZE], col[SIZE]; int main() { int ___T; scanf( %d , &___T); for (int cs = 1; cs <= ___T; cs++) { int n, m; R(n, m); for (int i = 0; i < (n); ++i) row[i] = 0; for (int i = 0; i < (m); ++i) col[i] = 0; for (int i = 0; i < (n); ++i) { R(s[i]); for (int j = 0; j < (m); ++j) if (s[i][j] == * ) row[i]++, col[j]++; } int an = n + m; for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) { int me = row[i] + col[j] - (s[i][j] == * ); an = min(an, n + m - 1 - me); } W(an); } return 0; } |
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