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//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module key (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 1}{1'b0}},read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long fmm(long long a, long long b, long long m = 1000000007) { long long r = 0; a %= m; b %= m; while (b > 0) { if (b & 1) { r += a; r %= m; } a += a; a %= m; b >>= 1; } return r % m; } inline long long fme(long long a, long long b, long long m = 1000000007) { long long r = 1; a %= m; while (b > 0) { if (b & 1) { r *= a; r %= m; } a *= a; a %= m; b >>= 1; } return r % m; } inline long long sfme(long long a, long long b, long long m = 1000000007) { long long r = 1; a %= m; while (b > 0) { if (b & 1) r = fmm(r, a, m); a = fmm(a, a, m); b >>= 1; } return r % m; } std::vector<long long> primes; long long primsiz; std::vector<long long> fact; std::vector<long long> invfact; inline void sieve(long long n) { long long i, j; std::vector<bool> a(n); a[0] = true; a[1] = true; for (i = 2; i * i < n; ++i) { if (!a[i]) { for (j = i * i; j < n; j += i) { a[j] = true; } } } for (i = 2; i < n; ++i) if (!a[i]) primes.push_back(i); primsiz = primes.size(); } inline void sieve() { long long n = 1010000, i, j, k = 0; std::vector<bool> a(n); primes.resize(79252); a[0] = a[1] = true; for (i = 2; (j = (i << 1)) < n; ++i) a[j] = true; for (i = 3; i * i < n; i += 2) { if (!a[i]) { k = (i << 1); for (j = i * i; j < n; j += k) a[j] = true; } } k = 0; for (i = 2; i < n; ++i) if (!a[i]) primes[k++] = i; primsiz = k; } inline bool isPrimeSmall(unsigned long long n) { if (((!(n & 1)) && n != 2) || (n < 2) || (n % 3 == 0 && n != 3)) return false; for (unsigned long long k = 1; 36 * k * k - 12 * k < n; ++k) if ((n % (6 * k + 1) == 0) || (n % (6 * k - 1) == 0)) return false; return true; } bool _p(unsigned long long a, unsigned long long n) { unsigned long long t, u, i, p, c = 0; u = n / 2, t = 1; while (!(u & 1)) { u /= 2; ++t; } p = fme(a, u, n); for (i = 1; i <= t; ++i) { c = (p * p) % n; if ((c == 1) && (p != 1) && (p != n - 1)) return 1; p = c; } if (c != 1) return 1; return 0; } inline bool isPrime(unsigned long long n) { if (((!(n & 1)) && n != 2) || (n < 2) || (n % 3 == 0 && n != 3)) return 0; if (n < 1373653) { for (unsigned long long k = 1; (((36 * k * k) - (12 * k)) < n); ++k) if ((n % (6 * k + 1) == 0) || (n % (6 * k - 1) == 0)) return 0; return 1; } if (n < 9080191) { if (_p(31, n) || _p(73, n)) return 0; return 1; } if (_p(2, n) || _p(7, n) || _p(61, n)) return 0; return 1; } unsigned long long nCk(long long n, long long k, unsigned long long m = 1000000007) { if (k < 0 || k > n || n < 0) return 0; if (k == 0 || k == n) return 1; if (fact.size() >= (unsigned long long)n && isPrime(m)) { return (((fact[n] * invfact[k]) % m) * invfact[n - k]) % m; } unsigned long long i = 0, j = 0, a = 1; k = ((k) < (n - k) ? (k) : (n - k)); for (; i < (unsigned long long)k; ++i) { a = (a * (n - i)) % m; while (j < (unsigned long long)k && (a % (j + 1) == 0)) { a = a / (j + 1); ++j; } } while (j < (unsigned long long)k) { a = a / (j + 1); ++j; } return a % m; } void nCkInit(unsigned long long m = 1000000007) { long long i, mx = 1010000; fact.resize(mx + 1); invfact.resize(mx + 1); fact[0] = 1; for (i = 1; i <= mx; ++i) { fact[i] = (i * fact[i - 1]) % m; } invfact[mx] = fme(fact[mx], m - 2, m); for (i = mx - 1; i >= 0; --i) { invfact[i] = (invfact[i + 1] * (i + 1)) % m; } } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } void extGCD(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1, y = 0; return; } long long x1, y1; extGCD(b, a % b, x1, y1); x = y1; y = x1 - (a / b) * y1; } inline void get(long long &x) { int n = 0; x = 0; char c = getchar_unlocked(); if (c == - ) n = 1; while (c < 0 || c > 9 ) { c = getchar_unlocked(); if (c == - ) n = 1; } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar_unlocked(); } if (n) x = -x; } inline int get(char *p) { char c = getchar_unlocked(); int i = 0; while (c != n && c != 0 && c != && c != r && c != EOF) { p[i++] = c; c = getchar_unlocked(); } p[i] = 0 ; return i; } inline void put(long long a) { int n = (a < 0 ? 1 : 0); if (n) a = -a; char b[20]; int i = 0; do { b[i++] = a % 10 + 0 ; a /= 10; } while (a); if (n) putchar_unlocked( - ); i--; while (i >= 0) putchar_unlocked(b[i--]); putchar_unlocked( ); } inline void putln(long long a) { int n = (a < 0 ? 1 : 0); if (n) a = -a; char b[20]; int i = 0; do { b[i++] = a % 10 + 0 ; a /= 10; } while (a); if (n) putchar_unlocked( - ); i--; while (i >= 0) putchar_unlocked(b[i--]); putchar_unlocked( n ); } const int K = 3; std::vector<std::vector<long long> > mul(std::vector<std::vector<long long> > a, std::vector<std::vector<long long> > b, unsigned long long m = 1000000007) { std::vector<std::vector<long long> > c(K, std::vector<long long>(K)); for (int ii = 0; ii < (K); ++ii) for (int jj = 0; jj < (K); ++jj) for (int kk = 0; kk < (K); ++kk) c[ii][jj] = (c[ii][jj] + a[ii][kk] * b[kk][jj]) % m; return c; } std::vector<std::vector<long long> > fme(std::vector<std::vector<long long> > a, unsigned long long n, unsigned long long m = 1000000007) { if (n == 1) return a; if (n & 1) return mul(a, fme(a, n - 1, m), m); std::vector<std::vector<long long> > x = fme(a, n / 2, m); return mul(x, x, m); } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); std::cout.tie(NULL); long long t = 0, n = 0, m = 0, maxx = 0, minn = 0, curr = 0, k = 0, num = 0, siz = 0, n1 = 0, n2 = 0, n3 = 0, n4 = 0, ind = 0; long long root = 0, sum = 0, diff = 0, q = 0, choice = 0, d = 0, len = 0, begg = 0, endd = 0, pos = 0, cnt = 0, lo = 0, hi = 0, mid = 0, ans = 0; bool flag = false; std::string s1, s2, s3, str; char ch, ch1, ch2, ch3, *ptr; double dub = 0; cin >> n1 >> n2; root = 1; while (1) { if (pos == 0) { if (n1 < root) break; n1 -= root; } else { if (n2 < root) break; n2 -= root; } ++root; pos = 1 - pos; } if (pos == 0) cout << Vladik ; else cout << Valera ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_1_V
`define SKY130_FD_SC_LS__SEDFXBP_1_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_1_V
|
// Lab 1A: ELEC 4440- Reconfigurable Computing: From Theory to Practice
// Department of ECE, Hong Kong University of Science & Technology
// Controlling the LEDs using DIP switches on
module control_LED
( input [7:0] input_value,
output [7:0] show_value
);
/*
// Task 1: Input -> Output
assign show_value = input_value;
*/
/*
// Task 2: 2-1 Mux
wire[2:0] mux1;
wire[2:0] mux2;
reg [2:0] mux_out;
wire control;
assign mux1 = input_value[2:0];
assign mux2 = input_value[5:3];
assign control = input_value[6];
assign show_value[2:0] = mux_out;
assign show_value[7:3] = 5'b00000;
always@*
case(control)
1'b0: mux_out <= mux1;
1'b1: mux_out <= mux2;
endcase
*/
///*
// Task 3: 3-8 Decoder
wire [2:0] control;
reg[7:0] dec;
assign control = input_value[2:0];
assign show_value = dec;
always@*
case (control)
3'b000 : dec <= 8'b00000001;
3'b001 : dec <= 8'b00000010;
3'b010 : dec <= 8'b00000100;
3'b011 : dec <= 8'b00001000;
3'b100 : dec <= 8'b00010000;
3'b101 : dec <= 8'b00100000;
3'b110 : dec <= 8'b01000000;
default : dec <= 8'b10000000;
endcase
//*/
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_TB_V
`define SKY130_FD_SC_HVL__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRTP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_BLACKBOX_V
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
//////////////////////////
// arithmetic //
//////////////////////////
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH: 0 ] CARRY;
assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
// Due to VPR limitations regarding IO connexion to carry chain,
// we generate the carry chain input signal using an intermediate adder
// since we can connect a & b from io pads, but not cin & cout
generate
adder intermediate_adder (
.cin ( ),
.cout (CARRY[0]),
.a (CI ),
.b (CI ),
.sumout ( )
);
adder first_adder (
.cin (CARRY[0]),
.cout (CARRY[1]),
.a (AA[0] ),
.b (BB[0] ),
.sumout (Y[0] )
);
endgenerate
genvar i;
generate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i] ),
.cout (CARRY[i+1]),
.a (AA[i] ),
.b (BB[i] ),
.sumout (Y[i] )
);
end endgenerate
assign X = AA ^ BB;
endmodule
|
module hexdisp(inword, outword);
// by teknohog 0 iki 8 fi
// Converts numbers into legible hexadecimals for a 7-segment display.
// The DE2-115 has 8 digits with no decimal points connected, so
// only 7 wires per digit. Treated as a single 56-bit word.
// Strangely, all these 56 LEDs are wired directly into the
// FPGA. The guys at Terasic must have had a great time routing all
// those wires. Maybe someone should tell them about this new thing
// called multiplexing, so we could get more general I/O pins, and
// maybe even decimal points :-/
// There is also the ergonomic point that these LEDs are much
// brighter than multiplexed ones. Of course, one could add some
// PWM here...
// Size of 7-seg display to use, also determines the input word
// size which must be 4 times this. No need to be a power of 2.
parameter HEX_DIGITS = 8;
parameter SEGS_PER_DIGIT = 7;
input [(HEX_DIGITS * 4 - 1):0] inword;
output [(HEX_DIGITS * SEGS_PER_DIGIT - 1):0] outword;
generate
genvar i;
for (i = 0; i < HEX_DIGITS; i = i + 1)
begin: for_digits
hexdigit7seg H(.nibble(inword[(4*i + 3):(4*i)]), .sseg(outword[(SEGS_PER_DIGIT*i + SEGS_PER_DIGIT - 1):(SEGS_PER_DIGIT*i)]));
end
endgenerate
endmodule // hex27seg
module hexdigit7seg(nibble, sseg);
input [3:0] nibble;
output [6:0] sseg;
reg [6:0] segment;
// DE2-115 needs inverted signals
assign sseg = ~segment;
always @(*)
case(nibble)
4'b0000: segment <= 7'b1111110;
4'b0001: segment <= 7'b0110000;
4'b0010: segment <= 7'b1101101;
4'b0011: segment <= 7'b1111001;
4'b0100: segment <= 7'b0110011;
4'b0101: segment <= 7'b1011011;
4'b0110: segment <= 7'b1011111;
4'b0111: segment <= 7'b1110000;
4'b1000: segment <= 7'b1111111;
4'b1001: segment <= 7'b1111011;
4'b1010: segment <= 7'b1110111;
4'b1011: segment <= 7'b0011111;
4'b1100: segment <= 7'b1001110;
4'b1101: segment <= 7'b0111101;
4'b1110: segment <= 7'b1001111;
4'b1111: segment <= 7'b1000111;
endcase
endmodule |
#include <bits/stdc++.h> const int Mod = (int)1e9 + 7; const int MX = 1073741822; const long long MXLL = 4611686018427387903; const int Sz = 2e5 + 1; using namespace std; inline void Read_rap() { ios_base ::sync_with_stdio(0); cin.tie(0); } int n; int a[Sz]; long long dp[Sz][20][2], lca[Sz][20][2], sum[Sz][20][2]; vector<int> g[Sz]; void dfs(int v, int pr) { for (int i = 0; i < 20; i++) dp[v][i][((a[v] & (1 << i)) > 0)]++; for (auto to : g[v]) { if (to != pr) { dfs(to, v); for (int i = 0; i < 20; i++) { for (int j = 0; j < 2; j++) { bool bit = (a[v] & (1 << i)) > 0; bool b = (j ^ bit); dp[v][i][b] += dp[to][i][j]; } } } } for (auto to : g[v]) { if (to != pr) { for (int i = 0; i < 20; i++) { for (int j = 0; j < 2; j++) { for (int k = 0; k < 2; k++) { bool bit = (a[v] & (1 << i)) > 0; bool b = (j ^ k ^ bit); lca[v][i][b] += sum[v][i][j] * dp[to][i][k]; } } for (int j = 0; j < 2; j++) sum[v][i][j] = sum[v][i][j] + dp[to][i][j]; } } } } int main() { Read_rap(); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs(1, 1); long long ans = 0; for (int i = 0; i < 20; i++) for (int v = 1; v <= n; v++) ans = (ans + (dp[v][i][1] + lca[v][i][1]) * (1ll << i)); cout << ans; return 0; } |
module mem_wait
(/*AUTOARG*/
// Outputs
mem_wait_arry,
// Inputs
clk, rst, lsu_valid, f_sgpr_lsu_instr_done, f_vgpr_lsu_wr_done,
lsu_wfid, f_sgpr_lsu_instr_done_wfid, f_vgpr_lsu_wr_done_wfid
);
input clk,rst;
input lsu_valid, f_sgpr_lsu_instr_done, f_vgpr_lsu_wr_done;
input [5:0] lsu_wfid, f_sgpr_lsu_instr_done_wfid, f_vgpr_lsu_wr_done_wfid;
output [`WF_PER_CU-1:0] mem_wait_arry;
wire [`WF_PER_CU-1:0] decoded_issue_value, decoded_sgpr_retire_value,
decoded_vgpr_retire_value,
mem_wait_reg_wr_en, mem_waiting_wf;
decoder_6b_40b_en issue_value_decoder
(
.addr_in(lsu_wfid),
.out(decoded_issue_value),
.en(lsu_valid)
);
decoder_6b_40b_en retire_sgpr_value_decoder
(
.addr_in(f_sgpr_lsu_instr_done_wfid),
.out(decoded_sgpr_retire_value),
.en(f_sgpr_lsu_instr_done)
);
decoder_6b_40b_en retire_vgpr_value_decoder
(
.addr_in(f_vgpr_lsu_wr_done_wfid),
.out(decoded_vgpr_retire_value),
.en(f_vgpr_lsu_wr_done)
);
dff_set_en_rst mem_wait[`WF_PER_CU-1:0]
(
.q(mem_waiting_wf),
.d(40'b0),
.en(mem_wait_reg_wr_en),
.clk(clk),
.set(decoded_issue_value),
.rst(rst)
);
assign mem_wait_reg_wr_en = decoded_vgpr_retire_value | decoded_sgpr_retire_value | decoded_issue_value;
assign mem_wait_arry = mem_waiting_wf;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ksm(long long a, long long b) { if (!b) return 1; long long ns = ksm(a, b >> 1); ns = ns * ns % 998244353; if (b & 1) ns = ns * a % 998244353; return ns; } int chk(int x1, int y1, int x2, int y2) { cout << ? << x1 << << y1 << << x2 << << y2 << endl; fflush(stdout); int r = 0; cin >> r; return r; } int a[55][55]; int main() { int n; cin >> n; a[1][1] = 1; for (int j = 3; j <= n; j++) if (chk(1, j - 2, 1, j)) a[1][j] = a[1][j - 2]; else a[1][j] = a[1][j - 2] ^ 1; for (int i = 2; i <= n; i++) for (int j = n; j >= 1; j--) { if (i == n && j == n) a[i][j] = 0; else { if (j >= 2) if (chk(i - 1, j - 1, i, j)) a[i][j] = a[i - 1][j - 1]; else a[i][j] = a[i - 1][j - 1] ^ 1; else if (chk(i, j, i, j + 2)) a[i][j] = a[i][j + 2]; else a[i][j] = a[i][j + 2] ^ 1; } } int ed = 0; for (int i = 1; i <= n; i += 2) { if (a[i][i] == 1 && a[i + 2][i + 2] == 0) { if (chk(i, i + 1, i + 2, i + 2)) ed = a[i][i + 1]; else if (chk(i, i, i + 1, i + 2)) ed = a[i + 1][i + 2] ^ 1; else { if (a[i][i + 1] == a[i + 1][i + 2]) ed = a[i][i + 1] ^ a[i][i + 2] ^ 1; else if (a[i][i + 2] == 0) ed = a[i + 1][i + 2]; else ed = a[i][i + 1] ^ 1; } break; } } cout << ! << endl; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if ((i + j) & 1) a[i][j] ^= ed; cout << a[i][j]; } cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_0_V
`define SKY130_FD_SC_LP__A41O_0_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_0 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_0 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_0_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 14150 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w255,
w8160,
w8159,
w64,
w8095,
w1020,
w7075,
w14150;
assign w1 = i_data0;
assign w1020 = w255 << 2;
assign w14150 = w7075 << 1;
assign w255 = w256 - w1;
assign w256 = w1 << 8;
assign w64 = w1 << 6;
assign w7075 = w8095 - w1020;
assign w8095 = w8159 - w64;
assign w8159 = w8160 - w1;
assign w8160 = w255 << 5;
assign o_data0 = w14150;
//multiplier_block area estimate = 7338.03819621765;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 50005; int n; int id[N]; vector<pair<int, int> > val; vector<int> sol; int main() { ios ::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { cin >> id[i]; } id[n] = id[0]; for (int i = 0; i < n; i++) { val.push_back(make_pair((n - id[i]) - id[i + 1], i)); } sort(val.begin(), val.end()); sol.resize(n); for (int i = 0; i < n; i++) { sol[val[i].second] = n - i - 1; } for (int i = 0; i < n; i++) { cout << sol[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e17; const long long maxn = 2e5 + 700; const int mod = 1e9 + 7; template <typename T> inline void read(T &a) { char c = getchar(); T x = 0, f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } a = f * x; } long long n, m, p; char s[maxn]; int a[maxn], b[maxn]; int digit(long long x, int *d) { int ans = 0; while (x) { d[++ans] = x % 10; x /= 10; } return ans; } int path[maxn]; int check(int pos, int lbound, int rbound) { if (!pos) return 1; if (!lbound && !rbound) return 1; int l = lbound ? a[pos] : 0; int r = rbound ? b[pos] : 9; for (int i = l; i <= r; i++) { if (path[i] > 0) { path[i]--; if (check(pos - 1, lbound && i == l, rbound && i == r)) { path[i]++; return 1; } path[i]++; } } return 0; } int pos, res = 0; void dfs(int u, int w) { if (u == 9) { path[u] = w; if (check(pos, 1, 1)) res++; return; } for (int i = 0; i <= w; i++) { path[u] = i; dfs(u + 1, w - i); } } int main() { read(n); read(m); digit(n, a); pos = digit(m, b); dfs(0, pos); printf( %d n , res); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); for (int z = 0; z < n; z++) { long long a, b, c; cin >> a >> b; while ((c = a | a + 1) <= b) a = (a | a + 1); cout << a << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_SYMBOL_V
`define SKY130_FD_SC_HS__A222OI_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_SYMBOL_V
|
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "gpio/gpio.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "fast_spi_rx/fast_spi_rx.v"
`include "fast_spi_rx/fast_spi_rx_core.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/CG_MOD_pos.v"
`include "utils/clock_divider.v"
`include "utils/RAMB16_S1_S9_sim.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam GPIO_BASEADDR = 32'h0000;
localparam GPIO_HIGHADDR = 32'h1000-1;
localparam SPI_BASEADDR = 32'h1000; //0x1000
localparam SPI_HIGHADDR = 32'h2000-1; //0x300f
localparam FAST_SR_AQ_BASEADDR = 32'h2000;
localparam FAST_SR_AQ_HIGHADDR = 32'h3000-1;
localparam PULSE_BASEADDR = 32'h3000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
// MODULES //
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO()
);
wire SPI_CLK;
wire EX_START_PULSE;
pulse_gen
#(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(SPI_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(SPI_CLK)
);
wire SCLK, SDI, SDO, SEN, SLD;
spi
#(
.BASEADDR(SPI_BASEADDR),
.HIGHADDR(SPI_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16)
) i_spi
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(SPI_CLK),
.EXT_START(EX_START_PULSE),
.SCLK(SCLK),
.SDI(SDI),
.SDO(SDO),
.SEN(SEN),
.SLD(SLD)
);
assign SDO = SDI;
wire FIFO_READ_SPI_RX;
wire FIFO_EMPTY_SPI_RX;
wire [31:0] FIFO_DATA_SPI_RX;
fast_spi_rx
#(
.BASEADDR(FAST_SR_AQ_BASEADDR),
.HIGHADDR(FAST_SR_AQ_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pixel_sr_fast_rx
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SCLK(~SPI_CLK),
.SDI(SDI),
.SEN(SEN),
.FIFO_READ(FIFO_READ_SPI_RX),
.FIFO_EMPTY(FIFO_EMPTY_SPI_RX),
.FIFO_DATA(FIFO_DATA_SPI_RX)
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_SPI_RX;
assign FIFO_EMPTY = FIFO_EMPTY_SPI_RX;
assign FIFO_READ_SPI_RX = FIFO_READ;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("spi.vcd");
$dumpvars(0);
end
endmodule
|
/*
* Copyright (c) 2005 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the bool type used as an index to a for loop, and in a
* few other minor cases.
*/
module main;
reg bool [31:0] idx;
reg logic [7:0] tmp;
initial begin
idx = 7;
tmp = 7;
$display("Dispay of 7s: %d, %d", idx, tmp);
for (idx = 0 ; idx < 17 ; idx = idx + 1) begin
tmp = idx[7:0];
if (tmp != idx[7:0]) begin
$display("FAILED -- %b != %b", tmp, idx[7:0]);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbp (
VPWR,
VGND,
Q ,
Q_N ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
reg notifier ;
wire buf_Q ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_4_V
`define SKY130_FD_SC_HD__DLXTN_4_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtn_4 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtn_4 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_BLACKBOX_V
`define SKY130_FD_SC_HD__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_BLACKBOX_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../lib/radar_config.vh"
module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
// Control and configuration outputs
output reset_o;
output tx_side_o;
output dbg_o;
output tx_strobe_o;
output tx_ctrl_o;
output rx_ctrl_o;
output [15:0] ampl_o;
output [31:0] fstart_o;
output [31:0] fincr_o;
output [15:0] pulse_num_o;
output io_tx_ena_o;
// Internal configuration
wire lp_ena;
wire md_ena;
wire dr_ena;
wire [1:0] chirps;
wire [15:0] t_on;
wire [15:0] t_sw;
wire [15:0] t_look;
wire [31:0] t_idle;
wire [31:0] atrdel;
// Configuration from host
wire [31:0] mode;
setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(mode));
assign reset_o = mode[0];
assign tx_side_o = mode[1];
assign lp_ena = mode[2];
assign md_ena = mode[3];
assign dr_ena = mode[4];
assign chirps = mode[6:5];
assign dbg_o = mode[7];
setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_on));
setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_sw));
setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_look));
setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_idle));
setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(ampl_o));
setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fstart_o));
setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fincr_o));
setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(atrdel));
// Pulse state machine
`define ST_ON 4'b0001
`define ST_SW 4'b0010
`define ST_LOOK 4'b0100
`define ST_IDLE 4'b1000
reg [3:0] state;
reg [31:0] count;
reg [15:0] pulse_num_o;
always @(posedge clk_i)
if (reset_o)
begin
state <= `ST_ON;
count <= 32'b0;
pulse_num_o <= 16'b0;
end
else
case (state)
`ST_ON:
if (count == {16'b0,t_on})
begin
state <= `ST_SW;
count <= 32'b0;
pulse_num_o <= pulse_num_o + 16'b1;
end
else
count <= count + 32'b1;
`ST_SW:
if (count == {16'b0,t_sw})
begin
state <= `ST_LOOK;
count <= 32'b0;
end
else
count <= count + 32'b1;
`ST_LOOK:
if (count == {16'b0,t_look})
begin
state <= `ST_IDLE;
count <= 32'b0;
end
else
count <= count + 32'b1;
`ST_IDLE:
if (count == t_idle)
begin
state <= `ST_ON;
count <= 32'b0;
end
else
count <= count + 32'b1;
default: // Invalid state, reset state machine
begin
state <= `ST_ON;
count <= 32'b0;
end
endcase
assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
assign tx_ctrl_o = (state == `ST_ON);
assign rx_ctrl_o = (state == `ST_LOOK);
// Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
.tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
.atr_tx_o(io_tx_ena_o));
endmodule // radar_control
|
#include <bits/stdc++.h> using namespace std; vector<long long int> v; int main() { long long int n, m, a, b, sum = 0, i, j, k; cin >> n >> k; long long int s[n], x[n]; for (i = 0; i < n; i++) { cin >> a >> b; sum += min(a, b); v.push_back(min(2 * a, b) - min(a, b)); } sort(v.begin(), v.end()); for (i = 0; i < n && i < k; i++) sum += v[n - i - 1]; cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; long long ar[100010]; unordered_map<long long, long long> um; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t, n, x, ans, y, prev; scanf( %lld , &t); long long sm = 0; while (t--) { scanf( %lld , &n); scanf( %lld , &x); for (int i = 0; i < n; i++) { scanf( %lld , &ar[i]); } sm = 0; prev = ans = -1; for (long long i = 0; i < n; i++) { sm = (sm + ar[i]) % x; if (sm && prev == -1) prev = i; if (sm) ans = i + 1; else if (prev != -1) ans = max(ans, i - prev); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000LL * 1000 * 1000 + 7; const int INF = 1000 * 1000 * 1000; const long long base = 1e18; const int MAXN = 600000; const double EPS = 1e-9; const double PI = acos(-1.); long long binPow(long long a, long long x) { long long res = 1; while (x) { if (x & 1) { res *= a; res %= MOD; } a *= a; a %= MOD; x /= 2; } return res; } long long dpT[200000][2]; long long n, m; long long a[200000]; long long b[200000]; long long dp(int pos, int more) { if (pos == n) { return more; } if (dpT[pos][more] != -1) return dpT[pos][more]; if (more == 1) { long long ans = dp(pos + 1, more); if (a[pos] == 0) { ans *= m; ans %= MOD; } if (b[pos] == 0) { ans *= m; ans %= MOD; } return dpT[pos][more] = ans; } if (a[pos] && b[pos] && a[pos] < b[pos]) return dpT[pos][more] = 0; if (a[pos] && b[pos] && a[pos] > b[pos]) return dpT[pos][more] = dp(pos + 1, 1); if (a[pos] && b[pos] && a[pos] == b[pos]) { return dpT[pos][more] = dp(pos + 1, 0); } if (a[pos] == 0 && b[pos]) { long long res = 0; res += (dp(pos + 1, 1) * (m - b[pos])) % MOD; res %= MOD; res += dp(pos + 1, 0); res %= MOD; return dpT[pos][more] = res; } if (a[pos] && b[pos] == 0) { long long res = 0; res += (dp(pos + 1, 1) * (a[pos] - 1)) % MOD; res %= MOD; res += dp(pos + 1, 0); res %= MOD; return dpT[pos][more] = res; } long long res = 0; long long cur = (m * (m - 1) / 2) % MOD; res += (dp(pos + 1, 1) * (cur)) % MOD; res %= MOD; res += (dp(pos + 1, 0) * m) % MOD; res %= MOD; return dpT[pos][more] = res; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; int cnt = 0; for (int i = (0); i < (n); ++i) { cin >> a[i]; if (!a[i]) cnt++; } for (int i = (0); i < (n); ++i) { cin >> b[i]; if (!b[i]) cnt++; } memset(dpT, -1, sizeof dpT); long long div = binPow(m, cnt); long long y = binPow(div, MOD - 2); cout << (dp(0, 0) * y) % MOD; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_cnt_lead0_lvl3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// 3rd level of lead 0 counters. Lead 0 count for 16 bits.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_cnt_lead0_lvl3 (
din_15_8_eq_0,
din_15_12_eq_0,
lead0_8b_1_hi,
lead0_8b_0_hi,
din_7_0_eq_0,
din_7_4_eq_0,
lead0_8b_1_lo,
lead0_8b_0_lo,
din_15_0_eq_0,
lead0_16b_2,
lead0_16b_1,
lead0_16b_0
);
input din_15_8_eq_0; // data in[15:8] is zero
input din_15_12_eq_0; // data in[15:12] is zero
input lead0_8b_1_hi; // bit[1] of lead 0 count- din[15:8]
input lead0_8b_0_hi; // bit[0] of lead 0 count- din[15:8]
input din_7_0_eq_0; // data in[7:0] is zero
input din_7_4_eq_0; // data in[7:4] is zero
input lead0_8b_1_lo; // bit[1] of lead 0 count- din[7:0]
input lead0_8b_0_lo; // bit[0] of lead 0 count- din[7:0]
output din_15_0_eq_0; // data in[15:0] is zero
output lead0_16b_2; // bit[2] of lead 0 count
output lead0_16b_1; // bit[1] of lead 0 count
output lead0_16b_0; // bit[0] of lead 0 count
wire din_15_0_eq_0;
wire lead0_16b_2;
wire lead0_16b_1;
wire lead0_16b_0;
assign din_15_0_eq_0= din_7_0_eq_0 && din_15_8_eq_0;
assign lead0_16b_2= ((!din_15_8_eq_0) && din_15_12_eq_0)
|| (din_15_8_eq_0 && din_7_4_eq_0);
assign lead0_16b_1= ((!din_15_8_eq_0) && lead0_8b_1_hi)
|| (din_15_8_eq_0 && lead0_8b_1_lo);
assign lead0_16b_0= ((!din_15_8_eq_0) && lead0_8b_0_hi)
|| (din_15_8_eq_0 && lead0_8b_0_lo);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_BEHAVIORAL_PP_V |
//------------------------------------------------------------------------------
// Title : CDC Sync Block
// Project : Tri-Mode Ethernet MAC
//------------------------------------------------------------------------------
// File : sync_block.vhd
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// Description: Used on signals crossing from one clock domain to
// another, this is a flip-flop pair, with both flops
// placed together with RLOCs into the same slice. Thus
// the routing delay between the two is minimum to safe-
// guard against metastability issues.
// -----------------------------------------------------------------------------
// (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
`timescale 1ps / 1ps
module sync_block #(
parameter INITIALISE = 2'b00
)
(
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync1;
wire data_sync2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0" *)
FD #(
.INIT (INITIALISE[0])
) data_sync (
.C (clk),
.D (data_in),
.Q (data_sync1)
);
(* RLOC = "X0Y0" *)
FD #(
.INIT (INITIALISE[1])
) data_sync_reg (
.C (clk),
.D (data_sync1),
.Q (data_sync2)
);
assign data_out = data_sync2;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> adj[101]; int vis[101][101]; int id; bool dfs(const int &idx, int cur, int to) { if (cur == to) return true; bool ret = false; for (int i = 0; i < (int)adj[idx][cur].size(); i++) { if (vis[idx][adj[idx][cur][i]] == id) continue; vis[idx][adj[idx][cur][i]] = id; ret |= dfs(idx, adj[idx][cur][i], to); } return ret; } int main() { int n, m, q; scanf( %d%d , &n, &m); for (int i = 0; i < 101; i++) adj[i].resize(n); for (int i = 0, u, v, c; i < m; i++) { scanf( %d%d%d , &u, &v, &c); adj[c - 1][u - 1].push_back(v - 1); adj[c - 1][v - 1].push_back(u - 1); } int u, v; scanf( %d , &q); while (q--) { id++; scanf( %d%d , &u, &v); int ans = 0; for (int i = 0; i < m; i++) ans += dfs(i, u - 1, v - 1); printf( %d n , ans); } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void checkmin(T &a, const T &b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, const T &b) { if (b > a) a = b; } const int maxn = 1e3 + 10; const int inf = 1e9 + 10; const long long mod = 1e9 + 7; int dp[maxn][maxn][4], g[maxn]; int n, k; long long fac[maxn], c[maxn][maxn]; int main() { scanf( %d%d , &n, &k); dp[0][0][2] = 1; for (int i = 0; i < n; i++) for (int j = 0; j <= n; j++) for (int mask = 0; mask < 4; mask++) { if (dp[i][j][mask] == 0) continue; int mask2 = (mask & 1) << 1; dp[i + 1][j][mask2] += dp[i][j][mask]; dp[i + 1][j][mask2] %= mod; if (!((mask >> 1) & 1)) dp[i + 1][j + 1][mask2] += dp[i][j][mask], dp[i + 1][j + 1][mask2] %= mod; if (i == n - 1) continue; mask2 |= 1; dp[i + 1][j + 1][mask2] += dp[i][j][mask]; dp[i + 1][j + 1][mask2] %= mod; } fac[0] = 1; for (long long i = 1; i < maxn; i++) fac[i] = fac[i - 1] * i % mod; for (int i = k; i <= n; i++) { long long now = 0; for (int mask = 0; mask < 4; mask++) now += dp[n][i][mask], now %= mod; g[i] = now * fac[n - i] % mod; } c[0][0] = 1; for (int i = 1; i < maxn; i++) { c[i][0] = 1; for (int j = 1; j <= i; j++) c[i][j] = (c[i - 1][j - 1] + c[i - 1][j]) % mod; } long long ans = 0; for (int i = k; i <= n; i++) { if ((i - k) & 1) ans -= c[i][k] * g[i] % mod, ans += mod; else ans += c[i][k] * g[i] % mod; ans %= mod; } printf( %d n , ans); return 0; } |
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_byte #(parameter `BSG_INV_PARAM(els_p)
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter `BSG_INV_PARAM(data_width_p )
,parameter latch_last_read_p=0
,parameter write_mask_width_lp = data_width_p>>3
,parameter enable_clock_gating_p=0
)
( input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [`BSG_SAFE_MINUS(data_width_p, 1):0] data_i
// for each bit set in the mask, a byte is written
,input [`BSG_SAFE_MINUS(write_mask_width_lp, 1):0] write_mask_i
,output logic [`BSG_SAFE_MINUS(data_width_p, 1):0] data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_1rw_sync_mask_write_byte_synth
#(.els_p(els_p), .data_width_p(data_width_p), .latch_last_read_p(latch_last_read_p))
synth
(.clk_i(clk_lo)
,.reset_i
,.v_i
,.w_i
,.addr_i
,.data_i
,.write_mask_i
,.data_o
);
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## %L: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T x) { return x * x; } const int maxn = 3 * (int)1e5 + 5; int n; int a[maxn]; int p[maxn]; int main() { srand(time(NULL)); ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; p[a[i]] = i; } int q; cin >> q; while (q--) { int tst, x, y; cin >> tst >> x >> y; if (tst == 2) { swap(a[x], a[y]); p[a[x]] = x; p[a[y]] = y; } else { int ans = 1; int last = -1; for (int i = x; i <= y; ++i) { if (p[i] < last) ++ans; last = p[i]; } cout << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; bool vis[10005][10005], rev[10005]; struct E { int nxt, to; } e[MAXN]; int tot, head[MAXN]; inline void add(int x, int y) { e[++tot] = (E){head[x], y}; head[x] = tot; } int opt[MAXN], X[MAXN], Y[MAXN], s[MAXN], m, n, q; long long ans[MAXN]; void dfs(int x, int sum) { int tmp = 0, i = x; if (opt[i] == 1) { if (vis[X[i]][Y[i]] == rev[X[i]]) tmp = 1, ++sum, ++s[X[i]], vis[X[i]][Y[i]] = !rev[X[i]]; } if (opt[i] == 2) { if (vis[X[i]][Y[i]] != rev[X[i]]) tmp = 1, --sum, --s[X[i]], vis[X[i]][Y[i]] = rev[X[i]]; } if (opt[i] == 3) { sum += m - s[X[i]] - s[X[i]]; rev[X[i]] ^= 1; s[X[i]] = m - s[X[i]]; } ans[i] = sum; for (int i = head[x]; i; i = e[i].nxt) dfs(e[i].to, sum); if (opt[x] == 1 && tmp) --sum, --s[X[i]], vis[X[i]][Y[i]] = rev[X[i]]; if (opt[x] == 2 && tmp) ++sum, ++s[X[i]], vis[X[i]][Y[i]] = !rev[X[i]]; if (opt[x] == 3) sum -= m - s[X[i]] - s[X[i]], rev[X[i]] ^= 1, s[X[i]] = m - s[X[i]]; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= q; ++i) { scanf( %d%d , &opt[i], &X[i]); if (opt[i] < 3) scanf( %d , &Y[i]); if (opt[i] == 4) add(X[i], i); else add(i - 1, i); } dfs(0, 0); for (int i = 1; i <= q; ++i) printf( %lld n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 250005; int qr[maxn], qp[maxn], wm[maxn], loc[maxn]; int pp[maxn], pr[maxn], pm[maxn]; long long pd[maxn]; stack<int> f[maxn]; bool used[maxn]; int n, nx, ny, totm; long long dist(int x, int y) { return (long long)x * x + (long long)y * y; }; bool cmp(int a, int b) { return pd[a] > pd[b]; }; int main() { int i, x, y, h, t; long long d; scanf( %d%d%d%d%d , &nx, &ny, qp + 1, qr + 1, &n); for (i = 1; i <= n; ++i) { scanf( %d%d%d%d%d , &x, &y, pm + i, pp + i, pr + i); pd[i] = dist(x - nx, y - ny); wm[i - 1] = pm[i]; loc[i] = i; } sort(wm, wm + n); totm = unique(wm, wm + n) - wm; for (i = 1; i <= n; ++i) pm[i] = lower_bound(wm, wm + totm, pm[i]) - wm + 1; sort(loc + 1, loc + n + 1, cmp); for (i = 1; i <= n; ++i) for (x = pm[loc[i]]; x <= totm; x += x & -x) f[x].push(loc[i]); for (h = 1, t = 1; h <= t; ++h) { x = upper_bound(wm, wm + totm, qp[h]) - wm; d = (long long)qr[h] * qr[h]; for (; x > 0; x -= x & -x) while (!f[x].empty() && pd[f[x].top()] <= d) { y = f[x].top(); f[x].pop(); if (!used[y]) { used[y] = true; ++t; qp[t] = pp[y]; qr[t] = pr[y]; } } } printf( %d n , t - 1); return 0; } |
/*
* Text mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/*
* Pipeline description
* h_count[2:0]
* 000
* 001 col_addr, row_addr
* 010 ver_addr, hor_addr
* 011 csr_adr_o
* 100 csr_adr_i
* 101 sram_addr_
* 110 csr_dat_o
* 111 char_data_out, attr_data_out
* 000 vga_shift
* 001 vga_blue_o <= vga_shift[7]
*/
module vga_text_mode (
input clk,
input rst,
// CSR slave interface for reading
output reg [16:1] csr_adr_o,
input [15:0] csr_dat_i,
output csr_stb_o,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
// CRTC
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
output reg [3:0] attr,
output horiz_sync_o
);
// Registers and nets
reg [ 6:0] col_addr;
reg [ 4:0] row_addr;
reg [ 6:0] hor_addr;
reg [ 6:0] ver_addr;
wire [10:0] vga_addr;
wire [11:0] char_addr;
wire [ 7:0] char_data_out;
reg [ 7:0] attr_data_out;
reg [ 7:0] char_addr_in;
reg [7:0] pipe;
wire load_shift;
reg [9:0] video_on_h;
reg [9:0] horiz_sync;
wire fg_or_bg;
wire brown_bg;
wire brown_fg;
reg [ 7:0] vga_shift;
reg [ 3:0] fg_colour;
reg [ 2:0] bg_colour;
reg [22:0] blink_count;
// Cursor
reg cursor_on_v;
reg cursor_on_h;
reg cursor_on;
wire cursor_on1;
// Module instances
vga_char_rom char_rom (
.clk (clk),
.addr (char_addr),
.q (char_data_out)
);
// Continuous assignments
assign vga_addr = { 4'b0, hor_addr } + { ver_addr, 4'b0 };
assign char_addr = { char_addr_in, v_count[3:0] };
assign load_shift = pipe[7];
assign video_on_h_o = video_on_h[9];
assign horiz_sync_o = horiz_sync[9];
assign csr_stb_o = pipe[2];
assign fg_or_bg = vga_shift[7] ^ cursor_on;
assign cursor_on1 = cursor_on_h && cursor_on_v;
// Behaviour
// Address generation
always @(posedge clk)
if (rst)
begin
col_addr <= 7'h0;
row_addr <= 5'h0;
ver_addr <= 7'h0;
hor_addr <= 7'h0;
csr_adr_o <= 16'h0;
end
else
begin
// h_count[2:0] == 001
col_addr <= h_count[9:3];
row_addr <= v_count[8:4];
// h_count[2:0] == 010
ver_addr <= { 2'b00, row_addr } + { row_addr, 2'b00 };
// ver_addr = row_addr x 5
hor_addr <= col_addr;
// h_count[2:0] == 011
// vga_addr = row_addr * 80 + hor_addr
csr_adr_o <= { 5'h0, vga_addr };
end
// cursor
always @(posedge clk)
if (rst)
begin
cursor_on_v <= 1'b0;
cursor_on_h <= 1'b0;
end
else
begin
cursor_on_h <= (h_count[9:3] == hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == vcursor[4:0])
&& ({2'b00, v_count[3:0]} >= cur_start)
&& ({2'b00, v_count[3:0]} <= cur_end);
end
// Pipeline count
always @(posedge clk)
pipe <= rst ? 8'b0 : { pipe[6:0], (h_count[2:0]==3'b0) };
// attr_data_out
always @(posedge clk) attr_data_out <= pipe[5] ? csr_dat_i[15:8]
: attr_data_out;
// char_addr_in
always @(posedge clk) char_addr_in <= pipe[5] ? csr_dat_i[7:0]
: char_addr_in;
// video_on_h
always @(posedge clk)
video_on_h <= rst ? 10'b0 : { video_on_h[8:0], video_on_h_i };
// horiz_sync
always @(posedge clk)
horiz_sync <= rst ? 10'b0 : { horiz_sync[8:0], horiz_sync_i };
// blink_count
always @(posedge clk)
blink_count <= rst ? 23'h0 : (blink_count + 23'h1);
// Video shift register
always @(posedge clk)
if (rst)
begin
fg_colour <= 4'b0;
bg_colour <= 3'b0;
vga_shift <= 8'h0;
end
else
if (load_shift)
begin
fg_colour <= attr_data_out[3:0];
bg_colour <= attr_data_out[6:4];
cursor_on <= (cursor_on1 | attr_data_out[7]) & blink_count[22];
vga_shift <= char_data_out;
end
else vga_shift <= { vga_shift[6:0], 1'b0 };
// pixel attribute
always @(posedge clk)
if (rst) attr <= 4'h0;
else attr <= fg_or_bg ? fg_colour : { 1'b0, bg_colour };
endmodule
|
#include <bits/stdc++.h> using namespace std; int a; char c[100009]; unsigned int dp[200009] = {1}; int main() { scanf( %d%s , &a, c); for (int i = a; i >= 1; i--) { c[i] = c[i - 1]; } if (a & 1) { cout << 0; } else { int e = a >> 1; int q = 0; for (int i = 1; i <= a; i++) { if (c[i] == ? ) { for (int j = (i >> 1); j >= i - e && j > 0; j--) { dp[j] += dp[j - 1]; } } else { q++; } } unsigned int ans = dp[e]; for (int i = 1; i <= e - q; i++) { ans *= 25; } cout << ans; } return 0; } |
#include <bits/stdc++.h> int n, i, j, k, t, len; char st[200]; int main() { scanf( %d , &n); while (n--) { scanf( %s , st); len = strlen(st); t = 8; for (i = 0; i < len; i++) if (st[i] != : ) { t--; while (i < len && st[i] != : ) i++; } j = 0; for (i = 0; i < len; i++) { if (st[i] == : ) { if (j != i) { if (j != 0) printf( : ); for (k = 0; k < 4 - i + j; k++) printf( 0 ); for (k = j; k < i; k++) printf( %c , st[k]); } if (st[i + 1] == : ) { if (j == i) printf( 0000 ); else printf( :0000 ); for (k = 1; k < t; k++) printf( :0000 ); i++; } j = i + 1; } } if (st[len - 1] != : ) { printf( : ); for (k = 0; k < 4 - i + j; k++) printf( 0 ); for (k = j; k < i; k++) printf( %c , st[k]); } printf( n ); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:10:52 08/30/2014
// Design Name:
// Module Name: lab4dpath
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab4dpath(x1,x2,x3,y,clk);
input [9:0] x1,x2,x3;
input clk;
output [9:0] y;
//mult12x12 input (a,b[11:0] output (p[23:0])
wire [11:0] s1, s2, v1, v2, v3, p1, p2, p3;
wire [23:0] t1, t2, t3;
//ff before mult logic
//dff io ports
reg [9:0] d1, d2, d3, q1, q2, q3;
//input dff
always @(posedge clk) begin
d1 <= x1;
d2 <= x2;
d3 <= x3;
end
//wait in dff for one clock cycle
//output dff
always @(posedge clk) begin
q1 <= d1;
q2 <= d2;
q3 <= d3;
end
assign v1 = {q1, 2'b00};
assign v2 = {q2, 2'b00};
assign v3 = {q3, 2'b00};
//end ff before mult logic
mult12x12l3 i1 (.clk(clk), .a(12'b110000000000), .b(v1), .p(t1));
mult12x12l3 i2 (.clk(clk), .a(12'b010100000000), .b(v2), .p(t2));
mult12x12l3 i3 (.clk(clk), .a(12'b110000000000), .b(v3), .p(t3));
//pipeline for add logic
reg [11:0] qa1, qa2;
assign s1 = t2[22:11] + t3[22:11];
//dff
always @(posedge clk) begin
qa1 <= t1[22:11];
qa2 <= s1;
end
//end pipeline before add logic
assign s2 = qa1 + qa2;
//assign y to upper bits of s2
assign y = s2[11:2];
endmodule |
#include <bits/stdc++.h> int main(int argc, char *argv[]) { std::string s; int n; std::cin >> n >> s; int con = 0; int ans = 0; for (int i = 0; i < s.length();) { while (s[i] == x ) { con++; i++; } if (s[i] != x ) { if (con >= 3) { ans += con - 2; } con = 0; i++; } } if (con >= 3) { ans += con - 2; } std::cout << ans; } |
#include <bits/stdc++.h> using namespace std; struct str { long long cnt[26], len = 0; pair<long long, long long> pref = {0, 0}, suf = {0, 0}; str() { memset(cnt, 0, sizeof(cnt)); } str(string s) { memset(cnt, 0, sizeof(cnt)); len = ((int)s.size()); pair<long long, long long> mx = {0, 0}; for (int i = 0; i < ((int)s.size()); ++i) { if (s[i] - a != mx.first) mx = {s[i] - a , 1}; else mx.second++; cnt[mx.first] = max(cnt[mx.first], mx.second); } mx = {s[0] - a , 0}; for (int i = 0; i < ((int)s.size()); ++i) { if (s[i] - a == mx.first) mx.second++; else break; } pref = mx; mx = {s[((int)s.size()) - 1] - a , 0}; for (int i = ((int)s.size()) - 1; i >= 0; --i) { if (s[i] - a == mx.first) mx.second++; else break; } suf = mx; } }; int n; void debug(str x) { cerr << x.len << = << x.len << endl; cerr << x.pref.first << = << x.pref.first << endl; cerr << x.pref.second << = << x.pref.second << endl; cerr << x.suf.first << = << x.suf.first << endl; cerr << x.suf.second << = << x.suf.second << endl; for (int i = 0; i < 26; ++i) cout << x.cnt[i] << ; cout << n n ; } str merge(str A, str B) { str ret = str(); ret.pref = B.pref; ret.suf = B.suf; if (A.len + B.len > 1e9) ret.len = -1; else ret.len = A.len * B.len + A.len + B.len; if (A.pref.second == A.len && B.pref.second == B.len) { if (A.pref.first == B.pref.first) { ret.pref = ret.suf = {A.pref.first, ret.len}; ret.cnt[A.pref.first] = ret.len; } else { ret.cnt[A.pref.first] = 1; ret.cnt[B.pref.first] = B.pref.second; } } else { for (int i = 0; i < 26; ++i) { ret.cnt[i] = B.cnt[i]; if (A.cnt[i]) ret.cnt[i] = max(ret.cnt[i], 1LL); if (B.pref.second == B.len && i == B.pref.first && A.cnt[i] > 0) { ret.cnt[i] = max(ret.cnt[i], B.len * A.cnt[i] + A.cnt[i] + B.len); if (A.pref.first == B.pref.first) ret.pref = {A.pref.first, B.len * A.pref.second + A.pref.second + B.len}; if (A.suf.first == B.pref.first) ret.suf = {A.suf.first, B.len * A.suf.second + A.suf.second + B.len}; } else { if (i == B.pref.first) ret.cnt[i] = max(ret.cnt[i], B.pref.second + (A.cnt[i] > 0)); if (i == B.suf.first) ret.cnt[i] = max(ret.cnt[i], B.suf.second + (A.cnt[i] > 0)); if (B.pref.first == B.suf.first && B.pref.first == i && A.cnt[i] > 0) ret.cnt[i] = max(ret.cnt[i], B.pref.second + B.suf.second + 1); } if (ret.cnt[i] > 1e9) ret.cnt[i] = 1; } } return ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; string s; cin >> s; str sol = str(s); for (int i = 0; i < n - 1; ++i) { cin >> s; str x = str(s); sol = merge(sol, x); } long long pr = 0; for (int i = 0; i < 26; ++i) pr = max(pr, sol.cnt[i]); cout << pr; } |
module mips (clk, rst, rf_addr, mem_addr, rf_data, mem_data, cpu_pc, cpu_inst, cop_addr, cop_data, hi_data, lo_data);
input clk;
input rst;
//display data
input [ 4:0] rf_addr;
input [31:0] mem_addr;
output [31:0] rf_data;
output [31:0] mem_data;
output [31:0] cpu_pc;
output [31:0] cpu_inst;
input [ 4:0] cop_addr;
output [31:0] cop_data;
output [31:0] hi_data;
output [31:0] lo_data;
assign cpu_pc = pc_cur; //display pc
assign cpu_inst = ins;
// Wires.
wire [31:0] pc_next;
wire [31:0] pc_cur;
wire [31:0] ins;
wire [31:0] ext_imm;
wire [31:0] routa;
wire [31:0] routb;
wire [31:0] rin;
wire [31:0] aluSrcA_mux_out;
wire [31:0] aluSrcB_mux_out;
wire [31:0] alu_out;
wire [31:0] return_addr;
wire [31:0] dm_out;
wire [4:0] rWin;
wire [31:0] cop_out;
wire [31:0] npc_out;
wire [31:0] expiaddr;
wire [31:0] jiaddr;
// Control signals.
wire [3:0] aluCtr;
wire compare;
wire branch;
wire jump;
wire [1:0] regDst;
wire [1:0] aluSrcA;
wire [1:0] aluSrcB;
wire [1:0] regWr;
wire [1:0] memWr;
wire [1:0] immExt;
wire [1:0] memtoReg;
wire [1:0] copWr;
wire [1:0] byteExt;
wire [1:0] iaddrtoNPC;
wire [4:0] manInput_raddr;
wire [31:0] manInput_shf;
pc pc(
.clk(clk),
.rst(rst),
.niaddr(pc_next),
.iaddr(pc_cur)
);
npc npc(
.iaddr(pc_cur),
.branch(branch),
.jump(jump),
.ins(ins),
.jiaddr(jiaddr),
.imm16(ins[15:0]),
.imm26(ins[25:0]),
.riaddr(npc_out),
.niaddr(pc_next)
);
im_4k im(
.iaddr(pc_cur[11:2]),
.ins(ins)
);
ext immExt_ext(
.din(ins[15:0]),
.extOp(immExt),
.dout(ext_imm)
);
mux #(32) aluSrcA_mux(
.a(routa),
.b({{27{1'b0}}, ins[10:6]}),// Shift.
.c(manInput_shf),
.ctrl_s(aluSrcA),
.dout(aluSrcA_mux_out)
);
mux #(32) aluSrcB_mux(
.a(routb),
.b(ext_imm),
.ctrl_s(aluSrcB),
.dout(aluSrcB_mux_out)
);
mux #(5) regDst_mux(
.a(ins[20:16]),// rt.
.b(ins[15:11]),// rd.
.c(manInput_raddr),
.ctrl_s(regDst),
.dout(rWin)
);
regFile rf(
.busW(rin),
.clk(clk),
.wE(regWr),
.rW(rWin),
.rA(ins[25:21]),
.rB(ins[20:16]),
.busA(routa),
.busB(routb),
//display rf
.test_addr(rf_addr),
.test_data(rf_data),
.rst(rst)
);
alu alu(
.ALUop(aluCtr),
.a(aluSrcA_mux_out),
.b(aluSrcB_mux_out),
.result(alu_out),
.clk(clk),
.hi_data(hi_data),
.lo_data(lo_data)
);
dm_4k dm(
.addr(alu_out[11:0]),
.din(routb),
.byteExt(byteExt),
.wEn(memWr),
.clk(clk),
.dout(dm_out),
//display mem
.test_addr(mem_addr[4:0]),
.test_data(mem_data),
.rst(rst)
);
mux #(32) memtoReg_mux(
.a(alu_out),
.b(dm_out),
.c(cop_out),
.d(npc_out),
.ctrl_s(memtoReg),
.dout(rin)
);
ctrl ctrl(
.ins(ins),
.compare(compare),
.jump(jump),
.regDst(regDst),
.aluSrcA(aluSrcA),
.aluSrcB(aluSrcB),
.aluCtr(aluCtr),
.regWr(regWr),
.memWr(memWr),
.immExt(immExt),
.memtoReg(memtoReg),
.copWr(copWr),
.byteExt(byteExt),
.manInput_raddr(manInput_raddr),
.manInput_shf(manInput_shf),
.iaddrtoNPC(iaddrtoNPC)
);
comp comp(
.dinA(aluSrcA_mux_out),
.dinB(aluSrcB_mux_out),
.ins(ins),
.compare(compare),
.branch(branch)
);
CoProcessor0RF CoP0(
.clk(clk),
.din(aluSrcB_mux_out),
.wEn(copWr),
.regNum(ins[15:11]),
.sel(ins[2:0]),
.dout(cop_out),
.npc_out(npc_out),
.expiaddr(expiaddr),
.ins(ins),
//display COP0 rf data.
.cop_addr(cop_addr),
.cop_data(cop_data)
);
mux #(32) iaddrtoNPC_mux(
.a(aluSrcA_mux_out),
.b(expiaddr),
.ctrl_s(iaddrtoNPC),
.dout(jiaddr)
);
endmodule // MIPS main program;
|
#include <bits/stdc++.h> using namespace std; int n, m, d[100005], sd[100005][3], f[2 * 100005]; int Find(int x) { return f[x] == x ? x : f[x] = Find(f[x]); } void link(int a, int b) { int x = Find(a), y = Find(b); if (x != y) f[x] = y; } int main(void) { cin >> n >> m; for (int i = 0; i < n; ++i) cin >> d[i]; for (int i = 0; i < m; ++i) { int x; cin >> x; for (int j = 0; j < x; ++j) { int dr; cin >> dr; dr--; sd[dr][++sd[dr][0]] = i; } } for (int i = 0; i < 2 * m; ++i) f[i] = i; for (int i = 0; i < n; ++i) { if (d[i]) link(sd[i][1], sd[i][2]), link(sd[i][1] + m, sd[i][2] + m); else link(sd[i][1], sd[i][2] + m), link(sd[i][1] + m, sd[i][2]); } for (int i = 0; i < m; ++i) if (Find(i) == Find(i + m)) { cout << NO ; return 0; } cout << YES ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFRTP_PP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_PP_SYMBOL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosII_system_nios2_qsys_0_jtag_debug_module_tck the_niosII_system_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosII_system_nios2_qsys_0_jtag_debug_module_sysclk the_niosII_system_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosII_system_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// niosII_system_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_4_V
`define SKY130_FD_SC_HS__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 300; const long long mod = 1e9 + 7; long long dp[N][N], mi[N], mi_1[N], C[N][N], n, k; int main() { cin >> n >> k; for (int i = (0); i <= (n); i++) { C[i][0] = 1; for (int j = (1); j <= (i); j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } mi[0] = mi_1[0] = 1; for (int i = (1); i <= (n); i++) mi[i] = mi[i - 1] * k % mod, mi_1[i] = mi_1[i - 1] * (k - 1) % mod; for (int i = (1); i <= (n); i++) dp[1][i] = C[n][i] * mi_1[n - i] % mod; for (int i = (2); i <= (n); i++) for (int j = (0); j <= (n); j++) for (int s = (0); s <= (j); s++) { dp[i][j] = (dp[i][j] + dp[i - 1][s] * C[n - s][j - s] % mod * mi[s] % mod * mi_1[n - j] % mod) % mod; if (j == s) dp[i][j] = (dp[i][j] - mi_1[n] * dp[i - 1][s] % mod + mod) % mod; } cout << dp[n][n]; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream &operator>>(istream &is, vector<pair<T1, T2>> &v) { for (pair<T1, T2> &t : v) is >> t.first >> t.second; return is; } template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (T &t : v) is >> t; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (const T &t : v) { os << t << ; } os << n ; return os; } double pi = acos(-1.0); long long md = 1000000007; long long abst(long long a) { return a < 0 ? -a : a; } struct HASH { size_t operator()(const pair<long long, long long> &x) const { return (size_t)x.first * 37U + (size_t)x.second; } }; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; long long Pow(long long n, long long x) { long long ans = 1; while (x > 0) { if (x & 1) ans = (ans * n) % md; n = (n * n) % md; x = x >> 1; } return ans; } vector<long long> fact, inv; void inverse(long long n) { inv.resize(n + 1); inv[0] = 1; for (long long i = 1; i <= n; i++) inv[i] = Pow(fact[i], md - 2); } void factorial(long long n) { fact.resize(n + 1); fact[0] = 1; for (long long i = 1; i <= n; i++) fact[i] = (fact[i - 1] * i) % md; } long long max(long long a, long long b) { return a > b ? a : b; } long long min(long long a, long long b) { return a < b ? a : b; } void solve() { long long n; cin >> n; vector<long long> v(n); cin >> v; vector<long long> ans(2 * n); vector<long long> vis(2 * n + 1, -1); for (long long i = 0; i < n; i++) { ans[2 * i] = v[i]; vis[v[i]] = 1; } long long ptr; for (long long i = 1; i < 2 * n; i += 2) { ptr = -1; for (long long j = 1; j <= 2 * n; j++) if (vis[j] == -1 && j > ans[i - 1]) { ptr = j; break; } if (ptr == -1) { cout << -1 << n ; return; } ans[i] = ptr; vis[ptr] = 1; } cout << ans; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long t = 1; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; inline vector<int> prefix(string p) { vector<int> pi; int m = p.size(); for (int(i) = (0); (i) < (m); ++(i)) pi.push_back(-1); int k = -1; for (int(i) = (1); (i) < (m); ++(i)) { while (k != -1 && p[k + 1] != p[i]) k = pi[k]; if (p[k + 1] == p[i]) k++; pi[i] = k; } return pi; } set<int> s; inline void shift(string p) { vector<int> pi = prefix(p); int m = p.size(); int k = pi[m - 1]; while (k != -1) { s.insert(m - k); k = pi[k]; } } int main() { ios_base::sync_with_stdio(false); long long n, m; cin >> n >> m; string p; cin >> p; vector<int> pi = prefix(p); shift(p); vector<int> v; for (int(i) = (0); (i) < (m); ++(i)) { int a; cin >> a; v.push_back(a); } bool ok = true; for (int(i) = (1); (i) < (v.size()); ++(i)) { long long r = v[i], l = v[i - 1]; if (r < (l + p.size()) && s.find((r - l + 1)) == s.end()) { cout << 0 << endl; ok = false; break; } if ((p.size() + r - 1) > n && ok) { cout << 0 << endl; ok = false; break; } } long long first = n; if (ok) { v.push_back(2000000000); for (int(i) = (0); (i) < (v.size() - 1); ++(i)) first -= min((int)p.size(), v[i + 1] - v[i]); } long long ans = 1; if (first < 0 && ok) { cout << 0 << endl; ok = false; } for (int(i) = (0); (i) < (first); ++(i)) ans = (ans * (long long)26) % 1000000007; if (ok) cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapmet1 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct BIT { int N; vector<int> B; BIT(int n = 0) { N = n; B.resize(n + 2, 0); } void add(int x, int v) { x++; while (x <= N) { B[x] += v; x += x & -x; } } int sum(int x) { int s = 0; x++; while (x > 0) { s += B[x]; x -= x & -x; } return s; } int sum(int a, int b) { return sum(b) - sum(a - 1); } }; int main() { int h, m, n; scanf( %d%d%d , &h, &m, &n); long long sol = 0; map<int, pair<int, int> > pos; vector<BIT> X; vector<bool> visited(h, false); vector<int> ai(h), bi(h); for (int i = 0; i < h; ++i) { if (!visited[i]) { int cnt = 0; for (int j = i; !visited[j]; j = (j + m) % h) { visited[j] = true; ai[j] = X.size(); bi[j] = cnt; cnt++; } X.push_back(BIT(cnt)); } } for (int i = 0; i < n; ++i) { char op[8]; scanf( %s , op); int id, hs; if (op[0] == - ) { scanf( %d , &id); X[pos[id].first].add(pos[id].second, -1); } else { scanf( %d%d , &id, &hs); int xi = ai[hs], ti = bi[hs]; assert(X[xi].sum(0, X[xi].N - 1) < X[xi].N); if (X[xi].sum(ti, X[xi].N - 1) == X[xi].N - ti) { int lo = -1, hi = ti - 1; sol += X[xi].N - ti; while (hi - lo > 1) { int mid = (hi + lo) / 2; if (X[xi].sum(0, mid) == mid + 1) lo = mid; else hi = mid; } sol += hi; X[xi].add(hi, 1); pos[id] = make_pair(xi, hi); } else { int lo = ti - 1, hi = X[xi].N - 1; while (hi - lo > 1) { int mid = (hi + lo) / 2; if (X[xi].sum(ti, mid) == mid - ti + 1) lo = mid; else hi = mid; } sol += hi - ti; X[xi].add(hi, 1); pos[id] = make_pair(xi, hi); } } } printf( %I64d n , sol); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 7e4; const int INF = 1e9; struct d { int ad, xr; } a[N]; stack<int> s; vector<pair<int, int>> v; int n; int main() { ios::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n; int A, B; for (int i = 0; i < n; ++i) { cin >> A >> B; if (A == 0) continue; if (A == 1) s.push(i); a[i] = {A, B}; } while (!s.empty()) { int x = s.top(); s.pop(); if (a[x].ad == 1) { v.push_back({x, a[x].xr}); a[x].ad--; --a[a[x].xr].ad; a[a[x].xr].xr ^= x; if (a[a[x].xr].ad == 1) s.push(a[x].xr); } } cout << v.size() << n ; for (auto x : v) cout << x.first << << x.second << n ; } |
#include <bits/stdc++.h> long long int a[300000]; int main() { long long int n, i, hei, bai; while (scanf( %lld , &n) != EOF) { hei = bai = 0; for (i = 0; i < n; i++) { scanf( %lld , &a[i]); if (i % 2) { hei += (a[i] + 1) / 2; bai += a[i] / 2; } else { bai += (a[i] + 1) / 2; hei += a[i] / 2; } } printf( %lld n , bai < hei ? bai : hei); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; cout << (abs((b % n) + a + n) % n > 0 ? abs((b % n) + a + n) % n : n); } |
// Simple test of the SDRAM interface.
module SDRAM_test(
input wire clock,
input wire reset_n,
output reg [28:0] address,
output wire [7:0] burstcount,
input wire waitrequest,
input wire [63:0] readdata,
input wire readdatavalid,
output reg read,
output reg [63:0] writedata,
output wire [7:0] byteenable,
output reg write,
output wire [31:0] debug_value0,
output wire [31:0] debug_value1
);
// State machine.
localparam STATE_INIT = 4'h0;
localparam STATE_WRITE_START = 4'h1;
localparam STATE_WRITE_WAIT = 4'h2;
localparam STATE_READ_START = 4'h3;
localparam STATE_READ_WAIT = 4'h4;
localparam STATE_DONE = 4'h5;
reg [3:0] state;
// Registers and assignments.
assign burstcount = 8'h01;
assign byteenable = 8'hFF;
reg [63:0] data;
// 1G minus 128M, in 64-bit units:
localparam TEST_ADDRESS = 29'h0700_0000;
// Debug output.
assign debug_value0 = { 3'b0, waitrequest, 3'b0, readdatavalid, 3'b0, read, 3'b0, write, 12'b0, state };
assign debug_value1 = data[47:16];
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
state <= STATE_INIT;
address <= 29'h0;
read <= 1'b0;
writedata <= 64'h0;
write <= 1'b0;
end else begin
case (state)
STATE_INIT: begin
// Dummy state to start.
state <= STATE_WRITE_START;
data <= 64'h2357_1113_1719_2329;
end
STATE_WRITE_START: begin
// Initiate a write.
address <= TEST_ADDRESS;
writedata <= 64'hDEAD_BEEF_CAFE_BABE;
write <= 1;
state <= STATE_WRITE_WAIT;
end
STATE_WRITE_WAIT: begin
// Wait until we're not requested to wait.
if (!waitrequest) begin
address <= 29'h0;
writedata <= 64'h0;
write <= 1'b0;
state <= STATE_READ_START;
end
end
STATE_READ_START: begin
// Initiate a read.
address <= TEST_ADDRESS;
read <= 1'b1;
state <= STATE_READ_WAIT;
end
STATE_READ_WAIT: begin
// When no longer told to wait, deassert the request lines.
if (!waitrequest) begin
address <= 29'h0;
read <= 1'b0;
end
// If we have data, grab it and we're done.
if (readdatavalid) begin
data <= readdata;
state <= STATE_DONE;
end
end
STATE_DONE: begin
// Nothing, stay here.
end
default: begin
// Bug. Just restart.
state <= STATE_INIT;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, k, i; cin >> n >> k; string s[3]; cin >> s[0] >> s[1] >> s[2]; bool a[3][105]; while (s[0].size() <= n + 2) s[0] += . ; while (s[1].size() <= n + 2) s[1] += . ; while (s[2].size() <= n + 2) s[2] += . ; memset(a, 0, sizeof(a)); if (s[0][0] == s ) a[0][0] = true; else if (s[1][0] == s ) a[1][0] = true; else a[2][0] = true; for (i = 0; i < n; i++) { if (a[0][i]) { if (s[0][i + 1] == . ) { if (s[0][i + 3] == . && s[0][i + 2] == . ) a[0][i + 3] = true; if (s[1][i + 3] == . && s[1][i + 2] == . && s[1][i + 1] == . ) a[1][i + 3] = true; } } if (a[1][i]) { if (s[1][i + 1] == . ) { if (s[1][i + 3] == . && s[1][i + 2] == . ) a[1][i + 3] = true; if (s[0][i + 3] == . && s[0][i + 1] == . && s[0][i + 2] == . ) a[0][i + 3] = true; if (s[2][i + 3] == . && s[2][i + 1] == . && s[2][i + 2] == . ) a[2][i + 3] = true; } } if (a[2][i]) { if (s[2][i + 1] == . ) { if (s[2][i + 3] == . && s[2][i + 2] == . ) a[2][i + 3] = true; if (s[1][i + 3] == . && s[1][i + 2] == . && s[1][i + 1] == . ) a[1][i + 3] = true; } } } bool flag = false; if (a[0][n] || a[1][n] || a[2][n] || flag) flag = true; if (a[0][n + 1] || a[1][n + 1] || a[2][n + 1] || flag) flag = true; if (a[0][n - 1] || a[1][n - 1] || a[2][n - 1] || flag) cout << YES n ; else cout << NO n ; } } |
#include <bits/stdc++.h> using namespace std; double EPS = 1e-9; int N, K; double L, V1, V2; bool f(double t) { if (L / V1 < t - EPS) return true; int nGroups = N / K; if (N % K != 0) nGroups++; double distByBus = (t * V1 * V2 - L * V2) / (V1 - V2); double tByBus = distByBus / V2; double posBus = distByBus; double tElapsed = tByBus; nGroups--; while (nGroups > 0) { double posGroup = tElapsed * V1; if (posGroup > L - EPS) break; double tMeet = (posBus - posGroup) / (V1 + V2); double posMeet = posGroup + tMeet * V1; tElapsed += tMeet; if (L - posMeet < distByBus - EPS) { tElapsed += (L - posMeet) / V2; posBus = L; } else { tElapsed += tByBus; posBus = posMeet + distByBus; } nGroups--; } return tElapsed < t + EPS; } int main() { cin >> N >> L >> V1 >> V2 >> K; double lo = 0, hi = 1e9 + 5; int i = 0; while (hi - lo > EPS && i++ < 100) { double mid = (lo + hi) / 2; if (f(mid)) { hi = mid; } else lo = mid; } cout << fixed << setprecision(10) << hi << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t = 0, c = 0; char ch[105][105]; cin >> n; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) cin >> ch[i][j]; for (int i = 1; i <= n; i++) { c = 0; for (int j = 1; j <= n; j++) { if (ch[i][j] == C ) c++; } t += (c * (c - 1)) / 2; } for (int j = 1; j <= n; j++) { c = 0; for (int i = 1; i <= n; i++) { if (ch[i][j] == C ) c++; } t += (c * (c - 1)) / 2; } cout << t; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 5e2 + 5; vector<pair<int, int> > adj[MAX]; int dis[MAX][MAX], in[MAX][MAX]; int n, m; void dijkstra(int source) { memset(dis[source], 0x3F, sizeof dis[source]); dis[source][source] = 0; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > pq; pq.emplace(dis[source][source], source); while (!pq.empty()) { pair<int, int> cur = pq.top(); pq.pop(); int w, v; tie(w, v) = cur; if (w > dis[source][v]) { continue; } for (auto &each : adj[v]) { int vv, ww; tie(vv, ww) = each; if (dis[source][vv] > w + ww) { dis[source][vv] = w + ww; in[source][vv] = 1; pq.emplace(dis[source][vv], vv); } else if (dis[source][vv] == w + ww) { in[source][vv]++; } } } } int main() { scanf( %d %d , &n, &m); for (int i = int(0); i < int(m); i++) { int u, v, w; scanf( %d %d %d , &u, &v, &w); adj[u].emplace_back(v, w); adj[v].emplace_back(u, w); } for (int i = int(1); i < int(n + 1); i++) { dijkstra(i); } for (int i = int(1); i < int(n + 1); i++) { for (int j = int(i + 1); j < int(n + 1); j++) { int total = 0; for (int k = int(1); k < int(n + 1); k++) { if (dis[i][k] + dis[k][j] == dis[i][j]) { total += in[i][k]; } } printf( %d , total); } } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, m, k, i, j; cin >> n >> m >> k; long long int a[n]; vector<pair<long long int, long long int> > v; for (i = 0; i < n; i++) { cin >> a[i]; v.push_back(make_pair(a[i], i)); } long long int y = m * k; long long int x = n - y; sort(v.begin(), v.end()); long long int mark[n]; memset(mark, 0, sizeof(mark)); i = n - 1; while (i >= 0 && y > 0) { mark[v[i].second] = 1; i--; y--; } i = 0; long long int z; long long int ans = 0; vector<long long int> p; while (i < n) { z = 0; j = i; while (z < m && j < n) { if (mark[j] == 1) { z++; ans = ans + a[j]; } j++; } p.push_back(j); if (p.size() == k) break; i = j; } cout << ans << endl; for (i = 0; i < p.size() - 1; i++) { cout << p[i] << ; } return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_144x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_144x256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q);
input aclr;
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [143:0] q;
wire sub_wire0;
wire sub_wire1;
wire [143:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [143:0] q = sub_wire2[143:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "144"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL "data[143..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL "q[143..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a[1000000], n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int i = 1, j = n / 2 + 1; int ans = n; while (true) { if (i > n / 2) break; if (j > n) break; if (2 * a[i] <= a[j]) { i++; j++; ans--; } else j++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; long long n, l[MAXN], r[MAXN], vall[MAXN], valr[MAXN], pos[MAXN], d[MAXN], tree[4 * MAXN], ind[MAXN]; bool validl[MAXN], validr[MAXN], dead; pair<long long, long long> sortr[MAXN]; void computeleft() { l[0] = -1, r[0] = 1, r[n + 1] = -1, l[n + 1] = n; for (int i = 1; i <= n; ++i) l[i] = i - 1, r[i] = i + 1; validl[0] = 1, vall[0] = 2 * d[0]; for (int i = 1; i <= n + 1; ++i) { queue<int> drop; if ((i > 1) && (pos[r[i - 1]] - pos[l[i - 1]] > 2 * d[i - 1])) drop.push(i - 1); while (!drop.empty()) { int t = drop.front(); drop.pop(); int lt = l[t], rt = r[t]; r[lt] = r[t]; l[rt] = l[t]; if (lt != 0) { if (pos[r[lt]] - pos[l[lt]] > 2 * d[lt]) drop.push(lt); } if (rt != i) { if (pos[r[rt]] - pos[l[rt]] > 2 * d[rt]) drop.push(rt); } } if (2 * d[i] - (pos[i] - pos[l[i]]) > 0) validl[i] = 1; vall[i] = 2 * d[i] + pos[l[i]]; } if (r[0] != n + 1) { cout << 0.0 n ; exit(0); } } void computeright() { l[0] = -1, r[0] = 1, r[n + 1] = -1, l[n + 1] = n; for (int i = 1; i <= n; ++i) l[i] = i - 1, r[i] = i + 1; validr[n + 1] = 1, valr[n + 1] = pos[n + 1] - 2 * d[n + 1]; for (int i = n; i >= 1; --i) { queue<int> drop; if ((i < n) && (pos[r[i + 1]] - pos[l[i + 1]] > 2 * d[i + 1])) drop.push(i + 1); while (!drop.empty()) { int t = drop.front(); drop.pop(); int lt = l[t], rt = r[t]; r[lt] = r[t]; l[rt] = l[t]; if (lt != i) { if (pos[r[lt]] - pos[l[lt]] > 2 * d[lt]) drop.push(lt); } if (rt != n + 1) { if (pos[r[rt]] - pos[l[rt]] > 2 * d[rt]) drop.push(rt); } } if (2 * d[i] - (pos[r[i]] - pos[i]) > 0) validr[i] = 1; valr[i] = pos[r[i]] - 2 * d[i]; } } void init(int l = 0, int r = n, int node = 1) { if (l == r) { tree[node] = 1e9 + 5; return; } int mid = (l + r) / 2; init(l, mid, 2 * node); init(mid + 1, r, 2 * node + 1); tree[node] = min(tree[2 * node], tree[2 * node + 1]); } int findmin(int a, int b, int l = 0, int r = n, int node = 1) { if (a == l && b == r) return tree[node]; int mid = (l + r) / 2; if (b <= mid) return findmin(a, b, l, mid, 2 * node); if (a >= mid + 1) return findmin(a, b, mid + 1, r, 2 * node + 1); return min(findmin(a, mid, l, mid, 2 * node), findmin(mid + 1, b, mid + 1, r, 2 * node + 1)); } void upd(int v, int x, int l = 0, int r = n, int node = 1) { if (l == r) { tree[node] = x; return; } int mid = (l + r) / 2; if (v <= mid) upd(v, x, l, mid, 2 * node); else upd(v, x, mid + 1, r, 2 * node + 1); tree[node] = min(tree[2 * node], tree[2 * node + 1]); } void findans() { for (int i = 0; i <= n; ++i) sortr[i] = pair<long long, long long>(valr[i + 1], i + 1); sort(sortr, sortr + n + 1); for (int i = 0; i <= n; ++i) ind[sortr[i].second] = i; init(); long long best = 1e9 + 5; for (int i = n; i >= 0; --i) { if (validr[i + 1]) upd(ind[i + 1], pos[i + 1]); if (!validl[i]) continue; int lo = -1, hi = n; while (lo != hi) { int mid = (lo + hi + 1) / 2; if (sortr[mid].first > vall[i]) hi = mid - 1; else lo = mid; } if (lo != -1) best = min(best, findmin(0, lo) - pos[i]); } cout << fixed << setprecision(1) << 0.5 * best << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n + 2; ++i) cin >> pos[i]; d[0] = d[n + 1] = 1LL * 1000000 * 1000000 + 5; for (int i = 1; i <= n; ++i) cin >> d[i]; computeleft(); computeright(); findans(); } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int ans[N << 1]; int main() { int n; cin >> n; int b1 = n + 1; int b2 = 2 * n - 1; int a1 = 1; int a2 = n; int cnt = 1; for (int i = 1; i <= n - 1; ++i) { if (cnt & 1) ans[a1++] = i, ans[a2--] = i; else ans[b1++] = i, ans[b2--] = i; cnt++; } for (int i = 1; i <= 2 * n; ++i) if (ans[i] == 0) cout << n << ; else cout << ans[i] << ; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[2000000 + 100]; int main() { cin >> n >> m; if ((m < n - 1) || (m > 2 * (n + 1))) { cout << -1 << endl; return 0; } for (int i = 1; i <= n; i++) a[2 * i] = 0; for (int i = 2; i <= n; i++) a[2 * i - 1] = 1; m = m - (n - 1); for (int i = 2; i <= n; i++) { if (m == 0) break; a[2 * i - 1] = 11, m--; } if (m == 1) cout << 1; if (m == 2) cout << 11; if (m == 3) cout << 11; if (m == 4) cout << 11; for (int i = 2; i <= 2 * n; i++) cout << a[i]; if (m == 3) cout << 1; if (m == 4) cout << 11; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; set<pair<int, int>> s; map<int, int> m; int temp; for (int i = 0; i < n; i++) { cin >> temp; if (s.size() < k && (!m.count(temp))) { s.insert({i + 1, temp}); m[temp] = i + 1; } if (!m.count(temp) || (!s.count({m[temp], temp}))) { s.insert({i + 1, temp}); m[temp] = i + 1; s.erase(*s.begin()); } } int ar[k + 10]; int c = 0; for (auto u : s) { ar[c] = u.second; c++; } cout << c << n ; for (int i = c - 1; i >= 0; i--) { cout << ar[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double eps = 1e-9; const int Mod = 1e9 + 7; const int MaxN = 2e5 + 5; char s[MaxN]; int a[MaxN]; int l[MaxN], r[MaxN]; bool cmp(int x, int y) { return x > y; } int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %s , s + 1); int len = 0; for (int i = 1; i <= n; i++) { if (i == 1) { l[++len] = 1; continue; } if (s[i] == s[i - 1]) continue; r[len] = i - 1; l[++len] = i; } r[len] = n; for (int i = 1; i <= len; i++) { sort(a + l[i], a + r[i] + 1, cmp); } long long ans = 0LL, cnt = 1; for (int i = 1; i <= n; i++) { if (s[i] == s[i - 1]) cnt++; else cnt = 1; if (cnt > k) continue; ans += (long long)a[i]; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 32005; int n, m, i, j, f; int a[N]; long long ans; int main() { scanf( %d%d , &n, &m); for (i = m + 1; i <= (n + 1) / 2; i++) { for (j = m + 1; j < 2 * i; j++) { f = (i * (2 * i - j) + (n + 1) * (2 * j - i)) / (i + j); f = max(f, m); if (f > n - m) continue; a[i] += n - m - f; } } for (i = m + 1; i <= (n + 1) / 2; i++) ans += 2 * a[i]; if (n % 2) ans -= a[i - 1]; printf( %I64d n , 3 * ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, sgn = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) sgn = -1; for (; isdigit(ch); ch = getchar()) x = (x << 1) + (x << 3) + (ch ^ 48); return x * sgn; } const int N = 1e5 + 10; int n; long long ans1, ans2; struct line { int x, y, l, r; } seg[N]; bool cmp1(line a, line b) { return a.x < b.x; } bool cmp2(line a, line b) { return a.y < b.y; } struct BITT { int arr[N << 1]; void add(int x, int v = 1) { for (; x <= (n * 2); x += x & -x) arr[x] += v; return; } int q(int x, int v = 0) { for (; x; x -= x & -x) v += arr[x]; return v; } void clear() { memset(arr, 0, sizeof(arr)); } } BIT; int main() { n = read(); for (int i = 1; i <= n; i++) seg[i].x = read(), seg[i].y = read(); for (int i = 1; i <= n; i++) if (seg[i].x > seg[i].y) swap(seg[i].x, seg[i].y); sort(seg + 1, seg + n + 1, cmp1); for (int i = 1; i <= n; i++) { seg[i].l += BIT.q(seg[i].x) + BIT.q(n << 1) - BIT.q(seg[i].y); BIT.add(seg[i].y); } BIT.clear(); for (int i = n; i >= 1; i--) { seg[i].r += BIT.q(seg[i].y); BIT.add(seg[i].y); } BIT.clear(); sort(seg + 1, seg + n + 1, cmp2); for (int i = n; i >= 1; i--) { seg[i].l += BIT.q(n << 1) - BIT.q(seg[i].y); BIT.add(seg[i].x); } ans1 = 1ll * n * (n - 1) * (n - 2) / 6; for (int i = 1; i <= n; i++) { ans1 -= 1ll * seg[i].l * seg[i].r; ans2 += 1ll * (seg[i].l + seg[i].r) * (n - seg[i].l - seg[i].r - 1); } printf( %lld n , ans1 - ans2 / 2); return 0; } |
#include <bits/stdc++.h> const int maxn = 1e5 + 5; int n, k; int a[maxn]; int main() { scanf( %d%d , &n, &k); int ans = 0; int l = 0; while (k--) { bool flag = false; int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d , &a[i]); if (a[1] == 1) flag = true; } if (flag) { l = 1; for (int i = 2; i <= m; i++) { if (a[i] == (a[i - 1] + 1)) l++; else break; } ans += m - l; } else ans += m - 1; } ans += n - l; printf( %d n , ans); return 0; } |
//#############################################################################
//# Function: Parallel to Serial Converter #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE in OH! repositpory) #
//#############################################################################
module oh_par2ser #(parameter PW = 64, // parallel packet width
parameter SW = 1, // serial packet width
parameter CW = $clog2(PW/SW) // serialization factor
)
(
input clk, // sampling clock
input nreset, // async active low reset
input [PW-1:0] din, // parallel data
output [SW-1:0] dout, // serial output data
output access_out,// output data valid
input load, // load parallel data (priority)
input shift, // shift data
input [7:0] datasize, // size of data to shift
input lsbfirst, // lsb first order
input fill, // fill bit
input wait_in, // wait input
output wait_out // wait output (wait in | serial wait)
);
// local wires
reg [PW-1:0] shiftreg;
reg [CW-1:0] count;
wire start_transfer;
wire busy;
// start serialization
assign start_transfer = load & ~wait_in & ~busy;
//transfer counter
always @ (posedge clk or negedge nreset)
if(!nreset)
count[CW-1:0] <= 'b0;
else if(start_transfer)
count[CW-1:0] <= datasize[CW-1:0]; //one "SW sized" transfers
else if(shift & busy)
count[CW-1:0] <= count[CW-1:0] - 1'b1;
//output data is valid while count > 0
assign busy = |count[CW-1:0];
//data valid while shifter is busy
assign access_out = busy;
//wait until valid data is finished
assign wait_out = wait_in | busy;
// shift register
always @ (posedge clk)
if(start_transfer)
shiftreg[PW-1:0] = din[PW-1:0];
else if(shift & lsbfirst)
shiftreg[PW-1:0] = {{(SW){fill}}, shiftreg[PW-1:SW]};
else if(shift)
shiftreg[PW-1:0] = {shiftreg[PW-SW-1:0],{(SW){fill}}};
assign dout[SW-1:0] = lsbfirst ? shiftreg[SW-1:0] :
shiftreg[PW-1:PW-SW];
endmodule // oh_par2ser
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__XOR2_PP_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_PP_BLACKBOX_V
|
`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
module fragment_bench();
reg clk_i;
reg rst_i;
parameter point_width = 16;
reg [7:0] pixel_alpha_i;
// from raster
reg [point_width-1:0] x_counter_i;
reg [point_width-1:0] y_counter_i;
reg signed [point_width-1:0] z_i;
reg [point_width-1:0] u_i;
reg [point_width-1:0] v_i;
reg [point_width-1:0] bezier_factor0_i;
reg [point_width-1:0] bezier_factor1_i;
reg bezier_inside_i;
reg [31:0] pixel_color_i;
reg write_i;
reg curve_write_i;
reg ack_i;
//to blender
wire [point_width-1:0] pixel_x_o;
wire [point_width-1:0] pixel_y_o;
wire [31:0] pixel_color_o;
wire [7:0] pixel_alpha_o;
wire write_o;
wire ack_o;
// to/from wishbone master read
reg texture_ack_i;
reg [31:0] texture_data_i;
wire [31:2] texture_addr_o;
wire [3:0] texture_sel_o;
wire texture_request_o;
// from wishbone slave
reg texture_enable_i;
reg [31:2] tex0_base_i;
reg [point_width-1:0] tex0_size_x_i;
reg [point_width-1:0] tex0_size_y_i;
reg [1:0] color_depth_i;
reg colorkey_enable_i;
reg [31:0] colorkey_i;
initial begin
$dumpfile("fragment.vcd");
$dumpvars(0,fragment_bench);
// init values
clk_i = 0;
rst_i = 1;
write_i = 0;
curve_write_i = 0;
bezier_inside_i = 0;
texture_enable_i = 0;
color_depth_i = 2'b01;
ack_i = 0;
pixel_alpha_i = 8'hff;
pixel_color_i = 32'h12345678;
tex0_base_i = 32'h12341234;
tex0_size_x_i = 12;
tex0_size_y_i = 10;
u_i = 0;
v_i = 0;
z_i = 10;
bezier_factor0_i = 0;
bezier_factor1_i = 0;
x_counter_i = 0;
y_counter_i = 0;
texture_data_i = 32'hf800ffff;
colorkey_enable_i = 0;
colorkey_i = 32'h00000000;
//timing
#4 rst_i = 0;
#2 write_i = 1;
#2 write_i = 0;
#6 texture_enable_i = 1;
#40 write_i = 1;
#2 write_i = 0;
// end sim
#100 $finish;
end
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
texture_ack_i <= #1 texture_request_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_fragment_processor fragment(
.clk_i (clk_i),
.rst_i (rst_i),
.pixel_alpha_i (pixel_alpha_i),
.x_counter_i (x_counter_i),
.y_counter_i (y_counter_i),
.z_i (z_i),
.u_i (u_i),
.v_i (v_i),
.bezier_factor0_i (bezier_factor0_i),
.bezier_factor1_i (bezier_factor1_i),
.bezier_inside_i (bezier_inside_i),
.pixel_color_i (pixel_color_i),
.write_i (write_i),
.curve_write_i (curve_write_i),
.ack_i (ack_i),
.pixel_x_o (pixel_x_o),
.pixel_y_o (pixel_y_o),
.pixel_color_o (pixel_color_o),
.pixel_alpha_o (pixel_alpha_o),
.write_o (write_o),
.ack_o (ack_o),
.texture_ack_i (texture_ack_i),
.texture_data_i (texture_data_i),
.texture_addr_o (texture_addr_o),
.texture_sel_o (texture_sel_o),
.texture_request_o(texture_request_o),
.texture_enable_i (texture_enable_i),
.tex0_base_i (tex0_base_i),
.tex0_size_x_i (tex0_size_x_i),
.tex0_size_y_i (tex0_size_y_i),
.color_depth_i (color_depth_i),
.colorkey_enable_i(colorkey_enable_i),
.colorkey_i (colorkey_i)
);
endmodule
|
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_k_constants(
input wire [5 : 0] addr,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// addr_mux
//----------------------------------------------------------------
always @*
begin : addr_mux
case(addr)
00: tmp_K = 32'h428a2f98;
01: tmp_K = 32'h71374491;
02: tmp_K = 32'hb5c0fbcf;
03: tmp_K = 32'he9b5dba5;
04: tmp_K = 32'h3956c25b;
05: tmp_K = 32'h59f111f1;
06: tmp_K = 32'h923f82a4;
07: tmp_K = 32'hab1c5ed5;
08: tmp_K = 32'hd807aa98;
09: tmp_K = 32'h12835b01;
10: tmp_K = 32'h243185be;
11: tmp_K = 32'h550c7dc3;
12: tmp_K = 32'h72be5d74;
13: tmp_K = 32'h80deb1fe;
14: tmp_K = 32'h9bdc06a7;
15: tmp_K = 32'hc19bf174;
16: tmp_K = 32'he49b69c1;
17: tmp_K = 32'hefbe4786;
18: tmp_K = 32'h0fc19dc6;
19: tmp_K = 32'h240ca1cc;
20: tmp_K = 32'h2de92c6f;
21: tmp_K = 32'h4a7484aa;
22: tmp_K = 32'h5cb0a9dc;
23: tmp_K = 32'h76f988da;
24: tmp_K = 32'h983e5152;
25: tmp_K = 32'ha831c66d;
26: tmp_K = 32'hb00327c8;
27: tmp_K = 32'hbf597fc7;
28: tmp_K = 32'hc6e00bf3;
29: tmp_K = 32'hd5a79147;
30: tmp_K = 32'h06ca6351;
31: tmp_K = 32'h14292967;
32: tmp_K = 32'h27b70a85;
33: tmp_K = 32'h2e1b2138;
34: tmp_K = 32'h4d2c6dfc;
35: tmp_K = 32'h53380d13;
36: tmp_K = 32'h650a7354;
37: tmp_K = 32'h766a0abb;
38: tmp_K = 32'h81c2c92e;
39: tmp_K = 32'h92722c85;
40: tmp_K = 32'ha2bfe8a1;
41: tmp_K = 32'ha81a664b;
42: tmp_K = 32'hc24b8b70;
43: tmp_K = 32'hc76c51a3;
44: tmp_K = 32'hd192e819;
45: tmp_K = 32'hd6990624;
46: tmp_K = 32'hf40e3585;
47: tmp_K = 32'h106aa070;
48: tmp_K = 32'h19a4c116;
49: tmp_K = 32'h1e376c08;
50: tmp_K = 32'h2748774c;
51: tmp_K = 32'h34b0bcb5;
52: tmp_K = 32'h391c0cb3;
53: tmp_K = 32'h4ed8aa4a;
54: tmp_K = 32'h5b9cca4f;
55: tmp_K = 32'h682e6ff3;
56: tmp_K = 32'h748f82ee;
57: tmp_K = 32'h78a5636f;
58: tmp_K = 32'h84c87814;
59: tmp_K = 32'h8cc70208;
60: tmp_K = 32'h90befffa;
61: tmp_K = 32'ha4506ceb;
62: tmp_K = 32'hbef9a3f7;
63: tmp_K = 32'hc67178f2;
endcase // case (addr)
end // block: addr_mux
endmodule // sha256_k_constants
//======================================================================
// sha256_k_constants.v
//======================================================================
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_bCMD_IDLE for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_bCMD_IDLE
// Module Name: NPCG_Toggle_bCMD_IDLE
// File Name: NPCG_Toggle_bCMD_IDLE.v
//
// Version: v1.0.0
//
// Description: Idle execution FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_bCMD_IDLE
#
(
parameter NumberOfWays = 4
)
(
oWriteReady ,
oReadData ,
oReadLast ,
oReadValid ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData ,
oPM_WriteData ,
oPM_WriteLast ,
oPM_WriteValid ,
oPM_ReadReady
);
output oWriteReady ;
output [31:0] oReadData ;
output oReadLast ;
output oReadValid ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
output [31:0] oPM_WriteData ;
output oPM_WriteLast ;
output oPM_WriteValid ;
output oPM_ReadReady ;
// Output
// Dispatcher Interface
// - Data Write Channel
assign oWriteReady = 1'b0;
// - Data Read Channel
assign oReadData[31:0] = 32'h6789_ABCD;
assign oReadLast = 1'b0;
assign oReadValid = 1'b0;
// NPCG_Toggle Interface
assign oPM_PCommand[7:0] = 8'b0000_0000;
assign oPM_PCommandOption[2:0] = 3'b000;
assign oPM_TargetWay[NumberOfWays - 1:0] = 4'b0000;
assign oPM_NumOfData[15:0] = 16'h1234;
assign oPM_CASelect = 1'b0;
assign oPM_CAData[7:0] = 8'hCC;
assign oPM_WriteData[31:0] = 32'h6789_ABCD;
assign oPM_WriteLast = 1'b0;
assign oPM_WriteValid = 1'b0;
assign oPM_ReadReady = 1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:34:44 03/12/2012
// Design Name:
// Module Name: Regs
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Regs(
clk,
rst,
reg_R_addr_A,
reg_R_addr_B,
reg_W_addr,
wdata,
reg_we,
rdata_A,
rdata_B
);
input clk, rst, reg_we;
input [ 4: 0] reg_R_addr_A, reg_R_addr_B, reg_W_addr;
input [31: 0] wdata;
output [31: 0] rdata_A, rdata_B;
reg [31:0] register [1:31];
integer i;
assign rdata_A = (reg_R_addr_A == 0) ? 0 : register[reg_R_addr_A];
assign rdata_B = (reg_R_addr_B == 0) ? 0 : register[reg_R_addr_B];
initial begin
for(i = 1; i < 32; i = i + 1)
register[i] = 32'h0000_0000 ;
end
always @(posedge clk or posedge rst)
begin
if (rst == 1) begin
for(i = 1; i < 32; i = i + 1)
register[i] <= 0;
end
else begin
if((reg_W_addr != 0) && (reg_we == 1))
register[reg_W_addr] <= wdata;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; queue<pair<int, int> > q; vector<pair<int, int> > v; vector<vector<int> > g; set<pair<int, int> > out; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; v.push_back({x, y}); if (x == 1) q.push({i, y}); } while (!q.empty()) { pair<int, int> x = q.front(); q.pop(); int y = x.second; v[y].second ^= x.first; v[y].first--; out.insert({min(x.first, y), max(x.first, y)}); if (v[y].first == 1) { q.push({y, v[y].second}); } } cout << out.size() << n ; for (auto a : out) { cout << a.first << << a.second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > sol[1 << 9]; vector<pair<int, int> > gs(int t, int x) { static int fm[1 << 19]; static pair<int, int> fs[1 << 19]; queue<int> q; vector<pair<pair<int, int>, int> > sb; for (int i = 0; i < (1 << t); ++i) fm[i] = -1; for (int i = 0; i < t; ++i) for (int k = 1; i + k + k < t; ++k) sb.push_back(make_pair(pair<int, int>(i, k), (1 << i) ^ (1 << (i + k)) ^ (1 << (i + k + k)))); q.push(x); fm[x] = -2; while (!q.empty()) { int w = q.front(); q.pop(); for (auto p : sb) { if (fm[w ^ p.second] != -1) continue; fm[w ^ p.second] = w; fs[w ^ p.second] = p.first; q.push(w ^ p.second); } } if (fm[0] == -1) throw GG ; int tt = 0; vector<pair<int, int> > vp; while (tt != x) vp.push_back(fs[tt]), tt = fm[tt]; return vp; } int n; int a[233333]; int main() { int mx = 0; for (int i = 0; i < (1 << 9); ++i) { vector<pair<int, int> > sb; for (int j = 0; j < 12; ++j) for (int k = 1; j + k + k < 12; ++k) sb.push_back(pair<int, int>(j, k)); random_shuffle(sb.begin(), sb.end()); int u = sb.size(); for (int x = -1; x < u; ++x) for (int y = x; y < u; ++y) for (int z = y; z < u; ++z) { vector<pair<int, int> > p; if (x >= 0) p.push_back(sb[x]); if (y >= 0) p.push_back(sb[y]); if (z >= 0) p.push_back(sb[z]); int w = i; for (auto h : p) { int a = h.first, b = h.second; if (a >= 0 && a < 9) w ^= 1 << a; if (a + b >= 0 && a + b < 9) w ^= 1 << (a + b); if (a + b + b >= 0 && a + b + b < 9) w ^= 1 << (a + b + b); } if (!w) { sol[i] = p; goto GG; } } cout << NMSL. n ; GG:; } scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , a + i); vector<pair<pair<int, int>, int> > vp; int l = 1; while (n - l + 1 >= 18) { int h = 0; for (int p = 0; p < 9; ++p) if (a[l + p]) h ^= 1 << p; vector<pair<int, int> > w = sol[h]; for (auto& t : w) { t.first += l; vp.push_back(make_pair(make_pair(t.first, t.first + t.second), t.first + t.second + t.second)); a[t.first] ^= 1; a[t.first + t.second] ^= 1; a[t.first + t.second + t.second] ^= 1; } l += 9; } try { int g = 0; for (int i = l; i <= n; ++i) if (a[i]) g ^= 1 << (i - l); vector<pair<int, int> > w = gs(n - l + 1, g); for (auto& t : w) { t.first += l; vp.push_back(make_pair(make_pair(t.first, t.first + t.second), t.first + t.second + t.second)); a[t.first] ^= 1; a[t.first + t.second] ^= 1; a[t.first + t.second + t.second] ^= 1; } } catch (...) { puts( NO ); return 0; } for (int i = 0; i <= n + 1; ++i) if (a[i]) throw GG ; puts( YES ); printf( %d n , int(vp.size())); for (auto t : vp) printf( %d %d %d n , t.first.first, t.first.second, t.second); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V |
module psdos ( input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
//reg [1:0] k;
reg init;
//reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
//DONE=0;
//Rx_error=0;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
//=======
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if((!(j%2)&&(regis[8]))||((j%2)&&(!regis[8])))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init<=0;
end
end
assign DATA=regis0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long w, m, k; int main() { scanf( %I64d%I64d%I64d , &w, &m, &k); w /= k; if (!w) { puts( 0 ); return 0; } long long cnt = 0; long long tmp = m; while (tmp) { cnt++; tmp /= 10; } tmp = 1; for (int i = 0; i < cnt; i++) tmp *= 10; long long x = m - 1, y = tmp - 1; while (w) { if (w < cnt) break; if (w >= (y - x) * cnt) { w -= (y - x) * cnt; x = y; y = y * 10 + 9; cnt++; } else { x += w / cnt; w = 0; break; } } cout << x - m + 1 << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1, i = 0, j = 0, k = 0; cin >> t; while (t--) { long long int n; cin >> n; long long int l[n], r[n]; for (i = 0; i < n; ++i) cin >> l[i] >> r[i]; long long int t = 0; for (i = 0; i < n; ++i) { ++t; sg: if (i < n) { if (r[i] > t - 1 && l[i] <= t) cout << t << ; else if (r[i] > t - 1) { cout << l[i] << ; t = l[i]; } else { cout << 0 ; ++i; goto sg; } } } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, r; scanf( %d%d%d , &a, &b, &r); printf( %s n , a >= 2 * r && b >= 2 * r ? First : Second ); } |
module arbitro (
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
input wire [2:0] pe_request_bundle,
input wire [2:0] north_request_bundle,
input wire [2:0] east_request_bundle,
// Configuration bundles are composed by:
// * cfg_bundle[2] :: mux_ctrl[1]
// * cfg_bundle[1] :: mux_ctrl[0]
// * cfg_bundle[0] :: toggle
output reg [1:0] pe_cfg_bundle,
output reg [2:0] south_cfg_bundle,
output reg [2:0] west_cfg_bundle,
// ACK that a request from the PE has been accepted
output reg r2pe_ack
);
// Local Symbols
localparam MUX_EAST = 3'b111;
localparam MUX_NORTH = 3'b101;
localparam MUX_PE = 3'b001;
localparam MUX_NULL = 3'b000;
localparam PE_NULL = 2'b00;
// Signal for visivility at debug
wire [2:0] request_vector;
assign request_vector = {east_request_bundle[0], north_request_bundle[0], pe_request_bundle[0]};
// First level classification - by active request
always @(*)
begin
// default values to infer combinational logic
west_cfg_bundle = MUX_NULL;
south_cfg_bundle = MUX_NULL;
pe_cfg_bundle = PE_NULL;
r2pe_ack = 1'b0;
case (request_vector)
3'b000: // None
begin
// Everything on default
end
3'b001: // PE
begin
r2pe_ack = 1'b1;
case (pe_request_bundle[2:1])
2'b00: west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
2'b01: west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
2'b10: south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
2'b11:
begin
r2pe_ack = 1'b0;
south_cfg_bundle = MUX_NULL; // invalid
end
endcase
end
3'b010: // North
case (north_request_bundle[2:1])
2'b00: west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
2'b01: west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
2'b10: south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
2'b11: pe_cfg_bundle = 2'b01; // mux1 -> north toggle -> 1
endcase
3'b011: // North, PE
begin
r2pe_ack = 1'b1;
case (north_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b10:
begin
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b11:
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b01; // mux1 -> north toggle -> 1
end
endcase
end
3'b100: // East
case (east_request_bundle[2:1])
2'b00: west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
2'b01: west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
2'b10: south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
2'b11: pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
endcase
3'b101: // East, PE
begin
r2pe_ack = 1'b1;
case (east_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b10:
begin
south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b11:
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
end
endcase
end
3'b110: // East, North
case (east_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b10:
begin
south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b11:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
end
endcase
3'b111: // East, North, PE
case (east_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
if (north_request_bundle[2:1] == 2'b11)
begin
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b01; // mux1 -> north, toggle -> 1
r2pe_ack = 1'b1;
end
else
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b10:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
if (north_request_bundle[2:1] == 2'b11)
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b01; // mux1 -> north, toggle -> 1
r2pe_ack = 1'b1;
end
else
south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
end
2'b11:
begin
if (north_request_bundle[2:1] == 2'b01)
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
else
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
r2pe_ack = 1'b1;
end
endcase
endcase // first level descrimination :: by active request
end // arbiter body
endmodule
|
#include <bits/stdc++.h> using namespace std; int caseno = 1; typedef long long LL; typedef unsigned long long ULL; typedef long long int64; typedef unsigned long long uint64; const int SIZE = 100 + 10; int ar[SIZE]; int main() { std::ios_base::sync_with_stdio(0); int tcases, I, J, K, N, n, m, cnt = 0, len, f = 0, x, D, t; cin >> n; for (I = 0; I < n; I++) { cin >> ar[I]; f += ar[I]; } n++; D = 1; t = f; t += D; I = 1; x = 1; while (1) { x++; if (I == n) I = 1; else I++; if (x == t) break; } if (I != 1) cnt++; D = 2; t = f; t += D; I = 1; x = 1; while (1) { x++; if (I == n) I = 1; else I++; if (x == t) break; } if (I != 1) cnt++; D = 3; t = f; t += D; I = 1; x = 1; while (1) { x++; if (I == n) I = 1; else I++; if (x == t) break; } if (I != 1) cnt++; D = 4; t = f; t += D; I = 1; x = 1; while (1) { x++; if (I == n) I = 1; else I++; if (x == t) break; } if (I != 1) cnt++; D = 5; t = f; t += D; I = 1; x = 1; while (1) { x++; if (I == n) I = 1; else I++; if (x == t) break; } if (I != 1) cnt++; cout << cnt << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_PP_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LOWHVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int vis[10], A[300], B[300]; int ct[300], mrk[300]; vector<pair<int, int>> ans; int main() { int n, x; scanf( %d , &n); for (int i = 0; i < n; i++) { for (int j = 0; j < 3; j++) { scanf( %d , &x); A[i] |= (1 << j) * x; } } for (int i = 0; i < n; i++) { for (int j = 0; j < 3; j++) { scanf( %d , &x); B[i] |= (1 << j) * x; } } vis[7] = ct[0] = vis[0] = mrk[0] = 1; for (int i = 1; i <= 7; i++) { for (int j = 1; j <= 7; j++) { for (int k = 0; !vis[j] && k < n; k++) { if (vis[A[k]] && (A[k] & B[k]) == j) { vis[j] = k + 1; ct[k] = mrk[k] = 1; ans.push_back({vis[A[k]], k + 1}); } for (int _k = (A[k] - 1) & A[k]; _k != 0 && !vis[j]; _k = (_k - 1) & A[k]) { if (vis[A[k] ^ _k] && vis[_k] && (B[k] & A[k]) == j) { vis[j] = k + 1; ct[k] = mrk[k] = 1; ans.push_back({vis[_k], k + 1}); ans.push_back({vis[A[k] ^ _k], k + 1}); } if (!vis[j] && vis[A[k] ^ _k] && vis[_k] && A[k] == j) { vis[j] = k + 1; mrk[k] = 1; ans.push_back({vis[_k], k + 1}); ans.push_back({vis[A[k] ^ _k], k + 1}); } } } } } for (int i = 0; i < n; i++) { if (!vis[A[i]]) return !printf( Impossible n ); if (!mrk[i] && A[i] != 0) ans.push_back({vis[A[i]], i + 1}); } printf( Possible n ); for (int i = 0; i < n; i++) printf( %d , ct[i]); printf( n%d n , (int)ans.size()); for (auto it : ans) printf( %d %d n , it.first, it.second); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module uart #(parameter div=234)(
input clk,
input rst,
output reg txd,
input rxd,
input wr,
input[7:0] din,
output rdy,
output reg[7:0] dout,
output reg valid,
input rd // assert rd when dout is read so that the UART module can start sniffing for the next byte
);
//parameter div = 234; // 27MHz , 115200 baud , div=234
reg[31:0] count;
reg[7:0] data;
always @(posedge clk or posedge rst) begin
if(rst) data = 0;
else if(wr) begin
data = din;
end
end
wire tick;
reg[3:0] state,n_state;
parameter s0 = 0;
parameter s1 = 1;
parameter s2 = 2;
parameter s3 = 3;
parameter s4 = 4;
parameter s5 = 5;
parameter s6 = 6;
parameter s7 = 7;
parameter s8 = 8;
parameter s9 = 9;
always @(posedge clk or posedge rst) begin
if(rst) begin
count <= 0;
end
else begin
if(tick) count <= 0;
else count <= count + 1;
end
end
assign tick = (count == div) | (wr & (state==0));
always @(posedge clk or posedge rst) begin
if(rst) state <= 0;
else if(tick) state <= n_state;
end
always @(state or wr) begin
if(state == 0) begin
if(wr) n_state <= 1;
else n_state <= 0;
end
else if(state < 10) n_state <= state + 1;
else n_state <= 0;
end
always @(*) begin
case(state)
4'h0: txd <= 1;
4'h1: txd <= 0;
4'h2: txd <= data[0];
4'h3: txd <= data[1];
4'h4: txd <= data[2];
4'h5: txd <= data[3];
4'h6: txd <= data[4];
4'h7: txd <= data[5];
4'h8: txd <= data[6];
4'h9: txd <= data[7];
default: txd <= 1;
endcase
end
assign rdy = (state == s0);
////////////////////RX Section////////////////////////////
reg[15:0] rx_baud_count;
wire rx_tick;
reg rx_baudgen_rst;
always @(posedge clk or posedge rst) begin
if(rst) rx_baud_count <= 0;
else
if(rx_baudgen_rst | (rx_baud_count == div)) rx_baud_count <= 0;
else rx_baud_count <= rx_baud_count + 1;
end
assign rx_tick = (rx_baud_count == div/2);
reg rx_shift;
reg[3:0] rx_bits_rxed,rx_bits_next_rxed;
reg[3:0] rx_state,rx_next_state;
always @(posedge clk or posedge rst) begin
if(rst)
dout <= 0;
else
if(rx_shift) dout <= { rxd, dout[7:1] };
end
reg next_valid;
always @(posedge clk or posedge rst) begin
if(rst)
begin
rx_state <= 0;
rx_bits_rxed <= 0;
end
else
begin
rx_bits_rxed <= rx_bits_next_rxed;
rx_state <= rx_next_state;
end
end
always @(*) begin
rx_next_state <= rx_state;
rx_baudgen_rst <= 0;
rx_bits_next_rxed <= rx_bits_rxed;
rx_shift <= 0;
valid <= 0;
case(rx_state)
4'h0: begin
if(rxd==0) rx_next_state <= 1;
end
4'h1: begin
rx_baudgen_rst <= 1;
rx_bits_next_rxed <= 0;
rx_next_state <= 2;
end
4'h2: begin
if(rx_tick) rx_next_state <= 3;
end
4'h3: begin
rx_shift <= 1;
rx_bits_next_rxed <= rx_bits_rxed + 1;
if(rx_bits_rxed < 8) rx_next_state <= 2;
else rx_next_state <= 4;
end
4'h4: begin
if(rx_tick) rx_next_state <= 5;
end
4'h5: begin
valid <= 1;
if(rd) rx_next_state <= 0;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_2_V
`define SKY130_FD_SC_HD__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200020; const int MOD = 1000000000; int add(int a, int b) { return a >= MOD - b ? a - MOD + b : a + b; } int mul(int a, int b) { return a ? (b < MOD / a ? a * b : (long long)a * b % MOD) : 0; } int sub(int a, int b) { return a < b ? a - b + MOD : a - b; } template <int MATRIX_MAXN = 2> struct Matrix { int n; int mat[MATRIX_MAXN][MATRIX_MAXN]; void initEyeMatrix() { n = 2; mat[0][0] = 1; mat[0][1] = 0; mat[1][0] = 0; mat[1][1] = 1; } void initFibMatrix() { n = 2; mat[0][0] = 0; mat[0][1] = 1; mat[1][0] = 1; mat[1][1] = 1; } Matrix operator*(const Matrix &rhs) const { Matrix res; res.n = n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { res.mat[i][j] = 0; for (int k = 0; k < n; k++) { res.mat[i][j] = add(res.mat[i][j], mul(mat[i][k], rhs.mat[k][j])); } } } return res; } }; int fibsum[MAXN], a[MAXN]; Matrix<> fibmat[MAXN]; void initFibsum() { fibsum[0] = fibsum[1] = 1; fibmat[0].initEyeMatrix(); Matrix<> fmat; fmat.initFibMatrix(); for (int i = (2); i < (MAXN); i++) fibsum[i] = add(fibsum[i - 1], fibsum[i - 2]); for (int i = (1); i < (MAXN); i++) { fibmat[i] = fibmat[i - 1] * fmat; fibsum[i] = add(fibsum[i - 1], fibsum[i]); } } int getFib(int n, int f0, int f1) { return add(mul(f0, fibmat[n].mat[0][0]), mul(f1, fibmat[n].mat[1][0])); } struct Segment { int f0, f1, delta, size; Segment(int f0 = 0, int f1 = 0, int delta = 0, int size = 0) : f0(f0), f1(f1), delta(delta), size(size) {} int getF0() const { return add(f0, mul(delta, fibsum[size - 1])); } int getF1() const { return add(f1, mul(delta, sub(fibsum[size], 1))); } Segment operator+(const Segment &rhs) const { return Segment(add(getF0(), getFib(size, rhs.getF0(), rhs.getF1())), add(getF1(), getFib(size + 1, rhs.getF0(), rhs.getF1())), 0, size + rhs.size); } }; template <int MAXN = 200020, int MAXNODE = MAXN << 2> struct SegmentTree { int n; Segment seg[MAXNODE]; static int LEFT(int idx) { return idx << 1; } static int RIGHT(int idx) { return (idx << 1) | 1; } void _build(int idx, int lower, int upper) { if (lower == upper) { seg[idx] = Segment(a[lower], a[lower], 0, 1); return; } int middle = (lower + upper) >> 1; _build(LEFT(idx), lower, middle); _build(RIGHT(idx), middle + 1, upper); seg[idx] = seg[LEFT(idx)] + seg[RIGHT(idx)]; } void init(int n) { this->n = n; _build(1, 0, n - 1); } void pushDown(int idx) { seg[LEFT(idx)].delta = add(seg[LEFT(idx)].delta, seg[idx].delta); seg[RIGHT(idx)].delta = add(seg[RIGHT(idx)].delta, seg[idx].delta); seg[idx].delta = 0; } int l, r, x, v; void _modify(int idx, int lower, int upper) { if (l <= lower && upper <= r) { seg[idx].delta = add(seg[idx].delta, v); return; } pushDown(idx); int middle = (lower + upper) >> 1; if (r <= middle) { _modify(LEFT(idx), lower, middle); } else if (middle < l) { _modify(RIGHT(idx), middle + 1, upper); } else { _modify(LEFT(idx), lower, middle); _modify(RIGHT(idx), middle + 1, upper); } seg[idx] = seg[LEFT(idx)] + seg[RIGHT(idx)]; } void modify(int l, int r, int v) { this->l = l; this->r = r; this->v = v; _modify(1, 0, n - 1); } void _assign(int idx, int lower, int upper) { if (lower == upper) { seg[idx] = Segment(v, v, 0, 1); return; } pushDown(idx); int middle = (lower + upper) >> 1; if (x <= middle) { _assign(LEFT(idx), lower, middle); } else { _assign(RIGHT(idx), middle + 1, upper); } seg[idx] = seg[LEFT(idx)] + seg[RIGHT(idx)]; } void assign(int x, int v) { this->x = x; this->v = v; _assign(1, 0, n - 1); } Segment _calc(int idx, int lower, int upper) { if (l <= lower && upper <= r) return seg[idx]; pushDown(idx); int middle = (lower + upper) >> 1; Segment res; if (r <= middle) { res = _calc(LEFT(idx), lower, middle); } else if (middle < l) { res = _calc(RIGHT(idx), middle + 1, upper); } else { res = _calc(LEFT(idx), lower, middle) + _calc(RIGHT(idx), middle + 1, upper); } seg[idx] = seg[LEFT(idx)] + seg[RIGHT(idx)]; return res; } Segment calc(int l, int r) { this->l = l; this->r = r; return _calc(1, 0, n - 1); } }; int n, m; SegmentTree<> smt; int main() { initFibsum(); scanf( %d%d , &n, &m); for (int i = (0); i < (n); i++) scanf( %d , &a[i]); smt.init(n); for (int _ = (0); _ < (m); _++) { int op; scanf( %d , &op); if (op == 1) { int x, v; scanf( %d%d , &x, &v); smt.assign(x - 1, v); } else if (op == 2) { int l, r; scanf( %d%d , &l, &r); printf( %d n , smt.calc(l - 1, r - 1).getF0()); } else { int l, r, d; scanf( %d%d%d , &l, &r, &d); smt.modify(l - 1, r - 1, d); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MX = 2e5 + 5; const long long INF = 1e18; const long double PI = 4 * atan((long double)1); template <class T> bool ckmin(T& a, const T& b) { return a > b ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } mt19937 rng((uint32_t)chrono::steady_clock::now().time_since_epoch().count()); namespace input { template <class T> void re(complex<T>& x); template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } void re(long double& x) { string t; re(t); x = stold(t); } template <class T, class... Ts> void re(T& t, Ts&... ts) { re(t); re(ts...); } template <class T> void re(complex<T>& x) { T a, b; re(a, b); x = cd(a, b); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& a) { for (int i = (0); i < ((int)a.size()); ++i) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = (0); i < (SZ); ++i) re(a[i]); } } // namespace input using namespace input; namespace output { void pr(int x) { cout << x; } void pr(long x) { cout << x; } void pr(long long x) { cout << x; } void pr(unsigned x) { cout << x; } void pr(unsigned long x) { cout << x; } void pr(unsigned long long x) { cout << x; } void pr(float x) { cout << x; } void pr(double x) { cout << x; } void pr(long double x) { cout << x; } void pr(char x) { cout << x; } void pr(const char* x) { cout << x; } void pr(const string& x) { cout << x; } void pr(bool x) { pr(x ? true : false ); } template <class T> void pr(const complex<T>& x) { cout << x; } template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T> void pr(const T& x); template <class T, class... Ts> void pr(const T& t, const Ts&... ts) { pr(t); pr(ts...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T> void pr(const T& x) { pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } void ps() { pr( n ); } template <class T, class... Ts> void ps(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( ); ps(ts...); } void pc() { pr( ] n ); } template <class T, class... Ts> void pc(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( , ); pc(ts...); } } // namespace output using namespace output; namespace io { void setIn(string second) { freopen(second.c_str(), r , stdin); } void setOut(string second) { freopen(second.c_str(), w , stdout); } void setIO(string second = ) { cin.sync_with_stdio(0); cin.tie(0); if ((int)second.size()) { setIn(second + .in ), setOut(second + .out ); } } } // namespace io using namespace io; typedef decay<decltype(MOD)>::type T; struct mi { T val; explicit operator T() const { return val; } mi() { val = 0; } mi(const long long& v) { val = (-MOD <= v && v <= MOD) ? v : v % MOD; if (val < 0) val += MOD; } friend void pr(const mi& a) { pr(a.val); } friend void re(mi& a) { long long x; re(x); a = mi(x); } friend bool operator==(const mi& a, const mi& b) { return a.val == b.val; } friend bool operator!=(const mi& a, const mi& b) { return !(a == b); } friend bool operator<(const mi& a, const mi& b) { return a.val < b.val; } mi operator-() const { return mi(-val); } mi& operator+=(const mi& m) { if ((val += m.val) >= MOD) val -= MOD; return *this; } mi& operator-=(const mi& m) { if ((val -= m.val) < 0) val += MOD; return *this; } mi& operator*=(const mi& m) { val = (long long)val * m.val % MOD; return *this; } friend mi pow(mi a, long long p) { mi ans = 1; assert(p >= 0); for (; p; p /= 2, a *= a) if (p & 1) ans *= a; return ans; } friend mi inv(const mi& a) { assert(a != 0); return pow(a, MOD - 2); } mi& operator/=(const mi& m) { return (*this) *= inv(m); } friend mi operator+(mi a, const mi& b) { return a += b; } friend mi operator-(mi a, const mi& b) { return a -= b; } friend mi operator*(mi a, const mi& b) { return a *= b; } friend mi operator/(mi a, const mi& b) { return a /= b; } }; int n, ways; string g[2000]; pair<int, int> ans = {MOD, MOD}; bool check(vector<int> deg) { vector<int> v; for (int i = (0); i < (n); ++i) v.push_back(deg[i]); sort(begin(v), end(v)); int sum = 0; for (int i = (0); i < ((int)v.size() - 1); ++i) { sum += v[i]; if (sum == i * (i + 1) / 2) return 0; } return 1; } int main() { cin.sync_with_stdio(0); cin.tie(0); re(n); vector<int> deg(n); for (int i = (0); i < (n); ++i) { re(g[i]); for (int j = (0); j < (n); ++j) if (g[i][j] == 1 ) deg[i]++; } if (check(deg)) { ps(0, 1); exit(0); } for (int i = (0); i < (n); ++i) { for (int j = (0); j < (n); ++j) if (i != j) { if (g[i][j] == 0 ) { deg[j]--; deg[i]++; } else { deg[j]++; deg[i]--; } } ways += check(deg); for (int j = (0); j < (n); ++j) if (i != j) { if (g[i][j] == 0 ) { deg[j]++; deg[i]--; } else { deg[j]--; deg[i]++; } } } if (ways) ps(1, ways); else { assert(n <= 6); pair<int, long long> ans = {MOD, MOD}; for (int i = (0); i < (1 << n); ++i) { vector<int> deg(n); for (int j = (0); j < (n); ++j) for (int k = (0); k < (n); ++k) if (j != k) { int ori = g[j][k] - 0 ; if (i & (1 << j)) ori ^= 1; if (i & (1 << k)) ori ^= 1; deg[j] += ori; } int p = __builtin_popcount(i); if (check(deg)) { if (p < ans.first) ans = {p, 0}; if (p == ans.first) ans.second++; } } if (ans.first == MOD) { ps(-1); exit(0); } for (int i = (1); i < (ans.first + 1); ++i) ans.second *= i; ps(ans.first, ans.second); } } |
#include <bits/stdc++.h> using namespace std; int N, uz[1005], kay; char ar[1005][1005], k[1005]; int kontrol(int a, int say) { for (int i = 1; i <= uz[a] - say + 1; i++) { if (ar[a][i] == k[1]) { int m = 1, j, k1; for (j = i + 1, k1 = 2; j <= uz[a] && k1 <= say && m; j++, k1++) if (ar[a][j] != k[k1]) m = 0; if (m) { return 0; } } } return 1; } int maxs = 0; void oku() { cin >> N; for (int i = 1; i <= N; i++) { scanf( %s , ar[i] + 1); uz[i] = strlen(ar[i] + 1); maxs = max(maxs, uz[i]); } int o = 1, l; k[o] = a ; k[o]--; while (o <= maxs) { l = 1; if (k[o] != z ) k[o]++; else { int p1 = o; while (p1) { if (k[p1] != z ) { k[p1]++; break; } else p1--; } if (!p1) { memset(k, 0, sizeof(k)); o++; for (int i = 1; i <= o; i++) k[i] = a ; } else { p1++; while (p1 <= o) { k[p1] = a ; p1++; } } } l = 1; for (int i = 1; i <= N && l; i++) l = kontrol(i, o); if (l) { printf( %s n , k + 1); return; } } } int main() { oku(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000000 + 7; const int MAX = 100000; map<pair<string, int>, int> F; vector<pair<string, int>> v, ans; pair<string, int> q; set<string> s; int n; vector<int> g[300000]; vector<int> S[300000]; bool used[300000]; bool cmp(int i1, int i2) { return v[i1].second > v[i2].second; } bool qw(int i1, int i2) { return i1 > i2; } int main() { cin >> n; for (int i = (0); i < (n); i++) { cin >> q.first >> q.second; if (!F.count(q)) F[q] = v.size(), v.push_back(q); int V = F[q]; int k; cin >> k; for (int j = (0); j < (k); j++) { cin >> q.first >> q.second; if (!F.count(q)) F[q] = v.size(), v.push_back(q); g[V].push_back(F[q]); } } S[0].push_back(0); used[0] = 1; s.insert(v[0].first); for (int i = (0); i < (n); i++) { sort(S[i].begin(), S[i].end(), cmp); for (int j = (0); j < (S[i].size()); j++) { if (i && !s.count(v[S[i][j]].first)) { s.insert(v[S[i][j]].first); ans.push_back(v[S[i][j]]); } else if (i) continue; for (int k = (0); k < (g[S[i][j]].size()); k++) if (!used[g[S[i][j]][k]]) S[i + 1].push_back(g[S[i][j]][k]), used[g[S[i][j]][k]] = 1; } } sort(ans.begin(), ans.end()); cout << ans.size() << n ; for (int i = (0); i < (ans.size()); i++) cout << ans[i].first << << ans[i].second << endl; return 0; } |
// $Id: c_port_filter.v 1747 2010-01-30 08:17:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// module to filter output port requests based on turn restrictions
module c_port_filter
(route_in_op, inc_rc, route_out_op, error);
`include "c_constants.v"
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of input and output ports on router
parameter num_ports = 5;
// number of adjacent routers in each dimension
parameter num_neighbors_per_dim = 2;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 4;
// filter out illegal destination ports
// (the intent is to allow synthesis to optimize away the logic associated
// with such turns)
parameter restrict_turns = 1;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// ID of current port
parameter port_id = 0;
// current message class
parameter message_class = 0;
// current resource class
parameter resource_class = 0;
// unmasked output port
input [0:num_ports-1] route_in_op;
// if we have reached our destination for the current resource class,
// increment the resource class (unless it's already the highest)
input inc_rc;
// filtered output port
output [0:num_ports-1] route_out_op;
wire [0:num_ports-1] route_out_op;
// internal error condition detected
output error;
wire error;
wire [0:num_ports-1] route_restricted_op;
wire [0:num_ports-1] error_op;
generate
genvar op;
for(op = 0; op < num_ports; op = op + 1)
begin:ops
// packets in the lower resource classes can only go back out through
// the same port they came in on if the current router is the
// destination router for their current resource class (this cannot
// happen for packets in the highest resource class); for the
// flattened butterfly, this applies to all links in the same
// dimension; likewise, in the case of dimension-order routing,
// ports for dimensions that were already traversed can only be used
// when changing resource classes
if(((op < (num_ports - num_nodes_per_router)) &&
((routing_type == `ROUTING_TYPE_DOR) &&
((((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) &&
(op == port_id)) ||
((connectivity == `CONNECTIVITY_FULL) &&
((op / num_neighbors_per_dim) ==
(port_id / num_neighbors_per_dim))) ||
((port_id < (num_ports - num_nodes_per_router)) &&
(((dim_order == `DIM_ORDER_ASCENDING) &&
((op / num_neighbors_per_dim) <
(port_id / num_neighbors_per_dim))) ||
((dim_order == `DIM_ORDER_DESCENDING) &&
((op / num_neighbors_per_dim) >
(port_id / num_neighbors_per_dim)))))))))
begin
if(resource_class == (num_resource_classes - 1))
begin
assign route_restricted_op[op] = 1'b0;
assign error_op[op] = route_in_op[op];
end
else
begin
// we could mask this by inc_rc; however, the goal of port
// filtering is to allow synthesis to take advantage of
// turn restrictions in optimizing the design, so from this
// point of view, masking here would be counterproductive;
// also, note that we don't actually recover from illegal
// port requests -- packets just remain in the input buffer
// forever; consequently, we save the gate and don't mask
// here
assign route_restricted_op[op]
= route_in_op[op] /* & inc_rc*/;
assign error_op[op] = route_in_op[op] & ~inc_rc;
end
end
// only packets in the highest resource class can go to the
// injection/ejection ports; also, a packet coming in on an
// injection/ejection port should never exit the router on the same
// injection/ejection port
else if((op >= (num_ports - num_nodes_per_router)) &&
((resource_class < (num_resource_classes - 1)) ||
(op == port_id)))
begin
assign route_restricted_op[op] = 1'b0;
assign error_op[op] = route_in_op[op];
end
// remaining port requests are valid
else
begin
assign route_restricted_op[op] = route_in_op[op];
assign error_op[op] = 1'b0;
end
end
if(restrict_turns)
begin
assign route_out_op = route_restricted_op;
assign error = |error_op;
end
else
begin
assign route_out_op = route_in_op;
assign error = 1'b0;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_FUNCTIONAL_V |
// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0______126.455____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module design_1_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_design_1_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_0_0;
wire clkfbout_buf_design_1_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
.I (clkfbout_design_1_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_0_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; struct __s { __s() { if (1) { ios_base::Init i; cin.sync_with_stdio(0); cin.tie(0); } } ~__s() { if (!1) fprintf(stderr, Execution time: %.3lf s. n , (double)clock() / CLOCKS_PER_SEC); long long n; cin >> n; } } __S; int main(void) { long long n, m; cin >> n; vector<long long> a(n); for (long long i = 0; i < (long long)(n); i++) { cin >> a[i]; } cin >> m; long long b = 0; for (long long i = 0; i < (long long)(m); i++) { long long x; cin >> x; b += x - 1; } vector<long long> c; while (c.size() < 3 * max(m, n)) { for (long long i = 0; i < (long long)(n - 1); i++) { c.push_back(i); } for (long long i = 0; i < (long long)(n - 1); i++) { c.push_back(n - 1 - i); } } long long d = 0; for (long long i = 0; i < (long long)(m); i++) { b -= c[i]; if (i) d += abs(a[c[i]] - a[c[i - 1]]); } set<long long> ans; for (long long i = m; i < c.size(); i++) { if (b == 0) { ans.insert(d); } b -= c[i]; b += c[i - m]; d -= abs(a[c[i - m]] - a[c[i - m + 1]]); d += abs(a[c[i]] - a[c[i - 1]]); } if (ans.size() != 1) cout << -1 << n ; else cout << *ans.begin() << n ; return 0; } |
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