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#include <bits/stdc++.h> void solve() { int n; std::cin >> n; std::stack<int> q; int a = 0; int cur = 1; n += n; while (n--) { std::string s; std::cin >> s; if (s[0] == r ) { if (!q.empty() && q.top() != cur) { while (!q.empty()) q.pop(); ++a; } if (!q.empty()) q.pop(); ++cur; } else { int x; std::cin >> x; q.push(x); } } std::cout << a; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); solve(); return 0; } |
// This tests part selects of 2-value logic vectors through
// module ports. This is not supported in SystemVerilog, but
// we expect it to work as an Icarus Verilog extension, as
// long as all the bits of the 2-value are singly driven.
module main;
reg bit [5:0] a, b;
wire bit [6:0] sum;
wire bit c2, c4;
sub b10 (.c_i(1'b0), .a(a[1:0]), .b(b[1:0]), .out(sum[1:0]), .c_o(c2));
sub b32 (.c_i(c2), .a(a[3:2]), .b(b[3:2]), .out(sum[3:2]), .c_o(c4));
sub b54 (.c_i(c4), .a(a[5:4]), .b(b[5:4]), .out(sum[5:4]), .c_o(sum[6]));
reg bit [6:0] idxa, idxb;
initial begin
for (idxa = 0 ; idxa < 'b1_000000 ; idxa = idxa+1) begin
for (idxb = 0 ; idxb < 'b1_000000 ; idxb = idxb+1) begin
a = idxa;
b = idxb;
#1 /* wait for devices to settle */;
if (idxa + idxb != sum) begin
$display("FAILED: %0d + %0d --> %0d", a, b, sum);
$stop;
end
end
end // for (idxa = 0 ; idxa < 'b1_000000 ; idxa = idxa+1)
$display("PASSED");
$finish;
end // initial begin
endmodule // main
module sub (input wire bit c_i, input wire bit[1:0] a, b,
output wire bit [1:0] out, output wire bit c_o);
assign {c_o, out} = {1'b0, a} + {1'b0, b} + {2'b00, c_i};
endmodule // sub
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t != 0) { int n; cin >> n; long long m = (n - 1) / 2; long long sum = m * (m + 1) * (2 * m + 1) / 6; long long raspuns = 8 * sum; cout << raspuns << n ; t--; } } |
#include <bits/stdc++.h> using namespace std; int main() { string x; cin >> x; string ans, in, dec, exp; int flag = 0; for (int i = 0; i < x.length(); i++) { if (x[i] == . ) flag = 1; else if (x[i] == e ) flag = 2; else if (flag == 0) in += x[i]; else if (flag == 1) dec += x[i]; else if (flag == 2) exp += x[i]; } int e = stoi(exp); ans += in; if (e <= dec.length()) { ans += dec.substr(0, e); if (e < dec.length()) { ans += . ; ans += dec.substr(e, dec.length()); } } else { ans += dec; ans += string(e - dec.length(), 0 ); } flag = 0; if (dec.length() < 2 && stoi(dec) == 0 && e == 0) ans = in; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e15; class LazySegmentTree { private: int n; vector<pair<long long, int>> node; vector<long long> lazy; public: LazySegmentTree(vector<long long> v) { n = 1; while (n < v.size()) n *= 2; node.resize(2 * n - 1, make_pair(-INF, 0)); lazy.resize(2 * n - 1, 0); for (int i = 0; i < v.size(); i++) node[i + n - 1] = make_pair(v[i], i); for (int i = n - 2; i >= 0; i--) node[i] = max(node[2 * i + 1], node[2 * i + 2]); } void eval(int k, int l, int r) { if (lazy[k] != 0) { node[k].first += lazy[k]; if (r - l > 1) { lazy[2 * k + 1] += lazy[k]; lazy[2 * k + 2] += lazy[k]; } lazy[k] = 0; } } void add(int a, int b, long long x, int k = 0, int l = 0, int r = -1) { if (r < 0) r = n; eval(k, l, r); if (b <= l || r <= a) return; if (a <= l && r <= b) { lazy[k] += x; eval(k, l, r); } else { add(a, b, x, 2 * k + 1, l, (r + l) / 2); add(a, b, x, 2 * k + 2, (r + l) / 2, r); node[k] = max(node[2 * k + 1], node[2 * k + 2]); } } pair<long long, int> getMax(int a, int b, int k = 0, int l = 0, int r = -1) { if (r < 0) r = n; eval(k, l, r); if (b <= l || r <= a) return make_pair(-INF, 0); if (a <= l && r <= b) { return node[k]; } pair<long long, int> vl, vr; vl = getMax(a, b, 2 * k + 1, l, (l + r) / 2); vr = getMax(a, b, 2 * k + 2, (l + r) / 2, r); return max(vl, vr); } }; int main() { cin.tie(0); ios::sync_with_stdio(false); int N; cin >> N; vector<long long> X(N), Y(N), C(N); for (int i = 0; i < (N); ++i) cin >> X[i] >> Y[i] >> C[i]; vector<long long> v; map<long long, int> mp; map<int, long long> rev; for (int i = 0; i < N; i++) { v.push_back(X[i]); v.push_back(Y[i]); } sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); for (int i = 0; i < v.size(); i++) { mp[v[i]] = i; rev[i] = v[i]; } int V = v.size(); vector<vector<int>> rig(V), lef(V); for (int i = 0; i < N; i++) { lef[mp[min(X[i], Y[i])]].push_back(i); rig[mp[max(X[i], Y[i])]].push_back(i); } vector<long long> input(V, 0); for (int i = 0; i < (N); ++i) input[V - 1] += C[i]; for (int i = V - 2; i >= 0; i--) { input[i] = input[i + 1]; for (auto ng : rig[i + 1]) input[i] -= C[ng]; } for (int i = 0; i < V; i++) input[i] -= rev[i]; LazySegmentTree seg(input); vector<int> del(N, 0); long long ans = 0; int x = 2000000000; int y = x; for (int i = 0; i < V; i++) { auto f = seg.getMax(i, V); long long val = f.first; if (ans < val + rev[i]) { ans = val + rev[i]; x = rev[i]; y = rev[f.second]; } for (auto n : lef[i]) { if (del[n]) continue; del[n] = 1; seg.add(mp[max(X[n], Y[n])], V, -C[n]); } } cout << ans << endl; cout << min(x, y) << << min(x, y) << << max(y, x) << << max(y, x) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_SYMBOL_V
`define SKY130_FD_SC_MS__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, k, x[1010], dp[1010][1010], sm[1010]; long long solve(long long gap) { dp[0][0] = 1, x[0] = -200000; for (long long i = 1; i <= k; ++i) { for (long long j = 0; j <= n; ++j) sm[j] = j == 0 ? dp[i - 1][j] : (dp[i - 1][j] + sm[j - 1]) % 998244353; long long pos = 0; for (long long j = 1; j <= n; ++j) { while (x[j] - x[pos + 1] >= gap) pos++; dp[i][j] = sm[pos]; } } long long sum = 0; for (long long i = 1; i <= n; ++i) sum = (sum + dp[k][i]) % 998244353; return sum; } int32_t main() { cin.tie(0), cout.sync_with_stdio(0); cin >> n >> k; for (long long i = 1; i <= n; ++i) cin >> x[i]; sort(x + 1, x + 1 + n); long long dis = 100000 / (k - 1), pre = solve(1), ans = 0; for (long long i = 2; i <= dis + 5; ++i) { long long now = solve(i); ans = (ans + (pre - now + 998244353) * (i - 1)) % 998244353; pre = now; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 22; int n, mn = N + 1, q; int par[N], ans[N]; bool mark[N]; vector<int> G[N]; void dfs(int v, int p, int rr) { rr = min(rr, v); ans[v] = rr; par[v] = p; for (int i = 0; i < (G[v].size()); i++) { int u = G[v][i]; if (u == p) continue; dfs(u, v, rr); } } int main() { cin >> n >> q; for (int i = 0; i < (n - 1); i++) { int u, v; scanf( %d%d , &u, &v); u--, v--; G[u].push_back(v), G[v].push_back(u); } q--; int x, tp, last = -1; cin >> tp >> x; x = (x + last + 1) % n; mark[x] = true; dfs(x, -1, x); for (int Q = 0; Q < (q); Q++) { scanf( %d%d , &tp, &x); x = (x + last + 1) % n; if (tp == 1) { while (!mark[x]) { mark[x] = true; mn = min(mn, x); x = par[x]; } } else { printf( %d n , min(ans[x], mn) + 1); last = min(ans[x], mn); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int dp[1 << 23]; vector<pair<int, int> > p[23]; int a[100]; int main() { int n, res = 1000; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; for (int j = 0; j < i; j++) for (int k = j; k < i; k++) if (a[j] + a[k] == a[i]) p[i].push_back(make_pair(j, k)); } memset(dp, 125, sizeof(dp)); dp[1] = 1; for (int i = 1; i < n; i++) { for (int j = 0; j < (1 << (i - 1)); j++) { int jj = j | (1 << (i - 1)); for (int k = 0; k < p[i].size(); k++) { int a = p[i][k].first, b = p[i][k].second; if (!(jj & (1 << a)) || !(jj & (1 << b))) continue; int msk = jj | (1 << i); dp[msk] = min(dp[msk], dp[jj] + 1); for (int del = 0; del < i; del++) if (msk & (1 << del)) dp[msk ^ (1 << del)] = min(dp[msk ^ (1 << del)], dp[jj]); } } } for (int i = 0; i < 1 << n; i++) if ((i & (1 << (n - 1)))) res = min(res, dp[i]); cout << (res == 1000 ? -1 : res) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; cin >> s; string ans = ; int cnt = 0; for (int i = n - 1; i >= 0; i--) { if (s[i] == 1 ) { if (cnt > 0) { while (i >= 0 && s[i] == 1 ) i--; cnt = 1; i++; } else ans += 1 ; } else { cnt++; } } while (cnt--) ans += 0 ; reverse(ans.begin(), ans.end()); cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) solve(); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`timescale 1ns / 1ps
module t_clk (/*AUTOARG*/
// Outputs
passed,
// Inputs
fastclk, clk, reset_l
);
input fastclk;
input clk;
input reset_l;
output passed; reg passed; initial passed = 0;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
//$write("CLK1 %x\n", reset_l);
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_clk: Running\n",$time);
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
//$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
//$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
passed <= 1'b1;
$write("[%0t] t_clk: Passed\n",$time);
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
//$write("CLK4 %x\n", reset_l);
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
|
//Blitter minterm function generator
//The minterm function generator takes <ain>,<bin> and <cin>
//and checks every logic combination against the LF control byte.
//If a combination is marked as 1 in the LF byte,the ouput will
//also be 1,else the output is 0.
module agnus_blitter_minterm
(
input [7:0] lf, //LF control byte
input [15:0] ain, //A channel in
input [15:0] bin, //B channel in
input [15:0] cin, //C channel in
output [15:0] out //function generator output
);
reg [15:0] mt0; //minterm 0
reg [15:0] mt1; //minterm 1
reg [15:0] mt2; //minterm 2
reg [15:0] mt3; //minterm 3
reg [15:0] mt4; //minterm 4
reg [15:0] mt5; //minterm 5
reg [15:0] mt6; //minterm 6
reg [15:0] mt7; //minterm 7
//Minterm generator for each bit. The code inside the loop
//describes one bit. The loop is 'unrolled' by the
//synthesizer to cover all 16 bits in the word.
integer j;
always @(ain or bin or cin or lf)
for (j=15; j>=0; j=j-1)
begin
mt0[j] = ~ain[j] & ~bin[j] & ~cin[j] & lf[0];
mt1[j] = ~ain[j] & ~bin[j] & cin[j] & lf[1];
mt2[j] = ~ain[j] & bin[j] & ~cin[j] & lf[2];
mt3[j] = ~ain[j] & bin[j] & cin[j] & lf[3];
mt4[j] = ain[j] & ~bin[j] & ~cin[j] & lf[4];
mt5[j] = ain[j] & ~bin[j] & cin[j] & lf[5];
mt6[j] = ain[j] & bin[j] & ~cin[j] & lf[6];
mt7[j] = ain[j] & bin[j] & cin[j] & lf[7];
end
//Generate function generator output by or-ing all
//minterms together.
assign out = mt0 | mt1 | mt2 | mt3 | mt4 | mt5 | mt6 | mt7;
endmodule
|
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
/* fdisplay3 - check that $fdisplay rejects bogus first arguments */
module fdisplay3;
initial begin
// This error is now caught at compile time so this message will not
// be printed.
//
// $display("expect compile or runtime error from bad $fdisplay args:");
$fdisplay(fdisplay3, "bogus message");
$finish;
end // initial begin
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1000006], n, v[1000006], t[1000006]; void uma(int x) { int i; for (i = 0; i < n; i++) v[i] = i; for (; x; x >>= 1) { if (x & 1) { for (i = 0; i < n; i++) v[i] = a[v[i]]; } for (i = 0; i < n; i++) t[i] = a[a[i]]; for (i = 0; i < n; i++) a[i] = t[i]; } for (i = 0; i < n; i++) a[i] = v[i]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int m, i, d, k, j, l, p; string s, os; cin >> s >> m; os = s; n = s.size(); for (i = 0; i < m; i++) { cin >> k >> d; p = 0; for (j = 0; j < d; j++) for (l = j; l < k; l += d) a[p++] = l; for (j = 0; j < k - 1; j++) a[j] = a[j + 1]; for (j = k - 1; j < n - 1; j++) a[j] = j + 1; a[j] = 0; uma(n - k + 1); for (j = 0; a[j]; j++) { } p = 0; for (; j < n; j++) os[p++] = s[a[j]]; for (j = 0; a[j]; j++) os[p++] = s[a[j]]; s = os; cout << s << n ; } } |
#include <bits/stdc++.h> using namespace std; vector<int> l[1000000]; int main() { int n; cin >> n; int a[n], b[n], c[n]; for (int i = 0; i < n; i++) { cin >> a[i]; l[a[i]].push_back(i + 1); } int q = 0; for (int i = 0; i < n; i++) { int j = a[i]; if (a[j - 1] != j) q = 1; } int m = 1; for (int i = 1; i <= n; i++) { int z = 0; for (std::vector<int>::iterator it = l[i].begin(); it != l[i].end(); ++it) { b[*it - 1] = m; z = 1; } if (z == 1) { c[m - 1] = i; m++; } } if (q == 0) { cout << m - 1 << endl; for (int i = 0; i < n; i++) { cout << b[i] << ; } cout << endl; for (int i = 0; i < m - 1; i++) { cout << c[i] << ; } } else cout << -1 ; } |
module Keyboard_driver(clk, reset, ready_pulse, Keyboard_Data, ACK, STB, DAT_O);
input clk;
input reset;
input ready_pulse;
input [7: 0] Keyboard_Data;
input STB;
output ACK;
output [31: 0] DAT_O;
reg [31: 0] data_hold = 0;
reg [7: 0] data_cooked;
reg [23: 0] data_cnt = 0;
reg f0 = 0;
assign DAT_O = {data_cooked, data_cnt};
assign ACK = STB;
always @(posedge ready_pulse) begin
if (Keyboard_Data == 8'hf0)
f0 <= 1;
else begin
if (!f0) begin
data_hold <= Keyboard_Data;
data_cnt <= data_cnt + 1;
end else
f0 <= 0;
end
end
always @* begin
case(data_hold)
8'h16: data_cooked = 49;// 1
8'h1E: data_cooked = 50;// 2
8'h26: data_cooked = 51;// 3
8'h25: data_cooked = 52;// 4
8'h2E: data_cooked = 53;// 5
8'h36: data_cooked = 54;// 6
8'h3D: data_cooked = 55;// 7
8'h3E: data_cooked = 56;// 8
8'h46: data_cooked = 57;// 9
8'h45: data_cooked = 48;// 0
8'h4E: data_cooked = 45;// -
8'h55: data_cooked = 43;// +
8'h15: data_cooked = 113;// q
8'h1D: data_cooked = 119;// w
8'h24: data_cooked = 101;// e
8'h2D: data_cooked = 114;// r
8'h2C: data_cooked = 116;// t
8'h35: data_cooked = 121;// y
8'h3C: data_cooked = 117;// u
8'h43: data_cooked = 105;// i
8'h44: data_cooked = 111;// o
8'h4D: data_cooked = 112;// p
8'h54: data_cooked = 91;// [
8'h5B: data_cooked = 93;// ]
8'h1C: data_cooked = 97;// a
8'h1B: data_cooked = 115;// s
8'h23: data_cooked = 100;// d
8'h2B: data_cooked = 102;// f
8'h34: data_cooked = 103;// g
8'h33: data_cooked = 104;// h
8'h3B: data_cooked = 106;// j
8'h42: data_cooked = 107;// k
8'h4B: data_cooked = 108;// l
8'h4C: data_cooked = 59;// ;
8'h52: data_cooked = 92;// \
8'h1A: data_cooked = 122;// z
8'h22: data_cooked = 120;// x
8'h21: data_cooked = 99;// c
8'h2A: data_cooked = 118;// v
8'h32: data_cooked = 98;// b
8'h31: data_cooked = 110;// n
8'h3A: data_cooked = 109;// m
8'h41: data_cooked = 44;// ,
8'h49: data_cooked = 46;// .
8'h4A: data_cooked = 47;// /
8'h29: data_cooked = 32;//
8'h66: data_cooked = 8; // Backspace
8'h5A: data_cooked = 10;// Enter to '\n'
default: data_cooked = 0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<long long> > g; vector<vector<pair<long long, long long> > > updates; vector<long long> tree; vector<long long> ans; long long n; void update(long long v, long long l, long long r, long long al, long long ar, long long val) { if (al <= l && ar >= r) { tree[v] += val; return; } if (al <= r && ar >= l) { update(v * 2, l, (r + l) / 2, al, ar, val); update(v * 2 + 1, (r + l) / 2 + 1, r, al, ar, val); } } long long answer(long long v, long long l, long long r, long long ind) { if (l == r) { return tree[v]; } if (ind <= (r + l) / 2) { return tree[v] + answer(v * 2, l, (r + l) / 2, ind); } else { return tree[v] + answer(v * 2 + 1, (r + l) / 2 + 1, r, ind); } } void dfs(long long v, long long pred = -1, long long h = 0) { for (long long i = 0; i < updates[v].size(); i++) { update(1, 0, n - 1, h, min(updates[v][i].second + h, n), updates[v][i].first); } ans[v] = answer(1, 0, n - 1, h); for (long long i = 0; i < g[v].size(); i++) { if (g[v][i] != pred) { dfs(g[v][i], v, h + 1); } } for (long long i = 0; i < updates[v].size(); i++) { update(1, 0, n - 1, h, min(updates[v][i].second + h, n), -updates[v][i].first); } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; tree.resize(n * 4); g.resize(n); ans.resize(n); updates.resize(n); for (long long i = 0; i < n - 1; i++) { long long x, y; cin >> x >> y; x--; y--; g[x].push_back(y); g[y].push_back(x); } long long m; cin >> m; for (long long i = 0; i < m; i++) { long long v, x, d; cin >> v >> d >> x; v--; updates[v].push_back({x, d}); } dfs(0); for (long long i = 0; i < ans.size(); i++) { cout << ans[i] << ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`timescale 1ns / 1ps
module t (/*AUTOARG*/
// Outputs
passed,
// Inputs
clk, fastclk, reset_l
);
input clk;
input fastclk;
input reset_l;
output passed;
// Combine passed signals from each sub signal
// verilator lint_off MULTIDRIVEN
wire [20:0] passedv;
// verilator lint_on MULTIDRIVEN
wire passed = &passedv;
assign passedv[0] = 1'b1;
assign passedv[1] = 1'b1;
assign passedv[2] = 1'b1;
assign passedv[3] = 1'b1;
assign passedv[4] = 1'b1;
assign passedv[5] = 1'b1;
t_inst tinst
(.passed (passedv[6]),
/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk));
t_param tparam
(.passed (passedv[7]),
/*AUTOINST*/
// Inputs
.clk (clk));
assign passedv[8] = 1'b1;
assign passedv[9] = 1'b1;
assign passedv[10] = 1'b1;
t_clk tclk
(.passed (passedv[11]),
/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.clk (clk),
.reset_l (reset_l));
assign passedv[12] = 1'b1;
assign passedv[13] = 1'b1;
t_chg tchg
(.passed (passedv[14]),
/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk));
assign passedv[15] = 1'b1;
assign passedv[16] = 1'b1;
assign passedv[17] = 1'b1;
assign passedv[18] = 1'b1;
assign passedv[19] = 1'b1;
t_netlist tnetlist
(.passed (passedv[20]),
.also_fastclk (fastclk),
/*AUTOINST*/
// Inputs
.fastclk (fastclk));
endmodule
|
#include <bits/stdc++.h> int main() { int t, x, i, z, n, max = 0, s = 0, a[1000], m; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) { scanf( %d , &a[i]); s += a[i]; if (max < a[i]) { max = a[i]; } } max = max + m; s = s + m; if (s % n == 0) { x = s / n; } else { x = (s / n) + 1; } for (i = 0; i < n; i++) { if (x < a[i]) { x = a[i]; } } printf( %d %d , x, max); } |
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; cout << s; reverse(s.begin(), s.end()); cout << s; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_BEHAVIORAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int cal(vector<int> q, int n, int m) { int sum = 0; for (int i = (int)0; i < (int)n; ++i) { for (int j = (int)i; j < (int)n; ++j) { int mn = INT_MAX; for (int k = (int)i; k < (int)j + 1; ++k) mn = ((mn) < (q[k]) ? (mn) : (q[k])); sum += mn; } } return sum; } int main() { int i, j, n, t; int m; scanf( %d , &n); scanf( %d , &m); vector<int> q; for (int i = (int)1; i < (int)n + 1; ++i) q.push_back(i); int mx = 0; do { mx = ((mx) > (cal(q, n, m)) ? (mx) : (cal(q, n, m))); } while (next_permutation(q.begin(), q.end())); sort(q.begin(), q.end()); int cnt = 0; do { if (cal(q, n, m) == mx) cnt++; if (cnt == m) break; } while (next_permutation(q.begin(), q.end())); for (int i = (int)0; i < (int)n; ++i) printf( %d , q[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long temp; long long a[n]; int fg = 0; for (int(i) = 0; (i) < (n); (i)++) { cin >> temp; fg++; a[i] = temp; } sort(a, a + n); for (int(i) = 0; (i) < (n - 1); (i)++) { if (a[i] == a[i + 1]) continue; if (a[i + 1] < 2 * a[i]) { cout << YES n ; return 0; } } cout << NO n ; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_response_handler #(
parameter ID_WIDTH = 3)(
input clk,
input resetn,
input bvalid,
output bready,
input [1:0] bresp,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input enable,
output reg enabled,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
`include "resp.vh"
`include "inc_id.vh"
assign resp_resp = bresp;
assign resp_eot = eot;
wire active = id != request_id;
assign bready = active && resp_ready;
assign resp_valid = active && bvalid;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else if (enable == 1'b1) begin
enabled <= 1'b1;
end else if (request_id == id) begin
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else if (bready == 1'b1 && bvalid == 1'b1) begin
id <= inc_id(id);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long ans = 0; int n; cin >> n; char str[65000]; cin >> str; for (int i = 0; i < n; i++) { if ((str[i] - 0 ) % 2 == 0) { ans += i + 1; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; constexpr int N = 23; int n, m, u, v, adj[N], hamsaye[1 << N], ans = N, ans2; bool connected[1 << N]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; if (2 * m == n * (n - 1)) { cout << 0 << n ; return 0; } for (int i = 0; i < m; i++) { cin >> u >> v; u--, v--; adj[u] ^= 1 << v; adj[v] ^= 1 << u; } for (int i = 0; i < n; i++) adj[i] ^= (1 << i); connected[0] = true; for (int mask = 1; mask < (1 << n); mask++) { if (__builtin_popcount(mask) == 1) { connected[mask] = true; continue; } for (int i = 0; i < n; i++) { if ((adj[i] & (mask ^ (1 << i))) && connected[mask ^ (1 << i)]) connected[mask] = true; } } for (int mask = 1; mask < (1 << n); mask++) { hamsaye[mask] = adj[__builtin_ctz(mask)] | hamsaye[mask ^ (1 << __builtin_ctz(mask))]; if (connected[mask] && __builtin_popcount(hamsaye[mask]) == n) { if (__builtin_popcount(mask) < ans) { ans = __builtin_popcount(mask); ans2 = mask; } } } cout << ans << n ; for (int i = 0; i < n; i++) if (ans2 & (1 << i)) cout << i + 1 << ; cout << n ; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ddr_pad_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ddr_pad_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int inf = (int)2e9; const long long md = 1000000007; int dx[] = {1, -1, 0, 0}, dy[] = {0, 0, 1, -1}; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<pair<int, int> > v(n); for (int i = 0; i < (int)n; i++) { cin >> v[i].first >> v[i].second; } sort((v).begin(), (v).end(), [&](pair<int, int>& a, pair<int, int>& b) { return abs(a.first) + abs(a.second) < abs(b.first) + abs(b.second); }); vector<string> out; for (pair<int, int>& p : v) { int first = p.first, second = p.second; if (first) { out.emplace_back( 1 + to_string(abs(first)) + + (first > 0 ? R : L )); } if (second) { out.emplace_back( 1 + to_string(abs(second)) + + (second > 0 ? U : D )); } out.emplace_back(to_string(2)); if (second) { out.emplace_back( 1 + to_string(abs(second)) + + (second < 0 ? U : D )); } if (first) { out.emplace_back( 1 + to_string(abs(first)) + + (first < 0 ? R : L )); } out.emplace_back(to_string(3)); } cout << (int)(out.size()) << n ; for (string& s : out) cout << s << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int a[205], max1, n, k, t; int main() { cin >> t; while (t > 0) { t--; scanf( %d%d , &n, &k); for (int i = 0; i < k; i++) scanf( %d , &a[i]); max1 = 0; if (k == 1) cout << max(n - a[0] + 1, a[0]) << endl; else { for (int i = 1; i < k; i++) { if ((a[i] - a[i - 1]) / 2 + 1 > max1) max1 = (a[i] - a[i - 1]) / 2 + 1; } int d = max(n - a[k - 1] + 1, a[0]); if (d > max1) cout << d << endl; else { cout << max1 << endl; } } } return 0; } |
`ifndef VCDFILE
`define VCDFILE "out.vcd"
`endif
`timescale 1 ms / 1 ps
module test;
/* Make a regular pulsing clock. */
reg clk = 0;
always #2 clk = !clk;
reg [3:0] in;
wire [3:0] out;
wire [4:0] vec0;
wire [4:0] vec1;
top uut (.clk(clk), .cen(in[0]), .rst(in[1]), .ina(in[2]), .inb(in[3]),
.outa(out[0]), .outb(out[1]), .outc(out[2]), .outd(out[3]),
.vec0(vec0), .vec1(vec1));
initial begin
$dumpfile(`VCDFILE);
$dumpvars(1, uut);
#3; // get between edges
in <= 4'b0010;
#1; //negedge
if (out != 4'b1000) $error("initial reset %b", out);
#1; // between
in <= 4'b0000;
#1; //posedge
#1; //between
if (out != 4'b1000) $error("set and reg1 %b", out);
#1; //negedge
#1; //between
if (out != 4'b0000) $error("set and reg1 %b", out);
in <= 4'b1101;
#1; //posedge
#1; // b
if (vec0 != 5'b00001) $error("vec0 %b", out);
#1; // neg
#1; // b
if (vec1 != 5'b00001) $error("vec1 %b", out);
#1; // pos
#1; // b
repeat (3)
#4; // full cycle
if (out != 4'b0000) $error("set and reg1 %b", out);
#1; // neg
#1; // b
if (out != 4'b0100) $error("clock to out %b", out);
#1; // pos
#1; // b
if (out != 4'b0111) $error("clock to out %b", out);
#1; // neg
#1; // b
#1; // pos
#1; // b
in <= 4'b0010;
$display("reseting with cen and ina off");
#1; // neg
if (out != 4'b1110) $error("clock to out %b", out);
#1; // b
in <= 4'b0111;
$display("reseting with cen and ina");
#1; // pos
#1; // b
if (vec0 != 5'b00000) $error("vec0 %b", vec0);
if (vec1 != 5'b11111) $error("vec1 %b", vec1);
#1; // neg
#1; // b
if (vec0 != 5'b00000) $error("vec0 %b", vec0);
if (vec1 != 5'b00001) $error("vec1 %b", vec1);
$dumpflush;
$finish;
end // initial begin
endmodule // test
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_FUNCTIONAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int r, c, n, k; cin >> r >> c >> n >> k; int x[n], y[n], res = 0, xi, yi; for (int i = 0; i < n; i++) { cin >> xi >> yi; x[i] = xi - 1; y[i] = yi - 1; } for (int i = 0; i < r; i++) { for (int j = 0; j < c; j++) { for (int i2 = i; i2 < r; i2++) { for (int j2 = j; j2 < c; j2++) { int violasenimg = 0; for (int v = 0; v < n; v++) { if (i <= x[v] && x[v] <= i2 && j <= y[v] && y[v] <= j2) violasenimg++; } if (violasenimg >= k) res++; } } } } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; void process() { vector<vector<char> > d(8, vector<char>(8)); int x1 = 8, y1 = 8, x2 = 8, y2 = 8; vector<vector<pair<int, int> > > steps( 8, vector<pair<int, int> >(8, make_pair(-INF, -INF))); for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) { cin >> d[i][j]; if (d[i][j] == K ) if (x1 == 8) { x1 = j; y1 = i; } else { x2 = j; y2 = i; } } for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) { if (abs(x1 - j) % 4 + abs(y1 - i) % 4 == 0) steps[i][j].first = 0; if (abs(x1 - j) % 4 == 2 && abs(y1 - i) % 4 == 2) steps[i][j].first = 1; if (abs(x2 - j) % 4 + abs(y2 - i) % 4 == 0) steps[i][j].second = 0; if (abs(x2 - j) % 4 == 2 && abs(y2 - i) % 4 == 2) steps[i][j].second = 1; } for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) if (steps[i][j].first == steps[i][j].second && steps[i][j].first >= 0 && d[i][j] != # ) { cout << YES << endl; return; } cout << NO << endl; return; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) process(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__TAP_PP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tap (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long small = 1298173; int n, m, a = 1, b = 2; void step() { if (a == 1 and b == n - 1) { a++; b = a + 1; } else if (b < n) { b++; } else { a++; b = a + 1; } } int main() { ios_base::sync_with_stdio(0); cin.tie(); cin >> n >> m; if (m == 1) { cout << 2 2 n ; cout << 1 << n << 2 n ; return 0; } cout << 2 << << small << n ; cout << 1 << << n << 2 << n ; small -= 2; int counter = n - 2; while (counter > 1) { cout << a << << b << << 10 << n ; small -= 10; step(); counter--; } cout << a << << b << << small << n ; step(); m -= (n - 1); while (m > 0) { cout << a << << b << << 1298183 << n ; step(); m--; } return 0; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A synchronization module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
// while deassertion is synchronized to the clock.
module SyncResetA (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK or `BSV_RESET_EDGE IN_RST )
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY {RSTDELAY+1 {`BSV_RESET_VALUE}} ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK or `BSV_RESET_EDGE IN_RST )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // SyncResetA
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 5; const long long M = 1e9 + 7; const long long inf = 1e18 + 5; vector<int> prefix_function(string &s) { int n = s.size(); vector<int> pre(n); int pos = 0; pre[0] = 0; for (int i = 1; i < n; i++) { while (pos and s[pos] != s[i]) pos = pre[pos - 1]; if (s[pos] == s[i]) pos++; pre[i] = pos; } return pre; } int main() { string s, t; cin >> t >> s; int n = s.size(); vector<int> pre = prefix_function(s); int a[n][26]; for (int i = 0; i < n; i++) { for (int c = 0; c < 26; c++) { if (i and s[i] != a + c) a[i][c] = a[pre[i - 1]][c]; else a[i][c] = i + (s[i] == a + c); } } int tz = t.size(); int dp[tz + 1][n]; memset(dp, -1, sizeof(dp)); dp[0][0] = 0; for (int i = 0; i < tz; i++) { for (int j = 0; j < n; j++) { if (dp[i][j] != -1) { if (t[i] == ? ) { for (int ch = 0; ch < 26; ch++) { int val = a[j][ch]; if (val == n) dp[i + 1][pre[n - 1]] = max(dp[i + 1][n - 1], dp[i][j] + 1); else dp[i + 1][val] = max(dp[i + 1][val], dp[i][j]); } } else { int val = a[j][t[i] - a ]; if (val == n) dp[i + 1][pre[n - 1]] = max(dp[i + 1][n - 1], dp[i][j] + 1); else dp[i + 1][val] = max(dp[i + 1][val], dp[i][j]); } } } } int ans = 0; for (int i = 0; i < n; i++) ans = max(ans, dp[tz][i]); printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; int n, in[100010], cnt, dyn[100010]; void check() { if (cnt < 2) { printf( %d n , cnt); exit(0); } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &in[i]); for (int i = n - 1; i >= 0; i--) dyn[i] = dyn[i + 1] + (in[i] == 0 ? 1 : 0); if (n == 2) { if (in[0] == 0 && in[1] != 0) printf( 1 n ); else printf( 0 n ); return 0; } if (dyn[0] > 1) { int ans = INF; if (dyn[0] == n) ans = min(ans, 0); if (dyn[1] >= n - 2) ans = min(ans, n - 1 - dyn[1]); if (dyn[2] == n - 2) ans = min(ans, n - 2); if (ans < 2) printf( %d n , ans); else printf( 2 n ); return 0; } bool t = true; for (int i = 2; i < n; i++) if (in[i] * in[i - 2] != in[i - 1] * in[i - 1]) t = false; if (t) { printf( 0 n ); return 0; } if (n == 3) { if (in[1] == 0) goto l; } t = true; for (int i = 2; i < n; i++) if (in[i] * in[1] != in[2] * in[i - 1]) t = false; if (t) { printf( 1 n ); return 0; } l:; cnt = 0; for (int i = 1; i < n; i++) { if (in[i] * in[0] != in[1] * in[i - 1]) { cnt++; if (i < n - 1 && in[i + 1] * in[0] != in[1] * in[i - 1]) cnt++; i++; } } check(); cnt = 0; for (int i = 1; i < n; i++) { if (in[i] * in[1] != in[2] * in[i - 1]) { cnt++; if (i < n - 1 && in[i + 1] * in[1] != in[2] * in[i - 1]) cnt++; i++; } } check(); cnt = 0; for (int i = 1; i < n; i++) { if (in[i] * in[0] != in[2] * in[i - 1]) { cnt++; if (i < n - 1 && in[i + 1] * in[0] != in[2] * in[i - 1]) cnt++; i++; } } check(); printf( 2 n ); return 0; } |
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module master_updateable_megarom(
inout wire [7:0] D,
input wire [16:0] bbc_A,
output wire [18:0] flash_A,
output wire flash_nOE,
output wire flash_nWE,
input wire cpld_SCK_in,
// Clock output so we can throw it on a BUFG.
// TODO this doesn't seem to work. maybe the
// signal needs to be internally generated,
// as opposed to just a copy of cpld_SCK_in?
//output wire cpld_SCK,
input wire cpld_MOSI,
input wire cpld_SS,
output reg cpld_MISO,
input wire [1:0] cpld_JP
);
assign cpld_SCK = cpld_SCK_in;
// 1 when installed in a Master 128, 0 when installed in a Model B
reg installed_in_bbc_master = 1'b0;
// flash bank to use for BBC reads
reg [1:0] flash_bank = 2'b0;
// When installed in a Model B, this decodes A16 from cpld_JP
wire model_b_A16;
// We're always selected when installed as a Master 128 MOS ROM, but when
// installed in a Model B, this decodes /CE from cpld_JP
wire bbc_nCE;
// address value from SPI transaction
reg [18:0] spi_A = 19'b0;
// data value from SPI transaction
reg [7:0] spi_D = 8'b0;
// 1 to pass the bbc_A through to flash_A, 0 to use A instead
reg allowing_bbc_access_int = 1'b1;
// overrideable version of the above
wire allowing_bbc_access;
// 1 to drive flash_nOE or flash_nWR
reg accessing_memory = 1'b0;
wire reading_memory;
wire writing_memory;
// 1 for read (drive flash_nOE), 0 for write (drive flash_nWR)
reg rnw = 1'b0;
// 1 to pass spi_D through to D
reg driving_bus = 1'b0;
// counts up to 31
reg [4:0] spi_bit_count = 5'b0;
// this is controllable for debugging:
assign allowing_bbc_access = allowing_bbc_access_int; // normal operation
// assign allowing_bbc_access = 1'b0; // never allow bbc access, for debugging
// We're either passing bbc_A through to flash_A, with D tristated, or we're
// controlling both and ignoring bbc_A.
assign flash_A = (allowing_bbc_access == 1'b1)
? (installed_in_bbc_master
? {flash_bank, bbc_A} // Master 128
: {flash_bank, model_b_A16, bbc_A[15:0]}) // Model B
: spi_A;
// when installed in a Model B, we need to decode A16 and nCE from cpld_JP.
assign model_b_A16 = cpld_JP[0];
assign bbc_nCE = installed_in_bbc_master
? 1'b0 // Master 128
: (cpld_JP[0] && cpld_JP[1]); // Model B
// assert OE
assign reading_memory = accessing_memory && rnw;
assign flash_nOE = !((allowing_bbc_access && !bbc_nCE && !bbc_A[16]) // A16=nOE
|| reading_memory);
// assert WE and D when the BBC is disabled and we're doing a memory write
assign writing_memory = accessing_memory && !rnw;
assign flash_nWE = !(!allowing_bbc_access && writing_memory);
// drive D when writing
assign D = (allowing_bbc_access == 1'b0 && (driving_bus == 1'b1 && rnw == 1'b0)) ? spi_D : 8'bZZZZZZZZ;
always @(posedge cpld_SCK or posedge cpld_SS) begin
if (cpld_SS == 1'b1) begin
accessing_memory <= 1'b0;
driving_bus <= 1'b0;
spi_bit_count <= 6'b000000;
end else begin
// the master device should bring cpld_SS high between every transaction.
// SPI is big-endian; send the MSB first and clock into the LSB.
// to block out the BBC and enable flash access: send ffffff00. to reenable
// the BBC, send 32 bits of ones. the final bit sets 'allowing_bbc_access'.
// message format for a WRITE that blocks the BBC after: 19 address bits,
// rnw, 8 data bits, 4 zeros, with the write happening during the six zeros.
// message format for a READ that blocks the BBC after: 19 address bits,
// rnw, 12 zeros, with the data byte returned in the final 8 bits.
// so if you want to do a single read and reenable BBC access afterward,
// send 19 address bits, then 1000000000001.
// the flash chip only needs a 40ns low pulse on /CE + /WE, and its read
// access time is 55-70ns. we hold /OE for reads or /WE for writes low for
// three SCK periods, so for a 70ns flash chip, the SPI clock period must be
// less than 42.8 MHz.
if (spi_bit_count < 19) begin
spi_A <= {spi_A[17:0], cpld_MOSI};
end else if (spi_bit_count == 19) begin
rnw <= cpld_MOSI;
// Disable BBC access if it's enabled. We do this here rather than just
// masking it with cpld_SS, so the board will run in ROM mode when the
// microcontroller is disconnected. If we got 19 clocks on cpld_SCK
// with cpld_SS=0, it's pretty safe to say that a microcontroller is
// indeed connected and active.
allowing_bbc_access_int <= 1'b0;
end else if (rnw == 1'b1) begin
// 0-18 address, 19 rnw, 20-23 access, 24-31 data out
if (spi_bit_count == 20) begin
// start read
accessing_memory <= 1'b1;
end else if (spi_bit_count == 23) begin
// end read
accessing_memory <= 1'b0;
spi_D <= D;
end else if (spi_bit_count >= 24) begin
spi_D <= {spi_D[6:0], 1'b0};
end
end else if (rnw == 1'b0) begin
// 0-18 address, 19 rnw, 20-27 data in, 28-31 access
if (spi_bit_count < 28) begin
spi_D <= {spi_D[6:0], cpld_MOSI};
driving_bus <= 1'b1;
end
if (spi_bit_count == 28) begin
accessing_memory <= 1'b1;
end
if (spi_bit_count == 30) begin
accessing_memory <= 1'b0;
end
end
if (spi_bit_count == 31) begin
driving_bus <= 1'b0;
allowing_bbc_access_int <= cpld_MOSI;
end
spi_bit_count <= spi_bit_count + 1;
end
end
always @(negedge cpld_SCK) begin
if (spi_bit_count < 19) begin
cpld_MISO <= spi_bit_count[0]; // should toggle and result in data & ffffe00 == 55554000
end else begin
cpld_MISO <= spi_D[7];
end
end
endmodule
|
`default_nettype none
`include "define.v"
module DRAMCON(input wire CLK_P,
input wire CLK_N,
input wire RST_X_IN,
////////// User logic interface ports //////////
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`APPDATA_WIDTH-1:0] D_DIN, //
output wire D_W, //
output reg [`APPDATA_WIDTH-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY, //
output wire USERCLK, //
output wire RST_O, //
////////// Memory interface ports //////////
inout wire [`DDR3_DATA] DDR3DQ,
inout wire [7:0] DDR3DQS_N,
inout wire [7:0] DDR3DQS_P,
output wire [`DDR3_ADDR] DDR3ADDR,
output wire [2:0] DDR3BA,
output wire DDR3RAS_N,
output wire DDR3CAS_N,
output wire DDR3WE_N,
output wire DDR3RESET_N,
output wire [0:0] DDR3CK_P,
output wire [0:0] DDR3CK_N,
output wire [0:0] DDR3CKE,
output wire [0:0] DDR3CS_N,
output wire [7:0] DDR3DM,
output wire [0:0] DDR3ODT);
function [`APPADDR_WIDTH-1:0] mux;
input [`APPADDR_WIDTH-1:0] a;
input [`APPADDR_WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
// inputs of u_dram
reg [`APPADDR_WIDTH-1:0] app_addr;
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`APPDATA_WIDTH-1:0] app_wdf_data = D_DIN;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
wire app_sr_req = 0; // no used
wire app_ref_req = 0; // no used
wire app_zq_req = 0; // no used
// outputs of u_dram
wire [`APPDATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire app_sr_active; // no used
wire app_ref_ack; // no used
wire app_zq_ack; // no used
wire ui_clk;
wire ui_clk_sync_rst;
wire init_calib_complete;
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
dram u_dram (
// Memory interface ports
.ddr3_addr (DDR3ADDR),
.ddr3_ba (DDR3BA),
.ddr3_cas_n (DDR3CAS_N),
.ddr3_ck_n (DDR3CK_N),
.ddr3_ck_p (DDR3CK_P),
.ddr3_cke (DDR3CKE),
.ddr3_ras_n (DDR3RAS_N),
.ddr3_reset_n (DDR3RESET_N),
.ddr3_we_n (DDR3WE_N),
.ddr3_dq (DDR3DQ),
.ddr3_dqs_n (DDR3DQS_N),
.ddr3_dqs_p (DDR3DQS_P),
.ddr3_cs_n (DDR3CS_N),
.ddr3_dm (DDR3DM),
.ddr3_odt (DDR3ODT),
.sys_clk_p (CLK_P),
.sys_clk_n (CLK_N),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.app_wdf_mask ({`APPMASK_WIDTH{1'b0}}),
.sys_rst (RST_X_IN)
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
reg [1:0] mode;
reg [31:0] remain, remain2;
reg rst_o;
always @(posedge ui_clk) rst_o <= (ui_clk_sync_rst || ~init_calib_complete); // High Active
assign USERCLK = ui_clk;
assign RST_O = rst_o;
assign D_BUSY = (mode != M_REQ); // DRAM busy
assign D_W = (mode == M_WRITE && app_rdy && app_wdf_rdy); // store one element
always @(posedge ui_clk) begin
if (RST_O) begin
mode <= M_REQ;
app_addr <= 0;
app_cmd <= 0;
app_en <= 0;
app_wdf_wren <= 0;
D_DOUT <= 0;
D_DOUTEN <= 0;
remain <= 0;
remain2 <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
case (D_REQ)
`DRAM_REQ_READ: begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
`DRAM_REQ_WRITE: begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
default: begin
app_wdf_wren <= 0;
app_en <= 0;
end
endcase
end
///////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= mux((app_addr+8), 0, (app_addr==`MEM_LAST_ADDR));
remain2 <= remain2 - 1;
if (remain2 == 1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
remain <= remain - 1;
if (remain == 1) mode <= M_REQ;
end
end
///////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= mux((app_addr+8), 0, (app_addr==`MEM_LAST_ADDR));
remain <= remain - 1;
if (remain == 1) begin
mode <= M_REQ;
app_en <= 0;
end
end else begin
app_wdf_wren <= 0;
end
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) ////////////////////////////////////////////
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_TB_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_TB_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dlatch_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10, inf = 0x3f3f3f3f; int sa[N]; int rk[N]; int tmp[N]; int lcp[N]; char s[N], t[N]; int n, k; bool cmp(int i, int j) { if (rk[i] != rk[j]) return rk[i] < rk[j]; else { int ri = i + k <= n ? rk[i + k] : -1; int rj = j + k <= n ? rk[j + k] : -1; return ri < rj; } } void build(char *s, int *sa) { n = strlen(s); for (int i = 0; i <= n; i++) { sa[i] = i; rk[i] = i < n ? s[i] : -1; } for (k = 1; k <= n; k *= 2) { sort(sa, sa + n + 1, cmp); tmp[sa[0]] = 0; for (int i = 1; i <= n; i++) { tmp[sa[i]] = tmp[sa[i - 1]] + (cmp(sa[i - 1], sa[i]) ? 1 : 0); } for (int i = 0; i <= n; i++) { rk[i] = tmp[i]; } } } void LCP(char *s, int *sa, int *lcp) { n = strlen(s); for (int i = 0; i <= n; i++) rk[sa[i]] = i; int h = 0; lcp[0] = 0; for (int i = 0; i < n; i++) { int j = sa[rk[i] - 1]; for (h ? h-- : 0; j + h < n && i + h < n && s[j + h] == s[i + h]; h++) ; lcp[rk[i] - 1] = h; } } int st[N], pos[N]; int main() { int T; scanf( %d , &T); while (T--) { scanf( %s , s); int n = strlen(s); build(s, sa); LCP(s, sa, lcp); for (int i = 0; i < n; i++) { } int now = 0; lcp[n] = 0; long long ans = 0; for (int i = 1; i <= n; i++) { int newpos = i, len = lcp[i]; while (now > 0 && st[now] > len) { long long v1 = st[now] - max(st[now - 1], len); long long v2 = i - pos[now] + 1; ans += v1 * v2 * v2; newpos = pos[now--]; } st[++now] = len; pos[now] = newpos; } for (int i = 0; i < n; i++) { ans += n - i - max(lcp[rk[i] - 1], lcp[rk[i]]); } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int max_n = 200005; vector<pair<int, int>> g[max_n]; int sz[max_n]; long long dis[max_n]; void dfs(int x) { sz[x] = 1; for (auto p : g[x]) { int u = p.first; if (sz[u]) continue; dis[u] = p.second; dfs(u); sz[x] += sz[u]; } } void solve() { int n; cin >> n; n *= 2; for (int i = 0; i <= n; i++) g[i].clear(); for (int i = 0; i <= n; i++) sz[i] = dis[i] = 0; for (int i = 1; i < n; i++) { int u, v, w; cin >> u >> v >> w; g[u].push_back({v, w}); g[v].push_back({u, w}); } dfs(1); long long ans1 = 0, ans2 = 0; for (int i = 2; i <= n; i++) { if (sz[i] & 1) ans1 += dis[i]; ans2 += min(sz[i], n - sz[i]) * dis[i]; } cout << ans1 << << ans2 << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) solve(); return 0; } |
//
// Test bench for xoro_top.v
//
`include "timescale.vh"
`define SIMULATION
module xoro_top_tb;
// Define all inputs
reg clk;
reg resn;
// Define all outputs
wire [3:0] leds;
wire [3:0] rnd;
wire serialOut;
// Instantiate DUT.
xoro_top xoro_top (
.CLOCK_50(clk),
.reset_btn(resn),
.LED(leds),
.RND_OUT(rnd),
.UART_TX(serialOut)
);
// Initialize all inputs
initial
begin
clk = 0;
resn = 0;
end
// Specify file for waveform dump
initial begin
$dumpfile ("xoro_top_tb.vcd");
$dumpvars;
end
// Monitor all signals
initial begin
$display("\tclk,\tresn,\tleds,\trnd,\tserialOut,\txoro_top.mem_addr, \txoro_top.mem_rdata,\txoro_top.resetn");
$monitor("\t%b,\t%b,\t%b,\t%b,\t%b,\t\t%h,\t\t%h,\t\t%b", clk, resn, leds, rnd, serialOut, xoro_top.mem_addr, xoro_top.mem_rdata, xoro_top.resetn);
end
// Generate a clock tick
always
#5clk = !clk;
// Generate a reset on start up
event reset_trigger;
event reset_done_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
resn = 0;
@ (negedge clk);
resn = 1;
-> reset_done_trigger;
end
end
/*
initial begin
-> reset_trigger;
end
*/
endmodule
|
`include "top.vh"
`include "chip8.vh"
`include "uart.vh"
module top(
input ice_clk_i,
input rstn_i,
input rs232_rx_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
wire clk_uart_rx, clk_led, clk_25;
reg [7 : 0] rx_i = 0;
reg rx_i_v = 0, rx_i_v_d = 0, tx_o_v_d = 0;
wire [7 : 0] tx_o;
wire tx_o_v;
wire [7 : 0] _rx_i;
wire _rx_i_v;
wire draw_o;
assign led_o[0] = 1;
assign led_o[1] = clk_led;
assign _rx_i = rx_i;
assign _rx_i_v = rx_i_v;
assign red_o = draw_o ? 4'b1111 : 0;
assign blue_o = draw_o ? 4'b1111 : 0;
assign green_o = draw_o ? 4'b1111 : 0;
always @ (posedge clk_25)
begin
rx_i_v <= tx_o_v & ~rx_i_v_d;
rx_i_v_d <= tx_o_v;
rx_i <= tx_o;
end
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T()
)led_clk(
.clk_i (ice_clk_i),
.clk_o (clk_led)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
) clk_uart_rx_gen(
.clk_i (ice_clk_i),
.clk_o (clk_uart_rx)
);
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
//.DIVR(4'b0000),
//.DIVF(7'b1010011),
//.DIVQ(3'b101)
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b101)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_25)
);
uart_rx uart_rx(
.clk_i(clk_uart_rx),
.rx_i(rs232_rx_i),
.tx_o(tx_o),
.tx_o_v(tx_o_v)
);
interpreter interpreter(
.clk(clk_25),
.rx_i(rx_i),
.rx_i_v(rx_i_v),
.hs(hs_o),
.vs(vs_o),
.draw_o(draw_o)
);
endmodule // top
|
#include <bits/stdc++.h> using namespace std; int testnum; const int maxn = 100005; int par[maxn]; int size[maxn]; int find(int u) { if (par[u] == u) return u; return par[u] = find(par[u]); } bool unify(int u, int v) { int cu = find(u), cv = find(v); if (cu == cv) return true; if (size[cu] > size[cv]) { par[cv] = cu; size[cu] += size[cv]; } else { par[cu] = cv; size[cv] += size[cu]; } return false; } int n, m; void preprocess() { for (int i = 0; i < maxn; i++) { par[i] = i; size[i] = 1; } } long long mod = 1000000009; void solve() { int a, b; long long ans = 1; for (int i = 0; i < m; i++) { scanf( %d , &a); scanf( %d , &b); bool z = unify(a, b); if (z) { ans = (ans + ans) % mod; } cout << (ans - 1) << endl; } } bool input() { scanf( %d , &n); scanf( %d , &m); return true; } int main() { preprocess(); int T = 1; for (testnum = 1; testnum <= T; testnum++) { if (!input()) break; solve(); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 10005; short dp[MAXN][MAXN]; int32_t main() { ios::sync_with_stdio(false); string s, t; cin >> s >> t; dp[0][0] = 0; int n = s.size(), m = t.size(); for (int i = 0; i <= n + 3; i++) for (int j = 0; j <= m + 3; j++) dp[i][j] = MAXN; dp[0][0] = 0; vector<int> prv(n + 1, -1); vector<int> wh(2 * n + 1, -1); wh[n] = 0; for (int i = 1, v = 0; i <= n; i++) { v += (s[i - 1] == . ? -1 : 1); if (s[i - 1] == . && wh[v + n] != -1) prv[i] = wh[v + n]; wh[v + n] = i; } for (int i = 1; i <= n; i++) { for (int j = 0; j <= m; j++) { if (j > 0 && s[i - 1] == t[j - 1]) dp[i][j] = dp[i - 1][j - 1]; if (s[i - 1] == . ) dp[i][j] = dp[i - 1][j + 1]; dp[i][j] = min(dp[i][j], (short)(dp[i - 1][j] + 1)); if (prv[i] != -1) dp[i][j] = min(dp[i][j], dp[prv[i]][j]); } } cout << dp[n][m] << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_M_V
`define SKY130_FD_SC_LP__A2BB2OI_M_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_m (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_m (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_M_V
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module mux4(/*AUTOARG*/
// Outputs
out,
// Inputs
in0, in1, in2, in3, sel0, sel1, sel2, sel3
);
parameter DW=99;
//data inputs
input [DW-1:0] in0;
input [DW-1:0] in1;
input [DW-1:0] in2;
input [DW-1:0] in3;
//select inputs
input sel0;
input sel1;
input sel2;
input sel3;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0]);
endmodule // mux4
|
#include <bits/stdc++.h> using namespace std; void solve() { long long i, j, k, l, n, m, a, b, u; cin >> n; vector<pair<string, pair<long long, long long>>> v(n); for (i = 0; i < n; i++) { cin >> v[i].first >> v[i].second.first >> v[i].second.second; } long long ans = 0; for (i = 1; i <= 366; i++) { long long m = 0, f = 0; for (j = 0; j < n; j++) { if (v[j].second.first <= i && v[j].second.second >= i) { if (v[j].first == M ) m++; else f++; } } ans = max(ans, min(m, f)); } cout << ans * 2; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) solve(); return 0; } |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mem_1k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mem_1k (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [63:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL rdaddress[9..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL wraddress[9..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/***********************************************************************
Asynchronous FIFO Memory
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
FIFO2: Implements de FIFO2 algorithm described in the "Simulation
and Synthesis Techniques for Asynchronous FIFO Design with
Asynchronous Pointer Comparisons" by Clifford E. Cummings and Peter
Alfke SNUG 2002.
To Do:
-
Author:
- Salvador E. Tropea, salvador en inti gov ar
------------------------------------------------------------------------------
Copyright (c) 2017 Salvador E. Tropea <salvador en inti gov ar>
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: FIFO_Async
File name: fifo_async.v
Note: If you read when no data is available or write
when the FIFO is full the result is undefined.
Data is available in the next clock for reads,
this is how BRAMs work (1 clock addr latch)
Limitations: rrst_i and wrst_i are async, but must be
deasserted sync.
Synplify Pro sometimes gets confused about the
reset when using this core.
Errors: None known
Library: None
Dependencies: IEEE.std_logic_1164
IEEE.numeric_std
mems.Devices
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: Lattice 2017.01.27914
Simulation tools: GHDL 0.3x
Text editor: SETEdit 0.5.x
***********************************************************************/
localparam N=ADDR_W-1;
// Read side
reg [ADDR_W-1:0] rptr_r; // Read pointer (Gray encoding)
wire [ADDR_W-1:0] rptr_next; // Read pointer next (Gray encoding)
reg [ADDR_W-1:0] rbin_r; // Read pointer (binary encoding)
wire [ADDR_W-1:0] rbin_next; // Read pointer next (binary encoding)
reg empty_r; // Sync empty (2 stages)
reg empty2_r; // Sync empty intermediate
// Write side
reg [ADDR_W-1:0] wptr_r; // Write pointer (Gray encoding)
wire [ADDR_W-1:0] wptr_next; // Write pointer next (Gray encoding)
reg [ADDR_W-1:0] wbin_r; // Write pointer (binary encoding)
wire [ADDR_W-1:0] wbin_next; // Write pointer next (binary encoding)
wire full_r; // Sync full (2 stages)
wire full2_r; // Sync full intermediate
// Asynchronous comparator
wire asy_empty; // Asynchronous empty (active low)
wire asy_full; // Asynchronous full (active low)
wire dir_set; // Direction latch SET
wire dir_clr; // Direction latch CLEAR
reg direction_r; // Direction latch
///////////////////
// Read pointer //
///////////////////
always @(posedge rclk_i or posedge rrst_i)
begin : do_rptr
if (rrst_i)
begin
rbin_r <= 0;
rptr_r <= 0;
end
else
begin
rbin_r <= rbin_next;
rptr_r <= rptr_next;
end
end // do_rptr
assign rbin_next=!empty_r ? rbin_r+re_i : rbin_r;
// Convert rbin_next to Gray
assign rptr_next=(rbin_next>>1) ^ rbin_next;
////////////////////////
// Empty synchronizer //
////////////////////////
// 2 FFs with async preset
always @(posedge rclk_i or posedge asy_empty)
begin : do_empty_r
if (asy_empty)
{ empty_r, empty2_r } <= 2'b11;
else
{ empty_r, empty2_r } <= { empty2_r, asy_empty };
end // do_empty_r
assign avail_o=~empty_r;
assign empty_o= empty_r;
///////////////////
// Write pointer //
///////////////////
always @(posedge wclk_i or posedge wrst_i)
begin : do_wptr
if (wrst_i)
begin
wbin_r <= 0;
wptr_r <= 0;
end
else
begin
wbin_r <= wbin_next;
wptr_r <= wptr_next;
end
end // do_wptr
assign wbin_next=full_r ? wbin_r : wbin_r+we_i;
// Convert wbin_next to Gray
assign wptr_next=(wbin_next>>1) ^ wbin_next;
///////////////////////
// Full synchronizer //
///////////////////////
// 2 FFs with async preset (&clr)
reg q1, q2;
always @(posedge wclk_i or posedge asy_full)
begin : do_ff
if (asy_full)
{ q1, q2 } <= 2'b11;
else
{ q1, q2 } <= { asy_full, full2_r };
end // do_ff
// Another FF for clear
reg q1_clr, q2_clr;
always @(posedge wclk_i or posedge wrst_i)
begin : do_clr
if (wrst_i)
{ q1_clr, q2_clr } <= 2'b00;
else
{ q1_clr, q2_clr } <= 2'b11;
end // do_clr
// Output is conditioned by the clear FF
assign { full2_r, full_r }={ q1, q2 } & { q1_clr, q2_clr };
assign full_o=full_r;
/////////////////////////////
// Asynchronous comparator //
/////////////////////////////
// Quadrant detector
assign dir_set=( wptr_r[N]^rptr_r[N-1]) & ~(wptr_r[N-1]^rptr_r[N]);
assign dir_clr=(~(wptr_r[N]^rptr_r[N-1]) & (wptr_r[N-1]^rptr_r[N])) | wrst_i;
// Direction latch according to the quadrant (1==up, 0==down)
always @ (negedge dir_set or posedge dir_clr)
if (dir_clr)
direction_r <= 1'b0;
else
direction_r <= 1'b1;
// Asynchronous empty/full
assign asy_empty=wptr_r==rptr_r && !direction_r;
assign asy_full =wptr_r==rptr_r && direction_r;
/////////////////
// FIFO memory //
/////////////////
reg [DATA_W-1:0] ram[DEPTH-1:0];
always @(posedge wclk_i)
begin : side1
if (we_i)
ram[wptr_r]=datai_i;
end // side1
reg [DATA_W-1:0] datao_r;
always @(posedge rclk_i)
begin : side2
datao_r <= ram[rptr_r];
end // side2
assign datao_o=datao_r;
|
#include <bits/stdc++.h> using namespace std; long long ans, i, N, H, alive, last1, last2, last3, a, b, c; long long A[2][32][32][32], B[2][32][32][32]; int main() { cin >> N >> H; A[1][0][0][0] = 4; for (i = 1; i < N; i++) { for (alive = 0; alive < 2; alive++) for (last1 = 0; i - last1 > 0 && last1 < H; last1++) for (last2 = 0; i - last2 > 0 && last2 < H; last2++) for (last3 = 0; i - last3 > 0 && last3 < H; last3++) { if (last1 == 0 || last1 == H - 1) a = 0; else a = last1 + 1; if (last2 == 0 || last2 == H - 1) b = 0; else b = last2 + 1; if (last3 == 0 || last3 == H - 1) c = 0; else c = last3 + 1; B[alive][a][b][c] += A[alive][last1][last2][last3]; B[alive][a][b][c] %= 1000000009; B[last1 > 0 || i < H][alive][b][c] += A[alive][last1][last2][last3]; B[last1 > 0 || i < H][alive][b][c] %= 1000000009; B[last2 > 0 || i < H][a][alive][c] += A[alive][last1][last2][last3]; B[last2 > 0 || i < H][a][alive][c] %= 1000000009; B[last3 > 0 || i < H][a][b][alive] += A[alive][last1][last2][last3]; B[last3 > 0 || i < H][a][b][alive] %= 1000000009; } for (alive = 0; alive < 2; alive++) for (last1 = 0; last1 < H; last1++) for (last2 = 0; last2 < H; last2++) for (last3 = 0; last3 < H; last3++) { A[alive][last1][last2][last3] = B[alive][last1][last2][last3]; B[alive][last1][last2][last3] = 0; } } for (a = 0; a < H; a++) for (b = 0; b < H; b++) for (c = 0; c < H; c++) ans = (ans + A[1][a][b][c]) % 1000000009; for (a = 0; a < H; a++) for (b = 0; b < H; b++) for (c = 0; c < H; c++) if (a > 0 || b > 0 || c > 0) ans = (ans + A[0][a][b][c]) % 1000000009; cout << ans << endl; } |
module scaler_1d # (
parameter integer C_S_WIDTH = 12,
parameter integer C_M_WIDTH = 12,
parameter integer C_S_BMP = 4 ,
parameter integer C_S_BID = 2 ,
parameter integer C_S_IDX = 0 , /// C_S_WIDTH or 0
parameter integer C_SPLIT_ID_WIDTH = 2
) (
input wire clk,
input wire resetn,
input [C_S_WIDTH-1:0] s_nbr,
input [C_M_WIDTH-1:0] m_nbr,
output wire o_valid ,
input wire i_ready ,
output wire o_s_advance ,
output wire o_s_last ,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx0,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx1,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx2,
output wire o_m_advance ,
output wire o_m_first ,
output wire o_m_last ,
output wire o_a_last ,
output wire o_d_valid ,
output wire [C_SPLIT_ID_WIDTH : 0] o_split_id
);
///////////////////////////// row ////////////////////////////////////////////
wire sd_algo_enable ;
wire sd_core2split_o_valid ;
wire sd_core2split_s_advance ;
wire sd_core2split_s_last ;
wire [C_S_WIDTH + C_M_WIDTH : 0] sd_core2split_s_c ;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_core2split_s_bmp_bid_idx0;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_core2split_s_bmp_bid_idx1;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_core2split_s_bmp_bid_idx2;
wire sd_core2split_m_advance ;
wire sd_core2split_m_first ;
wire sd_core2split_m_last ;
wire [C_S_WIDTH + C_M_WIDTH : 0] sd_core2split_m_c ;
wire sd_core2split_a_last ;
wire sd_core2split_d_valid ;
scaler_core # (
.C_S_WIDTH (C_S_WIDTH),
.C_M_WIDTH (C_M_WIDTH),
.C_S_BMP (C_S_BMP ),
.C_S_BID (C_S_BID ),
.C_S_IDX (C_S_IDX )
) sd_core (
.clk (clk ),
.resetn (resetn),
.s_nbr (s_nbr),
.m_nbr (m_nbr),
.enable (sd_algo_enable ),
.o_valid (sd_core2split_o_valid ),
.s_advance (sd_core2split_s_advance ),
.s_last (sd_core2split_s_last ),
.s_c (sd_core2split_s_c ),
.s_bmp_bid_idx0(sd_core2split_s_bmp_bid_idx0),
.s_bmp_bid_idx1(sd_core2split_s_bmp_bid_idx1),
.s_bmp_bid_idx2(sd_core2split_s_bmp_bid_idx2),
.m_advance (sd_core2split_m_advance ),
.m_first (sd_core2split_m_first ),
.m_last (sd_core2split_m_last ),
.m_c (sd_core2split_m_c ),
.a_last (sd_core2split_a_last ),
.d_valid (sd_core2split_d_valid )
);
wire sd_split2relay_valid ;
wire sd_split2relay_s_advance ;
wire sd_split2relay_s_last ;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_split2relay_s_bmp_bid_idx0;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_split2relay_s_bmp_bid_idx1;
wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] sd_split2relay_s_bmp_bid_idx2;
wire sd_split2relay_m_advance ;
wire sd_split2relay_m_first ;
wire sd_split2relay_m_last ;
wire sd_split2relay_a_last ;
wire sd_split2relay_d_valid ;
wire [C_SPLIT_ID_WIDTH : 0] sd_split2relay_split_id ;
scaler_spliter # (
.C_S_WIDTH (C_S_WIDTH ),
.C_M_WIDTH (C_M_WIDTH ),
.C_S_BMP (C_S_BMP ),
.C_S_BID (C_S_BID ),
.C_S_IDX (C_S_IDX ),
.C_SPLIT_ID_WIDTH (C_SPLIT_ID_WIDTH)
) sd_spliter (
.clk (clk ),
.resetn (resetn),
///.s_nbr (s_nbr),
.m_nbr (m_nbr),
.enable (sd_algo_enable ),
.i_valid (sd_core2split_o_valid ),
.i_s_advance (sd_core2split_s_advance ),
.i_s_last (sd_core2split_s_last ),
.i_s_c (sd_core2split_s_c ),
.i_s_bmp_bid_idx0(sd_core2split_s_bmp_bid_idx0 ),
.i_s_bmp_bid_idx1(sd_core2split_s_bmp_bid_idx1 ),
.i_s_bmp_bid_idx2(sd_core2split_s_bmp_bid_idx2 ),
.i_m_advance (sd_core2split_m_advance ),
.i_m_first (sd_core2split_m_first ),
.i_m_last (sd_core2split_m_last ),
.i_m_c (sd_core2split_m_c ),
.i_a_last (sd_core2split_a_last ),
.i_d_valid (sd_core2split_d_valid ),
.o_valid (sd_split2relay_valid ),
.o_s_advance (sd_split2relay_s_advance ),
.o_s_last (sd_split2relay_s_last ),
.o_s_bmp_bid_idx0(sd_split2relay_s_bmp_bid_idx0),
.o_s_bmp_bid_idx1(sd_split2relay_s_bmp_bid_idx1),
.o_s_bmp_bid_idx2(sd_split2relay_s_bmp_bid_idx2),
.o_m_advance (sd_split2relay_m_advance ),
.o_m_first (sd_split2relay_m_first ),
.o_m_last (sd_split2relay_m_last ),
.o_a_last (sd_split2relay_a_last ),
.o_d_valid (sd_split2relay_d_valid ),
.o_split_id (sd_split2relay_split_id )
);
localparam integer C_DATA_WIDTH = (7
+ (C_S_BMP + C_S_BID + C_S_IDX) * 3
+ (C_SPLIT_ID_WIDTH + 1));
scaler_relay # (
.C_DATA_WIDTH(C_DATA_WIDTH)
) relay (
.clk (clk ),
.resetn (resetn),
.s_valid(sd_split2relay_valid),
.s_data ({
sd_split2relay_s_advance ,
sd_split2relay_s_last ,
sd_split2relay_s_bmp_bid_idx0,
sd_split2relay_s_bmp_bid_idx1,
sd_split2relay_s_bmp_bid_idx2,
sd_split2relay_m_advance ,
sd_split2relay_m_first ,
sd_split2relay_m_last ,
sd_split2relay_a_last ,
sd_split2relay_d_valid ,
sd_split2relay_split_id
}),
.s_ready(sd_algo_enable),
.m_valid(o_valid),
.m_data ({
o_s_advance ,
o_s_last ,
o_s_bmp_bid_idx0,
o_s_bmp_bid_idx1,
o_s_bmp_bid_idx2,
o_m_advance ,
o_m_first ,
o_m_last ,
o_a_last ,
o_d_valid ,
o_split_id
}),
.m_ready(i_ready)
);
endmodule
|
// ghrd_10as066n2_emif_hps.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_emif_hps (
input wire global_reset_n, // global_reset_reset_sink.reset_n
input wire [4095:0] hps_to_emif, // hps_emif_conduit_end.hps_to_emif
output wire [4095:0] emif_to_hps, // .emif_to_hps
input wire [1:0] hps_to_emif_gp, // .gp_to_emif
output wire [0:0] emif_to_hps_gp, // .emif_to_gp
output wire [0:0] mem_ck, // mem_conduit_end.mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [16:0] mem_a, // .mem_a
output wire [0:0] mem_act_n, // .mem_act_n
output wire [1:0] mem_ba, // .mem_ba
output wire [0:0] mem_bg, // .mem_bg
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [0:0] mem_odt, // .mem_odt
output wire [0:0] mem_reset_n, // .mem_reset_n
output wire [0:0] mem_par, // .mem_par
input wire [0:0] mem_alert_n, // .mem_alert_n
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dbi_n, // .mem_dbi_n
input wire oct_rzqin, // oct_conduit_end.oct_rzqin
input wire pll_ref_clk // pll_ref_clk_clock_sink.clk
);
ghrd_10as066n2_emif_hps_altera_emif_a10_hps_171_or5co3i emif_hps (
.global_reset_n (global_reset_n), // input, width = 1, global_reset_reset_sink.reset_n
.hps_to_emif (hps_to_emif), // input, width = 4096, hps_emif_conduit_end.hps_to_emif
.emif_to_hps (emif_to_hps), // output, width = 4096, .emif_to_hps
.hps_to_emif_gp (hps_to_emif_gp), // input, width = 2, .gp_to_emif
.emif_to_hps_gp (emif_to_hps_gp), // output, width = 1, .emif_to_gp
.mem_ck (mem_ck), // output, width = 1, mem_conduit_end.mem_ck
.mem_ck_n (mem_ck_n), // output, width = 1, .mem_ck_n
.mem_a (mem_a), // output, width = 17, .mem_a
.mem_act_n (mem_act_n), // output, width = 1, .mem_act_n
.mem_ba (mem_ba), // output, width = 2, .mem_ba
.mem_bg (mem_bg), // output, width = 1, .mem_bg
.mem_cke (mem_cke), // output, width = 1, .mem_cke
.mem_cs_n (mem_cs_n), // output, width = 1, .mem_cs_n
.mem_odt (mem_odt), // output, width = 1, .mem_odt
.mem_reset_n (mem_reset_n), // output, width = 1, .mem_reset_n
.mem_par (mem_par), // output, width = 1, .mem_par
.mem_alert_n (mem_alert_n), // input, width = 1, .mem_alert_n
.mem_dqs (mem_dqs), // inout, width = 4, .mem_dqs
.mem_dqs_n (mem_dqs_n), // inout, width = 4, .mem_dqs_n
.mem_dq (mem_dq), // inout, width = 32, .mem_dq
.mem_dbi_n (mem_dbi_n), // inout, width = 4, .mem_dbi_n
.oct_rzqin (oct_rzqin), // input, width = 1, oct_conduit_end.oct_rzqin
.pll_ref_clk (pll_ref_clk) // input, width = 1, pll_ref_clk_clock_sink.clk
);
endmodule
|
//
// This module instantiates num_nodes_p two-element-fifos in chains
// It supports multiple bsg_noc_links in parallel
//
// Insert this module into long routings on chip, which can become critical path
//
// Node that side_A_reset_i signal shoule be close to side A
// If reset happens to be close to side B, please swap side A and side B connection,
// since side A and side B are symmetric, functionality will not be affected.
//
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
module bsg_noc_repeater_node
#(parameter `BSG_INV_PARAM(width_p )
, parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p)
)
( input clk_i
, input reset_i
, input [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_i
, output [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_o
, input [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_i
, output [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_o
);
// declare the bsg_ready_and_link_sif_s struct
`declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s);
// noc links
bsg_ready_and_link_sif_s links_A_cast_i, links_B_cast_i;
bsg_ready_and_link_sif_s links_A_cast_o, links_B_cast_o;
assign links_A_cast_i = side_A_links_i;
assign links_B_cast_i = side_B_links_i;
assign side_A_links_o = links_A_cast_o;
assign side_B_links_o = links_B_cast_o;
bsg_two_fifo #(.width_p(width_p))
A_to_B
(.clk_i ( clk_i )
,.reset_i ( reset_i )
,.v_i ( links_A_cast_i.v )
,.data_i ( links_A_cast_i.data )
,.ready_o ( links_A_cast_o.ready_and_rev )
,.v_o ( links_B_cast_o.v )
,.data_o ( links_B_cast_o.data )
,.yumi_i ( links_B_cast_i.ready_and_rev & links_B_cast_o.v )
);
bsg_two_fifo #(.width_p(width_p))
B_to_A
(.clk_i ( clk_i )
,.reset_i ( reset_i )
,.v_i ( links_B_cast_i.v )
,.data_i ( links_B_cast_i.data )
,.ready_o ( links_B_cast_o.ready_and_rev )
,.v_o ( links_A_cast_o.v )
,.data_o ( links_A_cast_o.data )
,.yumi_i ( links_A_cast_i.ready_and_rev & links_A_cast_o.v )
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_noc_repeater_node)
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1010; int n, q, ans; int mat[maxn][maxn]; int main() { cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { int k; scanf( %d , &k); if (i == j) { ans += k; } } } ans %= 2; cin >> q; for (int i = 0; i < q; i++) { int c; scanf( %d , &c); if (c == 1 || c == 2) { int bucket; scanf( %d , &bucket); ans = (ans + 1) % 2; } else { printf( %d , ans); } } cout << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_LP_V
`define SKY130_FD_SC_LP__O2111A_LP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_lp (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_lp (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_LP_V
|
#include <bits/stdc++.h> const int MAXN = 10010100; const int MAZN = 301010; int ch[MAXN][3]; int n, cnt, cout[MAXN]; int arr[MAZN]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); } for (int i = 1; i <= n; i++) { int tem, p = 0; scanf( %d , &tem); for (int k = 29; k >= 0; k--) { int tmp = (tem >> k) & 1; if (ch[p][tmp]) p = ch[p][tmp]; else p = ch[p][tmp] = ++cnt; cout[p]++; } } for (int i = 1; i <= n; i++) { int x = arr[i]; int ans = 0, p = 0; for (int j = 29; j >= 0; j--) { int tmp = (x >> j) & 1; if (ch[p][tmp] && cout[ch[p][tmp]]) { p = ch[p][tmp]; } else { p = ch[p][!tmp]; ans += (1 << j); } cout[p]--; } printf( %d , ans); } } |
#include <bits/stdc++.h> using namespace std; const int Mo = (int)1e9 + 7; int i, j, m, n, p, k, sum, id, x, y, a[1000005], flag, ans; int power(int x, int y) { int sum = 1; for (; y; y >>= 1) { if (y & 1) sum = 1ll * x * sum % Mo; x = 1ll * x * x % Mo; } return sum; } int main() { scanf( %d%d%d , &n, &m, &k); id = 1; for (i = 1; i <= m; ++i) { scanf( %d%d , &x, &y); if (y - x != 1 && y - x != k + 1) { printf( 0 n ); return 0; } else if (y - x != 1) a[x]++, ++sum, id = x; } for (i = 1; i <= n; ++i) a[i] += a[i - 1]; for (i = id; i <= n && i + k + 1 <= n; ++i) if (a[max(0, i - k - 1)] == 0) ans = (ans + power(2, (i - 1 - max(0, i - k - 1) - (a[i - 1] - a[max(0, i - k - 1)])))) % Mo; if (!a[n]) ans = (ans + 1) % Mo; printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6, inf = 1e9 + 2; pair<int, int> a[N + 2], b[N + 2], aa[N + 2], bb[N + 2]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, c, d; cin >> n >> c >> d; int p = 0, q = 0; for (int i = 1; i <= n; i++) { int x, y; char c; cin >> x >> y >> c; if (c == C ) a[++p] = {y, x}; else b[++q] = {y, x}; } sort(a + 1, a + p + 1); sort(b + 1, b + q + 1); for (int i = 1; i <= p; i++) aa[i] = a[i]; for (int i = 1; i <= q; i++) bb[i] = b[i]; for (int i = 1; i <= p; i++) a[i].second = max(a[i].second, a[i - 1].second); for (int i = 1; i <= q; i++) b[i].second = max(b[i].second, b[i - 1].second); int ans = 0; for (int i = 2; i <= p; i++) { int rm = c - a[i].first; int id = upper_bound(a + 1, a + p + 1, make_pair(rm, inf)) - a; id--; if (id >= i) id = i - 1; if (id > 0) ans = max(ans, aa[i].second + a[id].second); } for (int i = 2; i <= q; i++) { int rm = d - b[i].first; int id = upper_bound(b + 1, b + q + 1, make_pair(rm, inf)) - b; id--; if (id >= i) id = i - 1; if (id > 0) ans = max(ans, bb[i].second + b[id].second); } int ad1 = -1, ad2 = -1; for (int i = 1; i <= p; i++) if (a[i].first <= c) ad1 = a[i].second; for (int i = 1; i <= q; i++) if (b[i].first <= d) ad2 = b[i].second; if (ad1 != -1 && ad2 != -1) ans = max(ans, ad1 + ad2); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 9; long long pow_mod(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res = res * x % mod; n >>= 1; x = x * x % mod; } return res; } long long inv(long long x) { return pow_mod(x, mod - 2); } int main() { long long n, a, b, k; string s; while (cin >> n >> a >> b >> k) { cin >> s; long long ans = 0; for (long long i = 0; i < k; i++) { if (s[i] == + ) ans = ((ans + pow_mod(a, n - i) * pow_mod(b, i)) % mod + mod) % mod; else ans = ((ans - pow_mod(a, n - i) * pow_mod(b, i)) % mod + mod) % mod; } long long m = (n + 1) / k; long long q = pow_mod(b, k) * inv(pow_mod(a, k)) % mod; if (q == 1) ans = ans * m % mod; else { ans = ans * (1 - pow_mod(q, m)) % mod; ans = ans * inv(1 - q) % mod; } cout << (ans + mod) % mod << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, w; long long ans; double a[100010], b[100010]; struct node { int f, x, v; double a, b; } sh[100010]; double m_abs(double x) { if (x < 0) return -x; else return x; } bool cmp(node x, node y) { return (x.a < y.a || (x.a == y.a && x.b > y.b)); } void m_sort(int l, int r) { if (l == r) return; int mid; mid = (l + r) / 2; m_sort(l, mid); m_sort(mid + 1, r); int ll, rr, now; now = 0; ll = l; rr = mid + 1; while (ll <= mid && rr <= r) { if (a[ll] < a[rr]) { now++; b[now] = a[ll]; ll++; } else { now++; b[now] = a[rr]; rr++; ans += (long long)mid - ll + 1; } } for (int i = ll; i <= mid; i++) { now++; b[now] = a[i]; } for (int i = rr; i <= r; i++) { now++; b[now] = a[i]; } for (int i = 1; i <= now; i++) { a[l + i - 1] = b[i]; } } int main() { scanf( %d%d , &n, &w); for (int i = 1; i <= n; i++) { scanf( %d%d , &sh[i].x, &sh[i].v); if (sh[i].x > 0) sh[i].f = 1; } for (int i = 1; i <= n; i++) { if (sh[i].f == 0) { sh[i].a = m_abs((sh[i].x * 1.0) / ((sh[i].v + w) * 1.0)); sh[i].b = m_abs((sh[i].x * 1.0) / ((sh[i].v - w) * 1.0)); } else { sh[i].b = m_abs((sh[i].x * 1.0) / ((sh[i].v - w) * 1.0)); sh[i].a = m_abs((sh[i].x * 1.0) / ((sh[i].v + w) * 1.0)); } } sort(sh + 1, sh + 1 + n, cmp); for (int i = 1; i <= n; i++) a[i] = sh[i].b; m_sort(1, n); printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; char a[1100], b[1100][1100]; const int inf = 2000000000; int c[1100], len[1100], f[1100][1100], sum[1100], ran[2][1100], to[1100], d[1100], n, m, fr[1100]; int cal(int i) { int j, res = 0; for (j = len[i]; j > m; j--) res += c[b[i][j] - 0 ]; return res; } void add(int i) { if (len[i] <= m) len[i] = m + 1, b[i][m + 1] = 1 ; else { int pos = m + 1; b[i][pos]++; while (b[i][pos] > 9 ) { if (len[i] == pos) len[i]++, b[i][len[i]] = 1 ; else b[i][pos + 1]++; b[i][pos] = 0 ; pos++; } } } int main() { int i, j, k, nw, pre, l, r, co, p, q, ans; scanf( %s , a + 1); m = strlen(a + 1); reverse(a + 1, a + m + 1); scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %s , b[i] + 1); len[i] = strlen(b[i] + 1); reverse(b[i] + 1, b[i] + len[i] + 1); for (j = len[i] + 1; j <= m; j++) b[i][++len[i]] = 0 ; } for (i = 0; i <= 9; i++) scanf( %d , &c[i]); for (i = 1; i <= n; i++) ran[0][i] = i; nw = 0; pre = 1; for (i = 0; i <= m; i++) for (j = 1; j <= n + 1; j++) f[i][j] = -inf; f[0][n + 1] = 0; for (i = 1; i <= m; i++) { nw ^= 1; pre ^= 1; for (j = 0; j <= 9; j++) sum[j] = 0; for (j = 1; j <= n; j++) sum[b[j][i] - 0 ]++; for (j = 1; j <= 9; j++) sum[j] += sum[j - 1]; for (j = n; j; j--) { ran[nw][sum[b[ran[pre][j]][i] - 0 ]] = ran[pre][j]; to[sum[b[ran[pre][j]][i] - 0 ]] = j; fr[j] = sum[b[ran[pre][j]][i] - 0 ]--; } l = 0; r = 9; if (i == m) l = 1; if (a[i] != ? ) l = a[i] - 0 , r = a[i] - 0 ; for (j = l; j <= r; j++) { co = 0; for (k = 1; k <= n; k++) co += c[(b[k][i] - 0 + j) % 10]; for (k = n; ((k) && (b[ran[nw][k]][i] - 0 + j > 9)); k--) ; for (p = n + 1; (((!k) || (p > to[k]) || (b[ran[nw][k]][i] - 0 + j < 9)) && (p)); p--) { if (p != n + 1) { co -= c[(b[ran[nw][fr[p]]][i] - 0 + j) % 10]; co += c[(b[ran[nw][fr[p]]][i] - 0 + j + 1) % 10]; } f[i][k + 1] = max(f[i][k + 1], f[i - 1][p] + co); } for (; ((k) && (b[ran[nw][k]][i] - 0 + j == 9)); k--) { if ((k == 1) || (b[ran[nw][k - 1]][i] - 0 + j != 9)) q = 1; else q = to[k - 1] + 1; for (; p >= q; p--) { co -= c[(b[ran[nw][fr[p]]][i] - 0 + j) % 10]; co += c[(b[ran[nw][fr[p]]][i] - 0 + j + 1) % 10]; f[i][k] = max(f[i][k], f[i - 1][p] + co); } } } } for (i = 1; i <= n; i++) d[i] = ran[nw][i]; co = 0; ans = 0; for (i = 1; i <= n; i++) co += cal(i); ans = max(ans, co + f[m][n + 1]); for (i = n; i; i--) { co -= cal(d[i]); add(d[i]); co += cal(d[i]); ans = max(ans, co + f[m][i]); } printf( %d n , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__probe_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 50 + 5; const int maxm = 2500 + 5; const int inf = 1 << 29; const long long mod = 1e9 + 7; const double eps = 1e-8; long long read() { long long s = 0, w = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) { if (c == - ) w = -1; } for (; isdigit(c); c = getchar()) { s = (s << 3) + (s << 1) + (c ^ 48); } return w == 1 ? s : -s; } int main() { int t = read(); while (t--) { int a = read(), b = read(); if (a > b) swap(a, b); if ((a + b) & 1) { int mn = b - (a + b + 1) / 2; int mx = min((a + b + 1) / 2, b) + min((a + b) / 2, a); printf( %d n , mx - mn + 1); for (int i = mn; i <= mx; i++) { printf( %d , i); } puts( ); } else { int mn = b - (a + b) / 2; int mx = min((a + b) / 2, b) + min((a + b) / 2, a); printf( %d n , (mx / 2 - mn / 2 + 1)); for (int i = mn; i <= mx; i += 2) { printf( %d , i); } puts( ); } } return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int n = 8; bool ww = 1; int con = 0; while (n--) { string s; cin >> s; bool tb = 1; for (int i = 0; i < s.size(); i++) { if (s[i] == W ) { tb = 0; } } if (tb == 0 && ww == 1) { for (int i = 0; i < s.size(); i++) { if (s[i] == B ) { con++; } } ww = 0; } else if (tb) { con++; } } cout << con; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3005; const int maxm = maxn * maxn << 1; int n, m, q; int id[maxn][maxn << 1]; int fa[maxm]; int vis[maxm]; int top = 0; stack<pair<int, int> > sta; inline int getfa(int x) { sta.push(make_pair(x, fa[x])); return fa[x] == x ? x : fa[x] = getfa(fa[x]); } inline void bing(int x, int y) { if (vis[x] && vis[y]) { int fax = getfa(x); int fay = getfa(y); if (fax != fay) fa[fax] = fay; } } inline void Union(int x, int y) { int now = id[x][y]; bing(id[x + 1][y], now); bing(id[x + 1][y - 1], now); bing(id[x + 1][y + 1], now); bing(id[x - 1][y], now); bing(id[x - 1][y - 1], now); bing(id[x - 1][y + 1], now); bing(id[x][y - 1], now); bing(id[x][y + 1], now); } inline void rm() { while (!sta.empty()) { fa[sta.top().first] = sta.top().second; sta.pop(); } } int main() { scanf( %d%d%d , &n, &m, &q); int __cnt = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= (m << 1); ++j) { id[i][j] = ++__cnt; fa[id[i][j]] = id[i][j]; } } for (int i = 1; i <= n; ++i) { id[i][0] = id[i][m << 1]; id[i][m << 1 | 1] = id[i][1]; } int ans = 0; while (q--) { int x, y; scanf( %d%d , &x, &y); if (vis[id[x][y]]) continue; vis[id[x][y]] = vis[id[x][y + m]] = true; Union(x, y); Union(x, y + m); if (getfa(id[x][y]) == getfa(id[x][y + m])) { rm(); vis[id[x][y]] = vis[id[x][y + m]] = false; } else ans++; while (!sta.empty()) sta.pop(); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long double ld; const long double PI = 3.141592653589793238462643383279502884197169399375105820974944; long long mod = 1e9 + 7; const long long inf = 1e18; const long long maxn = 3e5 + 5; void solve() { long long n, k; cin >> n >> k; vector<pair<long long, pair<long long, long long>>> v(n); for (long long i = 0; i < n; i++) { cin >> v[i].first >> v[i].second.first; v[i].second.second = i + 1; } sort((v).begin(), (v).end()); multiset<pair<long long, long long>> s; vector<long long> ans; for (auto i : v) { while (!s.empty() && (*s.begin()).first < i.first) s.erase(s.begin()); while ((long long)((s).size()) > k) { auto it = --s.end(); ans.push_back((*it).second); s.erase(it); } if ((long long)((s).size()) == k) { auto it = --s.end(); if ((*it).first >= i.second.first) { ans.push_back((*it).second); s.erase(it); s.insert({i.second.first, i.second.second}); } else ans.push_back(i.second.second); } else s.insert({i.second.first, i.second.second}); } cout << (long long)((ans).size()) << n ; for (auto i : ans) cout << i << ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long tc = 1; while (tc--) { solve(); cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; scanf( %d , &T); while (T--) { int n, ans = 0; scanf( %d , &n); map<string, int> book; vector<string> aa, temp; for (int i = 1; i <= n; i++) { string s; cin >> s; book[s] = 1; temp.push_back(s); } for (vector<string>::iterator it = temp.begin(); it < temp.end(); it++) { string s; s = *it; if (book[s] == 1) { book[s]++; aa.push_back(s); } else { for (int i = 0; i <= 9; i++) { s[3] = i + 0 ; if (!book.count(s)) { book[s] = 1; aa.push_back(s); break; } } ans++; } } printf( %d n , ans); for (vector<string>::iterator it = aa.begin(); it < aa.end(); it++) cout << *it << endl; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb565_to_rgb888_0_0
(clk,
rgb_565,
rgb_888);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire clk;
wire [15:0]rgb_565;
wire [20:3]\^rgb_888 ;
assign rgb_888[23:21] = \^rgb_888 [18:16];
assign rgb_888[20:16] = \^rgb_888 [20:16];
assign rgb_888[15:14] = \^rgb_888 [9:8];
assign rgb_888[13:3] = \^rgb_888 [13:3];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 U0
(.clk(clk),
.rgb_565(rgb_565),
.rgb_888({\^rgb_888 [18:16],\^rgb_888 [20:19],\^rgb_888 [9:8],\^rgb_888 [13:10],\^rgb_888 [7:3]}));
endmodule
(* ORIG_REF_NAME = "rgb565_to_rgb888" *)
module system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
(rgb_888,
rgb_565,
clk);
output [15:0]rgb_888;
input [15:0]rgb_565;
input clk;
wire clk;
wire [15:0]rgb_565;
wire [15:0]rgb_888;
FDRE \rgb_888_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb_565[5]),
.Q(rgb_888[5]),
.R(1'b0));
FDRE \rgb_888_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb_565[6]),
.Q(rgb_888[6]),
.R(1'b0));
FDRE \rgb_888_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb_565[7]),
.Q(rgb_888[7]),
.R(1'b0));
FDRE \rgb_888_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb_565[8]),
.Q(rgb_888[8]),
.R(1'b0));
FDRE \rgb_888_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb_565[9]),
.Q(rgb_888[9]),
.R(1'b0));
FDRE \rgb_888_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb_565[10]),
.Q(rgb_888[10]),
.R(1'b0));
FDRE \rgb_888_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb_565[11]),
.Q(rgb_888[11]),
.R(1'b0));
FDRE \rgb_888_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb_565[12]),
.Q(rgb_888[12]),
.R(1'b0));
FDRE \rgb_888_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb_565[13]),
.Q(rgb_888[13]),
.R(1'b0));
FDRE \rgb_888_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb_565[14]),
.Q(rgb_888[14]),
.R(1'b0));
FDRE \rgb_888_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb_565[15]),
.Q(rgb_888[15]),
.R(1'b0));
FDRE \rgb_888_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_565[0]),
.Q(rgb_888[0]),
.R(1'b0));
FDRE \rgb_888_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_565[1]),
.Q(rgb_888[1]),
.R(1'b0));
FDRE \rgb_888_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_565[2]),
.Q(rgb_888[2]),
.R(1'b0));
FDRE \rgb_888_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_565[3]),
.Q(rgb_888[3]),
.R(1'b0));
FDRE \rgb_888_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb_565[4]),
.Q(rgb_888[4]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { if (a == 1 || b == 0) return 1; long long c = power(a, b / 2); long long res = 1; res = c * c; if (res >= 1000000007) res %= 1000000007; if (b % 2) res *= a; if (res >= 1000000007) res %= 1000000007; return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; string s; cin >> s; map<char, long long> count; for (long long i = 0; i < n; i++) { count[s[i]]++; } vector<long long> v; for (auto &i : count) { v.push_back(i.second); } long long ans = 0; sort(v.begin(), v.end(), greater<long long>()); for (long long i = 0; i < v.size(); i++) { if (v[i] == v[0]) ans++; } cout << power(ans, n); } |
// Copyright 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Tunable ring oscillator---synthesizable (physical) version.
//
// NOTE: This netlist cannot be simulated correctly due to lack
// of accurate timing in the digital cell verilog models.
module delay_stage(in, trim, out);
input in;
input [1:0] trim;
output out;
wire d0, d1, d2;
sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
.A(in),
.X(ts)
);
sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
.A(ts),
.X(d0)
);
sky130_fd_sc_hd__einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__einvn_4 delayenb1 (
.A(ts),
.TE_B(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
sky130_fd_sc_hd__einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
sky130_fd_sc_hd__einvn_8 delayenb0 (
.A(ts),
.TE_B(trim[0]),
.Z(out)
);
endmodule
module start_stage(in, trim, reset, out);
input in;
input [1:0] trim;
input reset;
output out;
wire d0, d1, d2, ctrl0, one;
sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
.A(in),
.X(d0)
);
sky130_fd_sc_hd__einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__einvn_4 delayenb1 (
.A(in),
.TE_B(trim[1]),
.Z(d1)
);
sky130_fd_sc_hd__clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
sky130_fd_sc_hd__einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
sky130_fd_sc_hd__einvn_8 delayenb0 (
.A(in),
.TE_B(ctrl0),
.Z(out)
);
sky130_fd_sc_hd__einvp_1 reseten0 (
.A(one),
.TE(reset),
.Z(out)
);
sky130_fd_sc_hd__or2_2 ctrlen0 (
.A(reset),
.B(trim[0]),
.X(ctrl0)
);
sky130_fd_sc_hd__conb_1 const1 (
.HI(one),
.LO()
);
endmodule
// Ring oscillator with 13 stages, each with two trim bits delay
// (see above). Trim is not binary: For trim[1:0], lower bit
// trim[0] is primary trim and must be applied first; upper
// bit trim[1] is secondary trim and should only be applied
// after the primary trim is applied, or it has no effect.
//
// Total effective number of inverter stages in this oscillator
// ranges from 13 at trim 0 to 65 at trim 24. The intention is
// to cover a range greater than 2x so that the midrange can be
// reached over all PVT conditions.
//
// Frequency of this ring oscillator under SPICE simulations at
// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
module ring_osc2x13(reset, trim, clockp);
input reset;
input [25:0] trim;
output[1:0] clockp;
wire [12:0] d;
wire [1:0] clockp;
wire [1:0] c;
// Main oscillator loop stages
genvar i;
generate
for (i = 0; i < 12; i = i + 1) begin : dstage
delay_stage id (
.in(d[i]),
.trim({trim[i+13], trim[i]}),
.out(d[i+1])
);
end
endgenerate
// Reset/startup stage
start_stage iss (
.in(d[12]),
.trim({trim[25], trim[12]}),
.reset(reset),
.out(d[0])
);
// Buffered outputs a 0 and 90 degrees phase (approximately)
sky130_fd_sc_hd__clkinv_2 ibufp00 (
.A(d[0]),
.Y(c[0])
);
sky130_fd_sc_hd__clkinv_8 ibufp01 (
.A(c[0]),
.Y(clockp[0])
);
sky130_fd_sc_hd__clkinv_2 ibufp10 (
.A(d[6]),
.Y(c[1])
);
sky130_fd_sc_hd__clkinv_8 ibufp11 (
.A(c[1]),
.Y(clockp[1])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[200010]; int price[200010]; bool vist[200010][2]; long long int dp[200010][2], sum[200010], ans[200010]; long long int gcd(long long int a, long long int b) { if (b == 0) return a; a %= b; return gcd(b, a); } long long int lcm(long long int a, long long int b) { return (a * b) / gcd(a, b); } int binsearch(int n, long long int arr[], long long int sum) { int l = 0, r = n - 1, mid; while (l <= r) { mid = (l + r) / 2; if (arr[mid] == sum) return mid; if (arr[mid] < sum) l = mid + 1; else r = mid - 1; } return -1; } void DFS(int u, int p) { if (p && g[u].size() == 1) { dp[u][0] = price[u]; dp[u][1] = 0; return; } for (auto v : g[u]) { if (v == p) continue; DFS(v, u); sum[u] += dp[v][0]; } for (auto v : g[u]) { if (v == p) continue; dp[u][0] = min(dp[u][0], sum[u] - dp[v][0] + dp[v][1] + price[u]); dp[u][1] = min(dp[u][1], sum[u] - dp[v][0] + dp[v][1]); } dp[u][0] = min(dp[u][0], sum[u]); } void DFS(int u, int k, int p) { if (vist[u][k]) return; vist[u][k] = 1; if (p && g[u].size() == 1) { if (!k) ans[u] = 1; return; } if (!k) { if (dp[u][0] == dp[u][1] + price[u]) { ans[u] = 1; int cnt = 0; for (auto v : g[u]) { if (v == p) continue; if (dp[v][1] - dp[v][0] == dp[u][1] - sum[u]) DFS(v, 1, u), cnt++; } for (auto v : g[u]) { if (v == p) continue; if (cnt > 1 || dp[v][1] - dp[v][0] != dp[u][1] - sum[u]) DFS(v, 0, u); } } if (dp[u][0] == sum[u]) { for (auto v : g[u]) { if (v == p) continue; DFS(v, 0, u); } } } else { int cnt = 0; for (auto v : g[u]) { if (v == p) continue; if (dp[v][1] - dp[v][0] == dp[u][1] - sum[u]) DFS(v, 1, u), cnt++; } for (auto v : g[u]) { if (v == p) continue; if (cnt > 1 || dp[v][1] - dp[v][0] != dp[u][1] - sum[u]) DFS(v, 0, u); } } } int main() { int n, u, v, cnt = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &price[i]), dp[i][0] = dp[i][1] = LONG_LONG_MAX; for (int i = 0; i < n - 1; i++) scanf( %d %d , &u, &v), g[u].push_back(v), g[v].push_back(u); DFS(1, 0); DFS(1, 0, 0); printf( %lld , dp[1][0]); for (int i = 1; i <= n; i++) if (ans[i]) cnt++; printf( %d n , cnt); for (int i = 1; i <= n; i++) if (ans[i]) printf( %d , i); return 0; } |
#include <bits/stdc++.h> using namespace std; void input() { freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); } const int N = 1e6 + 10; vector<int> G[N]; int in[N], n, cnt[3], vis[N]; void dfs(int x, int flag) { cnt[flag]++; vis[x] = 1; for (int i = 0; i < G[x].size(); i++) { int u = G[x][i]; if (vis[u]) continue; dfs(u, (flag + 1) % 2); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n - 1; i++) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } dfs(1, 1); cout << min(cnt[0], cnt[1]) - 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; template <typename T> using posteriority_queue = priority_queue<T, vector<T>, greater<T> >; const int INF = 0x3f3f3f3f; const ll LINF = 0x3f3f3f3f3f3f3f3fLL; const double EPS = 1e-8; const int MOD = 1000000007; const int dy[] = {1, 0, -1, 0}, dx[] = {0, -1, 0, 1}; const int dy8[] = {1, 1, 0, -1, -1, -1, 0, 1}, dx8[] = {0, -1, -1, -1, 0, 1, 1, 1}; template <typename T, typename U> inline bool chmax(T &a, U b) { return a < b ? (a = b, true) : false; } template <typename T, typename U> inline bool chmin(T &a, U b) { return a > b ? (a = b, true) : false; } template <typename T> void unique(vector<T> &a) { a.erase(unique((a).begin(), (a).end()), a.end()); } struct IOSetup { IOSetup() { cin.tie(nullptr); ios_base::sync_with_stdio(false); cout << fixed << setprecision(20); } } iosetup; using CostType = ll; struct Edge { int src, dst; CostType cost; Edge(int src, int dst, CostType cost = 0) : src(src), dst(dst), cost(cost) {} inline bool operator<(const Edge &rhs) const { return cost != rhs.cost ? cost < rhs.cost : dst != rhs.dst ? dst < rhs.dst : src < rhs.src; } inline bool operator<=(const Edge &rhs) const { return !(rhs < *this); } inline bool operator>(const Edge &rhs) const { return rhs < *this; } inline bool operator>=(const Edge &rhs) const { return !(*this < rhs); } }; struct CentroidDecomposition { int root; vector<vector<int> > comp; vector<int> par; CentroidDecomposition(const vector<vector<Edge> > &graph) : graph(graph) { int n = graph.size(); alive.assign(n, true); subtree.resize(n); comp.resize(n); par.assign(n, -1); root = build(0); } private: const vector<vector<Edge> > graph; vector<bool> alive; vector<int> subtree; int build(int s) { int centroid = search_centroid(-1, s, calc_subtree(-1, s) / 2); alive[centroid] = false; for (const Edge &e : graph[centroid]) { if (alive[e.dst]) { comp[centroid].emplace_back(build(e.dst)); par[e.dst] = centroid; } } alive[centroid] = true; return centroid; } int calc_subtree(int par, int ver) { subtree[ver] = 1; for (const Edge &e : graph[ver]) { if (e.dst != par && alive[e.dst]) subtree[ver] += calc_subtree(ver, e.dst); } return subtree[ver]; } int search_centroid(int par, int ver, int half) { for (const Edge &e : graph[ver]) { if (e.dst != par && alive[e.dst]) { if (subtree[e.dst] > half) return search_centroid(ver, e.dst, half); } } return ver; } }; template <typename T> struct LiChaoTree { struct Line { T a, b; Line(T a, T b) : a(a), b(b) {} T f(T x) { return a * x + b; } }; LiChaoTree(const vector<T> &xs_, const T TINF, bool is_minimized = true) : xs(xs_), TINF(TINF), is_minimized(is_minimized) { sort((xs).begin(), (xs).end()); unique(xs); int sz = xs.size(); while (n < sz) n <<= 1; xs.resize(n, TINF); Line unity(0, is_minimized ? TINF : -TINF); dat.assign(n << 1, unity); } void add(T a, T b) { Line line(a, b); add(line, 1, 0, n); } void add(T a, T b, T left, T right) { int l = lower_bound((xs).begin(), (xs).end(), left) - xs.begin(), r = lower_bound((xs).begin(), (xs).end(), right) - xs.begin(); int len, node_l = l, node_r = r; for (l += n, r += n, len = 1; l < r; l >>= 1, r >>= 1, len <<= 1) { if (l & 1) { Line line(a, b); add(line, l++, node_l, node_l + len); node_l += len; } if (r & 1) { Line line(a, b); node_r -= len; add(line, --r, node_r, node_r + len); } } } T query(T x) { int node = lower_bound((xs).begin(), (xs).end(), x) - xs.begin(); node += n; T res = dat[node].f(x); while (node >>= 1) { if (is_minimized) { chmin(res, dat[node].f(x)); } else { chmax(res, dat[node].f(x)); } } return res; } private: const T TINF; bool is_minimized; int n = 1; vector<T> xs; vector<Line> dat; void add(Line &line, int node, int left, int right) { bool l = dat[node].f(xs[left]) <= line.f(xs[left]), r = dat[node].f(xs[right - 1]) <= line.f(xs[right - 1]); if (l && r) { if (!is_minimized) swap(dat[node], line); return; } if (!l && !r) { if (is_minimized) swap(dat[node], line); return; } int mid = (left + right) >> 1; bool m = line.f(xs[mid]) < dat[node].f(xs[mid]); if (is_minimized) { if (m) swap(dat[node], line); } else { if (!m) swap(dat[node], line); } if (line.f(xs[left]) <= dat[node].f(xs[left])) { if (is_minimized) { add(line, node << 1, left, mid); } else { add(line, (node << 1) + 1, mid, right); } } else { if (is_minimized) { add(line, (node << 1) + 1, mid, right); } else { add(line, node << 1, left, mid); } } } }; int main() { int n; cin >> n; vector<vector<Edge> > graph(n); for (int _ = (0); _ < (n - 1); ++_) { int u, v; cin >> u >> v; --u; --v; graph[u].emplace_back(u, v); graph[v].emplace_back(v, u); } vector<int> a(n); for (int i = (0); i < (n); ++i) cin >> a[i]; CentroidDecomposition cent(graph); vector<bool> visited(n, false); ll ans = 0; function<void(int)> dfs = [&](int root) { visited[root] = true; chmax(ans, a[root]); vector<vector<ll> > sum_a, psum_a; vector<vector<pair<ll, int> > > psum_b; function<void(int, int, int, ll, ll, ll, int)> dfs2 = [&](int par, int ver, int idx, ll sum, ll A, ll B, int len) { sum += a[ver]; A += 1LL * a[ver] * len; B += sum - a[root]; bool leaf = true; for (const Edge &e : graph[ver]) { if (e.dst == par || visited[e.dst]) continue; dfs2(ver, e.dst, idx, sum, A, B, len + 1); leaf = false; } if (leaf) { sum_a[idx].emplace_back(sum); psum_a[idx].emplace_back(A); psum_b[idx].emplace_back(B, len - 1); } }; for (const Edge &e : graph[root]) { if (visited[e.dst]) continue; int sz = sum_a.size(); sum_a.emplace_back(); psum_a.emplace_back(); psum_b.emplace_back(); dfs2(-1, e.dst, sz, a[root], a[root], 0, 2); } int m = sum_a.size(); vector<ll> xs; for (int i = (0); i < (m); ++i) { for (ll e : sum_a[i]) xs.emplace_back(e); for (ll e : psum_a[i]) chmax(ans, e); for (auto pr : psum_b[i]) chmax(ans, pr.first + 1LL * a[root] * (pr.second + 1)); } if (!xs.empty()) { sort((xs).begin(), (xs).end()); unique(xs); LiChaoTree<ll> lct1(xs, LINF, false); for (int i = (0); i < (m); ++i) { int sz = sum_a[i].size(); for (int j = (0); j < (sz); ++j) chmax(ans, lct1.query(sum_a[i][j]) + psum_a[i][j]); for (int j = (0); j < (sz); ++j) lct1.add(psum_b[i][j].second, psum_b[i][j].first); } LiChaoTree<ll> lct2(xs, LINF, false); for (int i = m - 1; i >= 0; --i) { int sz = sum_a[i].size(); for (int j = (0); j < (sz); ++j) chmax(ans, lct2.query(sum_a[i][j]) + psum_a[i][j]); for (int j = (0); j < (sz); ++j) lct2.add(psum_b[i][j].second, psum_b[i][j].first); } } for (int e : cent.comp[root]) dfs(e); }; dfs(cent.root); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; priority_queue<pair<long long int, long long int> > p_que; long long int arr[300005]; long long int ans[300005]; int main(int argc, char const *argv[]) { long long int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> arr[i]; } for (int i = 1; i <= k; i++) { p_que.push(make_pair(arr[i], i)); } long long int tot = 0; for (int i = k + 1; i <= n + k; i++) { if (i <= n) p_que.push(make_pair(arr[i], i)); pair<long long int, long long int> p = p_que.top(); p_que.pop(); tot = tot + (i - p.second) * p.first; ans[p.second] = i; } cout << tot << n ; for (int i = 1; i <= n; i++) { cout << ans[i] << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int sum, i, j, a[5][5], n, b[20]; int check() { int res = 0; int i, j, nowsum; for (i = 0; i < n; i++) for (j = 0; j < n; j++) { a[i][j] = b[i * n + j]; } for (i = 0; i < n; i++) { nowsum = 0; for (j = 0; j < n; j++) nowsum += a[i][j]; res += abs(sum - nowsum); } for (j = 0; j < n; j++) { nowsum = 0; for (i = 0; i < n; i++) nowsum += a[i][j]; res += abs(sum - nowsum); } nowsum = 0; for (i = 0; i < n; i++) nowsum += a[i][i]; res += abs(nowsum - sum); nowsum = 0; for (i = 0; i < n; i++) nowsum += a[i][n - i - 1]; res += abs(nowsum - sum); return res; } int main() { srand((unsigned)time(NULL)); cin >> n; for (i = 0; i < n * n; i++) { cin >> b[i]; sum += b[i]; } sum /= n; int q, p, i, j; q = check(); while (q) { random_shuffle(b, b + n * n); q = check(); for (int iter = 0; iter < 1000; iter++) { i = (rand() * 257) % (n * n); j = (rand() * 37) % (n * n); while (j == i) { j = (rand() * 37) % (n * n); } if (i > j) swap(i, j); swap(b[i], b[j]); p = check(); if (p < q) { q = p; } else { swap(b[i], b[j]); } } q = check(); } cout << sum << endl; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) cout << a[i][j] << ; cout << endl; } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_sc_1_rep2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_sc_1_rep2(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_buf, dram_scbuf_ecc_r2_buf,
scbuf_dram_wr_data_r5_buf, scbuf_dram_data_vld_r5_buf,
scbuf_dram_data_mecc_r5_buf, sctag_dram_rd_req_buf,
sctag_dram_rd_dummy_req_buf, sctag_dram_rd_req_id_buf,
sctag_dram_addr_buf, sctag_dram_wr_req_buf, dram_sctag_rd_ack_buf,
dram_sctag_wr_ack_buf, dram_sctag_chunk_id_r0_buf,
dram_sctag_data_vld_r0_buf, dram_sctag_rd_req_id_r0_buf,
dram_sctag_secc_err_r2_buf, dram_sctag_mecc_err_r2_buf,
dram_sctag_scb_mecc_err_buf, dram_sctag_scb_secc_err_buf,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_buf;
output [27:0] dram_scbuf_ecc_r2_buf;
// scbuf to dram TOp
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// BOTTOM
output [63:0] scbuf_dram_wr_data_r5_buf;
output scbuf_dram_data_vld_r5_buf;
output scbuf_dram_data_mecc_r5_buf;
// sctag_dramsctag signals INputs
// @ the TOp.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
// sctag_dram BOTTOM
output sctag_dram_rd_req_buf;
output sctag_dram_rd_dummy_req_buf;
output [2:0] sctag_dram_rd_req_id_buf;
output [39:5] sctag_dram_addr_buf;
output sctag_dram_wr_req_buf;
// Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
// outputs BOTTOM
output dram_sctag_rd_ack_buf;
output dram_sctag_wr_ack_buf;
output [1:0] dram_sctag_chunk_id_r0_buf;
output dram_sctag_data_vld_r0_buf;
output [2:0] dram_sctag_rd_req_id_r0_buf;
output dram_sctag_secc_err_r2_buf ;
output dram_sctag_mecc_err_r2_buf ;
output dram_sctag_scb_mecc_err_buf;
output dram_sctag_scb_secc_err_buf;
// The placement of pins on the top and bottom should be identical to
// the placement of the data column of pins in dram_l2_buf1.v
assign dram_scbuf_data_r2_buf = dram_scbuf_data_r2 ;
assign dram_scbuf_ecc_r2_buf = dram_scbuf_ecc_r2 ;
assign scbuf_dram_wr_data_r5_buf = scbuf_dram_wr_data_r5 ;
assign scbuf_dram_data_vld_r5_buf = scbuf_dram_data_vld_r5 ;
assign scbuf_dram_data_mecc_r5_buf = scbuf_dram_data_mecc_r5 ;
assign dram_sctag_rd_ack_buf = dram_sctag_rd_ack ;
assign dram_sctag_wr_ack_buf = dram_sctag_wr_ack ;
assign dram_sctag_chunk_id_r0_buf = dram_sctag_chunk_id_r0 ;
assign dram_sctag_data_vld_r0_buf = dram_sctag_data_vld_r0;
assign dram_sctag_rd_req_id_r0_buf = dram_sctag_rd_req_id_r0;
assign dram_sctag_secc_err_r2_buf = dram_sctag_secc_err_r2;
assign dram_sctag_mecc_err_r2_buf = dram_sctag_mecc_err_r2;
assign dram_sctag_scb_mecc_err_buf = dram_sctag_scb_mecc_err;
assign dram_sctag_scb_secc_err_buf = dram_sctag_scb_secc_err;
assign sctag_dram_rd_req_buf = sctag_dram_rd_req ;
assign sctag_dram_rd_dummy_req_buf = sctag_dram_rd_dummy_req ;
assign sctag_dram_rd_req_id_buf = sctag_dram_rd_req_id ;
assign sctag_dram_addr_buf = sctag_dram_addr ;
assign sctag_dram_wr_req_buf = sctag_dram_wr_req ;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; long long f(int x, int len) { if (len == 0) return 0; if (x > len) return (long long)len * (2 * x - len - 1) / 2; else return (long long)x * (x - 1) / 2 + len - x + 1; } bool ok(int x) { if (f(x, k - 1) + f(x, n - k) + x <= m) return 1; else return 0; } int main() { cin >> n >> m >> k; int l = 1, r = 1e9; while (r - l > 1) { int mid = (l + r) / 2; if (ok(mid)) { l = mid; } else { r = mid; } } int res = 0; if (ok(l)) res = l; if (ok(r)) res = r; cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == 1 ) continue; if (s[i] == 4 && s[i - 1] == 1 ) continue; if (s[i] == 4 && i > 1 && s[i - 1] == 4 && s[i - 2] == 1 ) continue; return cout << NO , 0; } cout << YES ; } |
#include <bits/stdc++.h> using namespace std; int mas[21][21]; int n, m; inline bool checkarr() { for (int i = 0; i < n; i++) { int wrongs = 0; for (int j = 0; j < m; j++) { if (mas[i][j] != j + 1) wrongs++; if (wrongs > 2) return false; } } return true; } inline void swapa(int a, int b) { for (int j = 0; j < n; j++) { int t = mas[j][a]; mas[j][a] = mas[j][b]; mas[j][b] = t; } } int main() { cin >> n >> m; int i, j; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> mas[i][j]; } } if (checkarr()) { cout << YES ; return 0; } for (i = 0; i < m; i++) { for (j = i + 1; j < m; j++) { swapa(i, j); if (checkarr()) { cout << YES ; return 0; } swapa(i, j); } } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; char s[100005]; int cnt[30]; int main() { int k, i; scanf( %s , s); scanf( %d , &k); for (i = 0; s[i]; i++) cnt[s[i] - a ]++; if (k >= i) { puts( 0 n ); return 0; } while (1) { int minx = 1 << 30, mini; for (i = 0; i < 30; i++) { if (cnt[i]) { minx = min(cnt[i], minx); if (minx == cnt[i]) mini = i; } } if (k >= cnt[mini]) { k -= cnt[mini]; cnt[mini] = 0; } else break; } int ans = 0; for (i = 0; i < 30; i++) if (cnt[i]) ans++; printf( %d n , ans); for (i = 0; s[i]; i++) { if (cnt[s[i] - a ]) putchar(s[i]); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_4_V
`define SKY130_FD_SC_MS__EINVN_4_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d, maxi1, maxi2; cin >> a >> b >> c >> d; maxi1 = max(((3 * a) / 10), (a - ((a / 250) * c))); maxi2 = max(((3 * b) / 10), (b - ((b / 250) * d))); if (maxi1 == maxi2) { cout << Tie n ; } else if (maxi2 > maxi1) { cout << Vasya n ; } else { cout << Misha n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool vis[100010]; int pr[100010], e; void Shai() { vis[1] = true; for (long long i = 2; i <= 1000ll; i++) { if (!vis[i]) { pr[++e] = i; for (long long j = i * i; j <= 1000ll; j += i) { vis[j] = true; } } } } int n, cnta[100010]; int main() { Shai(); int x, y; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , &x, &y); int X = x; for (int j = 1; j <= e; ++j) { if (X % pr[j] == 0) { while (X % pr[j] == 0) { X /= pr[j]; ++cnta[j]; } } } bool lose = 0; for (int j = 1; j <= e; ++j) { int cntb = 0; if (y % pr[j] == 0) { while (y % pr[j] == 0) { y /= pr[j]; ++cntb; } } if ((cnta[j] + cntb) % 3 != 0) { lose = 1; break; } else if (min(cnta[j], cntb) * 2 < max(cnta[j], cntb)) { lose = 1; break; } } if (!(X == 1 && y == 1) && !((long long)min(X, y) * (long long)min(X, y) == (long long)max(X, y))) { lose = 1; } for (int j = 1; j <= e; ++j) { cnta[j] = 0; } if (!lose) puts( Yes ); else puts( No ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, i; cin >> t; for (i = 0; i < t; i++) { int n, k1, k2, j, f; cin >> n >> k1 >> k2; int a[100], b[100], sum, hum; for (j = 0; j < k1; j++) { cin >> a[j]; } sum = a[0]; for (j = 0; j < k1; j++) { if (a[j] > sum) { sum = a[j]; } } for (f = 0; f < k2; f++) { cin >> b[f]; } hum = b[0]; for (f = 0; f < k2; f++) { if (b[f] > hum) { hum = b[f]; } } if (sum > hum) { cout << YES << endl; } else { cout << NO << endl; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_4_V
`define SKY130_FD_SC_HD__A21O_4_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21o_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21o_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_4_V
|
#include <bits/stdc++.h> using namespace std; long long d[111111]; long long sum[111111]; int q[111111]; long long cat[111111]; long long dp[101][100001]; long long getDP(int i, int j, int k) { return (long long)j * cat[j] + dp[i - 1][k] - j * cat[k]; } long long getUP(int i, int j, int k) { return (long long)dp[i - 1][j] - dp[i - 1][k]; } long long getDOWN(int j, int k) { return (long long)cat[j] - cat[k]; } int main() { int i, j, k, n, m, p, h; cin >> n >> m >> p; for (i = 2; i <= n; i++) { cin >> d[i]; d[i] += d[i - 1]; } for (i = 1; i <= m; i++) { cin >> h >> cat[i]; cat[i] -= d[h]; } sort(cat + 1, cat + 1 + m); for (i = 1; i <= m; i++) sum[i] = sum[i - 1] + cat[i]; for (i = 1; i <= p; i++) for (j = 1; j <= m; j++) dp[i][j] = 999999999999999; dp[1][m] = (long long)m * cat[m] - sum[m]; for (i = 2; i <= p; i++) { int head, tail; head = tail = 0; q[tail++] = m; for (j = m; j >= 1; j--) { while (head + 1 < tail && (getUP(i, q[head + 1], q[head]) <= j * getDOWN(q[head + 1], q[head]))) head++; dp[i][j] = min(dp[i][j], getDP(i, j, q[head])); while (head + 1 < tail && getUP(i, j, q[tail - 1]) * getDOWN(q[tail - 1], q[tail - 2]) > getUP(i, q[tail - 1], q[tail - 2]) * getDOWN(j, q[tail - 1])) tail--; q[tail++] = j; } } long long ans = dp[p][1]; for (i = 1; i <= m; i++) ans = min(ans, dp[p][i]); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100000 + 1; const int INF = numeric_limits<int>::max() / 2; pair<int, int> P[MAX_N]; pair<int, int> prefix[MAX_N], suffix[MAX_N]; int N; long long square(int first) { return 1LL * first * first; } bool valid(long long M) { long long bestY, bestXY; int i = 1, j = 1; while (i <= N) { while (square(P[i].first - P[j].first) > M) j++; assert(j <= i); assert(square(P[i].first - P[j].first) <= M); int maxY = -INF; int minY = INF; bool changed = false; if (j > 1) { changed = true; minY = min(minY, prefix[j - 1].first); maxY = max(maxY, prefix[j - 1].second); } if (i < N) { changed = true; minY = min(minY, suffix[i + 1].first); maxY = max(maxY, suffix[i + 1].second); } if (changed) { bestY = square(maxY - minY); bestXY = max(square(maxY), square(minY)) + max(square(P[i].first), square(P[j].first)); } else bestY = 0, bestXY = 0; if (bestY <= M && bestXY <= M) return true; i++; } return false; } void makePrefixSuffix() { pair<int, int> p = {INF, -INF}; for (int i = 1; i <= N; ++i) { p.first = min(p.first, P[i].second); p.second = max(p.second, P[i].second); prefix[i] = p; } p = {INF, -INF}; for (int i = N; i >= 1; i--) { p.first = min(p.first, P[i].second); p.second = max(p.second, P[i].second); suffix[i] = p; } } long long binarySearch() { long long l = 0; long long r = 1LL * INF * INF >> 1; long long sol = -1; while (l <= r) { long long m = (l + r) / 2; if (valid(m)) { sol = m; r = m - 1; } else l = m + 1; } return sol; } int main() { ios_base::sync_with_stdio(false); cin >> N; for (int i = 1; i <= N; ++i) cin >> P[i].first >> P[i].second; sort(P + 1, P + N + 1); makePrefixSuffix(); long long sol1 = binarySearch(); for (int i = 1; i <= N; ++i) swap(P[i].first, P[i].second); sort(P + 1, P + N + 1); makePrefixSuffix(); long long sol2 = binarySearch(); cout << min(sol1, sol2) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const long long maxn = 110; struct node { int v, cost; } a[1500]; int N, K, dp1[100 * 150], dp2[100 * 150]; int solve() { memset(dp1, -0x3f3f3f3f, sizeof(dp1)); ; memset(dp2, -0x3f3f3f3f, sizeof(dp2)); ; dp1[1] = dp2[1] = 0; for (int i = 1; i <= N; i++) { if (a[i].cost >= 0) { for (int j = 100 * 105; j >= a[i].cost; j--) dp1[j] = max(dp1[j], dp1[j - a[i].cost] + a[i].v); } else { a[i].cost = -a[i].cost; for (int j = 100 * 105; j >= a[i].cost; j--) dp2[j] = max(dp2[j], dp2[j - a[i].cost] + a[i].v); } } int ans = -1; for (int i = 0; i <= 100 * 105; i++) { if (dp1[i] + dp2[i] != 0 && dp1[i] + dp2[i] > ans) ans = dp1[i] + dp2[i]; } return ans; } int main() { cin >> N >> K; for (int i = 1; i <= N; i++) cin >> a[i].v; int b; for (int i = 1; i <= N; i++) cin >> b, a[i].cost = a[i].v - K * b; cout << solve() << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSRECEIVER_BLACKBOX_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busreceiver (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_BLACKBOX_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 29; const double EPS = 1e-10; vector<int> G[50010]; vector<int> chil[50010]; int cnt[50010][510]; void dfs(int pos, int par) { for (int i = 0; i < (int)G[pos].size(); i++) { if (G[pos][i] != par) { chil[pos].push_back(G[pos][i]); dfs(G[pos][i], pos); } } } void init(int n) { memset(cnt, 0, sizeof(cnt)); dfs(0, -1); } void calc(int v, int k, long long &sum) { for (int i = 0; i < (int)chil[v].size(); i++) { int c = chil[v][i]; calc(c, k, sum); for (int j = 0; j < k; j++) { sum += (long long)cnt[c][j] * cnt[v][k - j - 1]; } for (int j = 0; j < k; j++) { cnt[v][j + 1] += cnt[c][j]; } } cnt[v][0] = 1; sum += (long long)cnt[v][0] * cnt[v][k]; } int main() { int n, k, a, b; cin >> n >> k; for (int i = 0; i < n - 1; i++) { cin >> a >> b; a--, b--; G[a].push_back(b); G[b].push_back(a); } init(n); long long res = 0; calc(0, k, res); cout << res << endl; return 0; } |
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* System fabric (version 2)
*/
`include "common.vh"
`include "ocp_const.vh"
/* Address decoder */
module fabric2_decoder #(
parameter PORTNO_WIDTH = 11
)
(
i_addr,
o_addr,
o_portno
);
localparam PORT_BITS = PORTNO_WIDTH + 1;
input wire [`ADDR_WIDTH-1:0] i_addr;
output wire [`ADDR_WIDTH-1:0] o_addr;
output wire [PORTNO_WIDTH-1:0] o_portno;
/* Decode address */
assign o_addr = (!i_addr[`ADDR_WIDTH-1] ? { 1'b0, i_addr[`ADDR_WIDTH-2:0] } :
{ {(PORT_BITS){1'b0}}, i_addr[`ADDR_WIDTH-PORT_BITS-1:0] });
/* Decode port number */
assign o_portno = (i_addr[`ADDR_WIDTH-1] ? i_addr[`ADDR_WIDTH-2:`ADDR_WIDTH-PORT_BITS] + 1'b1 :
{(PORT_BITS-1){1'b0}});
endmodule /* fabric2_decoder */
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The PORRST circuit
//
// ====================================================================
module sirv_aon_porrst(
output porrst_n
);
`ifdef FPGA_SOURCE//{
// In FPGA, we have no PORRST circult
assign porrst_n = 1'b1;
`else //}{
assign porrst_n = 1'b1;
`endif//}
endmodule
|
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