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//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
module pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 6: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 128,
the_altsyncram.numwords_a = 128,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 7;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int primes[] = { 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719, 727, 733, 739, 743, 751, 757, 761, 769, 773, 787, 797, 809, 811, 821, 823, 827, 829, 839, 853, 857, 859, 863, 877, 881, 883, 887, 907, 911, 919, 929, 937, 941, 947, 953, 967, 971, 977, 983, 991, 997, 1009, 1013, 1019, 1021, 1031, 1033, 1039, 1049, 1051, 1061, 1063, 1069, 1087, 1091, 1093, 1097, 1103, 1109, 1117, 1123, 1129, 1151, 1153, 1163, 1171, 1181, 1187, 1193, 1201, 1213, 1217, 1223, 1229, 1231, 1237, 1249, 1259, 1277, 1279, 1283, 1289, 1291, 1297, 1301, 1303, 1307, 1319, 1321, 1327, 1361, 1367, 1373, 1381, 1399, 1409, 1423, 1427, 1429, 1433, 1439, 1447, 1451, 1453, 1459, 1471, 1481, 1483, 1487, 1489, 1493, 1499, 1511, 1523, 1531, 1543, 1549, 1553, 1559, 1567, 1571, 1579, 1583, 1597, 1601, 1607, 1609, 1613, 1619, 1621, 1627, 1637, 1657, 1663, 1667, 1669, 1693, 1697, 1699, 1709, 1721, 1723, 1733, 1741, 1747, 1753, 1759, 1777, 1783, 1787, 1789, 1801, 1811, 1823, 1831, 1847, 1861, 1867, 1871, 1873, 1877, 1879, 1889, 1901, 1907, 1913, 1931, 1933, 1949, 1951, 1973, 1979, 1987, 1993, 1997, 1999, 2003, 2011, 2017, 2027, 2029, 2039, 2053, 2063, 2069, 2081, 2083, 2087, 2089, 2099, 2111, 2113, 2129, 2131, 2137, 2141, 2143, 2153, 2161, 2179, 2203, 2207, 2213, 2221, 2237, 2239, 2243, 2251, 2267, 2269, 2273, 2281, 2287, 2293, 2297, 2309, 2311, 2333, 2339, 2341, 2347, 2351, 2357, 2371, 2377, 2381, 2383, 2389, 2393, 2399, 2411, 2417, 2423, 2437, 2441, 2447, 2459, 2467, 2473, 2477, 2503, 2521, 2531, 2539, 2543, 2549, 2551, 2557, 2579, 2591, 2593, 2609, 2617, 2621, 2633, 2647, 2657, 2659, 2663, 2671, 2677, 2683, 2687, 2689, 2693, 2699, 2707, 2711, 2713, 2719, 2729, 2731, 2741, 2749, 2753, 2767, 2777, 2789, 2791, 2797, 2801, 2803, 2819, 2833, 2837, 2843, 2851, 2857, 2861, 2879, 2887, 2897, 2903, 2909, 2917, 2927, 2939, 2953, 2957, 2963, 2969, 2971, 2999, 3001, 3011, 3019, 3023, 3037, 3041, 3049, 3061, 3067, 3079, 3083, 3089, 3109, 3119, 3121, 3137, 3163, 3167, 3169, 3181, 3187, 3191, 3203, 3209, 3217, 3221, 3229, 3251, 3253, 3257, 3259, 3271, 3299, 3301, 3307, 3313, 3319, 3323, 3329, 3331, 3343, 3347, 3359, 3361, 3371, 3373, 3389, 3391, 3407, 3413, 3433, 3449, 3457, 3461, 3463, 3467, 3469, 3491, 3499, 3511, 3517, 3527, 3529, 3533, 3539, 3541, 3547, 3557, 3559, 3571, 3581, 3583, 3593, 3607, 3613, 3617, 3623, 3631, 3637, 3643, 3659, 3671, 3673, 3677, 3691, 3697, 3701, 3709, 3719, 3727, 3733, 3739, 3761, 3767, 3769, 3779, 3793, 3797, 3803, 3821, 3823, 3833, 3847, 3851, 3853, 3863, 3877, 3881, 3889, 3907, 3911, 3917, 3919, 3923, 3929, 3931, 3943, 3947, 3967, 3989, 4001, 4003, 4007, 4013, 4019, 4021, 4027, 4049, 4051, 4057, 4073, 4079, 4091, 4093, 4099, 4111, 4127, 4129, 4133, 4139, 4153, 4157, 4159, 4177, 4201, 4211, 4217, 4219, 4229, 4231, 4241, 4243, 4253, 4259, 4261, 4271, 4273, 4283, 4289, 4297, 4327, 4337, 4339, 4349, 4357, 4363, 4373, 4391, 4397, 4409, 4421, 4423, 4441, 4447, 4451, 4457, 4463, 4481, 4483, 4493, 4507, 4513, 4517, 4519, 4523, 4547, 4549, 4561, 4567, 4583, 4591, 4597, 4603, 4621, 4637, 4639, 4643, 4649, 4651, 4657, 4663, 4673, 4679, 4691, 4703, 4721, 4723, 4729, 4733, 4751, 4759, 4783, 4787, 4789, 4793, 4799, 4801, 4813, 4817, 4831, 4861, 4871, 4877, 4889, 4903, 4909, 4919, 4931, 4933, 4937, 4943, 4951, 4957, 4967, 4969, 4973, 4987, 4993, 4999, 5003, 5009, 5011, 5021, 5023, 5039, 5051, 5059, 5077, 5081, 5087, 5099, 5101, 5107, 5113, 5119, 5147, 5153, 5167, 5171, 5179, 5189, 5197, 5209, 5227, 5231, 5233, 5237, 5261, 5273, 5279, 5281, 5297, 5303, 5309, 5323, 5333, 5347, 5351, 5381, 5387, 5393, 5399, 5407, 5413, 5417, 5419, 5431, 5437, 5441, 5443, 5449, 5471, 5477, 5479, 5483, 5501, 5503, 5507, 5519, 5521, 5527, 5531, 5557, 5563, 5569, 5573, 5581, 5591, 5623, 5639, 5641, 5647, 5651, 5653, 5657, 5659, 5669, 5683, 5689, 5693, 5701, 5711, 5717, 5737, 5741, 5743, 5749, 5779, 5783, 5791, 5801, 5807, 5813, 5821, 5827, 5839, 5843, 5849, 5851, 5857, 5861, 5867, 5869, 5879, 5881, 5897, 5903, 5923, 5927, 5939, 5953, 5981, 5987, 6007, 6011, 6029, 6037, 6043, 6047, 6053, 6067, 6073, 6079, 6089, 6091, 6101, 6113, 6121, 6131, 6133, 6143, 6151, 6163, 6173, 6197, 6199, 6203, 6211, 6217, 6221, 6229, 6247, 6257, 6263, 6269, 6271, 6277, 6287, 6299, 6301, 6311, 6317, 6323, 6329, 6337, 6343, 6353, 6359, 6361, 6367, 6373, 6379, 6389, 6397, 6421, 6427, 6449, 6451, 6469, 6473, 6481, 6491, 6521, 6529, 6547, 6551, 6553, 6563, 6569, 6571, 6577, 6581, 6599, 6607, 6619, 6637, 6653, 6659, 6661, 6673, 6679, 6689, 6691, 6701, 6703, 6709, 6719, 6733, 6737, 6761, 6763, 6779, 6781, 6791, 6793, 6803, 6823, 6827, 6829, 6833, 6841, 6857, 6863, 6869, 6871, 6883, 6899, 6907, 6911, 6917, 6947, 6949, 6959, 6961, 6967, 6971, 6977, 6983, 6991, 6997, 7001, 7013, 7019, 7027, 7039, 7043, 7057, 7069, 7079, 7103, 7109, 7121, 7127, 7129, 7151, 7159, 7177, 7187, 7193, 7207, 7211, 7213, 7219, 7229, 7237, 7243, 7247, 7253, 7283, 7297, 7307, 7309, 7321, 7331, 7333, 7349, 7351, 7369, 7393, 7411, 7417, 7433, 7451, 7457, 7459, 7477, 7481, 7487, 7489, 7499, 7507, 7517, 7523, 7529, 7537, 7541, 7547, 7549, 7559, 7561, 7573, 7577, 7583, 7589, 7591, 7603, 7607, 7621, 7639, 7643, 7649, 7669, 7673, 7681, 7687, 7691, 7699, 7703, 7717, 7723, 7727, 7741, 7753, 7757, 7759, 7789, 7793, 7817, 7823, 7829, 7841, 7853, 7867, 7873, 7877, 7879, 7883, 7901, 7907, 7919, 7927, 7933, 7937, 7949, 7951, 7963, 7993, 8009, 8011, 8017, 8039, 8053, 8059, 8069, 8081, 8087, 8089, 8093, 8101, 8111, 8117, 8123, 8147, 8161, 8167, 8171, 8179, 8191, 8209, 8219, 8221, 8231, 8233, 8237, 8243, 8263, 8269, 8273, 8287, 8291, 8293, 8297, 8311, 8317, 8329, 8353, 8363, 8369, 8377, 8387, 8389, 8419, 8423, 8429, 8431, 8443, 8447, 8461, 8467, 8501, 8513, 8521, 8527, 8537, 8539, 8543, 8563, 8573, 8581, 8597, 8599, 8609, 8623, 8627, 8629, 8641, 8647, 8663, 8669, 8677, 8681, 8689, 8693, 8699, 8707, 8713, 8719, 8731, 8737, 8741, 8747, 8753, 8761, 8779, 8783, 8803, 8807, 8819, 8821, 8831, 8837, 8839, 8849, 8861, 8863, 8867, 8887, 8893, 8923, 8929, 8933, 8941, 8951, 8963, 8969, 8971, 8999, 9001, 9007, 9011, 9013, 9029, 9041, 9043, 9049, 9059, 9067, 9091, 9103, 9109, 9127, 9133, 9137, 9151, 9157, 9161, 9173, 9181, 9187, 9199, 9203, 9209, 9221, 9227, 9239, 9241, 9257, 9277, 9281, 9283, 9293, 9311, 9319, 9323, 9337, 9341, 9343, 9349, 9371, 9377, 9391, 9397, 9403, 9413, 9419, 9421, 9431, 9433, 9437, 9439, 9461, 9463, 9467, 9473, 9479, 9491, 9497, 9511, 9521, 9533, 9539, 9547, 9551, 9587, 9601, 9613, 9619, 9623, 9629, 9631, 9643, 9649, 9661, 9677, 9679, 9689, 9697, 9719, 9721, 9733, 9739, 9743, 9749, 9767, 9769, 9781, 9787, 9791, 9803, 9811, 9817, 9829, 9833, 9839, 9851, 9857, 9859, 9871, 9883, 9887, 9901, 9907, 9923, 9929, 9931, 9941, 9949, 9967, 9973, 10007, 10009, 10037, 10039, 10061, 10067, 10069, 10079, 10091, 10093, 10099, 10103, 10111, 10133, 10139, 10141, 10151, 10159, 10163, 10169, 10177, 10181, 10193, 10211, 10223, 10243, 10247, 10253, 10259, 10267, 10271, 10273, 10289, 10301, 10303, 10313, 10321, 10331, 10333, 10337, 10343, 10357, 10369, 10391, 10399, 10427, 10429, 10433, 10453, 10457, 10459, 10463, 10477, 10487, 10499, 10501, 10513, 10529, 10531, 10559, 10567, 10589, 10597, 10601, 10607, 10613, 10627, 10631, 10639, 10651, 10657, 10663, 10667, 10687, 10691, 10709, 10711, 10723, 10729, 10733, 10739, 10753, 10771, 10781, 10789, 10799, 10831, 10837, 10847, 10853, 10859, 10861, 10867, 10883, 10889, 10891, 10903, 10909, 10937, 10939, 10949, 10957, 10973, 10979, 10987, 10993, 11003, 11027, 11047, 11057, 11059, 11069, 11071, 11083, 11087, 11093, 11113, 11117, 11119, 11131, 11149, 11159, 11161, 11171, 11173, 11177, 11197, 11213, 11239, 11243, 11251, 11257, 11261, 11273, 11279, 11287, 11299, 11311, 11317, 11321, 11329, 11351, 11353, 11369, 11383, 11393, 11399, 11411, 11423, 11437, 11443, 11447, 11467, 11471, 11483, 11489, 11491, 11497, 11503, 11519, 11527, 11549, 11551, 11579, 11587, 11593, 11597, 11617, 11621, 11633, 11657, 11677, 11681, 11689, 11699, 11701, 11717, 11719, 11731, 11743, 11777, 11779, 11783, 11789, 11801, 11807, 11813, 11821, 11827, 11831, 11833, 11839, 11863, 11867, 11887, 11897, 11903, 11909, 11923, 11927, 11933, 11939, 11941, 11953, 11959, 11969, 11971, 11981, 11987, 12007, 12011, 12037, 12041, 12043, 12049, 12071, 12073, 12097, 12101, 12107, 12109, 12113, 12119, 12143, 12149, 12157, 12161, 12163, 12197, 12203, 12211, 12227, 12239, 12241, 12251, 12253, 12263, 12269, 12277, 12281, 12289, 12301, 12323, 12329, 12343, 12347, 12373, 12377, 12379, 12391, 12401, 12409, 12413, 12421, 12433, 12437, 12451, 12457, 12473, 12479, 12487, 12491, 12497, 12503, 12511, 12517, 12527, 12539, 12541, 12547, 12553, 12569, 12577, 12583, 12589, 12601, 12611, 12613, 12619, 12637, 12641, 12647, 12653, 12659, 12671, 12689, 12697, 12703, 12713, 12721, 12739, 12743, 12757, 12763, 12781, 12791, 12799, 12809, 12821, 12823, 12829, 12841, 12853, 12889, 12893, 12899, 12907, 12911, 12917, 12919, 12923, 12941, 12953, 12959, 12967, 12973, 12979, 12983, 13001, 13003, 13007, 13009, 13033, 13037, 13043, 13049, 13063, 13093, 13099, 13103, 13109, 13121, 13127, 13147, 13151, 13159, 13163, 13171, 13177, 13183, 13187, 13217, 13219, 13229, 13241, 13249, 13259, 13267, 13291, 13297, 13309, 13313, 13327, 13331, 13337, 13339, 13367, 13381, 13397, 13399, 13411, 13417, 13421, 13441, 13451, 13457, 13463, 13469, 13477, 13487, 13499, 13513, 13523, 13537, 13553, 13567, 13577, 13591, 13597, 13613, 13619, 13627, 13633, 13649, 13669, 13679, 13681, 13687, 13691, 13693, 13697, 13709, 13711, 13721, 13723, 13729, 13751, 13757, 13759, 13763, 13781, 13789, 13799, 13807, 13829, 13831, 13841, 13859, 13873, 13877, 13879, 13883, 13901, 13903, 13907, 13913, 13921, 13931, 13933, 13963, 13967, 13997, 13999, 14009, 14011, 14029, 14033, 14051, 14057, 14071, 14081, 14083, 14087, 14107, 14143, 14149, 14153, 14159, 14173, 14177, 14197, 14207, 14221, 14243, 14249, 14251, 14281, 14293, 14303, 14321, 14323, 14327, 14341, 14347, 14369, 14387, 14389, 14401, 14407, 14411, 14419, 14423, 14431, 14437, 14447, 14449, 14461, 14479, 14489, 14503, 14519, 14533, 14537, 14543, 14549, 14551, 14557, 14561, 14563, 14591, 14593, 14621, 14627, 14629, 14633, 14639, 14653, 14657, 14669, 14683, 14699, 14713, 14717, 14723, 14731, 14737, 14741, 14747, 14753, 14759, 14767, 14771, 14779, 14783, 14797, 14813, 14821, 14827, 14831, 14843, 14851, 14867, 14869, 14879, 14887, 14891, 14897, 14923, 14929, 14939, 14947, 14951, 14957, 14969, 14983, 15013, 15017, 15031, 15053, 15061, 15073, 15077, 15083, 15091, 15101, 15107, 15121, 15131, 15137, 15139, 15149, 15161, 15173, 15187, 15193, 15199, 15217, 15227, 15233, 15241, 15259, 15263, 15269, 15271, 15277, 15287, 15289, 15299, 15307, 15313, 15319, 15329, 15331, 15349, 15359, 15361, 15373, 15377, 15383, 15391, 15401, 15413, 15427, 15439, 15443, 15451, 15461, 15467, 15473, 15493, 15497, 15511, 15527, 15541, 15551, 15559, 15569, 15581, 15583, 15601, 15607, 15619, 15629, 15641, 15643, 15647, 15649, 15661, 15667, 15671, 15679, 15683, 15727, 15731, 15733, 15737, 15739, 15749, 15761, 15767, 15773, 15787, 15791, 15797, 15803, 15809, 15817, 15823, 15859, 15877, 15881, 15887, 15889, 15901, 15907, 15913, 15919, 15923, 15937, 15959, 15971, 15973, 15991, 16001, 16007, 16033, 16057, 16061, 16063, 16067, 16069, 16073, 16087, 16091, 16097, 16103, 16111, 16127, 16139, 16141, 16183, 16187, 16189, 16193, 16217, 16223, 16229, 16231, 16249, 16253, 16267, 16273, 16301, 16319, 16333, 16339, 16349, 16361, 16363, 16369, 16381, 16411, 16417, 16421, 16427, 16433, 16447, 16451, 16453, 16477, 16481, 16487, 16493, 16519, 16529, 16547, 16553, 16561, 16567, 16573, 16603, 16607, 16619, 16631, 16633, 16649, 16651, 16657, 16661, 16673, 16691, 16693, 16699, 16703, 16729, 16741, 16747, 16759, 16763, 16787, 16811, 16823, 16829, 16831, 16843, 16871, 16879, 16883, 16889, 16901, 16903, 16921, 16927, 16931, 16937, 16943, 16963, 16979, 16981, 16987, 16993, 17011, 17021, 17027, 17029, 17033, 17041, 17047, 17053, 17077, 17093, 17099, 17107, 17117, 17123, 17137, 17159, 17167, 17183, 17189, 17191, 17203, 17207, 17209, 17231, 17239, 17257, 17291, 17293, 17299, 17317, 17321, 17327, 17333, 17341, 17351, 17359, 17377, 17383, 17387, 17389, 17393, 17401, 17417, 17419, 17431, 17443, 17449, 17467, 17471, 17477, 17483, 17489, 17491, 17497, 17509, 17519, 17539, 17551, 17569, 17573, 17579, 17581, 17597, 17599, 17609, 17623, 17627, 17657, 17659, 17669, 17681, 17683, 17707, 17713, 17729, 17737, 17747, 17749, 17761, 17783, 17789, 17791, 17807, 17827, 17837, 17839, 17851, 17863, 17881, 17891, 17903, 17909, 17911, 17921, 17923, 17929, 17939, 17957, 17959, 17971, 17977, 17981, 17987, 17989, 18013, 18041, 18043, 18047, 18049, 18059, 18061, 18077, 18089, 18097, 18119, 18121, 18127, 18131, 18133, 18143, 18149, 18169, 18181, 18191, 18199, 18211, 18217, 18223, 18229, 18233, 18251, 18253, 18257, 18269, 18287, 18289, 18301, 18307, 18311, 18313, 18329, 18341, 18353, 18367, 18371, 18379, 18397, 18401, 18413, 18427, 18433, 18439, 18443, 18451, 18457, 18461, 18481, 18493, 18503, 18517, 18521, 18523, 18539, 18541, 18553, 18583, 18587, 18593, 18617, 18637, 18661, 18671, 18679, 18691, 18701, 18713, 18719, 18731, 18743, 18749, 18757, 18773, 18787, 18793, 18797, 18803, 18839, 18859, 18869, 18899, 18911, 18913, 18917, 18919, 18947, 18959, 18973, 18979, 19001, 19009, 19013, 19031, 19037, 19051, 19069, 19073, 19079, 19081, 19087, 19121, 19139, 19141, 19157, 19163, 19181, 19183, 19207, 19211, 19213, 19219, 19231, 19237, 19249, 19259, 19267, 19273, 19289, 19301, 19309, 19319, 19333, 19373, 19379, 19381, 19387, 19391, 19403, 19417, 19421, 19423, 19427, 19429, 19433, 19441, 19447, 19457, 19463, 19469, 19471, 19477, 19483, 19489, 19501, 19507, 19531, 19541, 19543, 19553, 19559, 19571, 19577, 19583, 19597, 19603, 19609, 19661, 19681, 19687, 19697, 19699, 19709, 19717, 19727, 19739, 19751, 19753, 19759, 19763, 19777, 19793, 19801, 19813, 19819, 19841, 19843, 19853, 19861, 19867, 19889, 19891, 19913, 19919, 19927, 19937, 19949, 19961, 19963, 19973, 19979, 19991, 19993, 19997, 20011, 20021, 20023, 20029, 20047, 20051, 20063, 20071, 20089, 20101, 20107, 20113, 20117, 20123, 20129, 20143, 20147, 20149, 20161, 20173, 20177, 20183, 20201, 20219, 20231, 20233, 20249, 20261, 20269, 20287, 20297, 20323, 20327, 20333, 20341, 20347, 20353, 20357, 20359, 20369, 20389, 20393, 20399, 20407, 20411, 20431, 20441, 20443, 20477, 20479, 20483, 20507, 20509, 20521, 20533, 20543, 20549, 20551, 20563, 20593, 20599, 20611, 20627, 20639, 20641, 20663, 20681, 20693, 20707, 20717, 20719, 20731, 20743, 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44497, 44501, 44507, 44519, 44531, 44533, 44537, 44543, 44549, 44563, 44579, 44587, 44617, 44621, 44623, 44633, 44641, 44647, 44651, 44657, 44683, 44687, 44699, 44701, 44711, 44729, 44741, 44753, 44771, 44773, 44777, 44789, 44797, 44809, 44819, 44839, 44843, 44851, 44867, 44879, 44887, 44893, 44909, 44917, 44927, 44939, 44953, 44959, 44963, 44971, 44983, 44987, 45007, 45013, 45053, 45061, 45077, 45083, 45119, 45121, 45127, 45131, 45137, 45139, 45161, 45179, 45181, 45191, 45197, 45233, 45247, 45259, 45263, 45281, 45289, 45293, 45307, 45317, 45319, 45329, 45337, 45341, 45343, 45361, 45377, 45389, 45403, 45413, 45427, 45433, 45439, 45481, 45491, 45497, 45503, 45523, 45533, 45541, 45553, 45557, 45569, 45587, 45589, 45599, 45613, 45631, 45641, 45659, 45667, 45673, 45677, 45691, 45697, 45707, 45737, 45751, 45757, 45763, 45767, 45779, 45817, 45821, 45823, 45827, 45833, 45841, 45853, 45863, 45869, 45887, 45893, 45943, 45949, 45953, 45959, 45971, 45979, 45989, 46021, 46027, 46049, 46051, 46061, 46073, 46091, 46093, 46099, 46103, 46133, 46141, 46147, 46153, 46171, 46181, 46183, 46187, 46199, 46219, 46229, 46237, 46261, 46271, 46273, 46279, 46301, 46307, 46309, 46327, 46337, 46349, 46351, 46381, 46399, 46411, 46439, 46441, 46447, 46451, 46457, 46471, 46477, 46489, 46499, 46507, 46511, 46523, 46549, 46559, 46567, 46573, 46589, 46591, 46601, 46619, 46633, 46639, 46643, 46649, 46663, 46679, 46681, 46687, 46691, 46703, 46723, 46727, 46747, 46751, 46757, 46769, 46771, 46807, 46811, 46817, 46819, 46829, 46831, 46853, 46861, 46867, 46877, 46889, 46901, 46919, 46933, 46957, 46993, 46997, 47017, 47041, 47051, 47057, 47059, 47087, 47093, 47111, 47119, 47123, 47129, 47137, 47143, 47147, 47149, 47161, 47189, 47207, 47221, 47237, 47251, 47269, 47279, 47287, 47293, 47297, 47303, 47309, 47317, 47339, 47351, 47353, 47363, 47381, 47387, 47389, 47407, 47417, 47419, 47431, 47441, 47459, 47491, 47497, 47501, 47507, 47513, 47521, 47527, 47533, 47543, 47563, 47569, 47581, 47591, 47599, 47609, 47623, 47629, 47639, 47653, 47657, 47659, 47681, 47699, 47701, 47711, 47713, 47717, 47737, 47741, 47743, 47777, 47779, 47791, 47797, 47807, 47809, 47819, 47837, 47843, 47857, 47869, 47881, 47903, 47911, 47917, 47933, 47939, 47947, 47951, 47963, 47969, 47977, 47981, 48017, 48023, 48029, 48049, 48073, 48079, 48091, 48109, 48119, 48121, 48131, 48157, 48163, 48179, 48187, 48193, 48197, 48221, 48239, 48247, 48259, 48271, 48281, 48299, 48311, 48313, 48337, 48341, 48353, 48371, 48383, 48397, 48407, 48409, 48413, 48437, 48449, 48463, 48473, 48479, 48481, 48487, 48491, 48497, 48523, 48527, 48533, 48539, 48541, 48563, 48571, 48589, 48593, 48611, 48619, 48623, 48647, 48649, 48661, 48673, 48677, 48679, 48731, 48733, 48751, 48757, 48761, 48767, 48779, 48781, 48787, 48799, 48809, 48817, 48821, 48823, 48847, 48857, 48859, 48869, 48871, 48883, 48889, 48907, 48947, 48953, 48973, 48989, 48991, 49003, 49009, 49019, 49031, 49033, 49037, 49043, 49057, 49069, 49081, 49103, 49109, 49117, 49121, 49123, 49139, 49157, 49169, 49171, 49177, 49193, 49199, 49201, 49207, 49211, 49223, 49253, 49261, 49277, 49279, 49297, 49307, 49331, 49333, 49339, 49363, 49367, 49369, 49391, 49393, 49409, 49411, 49417, 49429, 49433, 49451, 49459, 49463, 49477, 49481, 49499, 49523, 49529, 49531, 49537, 49547, 49549, 49559, 49597, 49603, 49613, 49627, 49633, 49639, 49663, 49667, 49669, 49681, 49697, 49711, 49727, 49739, 49741, 49747, 49757, 49783, 49787, 49789, 49801, 49807, 49811, 49823, 49831, 49843, 49853, 49871, 49877, 49891, 49919, 49921, 49927, 49937, 49939, 49943, 49957, 49991, 49993, 49999, 50021, 50023, 50033, 50047, 50051, 50053, 50069, 50077, 50087, 50093, 50101, 50111, 50119, 50123, 50129, 50131, 50147, 50153, 50159, 50177, 50207, 50221, 50227, 50231, 50261, 50263, 50273, 50287, 50291, 50311, 50321, 50329, 50333, 50341, 50359, 50363, 50377, 50383, 50387, 50411, 50417, 50423, 50441, 50459, 50461, 50497, 50503, 50513, 50527, 50539, 50543, 50549, 50551, 50581, 50587, 50591, 50593, 50599, 50627, 50647, 50651, 50671, 50683, 50707, 50723, 50741, 50753, 50767, 50773, 50777, 50789, 50821, 50833, 50839, 50849, 50857, 50867, 50873, 50891, 50893, 50909, 50923, 50929, 50951, 50957, 50969, 50971, 50989, 50993, 51001, 51031, 51043, 51047, 51059, 51061, 51071, 51109, 51131, 51133, 51137, 51151, 51157, 51169, 51193, 51197, 51199, 51203, 51217, 51229, 51239, 51241, 51257, 51263, 51283, 51287, 51307, 51329, 51341, 51343, 51347, 51349, 51361, 51383, 51407, 51413, 51419, 51421, 51427, 51431, 51437, 51439, 51449, 51461, 51473, 51479, 51481, 51487, 51503, 51511, 51517, 51521, 51539, 51551, 51563, 51577, 51581, 51593, 51599, 51607, 51613, 51631, 51637, 51647, 51659, 51673, 51679, 51683, 51691, 51713, 51719, 51721, 51749, 51767, 51769, 51787, 51797, 51803, 51817, 51827, 51829, 51839, 51853, 51859, 51869, 51871, 51893, 51899, 51907, 51913, 51929, 51941, 51949, 51971, 51973, 51977, 51991, 52009, 52021, 52027, 52051, 52057, 52067, 52069, 52081, 52103, 52121, 52127, 52147, 52153, 52163, 52177, 52181, 52183, 52189, 52201, 52223, 52237, 52249, 52253, 52259, 52267, 52289, 52291, 52301, 52313, 52321, 52361, 52363, 52369, 52379, 52387, 52391, 52433, 52453, 52457, 52489, 52501, 52511, 52517, 52529, 52541, 52543, 52553, 52561, 52567, 52571, 52579, 52583, 52609, 52627, 52631, 52639, 52667, 52673, 52691, 52697, 52709, 52711, 52721, 52727, 52733, 52747, 52757, 52769, 52783, 52807, 52813, 52817, 52837, 52859, 52861, 52879, 52883, 52889, 52901, 52903, 52919, 52937, 52951, 52957, 52963, 52967, 52973, 52981, 52999, 53003, 53017, 53047, 53051, 53069, 53077, 53087, 53089, 53093, 53101, 53113, 53117, 53129, 53147, 53149, 53161, 53171, 53173, 53189, 53197, 53201, 53231, 53233, 53239, 53267, 53269, 53279, 53281, 53299, 53309, 53323, 53327, 53353, 53359, 53377, 53381, 53401, 53407, 53411, 53419, 53437, 53441, 53453, 53479, 53503, 53507, 53527, 53549, 53551, 53569, 53591, 53593, 53597, 53609, 53611, 53617, 53623, 53629, 53633, 53639, 53653, 53657, 53681, 53693, 53699, 53717, 53719, 53731, 53759, 53773, 53777, 53783, 53791, 53813, 53819, 53831, 53849, 53857, 53861, 53881, 53887, 53891, 53897, 53899, 53917, 53923, 53927, 53939, 53951, 53959, 53987, 53993, 54001, 54011, 54013, 54037, 54049, 54059, 54083, 54091, 54101, 54121, 54133, 54139, 54151, 54163, 54167, 54181, 54193, 54217, 54251, 54269, 54277, 54287, 54293, 54311, 54319, 54323, 54331, 54347, 54361, 54367, 54371, 54377, 54401, 54403, 54409, 54413, 54419, 54421, 54437, 54443, 54449, 54469, 54493, 54497, 54499, 54503, 54517, 54521, 54539, 54541, 54547, 54559, 54563, 54577, 54581, 54583, 54601, 54617, 54623, 54629, 54631, 54647, 54667, 54673, 54679, 54709, 54713, 54721, 54727, 54751, 54767, 54773, 54779, 54787, 54799, 54829, 54833, 54851, 54869, 54877, 54881, 54907, 54917, 54919, 54941, 54949, 54959, 54973, 54979, 54983, 55001, 55009, 55021, 55049, 55051, 55057, 55061, 55073, 55079, 55103, 55109, 55117, 55127, 55147, 55163, 55171, 55201, 55207, 55213, 55217, 55219, 55229, 55243, 55249, 55259, 55291, 55313, 55331, 55333, 55337, 55339, 55343, 55351, 55373, 55381, 55399, 55411, 55439, 55441, 55457, 55469, 55487, 55501, 55511, 55529, 55541, 55547, 55579, 55589, 55603, 55609, 55619, 55621, 55631, 55633, 55639, 55661, 55663, 55667, 55673, 55681, 55691, 55697, 55711, 55717, 55721, 55733, 55763, 55787, 55793, 55799, 55807, 55813, 55817, 55819, 55823, 55829, 55837, 55843, 55849, 55871, 55889, 55897, 55901, 55903, 55921, 55927, 55931, 55933, 55949, 55967, 55987, 55997, 56003, 56009, 56039, 56041, 56053, 56081, 56087, 56093, 56099, 56101, 56113, 56123, 56131, 56149, 56167, 56171, 56179, 56197, 56207, 56209, 56237, 56239, 56249, 56263, 56267, 56269, 56299, 56311, 56333, 56359, 56369, 56377, 56383, 56393, 56401, 56417, 56431, 56437, 56443, 56453, 56467, 56473, 56477, 56479, 56489, 56501, 56503, 56509, 56519, 56527, 56531, 56533, 56543, 56569, 56591, 56597, 56599, 56611, 56629, 56633, 56659, 56663, 56671, 56681, 56687, 56701, 56711, 56713, 56731, 56737, 56747, 56767, 56773, 56779, 56783, 56807, 56809, 56813, 56821, 56827, 56843, 56857, 56873, 56891, 56893, 56897, 56909, 56911, 56921, 56923, 56929, 56941, 56951, 56957, 56963, 56983, 56989, 56993, 56999, 57037, 57041, 57047, 57059, 57073, 57077, 57089, 57097, 57107, 57119, 57131, 57139, 57143, 57149, 57163, 57173, 57179, 57191, 57193, 57203, 57221, 57223, 57241, 57251, 57259, 57269, 57271, 57283, 57287, 57301, 57329, 57331, 57347, 57349, 57367, 57373, 57383, 57389, 57397, 57413, 57427, 57457, 57467, 57487, 57493, 57503, 57527, 57529, 57557, 57559, 57571, 57587, 57593, 57601, 57637, 57641, 57649, 57653, 57667, 57679, 57689, 57697, 57709, 57713, 57719, 57727, 57731, 57737, 57751, 57773, 57781, 57787, 57791, 57793, 57803, 57809, 57829, 57839, 57847, 57853, 57859, 57881, 57899, 57901, 57917, 57923, 57943, 57947, 57973, 57977, 57991, 58013, 58027, 58031, 58043, 58049, 58057, 58061, 58067, 58073, 58099, 58109, 58111, 58129, 58147, 58151, 58153, 58169, 58171, 58189, 58193, 58199, 58207, 58211, 58217, 58229, 58231, 58237, 58243, 58271, 58309, 58313, 58321, 58337, 58363, 58367, 58369, 58379, 58391, 58393, 58403, 58411, 58417, 58427, 58439, 58441, 58451, 58453, 58477, 58481, 58511, 58537, 58543, 58549, 58567, 58573, 58579, 58601, 58603, 58613, 58631, 58657, 58661, 58679, 58687, 58693, 58699, 58711, 58727, 58733, 58741, 58757, 58763, 58771, 58787, 58789, 58831, 58889, 58897, 58901, 58907, 58909, 58913, 58921, 58937, 58943, 58963, 58967, 58979, 58991, 58997, 59009, 59011, 59021, 59023, 59029, 59051, 59053, 59063, 59069, 59077, 59083, 59093, 59107, 59113, 59119, 59123, 59141, 59149, 59159, 59167, 59183, 59197, 59207, 59209, 59219, 59221, 59233, 59239, 59243, 59263, 59273, 59281, 59333, 59341, 59351, 59357, 59359, 59369, 59377, 59387, 59393, 59399, 59407, 59417, 59419, 59441, 59443, 59447, 59453, 59467, 59471, 59473, 59497, 59509, 59513, 59539, 59557, 59561, 59567, 59581, 59611, 59617, 59621, 59627, 59629, 59651, 59659, 59663, 59669, 59671, 59693, 59699, 59707, 59723, 59729, 59743, 59747, 59753, 59771, 59779, 59791, 59797, 59809, 59833, 59863, 59879, 59887, 59921, 59929, 59951, 59957, 59971, 59981, 59999}; int num_of_element = 6057; int *arr, n; typedef struct { int first; int second; } pa; vector<pa> pairs; void generate(vector<int> numbers) { int siz = numbers.size(); int i; if (numbers.size() % 2 != 0) { numbers.erase(numbers.begin() + 1); } for (i = 0; (i + 1) < siz;) { arr[numbers[i]] = 1; arr[numbers[i + 1]] = 1; pa t; t.first = numbers[i]; t.second = numbers[i + 1]; pairs.push_back(t); i = i + 2; } numbers.clear(); } void generatePairs() { vector<int> numbers; for (int pos = 1; pos <= 6056; pos++) { int prime = primes[pos]; if ((2 * prime) > n) return; for (int i = 1; (i * prime) <= n; i++) { if (arr[i * prime] == 0) numbers.push_back(i * prime); } generate(numbers); numbers.clear(); } } void last() { vector<int> numbers; for (int i = 2; i <= n; i++) { if ((i % 2 == 0) && (arr[i] == 0)) { numbers.push_back(i); } } int siz = numbers.size(); int i; for (i = 0; (i + 1) < siz;) { arr[numbers[i]] = 1; arr[numbers[i + 1]] = 1; pa t; t.first = numbers[i]; t.second = numbers[i + 1]; pairs.push_back(t); i = i + 2; } numbers.clear(); } int main() { scanf( %d , &n); arr = (int *)calloc(n + 10, sizeof(int)); if (n <= 3) { printf( 0 ); return 0; } arr = (int *)calloc(n + 10, sizeof(int)); generatePairs(); last(); printf( %d n , pairs.size()); int siz = pairs.size(); for (int i = 0; i < siz; i++) { printf( %d %d n , pairs[i].first, pairs[i].second); } } |
#include <bits/stdc++.h> using namespace std; int main() { int xa[300005] = {0}; for (int i = 1; i <= 300000; i++) { xa[i] = (xa[i - 1] ^ i); } int t; cin >> t; while (t--) { long long a, b; cin >> a >> b; long long x = xa[a - 1]; if (x == b) { cout << a << endl; } else { if ((x ^ b) == a) { cout << a + 2 << endl; } else { cout << a + 1 << endl; } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instatiation of DC RAM blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_dc_ram.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_ram(
// Reset and clock
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of RAM block
//
or1200_spram_32_bw #
(
.aw(`OR1200_DCINDX),
.dw(dw)
)
dc_ram
(
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.ce(en),
.we(we),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule // or1200_dc_ram
|
#include <bits/stdc++.h> using namespace std; int main() { int n, b; cin >> n >> b; if (n - b <= b) { cout << -1; } else { cout << b * n << n ; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= b + i; j++) { cout << i << ; if (j % n == 0) { cout << j << n ; } else { cout << j % n << n ; } } } } } |
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____11.900______0.000______50.0______394.277____301.475
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "system_clk_wiz_0_0,clk_wiz_v5_3_3_0,{component_name=system_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module system_clk_wiz_0_0
(
// Clock out ports
output clk_out1,
// Clock in ports
input clk_in1
);
system_clk_wiz_0_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string s[500000]; const int mod = 1000003; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; int result = 1; for (int i = 0; i < n; i++) { bool ok1 = false, ok2 = false; for (int j = 0; j < m; j++) { if (j % 2 == 0 && (s[i][j] == 1 || s[i][j] == 2 )) ok1 = true; if (j % 2 == 1 && (s[i][j] == 3 || s[i][j] == 4 )) ok1 = true; if (j % 2 == 1 && (s[i][j] == 1 || s[i][j] == 2 )) ok2 = true; if (j % 2 == 0 && (s[i][j] == 3 || s[i][j] == 4 )) ok2 = true; } if (ok1 && ok2) result *= 0; if (!ok1 && !ok2) result = (result * 2) % mod; } for (int j = 0; j < m; j++) { bool ok1 = false, ok2 = false; for (int i = 0; i < n; i++) { if (i % 2 == 0 && (s[i][j] == 4 || s[i][j] == 1 )) ok1 = true; if (i % 2 == 1 && (s[i][j] == 2 || s[i][j] == 3 )) ok1 = true; if (i % 2 == 1 && (s[i][j] == 4 || s[i][j] == 1 )) ok2 = true; if (i % 2 == 0 && (s[i][j] == 2 || s[i][j] == 3 )) ok2 = true; } if (ok1 && ok2) result *= 0; if (!ok1 && !ok2) result = (result * 2) % mod; } cout << result; } |
#include <bits/stdc++.h> using namespace std; const int MX = (1 << 19); string str; vector<pair<int, char> > sorted; int cnt[MX], done[MX], K; int main() { cin >> str >> K; for (int j = 0; j < str.size(); j++) cnt[str[j] - a ]++; for (int j = 0; j < 26; j++) { sorted.push_back(make_pair(cnt[j], j + a )); } sort(sorted.begin(), sorted.end()); int ans = 26; for (auto pp : sorted) { if (pp.first > K) break; K -= pp.first; done[pp.second] = 1; --ans; } cout << ans << endl; for (auto ch : str) if (!done[ch]) cout << ch; cout << endl; } |
#include <bits/stdc++.h> using namespace std; string smallest(string s) { if (s.length() % 2 == 1) return s; string s1 = smallest(s.substr(0, s.length() / 2)); string s2 = smallest(s.substr(s.length() / 2)); if (s1 < s2) return s1 + s2; else return s2 + s1; } bool solve(string s1, string s2) { for (int i = 0; i < s1.length(); i++) if (s1[i] != s2[i]) return 0; return 1; } int main() { string s1, s2; cin >> s1 >> s2; s1 = smallest(s1); s2 = smallest(s2); if (solve(s1, s2)) cout << YES n ; else cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); srand(time(NULL)); int t; cin >> t; while (t--) { int n; cin >> n; unordered_map<string, int> codes; vector<string> v(n); for (int i = 0; i < n; i++) { string x; cin >> x; v[i] = x; codes[x]++; } int ans = 0; vector<string> anss; for (int i = 0; i < n; i++) { if (codes[v[i]] > 1) { ans++; string x = v[i]; while (codes[x] >= 1) { x = v[i]; int pos = rand() % 4; char digit = (char)( 0 + (rand() % 10)); x[pos] = digit; } codes[x] = 1; codes[v[i]]--; anss.push_back(x); } else anss.push_back(v[i]); } cout << ans << n ; for (auto a : anss) cout << a << n ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.04.2017 02:00:33
// Design Name:
// Module Name: dragster_spi_adapter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dragster_spi_adapter #
(
EXTENDED_CLOCKS = 3,
TRANSACTION_DEPTH = 128,
DATA_WIDTH = 16
)
(
input wire clk,
input wire reset,
input wire internal_mosi,
output wire internal_miso,
input wire internal_sck,
input wire[1:0] internal_ss,
output reg external_mosi,
input wire external_miso,
output wire external_sck,
output reg[1:0] external_ss
);
/* Ìû íå ìîæåì äåëàòü ñåëåêòû íà ïàìÿòè, ïîýòîìó äëÿ ýòîãî äåëà áóäåò âûäåëåí îòäåëüíûé ðåãèñòð. */
reg[DATA_WIDTH - 1 : 0] transactions[TRANSACTION_DEPTH - 1 : 0];
/* Ïîëó÷àòåëè. */
reg[1:0] slaves[TRANSACTION_DEPTH - 1 : 0];
/* Ðåãèñòð äëÿ àíàëèçà äàííûõ. Çäåñü ìû äåëàåì ñåëåêò è óòî÷íÿåì òèï îïåðàöèè, ïðîâåðÿÿ àäðåñíûé áàéò íà íàëè÷èå çíà÷åíèÿ 15. */
//reg[15:0] transaction;
/* Ñ÷åò÷èêè áèò */
reg[3:0] bit_counter;
reg[3:0] internal_bit_count;
reg[7:0] external_clock_count;
reg generate_external_clock;
reg clock_enable;
/* Êîëè÷åñòâî áóôåðèçèðîâàííûõ òðàíçàêöèé. */
reg[7:0] buffered_transaction_count;
/* Êîëè÷åñòâî òðàíçàêöèé îòïðàâëåííûõ â ñåíñîð. */
reg[7:0] forwarded_transaction_count;
/* Èíäåêñ òðàíçàêöèè áóôåðèçèðóåìîé â äàííûé ìîìåíò. Îòñþäà ìû ÷èòàòü íå áóäåì. */
reg[7:0] transaction_about_to_be_buffered;
integer counter;
assign external_sck = clock_enable ? clk : 0;
/* always ïî êëîêó èñòî÷íèêà */
always @ (negedge clk)
begin
if(!reset)
begin
forwarded_transaction_count <= 0;
bit_counter <= 0;
external_mosi <= 0;
external_ss <= 3;
clock_enable <= 0;
generate_external_clock <= 0;
external_clock_count <= 0;
end
else
begin
if(buffered_transaction_count > 0 && forwarded_transaction_count < buffered_transaction_count)
begin
clock_enable <= 1;
if(clock_enable && ~generate_external_clock)
begin
bit_counter <= bit_counter + 1;
external_ss <= slaves[forwarded_transaction_count];
external_mosi <= transactions[forwarded_transaction_count][bit_counter];
if(bit_counter == DATA_WIDTH - 1)
generate_external_clock <= 1;
end
else
begin
external_clock_count <= external_clock_count + 1;
if(EXTENDED_CLOCKS == 0 || external_clock_count == EXTENDED_CLOCKS)
begin
external_clock_count <= 0;
generate_external_clock <= 0;
clock_enable <= 0;
external_ss <= 3;
external_mosi <= 0;
if(forwarded_transaction_count == TRANSACTION_DEPTH - 1)
forwarded_transaction_count <= 0;
else forwarded_transaction_count <= forwarded_transaction_count + 1;
bit_counter <= 0;
end
end
end
end
end
/* Èíäåêñ áèòà. */
//reg[5:0] bit_count;
/* Áóôåð â êîòîðûé ìû ñêëàäûâàåì áèòû ïåðåä ñîõðàíåíèåì èõ â ïàìÿòü. */
reg[15:0] internal_transaction_buffer;
/* always ïî êëîêó AXI Quad SPI */
always @ (negedge reset or negedge internal_sck)
begin
if(!reset)
begin
for(counter = 0; counter < TRANSACTION_DEPTH; counter = counter + 1)
begin
slaves[counter] = 3;
transactions[counter] = 0;
end
buffered_transaction_count = 0;
internal_bit_count = 0;
end
else
begin
internal_bit_count = internal_bit_count + 1;
internal_transaction_buffer[internal_bit_count - 1] = internal_mosi;
if(internal_bit_count == 0) //DATA_WIDTH - 1)
begin
internal_transaction_buffer[15] = internal_mosi;
transactions[buffered_transaction_count] = internal_transaction_buffer;
slaves[buffered_transaction_count] = internal_ss;
if(buffered_transaction_count == TRANSACTION_DEPTH - 1)
buffered_transaction_count = 0;
else buffered_transaction_count = buffered_transaction_count + 1;
internal_bit_count = 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int dcmp(double a, double b) { return fabs(a - b) < (1e-9) ? 0 : a < b ? -1 : +1; } const int N = 1000 + 9; int pr[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31}; int ans[N]; vector<vector<int> > g; int x[N]; bitset<N> del; int main() { int tc; scanf( %d , &tc); while (tc--) { int n; scanf( %d , &n); for (auto i = 0; i < n; ++i) scanf( %d , x + i); for (int cnt = 0, p = 0; cnt != n; p++) { g.emplace_back(vector<int>()); for (auto i = 0; i < n; ++i) if (!del[i] && x[i] % pr[p] == 0) del[i] = 1, g.back().emplace_back(i), cnt++; if (g.back().empty()) g.pop_back(); } for (auto i = 0; i < ((int)((g).size())); ++i) for (auto j = 0; j < ((int)((g[i]).size())); ++j) ans[g[i][j]] = i; printf( %d n , ((int)((g).size()))); for (auto i = 0; i < n; ++i) printf( %d , ans[i] + 1); puts( ); del.reset(); g.clear(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int INF = (1LL << 60) - 1; const long long int MAX = 1000000001; const long long int mod = 1000000007; long long int s[1000001] = {0}; long long int f[1000001] = {0}; long long int po[1000001] = {0}; long long int fast_exp(long long int base, long long int exp, long long int m) { long long int res = 1; while (exp > 0) { if (exp % 2 == 1) { res = (res * base) % m; } base = (base * base) % m; exp /= 2; } return res % m; } long long int gcd(int a, int b); long long int power(long long int x, long long int y, long long int m); long long int modInverse(long long int a, long long int m) { return power(a, m - 2, m); } long long int power(long long int x, long long int y, long long int m) { if (y == 0) return 1; long long int p = power(x, y / 2, m) % m; p = (p * p) % m; return (y % 2 == 0) ? p : (x * p) % m; } long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } int main() { ios ::sync_with_stdio(false); cin.tie(0); cout.tie(0); int a[6] = {0}, sum = 0; int freq[101] = {0}; for (int i = 1; i <= 5; i++) { cin >> a[i]; freq[a[i]]++; sum += a[i]; } int temp1 = 0, temp2 = 0; for (int i = 1; i <= 100; i++) { if (freq[i] == 2) temp1 = freq[i] * i; else if (freq[i] >= 3) temp2 = 3 * i; } cout << min(sum - temp1, sum - temp2) << n ; return 0; } |
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* vending machine
*/
// Import the modules that will be tested for in this testbench
`include "ee577bHw2q1.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q1.f +gui
module tbfsm();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the couunter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire disp_Q,disp_D,disp_N,disp_P,done;
// Declare "reg" signals: inputs to the DUT
reg [6:0] money,price;
reg start,clk,reset;
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
fsmVendingMachine fsm (
// instance_name(signal name),
// Signal name can be the same as the instance name
disp_Q,disp_D,disp_N,disp_P,done,money,price,start,clk,reset);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk <= 0;
#5 clk <= 1;
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses/waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0,
money = 7'd75;
price = 7'd64;
reset = 1'b0;
start = 1'b1;
// @ t=50;
#50
money = 7'd100;
price = 7'd54;
reset = 1'b0;
start = 1'b1;
// @ t=100;
#50
money = 7'd50;
price = 7'd27;
reset = 1'b0;
start = 1'b1;
// @ t=150;
#50
money = 7'd50;
price = 7'd27;
reset = 1'b0;
start = 1'b1;
//
$display($time, " << Finishing the simulation >>");
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_pipe_misc.v
// Version : 1.10
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_core_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:33:21 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_2_stub.v
// Design : fifo_generator_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.1" *)
module fifo_generator_2(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[88:0],wr_en,rd_en,dout[88:0],full,empty" */;
input clk;
input rst;
input [88:0]din;
input wr_en;
input rd_en;
output [88:0]dout;
output full;
output empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long mx = 0, x = 0; cin >> n; for (int i = 0; i < n; i++) { long long y; cin >> y; y += mx; mx += max(0LL, x - y), x = max(y, x); } cout << mx << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int l = 0, r = 0; string s, t; cin >> s >> t; int i = 0; for (int j = 0; j < t.length(); j++) { if (s[i] == t[j]) { if (i == s.length() - 1) { i = s.length() - 1; l = j + 1; break; } else i++; } } for (int j = t.length() - 1; j > l - 1; j--) { if (s[i] == t[j]) { if (i == 0) { i = 0; r = t.length() - j; break; } else i--; } } if (l == 0 || r == 0) { cout << 0; return 0; } int ans; ans = t.length() - l - r + 1; cout << ans; return 0; } |
module testr(input clk, output real out, input wire real in);
always @(posedge clk)
out <= in + 1.0;
endmodule // testr
module testi(input clk, output int out, input wire int in);
always @(posedge clk)
out <= in + 1;
endmodule // testi
module main;
reg clk;
always begin
#10 clk = 0;
#10 clk = 1;
end
real srcr;
int srci;
wire real valr;
wire int vali;
testr r0 (.clk(clk), .out(valr), .in(srcr));
testi i0 (.clk(clk), .out(vali), .in(srci));
real refr;
int refi;
always @(posedge clk) begin
refr <= srcr + 1.0;
refi <= srci + 1;
end
initial begin
@(negedge clk) ;
srcr = 2.0;
srci = 2;
@(negedge clk) ;
@(negedge clk) ;
$display("srcr=%f, valr=%f, refr=%f", srcr, valr, refr);
if (valr != refr && valr != 3.0) begin
$display("FAILED");
$finish;
end
$display("srci=%0d, vali=%0d, refi=%0d", srci, vali, refi);
if (vali != refi && vali != 3) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int q, r, g, b, w; cin >> q; while (q--) { vector<int> a(4); int odd = 0, even = 0; for (int i = 0; i < 4; i++) { cin >> a[i]; if (a[i] % 2) odd += 1; else even += 1; } if (odd <= 1) cout << YES n ; else { if (min(a[0], min(a[1], a[2])) >= 1) { odd = 0, even = 0; for (int i = 0; i < 3; i++) { a[i] -= 1; if (a[i] % 2) odd += 1; else even += 1; } a[3] += 1; if (a[3] % 2) odd += 1; else even += 1; if (odd <= 1) cout << YES n ; else cout << NO n ; } else { cout << NO n ; } } } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_jp_sstl_odt_oebscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_jp_sstl_odt_oebscan(test_mode_oe ,bsr_hiz_l ,in ,update_dr
,mode_ctl ,shift_dr ,clock_dr ,bsr_so ,out ,bsr_si );
output bsr_so ;
output out ;
input test_mode_oe ;
input bsr_hiz_l ;
input in ;
input update_dr ;
input mode_ctl ;
input shift_dr ;
input clock_dr ;
input bsr_si ;
wire net021 ;
wire upd_hiz ;
wire net037 ;
wire net039 ;
wire net046 ;
wire net047 ;
wire net54 ;
bw_u1_muxi21_2x bs_mux (
.z (net54 ),
.d0 (in ),
.d1 (upd_hiz ),
.s (net021 ) );
bw_u1_inv_1x hiz_inv (
.z (upd_hiz ),
.a (net037 ) );
bw_u1_inv_1x se_inv (
.z (net039 ),
.a (test_mode_oe ) );
bw_u1_nand3_1x hiz_nand (
.z (net037 ),
.a (net046 ),
.b (bsr_hiz_l ),
.c (net039 ) );
bw_u1_inv_2x ctl_inv2x (
.z (net021 ),
.a (net047 ) );
bw_io_jp_bs_baseblk bs_baseblk (
.upd_q (net046 ),
.bsr_si (bsr_si ),
.update_dr (update_dr ),
.clock_dr (clock_dr ),
.shift_dr (shift_dr ),
.bsr_so (bsr_so ),
.in (in ) );
bw_u1_inv_5x out_inv5x (
.z (out ),
.a (net54 ) );
bw_u1_nor2_1x ctl_nor1x (
.z (net047 ),
.a (mode_ctl ),
.b (test_mode_oe ) );
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate task w/ multiple inputs, single output
module main;
reg var1,var2;
reg in1;
reg error;
task my_task ;
input in1,in2;
output out1,out2;
begin
out1 = in1 ;
out2 = in2 ;
end
endtask
initial
begin
error = 0;
my_task(1'b1,1'b0,var1,var2);
if(~(var1 & ~var2))
begin
$display("FAILED - task 3.14D task didn't return correct value (1)");
error = 1;
end
in1 = 0;
my_task(~in1,~in1,var1,var2);
if(~(var1 & var2))
begin
$display("FAILED - task 3.14D task didn't return correct value(2)");
error = 1;
end
in1 = 0;
my_task(in1,in1,var1,var2);
if(~(~var1 & ~var2))
begin
$display("FAILED - task 3.14D task didn't return correct value(2)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int n; char s[105][105]; char t[105]; bool judge1() { int i = 0; for (; i < n; i++) t[i] = E ; t[i] = 0 ; for (int i = 0; i < n; i++) if (strcmp(t, s[i]) == 0) return 1; return 0; } bool judge2() { for (int i = 0; i < n; i++) { int F = 1; for (int j = 0; j < n; j++) if (s[j][i] != E ) { F = 0; break; } if (F) return 1; } return 0; } int main() { while (~scanf( %d , &n)) { for (int i = 0; i < n; i++) scanf( %s , s[i]); if (judge1() && judge2()) { cout << -1 << endl; continue; } if (judge1()) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) if (s[j][i] == . ) { cout << j + 1 << << i + 1 << endl; break; } } } else for (int i = 0; i < n; i++) { int l = strlen(s[i]); for (int j = 0; j < l; j++) if (s[i][j] == . ) { cout << i + 1 << << j + 1 << endl; break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; char board[2100][2100]; int mark[2100][2100]; class Graph { int V; list<int> *adj; bool isCyclicUtil(int v, bool visited[], bool *rs); public: Graph(int V); void addEdge(int v, int w); bool isCyclic(); }; Graph::Graph(int V) { this->V = V; adj = new list<int>[V]; } void Graph::addEdge(int v, int w) { adj[v].push_back(w); } bool Graph::isCyclicUtil(int v, bool visited[], bool *recStack) { if (visited[v] == false) { visited[v] = true; recStack[v] = true; list<int>::iterator i; for (i = adj[v].begin(); i != adj[v].end(); ++i) { if (!visited[*i] && isCyclicUtil(*i, visited, recStack)) return true; else if (recStack[*i]) return true; } } recStack[v] = false; return false; } bool Graph::isCyclic() { bool *visited = new bool[V]; bool *recStack = new bool[V]; for (int i = 0; i < V; i++) { visited[i] = false; recStack[i] = false; } for (int i = 0; i < V; i++) if (isCyclicUtil(i, visited, recStack)) return true; return false; } int move(int i, int j) { int i0 = i, j0 = j; if (board[i][j] == # ) return 0; int di = 0, dj = 0; if (mark[i][j] != 0) { return mark[i][j]; } di = 0; dj = 0; if (board[i][j] == v ) di = 1; if (board[i][j] == ^ ) di = -1; if (board[i][j] == > ) dj = 1; if (board[i][j] == < ) dj = -1; i += di; j += dj; if (mark[i][j] != 0) { mark[i0][j0] = mark[i][j] + 1; return mark[i][j] + 1; } else { int d = move(i, j); mark[i0][j0] = d + 1; return d + 1; } } bool check(int i1, int j1, int i2, int j2) { if (board[i1][j1] == # || board[i1][j2] == # ) return false; int di1 = 0, dj1 = 0, di2 = 0, dj2 = 0; while (board[i1][j1] != # || board[i2][j2] != # ) { di1 = 0; dj1 = 0, di2 = 0, dj2 = 0; if (board[i1][j1] == v ) di1 = 1; if (board[i1][j1] == ^ ) di1 = -1; if (board[i1][j1] == > ) dj1 = 1; if (board[i1][j1] == < ) dj1 = -1; i1 += di1; j1 += dj1; if (board[i2][j2] == v ) di2 = 1; if (board[i2][j2] == ^ ) di2 = -1; if (board[i2][j2] == > ) dj2 = 1; if (board[i2][j2] == < ) dj2 = -1; i2 += di2; j2 += dj2; if (i1 == i2 && j1 == j2) if (board[i1][j1] != # ) return false; } return true; } Graph g(2000 * 2000); int main() { int n, m, max = 0, val = 0, maxi[2000], maxj[2000], num = 0, cnt = 0; bool f = false; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> board[i][j]; if (board[i][j] == v && cnt < 10000) { g.addEdge(m * i + j, m * (i + 1) + j); cnt++; } if (board[i][j] == ^ && cnt < 10000) { g.addEdge(m * i + j, m * (i - 1) + j); cnt++; } if (board[i][j] == > && cnt < 10000) { g.addEdge(m * i + j, m * i + j + 1); cnt++; } if (board[i][j] == < && cnt < 10000) { g.addEdge(m * i + j, m * i + j - 1); cnt++; } } } if (g.isCyclic()) { cout << -1; return 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { val = move(i, j); if (val == max && !f && max != 0) { maxj[num] = j; maxi[num] = i; num++; } if (val > max) { max = val; maxi[0] = i; maxj[0] = j; num = 1; f = false; } } } if (max == 0) { cout << 0; return 0; } if (num > 1) f = check(maxi[0], maxj[0], maxi[1], maxj[1]); if (num > 2) { for (int i = 2; i < num; i++) { if (!f) { f = check(maxi[1], maxj[1], maxi[i], maxj[i]); } } } if (f) cout << max * 2; else cout << max * 2 - 1; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/07/2015 06:38:17 PM
// Design Name:
// Module Name: m_port_ultra
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module m_port_ultra (
input clk,
input reset_n,
input ack,
input [32767:0] convexCloud,
output [4095:0] convexHull1,
output [4095:0] convexHull2,
output [4095:0] convexHull3,
output [4095:0] convexHull4,
output [4095:0] convexHull5,
output [4095:0] convexHull6,
output [4095:0] convexHull7,
output [4095:0] convexHull8,
output [8:0] convexHullSize1,
output [8:0] convexHullSize2,
output [8:0] convexHullSize3,
output [8:0] convexHullSize4,
output [8:0] convexHullSize5,
output [8:0] convexHullSize6,
output [8:0] convexHullSize7,
output [8:0] convexHullSize8,
output processorDone1,
output processorDone2,
output processorDone3,
output processorDone4,
output processorDone5,
output processorDone6,
output processorDone7,
output processorDone8,
output QINIT,
output QPULSE,
output QDIVIDE,
output QCONVEX_HULL,
output QDISPLAY
);
// Registers -- State machine intermediate values
reg [3:0] timer;
reg processorEnable;
reg divideEnable;
reg divideFinished;
// Module declaration
m_port_ultra_processor_array processorArray (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.divideEnable (divideEnable),
.divideFinished (divideFinished),
.convexCloud (convexCloud),
.convexHull1 (convexHull1),
.convexHull2 (convexHull2),
.convexHull3 (convexHull3),
.convexHull4 (convexHull4),
.convexHull5 (convexHull5),
.convexHull6 (convexHull6),
.convexHull7 (convexHull7),
.convexHull8 (convexHull8),
.convexHullSize1 (convexHullSize1),
.convexHullSize2 (convexHullSize2),
.convexHullSize3 (convexHullSize3),
.convexHullSize4 (convexHullSize4),
.convexHullSize5 (convexHullSize5),
.convexHullSize6 (convexHullSize6),
.convexHullSize7 (convexHullSize7),
.convexHullSize8 (convexHullSize8),
.processorDone1 (processorDone1),
.processorDone2 (processorDone2),
.processorDone3 (processorDone3),
.processorDone4 (processorDone4),
.processorDone5 (processorDone5),
.processorDone6 (processorDone6),
.processorDone7 (processorDone7),
.processorDone8 (processorDone8)
);
// State Machine
reg[4:0] state;
localparam
INIT = 5'b00001,
PULSE = 5'b00010,
DIVIDE = 5'b00100,
CONVEX_HULL = 5'b01000,
DISPLAY = 5'b10000;
// Processor output
assign { QDISPLAY, QCONVEX_HULL, QDIVIDE, QPULSE, QINIT } = state;
//NSL and State Machine
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
timer <= 0;
processorEnable <= 0;
divideEnable <= 0;
divideFinished <= 0;
state <= INIT;
end
else begin
case (state)
INIT: begin
timer <= 0;
if (ack) begin
state <= PULSE;
end
end
PULSE: begin
timer <= timer + 1;
if (timer >= 9) begin
divideEnable <= 1'b1;
state <= DIVIDE;
end
end
DIVIDE: begin
processorEnable <= 1;
state <= CONVEX_HULL;
end
CONVEX_HULL: begin
if (processorDone1 && processorDone2 && processorDone3 && processorDone4 && processorDone5 && processorDone6 && processorDone7 && processorDone8) begin
state <= DISPLAY;
end
end
DISPLAY: begin
if (ack) begin
state <= INIT;
end
end
endcase
end
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression evaluates to a value outside the range specified by parameters min and max");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = ((test_expr < min) || (test_expr > max));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
// REVISIT: update only if SANITY on?
prev_test_expr <= test_expr; // deliberately not reset
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_at_min covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_at_max covered"); // corner
end
if (fire_cover_1 || fire_cover_2 || fire_cover_3) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == min));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == max));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; int sum, c = 0; cin >> n; int arr[3]; for (int i = 0; i < n; i++) { for (int i = 0; i < 3; i++) { cin >> arr[i]; } sum = arr[0] + arr[1] + arr[2]; if (sum > 1) c++; } cout << c; return 0; } |
#include <bits/stdc++.h> using namespace std; // #include <atcoder/all> // using namespace atcoder; #define rep(i,n) for (int i = 0; i < (n); ++i) #define STRING(str) #str #define ll long long #define ld long double template <typename T> void print(T x, string name) { cout << name+ : << x << endl; } template <typename T > void print_vec_1d(vector<T> x, string name) { cout << name << endl; cout << [ ; for (int i=0;i<x.size();i++) { cout << x[i]; if (i != x.size()-1) cout << , ; else cout << ] << endl; } } template <typename T > void print_vec_2d(vector<vector<T>> x, string name) { cout << name << endl; cout << [ ; for (int i=0;i<x.size();i++) { cout << [ ; for (int j=0;j<x[i].size();j++) { cout << x[i][j]; if (j != x[i].size()-1) cout << , ; else { cout << ] ; if (!((i == x.size()-1) && (j == x[i].size()-1))) { cout << , << endl; } } } } cout << ] << endl; } template <typename T > void print_vec_3d(vector<vector<vector<T>>> x, string name) { cout << name << endl; cout << [ ; for (int i=0;i<x.size();i++) { cout << [ ; for (int j=0;j<x[i].size();j++) { cout << [ ; for (int k=0;k<x[i][j].size();k++) { cout << x[i][j][k]; if (k != x[i][j].size()-1) cout << , ; else { cout << ] ; if (!((i == x.size()-1) && (j == x[i].size()-1) && (k == x[i][j].size()-1))) { cout << , << endl; } } } if (j != x[i].size()-1) cout << , ; else { cout << ] ; if (!((i == x.size()-1) && (j == x[i].size()-1))) { cout << , << endl; } } } } cout << ] << endl; } int main() { // ios::sync_with_stdio(0); // cin.tie(0); int n; cin >> n; int ind_2; cout << ? 1 << n << n ; cin >> ind_2; ind_2--; int a1, a2; if (ind_2 != 0 && ind_2 != n-1) { cout << ? 1 << ind_2+1 << n ; cin >> a1; a1--; int a2; cout << ? << ind_2+1 << << n << n ; cin >> a2; a2--; } bool left_flag; if (ind_2 == n-1) { left_flag = true; } else if (ind_2 == 0) { left_flag = false; } else if (ind_2 == a1) { left_flag = true; } else { // ind_2 == a2 left_flag = false; } if (left_flag) { // ? ? ? 1 ? ? ? 2 ? ? ? ? int ok = 0; int ng = ind_2; while (abs(ok-ng) > 1) { int mid = (ok+ng)/2; int b; cout << ? << mid+1 << << ind_2+1 << n ; cin >> b; b--; if (b == ind_2) { ok = mid; } else { ng = mid; } } cout << ! << ok+1 << n ; } else { // ? ? ? ? ? ? ? 2 ? 1 ? ? int ok = n-1; int ng = ind_2; while (abs(ok-ng) > 1) { int mid = (ok+ng)/2; int b; cout << ? << ind_2+1 << << mid+1 << n ; cin >> b; b--; if (b == ind_2) { ok = mid; } else { ng = mid; } } cout << ! << ok+1 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, a, b, ans; scanf( %d , &t); while (t--) { ans = 0; scanf( %d %d , &a, &b); while (a > 0 && b > 0) { if (a >= b) { ans += (a / b); a = a % b; } else if (b > a) { ans += (b / a); b = b % a; } } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> int main() { int n, i, j, g, k, a[3]; while (~scanf( %d , &n)) { for (i = 0, k = 0; i < n; i++) { for (j = 0, g = 0; j < 3; j++) { scanf( %d , &a[j]); if (a[j] == 1) { g++; } } if (g >= 2) { k++; } } printf( %d n , k); } return 0; } |
#include <bits/stdc++.h> using namespace std; int ans = 1000000005, rans = 0, bans = 0; int numr[20], numb[20], color[20]; int dp[70005][160]; bool life[70005][160]; int nowr, nowb, tempr, tempb; char s[6]; int nex[20]; void ok(int x) { int now; nowr = nowb = now = 0; while (x) { if (x % 2) { if (color[now]) nowb++; else nowr++; } x /= 2; now++; } } int main() { int n; cin >> n; int maxx = 1 << n, maxxx = n * (1 + n) / 2; nex[0] = 1; life[0][0] = 1; for (int i = 1; i < n; i++) nex[i] = nex[i - 1] * 2; for (int i = 0; i < n; i++) { scanf( %s , s); if (s[0] == R ) color[i] = 0; else color[i] = 1; scanf( %d%d , numr + i, numb + i); rans += numr[i]; bans += numb[i]; } for (int i = 0; i < maxx; i++) { ok(i); for (int j = 0; j < n; j++) { if ((nex[j] & i) == 0) { tempr = min(nowr, numr[j]); tempb = min(nowb, numb[j]); for (int k = 0; k <= maxxx; k++) if (life[i][k]) { dp[i + nex[j]][k + tempr] = max(dp[i + nex[j]][k + tempr], dp[i][k] + tempb); life[i + nex[j]][k + tempr] = 1; } } } } for (int i = 0; i < maxxx; i++) if (life[maxx - 1][i]) { ans = min(ans, max(rans - i, bans - dp[maxx - 1][i])); } cout << ans + n << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int N = 1e6; ; int n, m, a, l, r, num; int arr[2]; int main() { scanf( %d%d , &n, &m); while (n--) { scanf( %d , &a); if (a == -1) ++arr[0]; else ++arr[1]; } while (m--) { scanf( %d%d , &l, &r); if (l == r) { printf( 0 n ); continue; } num = r - l + 1; if (num % 2 != 0) printf( 0 n ); else { if (num / 2 > arr[0] || num / 2 > arr[1]) printf( 0 n ); else printf( 1 n ); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_TB_V
`define SKY130_FD_SC_LS__FILL_DIODE_TB_V
/**
* fill_diode: Fill diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__fill_diode dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__BUFBUF_BEHAVIORAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x, y; cin >> x; int c = 1; bool ch = true; for (int i = 0; i < n - 1; i++) { cin >> y; if (y > x) { if (c != 1) ch = false; } else if (x == y) { if (c > 2) { ch = false; } else c = 2; } else if (x > y) { c = 3; } x = y; } if (ch) cout << YES ; else cout << NO ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$PS_pp$PKG$s: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PKG$s (
Q ,
D ,
CLK ,
SET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input SET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_S_BLACKBOX_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module Video_System_VGA_Controller (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 20;
parameter G_UI = 19;
parameter G_LI = 10;
parameter B_UI = 9;
parameter B_LI = 0;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int NMax = 40, MMax = 200; int N, nn, A[NMax][NMax], B[NMax]; int get(int a, int b) { return (a ^ b); } int P(int a, int b) { if (b) return a * -1; else return a; } int main() { scanf( %d , &N); nn = (N + 1) >> 1; for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) scanf( %d , &A[i][j]); int ret = -100000000; for (int I = 0; I < (1 << nn); I++) { int cnt = 0; int k = I; for (int i = 1; i <= nn; i++) { B[i] = (I & 1); cnt += P(A[i][nn], B[i]); I >>= 1; } I = k; for (int i = 1; i < nn; i++) cnt += P(A[i + nn][nn], get(B[i], B[nn])); for (int i = 1; i < nn; i++) { int tot0 = P(A[nn][i], 0) + P(A[nn][nn + i], get(0, B[nn])), tot1 = P(A[nn][i], 1) + P(A[nn][nn + i], get(1, B[nn])); for (int j = 1; j < nn; j++) { int maxx = -100000000; for (int first = 0; first < 2; first++) { int second = 0; int x1 = get(first, B[j]), x2 = get(second, B[nn]), x3 = get(B[j], B[nn]), x4 = get(first, second), x5 = get(x1, x2); if (get(x3, x4) == x5) maxx = max(maxx, P(A[j][i], first) + P(A[j][nn + i], x1) + P(A[nn + j][i], x4) + P(A[nn + j][nn + i], x5)); } if (maxx != -100000000) tot0 += maxx; else tot0 = -100000000; } for (int j = 1; j < nn; j++) { int maxx = -100000000; for (int first = 0; first < 2; first++) { int second = 1; int x1 = get(first, B[j]), x2 = get(second, B[nn]), x3 = get(B[j], B[nn]), x4 = get(first, second), x5 = get(x1, x2); if (get(x3, x4) == x5) maxx = max(maxx, P(A[j][i], first) + P(A[j][nn + i], x1) + P(A[nn + j][i], x4) + P(A[nn + j][nn + i], x5)); } if (maxx != -100000000) tot1 += maxx; else tot1 = -100000000; } cnt += max(tot0, tot1); } ret = max(ret, cnt); } printf( %d n , ret); return 0; } |
#include <bits/stdc++.h> using namespace std; void desperate_optimization(int precision) { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.setf(ios::fixed); cout.setf(ios::showpoint); cout.precision(precision); } const int N = 2e5; long long arrA[N + 5], arrB[N + 5]; long long posA[N + 5], posB[N + 5]; long long res[N + 5]; long long bit[N + 5]; int n; int query(int x) { int tot = 0; for (; x; x -= (x & -x)) tot += bit[x]; return tot; } void update(int x) { for (; x <= n; x += (x & -x)) bit[x]++; } void hora(int tc) { cin >> n; for (int i = 0; i < n; i++) cin >> arrA[i]; for (int i = 0; i < n; i++) cin >> arrB[i]; for (int i = 0; i < n; i++) { int val = query(arrA[i] + 1); posA[i] = arrA[i] - val; update(arrA[i] + 1); } memset(bit, 0, sizeof bit); for (int i = 0; i < n; i++) { int val = query(arrB[i] + 1); posB[i] = arrB[i] - val; update(arrB[i] + 1); } long long cur = 0; long long sisa = 0; for (int i = n - 1; i >= 0; i--) { res[i] = posA[i] + posB[i] + sisa; sisa = res[i] / (cur + 1); res[i] %= (cur + 1); cur += 1; } memset(bit, 0, sizeof bit); for (int i = 0; i < n; i++) { int lo = 0; int hi = n; int ans = -1; while (lo <= hi) { int mid = (lo + hi) / 2; if (mid - query(mid + 1) >= res[i]) { ans = mid; hi = mid - 1; } else lo = mid + 1; } update(ans + 1); cout << ans << ; } } int main() { desperate_optimization(10); int ntc = 1; for (int tc = 1; tc <= ntc; tc++) hora(tc); return 0; } |
#include <bits/stdc++.h> using namespace std; void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } const int INF = 1e9; const long long MOD = 1e9 + 7; const int N = 1e5 + 5, MO = 350, SQ = 650; int n, q, A[N], QL[N], QR[N], P[N], T[N], C[N], K[N], Q[N]; vector<int> B, X, Y; bool CMP(int i, int j) { if (QL[i] / MO != QL[j] / MO) return QL[i] < QL[j]; return (QL[i] / MO) % 2 ? QR[i] > QR[j] : QR[i] < QR[j]; } void Update(int x, int y) { T[C[x]]--, C[x] += y, T[C[x]]++; } void Insert(int x, int y) { if (x >= SQ && !K[x]) Y.push_back(x); K[x] += y; } int Huf() { X.clear(), Y.clear(); for (int i : B) if (C[i] >= SQ) X.push_back(C[i]), K[C[i]]++; sort(X.begin(), X.end()); int huf = 0, c = 0, x = 0, y = 0; for (int i = 1; i < SQ; i++) if (K[i] + T[i]) { K[i] += T[i]; if (c) huf += i + c, K[i]--, Insert(i + c, 1), c = 0; if (K[i] & 1) c = i, K[i]--; if (K[i]) huf += i * K[i], Insert(i + i, K[i] >> 1), K[i] = 0; } while (x < (int)(X.size()) || y < (int)(Y.size())) { while (x + 1 < (int)(X.size()) && X[x + 1] == X[x]) x++; while (y + 1 < (int)(Y.size()) && Y[y + 1] == Y[y]) y++; int i = 0; if (x == (int)(X.size())) i = Y[y++]; else if (y == (int)(Y.size())) i = X[x++]; else if (X[x] < Y[y]) i = X[x++]; else i = Y[y++]; if (c) huf += i + c, K[i]--, Insert(i + c, 1), c = 0; if (K[i] & 1) c = i, K[i]--; if (K[i]) huf += i * K[i], Insert(i + i, K[i] >> 1), K[i] = 0; } return huf; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); mt19937 Rnd(time(0)); cin >> n; for (int i = 0; i < n; i++) cin >> A[i], C[A[i]]++; for (int i = 0; i < N; i++) if (C[i] >= SQ) B.push_back(i); for (int i = 0; i < n; i++) C[A[i]]--; cin >> q; for (int i = 0; i < q; i++) cin >> QL[i] >> QR[i], QL[i]--, P[i] = i; sort(P, P + q, CMP); int L = 0, R = 0; for (int i = 0; i < q; i++) { int l = QL[P[i]], r = QR[P[i]]; while (l < L) Update(A[--L], +1); while (R < r) Update(A[R++], +1); while (L < l) Update(A[L++], -1); while (r < R) Update(A[--R], -1); Q[P[i]] = Huf(); } for (int i = 0; i < q; i++) cout << Q[i] << endl; return 0; } |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat progress (f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
reflexivity.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
//
// Copyright (c) 2000 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// force3.17A - Template 1 - force net_lvalue = constant.
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
wire [3:0] val3;
initial
begin
#50 ;
if(val3 !== 4'b1010)
$display("FAILED");
else
$display("PASSED");
end
initial
begin
#20;
force val3 = 4'b1010;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 5007; const double eps = 0.00000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } template <typename T> inline T powMM(T a, T b) { T ret = 1; for (; b; b >>= 1ll, a = a * a % M) ret = 1ll * ret * a % M; return ret; } vector<int> edge[maxn]; vector<long long> dp1[maxn], dp2[maxn]; long long now1[maxn], now2[maxn]; long long a[maxn], b[maxn], m; int num[maxn], ans; void dfs(int x) { num[x] = 1; dp1[x].resize(maxn, INFF); dp2[x].resize(maxn, INFF); dp1[x][1] = a[x]; dp1[x][0] = 0; dp2[x][1] = a[x] - b[x]; dp2[x][0] = INFF; int i, j; for (int v : edge[x]) { dfs(v); for (i = 0; i <= num[x]; i++) now1[i] = dp1[x][i], now2[i] = dp2[x][i]; for (i = 0; i <= num[x]; i++) for (j = 1; j <= num[v]; j++) { dp1[x][i + j] = min(dp1[x][i + j], now1[i] + dp1[v][j]); dp2[x][i + j] = min(dp2[x][i + j], now2[i] + min(dp1[v][j], dp2[v][j])); } vector<long long>().swap(dp1[v]); vector<long long>().swap(dp2[v]); num[x] += num[v]; } } int n; int i, j, k; int main() { scanf( %d%I64d , &n, &m); for (i = 1; i <= n; i++) { scanf( %I64d%I64d , &a[i], &b[i]); if (i != 1) { int v; scanf( %d , &v); edge[v].push_back(i); }; } dfs(1); ans = 0; for (i = 1; i <= n; i++) if (dp1[1][i] <= m || dp2[1][i] <= m) ans = max(ans, i); printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; int n, m, k, w, f[1005], ans, cnt, t; char a[1005][15][15]; vector<int> v[1005]; struct rec { int x, y, z; } e[1050005]; bool operator<(rec a, rec b) { return (a.z < b.z); } int find(int x) { if (f[x] == x) return x; else return (f[x] = find(f[x])); } void dfs(int x, int fa) { if (x > 0) cout << x << << fa << n ; for (auto y : v[x]) if (y != fa) dfs(y, x); } int main() { cin >> n >> m >> k >> w; for (int i = 1; i <= k; ++i) { for (int j = 1; j <= n; ++j) for (int k = 1; k <= m; ++k) cin >> a[i][j][k]; e[++cnt].x = 0, e[cnt].y = i, e[cnt].z = n * m; for (int j = 1; j <= i - 1; ++j) { int sum = 0; for (int k = 1; k <= n; ++k) for (int l = 1; l <= m; ++l) if (a[j][k][l] != a[i][k][l]) sum += w; e[++cnt].x = i, e[cnt].y = j, e[cnt].z = sum; } } sort(e + 1, e + cnt + 1); for (int i = 0; i <= k; ++i) f[i] = i; for (int i = 1; i <= cnt; ++i) { int p = find(e[i].x), q = find(e[i].y); if (p != q) { f[p] = q; ans += e[i].z; v[e[i].x].push_back(e[i].y), v[e[i].y].push_back(e[i].x); ++t; if (t == k) break; } } cout << ans << n ; dfs(0, -1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, i; long long s, ans; int x[200000], y[200000]; long long a[200000], b[200000], c[200000], d[200000]; void count() { s = 0; for (i = 1; i <= n; i++) b[i] = c[i] = d[i] = 0; for (i = 1; i < n; i++) a[i] = a[i + 1] - a[i]; for (i = 1; i < n; i++) { b[i] = b[i - 1] + i * a[i]; c[i] = c[i - 1] + i * a[i] * a[i]; } for (i = 2; i < n; i++) d[i] = d[i - 1] + 2 * a[i] * b[i - 1]; for (i = 1; i < n; i++) s += c[i] + d[i]; } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d%d , &x[i], &y[i]); x[0] = y[0] = -200000000; for (i = 0; i <= n; i++) a[i] = x[i]; sort(a, a + n + 1); count(); ans += s; for (i = 0; i <= n; i++) a[i] = y[i]; sort(a, a + n); count(); ans += s; cout << ans; return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:33:48 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Initial/Initial_stub.v
// Design : Initial
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *)
module Initial(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[1599:0]" */;
input clka;
input [9:0]addra;
output [1599:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { long long a, b, n, m; scanf( %lld%lld%lld%lld , &a, &b, &n, &m); if (a < m || b < m) { printf( No n ); continue; } if ((a + b) < (m + n)) { printf( No n ); continue; } if (a <= b) { a -= m; } else { b -= m; } if (a + b >= n) { printf( Yes n ); } } return 0; } |
// This is the motor_controller for each H-bridge circuit
// Direction and on/off can be specified, as well as duty cycle
`include "defines.v"
module motor_controller (input clk, input dir, input on, input [15:0] period, input [15:0] duty_cycle, output [3:0] out);
reg [`PERIOD_LENGTH-1:0] duty_counter = 0;
reg dir_reg;
always @(posedge clk)
begin
if (duty_counter == period)
duty_counter <= 0;
else
duty_counter <= duty_counter + 1;
dir_reg <= (on && duty_counter < duty_cycle) ? ~dir : dir;
end
motor_internal mi(clk, dir_reg, on, out);
endmodule
module motor_internal (input clk, input dir, input on, output reg [3:0] out);
reg [3:0] out_reg;
reg [9:0] dead_time_counter = `DEAD_TIME;
reg [1:0] prev_in = 2'b00;
always @(posedge clk)
begin
if ({dir, on} != prev_in)
dead_time_counter <= 10'd0;
if (dead_time_counter != `DEAD_TIME)
dead_time_counter <= dead_time_counter + 10'd1;
casex ({dir, on})
2'b00: out_reg <= 4'b0000;
2'b10: out_reg <= 4'b1010;
2'b11: out_reg <= 4'b1001;
2'b01: out_reg <= 4'b0110;
endcase
prev_in <= {dir, on};
out <= (dead_time_counter != `DEAD_TIME) ? 4'd0 : out_reg;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_src_mm_axi (
input m_axi_aclk,
input m_axi_aresetn,
input req_valid,
output req_ready,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
output response_valid,
input response_ready,
output [1:0] response_resp,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
output [C_ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
output fifo_valid,
input fifo_ready,
output [C_DMA_DATA_WIDTH-1:0] fifo_data,
// Read address
input m_axi_arready,
output m_axi_arvalid,
output [31:0] m_axi_araddr,
output [ 7:0] m_axi_arlen,
output [ 2:0] m_axi_arsize,
output [ 1:0] m_axi_arburst,
output [ 2:0] m_axi_arprot,
output [ 3:0] m_axi_arcache,
// Read data and response
input [C_DMA_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp
);
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
parameter C_BEATS_PER_BURST_WIDTH = 4;
`include "resp.h"
wire address_enabled;
wire address_req_valid;
wire address_req_ready;
wire data_req_valid;
wire data_req_ready;
assign sync_id_ret = sync_id;
assign response_id = data_id;
assign response_valid = 1'b0;
assign response_resp = RESP_OKAY;
splitter #(
.C_NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
);
dmac_address_generator #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.sync_id(sync_id),
.request_id(request_id),
.id(address_id),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.eot(address_eot),
.addr_ready(m_axi_arready),
.addr_valid(m_axi_arvalid),
.addr(m_axi_araddr),
.len(m_axi_arlen),
.size(m_axi_arsize),
.burst(m_axi_arburst),
.prot(m_axi_arprot),
.cache(m_axi_arcache)
);
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DMA_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(address_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(address_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_valid(m_axi_rvalid),
.s_axi_ready(m_axi_rready),
.s_axi_data(m_axi_rdata),
.m_axi_valid(fifo_valid),
.m_axi_ready(fifo_ready),
.m_axi_data(fifo_data),
.m_axi_last()
);
reg [1:0] rresp;
always @(posedge m_axi_aclk)
begin
if (m_axi_rvalid && m_axi_rready) begin
if (m_axi_rresp != 2'b0)
rresp <= m_axi_rresp;
end
end
endmodule
|
`include "senior_defines.vh"
`include "registers.h"
module condition_logic
#(parameter alu_flags_w = `ALU_NUM_FLAGS,
parameter mac_flags_w = `MAC_NUM_FLAGS,
parameter ctrl_w = `COND_LOGIC_CTRL_WIDTH)
(
input wire [ctrl_w-1:0] ctrl_i,
input wire [alu_flags_w-1:0] alu_flags_i,
input wire [mac_flags_w-1:0] mac_flags_i,
output reg condition_check_o
);
`include "std_messages.vh"
always @(*) begin
case (ctrl_i`COND_LOGIC_CDT)
`UT: condition_check_o=1'b1;
`EQ: condition_check_o=alu_flags_i[`ALU_FLAG_AZ];
`NE: condition_check_o=~alu_flags_i[`ALU_FLAG_AZ];
`UGT: condition_check_o=(~alu_flags_i[`ALU_FLAG_AZ]) & (alu_flags_i[`ALU_FLAG_AC]);
`UGE_CS: condition_check_o=alu_flags_i[`ALU_FLAG_AC];
`ULE: condition_check_o=alu_flags_i[`ALU_FLAG_AZ] | ~alu_flags_i[`ALU_FLAG_AC];
`ULT_CC: condition_check_o=~alu_flags_i[`ALU_FLAG_AC];
`SGT: condition_check_o=(~alu_flags_i[`ALU_FLAG_AZ]) & ~(alu_flags_i[`ALU_FLAG_AN]^alu_flags_i[`ALU_FLAG_AV]);
`SGE: condition_check_o = ~(alu_flags_i[`ALU_FLAG_AN]^alu_flags_i[`ALU_FLAG_AV]);
`SLE: condition_check_o = alu_flags_i[`ALU_FLAG_AZ] | ~(alu_flags_i[`ALU_FLAG_AN]^(~alu_flags_i[`ALU_FLAG_AV]));
`SLT: condition_check_o= ~(alu_flags_i[`ALU_FLAG_AN]^(~alu_flags_i[`ALU_FLAG_AV]));
`MI: condition_check_o=alu_flags_i[`ALU_FLAG_AN];
`PL: condition_check_o=~alu_flags_i[`ALU_FLAG_AN];
`VS: condition_check_o=alu_flags_i[`ALU_FLAG_AV];
`VC: condition_check_o=~alu_flags_i[`ALU_FLAG_AV];
`MEQ: condition_check_o=mac_flags_i[`MAC_FLAG_MZ];
`MNE: condition_check_o=~mac_flags_i[`MAC_FLAG_MZ];
`MGT: condition_check_o=(~mac_flags_i[`MAC_FLAG_MZ]) & (~mac_flags_i[`MAC_FLAG_MN]);
`MGE_MPL: condition_check_o=~mac_flags_i[`MAC_FLAG_MN];
`MLE: condition_check_o=(~mac_flags_i[`MAC_FLAG_MZ]) | mac_flags_i[`MAC_FLAG_MN];
`MLT_MMI: condition_check_o=mac_flags_i[`MAC_FLAG_MN];
`MVS: condition_check_o=mac_flags_i[`MAC_FLAG_MS];
`MVC: condition_check_o=~mac_flags_i[`MAC_FLAG_MS];
default: begin
condition_check_o=1'b1; // others reserved
if(defined_but_illegal(ctrl_i`COND_LOGIC_CDT,5,"ctrl_i`COND_LOGIC_CDT")) begin
$stop;
end
end
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; map<long long, bool> mapa; long long _abs(long long a) { if (a >= 0) return a; else return -a; } int main() { long long b1, q, l, m; cin >> b1 >> q >> l >> m; for (int i = 0; i < m; i++) { long long a; cin >> a; mapa[a] = 1; } if (b1 == 0LL) { if (!mapa.count(0)) cout << inf n ; else cout << 0 n ; return 0; } if (q == 0LL) { if (_abs(b1) > l) cout << 0 n ; else if (!mapa.count(0)) cout << inf n ; else if (!mapa.count(b1)) cout << 1 n ; else cout << 0 n ; return 0; } else if (q == 1LL) { if (_abs(b1) <= l && !mapa.count(b1)) cout << inf n ; else cout << 0 n ; return 0; } else if (q == -1LL) { if (_abs(b1) > l) cout << 0 n ; else if (!mapa.count(b1) || !mapa.count(-b1)) cout << inf n ; else cout << 0 n ; return 0; } long long val = b1; int cont = 0; while (_abs(val) <= l) { if (!mapa.count(val)) cont++; val *= q; } cout << cont << n ; } |
// DEFINES
`define BITS 32 // Bit width of the operands
module syn2(clock,
reset,
in1,
in2,
in3,
in4,
in5,
out_1,
out_2,
out_3,
out_4
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] in1;
input [`BITS-1:0] in2;
input [`BITS-1:0] in3;
input [`BITS-1:0] in4;
input [`BITS-1:0] in5;
output [`BITS-1:0] out_1;
output [`BITS-1:0] out_2;
output [`BITS-1:0] out_3;
output [`BITS-1:0] out_4;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] x4;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] add2;
wire [`BITS-1:0] add3;
wire [`BITS-1:0] add4;
wire [`BITS-1:0] add5;
reg [`BITS-1:0] reg1;
reg [`BITS-1:0] reg2;
reg [`BITS-1:0] reg3;
reg [`BITS-1:0] reg4;
reg [`BITS-1:0] reg5;
reg [`BITS-1:0] reg6;
wire [`BITS-1:0] out_1;
wire [`BITS-1:0] out_2;
wire [`BITS-1:0] out_3;
wire [`BITS-1:0] out_4;
// ASSIGN STATEMENTS
//assign add1 = reg1 + in4;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(reg6),
.opb(in4),
.out(add1),
.control(add1_control)
);
//assign x1 = x3 * in1;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(x3),
.opb(in1),
.out(x1),
.control(x1_control)
);
//assign add2 = add5 + add1;
wire [7:0] add2_control;
fpu_add add2_add
(
.clk(clock),
.opa(add5),
.opb(add1),
.out(add2),
.control(add2_control)
);
//assign x2 = x1 * add2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(x1),
.opb(add2),
.out(x2),
.control(x2_control)
);
//assign add3 = in1 + reg1;
wire [7:0] add3_control;
fpu_add add3_add
(
.clk(clock),
.opa(in1),
.opb(reg6),
.out(add3),
.control(add3_control)
);
//assign x3 = in3 * in1;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(in3),
.opb(in1),
.out(x3),
.control(x3_control)
);
//assign add4 = in5 + in3;
wire [7:0] add4_control;
fpu_add add4_add
(
.clk(clock),
.opa(in5),
.opb(in3),
.out(add4),
.control(add4_control)
);
//assign x4 = in5 * in4;
wire [7:0] x4_control;
fpu_mul x4_mul
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(x4),
.control(x4_control)
);
//assign add5 = in5 + in4;
wire [7:0] add5_control;
fpu_add add5_add
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(add5),
.control(add5_control)
);
assign out_1 = x2;
assign out_2 = add3;
assign out_3 = add4;
assign out_4 = x4;
always @(posedge clock)
begin
reg1 <= in2;
reg2 <= reg1;
reg3 <= reg2;
reg4 <= reg3;
reg5 <= reg4;
reg6 <= reg5;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10, B = 1e6 + 3; int n, m, p1[N][2], p2[N][2], x, y; long long ans = 1; int main() { scanf( %d%d n , &n, &m); char a[n + 3][m + 3]; for (int i = 0; i < n; ++i) gets(a[i]); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) if (a[i][j] != . ) { x = (a[i][j] < 2 ) || (a[i][j] > 3 ); y = i % 2; p1[j][x ^ y] = 1; x = a[i][j] < 3 ; y = j % 2; p2[i][x ^ y] = 1; } } for (int i = 0; i < m; ++i) ans = (ans * (2 - p1[i][0] - p1[i][1])) % B; for (int i = 0; i < n; ++i) ans = (ans * (2 - p2[i][0] - p2[i][1])) % B; printf( %lld n , ans); return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: init_config.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fixed_config (
address_in,
clock,
q);
parameter LUT_SIZE = 6;
parameter NUM_STAGES = 78;
input [31:0] address_in;
input clock;
output [31:0] q;
// (2^lut_inputs times Num_Config_stages)
reg [31:0] ram[0:(2**LUT_SIZE)*NUM_STAGES];
reg [31:0] q;
// Initializing BlockRAM from external datafile
initial
begin
//$readmemh("output.hex.mif",ram,0,(2**LUT_SIZE)*NUM_STAGES);
$readmemh("output.hex.mif",ram);
end
always@(posedge clock)
begin
q = ram[address_in];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 5; int n; char str[N]; vector<int> g[N]; inline void init() { scanf( %d , &n); for (int i = 1, u, v; i < n; i++) { scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } scanf( %s , str + 1); for (int i = 1; i <= n; i++) { if (str[i] == W ) { g[i].push_back(++n); g[n].push_back(i); g[n].push_back(n + 1); g[n + 1].push_back(n); g[n].push_back(n + 2); g[n + 2].push_back(n); n = n + 2; } } } int dfs(int p, int fa, int dest) { if (p == dest) { return 1; } for (auto e : g[p]) { if (e ^ fa) { int ret = dfs(e, p, dest); if (~ret) { return ret ^ 1; } } } return -1; } vector<int> d3; inline void solve() { d3.clear(); for (int i = 1; i <= n; i++) { if (g[i].size() >= 4) { puts( White ); return; } if (g[i].size() == 3) { d3.push_back(i); int _cnt = 0; for (auto e : g[i]) { if (g[e].size() >= 2) { _cnt++; } } if (_cnt >= 2) { puts( White ); return; } } } if (d3.size() >= 3) { puts( White ); return; } if (d3.size() == 2) { puts((dfs(d3[0], 0, d3[1])) ? ( White ) : ( Draw )); } else { puts( Draw ); } } inline void clear() { for (int i = 1; i <= n; i++) { g[i].clear(); } } int T; int main() { scanf( %d , &T); while (T--) { init(); solve(); clear(); } return 0; } |
//////////////////////////////////////////////////////////////////
// //
// Asynchronous FIFO set for Wishbone to Xilinx Virtex-6 //
// DDR3 Bridge //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module ddr3_afifo
#(
parameter ADDR_WIDTH = 30,
parameter DATA_WIDTH = 32
)
(
input i_sys_clk,
input i_ddr_clk,
// Write-Side Ports
input i_cmd_en, // Command Enable
input [2:0] i_cmd_instr, // write = 000, read = 001
input [ADDR_WIDTH-1:0] i_cmd_byte_addr, // Memory address
output o_cmd_full, // DDR3 I/F Command FIFO is full
output o_wr_full, // DDR3 I/F Write Data FIFO is full
input i_wr_en, // Write data enable
input [DATA_WIDTH/8-1:0] i_wr_mask, // 1 bit per byte
input [DATA_WIDTH-1:0] i_wr_data, // 16 bytes write data
input [1:0] i_wr_addr_32, // address bits [3:2]
output [DATA_WIDTH-1:0] o_rd_data, // 16 bytes of read data
output o_rd_valid, // low when read data is valid
// Read-Side Ports
output o_ddr_cmd_en, // Command Enable
output [2:0] o_ddr_cmd_instr, // write = 000, read = 001
output [ADDR_WIDTH-1:0] o_ddr_cmd_byte_addr, // Memory address
input i_ddr_cmd_full, // DDR3 I/F Command FIFO is full
input i_ddr_wr_full, // DDR3 I/F Write Data FIFO is full
output o_ddr_wr_en, // Write data enable
output [DATA_WIDTH/8-1:0] o_ddr_wr_mask, // 1 bit per byte
output [DATA_WIDTH-1:0] o_ddr_wr_data, // 16 bytes write data
output [1:0] o_ddr_wr_addr_32, // address bits [3:2]
input [DATA_WIDTH-1:0] i_ddr_rd_data, // 16 bytes of read data
input i_ddr_rd_valid // low when read data is valid
);
wire cmd_empty, wr_empty, rd_empty;
assign o_ddr_cmd_en = !cmd_empty;
assign o_ddr_wr_en = !wr_empty;
assign o_rd_valid = !rd_empty;
afifo #(.D_WIDTH(ADDR_WIDTH+3)) u_afifo_cmd (
.wr_clk ( i_sys_clk ),
.rd_clk ( i_ddr_clk ),
.i_data ( {i_cmd_instr, i_cmd_byte_addr} ),
.o_data ( {o_ddr_cmd_instr, o_ddr_cmd_byte_addr} ),
.i_push ( i_cmd_en ),
.i_pop ( o_ddr_cmd_en && !i_ddr_cmd_full ),
.o_full ( o_cmd_full ),
.o_empty ( cmd_empty )
);
afifo #(.D_WIDTH(DATA_WIDTH+DATA_WIDTH/8+2)) u_afifo_wr (
.wr_clk ( i_sys_clk ),
.rd_clk ( i_ddr_clk ),
.i_data ( {i_wr_addr_32, i_wr_mask, i_wr_data } ),
.o_data ( {o_ddr_wr_addr_32, o_ddr_wr_mask, o_ddr_wr_data} ),
.i_push ( i_wr_en ),
.i_pop ( o_ddr_wr_en && !i_ddr_wr_full ),
.o_full ( o_wr_full ),
.o_empty ( wr_empty )
);
afifo #(.D_WIDTH(DATA_WIDTH)) u_afifo_rd (
.wr_clk ( i_ddr_clk ),
.rd_clk ( i_sys_clk ),
.i_data ( i_ddr_rd_data ),
.o_data ( o_rd_data ),
.i_push ( i_ddr_rd_valid ),
.i_pop ( o_rd_valid ),
.o_full ( ),
.o_empty ( rd_empty )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int q; int n; int nav[200005], pos[200005]; int main() { scanf( %d , &q); while (q--) { int men = 999999, lar = 999999; scanf( %d , &n); int a; for (int i = 0; i < n; i++) { scanf( %d , &a); if (nav[a] == 0) nav[a] = 1, pos[a] = i; if (nav[a] == 1) lar = i - pos[a], pos[a] = i; if (lar < men && lar != 0) men = lar; } printf( %d n , men == 999999 ? -1 : men + 1); for (int i = 0; i < 200001; i++) nav[i] = pos[i] = 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2 * 1e5; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } int a[N]; int n; int dfs(int h, int w, int s) { if (s > n) return h; int sum = 0; for (int i = s; i <= n; i++) { if (a[i] > a[i + 1]) sum++; if (sum == w) return dfs(h + 1, i - s + 1, i + 1); } return h + 1; } int main() { int T; T = read(); while (T--) { n = read(); for (int i = 1; i <= n; i++) a[i] = read(); printf( %d n , dfs(1, 1, 2) - 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, p, a[100005], fqn[100005], fqo[100005], mx, cur, exc = 0, lesdan = 0, mnvl[100005], gmod = 0, rekt = 0; int mc[100005], vl[100005]; vector<int> ok; map<int, int> fq; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> p; for (int i = 0; i < n; i++) { cin >> a[i]; fq[a[i]]++; } sort(a, a + n + 1, greater<int>()); mx = a[0]; cur = max(mx - (n - 1), 0); for (auto u : fq) if (u.second >= p) exc++; for (int i = 0; i < n; i++) { if (a[i] < cur) break; rekt = i; vl[i] = n - (a[i] - cur) - i; mnvl[i] = vl[i]; if (i != 0) mnvl[i] = min(mnvl[i], mnvl[i - 1]); mc[((vl[i] % p) + p) % p]++; } int gp = n - 1 - rekt; int cnt = 0; while (cur < mx) { while (a[rekt] < cur) { mc[((vl[rekt] % p) + p) % p]--; rekt--; gp++; } if (mnvl[rekt] + cnt > 0 && (mc[gmod] + gp / p) == 0) ok.push_back(cur); cur++; gmod--; gmod += p; gmod %= p; cnt++; } cout << ok.size() << endl; for (auto u : ok) cout << u << ; cout << endl; cout.flush(); return 0; } |
#include <bits/stdc++.h> using namespace std; int p[1001][1001], row[1001], col[1001]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int r = 1; r <= n; ++r) row[r] = r; for (int c = 1; c <= m; ++c) col[c] = c; for (int r = 1; r <= n; ++r) for (int c = 1; c <= m; ++c) scanf( %d , &p[r][c]); while (k--) { char s[2]; int x, y; scanf( %s%d%d , s, &x, &y); switch (s[0]) { case r : swap(row[x], row[y]); break; case c : swap(col[x], col[y]); break; case g : printf( %d n , p[row[x]][col[y]]); break; default: break; } } return 0; } |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mem (
address,
clock,
data,
wren,
q);
input [12:0] address;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "mem"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; bool check = false; string s; int maxi, n, i, j, a; int main() { cin >> n; vector<int> v; for (i = 0; i < n; i++) { maxi = 0; for (j = 0; j < n; j++) { cin >> a; maxi = max(maxi, a); } if (check == false && maxi == n - 1) { maxi = n; check = true; } v.push_back(maxi); } for (i = 0; i < v.size(); i++) { cout << v[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-10; template <typename T, typename S> vector<T>& operator<<(vector<T>& a, S b) { a.push_back(b); return a; } template <typename T> void operator>>(vector<T>& a, int b) { while (b--) if (!a.empty()) a.pop_back(); } bool isprime(int n) { if (n < 2) return false; for (int i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } long long b_pow(long long x, long long n) { return n ? b_pow(x * x, n / 2) * (n % 2 ? x : 1) : 1ll; } string itos(int n) { stringstream ss; ss << n; return ss.str(); } vector<vector<int> > DBG; vector<set<int> > SET; int where[(200010)]; int idx[(200010)]; int box_size[(200010)]; map<int, pair<int, int> > reg; int main() { ios_base::sync_with_stdio(false); int n, m, h; cin >> h >> m >> n; for (int i = 0; i < h; i++) where[i] = -1; for (int i = 0; i < h; i++) { if (where[i] == -1) { DBG.push_back(vector<int>(0)); int x = i; int size = 0; SET.push_back(set<int>()); while (where[x] == -1) { size++; where[x] = SET.size() - 1; idx[x] = size; SET.back().insert(size); DBG.back().push_back(x); x = (x + m) % h; } box_size[SET.size() - 1] = size; } } long long ans = 0; for (int i = 0; i < n; i++) { char c; int a, b; cin >> c; if (c == + ) { cin >> a >> b; int w = where[b]; int p = idx[b]; set<int>& my = SET[w]; set<int>::iterator it = my.lower_bound(p); if (it == my.end()) { ans += box_size[w] - p; set<int>::iterator it2 = my.lower_bound(0); ans += *(it2); reg[a] = make_pair(w, *it2); my.erase(*it2); } else { ans += (*it) - p; reg[a] = make_pair(w, *it); my.erase(*it); } } else { cin >> a; int w = reg[a].first; int p = reg[a].second; SET[w].insert(p); } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 111111; int last[3 * N], pre[3 * N], v[3 * N], cnt[3 * N], cur = 0; inline void add(int a, int b) { pre[cur] = last[a]; v[cur] = b; last[a] = cur; cur++; } set<int>* who[N]; inline set<int>* merge(set<int>*& a, set<int>*& b) { if (a->size() < b->size()) { return merge(b, a); } else { for (set<int>::iterator it = b->begin(); it != b->end(); it++) { if (a->find(-*it) != a->end()) { a->erase(-*it); } else { a->insert(*it); } } b->clear(); return a; } } int used[N]; void dfs(int u) { used[u] = true; for (int i = last[u]; i >= 0; i = pre[i]) if (!used[v[i]]) { dfs(v[i]); cnt[i ^ 1] = cnt[i] = who[v[i]]->size(); who[u] = merge(who[u], who[v[i]]); } } set<int>* mem[N]; int main() { memset(last, -1, sizeof(last)); int n; scanf( %d , &n); for (int i = (0); i <= ((n - 1) - 1); i++) { int u, v; scanf( %d%d , &u, &v); u--; v--; add(u, v); add(v, u); } for (int i = (0); i <= ((n)-1); i++) mem[i] = who[i] = new set<int>(); int k; scanf( %d , &k); for (int i = (1); i <= ((k)); i++) { int u, v; scanf( %d%d , &u, &v); u--; v--; if (u != v) { who[u]->insert(i); who[v]->insert(-i); } } dfs(0); for (int i = 0; i < cur; i += 2) { if (i) printf( ); printf( %d , cnt[i]); } puts( ); for (int i = (0); i <= ((n)-1); i++) delete (mem[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_1_V
`define SKY130_FD_SC_HS__A41OI_1_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_1_V
|
// Top-level processor module
module processor(
input clk,
input pc_reset,
input pc_enable,
input [31:0] instr,
input [31:0] data_out,
output wire[31:0] data_in,
output wire[31:0] inst_addr,
output wire[31:0] data_addr,
output wire mem_read_ctrlsig,
output wire mem_write_ctrlsig
);
// Wire instantiations for port connections between modules
wire [31:0] pc_in;
wire [31:0] pc_out;
wire [31:0] readData1;
wire [31:0] readData2;
wire [31:0] sign_ext_out;
wire [4:0] reg_dst_out;
wire [31:0] alu_src_out;
wire [31:0] mem_to_reg_out;
wire [31:0] branch_out;
wire [31:0] add0_in1;
wire [31:0] pc_plus_four;
wire [31:0] adder_result;
wire [31:0] alu_data_output;
wire [31:0] sl32_out;
wire [31:0] jump_addr;
wire [25:0] sl26_in;
wire [27:0] sl26_out;
wire [15:0] sign_ext_in;
wire [5:0] opcode;
wire [5:0] aluctrl_func_op;
wire [4:0]reg_dst_input0;
wire [4:0]reg_dst_input1;
wire [4:0] readReg1;
wire [4:0] readReg2;
wire [4:0] writeReg;
wire [3:0] alu_ctrl;
wire [1:0] alu_op;
wire reg_dst, jump, branch, mem_to_reg, alu_src, reg_write, mux3_sel, zero, ctrl_mem_read, ctrl_mem_write;
assign add0_in1 = 32'd4; // Constant 4 for PC+4
assign jump_addr = {pc_plus_four[31:28], sl26_out[27:0]}; // Jump address contactentation
assign aluctrl_func_op = instr[5:0]; // ALU Control func input
assign mux3_sel = branch & zero; // Set branch address when Branch,Zero == 1
assign readReg1 = instr[25-21];
assign readReg2 = instr[20-16];
assign inst_addr = pc_out;
assign data_in = readData2;
assign data_addr = alu_data_output;
assign writeReg = reg_dst_out;
assign opcode = instr[31:26];
assign sign_ext_in = instr[15:0];
assign sl26_in = instr[25:0];
assign reg_dst_input0 = instr[20:16];
assign reg_dst_input1 = instr[15:11];
pc pc0(
.in(pc_in), //32bit
.clk,
.rst(pc_reset),
.en(pc_enable),
.out(pc_out) //32bit
);
// Moved control up here because mem_write from control feeds
// into mem_write for mem0
Control ctrl0(
.clk,
.opcode(opcode), //6bit
.reg_dst(reg_dst),
.jump(jump),
.branch(branch),
.ctrl_mem_read(mem_read_ctrlsig),
.mem_to_reg(mem_to_reg),
.ctrl_mem_write(mem_write_ctrlsig),
.alu_src(alu_src),
.reg_write(reg_write),
.alu_op(alu_op) //2bit
);
// 32-bit Adder for PC + 4
Adder_32b pc_adder(
.clk,
.input0(pc_out), //32bi
.input1(add0_in1), //32bit
.out(pc_plus_four) //32bit
);
// 32-bit Adder for branch
Adder_32b adder1(
.clk,
.input0(pc_plus_four), //32bit
.input1(sl32_out), //32bit
.out(adder_result) //32bit
);
reg_file registers(
.clk,
.regWrite(reg_write),
.readReg1(readReg1), //5bit
.readReg2(readReg2), //5bit
.writeReg(writeReg), //5bit
.writeData(mem_to_reg_out), //32bit
.readData1(readData1), //32bit
.readData2(readData2) //32bit
);
sign_extender signext0(
.clk,
.in(sign_ext_in), //16bit
.out(sign_ext_out) //32bit
);
Shift_left2_26b sl26(
.clk,
.in(sl26_in), //26bit
.out(sl26_out) //28bit
);
Shift_left2_32b sl32(
.clk,
.in(sign_ext_out), //32bit
.out(sl32_out) //32bit
);
// THIS NEEDS TO BE 5 BIT MUX
Mux2x1_5b Mux_RegDst(
.clk,
.input0(reg_dst_input0), //5bit
.input1(reg_dst_input1), //5bit
.select(reg_dst),
.out(reg_dst_out) //5bit
);
Mux2x1_32b Mux_ALUsrc(
.clk,
.input0(readData2), //32bit
.input1(sign_ext_out), //32bit
.select(alu_src),
.out(alu_src_out) //32bit
);
Mux2x1_32b Mux_MemtoReg(
.clk,
.input0(alu_data_output), //32bit
.input1(data_out), //32bit
.select(mem_to_reg),
.out(mem_to_reg_out) //32bit
);
Mux2x1_32b Mux_Branch(
.clk,
.input0(pc_plus_four), //32bit
.input1(adder_result), //32bit
.select(mux3_sel),
.out(branch_out) //32bit
);
Mux2x1_32b Mux_Jump(
.clk,
.input0(branch_out), //32bit
.input1(jump_addr), //32bit
.select(jump),
.out(pc_in) //32bit
);
alu_control aluctrl(
.clk,
.alu_op, //2bit
.func_op(aluctrl_func_op), //6bit
.alu_control_sig(alu_ctrl) //4bit
);
ALU alu0(
.clk,
.control(alu_ctrl), //4bit
.data_input1(readData1), //32bit
.data_input2(alu_src_out), //32bit
.data_output(alu_data_output), //32bit
.zero
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename P, typename Q> ostream& operator<<(ostream& os, pair<P, Q> p) { os << ( << p.first << , << p.second << ) ; return os; } template <typename P, typename Q> istream& operator>>(istream& is, pair<P, Q>& p) { is >> p.first >> p.second; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T> v) { os << ( ; for (auto& i : v) os << i << , ; os << ) ; return os; } template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& i : v) is >> i; return is; } template <typename T> ostream& operator<<(ostream& os, set<T> s) { os << #{ ; for (auto& i : s) os << i << , ; os << } ; return os; } template <typename K, typename V> ostream& operator<<(ostream& os, map<K, V> m) { os << { ; for (auto& i : m) os << i << , ; os << } ; return os; } template <typename T> inline T setmax(T& a, T b) { return a = std::max(a, b); } template <typename T> inline T setmin(T& a, T b) { return a = std::min(a, b); } template <typename P, typename Q> inline pair<Q, P> reverse(pair<P, Q> p) { return make_pair(p.second, p.first); } using lli = long long int; using ull = unsigned long long; using point = complex<double>; using str = string; template <typename T> using vec = vector<T>; constexpr lli mod = 1e9 + 7; template <typename T> struct SegTree { int n; vector<T> dat; using F = function<T(T, T)>; F fn; T e; SegTree(int n_, T e_, F fn_) { e = e_; fn = fn_; n = 1; while (n < n_) n *= 2; dat.resize(2 * n - 1, e); } void update(size_t k, T a) { k += n - 1; dat[k] = a; while (k > 0) { k = (k - 1) / 2; dat[k] = fn(dat[k * 2 + 1], dat[k * 2 + 2]); } return; } T query(size_t a, size_t b) { return query(a, b, 0, 0, n); } T query(size_t a, size_t b, size_t k, size_t l, size_t r) { if (r <= a || b <= l) return e; if (a <= l && r <= b) return dat.at(k); T vl = query(a, b, k * 2 + 1, l, (l + r) / 2); T vr = query(a, b, k * 2 + 2, (l + r) / 2, r); return fn(vl, vr); } }; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, k; while (cin >> n >> m >> k) { vector<int> a(k); cin >> a; for (auto& i : a) --i; const int N = 2 * 1e5 + 5; vector<int> g[N]; for (int i = 0; i < m; ++i) { int x, y; cin >> x >> y; --x; --y; g[x].push_back(y); g[y].push_back(x); } const int inf = 1 << 29; auto bfs = [&](int src) { vector<int> cost(n, inf); queue<int> q; cost[src] = 0; for (q.push(src); q.size(); q.pop()) { int curr = q.front(); for (auto& next : g[curr]) { if (cost[next] == inf) { cost[next] = cost[curr] + 1; q.push(next); } } } return cost; }; vector<int> d1 = bfs(0); vector<int> d2 = bfs(n - 1); sort(a.begin(), a.end(), [&](int i, int j) { return d1[i] < d1[j]; }); SegTree<int> rmq(a.size(), -(1 << 29), [](int a, int b) { return max(a, b); }); for (int i = 0; i < a.size(); ++i) { rmq.update(i, d2[a[i]]); } int mx = 0; for (int i = 0; i < a.size(); ++i) { int x = rmq.query(i + 1, a.size()); setmax(mx, d1[a[i]] + x + 1); } cout << min(mx, d1[n - 1]) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std; const long double PI = acos(-1.0); long long diff[200010]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); ; int T, j, t, i, buckN = 1; int N = 1; scanf( %d , &T); long long sum = 0, a, x, lE = 0; while (T--) { scanf( %d , &t); if (t == 1) { scanf( %lld%lld , &a, &x); sum += a * x; diff[a] -= x; if (a == N) { diff[a] += x; lE += x; } } else if (t == 2) { scanf( %lld , &a); diff[N] = a - lE; lE = a; N++; sum += a; } else { sum -= lE; --N; lE -= diff[N]; diff[N] = 0; } printf( %.10f n , (1.0 * sum) / N); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long num[200000]; int sn = 0, asn = 0, save[200000], as[200000], m, n; struct str { int v, x; long long l, c; } str[200000]; void pre1() { scanf( %d , &m); int i, j; for (i = 0; i < m; i++) { scanf( %I64d , &str[i].v); if (str[i].v == 1) { scanf( %I64d , &str[i].x); } else scanf( %I64d%I64d , &str[i].l, &str[i].c); } scanf( %d , &n); for (j = 0; j < n; j++) scanf( %I64d , &num[j]); } void table() { int i, k, j; for (i = 0; i < m; i++) { if (str[i].v == 1) { save[sn++] = str[i].x; if (sn == 100000) return; } else { for (k = 0; k < str[i].c; k++) { for (j = 0; j < str[i].l; j++) { save[sn++] = save[j]; if (sn == 100000) return; } } } } } void work1() { table(); int j = 0, i = 0; long long now = 0; while (i < n) { while (j < m) { if (str[j].v == 1) { now++; if (now == num[i]) { as[asn++] = str[j].x; i++; if (i >= n) return; j++; break; } j++; } else { long long nn = now; now += str[j].l * str[j].c; if (now >= num[i]) { while (i < n) { if (num[i] <= now) { as[asn++] = save[(num[i++] - nn - 1) % str[j].l % 100000]; if (i >= n) return; } else { j++; break; } } } else { j++; } } } } } int main() { pre1(); work1(); for (int i = 0; i < asn - 1; i++) printf( %d , as[i]); printf( %d n , as[asn - 1]); return 0; } |
//----------------------------------------------------------------------------
//-- Unidad de transmision serie asincrona
//------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//--- Modulo de transmision serie
//--- La salida tx ESTA REGISTRADA
module uart_tx
#(
parameter BAUD = `B115200
)
(
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire rstn, //-- Reset global (activo nivel bajo)
input wire start, //-- Activar a 1 para transmitir
input wire [7:0] data, //-- Byte a transmitir
output reg tx, //-- Salida de datos serie (hacia el PC)
output wire ready //-- Transmisor listo / ocupado
);
//-- Señal de start registrada
reg start_r;
//-- Reloj para la transmision
wire clk_baud;
//-- Bitcounter
reg [3:0] bitc;
//-- Datos registrados
reg [7:0] data_r;
//--------- Microordenes
wire load; //-- Carga del registro de desplazamiento. Puesta a 0 del
//-- contador de bits
wire baud_en; //-- Habilitar el generador de baudios para la transmision
//-------------------------------------
//-- RUTA DE DATOS
//-------------------------------------
//-- Registrar la entrada start
//-- (para cumplir con las reglas de diseño sincrono)
always @(posedge clk)
start_r <= start;
always @(posedge clk)
if (start == 1 && state == IDLE)
data_r <= data;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Cuando la microorden load es 1 se carga la trama
//-- con load 0 se desplaza a la derecha y se envia un bit, al
//-- activarse la señal de clk_baud que marca el tiempo de bit
//-- Se introducen 1s por la izquierda
always @(posedge clk)
//-- Reset
if (rstn == 0)
shifter <= 10'b11_1111_1111;
//-- Modo carga
else if (load == 1)
shifter <= {data_r,2'b01};
//-- Modo desplazamiento
else if (load == 0 && clk_baud == 1)
shifter <= {1'b1, shifter[9:1]};
//-- Contador de bits enviados
//-- Con la microorden load (=1) se hace un reset del contador
//-- con load = 0 se realiza la cuenta de los bits, al activarse
//-- clk_baud, que indica el tiempo de bit
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono
//-- y hay que evitar que salgan pulsos espureos (glitches)
always @(posedge clk)
tx <= shifter[0];
//-- Divisor para obtener el reloj de transmision
baudgen #(.BAUD(BAUD))
BAUD0 (
.clk(clk),
.clk_ena(baud_en),
.clk_out(clk_baud)
);
//------------------------------
//-- CONTROLADOR
//------------------------------
//-- Estados del automata finito del controlador
localparam IDLE = 0; //-- Estado de reposo
localparam START = 1; //-- Comienzo de transmision
localparam TRANS = 2; //-- Estado: transmitiendo dato
//-- Estados del autómata del controlador
reg [1:0] state;
//-- Transiciones entre los estados
always @(posedge clk)
//-- Reset del automata. Al estado inicial
if (rstn == 0)
state <= IDLE;
else
//-- Transiciones a los siguientes estados
case (state)
//-- Estado de reposo. Se sale cuando la señal
//-- de start se pone a 1
IDLE:
if (start_r == 1)
state <= START;
else
state <= IDLE;
//-- Estado de comienzo. Prepararse para empezar
//-- a transmitir. Duracion: 1 ciclo de reloj
START:
state <= TRANS;
//-- Transmitiendo. Se esta en este estado hasta
//-- que se hayan transmitido todos los bits pendientes
TRANS:
if (bitc == 11)
state <= IDLE;
else
state <= TRANS;
//-- Por defecto. NO USADO. Puesto para
//-- cubrir todos los casos y que no se generen latches
default:
state <= IDLE;
endcase
//-- Generacion de las microordenes
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
//-- Señal de salida. Esta a 1 cuando estamos en reposo (listos
//-- para transmitir). En caso contrario esta a 0
assign ready = (state == IDLE) ? 1 : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long int t = 1; while (t--) { long long int k, b, n; cin >> k >> b >> n; long long int s = 0; long long int a[n]; map<long long int, vector<long long int> > mp; mp[0].push_back(-1); for (long long int i = 0; i < n; i++) { cin >> a[i]; s = s + a[i]; s = s % (k - 1); mp[s].push_back(i); } long long int an = 0; if (b == k - 1 || b == 0) { map<long long int, long long int> mp; mp[0]++; long long int an = 0, z = 0, ts = 0; for (long long int i = 0; i < n; i++) { ts = (ts + a[i]) % (k - 1); if (a[i] == 0) z++; else z = 0; long long int tmp = (ts + (k - 1) - b) % (k - 1); if (b == 0) an += z; else an = an + mp[tmp] - z; mp[ts]++; } cout << an; } else { for (auto x : mp) { long long int y = x.first; y = (y + b) % (k - 1); for (long long int i = 0; i < x.second.size(); i++) { long long int l = lower_bound(mp[y].begin(), mp[y].end(), x.second[i]) - mp[y].begin(); an = an + max(0ll, (long long int)(mp[y].size() - l)); } } cout << an; } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read(void) { int x = 0; char c = getchar(); while (c > 9 || c < 0 ) c = getchar(); while (c >= 0 && c <= 9 ) x = x * 10 + (c - 0 ), c = getchar(); return x; } const int N = 150010, M = 300010; int n, m, c; int loc[N], p[N]; struct xint { double max_left, max_right, sum, res; xint() {} xint(double A) : max_left(A), max_right(A), sum(A), res(A) {} inline void print(void) { printf( %.2lf %.2lf %.2lf %.2lf n , sum, max_left, max_right, res); puts( ); } } tr[N * 5]; xint update(xint lc, xint rc) { xint k; k.sum = lc.sum + rc.sum; k.max_left = max(lc.max_left, lc.sum + rc.max_left); k.max_right = max(rc.max_right, lc.max_right + rc.sum); k.res = max(lc.res, rc.res); k.res = max(k.res, lc.max_right + rc.max_left); return k; } void build(int k, int l, int r) { if (l == r) { double P = (double)p[l] / 100.0; double tmp = (double)(loc[l + 1] - loc[l]) / 2 - P * c; tr[k] = xint(tmp); return; } int mid = (l + r) >> 1; int lc = k << 1, rc = k << 1 | 1; build(lc, l, mid); build(rc, mid + 1, r); tr[k] = update(tr[lc], tr[rc]); } xint query(int k, int l, int r, int x, int y) { if (x <= l && r <= y) return tr[k]; if (l > r) return 0; int mid = (l + r) >> 1; int lc = k << 1, rc = k << 1 | 1; if (y <= mid) return query(lc, l, mid, x, y); if (x > mid) return query(rc, mid + 1, r, x, y); xint tmp1 = query(lc, l, mid, x, y); xint tmp2 = query(rc, mid + 1, r, x, y); return update(tmp1, tmp2); } int main(void) { n = read(), m = read(), c = read(); for (int i = 1; i <= n; ++i) loc[i] = read(); for (int i = 1; i < n; ++i) p[i] = read(); build(1, 1, n - 1); double ans = 0; for (int i = 1; i <= m; ++i) { int l = read(), r = read(); xint tmp = query(1, 1, n - 1, l, r - 1); ans += max(tmp.res, 0.0); } printf( %.8lf n , ans); return 0; } |
module testbench;
// localparam test_early_yumi_lp = 1;
localparam test_early_yumi_lp = 1;
`include "test_bsg_clock_params.v"
localparam cycle_time_lp = 20;
wire clk;
wire reset;
localparam width_lp = 16;
localparam els_lp = 4;
bsg_nonsynth_clock_gen #(.cycle_time_p(cycle_time_lp)) clock_gen
(.o(clk));
bsg_nonsynth_reset_gen #(.reset_cycles_lo_p(5)
,.reset_cycles_hi_p(5)
) reset_gen
(.clk_i(clk)
,.async_reset_o(reset)
);
logic [width_lp-1:0] test_data_in, test_data_out, test_data_check;
wire test_valid_in, test_valid_out, test_ready_out, test_ready_in;
logic [31:0] ctr;
bsg_cycle_counter counter (.clk_i(clk)
,.reset_i(reset)
,.ctr_r_o(ctr)
);
// *******************************************************
// ** generate pattern of valids
localparam pattern_width_lp = 20;
wire [$clog2(pattern_width_lp)-1:0] pattern_bit;
logic [pattern_width_lp-1:0] test_pattern, test_pattern_r;
bsg_circular_ptr #(.slots_p(1 << pattern_width_lp)
,.max_add_p(1)
) seq
(.clk(clk)
,.reset_i(reset)
,.add_i (pattern_bit == (pattern_width_lp-1))
,.o (test_pattern)
);
// cycles through each bit of the battern
bsg_circular_ptr #(.slots_p(pattern_width_lp)
,.max_add_p(1)
) sequ
(.clk(clk)
,.reset_i(reset)
,.add_i (1'b1)
,.o (pattern_bit)
);
assign test_valid_in = test_pattern[pattern_bit];
// our readies will be reflected and inverted
assign test_ready_in = ~test_pattern[pattern_width_lp-pattern_bit-1];
// end generate pattern of valids
// *******************************************************
// *******************************************************
// generate data
bsg_circular_ptr #(.slots_p(1 << width_lp)
,.max_add_p(1)
) gen
(.clk(clk)
,.reset_i(reset)
,.add_i (test_valid_in & test_ready_out)
,.o (test_data_in)
);
// end generate data
// *******************************************************
localparam verbose_lp=0;
localparam fifo_verbose_lp=0;
always @(posedge clk)
begin
if (test_valid_in & test_ready_out & verbose_lp)
$display("### %x sent %x (1rw r=%x w=%x f=%x e=%x) bypass_mode=%x storage=%d",ctr, test_data_in
, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr, fifo.big1p.fifo_full, fifo.big1p.fifo_empty
, fifo.bypass_mode, fifo.num_elements_debug);
end
wire test_yumi_in = test_ready_in & test_valid_out;
bsg_fifo_1r1w_pseudo_large #(.width_p (width_lp )
,.els_p (els_lp )
,.early_yumi_p(test_early_yumi_lp)
,.verbose_p (fifo_verbose_lp )
) fifo
(.clk_i(clk)
,.reset_i(reset )
,.data_i (test_data_in)
,.v_i (test_valid_in)
,.ready_o(test_ready_out)
,.v_o (test_valid_out)
,.data_o (test_data_out)
,.yumi_i (test_yumi_in) // recycle
);
bsg_circular_ptr #(.slots_p (1 << width_lp)
,.max_add_p(1)
) check
(.clk(clk)
,.reset_i(reset)
,.add_i (test_yumi_in)
,.o (test_data_check)
);
always_ff @(posedge clk)
begin
test_pattern_r <= test_pattern;
if (test_yumi_in & ~(|test_pattern) & (&test_pattern_r))
$finish();
end
always @(negedge clk)
begin
assert (reset | ((test_yumi_in !== 1'b1) | (test_data_check == test_data_out)))
else
begin
$error("### %x mismatched value v=%x y=%x ch=%x da=%x reset=%x",ctr,test_valid_out, test_yumi_in, test_data_check, test_data_out, reset);
$finish;
end
if (~reset & test_yumi_in === 1'b1)
if (verbose_lp | ((test_data_out & 16'hffff) == 0))
begin
$display("### %x received %x (1rw r=%x w=%x f=%x e=%x) pattern=%b storage=%d"
, ctr, test_data_out
, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr, fifo.big1p.fifo_full, fifo.big1p.fifo_empty
, test_pattern, fifo.num_elements_debug);
end
if (verbose_lp | 1)
if (fifo.num_elements_debug > els_lp+2)
$display("### storing > %d els!\n", fifo.num_elements_debug);
// IMPORTANT TEST: test that the fifo will never register full with less than els_lp
// elements actually stored.
if (~test_ready_out & test_valid_in)
if (fifo.num_elements_debug < els_lp)
begin
$display("### %x FAIL BAD FULL %x (1rw r=%x w=%x f=%x e=%x) pattern=%b storage=%d"
, ctr, test_data_out, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr
, fifo.big1p.fifo_full, fifo.big1p.fifo_empty, test_pattern, fifo.num_elements_debug);
$finish;
end
// IMPORTANT TEST: test that the fifo will never register empty if there are actually
// elements stored.
//
if (0) // mbt fixme; this check is from the non-pseudo version, what is the equivalent check for pseudo large?
if (~test_valid_out & (fifo.num_elements_debug != 0))
begin
$display("### %x FAIL BAD empty %x (1rw r=%x w=%x f=%x e=%x) pattern=%b storage=%d"
, ctr, test_data_out, fifo.big1p.rd_ptr, fifo.big1p.wr_ptr
, fifo.big1p.fifo_full, fifo.big1p.fifo_empty, test_pattern, fifo.num_elements_debug);
$finish;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_1_V
`define SKY130_FD_SC_LS__A31OI_1_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31oi_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_1_V
|
#include <bits/stdc++.h> using namespace std; char s[100][100]; int di[4][2] = {0, 1, 1, 0, 0, -1, -1, 0}; int v[100][100]; int fst[4] = {1, 0, 1, 0}; int xi[4][2] = {1, 0, 0, 1, 2, 3, 3, 2}; int m, r; struct zb { int z[2]; } po[100][100][4][2]; void gx(int x, int y, int &a, int &b, int xi) { if (xi == 0) { if (x > a || (x == a && y > b)) { a = x; b = y; } } if (xi == 1) { if (x > a || (x == a && y < b)) { a = x; b = y; } } if (xi == 2) { if (x < a || (x == a && y > b)) { a = x; b = y; } } if (xi == 3) { if (x < a || (x == a && y < b)) { a = x; b = y; } } } void dfs(int x, int y, int cx, int cy) { v[cx][cy] = 1; int i, j; for (i = 0; i < 4; i++) for (j = 0; j < 2; j++) { if (fst[i] == 1) gx(cy, cx, po[x][y][i][j].z[1], po[x][y][i][j].z[0], xi[i][j]); else gx(cx, cy, po[x][y][i][j].z[0], po[x][y][i][j].z[1], xi[i][j]); } for (i = 0; i < 4; i++) { int nx, ny; nx = cx + di[i][0]; ny = cy + di[i][1]; if (nx >= 0 && nx < m && ny >= 0 && ny < r && v[nx][ny] == 0 && s[nx][ny] == s[x][y]) dfs(x, y, nx, ny); } } int main() { int n, i, j, k, l, bp, cp, dp, cx, cy; while (scanf( %d%d , &m, &n) == 2) { for (i = 0; i < m; i++) scanf( %s , s[i]); r = strlen(s[0]); for (i = 0; i < m; i++) for (j = 0; j < r; j++) { for (k = 0; k < 4; k++) for (l = 0; l < 2; l++) { po[i][j][k][l].z[0] = i; po[i][j][k][l].z[1] = j; } memset(v, 0, sizeof(v)); if (s[i][j] != 0 ) dfs(i, j, i, j); } cx = 0; cy = 0; cp = 0; dp = 0; while (n--) { int nx, ny; nx = po[cx][cy][cp][dp].z[0]; ny = po[cx][cy][cp][dp].z[1]; cx = nx; cy = ny; i = cp; nx = cx + di[i][0]; ny = cy + di[i][1]; if (nx >= 0 && nx < m && ny >= 0 && ny < r && s[nx][ny] != 0 ) { cx = nx; cy = ny; } else { if (dp == 0) dp = 1; else { dp = 0; cp = (cp + 1) % 4; } } } printf( %c n , s[cx][cy]); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_4_V
`define SKY130_FD_SC_HD__O31AI_4_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o31ai_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_4_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 7; const long long mod = 1e9 + 7; int n; int a; int b; string s; int main() { cin >> n >> a >> b; cin >> s; if (s[b - 1] == s[a - 1]) { cout << 0; return 0; } int x = 1e7, y = 1e7; for (int i = b - 1; i < n; i++) { if (s[i] == s[b - 1]) { x = i; break; } } for (int i = b - 1; i >= 0; i--) { if (s[i] == s[b - 1]) { y = i; break; } } if (b - x < 0) { cout << b - x; } if (b - y < 0) { cout << b - y; } cout << min(b - x, b - y); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_SN_SYMBOL_V
/**
* udp_dlatch$PSa_pp$PKG$sN: Positive level sensitive D-type -latch
* with active low
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_ASYNC ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER_REG,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PSA_PP_PKG_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int64_t N = 1e3 + 3; const int64_t mod = 998244353; int64_t f[N][2][2][2 * N]; int64_t more(int64_t x, int64_t y, int64_t u, int64_t v) { if (x == y) { if (u != x || v != y) return 1; return 0; } if (u != x && v != y) return 2; return 0; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int64_t n, k; cin >> n >> k; f[1][0][1][2] = 1; f[1][0][0][1] = 1; f[1][1][1][1] = 1; f[1][1][0][2] = 1; for (int64_t i = 1; i < n; i++) for (int64_t x = 0; x < 2; x++) for (int64_t y = 0; y < 2; y++) for (int64_t c = 1; c <= 2 * i; c++) { for (int64_t nx = 0; nx < 2; nx++) for (int64_t ny = 0; ny < 2; ny++) { int64_t _c = c + more(x, y, nx, ny); (f[i + 1][nx][ny][_c] += f[i][x][y][c]) %= mod; } } cout << (f[n][0][0][k] + f[n][0][1][k] + f[n][1][0][k] + f[n][1][1][k]) % mod; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_TB_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_TB_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlymetal6s4s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__dlymetal6s4s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_TB_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> void print(vector<T> v) { for (T e : v) { cout << e << ; } cout << endl; } template <typename T> void print(vector<vector<T>> v) { int n = v.size(); for (int i = 0; i < n; i++) { cout << i << : ; for (T e : v[i]) { cout << e << ; } cout << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); vector<int> a(6); for (int i = 0; i < 6; i++) { cin >> a[i]; } cout << (int)(pow(a[0] + a[1] + a[2], 2) - a[0] * a[0] - a[2] * a[2] - a[4] * a[4]) << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2200, MAX_K = 2200, INDEX = 1; int n, k, a[MAX_N + INDEX], books[MAX_K + INDEX]; int ans = 0; bool isBook(int x) { for (int i = 1; i <= k; i++) { if (books[i] == x) { return true; } } return false; } int dist(int book, int x) { for (int i = 1; x + i <= n; i++) { if (a[x + i] == book) { return i; } } return n + 1; } int getBest(int x) { int best = 1; for (int i = 2; i <= k; i++) { if (dist(books[i], x) > dist(books[best], x)) { best = i; } } return best; } int main() { ios_base::sync_with_stdio(false); cin.tie(); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { if (!isBook((a[i]))) { books[getBest(i)] = a[i]; ans++; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; string solve() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; if (n % 2 == 0) return YES ; for (int i = 0; i < n - 1; i++) if (a[i] >= a[i + 1]) return YES ; return NO ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t = 1; cin >> t; while (t--) { cout << solve() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; map<int, int> used; int ans = 0; for (int i = n - 1; i >= 0; --i) { if (used[a[i]] == 0) { used[a[i]] = i; ans = a[i]; } } cout << ans; return 0; } |
// AXI Slave Model
module tb_axi_slave_model
(
// Reset, Clock
input ARESETN,
input ACLK,
// Master Write Address
input [0:0] M_AXI_AWID,
input [31:0] M_AXI_AWADDR,
input [7:0] M_AXI_AWLEN,
input [2:0] M_AXI_AWSIZE,
input [1:0] M_AXI_AWBURST,
input M_AXI_AWLOCK,
input [3:0] M_AXI_AWCACHE,
input [2:0] M_AXI_AWPROT,
input [3:0] M_AXI_AWQOS,
input [0:0] M_AXI_AWUSER,
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
// Master Write Data
input [31:0] M_AXI_WDATA,
input [3:0] M_AXI_WSTRB,
input M_AXI_WLAST,
input [0:0] M_AXI_WUSER,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
// Master Write Response
output reg [0:0] M_AXI_BID,
output reg [1:0] M_AXI_BRESP,
output reg [0:0] M_AXI_BUSER,
output M_AXI_BVALID,
input M_AXI_BREADY,
// Master Read Address
input [0:0] M_AXI_ARID,
input [31:0] M_AXI_ARADDR,
input [7:0] M_AXI_ARLEN,
input [2:0] M_AXI_ARSIZE,
input [1:0] M_AXI_ARBURST,
// input [1:0] M_AXI_ARLOCK,
input [0:0] M_AXI_ARLOCK,
input [3:0] M_AXI_ARCACHE,
input [2:0] M_AXI_ARPROT,
input [3:0] M_AXI_ARQOS,
input [0:0] M_AXI_ARUSER,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
// Master Read Data
output reg [0:0] M_AXI_RID,
output [31:0] M_AXI_RDATA,
output reg [1:0] M_AXI_RRESP,
output M_AXI_RLAST,
output reg [0:0] M_AXI_RUSER,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BID = 0;
M_AXI_BRESP = 0;
M_AXI_BUSER = 0;
//M_AXI_BVALID = 0;
M_AXI_ARREADY = 1;
M_AXI_RID = 0;
//M_AXI_RDATA = 0;
M_AXI_RRESP = 0;
//M_AXI_RLAST = 0;
M_AXI_RUSER = 0;
//M_AXI_RVALID = 0;
end
// AXI Read
reg axi_rena;
reg [31:0] count,rcount;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if(!ARESETN) begin
count <= 32'd0;
rcount <= 32'd0;
axi_rena <= 0;
axi_length <= 0;
// M_AXI_RVALID<=1'b0;
end else begin
if(M_AXI_RLAST) begin
axi_rena <= 0;
end else if(M_AXI_ARVALID) begin
axi_rena <= 1;
axi_length <= M_AXI_ARLEN;
end
if(axi_rena) begin
if(M_AXI_RREADY) begin
count <= count + 32'd1;
end
end else begin
count <= 0;
end
if(M_AXI_RVALID & M_AXI_RREADY) begin
rcount <= rcount + 32'd1;
end
end
end
assign M_AXI_RDATA = {rcount};
assign M_AXI_RLAST = (axi_rena & (axi_length == count))?1:0;
assign M_AXI_RVALID = axi_rena & M_AXI_RREADY;
// AXI BResponse
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN)begin
if(!ARESETN) begin
axi_wvalid <= 0;
end else begin
if(M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID & M_AXI_WLAST) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int z[N], t1[N], t2[N]; string s; vector<pair<int, int> > ans; int n; void BuildZArray() { int L = 0, R = 0; for (int i = 1; i < n; i++) { if (i > R) { L = R = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } else { int k = i - L; if (z[k] < R - i + 1) z[i] = z[k]; else { L = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> s; n = s.size(); BuildZArray(); for (int i = 0; i < n; i++) { t1[z[i]]++; } t1[n]++; for (int i = N - 1; i >= 0; i--) { t2[i] = t1[i] + t2[i + 1]; } for (int i = 0; i < n; i++) if (z[i] >= n - i) ans.push_back(pair<int, int>(z[i], t2[z[i]])); ans.push_back(pair<int, int>(n, 1)); sort(ans.begin(), ans.end()); cout << ans.size() << n ; for (auto it : ans) cout << it.first << << it.second << n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/14/2015 05:20:43 PM
// Design Name:
// Module Name: Problem4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem4(
input A,
input B,
input C,
input D,
input E,
output X
);
assign X = (~A & ~B & ~C & D & ~E) | (~A & ~B & ~C & D & E) | (~A & ~B & C & ~D & E) | (~A & ~B & C & D & E) | (~A & B & ~C & ~D & E) | (~A & B & ~C & D & E) | (~A & B & C & ~D & E) | (A & ~B & ~C & ~D & E) |(A & ~B & ~C & D & E) | (A & ~B & C & D & E) | (A & B & C & ~D & E) | (A & B & C & D & E);
// 00010 00011 00101 00111 01001 01011 01101 10001 10011 10111 11101 11111
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_4_V
`define SKY130_FD_SC_MS__AND4BB_4_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_TB_V
`define SKY130_FD_SC_HDLL__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_TB_V
`define SKY130_FD_SC_HD__O21A_TB_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_TB_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 102400; long long n, ans, c00, c01, c10, c11; string a, b; int main() { cin >> n >> a >> b; for (int i = 0; i < n; i++) { if (a[i] == 0 && b[i] == 0 ) c00++; else if (a[i] == 0 && b[i] == 1 ) c01++; else if (a[i] == 1 && b[i] == 0 ) c10++; else if (a[i] == 1 && b[i] == 1 ) c11++; } for (int i = 0; i < n; i++) { if (a[i] == 0 && b[i] == 0 ) ans += (c10 + c11); else if (a[i] == 0 && b[i] == 1 ) ans += c10; else if (a[i] == 1 && b[i] == 0 ) ans += (c00 + c01); else if (a[i] == 1 && b[i] == 1 ) ans += c00; } cout << ans / 2 << endl; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-8; const int T = 23; inline double sqr(double x) { return x * x; } inline int dcmp(double x) { return fabs(x) <= eps ? 0 : (x > 0 ? 1 : -1); } int n; double r, v, s, t; bool check(double x) { double len = x; int tmp = (int)(x / (2.0 * pi * r)); x -= 2.0 * pi * r * tmp; double delta = x / r; len -= (t - s); len /= r; double y = sqrt(sqr(1 - cos(delta)) + sqr(sin(delta))); len /= y; double a = acos(len) - acos((1 - cos(delta)) / y); if (a - 2.0 * pi >= 0) a -= 2 * pi; if (a < 0) a += 2.0 * pi; return dcmp(pi - a) >= 0; } int main() { scanf( %d %lf %lf , &n, &r, &v); for (int i = 1; i <= n; i++) { scanf( %lf %lf , &s, &t); double l = 0.0, r = t - s - eps; for (int j = 1; j <= T; j++) { double mid = (l + r) / 2.0; if (check(mid)) r = mid; else l = mid; } printf( %.9f n , l / v); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); int arr[4]; for (int i = 0; i < 4; i++) cin >> arr[i]; int a, b; cin >> a >> b; sort(arr, arr + 4); if (arr[0] > b) cout << b - a + 1 << endl; else if (arr[0] > a) cout << arr[0] - a << endl; else cout << 0 << endl; return 0; } |
// nrzi_4b5b_decoder.v
`timescale 1 ns / 1 ps
module nrzi_4b5b_decoder
(
input clk80,
input reset,
input enable,
input [4:0]din,
output reg [3:0]dout,
output reg error
);
reg [4:0]d;
reg inv;
always @(posedge clk80 or posedge reset)
begin
if (reset)
begin
d <= 5'b00000;
inv <= 0;
dout <= 4'b1010;
error <= 0;
end
else
begin if (enable)
d <= inv ? din : ~din;
inv <= din[0];
case (d)
5'b01011: {dout,error} <= 5'b0000_0;
5'b10001: {dout,error} <= 5'b0001_0;
5'b00111: {dout,error} <= 5'b0010_0;
5'b00110: {dout,error} <= 5'b0011_0;
5'b10011: {dout,error} <= 5'b0100_0;
5'b10010: {dout,error} <= 5'b0101_0;
5'b10100: {dout,error} <= 5'b0110_0;
5'b10101: {dout,error} <= 5'b0111_0;
5'b00011: {dout,error} <= 5'b1000_0;
5'b00010: {dout,error} <= 5'b1001_0;
5'b00100: {dout,error} <= 5'b1010_0;
5'b00000: {dout,error} <= 5'b1010_0;
5'b00101: {dout,error} <= 5'b1011_0;
5'b01100: {dout,error} <= 5'b1100_0;
5'b01101: {dout,error} <= 5'b1101_0;
5'b01000: {dout,error} <= 5'b1110_0;
5'b01001: {dout,error} <= 5'b1111_0;
default: {dout,error} <= 5'b1010_1;
endcase
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 23:35:06 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_sim_netlist.v
// Design : system_zed_vga_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_zed_vga_0_0,zed_vga,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "zed_vga,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_zed_vga_0_0
(clk,
active,
rgb565,
vga_r,
vga_g,
vga_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input active;
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
wire active;
wire clk;
wire [15:0]rgb565;
wire [3:0]vga_b;
wire [3:0]vga_g;
wire [3:0]vga_r;
system_zed_vga_0_0_zed_vga U0
(.active(active),
.clk(clk),
.rgb565({rgb565[15:12],rgb565[10:7],rgb565[4:1]}),
.vga_b(vga_b),
.vga_g(vga_g),
.vga_r(vga_r));
endmodule
(* ORIG_REF_NAME = "zed_vga" *)
module system_zed_vga_0_0_zed_vga
(vga_r,
vga_g,
vga_b,
rgb565,
clk,
active);
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
input [11:0]rgb565;
input clk;
input active;
wire active;
wire clk;
wire \red[4]_i_1_n_0 ;
wire [11:0]rgb565;
wire [3:0]vga_b;
wire [3:0]vga_g;
wire [3:0]vga_r;
FDRE \blue_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb565[0]),
.Q(vga_b[0]),
.R(\red[4]_i_1_n_0 ));
FDRE \blue_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb565[1]),
.Q(vga_b[1]),
.R(\red[4]_i_1_n_0 ));
FDRE \blue_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb565[2]),
.Q(vga_b[2]),
.R(\red[4]_i_1_n_0 ));
FDRE \blue_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb565[3]),
.Q(vga_b[3]),
.R(\red[4]_i_1_n_0 ));
FDRE \green_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb565[4]),
.Q(vga_g[0]),
.R(\red[4]_i_1_n_0 ));
FDRE \green_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb565[5]),
.Q(vga_g[1]),
.R(\red[4]_i_1_n_0 ));
FDRE \green_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb565[6]),
.Q(vga_g[2]),
.R(\red[4]_i_1_n_0 ));
FDRE \green_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb565[7]),
.Q(vga_g[3]),
.R(\red[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\red[4]_i_1
(.I0(active),
.O(\red[4]_i_1_n_0 ));
FDRE \red_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb565[8]),
.Q(vga_r[0]),
.R(\red[4]_i_1_n_0 ));
FDRE \red_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb565[9]),
.Q(vga_r[1]),
.R(\red[4]_i_1_n_0 ));
FDRE \red_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb565[10]),
.Q(vga_r[2]),
.R(\red[4]_i_1_n_0 ));
FDRE \red_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb565[11]),
.Q(vga_r[3]),
.R(\red[4]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int t[2000002]; int longestPrefix(string &s) { t[0] = 0; for (int pos = 1; pos < s.length(); ++pos) { int prev = t[pos - 1]; while (prev > 0 && s[pos] != s[prev]) { prev = t[prev - 1]; } if (s[pos] == s[prev]) { t[pos] = prev + 1; } else { t[pos] = prev; } } return t[s.length() - 1]; } int main() { int t; cin >> t; while (t-- > 0) { string s; cin >> s; int lindex = 0, rindex = s.length(); while (lindex < rindex && s[lindex] == s[rindex - 1]) { ++lindex; --rindex; } if (lindex >= rindex) { cout << s << endl; continue; } string mid = s.substr(lindex, rindex - lindex); string rmid = mid; reverse(rmid.begin(), rmid.end()); string pre = mid + * + rmid; string suf = rmid + * + mid; int pref = longestPrefix(pre); int suff = longestPrefix(suf); int len = max(pref, suff); for (int i = 0; i < lindex; ++i) { cout << s[i]; } if (pref >= suff) { for (int i = lindex; i < lindex + pref; ++i) { cout << s[i]; } } else { for (int i = rindex - suff; i < rindex; ++i) { cout << s[i]; } } for (int i = rindex; i < s.length(); ++i) { cout << s[i]; } cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_BLACKBOX_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } vector<int> b[200009], r[200009]; vector<pair<int, int> > upd[200009][2]; vector<int> last, now; int blue[200009], red[200009], type = 1, TIM, vis[200009][2]; int bin[200009], bout[200009], rin[200009], rout[200009]; void dfsB(int nd, int pr) { bin[nd] = ++TIM; for (int i = 0; i < int(b[nd].size()); i++) { int to = b[nd][i]; if (to == pr) continue; dfsB(to, nd); } bout[nd] = TIM; } void dfsR(int nd, int pr) { rin[nd] = ++TIM; for (int i = 0; i < int(r[nd].size()); i++) { int to = r[nd][i]; if (to == pr) continue; dfsR(to, nd); } rout[nd] = TIM; } struct Two_Rooted_Tree { vector<pair<int, int> > s[200009 << 2]; int st[200009 << 2], en[200009 << 2]; void merge(int nd) { int p1 = 0, p2 = 0; int s1 = s[nd << 1].size(); int s2 = s[nd << 1 | 1].size(); st[nd] = 0; en[nd] = s1 + s2 - 1; while (p1 + p2 < s1 + s2) { if (p1 >= s1) s[nd].push_back(s[nd << 1 | 1][p2++]); else if (p2 >= s2) s[nd].push_back(s[nd << 1][p1++]); else if (s[nd << 1][p1] <= s[nd << 1 | 1][p2]) s[nd].push_back(s[nd << 1][p1++]); else s[nd].push_back(s[nd << 1 | 1][p2++]); } } void build(int tp, int nd, int x, int y) { s[nd].clear(); if (x == y) { st[nd] = 0; en[nd] = -1; for (__typeof((upd[x][tp]).begin()) it = (upd[x][tp]).begin(); it != (upd[x][tp]).end(); it++) { s[nd].push_back(*it); en[nd]++; } sort(s[nd].begin(), s[nd].end()); return; } int mid = (x + y) >> 1; build(tp, nd << 1, x, mid); build(tp, nd << 1 | 1, mid + 1, y); merge(nd); } void tap(int l, int r, int nd, int x, int y) { if (l > y or x > r) return; if (l <= x and y <= r) { while (st[nd] <= en[nd] and s[nd][st[nd]].first < l) { if (!vis[s[nd][st[nd]].second][type]) { vis[s[nd][st[nd]].second][type] = 1; now.push_back(s[nd][st[nd]].second); } st[nd]++; } while (st[nd] <= en[nd] and s[nd][en[nd]].first > r) { if (!vis[s[nd][en[nd]].second][type]) { vis[s[nd][en[nd]].second][type] = 1; now.push_back(s[nd][en[nd]].second); } en[nd]--; } return; } int mid = (x + y) >> 1; tap(l, r, nd << 1, x, mid); tap(l, r, nd << 1 | 1, mid + 1, y); } } B, R; int main() { int n; scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d , blue + i); b[i + 1].push_back(blue[i]); b[blue[i]].push_back(i + 1); } for (int i = 1; i < n; i++) { scanf( %d , red + i); r[i + 1].push_back(red[i]); r[red[i]].push_back(i + 1); } dfsB(1, -1); TIM = 0; dfsR(1, -1); TIM = 0; for (int i = 1; i <= n; i++) { int u = i + 1; int v = blue[i]; upd[rin[u]][1].push_back(make_pair(rin[v], i)); upd[rin[v]][1].push_back(make_pair(rin[u], i)); } for (int i = 1; i <= n; i++) { int u = i + 1; int v = red[i]; upd[bin[u]][0].push_back(make_pair(bin[v], i)); upd[bin[v]][0].push_back(make_pair(bin[u], i)); } B.build(0, 1, 1, n); R.build(1, 1, 1, n); int ind; scanf( %d , &ind); last.push_back(ind); vis[ind][0] = 1; printf( Blue n%d n , ind); while (1) { for (int i = 0; i < int(last.size()); i++) { if (type) { int u = blue[last[i]]; int v = last[i] + 1; if (bin[v] <= bin[u] and bout[u] <= bout[v]) swap(u, v); if (bin[u] <= bin[v] and bout[v] <= bout[u]) B.tap(bin[v], bout[v], 1, 1, n); } else { int u = red[last[i]]; int v = last[i] + 1; if (rin[v] <= rin[u] and rout[u] <= rout[v]) swap(u, v); if (rin[u] <= rin[v] and rout[v] <= rout[u]) R.tap(rin[v], rout[v], 1, 1, n); } } if (now.size() == 0) break; sort(now.begin(), now.end()); if (type) printf( Red n ); else printf( Blue n ); type = (1 - type); for (__typeof((now).begin()) it = (now).begin(); it != (now).end(); it++) printf( %d , *it); puts( ); swap(last, now); now.clear(); } return 0; } |
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