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* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file data_ram.v when simulating
// the core, data_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module data_ram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [3 : 0] wea;
input [7 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input [3 : 0] web;
input [7 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_1 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( avx ) int V[100000]; float x; int main() { int n, m, l, r, res, type; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &V[i]); while (m--) { scanf( %d%d%d%f , &type, &l, &r, &x); if (type == 1) for (int i = l; i <= r; ++i) V[i] -= V[i] > x ? x : 0; else { res = 0; for (int i = l; i <= r; ++i) V[i] == x ? ++res : 0; printf( %d n , res); } } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2000001; int n, m, x; pair<int, int> a[maxn]; int st[maxn], q[maxn], cnt, ans[maxn], tail, top; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i].first); } int x; for (int i = 1; i <= n; i++) { scanf( %d , &x); a[n + i].first = m - 1 - x; a[n + i].second = 1; } sort(a + 1, a + 1 + 2 * n); top = 0; tail = 0; for (int i = 1; i <= 2 * n; i++) { if (a[i].second == 0) st[++top] = a[i].first; else { if (top == 0) q[++tail] = a[i].first; else ans[++cnt] = (m - 1 - a[i].first + st[top--]) % m; } } for (int i = 1; i <= tail; i++) ans[++cnt] = (st[i] + m - 1 - q[tail - i + 1]) % m; sort(ans + 1, ans + 1 + n); reverse(ans + 1, ans + 1 + n); for (int i = 1; i <= n; i++) printf( %d , ans[i]); cout << endl; fclose(stdin); return 0; } |
#include <bits/stdc++.h> using namespace std; char ch[200000]; int main() { scanf( %s , ch + 1); int n = strlen(ch + 1); int flag = 0; for (int i = 1; i <= n; i++) { if (ch[i] != ch[n - i + 1]) flag++; } if (flag == 2 || n % 2 == 1 && flag == 0) printf( YES ); else printf( NO ); return 0; } |
#include <bits/stdc++.h> int main() { std::string str; std::getline(std::cin, str); int number = 0; for (int j = 0, i = 0; j < str.size(); ++j) { int n = 0; while (j < str.size() && isdigit(str.at(j))) n = n * 10 + str.at(j++) - 48; number = number + n * i++; if (j >= str.size()) break; } std::cout << number << std::endl; } |
#include <bits/stdc++.h> using namespace std; int main() { char c1, c2; int t, n1, n2, ans1, ans2; string s = ^>v< ; cin >> c1 >> c2 >> t; n1 = s.find(c1); n2 = s.find(c2); t = t % 4; ans1 = (n1 + t) % 4; ans2 = (n1 - t); if (ans2 < 0) ans2 += 4; if (ans1 == n2 && ans2 == n2) puts( undefined ); else if (ans1 == n2) puts( cw ); else puts( ccw ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_V |
module regaccess(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output [6:0] regnum,
input [7:0] regdata_read,
output [7:0] regdata_write,
output read,
output write
);
wire done;
wire [7:0] din;
wire [7:0] dout;
reg [6:0] regnum_d, regnum_q;
reg we_d, we_q;
reg ss_d, ss_q;
reg first_d, first_q;
reg read_d, read_q;
reg write_d, write_q;
assign regnum = regnum_q;
assign read = read_q;
assign write = write_q;
assign regdata_write = dout;
assign din = (read_q? regdata_read : 8'b0);
spi_slave reg_spi
(
.clk(clk), .rst(rst),
.ss(ss), .mosi(mosi), .miso(miso), .sck(sck),
.done(done), .din(din), .din_update(read_q), .dout(dout)
);
always @(*) begin
ss_d = ss;
we_d = we_q;
first_d = first_q;
regnum_d = regnum_q;
read_d = 1'b0;
write_d = 1'b0;
if (ss_q) begin
we_d = 1'b0;
first_d = 1'b1;
end else if (done) begin
if (first_q) begin
regnum_d = dout[6:0];
we_d = !dout[7];
read_d = dout[7];
end else if (we_q) begin
write_d = 1'b1;
end else begin
regnum_d = dout[6:0];
read_d = 1'b1;
end
first_d = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
we_q <= 1'b0;
first_q <= 1'b1;
regnum_q <= 6'b0;
read_q <= 1'b0;
write_q <= 1'b0;
end else begin
we_q <= we_d;
first_q <= first_d;
regnum_q <= regnum_d;
read_q <= read_d;
write_q <= write_d;
end
ss_q <= ss_d;
end
endmodule // regaccess
|
#include <bits/stdc++.h> using namespace std; template <class A> void read(vector<A>& v) { for (auto& x : v) cin >> x; } template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cout << *x, 0); template <class c> char dud(...); struct debug { ~debug() { cout << endl; } template <class c> typename enable_if<sizeof dud<c>(0) != 1, debug&>::type operator<<(c i) { cout << boolalpha << i; return *this; } template <class c> typename enable_if<sizeof dud<c>(0) == 1, debug&>::type operator<<(c i) { return *this << range(begin(i), end(i)); } template <class c, class b> debug& operator<<(pair<b, c> d) { return *this << ( << d.first << , << d.second << ) ; } template <class c> debug& operator<<(rge<c> d) { *this << [ ; for (auto it = d.b; it != d.e; ++it) *this << , + 2 * (it == d.b) << *it; return *this << ] ; } }; const long MOD = 1000000007; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); ; int t; cin >> t; while (t--) { int n; cin >> n; int o = 0, z = 0; for (int _ = 0; _ < n; _++) { int v; cin >> v; if (v == 1) o++; else z++; } int times, val; if (o > z) { times = o; val = 1; } else { times = z; val = 0; } if (val == 1 && times % 2 && val == 1) times--; cout << times << endl; for (int _ = 0; _ < times; _++) cout << val << ; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int a[200010]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= (n + 1) / 2; i++) { if (i % 2 == 1) { int temp; temp = a[i]; a[i] = a[n + 1 - i]; a[n + 1 - i] = temp; } } for (int i = 1; i < n; i++) printf( %d , a[i]); printf( %d n , a[n]); return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[4] = {1, -1, 0, 0}; int dy[4] = {0, 0, 1, -1}; long long gcd(long long a, long long b) { for (; b; a %= b, swap(a, b)) ; return a; } int main(void) { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { string n; int k; cin >> n; cin >> k; while (true) { set<char> s; for (int i = 0; i < n.size(); i++) s.insert(n[i]); if (s.size() <= k) { cout << n << n ; break; } s.clear(); int ptr = 0; while (true) { s.insert(n[ptr]); if (s.size() > k) { while (n[ptr] == 9 ) ptr--; n[ptr]++; for (int i = ptr + 1; i < n.size(); i++) n[i] = 0 ; break; } ptr++; } } } } |
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { while (b) b ^= a ^= b ^= a %= b; return a; } long long LCM(long long a, long long b) { return a * (b / GCD(a, b)); } const double EPS = 10e-9; const long long INF = (1LL << 30); using namespace std; template <typename T> string toString(T t) { stringstream ss; ss << t; return ss.str(); } long long isSquare(long long N) { long long lo = 1, hi = 2 * sqrt(N); while (hi - lo > 1) { long long mid = (hi + lo) >> 1; long long res = mid * mid; if (res < N) { lo = mid; } else if (res > N) { hi = mid; } else { return mid; } } return lo; } int main() { long long N; cin >> N; if (N % 3 != 0) { cout << 0 << endl; } else { N /= 3; int options = 0; for (long long i = 1; i * i * i <= N; i++) { if (N % i == 0) { long long left = N / i, to = i / 2; for (long long a = 1; a <= to; a++) { long long c = i - a; long long d = (a - c) * (a - c); long long sqr = isSquare(d + 4 * left); if (sqr * sqr == d + 4 * left) { long long b = (-(a + c) + sqr) >> 1; if (c <= b) { if (a == c) { if (b == c) { options += 1; } else { options += 3; } } else { if (b == c) { options += 3; } else { options += 6; } } } } } } } cout << options << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLRTN_BEHAVIORAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_BEHAVIORAL_PP_V |
// $Id: c_incr.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic modulo incrementer (i.e., incrementer with wraparound)
//==============================================================================
module c_incr
(data_in, data_out);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam swidth = suffix_length(min_value, max_value);
localparam cwidth = clogb(num_values);
// operand inputs
input [0:width-1] data_in;
// result output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire wrap;
genvar i;
generate
// all MSBs that are common to min_value and max_value can simply be
// copied over from either constant
for(i = 0; i < (width-swidth); i = i + 1)
begin:prefix
assign data_out[i] = min_value[i];
end
// the LSBs for a modulo counter, possibly with offset
if(cwidth > 0)
begin
assign wrap = (data_in[(width-cwidth):width-1] ==
max_value[(width-cwidth):width-1]);
wire [0:cwidth-1] lsb_incr;
assign lsb_incr = data_in[(width-cwidth):width-1] + 1'b1;
if((1 << cwidth) == num_values)
begin
// if the counter's range is a power of two, we can take
// advantage of natural wraparound
assign data_out[(width-cwidth):width-1] = lsb_incr;
end
else
begin
// if the range is not a power of two, we need to implement
// explicit wraparound
assign data_out[(width-cwidth):width-1]
= wrap ? min_value[(width-cwidth):width-1] : lsb_incr;
end
end
else
assign wrap = 1'b1;
// for the remaining range of bit positions (if any), min_value and
// max_value differ by one due to the carry-out from the modulo counter
// that implements the LSBs; i.e., this range of bits can have two
// distinct values
if(swidth > cwidth)
begin
wire carry;
assign carry = &data_in[(width-cwidth):width-1];
assign data_out[(width-swidth):(width-cwidth)-1]
= wrap ? min_value[(width-swidth):(width-cwidth)-1] :
carry ? max_value[(width-swidth):(width-cwidth)-1] :
data_in[(width-swidth):(width-cwidth)-1];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; cout << Mike n ; int freq[26] = {0}; freq[str[0] - a ]++; for (int i = 1; i < str.length(); i++) { int val = 0; for (int j = 0; j < str[i] - a ; j++) { if (freq[j] > 0) { val = 1; break; } } freq[str[i] - a ]++; if (val == 1) { cout << Ann n ; } else { cout << Mike n ; } } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Note -- clocks must be synchronous (derived from the same source)
// Assumes alt_clk is running at a multiple of wb_clk
// Note -- assumes that the lower-16 bits will be requested first,
// and that the upper-16 bit request will come immediately after.
module wb_readback_mux_16LE
(input wb_clk_i,
input wb_rst_i,
input wb_stb_i,
input [15:0] wb_adr_i,
output [15:0] wb_dat_o,
output reg wb_ack_o,
input [31:0] word00,
input [31:0] word01,
input [31:0] word02,
input [31:0] word03,
input [31:0] word04,
input [31:0] word05,
input [31:0] word06,
input [31:0] word07,
input [31:0] word08,
input [31:0] word09,
input [31:0] word10,
input [31:0] word11,
input [31:0] word12,
input [31:0] word13,
input [31:0] word14,
input [31:0] word15
);
wire ack_next = wb_stb_i & ~wb_ack_o;
always @(posedge wb_clk_i)
if(wb_rst_i)
wb_ack_o <= 0;
else
wb_ack_o <= ack_next;
reg [31:0] data;
assign wb_dat_o = data[15:0];
always @(posedge wb_clk_i)
if (wb_adr_i[1] & ack_next) begin //upper half
data[15:0] <= data[31:16];
end
else if (~wb_adr_i[1] & ack_next) begin //lower half
case(wb_adr_i[5:2])
0 : data <= word00;
1 : data <= word01;
2 : data <= word02;
3 : data <= word03;
4 : data <= word04;
5 : data <= word05;
6 : data <= word06;
7 : data <= word07;
8 : data <= word08;
9 : data <= word09;
10: data <= word10;
11: data <= word11;
12: data <= word12;
13: data <= word13;
14: data <= word14;
15: data <= word15;
endcase // case(wb_adr_i[5:2])
end
endmodule // wb_readback_mux
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; double x, y, s = 0; for (int i = 0; i < a; i++) { cin >> x >> y; s += y; } s /= a; printf( %.3lf n , s + 5); return 0; } |
// i2c_hs_interface.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module i2c_hs_interface (
input wire clk, // clock.clk
input wire [2:0] slave_address, // slave.address
output wire [31:0] slave_readdata, // .readdata
input wire slave_read, // .read
input wire slave_write, // .write
input wire [31:0] slave_writedata, // .writedata
input wire reset, // reset.reset
output wire i2c_hs_read, // i2c_hs.export
output wire i2c_hs_write, // .export
output wire [2:0] i2c_hs_addr, // .export
input wire [31:0] i2c_hs_readdata, // .export
output wire [31:0] i2c_hs_writedata // .export
);
assign slave_readdata = i2c_hs_readdata;
assign i2c_hs_writedata = slave_writedata;
assign i2c_hs_write = slave_write;
assign i2c_hs_read = slave_read;
assign i2c_hs_addr = slave_address;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:12:35 06/03/2016
// Design Name:
// Module Name: Banderas_Alarma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Banderas_Alarma(
input [7:0] Segundos,
input [7:0] Minutos,
input [7:0] Horas,
input [7:0] Segundos_RTC,
input [7:0] Minutos_RTC,
input [7:0] Horas_RTC,
input [7:0] Estado,
input [7:0] Guardar,
input clk,
input reset,
output reg [7:0] Flag_Pico
);
always @(posedge clk)
if (reset)
begin
Flag_Pico <= 8'd0;
end
else
if ((Guardar == 8'h70)&&(Estado == 8'h75))
begin
if ((Segundos_RTC == Segundos )&& (Minutos_RTC == Minutos) && (Horas_RTC == Horas ) && (Segundos_RTC != 8'h00) && (Minutos_RTC != 8'h00) && (Horas_RTC != 8'h00))
begin
Flag_Pico <= 8'd1;
end
else
begin
Flag_Pico <= 8'd0;
end
end
else
begin
Flag_Pico <= Flag_Pico;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const long long _INF = 0x7ffffffffffffffll; const double EPS = 1e-9; const double PI = acos(-1.0); template <class T, class INT> inline T pow(T x, INT y) { T res(1); for (T tt(x); y; y /= 2) { if (y & 1) res *= tt; tt *= tt; } return res; } template <class T, class INT> inline T pow(T x, INT y, T p) { T res(1); for (T tt(x); y; y /= 2) { if (y & 1) res = res * tt % p; tt = tt * tt % p; } return res; } int toInt(string s) { int x = 0; istringstream sin(s); sin >> x; return x; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } template <class INT> inline INT gcd(INT x, INT y) { return y ? gcd(y, x % y) : x; } template <class INT> inline int calc_bits(INT x) { return x ? (x & 1) + calc_bits(x >> 1) : 0; } int n, x, xx, y, yy, ans; int main(int argc, char* argv[]) { cin >> n >> x >> y >> xx >> yy; ans = abs(x - xx) + abs(y - yy); if (x == 0 && xx == n || x == n && xx == 0) ans += min(n - max(y, yy), min(y, yy)) * 2; if (y == 0 && yy == n || y == n && yy == 0) ans += min(n - max(x, xx), min(x, xx)) * 2; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int arr[104]; int main() { int n, avg, mn, flag; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; } avg = 0; avg = arr[1] - arr[0]; flag = 0; for (int i = 1; i < n; i++) { int diff = (arr[i] - arr[i - 1]); if (diff != avg) { flag = 1; break; } } if (flag == 1) { cout << arr[n - 1] << endl; } else { cout << arr[n - 1] + avg << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRBP_PP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_PP_BLACKBOX_V
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
module sync
(
input clock,
input in,
output out
);
(* ASYNC_REG="TRUE", TIG="TRUE" *) reg [2:0] sreg = 0;
always @(posedge clock)
sreg <= {sreg[1:0], in};
assign out = sreg[2];
endmodule
module one_shot
(
input clock,
input in,
output reg out = 0
);
reg in_prev = 0;
always @(posedge clock)
begin
in_prev <= in;
out <= in & ~in_prev;
end
endmodule
module pulse_stretch
(
input clock,
input in,
output reg out = 0
);
parameter NB=3;
reg [NB-1:0] count = 0;
always @(posedge clock)
begin
if(in)
count <= 1'b1;
else
count <= count + (count != 0);
out <= in | (count != 0);
end
endmodule
module sync_oneshot(input c, input i, output o);
wire synced;
sync sync(.clock(c), .in(i), .o(synced));
one_shot one_shot(.clock(c), .in(synced), .out(o));
endmodule
module sync_pulse (input ci, input co, input i, output reg o = 0);
reg tog = 0;
always @ (posedge ci)
tog <= tog ^ i;
reg [1:0] prev = 0;
always @ (posedge co) begin
prev <= {prev[0], tog};
o <= prev[0] ^ prev[1];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream fin( abc.in ); string str[2]; long long let[26][500001]; long long a, b, sum, m; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } int main() { cin >> a >> b; cin >> str[0] >> str[1]; long long len_mx = str[1].size(), len_mn = str[0].size(), i, j, dif_len; int p = 1; if (str[0].size() > str[1].size()) p = 0, len_mx = str[0].size(), len_mn = str[1].size(); dif_len = str[p].size() - str[1 - p].size(); long long cmmmc = len_mx * len_mn / gcd(len_mx, len_mn); m = a / (cmmmc / str[0].size()); long long cmmdc = gcd(len_mn, len_mx); long long sx = 0; if (dif_len == 0) { for (i = 0; i < len_mx; i++) if (str[0][i] != str[1][i]) sx += m; } else { for (i = 0; i < len_mx; i++) { char c = str[p][i]; let[(long)(c - a )][i % cmmdc]++; } for (i = 0; i < len_mn; i++) { char c = str[1 - p][i]; sx += m * (str[p].size() / cmmdc - let[c - a ][i % cmmdc]); } } cout << sx; return 0; } |
// -----------------------------------------------------------------------------
// FILE NAME : Wu_Manber_checker.v
// DEPARTMENT : Computer Engineering
// AUTHOR : Ashik Poojari
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2016-09-18 Ashik Poojari
// -----------------------------------------------------------------------------
// KEYWORDS : General file searching keywords, leave blank if none.
// -----------------------------------------------------------------------------
// PURPOSE : Short description of functionality
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
// e.g.DATA_WIDTH [32,16] : width of the data : 32 :
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Asynchronous
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Scan Methodology :
// Instantiations :
// Synthesizable (y/n) : y
// Other :
// -FHDR------------------------------------------------------------------------
`timescale 1ns/1ns
module WUM_fsm #(parameter SIGN_DEPTH=5, NOS_KEY=2,NOS_STGS=4,SFT_DEL_WDH=4)
( input clk,
input reset,
input datInReady,
output reg compare_enable, output reg compare_mux,
output a_clr, output datin_clr, output reg shift_amt_clr,
output reg a_ld, output reg shift_amt_ld,
output reg input_ready);
localparam Idle=3'h0, DataInload=3'h1, DatadeMux=3'h2, Shift=3'h3, Shift_Dat_ld=3'h4, Compare=3'h5;
reg [2:0] current_state;
reg [2:0] next_state;
reg [SFT_DEL_WDH:0] shift_delay;
assign a_clr = 0;
assign datin_clr = 0;
always @ (posedge clk)
begin
if (reset) begin
current_state <= Idle;
end
else
current_state <= next_state;
end
always @(posedge clk)
begin
if(reset) begin
shift_delay <= 0;
end
else if(current_state == Compare) begin
if(shift_delay == NOS_STGS+NOS_KEY+1)
shift_delay <= 0;
else begin
shift_delay <= shift_delay + 1;;
end
end
else begin
shift_delay <= 0;
end
end
always @(current_state,shift_delay)
begin
if (shift_delay >= NOS_STGS+1 && shift_delay < NOS_STGS+NOS_KEY+1) begin
compare_mux<=1;
end
else begin
compare_mux<=0;
end
end
always @(current_state,shift_delay)
begin
if(current_state == Compare && shift_delay < NOS_STGS+1) begin
compare_enable <= 1;
end
else compare_enable <= 0;
end
always @(current_state)
begin
if(current_state == DatadeMux) begin
input_ready = 1;
end
else input_ready = 0;
end
//always @(current_state)
//begin
// if(current_state == DataInload) begin
// datin_ld = 1;
// end
// else datin_ld = 0;
//end
always @(current_state)
begin
if(current_state == Shift || current_state == Idle) begin
shift_amt_clr=1;
end
else begin
shift_amt_clr=0;
end
end
always @(current_state)
begin
if(current_state == Shift_Dat_ld) begin
a_ld=1;
end
else begin
a_ld=0;
end
end
always @(current_state,shift_delay)
begin
if(current_state == Compare && shift_delay == NOS_STGS+NOS_KEY+1) begin
shift_amt_ld=1;
end
else begin
shift_amt_ld=0;
end
end
always @ (current_state, datInReady,shift_delay)
begin
case(current_state)
Idle: if(datInReady == 1) begin
next_state=DataInload;
end
else next_state= Idle;
DataInload: next_state=DatadeMux;
DatadeMux: next_state=Shift;
Shift: next_state = Shift_Dat_ld;
Shift_Dat_ld: next_state = Compare;
Compare: if(shift_delay == NOS_STGS+NOS_KEY+1)
next_state = Shift;
else next_state = Compare;
default: next_state=current_state;
endcase
end
endmodule
|
module src_shift_reg (
source1_data,
source2_data,
source3_data,
source_vcc_value,
source_exec_value,
src_buffer_wr_en,
src_buffer_shift_en,
alu_source1_data,
alu_source2_data,
alu_source3_data,
alu_source_vcc_value,
alu_source_exec_value,
clk,
rst
);
input [2047:0] source1_data;
input [2047:0] source2_data;
input [2047:0] source3_data;
input [63:0] source_vcc_value;
input [63:0] source_exec_value;
input src_buffer_wr_en;
input src_buffer_shift_en;
output [511:0] alu_source1_data;
output [511:0] alu_source2_data;
output [511:0] alu_source3_data;
output [15:0] alu_source_vcc_value;
output [15:0] alu_source_exec_value;
input clk;
input rst;
shift_in #(32) src1_shift(
.data_in(source1_data),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source1_data),
.clk(clk),
.rst(rst)
);
shift_in #(32) src2_shift(
.data_in(source2_data),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source2_data),
.clk(clk),
.rst(rst)
);
shift_in #(32) src3_shift(
.data_in(source3_data),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source3_data),
.clk(clk),
.rst(rst)
);
shift_in #(1) exec_shift(
.data_in(source_exec_value),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source_exec_value),
.clk(clk),
.rst(rst)
);
shift_in #(1) vcc_shift(
.data_in(source_vcc_value),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source_vcc_value),
.clk(clk),
.rst(rst)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int K = 32; const int TIME = K * 24 * 60; int tot_subj, tot_stud, tot_days; map<string, int> subj_time; pair<int, int> occupied[4]; struct student { int time, when, pays; } st[N]; int dp_money[N][TIME]; int dp_nxt[N][TIME]; bool isFreeTime(int time) { time %= (24 * 60); for (int i = 0; i < 4; i++) { if (occupied[i].first <= time && time <= occupied[i].second) return false; } return true; } int main() { scanf( %d %d %d , &tot_subj, &tot_stud, &tot_days); vector<string> subjects(tot_subj); for (int i = 0; i < tot_subj; i++) cin >> subjects[i]; for (int i = 0; i < tot_subj; i++) { int time; cin >> time; subj_time[subjects[i]] = time; } for (int i = 0; i < 4; i++) { int hs, ms, he, me; scanf( %2d:%2d-%2d:%2d , &hs, &ms, &he, &me); occupied[i].first = hs * 60 + ms; occupied[i].second = he * 60 + me; } for (int i = 1; i <= tot_stud; i++) { string subj; cin >> subj; if (subj_time.find(subj) != subj_time.end()) st[i].time = subj_time[subj]; else st[i].time = TIME + 10; int d, h, m; scanf( %d %2d:%2d , &d, &h, &m); st[i].when = (d - 1) * 24 * 60 + h * 60 + m; scanf( %d , &st[i].pays); } int tot_time = tot_days * 24 * 60; vector<int> order(tot_stud); iota(order.begin(), order.end(), 1); sort(order.begin(), order.end(), [](int i, int j) { return st[i].when < st[j].when; }); for (int dp_i = 0; dp_i < order.size(); dp_i++) { int at_stud = order[dp_i]; for (int l_time = 0, r_time = 0, free_time = 0; r_time < tot_time; r_time++) { if (dp_i > 0) { dp_money[dp_i][r_time] = dp_money[dp_i - 1][r_time]; dp_nxt[dp_i][r_time] = -1; } if (r_time > 0 && dp_money[dp_i][r_time] < dp_money[dp_i][r_time - 1]) { dp_money[dp_i][r_time] = dp_money[dp_i][r_time - 1]; dp_nxt[dp_i][r_time] = 0; } free_time += isFreeTime(r_time); if (r_time >= st[at_stud].when || free_time < st[at_stud].time) continue; while (free_time > st[at_stud].time || !isFreeTime(l_time)) { free_time -= isFreeTime(l_time); l_time++; } int new_money = st[at_stud].pays + (l_time == 0 || dp_i == 0 ? 0 : dp_money[dp_i - 1][l_time - 1]); if (isFreeTime(r_time) && new_money > dp_money[dp_i][r_time]) { dp_money[dp_i][r_time] = new_money; dp_nxt[dp_i][r_time] = 1; } } } int got_money = dp_money[tot_stud - 1][tot_time - 1]; stack<int> got_students; stack<pair<int, int> > got_times; printf( %d n , got_money); for (int at_time = tot_time - 1, dp_i = tot_stud - 1; at_time >= 0 && dp_i >= 0;) { if (dp_nxt[dp_i][at_time] == -1) dp_i--; else if (dp_nxt[dp_i][at_time] == 0) at_time--; else { int at_stud = order[dp_i]; int start_time; int end_time = at_time; int free_time = 0; while (free_time < st[at_stud].time) { free_time += isFreeTime(at_time); start_time = at_time; at_time--; } got_students.push(order[dp_i]); got_times.push(make_pair(start_time, end_time)); dp_i--; } } int tot_helps = got_students.size(); printf( %d n , tot_helps); while (tot_helps--) { int stud_id = got_students.top(); got_students.pop(); int start_time = got_times.top().first; int end_time = got_times.top().second; got_times.pop(); int start_day = start_time / (24 * 60); start_time %= (24 * 60); int end_day = end_time / (24 * 60); end_time %= (24 * 60); int start_h = start_time / 60; start_time %= 60; int end_h = end_time / 60; end_time %= 60; int start_m = start_time; int end_m = end_time; printf( %d %d %02d:%02d %d %02d:%02d n , stud_id, start_day + 1, start_h, start_m, end_day + 1, end_h, end_m); } return 0; } |
/*****************************************************************************/
//
// Module: instdec.v
// Revision: $Revision: 1.1 $
// Last Modified On: $Date: 2011/08/11 16:28:50 $
// Last Modified By: $Author: mruff $
//
//-----------------------------------------------------------------------------
//
// Description: Decode CP instructions
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2011 : Created by Convey Computer Corp. This file is the
// confidential and proprietary property of Convey Computer Corp.
//
/*****************************************************************************/
/* $Id: instdec.v,v 1.1 2011/08/11 16:28:50 mruff Exp $ */
module instdec (
input [31:0] cae_inst,
input [63:0] cae_data,
input cae_inst_vld,
output inst_val,
output [4:0] inst_caep,
output inst_aeg_wr,
output inst_aeg_rd,
output [17:0] inst_aeg_idx,
output err_unimpl
);
reg c_val, c_aeg_wr, c_aeg_rd, c_unimpl;
reg [4:0] c_caep;
reg [17:0] c_aeg_idx;
always @* begin
c_val = 'b0;
c_caep = 'b0;
c_aeg_wr = 'b0;
c_aeg_rd = 'b0;
c_aeg_idx = 'b0;
c_unimpl = 'b0;
casex (cae_inst[28:24])
// Format 4 instructions
5'b1101?: begin
case (cae_inst[24:18])
7'h40: begin
c_aeg_idx = cae_inst[17:0];
c_aeg_wr = cae_inst_vld;
end
7'h68: begin
c_aeg_idx = cae_data[17:0];
c_aeg_rd = cae_inst_vld;
end
7'h70: begin
c_aeg_idx = {6'b0, cae_inst[17:6]};
c_aeg_rd = cae_inst_vld;
end
default: c_unimpl = cae_inst_vld;
endcase
end
// Format 5 instructions
5'b11100: begin
case (cae_inst[23:18])
6'h18: begin
c_aeg_idx = {6'b0, cae_inst[17:12], cae_inst[5:0]};
c_aeg_wr = cae_inst_vld;
end
6'h20: begin
c_aeg_idx = {6'b0, cae_inst[17:12], cae_inst[5:0]};
c_aeg_wr = cae_inst_vld;
end
default: c_unimpl = cae_inst_vld;
endcase
end
// Format 6 instructions
5'b11101: begin
case (cae_inst[23:18])
6'h1c: begin
c_aeg_idx = {6'b0, cae_inst[17:6]};
c_aeg_rd = cae_inst_vld;
end
default: c_unimpl = cae_inst_vld;
endcase
end
// Format 7 instructions
5'b11110: begin
// CAEP instructions in range 20-3F
c_caep = cae_inst[22:18];
c_val = cae_inst_vld & cae_inst[23];
c_unimpl = cae_inst_vld & !cae_inst[23];
end
default: c_unimpl = cae_inst_vld;
endcase
end
assign inst_val = c_val;
assign inst_caep = c_caep;
assign inst_aeg_wr = c_aeg_wr;
assign inst_aeg_rd = c_aeg_rd;
assign inst_aeg_idx = c_aeg_idx;
assign err_unimpl = c_unimpl;
endmodule
|
#include <bits/stdc++.h> using namespace std; int TRIE[200005 * 32 * 2][2]; int isword[200005 * 32 * 2]; int nxt; void ins(string &s) { int v = 0; for (int i = 0; i < s.size(); i++) { if (TRIE[v][s[i] - 0 ] == -1) TRIE[v][s[i] - 0 ] = nxt++; isword[v]++; v = TRIE[v][s[i] - 0 ]; } isword[v]++; } void del(string &s) { int v = 0; int u; for (int i = 0; i < s.size(); i++) { if (isword[v] > 0) isword[v]--; if (isword[v] == 0 && i > 0) TRIE[u][s[i - 1] - 0 ] = -1; u = v; v = TRIE[v][s[i] - 0 ]; } if (isword[v] > 0) isword[v]--; if (isword[v] == 0) TRIE[u][s[31] - 0 ] = -1; } string bin(int a) { string k = ; while (a) { k += to_string(a % 2); a /= 2; } int u = k.length(); for (int i = 0; i < 32 - u; i++) k += 0 ; reverse(k.begin(), k.end()); return k; } long long int query(string &s) { int v = 0; string k = ; for (int i = 0; i < s.size(); i++) { if (TRIE[v][1 - (s[i] - 0 )] != -1) { v = TRIE[v][1 - (s[i] - 0 )]; if (s[i] == 0 ) k += 1 ; else k += 0 ; } else { v = TRIE[v][s[i] - 0 ]; k += s[i]; } } long long int val = 0, bit; for (int i = 0; i <= 31; i++) { bit = (s[i] == k[i]) ? 0 : 1; val <<= 1; val += bit; } return val; } int main() { memset(isword, 0, sizeof(isword)); memset(TRIE, -1, sizeof(TRIE)); isword[0] = 1; nxt = 1; int q, a; string s; cin >> q; string k = bin(0); ins(k); for (int i = 0; i < q; i++) { cin >> s >> a; string k = bin(a); if (s == + ) ins(k); else if (s == - ) del(k); else cout << query(k) << endl; } return 0; } |
// Example module that doesn't instantiate
module appendix1 (/*AUTOARG*/
// Outputs
z,
// Inputs
i
);
input i;
output z;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg z;
// End of automatics
/*AUTOWIRE*/
always @ (/*AUTOSENSE*/i) begin
z = i;
end
endmodule
// Example module that does instantiate
module appendix2 (/*AUTOARG*/
// Outputs
z,
// Inputs
i
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i; // To apx10 of appendix1.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [11:10] z; // From apx10 of appendix1.v, ...
// End of automatics
/*AUTOREG*/
/*AUTOWIRE*/
/*
appendix1 AUTO_TEMPLATE (
.z (z[@]),
);
*/
appendix1 apx10 (/*AUTOINST*/
// Outputs
.z (z[10]), // Templated
// Inputs
.i (i));
appendix1 apx11 (/*AUTOINST*/
// Outputs
.z (z[11]), // Templated
// Inputs
.i (i));
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_bCMD_manager for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_bCMD_manager
// Module Name: NPCG_Toggle_bCMD_manager
// File Name: NPCG_Toggle_bCMD_manager.v
//
// Version: v1.0.0
//
// Description: NFC PCG layer command manager
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_bCMD_manager
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iTargetWay ,
ibCMDStart ,
ibCMDLast ,
ibCMDLast_SCC ,
iNANDPOE ,
iCMDHold ,
iOpcode ,
iTargetID ,
iSourceID ,
oOpcode_out ,
oTargetID_out ,
oSourceID_out ,
iCMDValid_in ,
oCMDValid_out_NPOE ,
oCMDValid_out ,
oCMDReady_out ,
iCMDReady_in ,
oWorkingWay
);
input iSystemClock ;
input iReset ;
input [NumberOfWays - 1:0] iTargetWay ;
input ibCMDStart ;
input ibCMDLast ;
input ibCMDLast_SCC ;
input iNANDPOE ;
input iCMDHold ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
output [5:0] oOpcode_out ;
output [4:0] oTargetID_out ;
output [4:0] oSourceID_out ;
input iCMDValid_in ;
output oCMDValid_out_NPOE ;
output oCMDValid_out ;
output oCMDReady_out ;
input iCMDReady_in ;
output [NumberOfWays - 1:0] oWorkingWay ;
// FSM Parameters/Wires/Regs
parameter MNG_FSM_BIT = 5; // MaNaGer
parameter MNG_RESET = 5'b00001;
parameter MNG_READY = 5'b00010; // Ready
parameter MNG_START = 5'b00100; // Blocking command start
parameter MNG_RUNNG = 5'b01000; // Blocking command running
parameter MNG_bH_Zd = 5'b10000; // Bus high-Z delay
reg [MNG_FSM_BIT-1:0] rMNG_cur_state ;
reg [MNG_FSM_BIT-1:0] rMNG_nxt_state ;
// Internal Wires/Regs
reg [3:0] rbH_ZdCounter ;
wire wbH_ZdDone ;
reg [NumberOfWays - 1:0] rWorkingWay ;
reg rCMDBlocking ;
// Control Signals
assign wbH_ZdDone = (rbH_ZdCounter[3:0] == 4'b0100);
// FSM: MaNaGer (MNG)
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rMNG_cur_state <= MNG_RESET;
end else begin
rMNG_cur_state <= rMNG_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (rMNG_cur_state)
MNG_RESET: begin
rMNG_nxt_state <= MNG_READY;
end
MNG_READY: begin
rMNG_nxt_state <= (ibCMDStart)? MNG_START:MNG_READY;
end
MNG_START: begin
rMNG_nxt_state <= (ibCMDLast)? ((ibCMDLast_SCC)? MNG_READY:MNG_bH_Zd):MNG_RUNNG;
end
MNG_RUNNG: begin
rMNG_nxt_state <= (ibCMDLast)? ((ibCMDLast_SCC)? MNG_READY:MNG_bH_Zd):MNG_RUNNG;
end
MNG_bH_Zd: begin
rMNG_nxt_state <= (wbH_ZdDone)? MNG_READY:MNG_bH_Zd;
end
default:
rMNG_nxt_state <= MNG_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rWorkingWay[NumberOfWays - 1:0] <= 0;
rCMDBlocking <= 0;
rbH_ZdCounter[3:0] <= 0;
end else begin
case (rMNG_nxt_state)
MNG_RESET: begin
rWorkingWay[NumberOfWays - 1:0] <= 0;
rCMDBlocking <= 0;
rbH_ZdCounter[3:0] <= 0;
end
MNG_READY: begin
rWorkingWay[NumberOfWays - 1:0] <= 0;
rCMDBlocking <= 0;
rbH_ZdCounter[3:0] <= 0;
end
MNG_START: begin
rWorkingWay[NumberOfWays - 1:0] <= iTargetWay[NumberOfWays - 1:0];
rCMDBlocking <= 1'b1;
rbH_ZdCounter[3:0] <= 4'b0000;
end
MNG_RUNNG: begin
rWorkingWay[NumberOfWays - 1:0] <= rWorkingWay[NumberOfWays - 1:0];
rCMDBlocking <= 1'b1;
rbH_ZdCounter[3:0] <= 4'b0000;
end
MNG_bH_Zd: begin
rWorkingWay[NumberOfWays - 1:0] <= rWorkingWay[NumberOfWays - 1:0];
rCMDBlocking <= 1'b1;
rbH_ZdCounter[3:0] <= rbH_ZdCounter[3:0] + 1'b1;
end
endcase
end
end
// Output
assign oCMDValid_out_NPOE = (~rCMDBlocking) & (iNANDPOE | (iCMDValid_in & (~iNANDPOE)));
assign oCMDValid_out = (~rCMDBlocking) & (~iCMDHold) & (iCMDValid_in) & (~iNANDPOE);
assign oCMDReady_out = (~rCMDBlocking) & (~iCMDHold) & (iCMDReady_in) & (~iNANDPOE);
assign oOpcode_out[5:0] = (iNANDPOE)? (6'b111110):(iOpcode[5:0]);
assign oTargetID_out[4:0] = (iNANDPOE)? (5'b00101):(iTargetID[4:0]);
assign oSourceID_out[4:0] = (iNANDPOE)? (5'b00101):(iSourceID[4:0]);
assign oWorkingWay[NumberOfWays - 1:0] = rWorkingWay[NumberOfWays - 1:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long M = 1000000007; const double pi = 3.141592653589793238463; long long modExp(long long x, long long n, long long M) { long long result = 1; while (n > 0) { if (n % 2 == 1) result = (result * x) % M; x = (x * x) % M; n = n / 2; } return result; } bool sortbysec(const pair<long long, long long> &a, const pair<long long, long long> &b) { return (a.second < b.second); } bool vow(char ch) { return ch == a || ch == e || ch == i || ch == o || ch == u ; } bool isPrime(long long n) { for (long long i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } long long fast_exp(long long x, long long n) { long long ans = 1; while (n) { if (n & 1) { ans *= x; ans %= M; } n = n >> 1; x = (x * x) % M; } return ans; } long long inverse(long long x) { return fast_exp(x, M - 2); } long long combination(long long n, long long r) { if (r == 0) return 1; else { long long ans = n % M; ans *= combination(n - 1, r - 1) % M; ans %= M; ans *= inverse(r) % M; ans %= M; return ans; } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; long long n, a, b, q; cin >> n >> a >> b; for (long long i = min(a, b); i > 0; i--) { q = a / i + b / i; if (q >= n) return cout << i, 0; } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) #pragma warning(disable : 4996) using namespace std; int main() { int Lpos1, Lpos2; bool p[9][9]; memset(p, true, sizeof(p)); for (int i = 0; i < 2; i++) { char k[3]; scanf( %s , &k); int pos1 = k[0] - a + 1; int pos2 = k[1] - 0 ; if (i == 0) { Lpos1 = pos1; Lpos2 = pos2; for (int j = pos1; j >= 1; j--) p[j][pos2] = false; for (int j = pos1; j <= 8; j++) p[j][pos2] = false; for (int j = pos2; j >= 1; j--) p[pos1][j] = false; for (int j = pos2; j <= 8; j++) p[pos1][j] = false; } else { int x = pos1, y = pos2; p[x][y] = false; if (x + 1 <= 8 && y + 2 <= 8) p[x + 1][y + 2] = false; if (x - 1 >= 1 && y + 2 <= 8) p[x - 1][y + 2] = false; if (x - 2 >= 1 && y + 1 <= 8) p[x - 2][y + 1] = false; if (x - 2 >= 1 && y - 1 >= 1) p[x - 2][y - 1] = false; if (x - 1 >= 1 && y - 2 >= 1) p[x - 1][y - 2] = false; if (x + 1 <= 8 && y - 2 >= 1) p[x + 1][y - 2] = false; if (x + 2 <= 8 && y - 1 >= 1) p[x + 2][y - 1] = false; if (x + 2 <= 8 && y + 1 <= 8) p[x + 2][y + 1] = false; } } int x = Lpos1, y = Lpos2; if (x + 1 <= 8 && y + 2 <= 8) p[x + 1][y + 2] = false; if (x - 1 >= 1 && y + 2 <= 8) p[x - 1][y + 2] = false; if (x - 2 >= 1 && y + 1 <= 8) p[x - 2][y + 1] = false; if (x - 2 >= 1 && y - 1 >= 1) p[x - 2][y - 1] = false; if (x - 1 >= 1 && y - 2 >= 1) p[x - 1][y - 2] = false; if (x + 1 <= 8 && y - 2 >= 1) p[x + 1][y - 2] = false; if (x + 2 <= 8 && y - 1 >= 1) p[x + 2][y - 1] = false; if (x + 2 <= 8 && y + 1 <= 8) p[x + 2][y + 1] = false; int d = 0; for (int i = 1; i <= 8; i++) for (int j = 1; j <= 8; j++) if (p[i][j]) d++; printf( %d , d); return 0; } |
#include <bits/stdc++.h> using namespace std; double inf = 1e+10; double eps = 1e-10; inline int sgn(const double& x) { return (x > +eps) - (x < -eps); } const int MAXN = 500; const int MAXM = 501; int n, m; double A[MAXM + 1][MAXN + 1]; int basis[MAXM + 1], out[MAXN + 1]; void pivot(int a, int b) { for (int i = 0; i <= m; ++i) if (i != a && sgn(A[i][b])) for (int j = 0; j <= n; ++j) if (j != b) A[i][j] -= A[a][j] * A[i][b] / A[a][b]; for (int i = 0; i <= m; ++i) if (i != a) A[i][b] /= -A[a][b]; for (int j = 0; j <= n; ++j) if (j != b) A[a][j] /= A[a][b]; A[a][b] = 1 / A[a][b]; swap(basis[a], out[b]); } double simplex() { for (int j = 0; j < n; ++j) A[0][j] = -A[0][j]; for (int i = 0; i <= m; ++i) basis[i] = -i; for (int j = 0; j <= n; ++j) out[j] = j; while (true) { int a = 1, b = 0; for (int i = 1; i <= m; ++i) if (make_pair(A[i][n], basis[i]) < make_pair(A[a][n], basis[a])) a = i; if (A[a][n] >= 0) break; for (int j = 0; j < n; ++j) if (A[a][j] < A[a][b]) b = j; if (A[a][b] >= 0) return -inf; pivot(a, b); } while (true) { int a = 1, b = 0; for (int j = 0; j < n; ++j) if (A[0][j] < A[0][b] || A[0][j] == A[0][b] && out[j] < out[b]) b = j; if (A[0][b] >= 0) break; for (int i = 1; i <= m; ++i) if (A[i][b] > 0 && (A[a][b] <= 0 || make_pair(A[i][n] / A[i][b], basis[i]) < make_pair(A[a][n] / A[a][b], basis[a]))) a = i; if (A[a][b] <= 0) return +inf; pivot(a, b); } return A[0][n]; } int d; vector<int> adj[500]; vector<int> wei[500]; void dfs(double A[], int u, int p, int d) { if (d >= 0) { A[u]--; for (int i = 0; i < ((int((adj[u]).size()))); ++i) { int v = adj[u][i]; if (v != p) { dfs(A, v, u, d - wei[u][i]); } } } } int main() { scanf( %d%d , &n, &d); int ttl = 0; for (int i = 0; i < (n); ++i) { int ti; scanf( %d , &ti), A[0][i] = ti - 1, ttl += ti; } for (int i = 0; i < (n - 1); ++i) { int u, v, w; scanf( %d%d%d , &u, &v, &w), --u, --v; adj[u].push_back(v), adj[v].push_back(u); wei[u].push_back(w), wei[v].push_back(w); } A[0][n] = 0; for (int i = 0; i < (n); ++i) { dfs(A[i + 1], i, -1, d); A[i + 1][n] = -1; } for (int i = 0; i < (n); ++i) A[n + 1][i] = 1; A[n + 1][n] = ttl; m = n + 1; double get = simplex(); int ans; if (get == -inf) ans = -1; else ans = -get + 0.5; printf( %d n , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_PP_SYMBOL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd3 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_PP_SYMBOL_V
|
#include <bits/stdc++.h> int main() { int c, input[100010]; int i = -1, j, k; while ((c = getchar()) != n ) { if (i < 0 || input[i] != c) input[++i] = c; else i--; } if (i < 0) printf( Yes n ); else printf( No n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; char img[2007][2007]; int c[2007], r[2007]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) scanf( %s , img[i]); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) img[i][j] -= 0 ; int ans = 0; for (int i = 0; i < n; i++) for (int j = n - 1; j > i; --j) if (c[j] ^ r[i] ^ img[i][j]) { ++ans; c[j] ^= 1, r[i] ^= 1; } for (int i = 0; i < n; i++) img[i][i] ^= c[i] ^ r[i]; memset(c, 0, sizeof(c)), memset(r, 0, sizeof(r)); for (int i = n - 1; i >= 0; --i) for (int j = 0; j < i + 1; j++) if (c[j] ^ r[i] ^ img[i][j]) { ++ans; c[j] ^= 1, r[i] ^= 1; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int Buffer_Size = 1 << 10; char buffer[Buffer_Size], *ihead = buffer + Buffer_Size, *itail = ihead; char Next_Char() { if (ihead == itail) fread(buffer, 1, Buffer_Size, stdin), ihead = buffer; return *ihead++; } template <typename T> void read(T &n) { n = 0; char ch = Next_Char(); while (!isdigit(ch)) ch = Next_Char(); while (isdigit(ch)) { n = (n << 3) + (n << 1) + (ch & 15); ch = Next_Char(); } } long long r, c, n, k, tp, sum; long long a[3002], cnt[3002], L[3002], R[3002]; vector<long long> v[3002]; struct Position { long long x, y; } p[3002]; bool Cmp(long long x, long long y) { return p[x].y < p[y].y; } bool DFS(long long x, long long step) { if (!step || !x) return 1; if (!DFS(L[x], step - 1)) cnt[L[x]] = cnt[x]; else cnt[L[x]] += cnt[x]; return 0; } int main() { read(r), read(c), read(n), read(k); for (long long i = 1; i <= n; ++i) { read(p[i].x), read(p[i].y); v[p[i].x].push_back(i); } long long ans = 0; for (long long i = 1; i <= r; ++i) { tp = sum = 0; for (long long j = 1; j <= n; ++j) if (p[j].x >= i) a[++tp] = j; sort(a + 1, a + tp + 1, Cmp); a[tp + 1] = n + 1; memset(cnt, 0, sizeof(cnt)); memset(L, 0, sizeof(L)); memset(R, 0, sizeof(R)); long long now = 0; for (long long j = 1; j <= c; ++j) { while (p[a[now + 1]].y == j && now < tp) { ++now; L[a[now]] = a[now - 1], R[a[now]] = a[now + 1]; } long long tmp = a[now]; for (long long l = 1; l < k; ++l) tmp = L[tmp]; ++cnt[tmp]; } for (long long j = 1; j <= tp; ++j) sum += p[a[j]].y * cnt[a[j]]; ans += sum; for (long long j = r; j >= i + 1; --j) { long long sz = (long long)v[j].size(); for (long long l = 0; l < sz; ++l) { long long x = v[j][l], q = x; for (long long o = 1; o <= k; ++o) { sum -= (p[x].y - p[L[x]].y) * cnt[x]; x = L[x]; if (!x) break; } x = q; DFS(x, k); x = q; L[R[x]] = L[x], R[L[x]] = R[x]; } ans += sum; } } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_TB_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_TB_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso0n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__inputiso0n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_TB_V
|
#include <bits/stdc++.h> int gi() { int x = 0; char ch = getchar(); while (!isdigit(ch)) { if (ch == ? ) return -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x; } bool eq(int a, int b) { if (b == -1) return 1; return a == b; } int n, D[310], L[310], Cnt[310], CNT[310], exist[310], maxdep[310]; int p[310]; int fir[610], dep[610], head[610], dis[10000010], nxt[10000010], w[10000010], id, cnt; int S, T, numl[310], numr[310], chain[310][310], chlen[310]; void link(int a, int b, int c) { nxt[++id] = fir[a], fir[a] = id, dis[id] = b, w[id] = c; nxt[++id] = fir[b], fir[b] = id, dis[id] = a, w[id] = 0; } int edger[310], edgelr[310][310], edgelc[310][310][310]; bool BFS() { static int que[610], hd, tl; hd = tl = 0; que[tl++] = S; memset(dep, 0, sizeof dep); dep[S] = 1; while (hd ^ tl) { int x = que[hd++]; for (int i = fir[x]; i; i = nxt[i]) if (w[i] && !dep[dis[i]]) dep[dis[i]] = dep[x] + 1, que[tl++] = dis[i]; } return dep[T]; } int Dinic(int x, int maxflow) { if (x == T) return maxflow; int ret = 0; for (int& i = head[x]; i; i = nxt[i]) if (dep[dis[i]] == dep[x] + 1 && w[i]) { int d = Dinic(dis[i], std::min(w[i], maxflow - ret)); w[i] -= d, w[i ^ 1] += d; ret += d; if (ret == maxflow) break; } return ret; } std::vector<int> V[310][310]; int Get(int i, int j) { int r = V[i][j].back(); V[i][j].pop_back(); return r; } int main() { n = gi(); int maxl = 0; for (int i = 1; i <= n; ++i) { D[i] = gi(), L[i] = gi(); if (~L[i]) { if (~D[i]) maxdep[L[i]] = std::max(maxdep[L[i]], D[i]); if (D[i] == 0) ++Cnt[L[i]]; else exist[L[i]] = 1; } else maxl = std::max(maxl, D[i]); } for (int i = 1; i <= n; ++i) { CNT[i] = (Cnt[i] + i - 1) / i; if (exist[i]) CNT[i] = std::max(CNT[i], 1); } bool FLG = 0; for (int o = 1; o <= n; ++o) { cnt = 2; S = 1, T = 2; memset(fir, 0, sizeof fir); id = 1; int tot = 0; bool flg = !CNT[o]; if (flg) if (!FLG) FLG = 1, CNT[o] = 1; else continue; for (int i = 1; i <= n; ++i) { int c = CNT[i] * i - Cnt[i]; if (c) edger[i] = id + 1, link(numr[i] = ++cnt, T, c), tot += c; else edger[i] = -1; } int sum = tot; for (int i = 1; i <= n; ++i) { chlen[i] = std::max(o == i ? maxl : 0, maxdep[i]); sum += chlen[i]; } if (sum > n) { if (flg) CNT[o] = 0; continue; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= chlen[i]; ++j) link(chain[i][j] = ++cnt, T, 1), ++tot; } for (int i = 1; i <= n; ++i) { memset(edgelr[i], -1, sizeof edgelr[i]); memset(edgelc[i], -1, sizeof edgelc[i]); if (D[i] == 0 && ~L[i]) continue; link(S, numl[i] = ++cnt, 1); if (D[i] <= 0) for (int j = 1; j <= n; ++j) if (numr[j] && eq(j, L[i])) edgelr[i][j] = id + 1, link(numl[i], numr[j], 1); if (D[i] != 0) { for (int j = 1; j <= n; ++j) if (eq(j, L[i])) for (int k = 1; k <= chlen[j]; ++k) if (k == D[i] || D[i] == -1) edgelc[i][j][k] = id + 1, link(numl[i], chain[j][k], 1); } } while (BFS()) memcpy(head, fir, sizeof head), tot -= Dinic(S, 1e9); if (tot) { if (flg) CNT[o] = 0; continue; } for (int i = 1; i <= n; ++i) p[i] = -1; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) if (~edgelr[i][j] && !w[edgelr[i][j]]) L[i] = j, D[i] = 0; for (int j = 1; j <= n; ++j) for (int k = 1; k <= chlen[j]; ++k) if (~edgelc[i][j][k] && !w[edgelc[i][j][k]]) L[i] = j, D[i] = k; if (~L[i] && ~D[i]) V[D[i]][L[i]].push_back(i); } for (int i = 1; i <= n; ++i) { if (!CNT[i]) continue; static int seq[82]; while (CNT[i]--) { for (int j = 1; j <= i; ++j) seq[j] = Get(0, i); seq[0] = seq[i]; for (int j = 1; j <= i; ++j) p[seq[j - 1]] = seq[j]; } for (int j = 1; j <= chlen[i]; ++j) seq[j] = Get(j, i); for (int j = 1; j <= chlen[i]; ++j) p[seq[j]] = seq[j - 1]; for (int j = 1; j <= n; ++j) if (p[j] == -1 && D[j] && eq(i, L[j]) && chlen[i] >= D[j] - 1) p[j] = seq[std::max(0, D[j] - 1)]; } for (int i = 1; i <= n; ++i) printf( %d , ~p[i] ? p[i] : i); exit(0); } puts( -1 ); return 0; } |
module top;
reg pass;
reg [5:0] cond;
reg [2:1] expr;
integer result;
always @(cond or expr) begin
casex (cond)
6'b01_??10 : result = 1;
{2'b10, 4'b??10} : result = 2;
{expr[1:0], 4'b??01} : result = 3;
expr[11:6] : result = 4;
default : result = 0;
endcase
end
initial begin
pass = 1'b1;
expr = 2'b10;
cond = 6'b01_xx10;
#1 if (result != 1) begin
$display("Failed case expr 1 test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'bxx_xxxx;
#1 if (result != 1) begin
$display("Failed case expr 1a test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'b10_zz10;
#1 if (result != 2) begin
$display("Failed case expr 2 test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'b0x_zz01;
#1 if (result != 3) begin
$display("Failed case expr 3 test, got expr %0d", result);
pass = 1'b0;
end
cond = 6'b11_1111;
#1 if (result != 4) begin
$display("Failed case expr 1a test, got expr %0d", result);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module microfono_TB;
reg reset, clk, micData,rd,wr;
microfono uut(.reset(reset),.micData(micData),.clk(clk),.rd(rd),.wr(wr));
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
reset =1'b1;
#10;
reset =1'b0;
end
initial
begin
rd = 1'b0;
wr = 1'b0;
#100 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
end
initial begin
micData = 1'b0;
#100 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
end
initial begin: TEST_CASE
$dumpfile("microfono_TB.vcd");
$dumpvars(-1, uut);
#(10000) $finish;
end
endmodule //
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_LP_V
`define SKY130_FD_SC_LP__O211A_LP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_lp (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_lp (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_LP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n; map<int, vector<vector<int> > > m; vector<int> v, ans; map<int, int> s; for (int i = 0; i < n - 2; i++) { int f, g, h; cin >> f >> g >> h; v.push_back(f); v.push_back(g); v.push_back(h); s[f]++; s[g]++; s[h]++; m[f].push_back(v); m[g].push_back(v); m[h].push_back(v); v.clear(); } for (auto i = s.begin(); i != s.end(); i++) { if (i->second == 1) { ans.push_back(i->first); for (auto p = m[i->first].begin(); p != m[i->first].end(); p++) { auto j = *p; for (int u = 0; u < 3; u++) { if (s[j[u]] == 2) a = j[u]; if (s[j[u]] == 3) b = j[u]; } } ans.push_back(a); ans.push_back(b); break; } } while (ans.size() < n) { int x, y, z, t; t = ans.size(); x = ans[t - 1]; y = ans[t - 2]; z = ans[t - 3]; for (auto p = m[y].begin(); p != m[y].end(); p++) { auto j = *p; if (((j[0] == y && j[1] == x) || (j[0] == x && j[1] == y)) && j[2] != z) ans.push_back(j[2]); else if (((j[0] == y && j[2] == x) || (j[0] == x && j[2] == y)) && j[1] != z) ans.push_back(j[1]); else if (((j[1] == y && j[2] == x) || (j[1] == x && j[2] == y)) && j[0] != z) ans.push_back(j[0]); } } for (auto c : ans) { cout << c << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int seg[(long long int)3e5 * 3]; int laz[(long long int)3e5 * 3]; void build(int index, int a, int b, int *ar) { if (a == b) { seg[index] = ar[a]; return; } int mid = (a + b) / 2; build(2 * index, a, mid, ar); build(2 * index + 1, mid + 1, b, ar); seg[index] = max(seg[2 * index], seg[2 * index + 1]); } void la(int l, int r, int index) { seg[index] += laz[index]; int a = 2 * index; int b = 2 * index + 1; if (l < r) { laz[a] += laz[index]; laz[b] += laz[index]; } laz[index] = 0; } void upd(int val, int l, int r, int x, int y, int index) { la(x, y, index); if (x > r || l > y) return; if (l <= x and r >= y) { laz[index] += val; la(x, y, index); return; } int mid = (x + y) / 2; upd(val, l, r, x, mid, 2 * index); upd(val, l, r, mid + 1, y, 2 * index + 1); seg[index] = max(seg[2 * index], seg[2 * index + 1]); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, p; cin >> n >> m >> p; vector<pair<int, int>> weap; vector<pair<int, int>> armr; vector<pair<int, pair<int, int>>> monst; for (int i = 0; i < n; i++) { int a, b; cin >> a >> b; weap.push_back({a, b}); } for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; armr.push_back({a, b}); } for (int i = 0; i < p; i++) { int a, b, c; cin >> a >> b >> c; monst.push_back({a, {b, c}}); } sort(weap.begin(), weap.end()); sort(armr.begin(), armr.end()); sort(monst.begin(), monst.end()); int pt = 0; int ar[(int)3e5]; for (int i = 0; i < m; i++) ar[i + 1] = -armr[i].second; build(1, 1, m, ar); int ans = -2 * (1e9 + 7); for (int i = 0; i < n; i++) { while (pt < p and weap[i].first > monst[pt].first) { int l = upper_bound(armr.begin(), armr.end(), make_pair(monst[pt].second.first, (int)1e9 + 7)) - armr.begin(); l++; if (l <= m) { upd(monst[pt].second.second, l, m, 1, m, 1); } pt++; } ans = max(ans, (seg[1] - weap[i].second)); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, q; cin >> n >> q; long long int ans[q]; for (long long int i = 0; i < q; i++) { long long int x, y, k = 0, cto = 0; ; cin >> x >> y; if (n % 2 == 0) { k = (n / 2) * (x - 1) + ((y / 2) + (y % 2)); if ((x + y) % 2 == 1) { k += (n * n) / 2; } } if (n % 2 == 1) { if (x % 2 == 0) { cto = (x / 2); } if (x % 2 == 1) { cto = (x - 1) / 2; } k = (n / 2) * (x - 1) + cto + ((y / 2) + (y % 2)); if ((x + y) % 2 == 1) { k += (n * n) / 2; if (x % 2 == 1) { k++; } } } ans[i] = k; } for (long long int i = 0; i < q; i++) { cout << ans[i] << endl; } } |
// 3rd party code: from Swapforth [1]
//
// Copyright (c) 2015 James Bowman
//
// [1] https://github.com/jamesbowman/swapforth
//
/*
Copyright (c) 2015, James Bowman
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of swapforth nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`define CLKFREQ 12000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
module inpin(
input clk,
input pin,
output rd);
SB_IO #(.PIN_TYPE(6'b0000_00)) _io (
.PACKAGE_PIN(pin),
.INPUT_CLK(clk),
.D_IN_0(rd));
endmodule
module outpin(
input clk,
output pin,
input we,
input wd,
output rd);
SB_IO #(.PIN_TYPE(6'b0101_01)) _io (
.PACKAGE_PIN(pin),
.CLOCK_ENABLE(we),
.OUTPUT_CLK(clk),
.D_OUT_0(wd),
.D_IN_0(rd));
endmodule
|
#include<bits/stdc++.h> #include<math.h> using namespace std; #define ll long long #define endl n #define pb push_back #define eraseO(s, x) if(s.find(x) != s.end()) { s.erase(s.lower_bound(x)); } #define vi vector<int> #define vc vector<char> #define vl vector<ll> #define ip pair<int, int> #define cip pair<int, char> #define vip vector<ip> #define msi multiset<int> #define REP(d, i) for(int i = 0; i < d; ++i) #define REPD(d, i) for(int i = d - 1; i >= 0; i--) #define REPM(d, d1, i, j) for(int i = 0; i < d; ++i){for(int j = 0; j < d1; ++j) #define REPV(v, i) REP(v.size(), i) #define REPVD(v, i) REPD(v.size(), i) #define FOR(d) REP(d, i) #define FORD(d) REPD(d, i) #define FORM(d, d1) REPM(d, d1, i, j) #define FORV(v) REPV(v, i) #define FORVD(v) REPVD(v, i) #define INA(a, d) FOR(d) { cin >> a[i]; } #define INM(a, d, d1) FORM(d, d1) { cin >> a[i][j];}} #define OUTA(a, d) FOR(d) { cout << a[i] << ; } #define OUTV(a) FORV(a) { cout << a[i] << ; } #define OUTM(c, d, d1) FORM(d, d1) { cout << c[i][j] << ; } cout << endl;} void solve() { int n; cin >> n; map<int, int> oc1; map<int, int> ec1; map<int, int> oc2; map<int, int> ec2; set<int> nums; int a[n]; INA(a, n); FOR(n) { if(i % 2) { oc1[a[i]]++; } else { ec1[a[i]]++; } nums.insert(a[i]); } sort(a, a + n); FOR(n) { if(i % 2) { oc2[a[i]]++; } else { ec2[a[i]]++; } } bool ok = 1; for(int i : nums) { if(oc1[i] != oc2[i] || ec1[i] != ec2[i]) { ok = 0; } } if(ok) { cout << YES << endl; } else { cout << NO << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; FOR(t) { solve(); } } |
#include <bits/stdc++.h> inline long long gcd(long long a, long long b) { return (b ? gcd(b, a % b) : a); } inline long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } inline int cmp(double x, double y = 0, double tol = 1e-7) { return (x <= y + tol) ? (x + tol < y) ? -1 : 0 : 1; } using namespace std; const int MAXN = 1e5 + 5; vector<int> adj[MAXN]; int y[MAXN]; int qy[MAXN]; void G(int n, int pai) { y[n] = 0; for (int i = 0; i < adj[n].size(); i++) { int x = adj[n][i]; if (x != pai && adj[x].size() <= 2) G(x, n); } } int main() { int n, a, b, x; cin >> n; for (int i = 0; i < n - 1; i++) { scanf( %d %d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } for (int i = 0; i < MAXN; i++) y[i] = 1; memset(qy, 0, sizeof qy); for (int i = 1; i < n + 1; i++) { if (adj[i].size() == 1 && y[i]) G(i, -1); } for (int i = 1; i < n + 1; i++) { int a = 0, b = 0; for (int j = 0; j < adj[i].size(); j++) { x = adj[i][j]; if (y[x]) a++; else b++; } qy[i] = a + max(b - 2, 0); } bool ans = true; for (int i = 1; i < n + 1; i++) { if (!y[i]) continue; int cnt = 0; for (int j = 0; j < adj[i].size(); j++) { a = adj[i][j]; if (qy[a] > 1) cnt++; } if (cnt > 2) { ans = false; break; } } cout << (ans ? Yes n : No n ); } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// -----------------------------------------------
// False path marker module
// This module creates a level of flops for the
// targetted clock, and cut the timing path to the
// flops using embedded SDC constraint
//
// Only use this module to clock cross the path
// that is being clock crossed properly by correct
// concept.
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_false_path_marker
#(
parameter MARKER_WIDTH = 1
)
(
input reset,
input clk,
input [MARKER_WIDTH - 1 : 0] data_in,
output [MARKER_WIDTH - 1 : 0] data_out
);
(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
assign data_out = data_out_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data_out_reg <= {MARKER_WIDTH{1'b0}};
end
else
begin
data_out_reg <= data_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double sum[2][30][200010]; char A[2][200010]; int main() { int N; cin >> N; cin >> A[0] >> A[1]; for (int i = 0; i < (N); i++) for (int k = 0; k < (2); k++) A[k][i] -= A ; double cont = 0; double val = 0; for (int i = (1); i <= (N); i++) val = N - i + 1, val *= val, cont += val; memset(sum, 0, sizeof(sum)); for (int i = 0; i < (N); i++) { for (int k = 0; k < (2); k++) { sum[k][A[k][i]][i] = ((i == 0) ? 0 : sum[k][A[k][i]][i - 1]) + (i + 1); if (i > 0) { for (char c = 0; c <= 25; c++) { sum[k][c][i] = max(sum[k][c][i], sum[k][c][i - 1]); } } } } double ans = 0; for (int i = 0; i < (N); i++) { for (int k = 0; k < (2); k++) { double* lst = sum[1 - k][A[k][i]]; double val = lst[i - 1]; ans += ((double)(N - i)) * val / cont; } if (A[0][i] == A[1][i]) { ans += ((double)(N - i)) * (i + 1) / cont; } } double vv = ans; cout << fixed << setprecision(12) << vv << endl; } |
#include <bits/stdc++.h> using namespace std; int f[20001][101]; struct node { int ai, bi; } a[1001]; bool cmp(node x, node y) { return x.bi > y.bi; } int main() { int n, sum1 = 0, sum2 = 0, d = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i].ai); sum1 += a[i].ai; } for (int i = 1; i <= n; i++) { scanf( %d , &a[i].bi); } sort(a + 1, a + n + 1, cmp); while (sum1 > sum2) sum2 += a[++d].bi; printf( %d , d); memset(f, 128, sizeof(f)); f[0][0] = 0; for (int i = 1; i <= n; i++) { for (int j = sum2; j >= a[i].bi; j--) { for (int k = 1; k <= d; k++) { f[j][k] = max(f[j][k], f[j - a[i].bi][k - 1] + a[i].ai); } } } int ans = 0; for (int i = sum1; i <= sum2; i++) { ans = max(ans, f[i][d]); } printf( %d n , sum1 - ans); return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module soc_system_up_clocks_0 (
// Inputs
CLOCK_50,
reset,
// Bidirectional
// Outputs
SDRAM_CLK,
VGA_CLK,
sys_clk,
sys_reset_n
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
// Bidirectionals
// Outputs
output SDRAM_CLK;
output VGA_CLK;
output sys_clk;
output sys_reset_n;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 2: 0] sys_mem_clks;
wire clk_locked;
wire video_in_clk;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_System (
// Inputs
.inclk ({1'b0, CLOCK_50}),
// Outputs
.clk (sys_mem_clks),
.locked (clk_locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone IV",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) using std::pair; using std::set; using std::vector; template <class T> inline void read(T &x) { T f = 1; x = 0; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = (x << 1) + (x << 3) + (s & 15); s = getchar(); } x *= f; } template <class T> inline T fabs(T a) { return a > 0 ? a : -a; } template <class T> inline T max(T a, T b) { return a > b ? a : b; } template <class T> inline T min(T a, T b) { return a < b ? a : b; } template <class T> inline T po(T a) { return a * a; } const long long maxn = 1e6 + 5; struct Edge { long long u, v, w; } e[maxn]; inline bool cmp(Edge a, Edge b) { return a.w > b.w; } long long fa[maxn], m, n, cnt, fx, fy, ans, siz[maxn], MAX, val[maxn]; inline long long find(long long x) { return (fa[x] == x) ? x : fa[x] = find(fa[x]); } signed main() { read(n); read(m); for (long long i = 1; i <= n; i++) fa[i] = i, siz[i] = 1, read(val[i]); for (long long i = 1; i <= m; i++) read(e[i].u), read(e[i].v), e[i].w = min(val[e[i].u], val[e[i].v]); std::sort(e + 1, e + m + 1, cmp); for (long long i = 1; i <= m; i++) { fx = find(e[i].u); fy = find(e[i].v); if (fx == fy) continue; ans += siz[fx] * siz[fy] * e[i].w; fa[fx] = fy; siz[fy] += siz[fx]; cnt++; if (cnt == (n - 1)) break; } MAX = ((n * (n - 1)) >> 1); printf( %.6Lf , ((long double)(ans)) / ((long double)(MAX))); } |
#include <bits/stdc++.h> using namespace std; string input; int main() { cin >> input; int last = -1; for (char i = z ; i >= a ; i--) for (int j = last + 1; j < input.length(); j++) if (input[j] == i) { cout << input[j]; last = j; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_TB_V
`define SKY130_FD_SC_HS__NOR4BB_TB_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 C_N = 1'b1;
#200 D_N = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 C_N = 1'b0;
#320 D_N = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D_N = 1'b1;
#440 C_N = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D_N = 1'bx;
#560 C_N = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hs__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pt(/*AUTOARG*/
// Outputs
out0_l, out1_l, pcx_spc_grant_px, so,
// Inputs
in0, in1, pcx_spc_grant_buf_pa, rclk, si, se
);
output [4:0] out0_l;
output out1_l;
output [4:0] pcx_spc_grant_px;
output so;
input [4:0] in0;
input in1;
input [4:0] pcx_spc_grant_buf_pa;
input rclk;
input si, se;
dff_s #(5) dff_ccx_com_spc(
.din (pcx_spc_grant_buf_pa[4:0]),
.q (pcx_spc_grant_px[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
assign out0_l[4:0] = ~in0[4:0];
assign out1_l = ~in1;
endmodule // pcx_grant_ff
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int c = 2; int max = 2; for (int i = 2; i < n; i++) { if (arr[i] == (arr[i - 2] + arr[i - 1])) { c++; if (c > max) { max = c; } } else c = 2; } if (n == 1) cout << 1 ; else cout << max; return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; bool pos = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) pos = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return pos ? x : -x; } const int N = 1 << 18 | 2, M = N; const int mod = 998244353, G = 3; int sz[N], dep[N]; vector<int> v[N]; inline int ksm(int a, int b) { int ans = 1; for (; b; b >>= 1) { if (b & 1) ans = (long long)ans * a % mod; a = (long long)a * a % mod; } return ans; } struct ffter { int wn[N], rev[N]; void init(int n) { int t = 1, L = 0; while (t < n) { t <<= 1; L++; } int w = ksm(G, (mod - 1) / n); for (int i = wn[0] = 1; i < n; i++) { wn[i] = (long long)wn[i - 1] * w % mod; rev[i] = rev[i >> 1] >> 1 | ((i & 1) << (L - 1)); } } void zheng(vector<int> &a) { for (auto &i : a) i = (i + mod) % mod; } void dft(vector<int> &a) { int n = a.size(); zheng(a); for (int i = 0; i < n; i++) if (rev[i] < i) swap(a[rev[i]], a[i]); for (int i = 1; i < n; i <<= 1) { for (int j = 0; j < n; j += i << 1) { for (int k = j, l = 0; l < i; k++, l++) { long long t = (long long)wn[l * (n / (i << 1))] * a[k + i] % mod; a[k + i] = (a[k] < t) ? a[k] - t + mod : a[k] - t; a[k] = a[k] + t >= mod ? a[k] + t - mod : a[k] + t; } } } } void idft(vector<int> &a) { int n = a.size(); dft(a); reverse(a.begin() + 1, a.end()); int zs = ksm(n, mod - 2); for (auto &i : a) i = (long long)i * zs % mod; } } T; void FFT(vector<int> &a, vector<int> &b) { int n = a.size() + b.size() - 1; int len = 1; while (len < n) len <<= 1; T.init(len); a.resize(len); b.resize(len); T.dft(a); T.dft(b); for (int i = 0; i < len; i++) a[i] = (long long)a[i] * b[i] % mod; T.idft(a); a.resize(n); } int n, son[N]; vector<int> tr[M], Tr[M], dp[N], f[N]; void solve(int p); void zy(vector<int> &a, int len) { a.resize(a.size() + len); for (int i = a.size() - 1; i >= len; i--) a[i] = a[i - len]; for (int i = 0; i < len; i++) a[i] = 0; } void bao(int p, int son) { for (auto i : v[p]) if (dep[i] > dep[p] && i != son) solve(i); } vector<int> get(int p, int son) { priority_queue<pair<int, vector<int> > > q; while (q.size()) q.pop(); for (auto i : v[p]) if (dep[i] > dep[p] && i != son) { q.push(make_pair(-dp[i].size(), dp[i])); } if (q.size() == 0) { vector<int> jb(1); jb[0] = 1; return jb; } while (q.size() > 1) { vector<int> a = q.top().second; q.pop(); vector<int> b = q.top().second; q.pop(); FFT(a, b); q.push(make_pair(-a.size(), a)); } vector<int> jb = q.top().second; q.pop(); return jb; } vector<int> operator+(vector<int> a, vector<int> b) { if (a.size() < b.size()) swap(a, b); for (unsigned i = 0; i < b.size(); i++) a[i] = (a[i] + b[i]) % mod; return a; } int TOT; void bao(int l, int r, int nod) { if (l == r) { tr[nod] = f[l]; if (r == TOT) { Tr[nod] = tr[nod]; zy(Tr[nod], 1); } else Tr[nod].resize(1); Tr[nod][0] = 1; return; } int mid = (l + r) >> 1; bao(l, mid, nod << 1); bao(mid + 1, r, nod << 1 | 1); tr[nod] = tr[nod << 1]; FFT(tr[nod], tr[nod << 1 | 1]); FFT(Tr[nod << 1 | 1], tr[nod << 1]); zy(Tr[nod << 1 | 1], mid - l + 1); Tr[nod] = Tr[nod << 1] + Tr[nod << 1 | 1]; } void solve(int p) { int tot = 0, jb = 0; for (int i = p; i; i = son[i]) bao(i, son[i]); for (int i = p; i; i = son[i]) { f[++tot] = get(i, son[i]); } for (int i = 1; i <= tot; i++) jb += f[i].size(); TOT = tot; bao(1, tot, 1); dp[p] = Tr[1]; } void init(int p, int fa) { sz[p] = 1; dep[p] = dep[fa] + 1; for (auto i : v[p]) if (i != fa) { init(i, p); sz[p] += sz[i]; if (sz[i] > sz[son[p]]) son[p] = i; } } int main() { n = read(); int x = read() % mod; for (int i = 1; i < n; i++) { int x = read(), y = read(); v[x].push_back(y); v[y].push_back(x); } init(1, 0); solve(1); vector<int> ans = dp[1]; ans[0]--; int dq = 1, Ans = 0; for (int i = 1; i <= n; i++) { if (i > 1) dq = (long long)dq * (i + x - 1) % mod * ksm(i - 1, mod - 2) % mod; Ans = (Ans + (long long)dq * ans[i]) % mod; } cout << (Ans + mod) % mod << endl; } |
module wb_bfm_master
#(parameter aw = 32,
parameter dw = 32,
parameter Tp = 0,
parameter MAX_BURST_LENGTH = 32)
(
input wb_clk_i,
input wb_rst_i,
output reg [aw-1:0] wb_adr_o,
output reg [dw-1:0] wb_dat_o,
output reg [3:0] wb_sel_o,
output reg wb_we_o,
output reg wb_cyc_o,
output reg wb_stb_o,
output reg [2:0] wb_cti_o,
output reg [1:0] wb_bte_o,
input [dw-1:0] wb_dat_i,
input wb_ack_i,
input wb_err_i,
input wb_rty_i);
`include "wb_bfm_common.v"
reg [aw-1:0] addr;
reg [31:0] index = 0;
reg [dw-1:0] data = {dw{1'b0}};
reg [3:0] mask;
reg op;
reg cycle_type;
reg [2:0] burst_type;
reg [31:0] burst_length;
task reset;
begin
wb_adr_o = {aw{1'b0}};
wb_dat_o = {dw{1'b0}};
wb_sel_o = 4'h0;
wb_we_o = 1'b0;
wb_cyc_o = 1'b0;
wb_stb_o = 1'b0;
wb_cti_o = 3'b000;
wb_bte_o = 2'b00;
end
endtask
task write;
input [aw-1:0] addr_i;
input [dw-1:0] data_i;
input [3:0] mask_i;
output err_o;
begin
addr = addr_i;
data = data_i;
mask = mask_i;
cycle_type = CLASSIC_CYCLE;
op = WRITE;
init;
@(posedge wb_clk_i);
next;
err_o = wb_err_i;
end
endtask //
task write_burst;
input [aw-1:0] addr_i;
input [dw*MAX_BURST_LENGTH-1:0] data_i;
input [3:0] mask_i;
input [31:0] burst_length_i;
input [2:0] burst_type_i;
output err_o;
integer idx;
begin
addr = addr_i;
mask = mask_i;
op = WRITE;
burst_length = burst_length_i;
cycle_type = BURST_CYCLE;
burst_type = burst_type_i;
index = 0;
init;
while(index < burst_length) begin
data = data_i[index*dw+:dw];
next;
addr = next_addr(addr, burst_type);
index = index + 1;
end
wb_cyc_o <= #Tp 1'b0;
wb_stb_o <= #Tp 1'b0;
wb_we_o <= #Tp 1'b0;
wb_cti_o <= #Tp 3'b000;
//last;
end
endtask
task read_burst;
input [aw-1:0] addr_i;
output [dw*MAX_BURST_LENGTH-1:0] data_o;
input [3:0] mask_i;
input [31:0] burst_length_i;
input [2:0] burst_type_i;
output err_o;
integer idx;
begin
addr = addr_i;
mask = mask_i;
op = READ;
burst_length = burst_length_i;
cycle_type = BURST_CYCLE;
burst_type = burst_type_i;
index = 0;
init;
while(index < burst_length) begin
next;
data_o[index*dw+:dw] = data;
addr = next_addr(addr, burst_type);
index = index + 1;
end
wb_cyc_o <= #Tp 1'b0;
wb_stb_o <= #Tp 1'b0;
wb_cti_o <= #Tp 3'b000;
//last;
end
endtask
//Low level tasks
task init;
begin
if(wb_rst_i !== 1'b0) begin
@(negedge wb_rst_i);
@(posedge wb_clk_i);
end
wb_sel_o <= #Tp mask;
wb_we_o <= #Tp op;
wb_cyc_o <= #Tp 1'b1;
if(cycle_type == CLASSIC_CYCLE) begin
wb_cti_o <= #Tp 3'b000;
wb_bte_o <= #Tp 2'b00;
end else if(index == burst_length-1) begin
wb_cti_o <= #Tp 3'b111;
wb_bte_o <= #Tp 2'b00;
end else if(cycle_type == CONSTANT_BURST) begin
wb_cti_o <= #Tp 3'b001;
wb_bte_o <= #Tp 2'b00;
end else begin
wb_cti_o <=# Tp 3'b010;
wb_bte_o <=# Tp burst_type[1:0];
end
end
endtask
task next;
begin
wb_adr_o <= #Tp addr;
wb_dat_o <= #Tp (op === WRITE) ? data : {dw{1'b0}};
wb_stb_o <= #Tp 1'b1; //FIXME: Add wait states
if(cycle_type == CLASSIC_CYCLE) begin
while (wb_ack_i !== 1'b1)
@(posedge wb_clk_i);
data = wb_dat_i;
wb_stb_o <= #Tp 1'b0;
@(negedge wb_ack_i);
end else begin
if(index == burst_length-1)
wb_cti_o <= #Tp 3'b111;
@(posedge wb_clk_i);
while(wb_ack_i !== 1'b1)
@(posedge wb_clk_i);
data = wb_dat_i;
end
end
endtask // while
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)2e5 + 5; vector<int> g[N], son[N]; bool used[N]; int tin[N], tout[N], tup[N]; vector<int> fstep[N]; int start = -1, a, b, c; void dfs(int v, int p) { static int TIME = 0; tin[v] = TIME++; tup[v] = tin[v]; used[v] = true; for (int u : g[v]) { if (u == p) continue; if (used[u]) { tup[v] = min(tup[v], tin[u]); } else { son[v].push_back(u); dfs(u, v); tup[v] = min(tup[v], tup[u]); } } for (int x : g[v]) { fstep[x].clear(); } for (int x : g[v]) { if (tin[x] < tin[v]) { fstep[p].push_back(x); } else { auto it = lower_bound((son[v]).begin(), (son[v]).end(), x, [&](int _x, int __x) { return tout[_x] < tout[__x]; }); if (tup[*it] < tin[v]) fstep[p].push_back(x); else fstep[*it].push_back(x); } } for (int x : g[v]) { if (start == -1 && (int)(fstep[x]).size() >= 3) { start = v; a = fstep[x][0]; b = fstep[x][1]; c = fstep[x][2]; } } tout[v] = TIME++; } bool inPath[N]; int par[N]; bool dfs2(int v, vector<int>& path, function<bool(int)> stop) { if (stop(v)) { path.push_back(v); for (int u = v; par[u] != u; u = par[u]) path.push_back(par[u]); reverse((path).begin(), (path).end()); return true; } used[v] = true; for (int u : g[v]) { if (u != start && !used[u]) { par[u] = v; if (dfs2(u, path, stop)) return true; } } return false; } int main() { int n, m; scanf( %d %d , &n, &m); while (m--) { int u, v; scanf( %d %d , &u, &v); --u; --v; g[u].push_back(v); g[v].push_back(u); } for (int x = 0; x < n; ++x) { if (!used[x]) dfs(x, x); } if (start == -1) { printf( NO n ); return 0; } vector<int> p1; par[a] = a; memset(used, false, sizeof used); dfs2(a, p1, [&](int x) { return x == b; }); for (int x : p1) inPath[x] = true; vector<int> p2; par[c] = c; memset(used, false, sizeof used); dfs2(c, p2, [&](int x) { return inPath[x]; }); int finish = p2.back(); vector<int> out[3]; out[0].push_back(start); for (int pos = 0; p1[pos] != finish; ++pos) out[0].push_back(p1[pos]); out[0].push_back(finish); out[1].push_back(start); for (int pos = (int)(p1).size() - 1; p1[pos] != finish; --pos) out[1].push_back(p1[pos]); out[1].push_back(finish); out[2].push_back(start); for (int x : p2) out[2].push_back(x); printf( YES n ); for (int ii = 0; ii < 3; ++ii) { printf( %d , (int)(out[ii]).size()); for (int x : out[ii]) printf( %d , x + 1); printf( n ); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct el { long long hp, dmg, i; }; bool comp(el a, el b) { return (a.hp - a.dmg) > (b.hp - b.dmg); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n, a, b, i = 0; cin >> n >> a >> b; el sol[n]; for (i = (0); i < (n); i++) { cin >> sol[i].hp >> sol[i].dmg; sol[i].i = i; } sort(sol, sol + n, comp); long long sum = 0; for (i = (0); i < (n); i++) { if (i < b) sum += max(sol[i].hp, sol[i].dmg); else sum += sol[i].dmg; } if (b == 0) { cout << sum << n ; return 0; } long long x = (1LL << a); long long res = sum; for (i = (0); i < (n); i++) { long long temp = res; if (i < b) { temp -= max(sol[i].hp, sol[i].dmg); temp += (sol[i].hp) * x; sum = max(sum, temp); } else { temp -= sol[i].dmg; temp += sol[i].hp * x; temp -= max(sol[b - 1].hp, sol[b - 1].dmg); temp += sol[b - 1].dmg; sum = max(sum, temp); } } cout << sum << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; pair<int, long long> operator+(const pair<int, long long> &A, const pair<int, long long> &B) { return {A.first + B.first, A.second + B.second}; } pair<int, long long> operator-(const pair<int, long long> &A, const pair<int, long long> &B) { return {A.first - B.first, A.second - B.second}; } struct FenwickTree { pair<int, long long> fw[N]; void Update(int i, pair<int, long long> v) { for (i; i < N; i += i & -i) fw[i] = fw[i] + v; } pair<int, long long> Query(int i) { pair<int, long long> ans = {0, 0}; for (i; i > 0; i -= i & -i) ans = ans + fw[i]; return ans; } pair<int, long long> Query(int l, int r) { if (l > r) return {0, 0}; return Query(r) - Query(l - 1); } } active_task; int n, m; int a[N], b[N]; long long t; vector<int> val[N]; int find_index(int x, int r) { int l = 1, f = 0; while (l <= r) { int m = (l + r) >> 1; pair<int, long long> ret = active_task.Query(m); if (ret.first <= x) { f = m; l = m + 1; } else r = m - 1; } return f; } void Solve() { cin >> n >> m >> t; int number = m; pair<int, long long> ans = {t, 0}; for (int i = 1; i <= n; ++i) { cin >> a[i]; b[i] = a[i]; } sort(b + 1, b + n + 1); int bSize = unique(b + 1, b + n + 1) - (b + 1); for (int i = 1; i <= n; ++i) val[a[i]].push_back(i); for (int i = 1; i <= bSize; ++i) { int value = b[i]; for (int idx : val[value]) { active_task.Update(idx, {1, a[idx]}); } int l = 1, r = n, f = -1; while (l <= r) { int m = (l + r) >> 1; pair<int, long long> ret1 = active_task.Query(m); int idx = find_index((ret1.first - 1) / number * number, m); pair<int, long long> ret2 = active_task.Query(idx); long long sum = ret2.second * 2LL + active_task.Query(idx + 1, m).second; if (sum <= t) { l = m + 1; f = m; } else r = m - 1; } if (f != -1) { pair<int, long long> ret = active_task.Query(f); if (ret.first > ans.second) ans = {value, ret.first}; } } cout << ans.second << << ans.first << n ; for (int i = 1; i <= n; ++i) active_task.Update(i, {-1, -a[i]}), val[a[i]].clear(); } int main() { int TC; cin >> TC; while (TC--) { Solve(); } } |
#include<bits/stdc++.h> #define fill(arr,c) memset(arr,c,sizeof(arr)) #define perm(r) next_permutation(all(r)) //it gives bool value ans permute the string lexoggraphically #define sortdesc greater<int>() #define ll long long int //std::setfill( 0 ) << std::setw(5) << 25; it adds leaing zeroes; #define f(i,a) for(ll i=0;i<a;i++) #define fo(i,a) for(ll i=1;i<=a;i++) #define foo(i,x,n,c) for(ll i=x;i<n;i+=c) #define foi(i,x,n,c) for(ll i=x;i>=n;i+=c) #define fauto(i,m) for(auto i:m) #define forall(a) for( auto itr=a.begin();itr!=a.end();itr++) #define ld long double #define in push_back #define mll map<ll,ll> #define mcl map<char,ll> #define msl map<string,ll> #define vi vector<int > #define vl vector<ll > #define vp vector< pair<int,int> > #define vs vector <string> #define vc vector <char> #define o(a) cout<<a #define os(a) cout<<a<< #define en cout<< n ; #define testcase ll t ;cin>>t; while(t--) #define ff first #define ss second #define pl pair<ll,ll> #define pi pair<int,int> #define all(a) (a).begin(), (a).end() #define sz(a) (a).size() #define prec(n) fixed<<setprecision(n) #define mp make_pair #define bitcount __builtin_popcountll #define imin o( imin );en; using namespace std; bool comp(const pair<int,int> &a , const pair<int,int> &b){ if(a.first == b.first) return a.second < b.second; return a.first < b.first; } bool comps(const pair<int,int> &a , const pair<int,int> &b){ if(a.second == b.second) return a.first< b.first; return a.second < b.second; } bool prime[1000005]; void primeseries(ll n) { memset(prime, true, sizeof(prime)); for (ll p=2; p*p<=n; p++) { // If prime[p] is not changed, then it is a prime if (prime[p] == true) { // Update all multiples of p greater than or // equal to the square of it // numbers which are multiple of p and are // less than p^2 are already been marked. for (ll i=p*p; i<=n; i += p) prime[i] = false; } } //return prime; } struct custom_hash { size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); x ^= FIXED_RANDOM; return x ^ (x >> 16); } }; bool compmx(int a, int b) { return (a < b); } // bool isprime(int x){ // for(int i = 2; i*i <= x; i++){ // if(x%i == 0) return false; // } // return true; // } // //ll pi=acos(0.0)*2; void fastio() { ios::sync_with_stdio(0); cin.tie(0); } ll mod=1E9+7; void inout() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif } unsigned long long power(unsigned long long x, int y, int p) { unsigned long long res = 1; // Initialize result x = x % p; // Update x if it is more than or // equal to p while (y > 0) { // If y is odd, multiply x with result if (y & 1) res = (res * x) % p; // y must be even now y = y >> 1; // y = y/2 x = (x * x) % p; } return res; } // Returns n^(-1) mod p unsigned long long modInverse(unsigned long long n, int p) { return power(n, p - 2, p); } // Returns nCr % p using Fermat s little // theorem. unsigned long long nCr(unsigned long long n, int r, int p) { // If n<r, then nCr should return 0 if (n < r) return 0; // Base case if (r == 0) return 1; // Fill factorial array so that we // can find all factorial of r, n // and n-r unsigned long long fac[n + 1]; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } bool chk(ll i,ll a,ll b,ll n) { ll x=i*a+(n-i)*b; bool r=true; while(x) { if(x%10!=a && x%10!=b) return false; x/=10; } return true; } //ll a[1001][1001]; int main() { //fastio(); //os(1);; testcase { ll n,m,u,v; cin>>n>>m>>u>>v; ll a[m]; f(i,m) cin>>a[i]; sort(a,a+m); f(i,m) a[i]++; ll ans=0; if(u>v) { u=n-u+1; v=n-v+1; } ll prev=m; f(i,v) { ll x=upper_bound(a,a+prev,v-i-1)-a; x--; prev=x; if(x>=0) ans++; else break; } o(min(ans,v-u-1)); en; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int size = 31; const int mod = 1e8 + 7; long long hash1[maxn], jec[maxn], hash2[maxn]; int cnt[maxn]; char s[maxn]; int main() { int n; scanf( %d , &n); scanf( %s , s + 1); jec[0] = 1; for (int i = 1; i <= n; ++i) jec[i] = jec[i - 1] * size % mod; for (int i = 1; i <= n; ++i) cnt[i] = cnt[i - 1] + !(s[i] - 0 ); for (int i = 1; i <= n; ++i) { if (s[i] == 0 ) { hash1[i] = hash1[i - 1] * size + ((i & 1) + 0 ); hash2[i] = hash2[i - 1] * size + !(i & 1) + 0 ; hash1[i] %= mod; hash2[i] %= mod; } else { hash1[i] = hash1[i - 1]; hash2[i] = hash2[i - 1]; } } int q; scanf( %d , &q); while (q--) { int l, r, len; scanf( %d%d%d , &l, &r, &len); long long p, pp; if (l & 1) p = (hash1[l + len - 1] - hash1[l - 1] * jec[cnt[l + len - 1] - cnt[l - 1]] % mod + mod) % mod; else p = (hash2[l + len - 1] - hash2[l - 1] * jec[cnt[l + len - 1] - cnt[l - 1]] % mod + mod) % mod; if (r & 1) pp = (hash1[r + len - 1] - hash1[r - 1] * jec[cnt[r + len - 1] - cnt[r - 1]] % mod + mod) % mod; else pp = (hash2[r + len - 1] - hash2[r - 1] * jec[cnt[r + len - 1] - cnt[r - 1]] % mod + mod) % mod; if (p == pp) printf( Yes n ); else printf( No n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; bool prime(int n) { for (int i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } int main() { int n; cin >> n; if (prime(n)) { cout << 1 << n << n << endl; return 0; } if (prime(n - 2)) { cout << 2 << n << 2 << n << n - 2 << endl; return 0; } cout << 3 << n << 3 << endl; n -= 3; for (int i = 2; i <= n; i++) { if (prime(i) and prime(n - i)) { cout << i << n << n - i << endl; break; } } return 0; } |
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
`default_nettype wire
module Frix(
input wire CLOCK_100,
input wire RST_IN,
// PSRAM
output wire PSRAM_CLK,
output wire PSRAM_ADV_N,
output wire PSRAM_CE_N,
output wire PSRAM_OE_N,
output wire PSRAM_WE_N,
output wire PSRAM_LB_N,
output wire PSRAM_UB_N,
inout wire [15:0] PSRAM_DATA,
output wire [22:0] PSRAM_ADDR,
//PS2 KEYBOARD
inout wire PS2_CLK,
inout wire PS2_DAT,
//SD
output wire SD_CLK,
inout wire SD_CMD,
inout wire [3:0] SD_DAT,
input wire SD_CD,
output wire SD_RESET,
//VGA
output wire VGA_HS,
output wire VGA_VS,
output wire [3:0] VGA_R,
output wire [3:0] VGA_G,
output wire [3:0] VGA_B,
//LED
output reg [15:0] LED
);
//------------------------------------------------------------------------------
wire clk_sys;
wire clk_vga;
wire clk_sound;
wire rst;
wire rst_n;
assign DRAM_CLK = clk_sys;
GEN gen(
.CLK_IN (CLOCK_100),
.RST_X_IN (~RST_IN),
.CLK_OUT (clk_sys),
.VGA_CLK_OUT (clk_vga),
.RST_X_OUT (rst_n)
);
assign SD_RESET = rst;
assign rst = ~rst_n;
//------------------------------------------------------------------------------
wire ao486_reset;
wire [7:0] VGA_R_8, VGA_G_8, VGA_B_8;
assign VGA_R = VGA_R_8[7:4];
assign VGA_G = VGA_G_8[7:4];
assign VGA_B = VGA_B_8[7:4];
//------------------------------------------------------------------------------
reg [25:0] cnt;
always @(posedge clk_sys) cnt <= cnt + 1;
always @(posedge clk_sys) begin
LED[0] <= cnt[25];
LED[1] <= ~rst;
LED[2] <= ~ao486_reset;
LED[3] <= ~SD_CD;
LED[4] <= ~SD_RESET;
LED[9:5] <= {~SD_CMD, ~SD_DAT};
LED[13:10] <= {~PSRAM_CE_N, ~PSRAM_OE_N, ~PSRAM_WE_N, ~PSRAM_ADV_N};
LED[15:14] <= {~PS2_CLK, ~PS2_DAT};
end
//------------------------------------------------------------------------------
system u0(
.clk_sys (clk_sys),
.reset_sys (rst),
.clk_vga (clk_vga),
.reset_vga (rst),
.vga_clock (VGA_CLK),
.vga_horiz_sync (VGA_HS),
.vga_vert_sync (VGA_VS),
.vga_r (VGA_R_8),
.vga_g (VGA_G_8),
.vga_b (VGA_B_8),
.PSRAM_CLK (PSRAM_CLK),
.PSRAM_ADV_N (PSRAM_ADV_N),
.PSRAM_CE_N (PSRAM_CE_N),
.PSRAM_OE_N (PSRAM_OE_N),
.PSRAM_WE_N (PSRAM_WE_N),
.PSRAM_LB_N (PSRAM_LB_N),
.PSRAM_UB_N (PSRAM_UB_N),
.PSRAM_DATA (PSRAM_DATA),
.PSRAM_ADDR (PSRAM_ADDR),
.sd_clk (SD_CLK),
.sd_dat (SD_DAT),
.sd_cmd (SD_CMD),
.ps2_kbclk (PS2_CLK),
.ps2_kbdat (PS2_DAT),
.reset_only_ao486 (ao486_reset)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_1_V
`define SKY130_FD_SC_LP__A21BO_1_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_1_V
|
#include <bits/stdc++.h> using namespace std; const int mxN = 1000000; int a[mxN]; void solve() { int n, k; cin >> n >> k; int idx = ceil((double)n / 2); int sub = (n - idx) + 1; for (int i = 0; i < n * k; i++) { cin >> a[i]; } long long ans = 0, cnt = 0; for (int i = n * k - sub; cnt < k; i -= sub) { ans += a[i]; cnt++; } cout << ans << n ; } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:49:19 05/27/2016
// Design Name:
// Module Name: prueba_lectura_rtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prueba_lectura_rtc
(
input wire clk, reset,
inout [7:0]dato,
output wire AD, CS, WR, RD,
output [7:0]port_id,out_port,wire_in_port,
output reg[7:0]fin_lectura_escritura,
output hold_seg_hora,
output [7:0] RGB,
output hsync, vsync
);
//Conexiones internas
reg [7:0]in_port;
assign wire_in_port = in_port;
//wire [7:0]out_port;
//wire [7:0]port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
// conexiones banco de registros a VGA
wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha,out_dia_semana;
wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
//////////////////////////// hold's
//wire hold_seg_hora;
wire hold_min_hora;
wire hold_hora_hora;
wire hold_dia_fecha;
wire hold_mes_fecha;
wire hold_jahr_fecha;
wire hold_dia_semana;
wire hold_seg_timer;
wire hold_min_timer;
wire hold_hora_timer;
// wire hold_banderas_config;
//////////////////////
wire flag_done;
//reg [7:0]fin_lectura_escritura;
wire [7:0]wire_out_dato;
reg state_reg_flag,state_next_flag;
assign interrupt = 1'b0;
microcontrolador instancia_microcontrolador
(
.clk(clk),
.reset(reset),
.interrupt(interrupt),
.in_port(in_port),
.write_strobe(write_strobe),
.k_write_strobe(),
.read_strobe(read_strobe),
.interrupt_ack(),
.port_id(port_id),
.out_port(out_port)
);
controlador_VGA instancia_controlador_VGA
(
.clock(clk),
.reset(reset),
.digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
.digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
.digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
.AM_PM(1'b0),
.config_mode(2'b0),
.cursor_location(2'b0),
.formato_hora(1'b1),
.estado_alarma(1'b0),
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
memoria_registros_VGA instancia_memoria_registros_VGA
(
.clk(clk),
.reset(reset),
.cs_seg_hora(1'b0),
.cs_min_hora(1'b0),
.cs_hora_hora(1'b0),
.cs_dia_fecha(1'b0),
.cs_mes_fecha(1'b0),
.cs_jahr_fecha(1'b0),
.cs_seg_timer(1'b0),
.cs_min_timer(1'b0),
.cs_hora_timer(1'b0),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer),
.hold_banderas_config(1'b1),
.data_PicoBlaze(out_port),
.count_seg_hora(8'b0),
.count_min_hora(8'b0),
.count_hora_hora(8'b0),
.count_dia_fecha(8'b0),
.count_mes_fecha(8'b0),
.count_jahr_fecha(8'b0),
.count_seg_timer(8'b0),
.count_min_timer(8'b0),
.count_hora_timer(8'b0),
.out_seg_hora(out_seg_hora),
.out_min_hora(out_min_hora),
.out_hora_hora(out_hora_hora),
.out_dia_fecha(out_dia_fecha),
.out_mes_fecha(out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_seg_timer(out_seg_timer),
.out_min_timer(out_min_timer),
.out_hora_timer(out_hora_timer),
.out_banderas_config()
);
deco_hold_registros instancia_deco_hold_registros (
.write_strobe(write_strobe),
.port_id(port_id),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer)
);
escritor_lector_rtc instancia_escritor_lector_rtc (
.clk(clk),
.reset(reset),
.port_id(port_id),
.in_dato(out_port),
.write_strobe(write_strobe),
.read_strobe(read_strobe),
.reg_a_d(AD),
.reg_cs(CS),
.reg_rd(RD),
.reg_wr(WR),
.out_dato(wire_out_dato),
.flag_done(flag_done),
.dato(dato)
);
always @ (posedge clk)
begin
case (port_id)
8'h0F : in_port <= fin_lectura_escritura;
8'h10 : in_port <= wire_out_dato;
default : in_port <= 8'bXXXXXXXX ;
endcase
end
/// maquina de estados para manipular fin lectura escritura
always @ (negedge clk,posedge reset) begin
if (reset) state_reg_flag = 1'b0;
else state_reg_flag = state_next_flag;
end
always@ (*) begin
state_next_flag = state_reg_flag;
case (state_reg_flag)
1'b0: begin
fin_lectura_escritura = 8'h00;
if (flag_done == 1) state_next_flag = 1'b1;
else state_next_flag = 1'b0;
end
1'b1: begin
fin_lectura_escritura = 8'h01;
if(port_id == 8'h0F && read_strobe == 1) state_next_flag = 1'b0;
else state_next_flag = 1'b1;
end
endcase
end
endmodule
|
// File: fpgalink_nexys.v
// Generated by MyHDL 0.9dev
// Date: Sun Sep 8 22:41:53 2013
`timescale 1ns/10ps
module fpgalink_nexys (
IFCLK,
RST,
SLWR,
SLRD,
SLOE,
FDI,
FDO,
FDS,
ADDR,
FLAGA,
FLAGB,
FLAGC,
FLAGD,
PKTEND,
LEDS
);
//
input IFCLK;
input RST;
output SLWR;
wire SLWR;
output SLRD;
wire SLRD;
output SLOE;
reg SLOE;
input [7:0] FDI;
output [7:0] FDO;
reg [7:0] FDO;
output FDS;
reg FDS;
output [1:0] ADDR;
reg [1:0] ADDR;
input FLAGA;
input FLAGB;
input FLAGC;
input FLAGD;
output PKTEND;
reg PKTEND;
output [7:0] LEDS;
reg [7:0] LEDS;
reg [23:0] tcnt;
reg f2hValid_in;
reg h2fReady_in;
reg fifosel;
reg [7:0] h2fData_out;
reg h2fValid_out;
reg [6:0] chanAddr_out;
reg [0:0] treg;
reg [6:0] lreg;
reg [7:0] f2hData_in;
reg g_fli_is_write;
reg [3:0] g_fli_state;
reg [31:0] g_fli_count;
reg g_fli_is_aligned;
reg [1:0] g_fli_fifop;
reg g_fli_flbus_ready_o;
always @(posedge IFCLK, negedge RST) begin: FPGALINK_NEXYS_G_FLI_HDL_SM
if (RST == 0) begin
g_fli_count <= 0;
FDO <= 0;
h2fValid_out <= 0;
h2fData_out <= 0;
g_fli_is_write <= 0;
g_fli_fifop <= 3;
g_fli_flbus_ready_o <= 0;
FDS <= 0;
g_fli_state <= 4'b0000;
chanAddr_out <= 0;
fifosel <= 0;
PKTEND <= 0;
g_fli_is_aligned <= 0;
end
else begin
case (g_fli_state)
4'b0001: begin
if (FLAGC) begin
g_fli_count <= (FDI << 24);
g_fli_state <= 4'b0010;
end
else begin
g_fli_count <= 0;
end
end
4'b0010: begin
if (FLAGC) begin
g_fli_count <= (g_fli_count | (FDI << 16));
g_fli_state <= 4'b0011;
end
end
4'b0011: begin
if (FLAGC) begin
g_fli_count <= (g_fli_count | (FDI << 8));
g_fli_state <= 4'b0100;
end
end
4'b0100: begin
if (FLAGC) begin
g_fli_count <= (g_fli_count | FDI);
if (g_fli_is_write) begin
g_fli_state <= 4'b0101;
end
else begin
if (h2fReady_in) begin
g_fli_fifop <= 2;
g_fli_state <= 4'b1001;
end
else begin
g_fli_fifop <= 3;
g_fli_state <= 4'b1010;
end
end
end
end
4'b0101: begin
fifosel <= 1;
g_fli_fifop <= 3;
if ((g_fli_count[9-1:0] == 0)) begin
g_fli_is_aligned <= 1'b1;
end
else begin
g_fli_is_aligned <= 1'b0;
end
g_fli_state <= 4'b0110;
end
4'b0110: begin
if (FLAGB) begin
g_fli_flbus_ready_o <= 1'b1;
end
if ((FLAGB && f2hValid_in)) begin
g_fli_fifop <= 1;
FDO <= f2hData_in;
FDS <= 1'b1;
g_fli_count <= (g_fli_count - 1);
if ((g_fli_count == 1)) begin
if (g_fli_is_aligned) begin
g_fli_state <= 4'b0111;
end
else begin
g_fli_state <= 4'b1000;
end
end
end
else begin
g_fli_fifop <= 3;
end
end
4'b0111: begin
fifosel <= 1;
g_fli_fifop <= 3;
g_fli_state <= 4'b0000;
end
4'b1000: begin
fifosel <= 1;
g_fli_fifop <= 3;
PKTEND <= 1'b0;
g_fli_state <= 4'b0000;
end
4'b1001: begin
fifosel <= 0;
if ((FLAGC && h2fReady_in)) begin
if ((!SLRD) !== 1) begin
$display("*** AssertionError ***");
end
h2fValid_out <= 1'b1;
h2fData_out <= FDI;
if ((g_fli_count <= 1)) begin
g_fli_state <= 4'b0000;
g_fli_count <= 0;
end
else begin
g_fli_count <= (g_fli_count - 1);
end
end
end
4'b1010: begin
if ((FLAGC && h2fReady_in)) begin
g_fli_state <= 4'b1001;
g_fli_fifop <= 2;
end
end
default: begin
g_fli_fifop <= 2;
g_fli_count <= 0;
h2fValid_out <= 1'b0;
if (FLAGC) begin
chanAddr_out <= FDI[7-1:0];
g_fli_is_write <= FDI[7];
g_fli_state <= 4'b0001;
end
end
endcase
end
end
assign SLRD = g_fli_fifop[0];
assign SLWR = g_fli_fifop[1];
always @(posedge IFCLK, negedge RST) begin: FPGALINK_NEXYS_HDL_FL
if (RST == 0) begin
tcnt <= 0;
treg <= 0;
lreg <= 0;
end
else begin
if ((h2fValid_out && (chanAddr_out == 1))) begin
lreg <= h2fData_out;
end
tcnt <= (tcnt + 1);
if (tcnt[23]) begin
treg <= (!treg);
end
end
end
always @(treg, chanAddr_out, fifosel, lreg, SLRD) begin: FPGALINK_NEXYS_HDL_ASSIGNS
ADDR[0] = 1'b0;
ADDR[1] = fifosel;
SLOE = SLRD;
f2hValid_in = 1'b1;
h2fReady_in = 1'b1;
LEDS[7-1:0] = lreg;
LEDS[7] = treg;
case (chanAddr_out)
'h0: begin
f2hData_in = 206;
end
'h1: begin
f2hData_in = lreg;
end
default: begin
f2hData_in = 85;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int low, up, x, n; int vec[16]; int recurse(int i, int a, int b, int s, int cnt) { if (i == n) { if (cnt >= 2 && low <= s && s <= up && a - b >= x) { return 1; } return 0; } return recurse(i + 1, max(a, vec[i]), min(b, vec[i]), s + vec[i], cnt + 1) + recurse(i + 1, a, b, s, cnt); } int main() { scanf( %d , &n); scanf( %d , &low); scanf( %d , &up); scanf( %d , &x); for (int i = 0; i <= n - 1; ++i) scanf( %d , &vec[i]); printf( %d n , recurse(0, INT_MIN, INT_MAX, 0, 0)); return 0; } |
#include <bits/stdc++.h> using namespace std; long long i, j, n, m, f1, f2, t, k, a, b, x1, x2, w; long long ans = -1; vector<long long> vis; vector<vector<long long>> adj; long long dfs(long long v) { vis[v] = 1; long long value = 1; for (long long u : adj[v]) { if (!vis[u]) { value += dfs(u); } } if (value % 2 == 0) ans++; return value; } int main() { t = 1; while (t--) { cin >> n; adj.assign(n + 1, {}); vis.assign(n + 1, 0); for (i = 1; i < n; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } if (n & 1) { cout << -1; return 0; } dfs(1); cout << ans; } } |
#include <bits/stdc++.h> using namespace std; const int N = 200; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, cnt, flag = 1; int a[N], b[N], c[N]; int main() { cnt = n = read(); a[0] = -1, b[0] = 0; while (cnt--) { for (int i = 0; i < N - 1; i++) c[i + 1] = a[i]; c[0] = 0; for (int i = 0; i < N; i++) c[i] += b[i]; for (int i = 0; i < N; i++) if (abs(c[i]) > 1) { for (int i = 0; i < N - 1; i++) c[i + 1] = a[i] * (-1); c[0] = 0; for (int i = 0; i < N; i++) c[i] += b[i]; break; } for (int i = 0; i < N; i++) b[i] = a[i], a[i] = c[i]; } cout << n << endl; if (a[n] < 0) flag = -1; else flag = 1; for (int i = 0; i <= n; i++) cout << a[i] * flag << ; cout << endl << n - 1 << endl; if (b[n - 1] < 0) flag = -1; else flag = 1; for (int i = 0; i <= n - 1; i++) cout << b[i] * flag << ; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 5009; string s[MAX]; int n, m, b[MAX], ans, a[MAX]; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < m; i++) { memset(a, 0, sizeof a); for (int j = 0; j < n; j++) if (s[j][i] == 1 ) b[j]++, a[b[j]]++; else b[j] = 0; for (int i = m; i >= 0; i--) a[i] += a[i + 1], ans = max(ans, a[i] * i); } cout << ans; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFSBP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_BLACKBOX_V
|
//==================================================================================================
// Filename : clk_generator.v
// Created On : 2015-02-07 21:17:35
// Last Modified : 2015-05-24 22:49:47
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Generate the two main clocks:
// - Bus and peripherals.
// - Core. This clock is equal to Bus clock divided by 2.
//==================================================================================================
module clk_generator(
input clk_i, // input clock
output reg clk_core, // core clock
output clk_bus // bus clock
);
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign clk_bus = clk_i;
//--------------------------------------------------------------------------
// Initialization
//--------------------------------------------------------------------------
initial begin
clk_core <= 1'b0;
end
//--------------------------------------------------------------------------
// divide the clock
//--------------------------------------------------------------------------
always @(posedge clk_i ) begin
clk_core <= !clk_core;
end
endmodule
|
`timescale 1ns / 1ps
`define intN 16
`include "primitives.v"
`include "tests_fibl.v"
module top(
input clk,
input [15:0] in,
output [15:0] out
);
reg `intT a = 0;
wire `intT a_in = in[4:0];
wire `intT b;
reg [26:0] div = 0;
reg in_valid;
assign out = b;
always @(posedge clk) begin
if(in[15]) begin
div <= div + 1;
if(div == 0) begin
if(a == 24) begin
a <= 0;
end
else begin
a <= a + 1;
end
`set(in_valid);
end
else begin
`reset(in_valid);
end
end
else if(a != a_in && a_in <= 24)
begin
a <= a_in;
`set(in_valid);
end
else
begin
`reset(in_valid);
end
end
`inst_sync(tests_fibl, fibl, #())(`sync(in_valid, `true), .in0(a), .out0(b));
endmodule
|
#include <bits/stdc++.h> const int MAXN = 100005; int n, val[MAXN], ch[MAXN][2], fa[MAXN], maxv[MAXN], size[MAXN], root; inline int max(int a, int b) { return a > b ? a : b; } inline int min(int a, int b) { return a > b ? b : a; } inline void maintain(int x) { size[x] = size[ch[x][0]] + size[ch[x][1]] + 1; maxv[x] = max(max(maxv[ch[x][0]], maxv[ch[x][1]]), val[x]); } void rotate(int x) { int y = fa[x], d = ch[y][1] == x; if (fa[x] = fa[y]) ch[fa[y]][ch[fa[y]][1] == y] = x; if (ch[y][d] = ch[x][d ^ 1]) fa[ch[y][d]] = y; fa[ch[x][d ^ 1] = y] = x; maintain(y), maintain(x); } void splay(int &rt, int x) { int f = fa[rt], y, z; while ((y = fa[x]) != f && (z = fa[y]) != f) { rotate((ch[z][1] == y) == (ch[y][1] == x) ? y : x); rotate(x); } if (y != f) rotate(x); rt = x; } void select(int &rt, int k) { int x = rt; while (size[ch[x][0]] + 1 != k) { if (k <= size[ch[x][0]]) x = ch[x][0]; else { k -= size[ch[x][0]] + 1; x = ch[x][1]; } } splay(rt, x); } void getPos(int &rt, int v) { int x = rt; while (true) { if (ch[x][1] && maxv[ch[x][1]] > v) x = ch[x][1]; else if (ch[x][0] && val[x] <= v) x = ch[x][0]; else break; } splay(rt, x); } void insert(int &rt, int p, int pos) { if (!pos) { select(rt, 1); fa[ch[rt][0] = p] = rt; rotate(p); rt = p; return; } select(rt, pos); int tmp = ch[rt][1]; if (!tmp) { fa[ch[rt][1] = p] = rt; rotate(p); rt = p; return; } fa[ch[rt][1] = p] = rt; fa[ch[p][1] = tmp] = p; splay(rt, tmp); } void traverse(int x) { if (!x) return; traverse(ch[x][0]); printf( %d , x); traverse(ch[x][1]); } int main() { int tmp, i; scanf( %d , &n); for (i = 1; i <= n; ++i) { scanf( %d%d , &val[i], &tmp); if (i == 1) { size[root = 1] = 1; maxv[1] = val[1]; continue; } getPos(root, val[i]); if (val[root] < val[i]) insert(root, i, i - 1 - min(tmp, i - 1)); else insert(root, i, i - 1 - min(tmp, size[ch[root][1]])); } traverse(root); return 0; } |
#include <bits/stdc++.h> using namespace std; bool isGeometrical(int *a, int n) { if (a[0] == 0) { for (int i = 0; i < n; i++) if (a[i] != 0) return false; return true; } for (int i = 0; i < n - 1; i++) if (a[i + 1] * a[0] != a[i] * a[1]) return false; return true; } int main() { int n; scanf( %d , &n); int a[100000], num0 = 0, pos0 = -1; for (int i = 0; i < n; i++) { scanf( %d , a + i); if (a[i] == 0) { num0++; if (pos0 == -1) pos0 = i; } } if (n <= 2) { printf( %d n , isGeometrical(a, n) ? 0 : 1); return 0; } if (n == 3) { int ans = 2; if (isGeometrical(a, n)) ans = 0; else { int b[2]; b[0] = a[0], b[1] = a[1]; if (isGeometrical(b, 2)) ans = 1; b[0] = a[0], b[1] = a[2]; if (isGeometrical(b, 2)) ans = 1; b[0] = a[1], b[1] = a[2]; if (isGeometrical(b, 2)) ans = 1; } printf( %d n , ans); return 0; } if (num0 >= 2) { int cnt = 0; for (int i = 1; i < n; i++) if (a[i] != 0) cnt++; printf( %d n , min(cnt, 2)); return 0; } if (num0 == 1) { for (int i = pos0; i < n - 1; i++) a[i] = a[i + 1]; printf( %d n , isGeometrical(a, n - 1) ? 1 : 2); return 0; } if (isGeometrical(a, n)) { puts( 0 ); return 0; } if (isGeometrical(a + 1, n - 1)) { puts( 1 ); return 0; } swap(a[0], a[1]); if (isGeometrical(a + 1, n - 1)) { puts( 1 ); return 0; } swap(a[0], a[1]); int cnt = 0; for (int i = 0; i < n - 1; i++) { if (a[i + 1] * a[0] != a[i] * a[1]) { cnt++; a[i + 1] = a[i]; } if (cnt == 2) break; } printf( %d n , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; long long maxi = INT_MIN; while (n--) { long long x, y; cin >> x >> y; long long sum = x + y; if (sum > maxi) { maxi = sum; } } cout << maxi << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) cout << (a[i] + a[i + 1]) << ; cout << a[n - 1]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_1_V
`define SKY130_FD_SC_LP__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_1_V
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 100005; long long A[MaxN][(1 << (5))], B[MaxN][(1 << (5))], dp[MaxN][(1 << (5))]; const long long Inf = 1LL << 60; int main() { int N, M; scanf( %d%d , &N, &M); for (int i = 0; i < M - 1; i++) for (int j = 0; j < N; j++) { int x; scanf( %d , &x); for (int k = 0; k < (1 << (N)); k++) if (k & (1 << (j))) A[i][k] += x; } for (int i = 0; i < M; i++) for (int j = 0; j < N; j++) { int x; scanf( %d , &x); for (int k = 0; k < (1 << (N)); k++) if (((k & (1 << (j))) == 0) ^ ((k & (1 << ((j + 1) % N))) == 0)) B[i][k] += x; } for (int i = 0; i <= M; i++) for (int j = 0; j < (1 << (N)); j++) dp[i][j] = Inf; dp[0][0] = 0; for (int i = 1; i < M; i++) for (int j = 0; j < (1 << (N)); j++) { dp[i][j] = min(dp[i][j], A[i - 1][j] + B[i][j]); for (int k = j; k > 0; k -= k & (-k)) dp[i][j] = min(dp[i][j], dp[i - 1][k] + A[i - 1][k ^ j] + B[i][j]); } printf( %I64d n , dp[M - 1][(1 << (N)) - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, x; vector<long long> a; void ans() { for (int i = 0; i < n; i++) { cout << a[i] << ; } exit(0); } int main(int argc, char* argv[]) { srand((unsigned int)time(NULL)); cin >> n >> k >> x; a.resize(n); int ch = 1; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] < 0) { ch *= -1; } } if (ch == 1) { set<pair<long long, int> > s; for (int i = 0; i < n; i++) { if (a[i] >= 0) { s.insert({abs(-1 - a[i]), i}); } else { s.insert({abs(1 - a[i]), i}); } } auto q = *s.begin(); int id = q.second; if (a[id] >= 0) { while (a[id] >= 0) { a[id] -= x; k--; if (k == 0) { ans(); } } } else { while (a[id] <= 0) { a[id] += x; k--; if (k == 0) { ans(); } } } } set<pair<long long, int> > s; for (int i = 0; i < n; i++) { s.insert({abs(a[i]), i}); } while (k > 0) { auto q = *s.begin(); s.erase(s.begin()); int id = q.second; if (a[id] >= 0) { a[id] += x; } else { a[id] -= x; } k--; s.insert({abs(a[id]), id}); } ans(); } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input [2:0] vol_select,
input play,
input reset,
input palmode,
output sdout,
output lrck,
output mclk,
output sclk,
output DAC_STATUS
);
reg[8:0] dac_address_r;
reg[8:0] dac_address_r_sync;
wire[8:0] dac_address = dac_address_r_sync;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[10:0] vol_reg;
reg[10:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
reg [8:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
assign mclk = cnt[2]; // mclk = clk/8
assign lrck = cnt[8]; // lrck = mclk/128
assign sclk = cnt[3]; // sclk = lrck*32
reg [2:0] lrck_sreg;
reg [2:0] sclk_sreg;
wire lrck_rising = (lrck_sreg[1:0] == 2'b01);
wire lrck_falling = (lrck_sreg[1:0] == 2'b10);
wire sclk_rising = (sclk_sreg[1:0] == 2'b01);
wire sclk_falling = (sclk_sreg[1:0] == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg [1:0] reset_sreg;
wire reset_rising = (reset_sreg[1:0] == 2'b01);
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b11;
sclk_sreg = 1'b0;
dac_address_r = 9'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 9'h000;
vol_target_reg = 9'h000;
samples <= 2'b00;
end
/*
21477272.727272... / 37500 * 77 = 44100
21281370 / 709379 * 1470 = 44100
*/
reg [19:0] phaseacc = 0;
wire [10:0] phasemul = (palmode ? 1470 : 77);
wire [19:0] phasediv = (palmode ? 709379 : 37500);
always @(posedge clkin) begin
if(reset_rising) begin
dac_address_r <= 0;
phaseacc <= 0;
end else if(sysclk_rising) begin
if(phaseacc >= phasediv) begin
phaseacc <= phaseacc - phasediv;
dac_address_r <= dac_address_r + play_r;
end else begin
phaseacc <= phaseacc + phasemul;
end
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[1:0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
reset_sreg <= {reset_sreg[0], reset};
end
wire [9:0] vol_orig = volume + volume[7];
wire [9:0] vol_3db = volume + volume[7:1] + volume[7];
wire [9:0] vol_6db = {1'b0, volume, volume[7]} + volume[7];
wire [9:0] vol_9db = {1'b0, volume, 1'b0} + volume + volume[7:6];
wire [9:0] vol_12db = {volume, volume[7:6]};
reg [9:0] vol_scaled;
always @* begin
case(vol_select)
3'b000: vol_scaled = vol_orig;
3'b001: vol_scaled = vol_3db;
3'b010: vol_scaled = vol_6db;
3'b011: vol_scaled = vol_9db;
3'b100: vol_scaled = vol_12db;
default: vol_scaled = vol_orig;
endcase
end
always @(posedge clkin) begin
vol_target_reg <= vol_scaled;
end
always @(posedge clkin) begin
if (lrck_rising) begin
dac_address_r_sync <= dac_address_r;
end
end
// ramp volume only on sample boundaries
always @(posedge clkin) begin
if (lrck_rising) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
wire signed [15:0] dac_data_ch = lrck ? dac_data[31:16] : dac_data[15:0];
wire signed [25:0] vol_sample;
wire signed [15:0] vol_sample_sat;
assign vol_sample = dac_data_ch * $signed({1'b0, vol_reg});
assign vol_sample_sat = ((vol_sample[25:23] == 3'b000 || vol_sample[25:23] == 3'b111) ? vol_sample[23:8]
: vol_sample[25] ? 16'sh8000
: 16'sh7fff);
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising | lrck_falling) begin
smpshift <= vol_sample_sat;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > adjl(500000); int s[500000] = {0}; long long int a[500000] = {0}; map<pair<int, int>, long long int> mp; int vis[500000] = {0}; void dfs(int n, vector<pair<int, int> > &ans, int p, long long int sum, long long int mini) { if (sum - mini > a[n]) { ans.push_back(make_pair(n, p)); } for (int i = 0; i < adjl[n].size(); i++) { int ch = adjl[n][i]; if (ch != p) { dfs(ch, ans, n, sum + mp[make_pair(ch, n)], min(mini, sum + mp[make_pair(ch, n)])); } } } void dfs1(int n, int p, int &count) { vis[n] = 1; count++; for (int i = 0; i < adjl[n].size(); i++) { int ch = adjl[n][i]; if (ch != p) { dfs1(ch, n, count); } } } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i + 1]; } for (int i = 0; i < (n - 1); i++) { int a, c; cin >> a >> c; adjl[a].push_back(i + 2); adjl[i + 2].push_back(a); mp[make_pair(a, i + 2)] = c; mp[make_pair(i + 2, a)] = c; } vector<pair<int, int> > ans; dfs(1, ans, -1, 0, 0); long long int ans1 = 0; for (int i = 0; i < ans.size(); i++) { if (!vis[ans[i].first]) { int count = 0; dfs1(ans[i].first, ans[i].second, count); ans1 += count; } } cout << ans1 << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, t; cin >> t; for (long long int aa = 0; aa < t; aa++) { long long int n, k, d; cin >> n >> k >> d; long long int mini = k; vector<long long int> v(n); map<long long int, long long int> m; for (i = 0; i < n; i++) { cin >> v[i]; if (i < d) { long long int ss = m.size(); m[v[i]]++; if (ss < m.size()) m[v[i]] = 1; } } m.size() < mini ? mini = m.size() : mini = mini; for (i = 1; i < n - d + 1; i++) { m[v[i - 1]]--; if (m[v[i - 1]] == 0) m.erase(v[i - 1]); long long int ss = m.size(); m[v[i + d - 1]]++; if (ss < m.size()) m[v[i + d - 1]] = 1; m.size() < mini ? mini = m.size() : mini = mini; } m.size() < mini ? mini = m.size() : mini = mini; cout << mini << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long long int ll; typedef unsigned long long int ull; inline void smax(int &x, int y) { x = max(x, y); } inline void smin(int &x, int y) { x = min(x, y); } ll gcd(ll a, ll b) { return ((b == 0) ? a : gcd(b, a % b)); } ll n, m, a, b; vector<vector<int> > gr; vector<int> vis; ll con = 0; int dfs(int s, int prt) { vis[s] = 1; con++; int f = 0; if (prt == s) f = 1; for (__typeof(gr[s].size()) i = (0) - ((0) > (gr[s].size())); i != (gr[s].size()) - ((0) > (gr[s].size())); i += 1 - 2 * ((0) > (gr[s].size()))) { int x = gr[s][i]; if (!vis[x]) { if (dfs(x, prt) == 1) f = 1; } } return f; } int main() { std::ios::sync_with_stdio(false); cin.tie(NULL); int tcase; cin >> tcase; for (__typeof(tcase + 1) tc = (1) - ((1) > (tcase + 1)); tc != (tcase + 1) - ((1) > (tcase + 1)); tc += 1 - 2 * ((1) > (tcase + 1))) { cin >> n >> m >> a >> b; gr.resize(0); vis.resize(0); gr.resize(n + 1); vis.resize(n + 1); for (__typeof(m) i = (0) - ((0) > (m)); i != (m) - ((0) > (m)); i += 1 - 2 * ((0) > (m))) { int x, y; cin >> x >> y; gr[x].push_back(y); gr[y].push_back(x); } ll con1 = 0; vis[a] = 1; for (__typeof(gr[a].size()) i = (0) - ((0) > (gr[a].size())); i != (gr[a].size()) - ((0) > (gr[a].size())); i += 1 - 2 * ((0) > (gr[a].size()))) { if (vis[gr[a][i]]) continue; con = 0; int tch = dfs(gr[a][i], b); if (tch == 0) { con1 += con; } } vis.resize(0); vis.resize(n + 1); vis[b] = 1; ll con2 = 0; for (__typeof(gr[b].size()) i = (0) - ((0) > (gr[b].size())); i != (gr[b].size()) - ((0) > (gr[b].size())); i += 1 - 2 * ((0) > (gr[b].size()))) { con = 0; if (vis[gr[b][i]]) continue; int tch = dfs(gr[b][i], a); if (tch == 0) { con2 += con; } } cout << con2 * con1 << n ; } } |
// author: sharad12arse #include<bits/stdc++.h> using namespace std; #define ll long long #define ull unsigned long long #define gcd __gcd #define INF LONG_LONG_MAX void solve(){ int n; cin>>n; ll a1=0,a2=0,x=0; vector<ll> arr(n); for(int i=0;i<n;i++){ cin>>arr[i]; x^=arr[i]; } a2=x; for(int i=0;i<n-1;i++){ a1^=arr[i]; a2^=arr[i]; if(a1==a2){ cout<< YES n ; return; } } a1=0,a2=0; for(int i=0;i<n-1;i++){ a1^=arr[i]; a2=0; for(int j=n-1;j>i;j--){ a2^=arr[j]; if(a1==a2&&((x^a1)^a2)==a1){ cout<< YES n ; return; } } } cout<< NO n ; } int main(){ ios_base::sync_with_stdio(0); cin.tie(0); int t=1; cin>>t; while(t--){ solve(); } } |
#include <bits/stdc++.h> using namespace std; using vint = vector<int>; using pint = pair<int, int>; using vpint = vector<pint>; template <typename A, typename B> inline void chmin(A& a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A& a, B b) { if (a < b) a = b; } template <class A, class B> ostream& operator<<(ostream& ost, const pair<A, B>& p) { ost << { << p.first << , << p.second << } ; return ost; } template <class T> ostream& operator<<(ostream& ost, const vector<T>& v) { ost << { ; for (int i = 0; i < v.size(); i++) { if (i) ost << , ; ost << v[i]; } ost << } ; return ost; } inline int topbit(unsigned long long x) { return x ? 63 - __builtin_clzll(x) : -1; } inline int popcount(unsigned long long x) { return __builtin_popcountll(x); } inline int parity(unsigned long long x) { return __builtin_parity(x); } const int INF = 1001001001; const int X = 30000; int N, D; int cnt[33333]; const int B = 300; int dp[X + 1][B]; map<int, int> dp2[X + 1]; signed main() { cin >> N >> D; for (int i = 0; i < (N); i++) { int p; cin >> p; cnt[p]++; } fill_n(*dp, (X + 1) * B, -INF); if (D >= B) { dp2[D][D] = 0; } else { dp[D][D] = 0; } int ans = 0; for (int i = D; i <= X; i++) { for (int j = 1; j < B; j++) { if (dp[i][j] == -INF) continue; dp[i][j] += cnt[i]; chmax(ans, dp[i][j]); for (int k = -1; k <= 1; k++) { int d = j + k; if (d <= 0 || i + d > X) continue; if (d < B) chmax(dp[i + d][d], dp[i][j]); else chmax(dp2[i + d][d], dp[i][j]); } } for (auto& p : dp2[i]) { p.second += cnt[i]; int j = p.first; chmax(ans, p.second); for (int k = -1; k <= 1; k++) { int d = j + k; if (d <= 0 || i + d > X) continue; if (d < B) chmax(dp[i + d][d], p.second); else chmax(dp2[i + d][d], p.second); } } } cout << ans << endl; return 0; } |
/* lab2_part7.v
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab2_part7 (SW, LEDR, HEX1, HEX0);
input [5:0] SW;
output [0:6] HEX1, HEX0;
output [5:0] LEDR;
reg [3:0] TENS, ONES;
assign LEDR = SW;
always begin
if (SW[5:0] > 59) begin
TENS = 6;
ONES = SW[5:0] - 60;
end else if (SW[5:0] > 49) begin
TENS = 5;
ONES = SW[5:0] - 50;
end else if (SW[5:0] > 39) begin
TENS = 4;
ONES = SW[5:0] - 40;
end else if (SW[5:0] > 29) begin
TENS = 3;
ONES = SW[5:0] - 30;
end else if (SW[5:0] > 19) begin
TENS = 2;
ONES = SW[5:0] - 20;
end else if (SW[5:0] > 9) begin
TENS = 1;
ONES = SW[5:0] - 10;
end else begin
TENS = 0;
ONES = SW[5:0];
end //if
end //always
b2d_7seg H1 (TENS, HEX1);
b2d_7seg H0 (ONES, HEX0);
endmodule
module b2d_7seg (X, SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));
assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_TB_V
`define SKY130_FD_SC_HDLL__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hdll__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; const long long mod = 1e9 + 7; char s[maxn]; int num[55]; long long dp[maxn]; long long tmp[maxn]; long long quesnum[55][55]; long long ques[55][55]; long long inv[maxn], fac[maxn], invf[maxn]; void init(int hf) { inv[1] = 1; for (int i = 2; i < maxn; i++) inv[i] = ((mod - mod / i) * inv[mod % i]) % mod; fac[0] = 1; for (int i = 1; i < maxn; i++) fac[i] = (fac[i - 1] * (long long)i) % mod; invf[0] = 1; for (int i = 1; i < maxn; i++) invf[i] = (invf[i - 1] * inv[i]) % mod; memset(dp, 0, sizeof(dp)); memset(ques, -1, sizeof(ques)); dp[0] = 1; for (int i = 0; i < 55; i++) { if (!num[i]) continue; for (int j = hf; j >= num[i]; j--) { dp[j] = (dp[j] + dp[j - num[i]]) % mod; } } for (int i = 0; i < 52; i++) { for (int j = i; j < 52; j++) { for (int k = 0; k <= hf; k++) tmp[k] = dp[k]; for (int k = num[i]; k <= hf; k++) tmp[k] = (tmp[k] - tmp[k - num[i]] + mod) % mod; if (i != j) for (int k = num[j]; k <= hf; k++) tmp[k] = (tmp[k] - tmp[k - num[j]] + mod) % mod; quesnum[i][j] = quesnum[j][i] = tmp[hf]; } } } int main() { scanf( %s , s); memset(num, 0, sizeof(num)); int len = strlen(s); int hf = len / 2; for (int i = 0; i < len; i++) { if (s[i] >= a && s[i] <= z ) num[s[i] - a ]++; else num[s[i] - A + 26]++; } init(hf); int q; scanf( %d , &q); int x, y; while (q--) { scanf( %d%d , &x, &y); x--; y--; int idx, idy; if (s[x] >= a && s[x] <= z ) idx = s[x] - a ; else idx = s[x] - A + 26; if (s[y] >= a && s[y] <= z ) idy = s[y] - a ; else idy = s[y] - A + 26; if (ques[idx][idy] != -1) { printf( %I64d n , ques[idx][idy]); continue; } long long ans; if (idx == idy) { if (num[idx] > hf) { printf( 0 n ); ques[idx][idx] = 0; continue; } long long cc = ((fac[hf] * invf[num[idx]]) % mod * invf[hf - num[idx]]) % mod; ans = ((cc * fac[hf - num[idx]]) % mod * fac[hf]) % mod; } else { if (num[idx] + num[idy] > hf) { ques[idx][idy] = ques[idy][idx] = 0; printf( 0 n ); continue; } int numx = num[idx], numy = num[idy]; int num_hfx = hf - numx; long long cc1 = ((fac[hf] * invf[numx]) % mod * invf[hf - numx]) % mod; long long cc2 = ((fac[num_hfx] * invf[numy]) % mod * invf[num_hfx - numy]) % mod; ans = (((cc1 * cc2) % mod * fac[hf]) % mod * fac[hf - numx - numy]) % mod; } for (int i = 0; i < 55; i++) { if (i == idx || i == idy) continue; ans = (ans * invf[num[i]]) % mod; } ans = (ans * quesnum[idx][idy]) % mod; ans = (ans * 2) % mod; ques[idx][idy] = ques[idy][idx] = ans; printf( %I64d n , ans); } } |
`include "constants.vh"
`include "rv32_opcodes.vh"
module testbench();
parameter CLK_CYCLE_TIME = 50;
parameter IMEM_INTERVAL = 2000;
parameter SIM_CYCLE = 100000000;
parameter SIM_TIME = SIM_CYCLE * CLK_CYCLE_TIME * 2;
reg [31:0] CLK_CYCLE;
reg clk;
reg reset;
initial begin
clk = 0;
forever #CLK_CYCLE_TIME clk = ~clk;
end
initial begin
reset = 0;
#IMEM_INTERVAL reset = 1;
end
initial begin
CLK_CYCLE = 32'h0;
#IMEM_INTERVAL CLK_CYCLE = 32'h0;
end
always @(posedge clk) begin
CLK_CYCLE <= CLK_CYCLE + 1;
end
/*
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, TOP);
end
*/
initial begin
#IMEM_INTERVAL;
#SIM_TIME;
$finish;
end
top rv(
.clk(clk),
.reset_x(reset)
);
integer fp;
integer temp;
integer i, j;
initial begin
//btb, bia init
for (i = 0; i < `BTB_IDX_NUM ; i = i + 1) begin
rv.pipe.pipe_if.brtbl.bia.mem[i] = 0;
rv.pipe.pipe_if.brtbl.bta.mem[i] = 0;
end
for (i = 0; i < `GSH_PHT_NUM ; i = i + 1) begin
rv.pipe.pipe_if.gsh.prhisttbl.pht0.mem[i] = 2;
rv.pipe.pipe_if.gsh.prhisttbl.pht1.mem[i] = 2;
end
fp = $fopen("../bin/init.bin", "rb");
temp = $fread(rv.instmemory.mem, fp);
fp = $fopen("../bin/init.bin", "rb");
temp = $fread(rv.datamemory.mem, fp);
for (i = 0 ; i < 512 ; i = i + 1) begin
j = rv.instmemory.mem[i][7:0];
rv.instmemory.mem[i][7:0] = rv.instmemory.mem[i][31:24];
rv.instmemory.mem[i][31:24] = j;
j = rv.instmemory.mem[i][15:8];
rv.instmemory.mem[i][15:8] = rv.instmemory.mem[i][23:16];
rv.instmemory.mem[i][23:16] = j;
j = rv.instmemory.mem[i][32+7:0+32];
rv.instmemory.mem[i][32+7:0+32]
= rv.instmemory.mem[i][32+31:24+32];
rv.instmemory.mem[i][32+31:24+32] = j;
j = rv.instmemory.mem[i][32+15:8+32];
rv.instmemory.mem[i][32+15:8+32]
= rv.instmemory.mem[i][32+23:16+32];
rv.instmemory.mem[i][32+23:16+32] = j;
j = rv.instmemory.mem[i][64+7:0+64];
rv.instmemory.mem[i][64+7:0+64]
= rv.instmemory.mem[i][64+31:24+64];
rv.instmemory.mem[i][64+31:24+64] = j;
j = rv.instmemory.mem[i][64+15:8+64];
rv.instmemory.mem[i][64+15:8+64]
= rv.instmemory.mem[i][64+23:16+64];
rv.instmemory.mem[i][64+23:16+64] = j;
j = rv.instmemory.mem[i][96+7:0+96];
rv.instmemory.mem[i][96+7:0+96]
= rv.instmemory.mem[i][96+31:24+96];
rv.instmemory.mem[i][96+31:24+96] = j;
j = rv.instmemory.mem[i][96+15:8+96];
rv.instmemory.mem[i][96+15:8+96]
= rv.instmemory.mem[i][96+23:16+96];
rv.instmemory.mem[i][96+23:16+96] = j;
j = rv.instmemory.mem[i][31:0];
rv.instmemory.mem[i][31:0] = rv.instmemory.mem[i][127:96];
rv.instmemory.mem[i][127:96] = j;
j = rv.instmemory.mem[i][63:32];
rv.instmemory.mem[i][63:32] = rv.instmemory.mem[i][95:64];
rv.instmemory.mem[i][95:64] = j;
end
for (i = 0 ; i < 2048 ; i = i + 1) begin
j = rv.datamemory.mem[i][7:0];
rv.datamemory.mem[i][7:0] = rv.datamemory.mem[i][31:24];
rv.datamemory.mem[i][31:24] = j;
j = rv.datamemory.mem[i][15:8];
rv.datamemory.mem[i][15:8] = rv.datamemory.mem[i][23:16];
rv.datamemory.mem[i][23:16] = j;
end
end
always @ (posedge clk) begin
if (rv.pipe.pipe_if.hit && ~rv.pipe.stall_IF && ~rv.pipe.kill_IF) begin
// $write("HIT Info\n");
$write("pc: %x jmpaddr: %x npc: %x prcond: %x\n",
rv.pipe.pipe_if.pc, rv.pipe.pipe_if.pred_pc, rv.pipe.npc, rv.pipe.pipe_if.predict_cond);
end
end
integer prmi, prsu, prnum, prcom;
initial begin
prmi = 0;
prsu = 0;
prnum = 0;
prcom = 0;
end
always @ (posedge clk) begin
if (reset && rv.pipe.prmiss) begin
prmi = prmi + 1;
prnum = prnum + 1;
$write("Miss: npc: %x\n", rv.pipe.jmpaddr);
end
if (reset && rv.pipe.prsuccess) begin
prsu = prsu + 1;
prnum = prnum + 1;
$write("Success: npc: %x\n", rv.pipe.jmpaddr);
end
if (reset && rv.pipe.combranch) begin
prcom = prcom + 1;
//$write("PC: %x, DST: %x\n", rv.pipe.pc_combranch, rv.pipe.jmpaddr_combranch);
end
end
always @ (posedge clk) begin
//Simulation I/OMAP****************************************************
if (rv.dmem_we && rv.dmem_addr == 32'h0) begin
//$write("\n***\n%c\n***\n", rv.dmem_wdata[7:0]);
$write("%c", rv.dmem_wdata[7:0]);
end
if (rv.dmem_we && rv.dmem_addr == 32'h4) begin
$write("%d", rv.dmem_wdata);
end
if (rv.dmem_we && rv.dmem_addr == 32'h8) begin
$write("\n%d clks\n", CLK_CYCLE);
$write("prnum: %d, prsuccess: %d, prmiss: %d\n (prcom: %d)\n", prnum, prsu, prmi, prcom);
$finish;
end
end // always @ (posedge clk)
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[8][8], b[8][8]; long long get() { char c = getchar(); long long x = 0LL; while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) { x *= 10LL; x += (c - 0 ); c = getchar(); } return x; } int main() { char c; for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) { cin >> c; if (c == B ) a[i][j] = 1; } int ans = 16; for (int i = 0; i < (1 << 8); i++) for (int j = 0; j < (1 << 8); j++) { for (int x = 0; x < 8; x++) for (int y = 0; y < 8; y++) { if (i & (1 << x) || j & (1 << y)) b[x][y] = 1; else b[x][y] = 0; } bool f = true; for (int x = 0; x < 8; x++) for (int y = 0; y < 8; y++) if (b[x][y] != a[x][y]) f = false; if (f) { ans = min(ans, __builtin_popcount(i) + __builtin_popcount(j)); } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s1 = 0, s2 = 0, s3 = 0; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; if (i % 3 == 0) s1 += a[i]; else if (i % 3 == 1) s2 += a[i]; else s3 += a[i]; } if (s1 >= s2 && s1 >= s3) cout << chest n ; else if (s2 >= s3 && s2 >= s1) cout << biceps n ; else cout << back n ; return 0; } |
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