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#include <bits/stdc++.h> using namespace std; bool mycomp(vector<long long int> a, vector<long long int> b) { long long int acost = min(2 * a[0], a[1]) - min(a[0], a[1]); long long int bcost = min(2 * b[0], b[1]) - min(b[0], b[1]); return acost > bcost; } long long int fn(vector<vector<long long int> > arr, long long int n, long long int f) { sort(arr.begin(), arr.end(), mycomp); long long int productSold = 0; for (long long int i = 0; i < f; i++) { productSold += min(2 * arr[i][0], arr[i][1]); } for (long long int i = f; i < n; i++) { productSold += min(arr[i][0], arr[i][1]); } return productSold; } int32_t main() { long long int n, f; cin >> n >> f; vector<vector<long long int> > arr(n); for (long long int i = 0; i < n; i++) { long long int k, l; cin >> k >> l; arr[i].push_back(k); arr[i].push_back(l); } long long int ans = fn(arr, n, f); cout << ans; } |
#include <bits/stdc++.h> using namespace std; int G[23][23], n, m; bool check() { for (int i = 1; i <= n; ++i) { int cnt = 0; for (int j = 1; j <= m; ++j) cnt += G[i][j] != j; if (cnt > 2) return false; } return true; } int main(int argc, char const *argv[]) { cin >> n >> m; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) scanf( %d , &G[i][j]); if (check()) { cout << YES << endl; return 0; } for (int i = 1; i <= m; ++i) for (int j = i + 1; j <= m; ++j) { for (int k = 1; k <= n; ++k) swap(G[k][i], G[k][j]); if (check()) { cout << YES << endl; return 0; } for (int k = 1; k <= n; ++k) swap(G[k][i], G[k][j]); } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, n1, n2, limiter = 1, fight = 0, temp; cin >> n >> n1; queue<int> p1, p2; for (int i = 1; i <= n1; i++) { cin >> temp; p1.push(temp); limiter *= i; } cin >> n2; for (int i = 1; i <= n2; i++) { cin >> temp; p2.push(temp); limiter *= (n1 + i); } limiter *= (n + 1); while (1) { if (fight > limiter) { cout << -1; break; } else if (p1.empty()) { cout << fight << << 2; break; } else if (p2.empty()) { cout << fight << << 1; break; } else { if (p1.front() > p2.front()) { p1.push(p2.front()); p1.push(p1.front()); p1.pop(); p2.pop(); fight++; } else { p2.push(p1.front()); p2.push(p2.front()); p2.pop(); p1.pop(); fight++; } } } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZE = 8;
integer cnt = 0;
logic [SIZE-1:0] vld_for;
logic vld_if = 1'b0;
logic vld_else = 1'b0;
genvar i;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if (cnt==SIZE) begin : if_cnt_finish
$write("*-* All Finished *-*\n");
$finish;
end : if_cnt_finish_bad
generate
for (i=0; i<SIZE; i=i+1) begin : generate_for
always @ (posedge clk)
if (cnt == i) vld_for[i] <= 1'b1;
end : generate_for_bad
endgenerate
generate
if (SIZE>0) begin : generate_if_if
always @ (posedge clk)
vld_if <= 1'b1;
end : generate_if_if_bad
else begin : generate_if_else
always @ (posedge clk)
vld_else <= 1'b1;
end : generate_if_else_bad
endgenerate
endmodule : t_bad
|
module autoinst_signed
(/*AUTOARG*/
// Outputs
another_output2, another_output, an_outputpre, an_output2
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
output signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
output signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
output [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
wire signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
wire signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
wire [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
autoinst_signed_fubar u_fubar
(
// Outputs
.an_output (an_outputpre[1:0]),
.plover (plump),
/*AUTOINST*/
// Outputs
.another_output (another_output[1:0]),
// Inputs
.an_input (an_input[1:0]));
autoinst_signed_fubar2 u_fubar2
(
/*AUTOINST*/
// Outputs
.an_output2 (an_output2[1:0]),
.another_output2 (another_output2[1:0]),
// Inputs
.an_input2 (an_input2[1:0]));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class S, class T> ostream& operator<<(ostream& o, const pair<S, T>& p) { return o << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& o, const vector<T>& vc) { o << { ; for (const T& v : vc) o << v << , ; o << } ; return o; } using ll = long long; template <class T> using V = vector<T>; template <class T> using VV = vector<vector<T>>; constexpr ll TEN(int n) { return (n == 0) ? 1 : 10 * TEN(n - 1); } template <unsigned int mod_> struct ModInt { using uint = unsigned int; using ll = long long; using ull = unsigned long long; constexpr static uint mod = mod_; uint v; ModInt() : v(0) {} ModInt(ll _v) : v(normS(_v % mod + mod)) {} explicit operator bool() const { return v != 0; } static uint normS(const uint& x) { return (x < mod) ? x : x - mod; } static ModInt make(const uint& x) { ModInt m; m.v = x; return m; } ModInt operator+(const ModInt& b) const { return make(normS(v + b.v)); } ModInt operator-(const ModInt& b) const { return make(normS(v + mod - b.v)); } ModInt operator-() const { return make(normS(mod - v)); } ModInt operator*(const ModInt& b) const { return make((ull)v * b.v % mod); } ModInt operator/(const ModInt& b) const { return *this * b.inv(); } ModInt& operator+=(const ModInt& b) { return *this = *this + b; } ModInt& operator-=(const ModInt& b) { return *this = *this - b; } ModInt& operator*=(const ModInt& b) { return *this = *this * b; } ModInt& operator/=(const ModInt& b) { return *this = *this / b; } ModInt& operator++(int) { return *this = *this + 1; } ModInt& operator--(int) { return *this = *this - 1; } ll extgcd(ll a, ll b, ll& x, ll& y) const { ll p[] = {a, 1, 0}, q[] = {b, 0, 1}; while (*q) { ll t = *p / *q; for (int i = 0; i < (int)(3); i++) swap(p[i] -= t * q[i], q[i]); } if (p[0] < 0) for (int i = 0; i < (int)(3); i++) p[i] = -p[i]; x = p[1], y = p[2]; return p[0]; } ModInt inv() const { ll x, y; extgcd(v, mod, x, y); return make(normS(x + mod)); } ModInt pow(ll p) const { if (p < 0) return inv().pow(-p); ModInt a = 1; ModInt x = *this; while (p) { if (p & 1) a *= x; x *= x; p >>= 1; } return a; } bool operator==(const ModInt& b) const { return v == b.v; } bool operator!=(const ModInt& b) const { return v != b.v; } friend istream& operator>>(istream& o, ModInt& x) { ll tmp; o >> tmp; x = ModInt(tmp); return o; } friend ostream& operator<<(ostream& o, const ModInt& x) { return o << x.v; } }; using mint = ModInt<1000000007>; int main() { cin.tie(0); ios::sync_with_stdio(false); cout << fixed << setprecision(20); int N, Q; cin >> N >> Q; V<ll> A(N); for (int i = 0; i < (int)(N); i++) cin >> A[i]; V<mint> p2(N + 1); p2[0] = 1; for (int i = 1; i <= (int)(N); i++) p2[i] = p2[i - 1] * 2; struct link { int to; mint sum; ll sum2; }; V<link> ls(N); const ll inf = 1e9; for (int i = 0; i < (int)(N); i++) { link cur{i, A[i], A[i]}; while (cur.to > 0 && cur.sum2 > 0) { link x = ls[cur.to - 1]; link nxt; nxt.to = x.to; nxt.sum = cur.sum * p2[cur.to - x.to] + x.sum; nxt.sum2 = (cur.sum2 << min(cur.to - x.to, 30)) + x.sum2; nxt.sum2 = min(nxt.sum2, inf); cur = nxt; } ls[i] = cur; } const int H = 20; V<array<pair<int, mint>, H>> par(N + 1); for (int h = 0; h < (int)(H); h++) par[0][h] = {-1, 0}; for (int i = 0; i < (int)(N); i++) { par[i + 1][0] = {ls[i].to, ls[i].sum}; for (int h = 1; h <= (int)(H - 1); h++) { int j; mint js; tie(j, js) = par[i + 1][h - 1]; if (j == -1) { par[i + 1][h] = {-1, 0}; } else { int k; mint ks; tie(k, ks) = par[j][h - 1]; if (k == -1) par[i + 1][h] = {-1, 0}; else par[i + 1][h] = {k, js + ks}; } } } V<mint> sum(N + 1); for (int i = N - 1; i >= 0; i--) sum[i] = sum[i + 1] * 2 + A[i]; for (int _ = 0; _ < (int)(Q); _++) { int l, r; cin >> l >> r; l--; mint ans = 0; for (int h = H - 1; h >= 0; h--) { if (l + 1 <= par[r][h].first) { ans += par[r][h].second; r = par[r][h].first; } } ans *= 2; ans += sum[l] - sum[r] * p2[r - l]; cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; int h; int edge[5000]; int extend[5000]; int maximum; int v[5000]; bool flag = 0; void dfs_m(int p, int value) { v[p] = value; if (edge[p * 2] != 0) dfs_m(p * 2 + 0, value + edge[p * 2]); else { if (maximum < value) maximum = value; } if (edge[p * 2 + 1] != 0) dfs_m(p * 2 + 1, value + edge[p * 2 + 1]); else { if (maximum < value) maximum = value; } } void dfs(int p, int value) { if (edge[p * 2] != 0) { dfs(p * 2, value + edge[p * 2] + extend[p * 2]); } else { if (value < maximum) { extend[p] += (maximum - value); } } if (edge[p * 2 + 1] != 0) { dfs(p * 2 + 1, value + edge[p * 2 + 1] + extend[p * 2 + 1]); } else { if (value < maximum) { extend[p] += (maximum - value); } } } int min(int a, int b) { if (a == b) return -1; if (a < b) { return a; } return b; } void merge(int n) { if (extend[n * 2] != 0 && extend[n * 2 + 1] != 0) { int m = min(extend[n * 2 + 1], extend[n * 2]); flag = false; if (m == -1) { extend[n] += extend[n * 2 + 1]; extend[n * 2] = extend[n * 2 + 1] = 0; merge(n / 2); } else { extend[n] += m; extend[n * 2] -= m; extend[n * 2 + 1] -= m; merge(n / 2); } } } int main() { scanf( %d , &h); int e = pow(2, h + 1) - 2; memset(edge, 0, sizeof(edge)); memset(extend, 0, sizeof(extend)); memset(v, 0, sizeof(v)); for (int i = 2; i <= e + 1; i++) { scanf( %d , &edge[i]); } maximum = 0; dfs_m(1, 0); dfs(1, 0); int node = pow(2, h + 1); for (int i = 2; i <= e + 1; i++) { extend[i] /= 2; } while (true) { flag = true; for (int i = 0; i < node; i++) { merge(i); } for (int i = 2; i <= e + 1; i++) { } if (flag) { break; } } int ans = 0; for (int i = 0; i <= e + 1; i++) { ans += extend[i]; } printf( %d , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_8_V
`define SKY130_FD_SC_HS__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_8_V
|
//-----------------------------------------------------------------------------
// File : alu.v
// Creation date : 18.04.2017
// Creation time : 14:44:52
// Description :
// Created by : TermosPullo
// Tool : Kactus2 3.4.79 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:core:alu:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/core/alu/1.0/alu.1.0.xml
//-----------------------------------------------------------------------------
module alu #(
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter ALU_OP_WIDTH = 3 // Bits reserved for identification of alu operation
) (
// Interface: cpu_system
input [ALU_OP_WIDTH-1:0] alu_op_i,
input [DATA_WIDTH-1:0] register_value_i1,
input [DATA_WIDTH-1:0] register_value_i2,
output reg [DATA_WIDTH-1:0] alu_result_o,
output reg [DATA_WIDTH-1:0] alu_status_o
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The available operations.
parameter [ALU_OP_WIDTH-1:0]
OP_PLUS = 3'b000,
OP_MINUS = 3'b001,
OP_MUL = 3'b010,
OP_DIV = 3'b011,
OP_CMP = 3'b100;
// The available status bits.
parameter [1:0]
C_OUT = 2'd3,
NEGATIVE = 2'd2,
ZERO = 2'd1,
DIV_ZERO = 2'd0;
// Result of the operation.
reg [DATA_WIDTH*2-1:0] operation_result;
// 1 = Division with zero attempted.
integer div_zero;
always @* begin
// By default, it did not happen.
div_zero = 0;
// Select a case depending on operation. Most are pretty straightforward execution.
case(alu_op_i)
OP_PLUS: operation_result <= register_value_i1 + register_value_i2;
OP_MINUS: operation_result <= register_value_i1 - register_value_i2;
OP_MUL: operation_result <= register_value_i1 * register_value_i2;
OP_DIV: begin
if (register_value_i2 == 0) begin
// Tried division by zero. Also result is then zero.
operation_result <= 0;
div_zero = 1;
end
else begin
operation_result <= register_value_i1 / register_value_i2;
end
end
OP_CMP : operation_result <= register_value_i1 != register_value_i2;
default: begin
// Unsupported opcode -> Result is zero.
$display("ERROR: Unknown ALU operation: %d", alu_op_i);
operation_result <= 0;
end
endcase
// Output the result.
alu_result_o <= operation_result[DATA_WIDTH-1:0];
// Undefined status bits are always zero.
alu_status_o[DATA_WIDTH-1:C_OUT+1] = 0;
// Carry out is always the least significant overflow bit.
alu_status_o[C_OUT] = operation_result[DATA_WIDTH];
// If applicable, the most significant output bit is the sign.
alu_status_o[NEGATIVE] = operation_result[DATA_WIDTH-1];
// Zero bit should be obvious.
alu_status_o[ZERO] = (operation_result == 0);
// Division by zero is was resolved earlier.
alu_status_o[DIV_ZERO] = div_zero;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long len[1000006]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, q, t, x, s, m, p, d, l; cin >> n >> m >> l; for (int i = 0; i < n; i++) { cin >> len[i]; } long long co = 0; long long pre; if (n == 1) { if (len[0] > l) co++; for (int i = 0; i < m; i++) { cin >> x; if (x == 1) { cin >> p >> d; pre = len[p - 1]; len[p - 1] += d; if (len[p - 1] > l && pre <= l) { co++; } } else cout << co << n ; } return 0; } for (int i = 0; i < n; i++) { if (len[i] > l) { co++; int j = i; while (j < n && len[j] > l) { j++; } if (j > i) i = j; } } long long prev; for (int i = 0; i < m; i++) { cin >> x; if (x == 1) { cin >> p >> d; p--; prev = len[p]; len[p] += d; if (prev <= l) { if (len[p] > l) { if (p == 0) { if (len[p + 1] > l) continue; else { co++; continue; } } else if (p == n - 1) { if (len[p - 1] > l) continue; else co++; } else { if (len[p - 1] > l && len[p + 1] > l) co--; else if (len[p - 1] <= l && len[p + 1] <= l) co++; } } } } else { cout << max(1ll * 0, co) << n ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> arr[100001]; int main() { int n, d, a, b; cin >> n >> d >> a >> b; for (int i = 0; i < n; i++) { int c, d; cin >> c >> d; arr[i].first = c * a + d * b; arr[i].second = i + 1; } sort(arr, arr + n); long long counter = 0; int in = n; for (int i = 0; i < n; i++) { counter += arr[i].first; if (counter > d) { in = i; break; } } cout << in << endl; for (int i = 0; i < in; i++) { cout << arr[i].second << ; } cout << endl; return 0; } |
/* Extracted from PR#820. */
module main();
wire clk;
wire reset;
reg [3:0] waddr, raddr;
reg [7:0] wdata;
wire [7:0] rdata;
clk_reset_gen cg(clk, reset);
ram_rw #(8,4) r(clk, waddr, wdata, 1'b1, raddr, rdata);
initial begin
waddr = 4'd0;
raddr = 4'd14;
wdata = 0;
#3001;
$finish(0);
end
always @(posedge clk) begin
waddr <= #1 waddr + 1;
raddr <= #1 raddr + 1;
wdata <= #1 wdata + 3;
end
always @(posedge clk)
$display($time,,"waddr wdata %d %d raddr rdata %d %d",waddr,wdata,raddr,rdata);
endmodule
module ram_rw(clk,waddr,wdata,we,raddr,rdata);
parameter WDATA = 8;
parameter WADDR = 11;
input clk;
input [(WADDR-1):0] waddr;
input [(WDATA-1):0] wdata;
input we;
input [(WADDR-1):0] raddr;
output [(WDATA-1):0] rdata;
//local
reg [(WDATA-1):0] mem[0:((1<<WADDR)-1)];
reg [(WADDR-1):0] qraddr;
always @(posedge clk) begin
qraddr <= #1 raddr;
if (we)
mem[waddr] <= #1 wdata;
end
assign rdata = mem[qraddr];
endmodule
module clk_reset_gen(clk, reset);
output clk;
output reset;
reg clk;
reg reset;
initial begin
reset = 1;
#5;
clk = 0;
#5;
clk = 1;
#5;
reset = 0;
clk = 0;
forever #5 clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, m, cnt, head[N], vis[N], in[N], u, v, ans, op[N]; int idx, dfn[N], g[N], f[N]; struct edge { int v, nxt; } e[N]; void add(int u, int v) { e[++cnt] = (edge){v, head[u]}; head[u] = cnt; } int dfs(int u) { vis[u] = in[u] = 1; for (int i = head[u], v; v = e[i].v, i; i = e[i].nxt) if (in[v] || (!vis[v] && !dfs(v))) return 0; return in[dfn[++idx] = u] = 0, 1; } int main() { cin >> n >> m; for (int i = (1); i <= (m); i++) scanf( %d%d , &u, &v), add(u, v); for (int i = (1); i <= (n); i++) if (!vis[i] && !dfs(i)) return puts( -1 ), 0; memset(g, 0x3f, sizeof g), memset(f, 0x3f, sizeof f); for (int j = (1); j <= (n); j++) for (int i = head[dfn[j]], v; v = e[i].v, i; i = e[i].nxt) g[dfn[j]] = min(g[dfn[j]], min(v, g[v])); for (int j = (n); j >= (1); j--) for (int i = head[dfn[j]], v; v = e[i].v, i; i = e[i].nxt) f[v] = min(f[v], min(dfn[j], f[dfn[j]])); for (int i = (1); i <= (n); i++) if (min(g[i], f[i]) > i) ans++, op[i] = 1; cout << ans << endl; for (int i = (1); i <= (n); i++) putchar(op[i] ? A : E ); return 0; } |
#include <bits/stdc++.h> #define modulus 1000000007 //for loops //------------------- #define for0(i, N) for (i = 0; i < (int) N; i++) #define for1(i, N) for (i = 1; i <= (int) N; i++) #define forr0(i, N) for (i = (int) N - 1; ~i; i--) #define forr1(i, N) for (i = (int) N; i; i--) #define foru(i, l, r, x) for (i = l; i <= r; i += x) //to declare a for loop, //first declare the primitive on a separate line // // int i; // for0(i, N){ // code // } //primitives & string //------------------- using ll = long long; using str = std::string; //pairs //----- using ii = std::pair<int, int>; using llll = std::pair<ll, ll>; #define mp make_pair #define fi first #define se second using mii = std::map<int, int>; using mllll = std::map<ll, ll>; //vectors //------------- #define pb push_back using vi = std::vector<int>; using vvi = std::vector<vi>; using vii = std::vector<ii>; using vll = std::vector<ll>; using vvll = std::vector<vll>; using vb = std::vector<bool>; //those grid problems (thanks BenCh) //---------------------------------- const int dx[] = {1, 0, -1, 0}, dy[] = {0, 1, 0, -1}; //division rounded up and rounded down //-------- ll cdiv(ll a, ll b) { return a/b+((a^b)>0&&a%b); } ll fdiv(ll a, ll b) { return a/b-((a^b)<0&&a%b); } using namespace std; //ACTUAL CODE //------------------------------------------------------------------------------------------------ // | // | void solve(){ int N; cin >> N; vector<pair<int, int>> coords; char arr[N][N]; for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { cin >> arr[i][j]; if (arr[i][j] == * ) { coords.pb({i, j}); } } } if (coords[0].first == coords[1].first) { if (coords[1].first == N - 1) { arr[N - 2][coords[1].second] = * ; arr[N - 2][coords[0].second] = * ; } else { arr[coords[1].first + 1][coords[1].second] = * ; arr[coords[0].first + 1][coords[0].second] = * ; } } else if (coords[0].second == coords[1].second) { if (coords[0].second == N - 1) { arr[coords[0].first][N - 2] = * ; arr[coords[1].first][N - 2] = * ; } else { arr[coords[0].first][coords[0].second + 1] = * ; arr[coords[1].first][coords[1].second + 1] = * ; } } else { arr[coords[0].first][coords[1].second] = * ; arr[coords[1].first][coords[0].second] = * ; } for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { cout << arr[i][j]; } cout << n ; } } int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); std::cout.tie(0); std::cout << std::fixed; int t; std::cin >> t; while(t--) solve(); return 0; } // | // | //------------------------------------------------------------------------------------------------ // NOTES: //~~~~~~~~~~~~~~~~~~~~~~~~ // debug: // - check int overflow, out of bounds // - negative indexing? // special cases (n = 1, n = 0?) // do something instead of nothing // *stay organized* // - write down IDEAS // - DON T GET CAUGHT ON ONE APPROACH // // // // most of all, maintain absolute concentration - take a break if you must // // |
#include <bits/stdc++.h> using namespace std; const int m = 320; struct data { int n, x, a[2 * m + 10]; data *next; }; data *head; int get(int value, int limit) { int ret = 0; data *k; for (k = head; k != NULL; k = k->next) { if (k->x > value) break; ret += k->n; } if (k != NULL) for (int i = 1; i <= k->n; i++) { if (k->a[i] > value) break; ret++; } return (min(ret, limit) + 1); } void split(data *k) { data *t = new (data); t->x = k->x = 0; for (int i = 1; i <= m; i++) { t->a[i] = k->a[i + m]; t->x = max(t->x, t->a[i]); k->x = max(k->x, k->a[i]); } k->n = t->n = m; t->next = k->next; k->next = t; } void insert(int value, int pos) { if (head == NULL) { head = new (data); head->n = 1; head->x = head->a[1] = value; head->next = NULL; return; } data *k; for (k = head; k != NULL; k = k->next) { if (pos <= k->n + 1) break; pos -= k->n; } for (int i = k->n; i >= pos; i--) k->a[i + 1] = k->a[i]; k->a[pos] = value; k->x = max(k->x, value); k->n++; if (k->n == 2 * m) split(k); } int ans[100010], p[100010]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); p[x] = i; int pos = get(x, y); insert(x, pos); } int t = 0; for (data *k = head; k != NULL; k = k->next) for (int i = 1; i <= k->n; i++) ans[++t] = k->a[i]; reverse(ans + 1, ans + n + 1); for (int i = 1; i <= n; i++) printf( %d%c , p[ans[i]], i == n ? n : ); return (0); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); string s; cin >> s; long long int n = s.length(), i; stack<char> a; for (i = 0; i < n; i++) { if (a.empty()) a.push(s[i]); else { if (a.top() == s[i]) a.pop(); else a.push(s[i]); } } if (a.size() != 0) cout << No ; else cout << Yes ; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, k, i, j; bool flag, flag1, final_flag; string p, q; cin >> t; for (i = 0; i < t; i++) { map<char, int> m; final_flag = false; cin >> p >> q; for (j = 0; j < p.size(); j++) { if (m.find(p[j]) == m.end()) m[p[j]] = 1; else m[p[j]] += 1; } for (j = 0; j < q.size(); j++) { map<char, int> m1; flag1 = true; flag = true; if (m.find(q[j]) != m.end()) { k = j; for (k = j; k < p.size() + j; k++) { if (m.find(q[k]) == m.end()) { flag = false; break; } else { if (m1.find(q[k]) == m1.end()) m1[q[k]] = 1; else m1[q[k]] += 1; } } if (flag) { map<char, int>::iterator it; for (it = m.begin(); it != m.end(); it++) { if (m1.find(it->first) == m1.end()) { flag1 = false; break; } if (m1[it->first] != m[it->first]) { flag1 = false; break; } } if (flag1) final_flag = true; } } if (final_flag) break; } if (final_flag) cout << YES << endl; else cout << NO << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O31AI_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31ai (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_4_V
`define SKY130_FD_SC_HS__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_4_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g_fifo
*/
module test_eth_mac_10g_fifo_32;
// Parameters
parameter DATA_WIDTH = 32;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
xgmii_rxd,
xgmii_rxc,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
xgmii_txd,
xgmii_txc,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_10g_fifo_32.lxt");
$dumpvars(0, test_eth_mac_10g_fifo_32);
end
eth_mac_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:47:19 02/21/2016
// Design Name: parityChecker
// Module Name: F:/VLSI Lab/parityChecker/parityCheckerTest.v
// Project Name: parityChecker
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: parityChecker
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module parityCheckerTest;
// Inputs
reg [3:0] data;
reg parity;
// Outputs
wire parity_result;
// Instantiate the Unit Under Test (UUT)
parityChecker uut (
.data(data),
.parity(parity),
.parity_result(parity_result)
);
initial begin
// Initialize Inputs
data = 4'b0101;
parity = 0;
#10;
data = 4'b1101;
parity = 0;
#10;
data = 4'b0101;
parity = 1;
#10;
data = 4'b1101;
parity = 1;
#10;
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long INF = 4e18; const int inf = 2e9; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a * b / gcd(a, b); } int a[3005], pos[3005]; int main(void) { int n, i, j, naik = 0; scanf( %d , &n); for (i = 1; i <= n; ++i) { scanf( %d , a + i); pos[a[i]] = i; } int ans = 0; for (i = 1; i <= n; ++i) { while (pos[i] > i) { swap(a[pos[i]], a[pos[i] - 1]); swap(pos[a[pos[i]]], pos[a[pos[i] - 1]]); ans++; } } ans = ((ans >> 1) << 2) + (ans & 1); printf( %.9f n , (double)ans); return 0; } |
#include <bits/stdc++.h> using namespace std; bool solved; const int MX = 1500000; int cache_map[1 << 22]; int nxt; int cache[MX][22]; void check_solution(vector<int>& g, vector<int>& sol, int n) { int mask(0); int ind(nxt); nxt += 1; if (nxt == MX) nxt = 0; if (((int)sol.size()) != 1) { for (int i(0), _l((int)(((int)sol.size())) - 1); i <= _l; ++i) mask |= (1 << sol[i]); int mask_prev = mask ^ (1 << sol.back()); int ind_prev(cache_map[mask_prev]); memcpy(cache[ind], cache[ind_prev], 22 * sizeof(int)); } else { mask |= (1 << sol.back()); for (int i(0), _l((int)(n)-1); i <= _l; ++i) cache[ind][i] = g[i]; } cache_map[mask] = ind; int v(sol.back()); for (int j(0), _l((int)(n)-1); j <= _l; ++j) { if ((cache[ind][v] & (1 << j)) != 0) { cache[ind][j] |= cache[ind][v]; } } int need((1 << n) - 1); for (int i(0), _l((int)(n)-1); i <= _l; ++i) if (cache[ind][i] != need) return; printf( %d n , ((int)sol.size())); for (int i(0), _l((int)(((int)sol.size())) - 1); i <= _l; ++i) printf( %d%c , sol[i] + 1, i + 1 == ((int)sol.size()) ? n : ); solved = true; } void try_solve(vector<int>& g, int n, int k, vector<int>& cur, int ind) { if (solved) return; if (((int)cur.size()) == k) { check_solution(g, cur, n); } else { if (ind == n) return; cur.push_back(ind); try_solve(g, n, k, cur, ind + 1); cur.pop_back(); if (solved) return; try_solve(g, n, k, cur, ind + 1); } } void solve() { nxt = 0; int n, m; scanf( %d%d , &n, &m); vector<int> g(n); for (int i(0), _l((int)(n)-1); i <= _l; ++i) { g[i] |= (1 << i); } for (int i(0), _l((int)(m)-1); i <= _l; ++i) { int a, b; scanf( %d%d , &a, &b); --a, --b; g[a] |= (1 << b); g[b] |= (1 << a); } if (m == n * (n - 1) / 2) { puts( 0 ); return; } solved = false; vector<int> s; for (int i(1), _l(n); i <= _l; ++i) { try_solve(g, n, i, s, 0); if (solved) break; } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 210; int n; int a[N]; bool vis[N]; int lp[N]; int dis[N]; int inloop(int v) { vis[v] = 1; int u = a[v]; int cnt = 1; while (u != v && !vis[u]) { vis[u] = 1; ++cnt; u = a[u]; } if (u == v) return cnt; return 0; } int dfsandsetlp(int v) { if (lp[v] > 0) return dis[v]; int t = dfsandsetlp(a[v]); lp[v] = lp[a[v]]; return dis[v] = t + 1; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { if (a == 0) return b; if (b == 0) return a; return a / gcd(a, b) * b; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , a + i); } for (int i = 1; i <= n; ++i) { memset(vis, 0, sizeof(vis)); int t = inloop(i); lp[i] = t; } for (int i = 1; i <= n; ++i) { if (!lp[i]) { dis[i] = dfsandsetlp(i); } } long long res = 1; for (int i = 1; i <= n; ++i) { res = lcm(res, lp[i]); } int mx = 0; for (int i = 1; i <= n; ++i) { mx = max(mx, dis[i]); } if (res < mx) { int t = mx / res; if (res * t == mx) { res = mx; } else { res = res * (t + 1); } } printf( %I64d n , res); return 0; } |
module vga_controller(
input reset,
input sys_clk,
input vga_clk,
input [23:0] pixel,
output blank_n,
output HS,
output VS,
output [10:0] next_pixel_h,
output [10:0] next_pixel_v,
output [31:0] next_pixel_addr,
output [7:0] red,
output [7:0] green,
output [7:0] blue
);
reg [7:0] r_red;
reg [7:0] r_green;
reg [7:0] r_blue;
vga_sync_generator vga_sync(
.reset(reset),
.vga_clk(vga_clk),
.blank_n(blank_n),
.next_pixel_h(next_pixel_h),
.next_pixel_v(next_pixel_v),
.next_pixel_addr(next_pixel_addr),
.HS(HS),
.VS(VS)
);
always@(posedge vga_clk) begin
// Only set pixel colours when in the visible display area.
if (blank_n) begin
// Draw the pixel.
r_red <= pixel[23:16];
r_green <= pixel[15:8];
r_blue <= pixel[7:0];
end else begin
r_red <= 8'h0;
r_green <= 8'h0;
r_blue <= 8'h0;
end
end
assign red = r_red;
assign green = r_green;
assign blue = r_blue;
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[2][2]; int main() { for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) scanf( %d , x[i] + j); printf( %d n , (max(1, abs(x[0][0] - x[1][0])) + max(1, abs(x[0][1] - x[1][1])) + 2) * 2); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_FUNCTIONAL_PP_V |
//local bus module,can write or read;
//by ZQ 20110916;
module local_bus(
clk,
reset,
cs_n,//local bus;
rd_wr,//only write,no read;
ack_n,
data,
data_out,
ale,
port0_select,
port1_select,
port2_select,
port3_select,
port1_check,
port2_check
);
input clk;
input reset;
input cs_n;
input rd_wr;
output ack_n;
input [31:0]data;//;
output [31:0]data_out;
input ale;
output port0_select;
output port1_select;
output port2_select;
output port3_select;
output [31:0]port1_check;
output [31:0]port2_check;
reg [31:0]data_out;
wire [31:0]data;
reg ack_n;
reg [27:0]local_bus_address_reg;
///////////////////UM register//////////////////////
reg [31:0]test0;
reg [31:0]test1;
reg [31:0]test2;
reg [31:0]test3;
reg [31:0]test4;
reg [31:0]test5;
reg port0_select;
reg port1_select;
reg port2_select;
reg port3_select;
reg [31:0]port1_check;
reg [31:0]port2_check;
///////////////////end of UM register//////////////////////
reg [2:0]current_state;
parameter idle=3'b0,
wait_ale0=3'b001,//wait the ale change to 0;
juedge_um=3'b010,
um_register=3'b011,
wait_wrreg_cs=3'b100,
wait_rdreg_cs=3'b101,
cancel_ack=3'b0110,
cancel_command=3'b111;
always@(posedge clk or negedge reset)
if(!reset)
begin
ack_n<=1'b1;
test0<=32'd20110704;
test1<=32'd20110704;
test2<=32'd20110704;
test3<=32'd20110704;
test4<=32'd20110704;
test5<=32'd20110704;
port0_select<=1'b0;
port1_select<=1'b0;
port2_select<=1'b0;
port3_select<=1'b0;
port1_check <=32'h4;//????64
port2_check <=32'h4;//????64
current_state <=idle;
end
else
begin
case(current_state)
idle:
begin
if(ale==1'b1)//address locked signal is coming;
begin
current_state<=wait_ale0;
end
else
current_state<=idle;
end//end idle;
wait_ale0://wait ale==1'b0;
begin
if(ale==1'b0)
begin
case(data[31:28])////
4'b0001://um RAM and registers;
begin
local_bus_address_reg<=data[27:0];//data[27:26]:00-register;01-RAM;////
current_state<=juedge_um;
end
default:
begin
current_state<=idle;
end
endcase//end case;
end
else
begin
//data_in_reg<=data_in;/////
current_state<=wait_ale0;
end
end//end wait ale==1'b0;
juedge_um:
begin
case(local_bus_address_reg[27:26])
2'b00:
begin
current_state<=um_register;//UM register;
end
default:
begin
current_state<=idle;
end
endcase
end//juedge_um;
um_register:
begin
if(rd_wr==1'b0)//write;
begin
current_state<=wait_wrreg_cs;
end
else
begin
current_state<=wait_rdreg_cs;
end
end//um_register;
wait_wrreg_cs:
begin
if(cs_n==1'b0)//ok
begin
case(local_bus_address_reg[7:0])
8'h00:
begin
test0<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h01:
begin
test1<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h02:
begin
test2<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h03:
begin
test3<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h04:
begin
test4<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h05:
begin
test5<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h06:
begin
port0_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h07:
begin
port1_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h08:
begin
port2_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h09:
begin
port3_select<=data[0];
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0a:
begin
port1_check<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0b:
begin
port2_check<=data;
ack_n<=1'b1;
current_state<=cancel_ack;
end
default:
current_state<=idle;
endcase
end
else
begin
current_state<=wait_wrreg_cs;
end
end//wait_wr_cs;
wait_rdreg_cs:
begin
if(cs_n==1'b0)//ok
begin
case(local_bus_address_reg[7:0])
8'h00:
begin
data_out<=test0;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h01:
begin
data_out<=test1;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h02:
begin
data_out<=test2;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h03:
begin
data_out<=test3;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h04:
begin
data_out<=test4;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h05:
begin
data_out<=test5;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h06:
begin
data_out<=port0_select;
data_out[31:1]<=31'b0;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h07:
begin
data_out[0]<=port1_select;
data_out[31:1]<=31'b0;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h08:
begin
data_out<=port2_select;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h09:
begin
data_out<=port3_select;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0a:
begin
data_out<=port1_check;
ack_n<=1'b1;
current_state<=cancel_ack;
end
8'h0b:
begin
data_out<=port2_check;
ack_n<=1'b1;
current_state<=cancel_ack;
end
default:
current_state<=idle;
endcase
end
else
begin
current_state<=wait_rdreg_cs;
end
end//wait_rd_cs;
cancel_ack:
begin
local_bus_address_reg<=28'b0;
ack_n<=1'b0;
current_state<=cancel_command;
end//cancel_ack;
cancel_command:
begin
if(cs_n==1'b1)
begin
ack_n<=1'b1;
current_state<=idle;
end
else
begin
current_state<=cancel_command;
end
end//cancel_command;
default:
begin
current_state<=idle;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_4_V
`define SKY130_FD_SC_MS__AND3_4_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_4_V
|
#include <bits/stdc++.h> using namespace std; void moveLeft() { cout << LEFT << endl; } void moveRight() { cout << RIGHT << endl; } void print(char ch) { cout << PRINT << ch << endl; } int main() { int numberOfCells, currentCell; cin >> numberOfCells >> currentCell; string slogan; cin >> slogan; if (currentCell <= numberOfCells - currentCell) { while (currentCell != 1) { moveLeft(); currentCell--; } while (currentCell <= numberOfCells) { print(slogan[currentCell - 1]); if (currentCell == numberOfCells) { break; } moveRight(); currentCell++; } } else { while (currentCell != numberOfCells) { moveRight(); currentCell++; } while (currentCell >= 1) { print(slogan[currentCell - 1]); if (currentCell == 1) { break; } moveLeft(); currentCell--; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRTN_PP_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int M = 5005; int a[M], n, dp[M], ans, mx, s[M], t[M], cnt; bool vis[M]; struct no { int l, r, x; } p[M]; bool cmp(no a, no b) { return a.r != b.r ? a.r < b.r : a.l < b.l; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; if (!p[a[i]].l) p[a[i]].l = i; p[a[i]].r = i; if (s[a[i]] == 0) s[a[i]] = i; t[a[i]] = i; mx = max(mx, a[i]); } for (int i = 1; i <= n; i++) { int l = i, r = t[a[i]]; memset(vis, 0, sizeof(vis)); bool flag = 0; int res = 0; for (int j = l; j <= r; j++) { if (vis[a[j]]) continue; if (s[a[j]] < l) { flag = 1; break; } r = max(r, t[a[j]]); res ^= a[j]; vis[a[j]] = 1; } if (flag) continue; p[++cnt] = (no){l, r, res}; } sort(p + 1, p + cnt + 1, cmp); for (int i = 1; i <= cnt; i++) { for (int j = 1; j < i; j++) { if (p[j].r < p[i].l) { dp[i] = max(dp[i], dp[j]); } } dp[i] += p[i].x; ans = max(ans, dp[i]); } cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:36:01 05/30/2013
// Design Name: fsm_mulplier
// Module Name: D:/Xilinx_ISE_Pro/maju_ASIC_FPGA/assign4/shardmulty/testbn.v
// Project Name: shardmulty
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fsm_mulplier
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbn;
// Inputs
reg clk;
reg rst;
reg in_en;
reg [7:0] in_a;
reg [7:0] in_b;
// Outputs
wire [15:0] prdct;
wire out_en;
// Instantiate the Unit Under Test (UUT)
fsm_mulplier uut (
.clk(clk),
.rst(rst),
.in_en(in_en),
.a(in_a),
.b(in_b),
.prdct(prdct),
.out_en(out_en)
);
localparam T =20;
always begin
clk = 0;
#(T/2);
clk = 1;
#(T/2);
end
initial begin
// Initialize Inputs
rst = 1;
in_en = 0;
in_a = 0;
in_b = 0;
// Wait 100 ns for global reset to finish
#70;
rst = 0;
#10
in_en = 1'b1;
in_a = 8'b00000101 ;
in_b = 8'b00000101 ;
#20
in_en = 1'b0;
// Add stimulus here
end
endmodule
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
module gpmc
#(parameter TXFIFOSIZE = 11,
parameter RXFIFOSIZE = 11,
parameter ADDR_WIDTH = 10,
parameter BUSDEBUG = 1)
(// GPMC signals
input arst,
input EM_CLK, inout [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input [1:0] EM_NBE,
input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
// GPIOs for FIFO signalling
output rx_have_data, output tx_have_space, output resp_have_data,
// FIFO interface
input fifo_clk, input fifo_rst,
output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
output [31:0] debug
);
wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
wire [15:0] EM_D_data;
wire [15:0] EM_D_ctrl;
assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_data : EM_D_ctrl;
// CS4 is RAM_2PORT for DATA PATH (high-speed data)
// Writes go into one RAM, reads come from the other
// CS6 is for CONTROL PATH (slow)
// ////////////////////////////////////////////
// TX Data Path
wire [17:0] tx18_data;
wire tx18_src_rdy, tx18_dst_rdy;
wire [35:0] txb_data;
wire txb_src_rdy, txb_dst_rdy;
gpmc_to_fifo #(.ADDR_WIDTH(10), .LAST_ADDR(10'h3ff), .PTR_WIDTH(2)) gpmc_to_fifo
(.EM_D(EM_D), .EM_A(EM_A[10:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE),
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
.data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
.have_space(tx_have_space));
fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE
(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy),
.f36_dataout(txb_data), .f36_src_rdy_o(txb_src_rdy), .f36_dst_rdy_i(txb_dst_rdy));
fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_buffering(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.datain(txb_data), .src_rdy_i(txb_src_rdy), .dst_rdy_o(txb_dst_rdy),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)
);
// ////////////////////////////////////////////
// RX Data Path
wire [17:0] rx18_data;
wire rx18_src_rdy, rx18_dst_rdy;
wire [35:0] rxb_data;
wire rxb_src_rdy, rxb_dst_rdy;
wire dummy;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_buffering(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
.dataout(rxb_data), .src_rdy_o(rxb_src_rdy), .dst_rdy_i(rxb_dst_rdy)
);
fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE
(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.f36_datain(rxb_data), .f36_src_rdy_i(rxb_src_rdy), .f36_dst_rdy_o(rxb_dst_rdy),
.f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h3ff)) fifo_to_gpmc
(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
.data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy),
.EM_D(EM_D_data), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE),
.data_available(rx_have_data));
// ////////////////////////////////////////////
// Control path on CS6
// ////////////////////////////////////////////////////////////////////
// CTRL TX Data Path
wire [17:0] ctrl18_data;
wire ctrl18_src_rdy, ctrl18_dst_rdy;
wire [35:0] ctrlb_data;
wire ctrlb_src_rdy, ctrlb_dst_rdy;
gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) ctrl_gpmc_to_fifo
(.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE),
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
.data_o(ctrl18_data), .src_rdy_o(ctrl18_src_rdy), .dst_rdy_i(ctrl18_dst_rdy),
.have_space(/*always*/));
fifo19_to_fifo36 #(.LE(1)) ctrl_f19_to_f36 // Little endian because ARM is LE
(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.f19_datain({1'b0,ctrl18_data}), .f19_src_rdy_i(ctrl18_src_rdy), .f19_dst_rdy_o(ctrl18_dst_rdy),
.f36_dataout(ctrlb_data), .f36_src_rdy_o(ctrlb_src_rdy), .f36_dst_rdy_i(ctrlb_dst_rdy));
fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_buffering(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.datain(ctrlb_data), .src_rdy_i(ctrlb_src_rdy), .dst_rdy_o(ctrlb_dst_rdy),
.dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)
);
// ////////////////////////////////////////////
// CTRL RX Data Path
wire [17:0] resp18_data;
wire resp18_src_rdy, resp18_dst_rdy;
wire [35:0] respb_data;
wire respb_src_rdy, respb_dst_rdy;
wire resp_dummy;
fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_buffering(
.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy),
.dataout(respb_data), .src_rdy_o(respb_src_rdy), .dst_rdy_i(respb_dst_rdy)
);
fifo36_to_fifo19 #(.LE(1)) resp_f36_to_f19 // Little endian because ARM is LE
(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
.f36_datain(respb_data), .f36_src_rdy_i(respb_src_rdy), .f36_dst_rdy_o(respb_dst_rdy),
.f19_dataout({resp_dummy,resp18_data}), .f19_src_rdy_o(resp18_src_rdy), .f19_dst_rdy_i(resp18_dst_rdy) );
fifo_to_gpmc #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) resp_fifo_to_gpmc
(.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
.data_i(resp18_data), .src_rdy_i(resp18_src_rdy), .dst_rdy_o(resp18_dst_rdy),
.EM_D(EM_D_ctrl), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE),
.data_available(resp_have_data));
//*
assign debug = {
EM_D,
//resp18_data[15:0], //16
EM_A, //10
//resp18_data[17:16], resp18_src_rdy, resp18_dst_rdy, //4
EM_NCS4, EM_NCS6, EM_NWE, EM_NOE, //4
EM_CLK, resp_have_data //2
};
//*/
endmodule // gpmc
|
module bfm (/*AUTOARG*/
// Inputs
name
);
input [8*5:1] name ;
endmodule
module tb;
// -------------------------------------------------------------------------
/*AUTOOUTPUT*/
// -------------------------------------------------------------------------
/*AUTOINPUT*/
// -------------------------------------------------------------------------
/*AUTOWIRE*/
// -------------------------------------------------------------------------
/* AUTO_CONSTANT ( "name0" "name1" "name2" ) */
// -------------------------------------------------------------------------
/* bfm AUTO_TEMPLATE (
// Inputs
.name ("name@"));
*/
// -------------------------------------------------------------------------
bfm bmf0 (/*AUTOINST*/
// Inputs
.name ("name0")); // Templated
// -------------------------------------------------------------------------
bfm bmf1 (/*AUTOINST*/
// Inputs
.name ("name1")); // Templated
// -------------------------------------------------------------------------
bfm bmf2 (/*AUTOINST*/
// Inputs
.name ("name2")); // Templated
// -------------------------------------------------------------------------
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_alu();
reg sys_clk;
reg alu_rst;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
for(i=0;i<n;i=i+1)
waitclock;
end
endtask
reg [31:0] a;
reg [31:0] b;
reg [1:0] flags;
reg [3:0] opcode;
wire [31:0] r;
pfpu_alu dut(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.flags(flags),
.opcode(opcode),
.r(r),
.r_valid(),
.err_collision()
);
real x;
always begin
alu_rst = 1'b1;
waitclock;
alu_rst = 1'b0;
/* Test addition */
opcode = 4'h1;
waitclock;
opcode = 4'h0;
$tofloat(3.0, a);
$tofloat(9.0, b);
waitnclock(3);
$fromfloat(r, x);
$display("Addition result:\t%f", x);
/* Test subtraction */
opcode = 4'h2;
waitclock;
opcode = 4'h0;
$tofloat(1.0, a);
$tofloat(12.34, b);
waitnclock(3);
$fromfloat(r, x);
$display("Subtraction result:\t%f", x);
/* Test multiplication */
opcode = 4'h3;
waitclock;
opcode = 4'h0;
$tofloat(0.1, a);
$tofloat(45.0, b);
waitnclock(4);
$fromfloat(r, x);
$display("Multiplication result:\t%f", x);
/* Test division */
opcode = 4'h4;
waitclock;
opcode = 4'h0;
$tofloat(1.0, a);
$tofloat(12.34, b);
waitnclock(3);
$fromfloat(r, x);
$display("Division result:\t%f", x);
/* Test float to integer */
opcode = 4'h5;
waitclock;
opcode = 4'h0;
$tofloat(2848.1374, a);
waitclock;
$display("F2I result:\t\t%d", r);
/* Test integer to float */
opcode = 4'h6;
waitclock;
opcode = 4'h0;
a = 32'd398487;
waitnclock(2);
$fromfloat(r, x);
$display("I2F result:\t\t%f", x);
/* Test vector maker */
opcode = 4'h7;
waitclock;
opcode = 4'h0;
a = 32'h0000cafe;
b = 32'h0000babe;
waitnclock(1);
$display("Vect result:\t\t%x", r);
/* Test sine */
opcode = 4'h8;
waitclock;
opcode = 4'h0;
a = -32'd133988374;
waitnclock(3);
$fromfloat(r, x);
$display("Sine result:\t\t%f", x);
/* Test cosine */
opcode = 4'h9;
waitclock;
opcode = 4'h0;
a = -32'd133988374;
waitnclock(3);
$fromfloat(r, x);
$display("Cosine result:\t\t%f", x);
/* Test above */
opcode = 4'ha;
waitclock;
opcode = 4'h0;
$tofloat(21.2984, a);
$tofloat(17.8148, b);
waitnclock(1);
$fromfloat(r, x);
$display("Above result:\t\t%f", x);
$finish;
end
endmodule
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : pkt_ff_wptr
-- Author : mammenx
-- Associated modules:
-- Function : This module maintains the write pointer logic for
the fifo.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module pkt_ff_wptr #(PTR_W = 8)
(
//--------------------- Misc Ports (Logic) -----------
clk,
rst_n,
valid,
sop,
eop,
error.
wptr
//--------------------- Interfaces --------------------
);
//----------------------- Global parameters Declarations ------------------
//----------------------- Input Declarations ------------------------------
input clk;
input rst_n;
input valid;
input sop;
input eop;
input error;
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
output [PTR_W-1:0] wptr;
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
reg [PTR_W-1:0] sop_ptr_f;
//----------------------- Internal Wire Declarations ----------------------
reg wptr_rewind_n_c;
reg wptr_inc_en_c;
//----------------------- Internal Interface Declarations -----------------
//----------------------- FSM Declarations --------------------------------
//----------------------- Start of Code -----------------------------------
always@(posedge clk, negedge rst_n)
begin
if(~rst_n)
begin
sop_ptr_f <= 0;
end
else
begin
//Record the start of packet location for future rewind
sop_ptr_f <= (valid & sop) ? wptr : sop_ptr_f;
end
end
//Reset the wptr to last SOP location
assign wptr_rewind_n_c = (valid & error) ? 1'b0 : rst_n;
//Logic to decide when to increment wptr
assign wptr_inc_en_c = valid & ~error;
//Implement wptr as a gray counter
gry_cntr u_wptr_gry_cntr
(
.clk (clk),
.rst_n (wptr_rewind_n_c),
.rst_val (sop_ptr_f),
.en (wptr_inc_en_c),
.gry_cnt (wptr),
.gry_cnt_nxt ()
);
defparam u_wptr_gry_cntr.WIDTH = PTR_W;
endmodule // pkt_ff_wptr
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-06-2014 03:30:57 PM][mammenx] Moved to Verilog
[08-06-2014 02:11:10 PM][mammenx] Modified gry_cntr reset signal
[08-06-2014 02:07:20 PM][mammenx] Brought out gry_cnt_nxt port
[08-06-2014 12:54:08 PM][mammenx] Initial Commit
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
//////////////////////////////////////////////////////////////////////////////
//
// Main
//
//////////////////////////////////////////////////////////////////////////////
module test();
integer count;
bit test_clk;
// Create a test clock
always #01.8 test_clk = ~test_clk;
//**********************************************************************
// Testing.
// Shift a moving set of ones up the input vector. At each shift
// the outputs should change, which is checked by the assertions
// below. This test doesnt care which output changes, as that was
// checked to be accurate by formal means.
//**********************************************************************
initial begin
count=0;
end
always @(posedge test_clk) begin
count++;
end
//**********************************************************************
// SV assertions
//**********************************************************************
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
lane_inputs);
end // UNMATCHED !!
endproperty //FIXME
property p_sup_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(sup_inputs) |-> !$stable(sup_outputs);
endproperty
a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
sup_inputs);
end
endproperty
endmodule // test
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] narrow;
reg [63:0] quad;
reg [127:0] wide;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [6:0] index;
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
narrow <= 32'h0;
quad <= 64'h0;
wide <= 128'h0;
crc <= 8'hed;
index <= 7'h0;
end
else if (cyc<90) begin
index <= index + 7'h2;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
// verilator lint_off WIDTH
if (index < 9'd20) narrow[index +: 3] <= crc[2:0];
if (index < 9'd60) quad [index +: 3] <= crc[2:0];
if (index < 9'd120) wide [index +: 3] <= crc[2:0];
//
narrow[index[3:0]] <= ~narrow[index[3:0]];
quad [~index[3:0]]<= ~quad [~index[3:0]];
wide [~index[3:0]] <= ~wide [~index[3:0]];
// verilator lint_on WIDTH
end
else if (cyc==90) begin
wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6;
wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6;
wide[82 +: 4] <=4'h6;
end
else if (cyc==91) begin
wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1;
wide[41] <=1'b1; quad[41] <=1'b1;
wide[81] <=1'b1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide);
if (crc != 8'b01111001) $stop;
if (narrow != 32'h001661c7) $stop;
if (quad != 64'h16d49b6f64266039) $stop;
if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 123; const int K = (int)500; const int maxn = (int)2e9; const int mod = (int)1e9 + 7; long long n; vector<long long> v; void solve() { cin >> n; long long cnt = 1; for (int i = 0; i <= 62; ++i) { if (i) { cnt *= 2ll; } long long cnt2 = cnt - 1; long long ok = 0; long long l = 1, r = 1ll * 1e18; while (l <= r) { long long m = l + (r - l) / 2; if (n % m) { if ((m - 1) / 2 + cnt2 < n / m) l = m + 1; else r = m - 1; continue; } if ((m - 1) / 2 + cnt2 == n / m) { if (m % 2) { ok = m + m * cnt2; } break; } if ((m - 1) / 2 + cnt2 < n / m) { l = m + 1; } else { r = m - 1; } } if (ok) { v.push_back(ok); } } if (!(int)v.size()) { cout << -1; return; } sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); for (long long i : v) { cout << i << n ; } } int main() { ios_base ::sync_with_stdio(0), cin.tie(0), cout.tie(0); int q = 1; while (q--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); char ar[n + 2]; char br[n + 2]; scanf( %s%s , ar + 1, br + 1); vector<int> v[2]; for (int i = 1; i <= n; i++) { if (ar[i] != br[i]) { if (ar[i] == a ) v[0].push_back(i); else v[1].push_back(i); } } if ((v[0].size() + v[1].size()) % 2 == 1) cout << -1 << endl; else { int res = v[0].size() + v[1].size(); res /= 2; if (v[0].size() % 2) res += 1; cout << res << endl; for (int i = 1; i < v[0].size(); i += 2) { cout << v[0][i - 1] << << v[0][i] << endl; } for (int i = 1; i < v[1].size(); i += 2) { cout << v[1][i - 1] << << v[1][i] << endl; } if (v[0].size() % 2) { cout << v[0][v[0].size() - 1] << << v[0][v[0].size() - 1] << endl; cout << v[0][v[0].size() - 1] << << v[1][v[1].size() - 1] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int h[15][15]; int dist[15][15]; double expect[15][15]; unordered_map<int, pair<int, int> > dist2pos; int main() { for (int i = 0; i < 10; i++) for (int j = 0; j < 10; ++j) cin >> h[i][j]; for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) { if (i % 2 == 0) { dist[i][j] = i + j + 9 * i; } else { dist[i][j] = i + 9 - j + 9 * i; } dist2pos[dist[i][j]] = make_pair(i, j); } bool left = true; expect[0][0] = 0.0; int x = 0, y = 1; while (true) { double e = 0.0; if (dist[x][y] < 6) { for (int dice = 1; dice <= dist[x][y]; ++dice) { int xx = dist2pos[dist[x][y] - dice].first; int yy = dist2pos[dist[x][y] - dice].second; e += (1.0 / 6.0) * (expect[xx][yy] + 1); } e += (6 - dist[x][y]) / 6.0; e /= (dist[x][y] / 6.0); expect[x][y] = e; } else { for (int dice = 1; dice <= min(6, dist[x][y]); ++dice) { int xx = dist2pos[dist[x][y] - dice].first; int yy = dist2pos[dist[x][y] - dice].second; double next_e; if (h[xx][yy] == 0) { next_e = expect[xx][yy]; } else { int xxx = xx - h[xx][yy]; int yyy = yy; next_e = min(expect[xx][yy], expect[xxx][yyy]); } e = e + (1.0 / 6.0) * next_e; } e += 1.0; expect[x][y] = e; } if (x == 9 && y == 0) break; auto p = dist2pos[dist[x][y] + 1]; x = p.first; y = p.second; } cout << fixed << setprecision(6) << expect[9][0] << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__OR2B_BEHAVIORAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_BEHAVIORAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Chris Randall.
interface ifc;
integer value;
modport out_modport (output value);
endinterface
module m
(
input clk_ip, // verilator tag clk_ip
input rst_ip,
output foo_op); // verilator tag foo_op
// This is a comment
typedef struct packed {
logic clk; /* verilator tag this is clk */
logic k; /* verilator lint_off UNUSED */
logic enable; // verilator tag enable
logic data; // verilator tag data
} my_struct; // verilator tag my_struct
// This is a comment
ifc itop();
my_struct this_struct [2]; // verilator tag this_struct
wire [31:0] dotted = itop.value;
function f(input string m);
$display("%s", m);
endfunction
initial begin
// Contains all 256 characters except 0 (null character)
f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, S; cin >> n >> S; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; long long z = LLONG_MAX; sort(a.begin(), a.end()); long long fh = 0, sh = 0; for (int i = 0; i < n / 2; i++) { if (a[i] > S) fh += a[i] - S; if (a[n - 1 - i] < S) sh += S - a[n - 1 - i]; } cout << fh + sh + abs(a[n / 2] - S); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t-- > 0) { int n; cin >> n; int a[n]; cin >> a[0]; for (int i = 1; i < n; i++) { cin >> a[i]; } vector<int> v; for (int i = 1; i < n - 1; i++) { if ((a[i] > a[i - 1] && a[i] > a[i + 1]) || (a[i] < a[i - 1] && a[i] < a[i + 1])) v.push_back(a[i]); } cout << v.size() + 2 << endl; cout << a[0] << ; for (auto i = v.begin(); i != v.end(); ++i) { cout << *i << ; } cout << a[n - 1] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j, a[110], b[110], a1, b1; cin >> n >> m; for (i = 0; i <= n; i++) cin >> a[i]; for (i = 0; i <= m; i++) cin >> b[i]; a1 = a[0], b1 = b[0]; if (n > m) { if (a1 * b1 > 0) cout << Infinity << endl; else cout << -Infinity << endl; } else if (n < m) { printf( 0/1 n ); } else if (n == m) { for (i = 1; i <= min(abs(a1), abs(b1)); i++) { if (a1 % i == 0 && b1 % i == 0) j = i; } a1 /= j, b1 /= j; if (a1 * b1 > 0) printf( %d/%d n , abs(a1), abs(b1)); else printf( -%d/%d n , abs(a1), abs(b1)); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O211AI_FUNCTIONAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_FUNCTIONAL_V |
module stopwatch(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input CLOCK_50;
input [1:0] KEY;
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire ms_clk;
wire tenths_in, ones_in, tens_in;
wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd;
ms_clock ms_clock1(CLOCK_50, clk);
ms_clock_switched ms_clock_switched1(clk, KEY[0], ms_clk);
bcd_counter bcd_counter_hundredths(ms_clk, KEY[1], hundredths_bcd[3:0], tenths_in);
bcd_counter bcd_counter_tenths(tenths_in, KEY[1], tenths_bcd[3:0], ones_in);
bcd_counter bcd_counter_ones(ones_in, KEY[1], ones_bcd[3:0], tens_in);
bcd_counter bcd_counter_tens(tens_in, KEY[1], tens_bcd[3:0], );
seven_segment_decoder seven_segment_decoder_hundredths(hundredths_bcd[3:0], HEX4[0:6]);
seven_segment_decoder seven_segment_decoder_tenths(tenths_bcd[3:0], HEX5[0:6]);
seven_segment_decoder seven_segment_decoder_ones(ones_bcd[3:0], HEX6[0:6]);
seven_segment_decoder seven_segment_decoder_tens(tens_bcd[3:0], HEX7[0:6]);
//Turn the unused displays off
assign HEX3[0:6] = 7'b0100100;
assign HEX2[0:6] = 7'b0110000;
assign HEX1[0:6] = 7'b0110001;
assign HEX0[0:6] = 7'b0100100;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_V |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: rx_lane_logic
*
*/
`default_nettype none
module rx_lane_logic #(
parameter DWIDTH = 512,
parameter NUM_LANES = 8,
parameter LANE_DWIDTH = (DWIDTH/NUM_LANES),
parameter CTRL_LANE_POLARITY = 1,
parameter BITSLIP_SHIFT_RIGHT= 1
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----CONNECT
//----------------------------------
input wire [LANE_DWIDTH-1:0] scrambled_data_in,
input wire bit_slip, //bit slip per lane
input wire lane_polarity,
output wire [LANE_DWIDTH-1:0] descrambled_data_out,
output wire descrambler_locked,
input wire descrambler_disable
);
wire [LANE_DWIDTH-1:0] descrambled_data_out_tmp;
wire [LANE_DWIDTH-1:0] data_2_descrambler;
wire descrambler_locked_tmp;
assign descrambler_locked = descrambler_disable ? 1'b1 : descrambler_locked_tmp;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
generate
if(CTRL_LANE_POLARITY==1) begin
reg [LANE_DWIDTH-1:0] scrambled_data_in_reg;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
scrambled_data_in_reg <= {LANE_DWIDTH{1'b0}};
end
else begin
scrambled_data_in_reg <= scrambled_data_in^{LANE_DWIDTH{lane_polarity}};
end
end
assign data_2_descrambler = scrambled_data_in_reg;
assign descrambled_data_out = descrambler_disable ? scrambled_data_in_reg : descrambled_data_out_tmp;
end else begin
assign data_2_descrambler = scrambled_data_in;
assign descrambled_data_out = descrambler_disable ? scrambled_data_in : descrambled_data_out_tmp;
end
endgenerate
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//Descrambler Init
rx_descrambler #(
.DWIDTH(LANE_DWIDTH),
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
) descrambler_I (
.clk(clk),
.res_n(res_n),
.bit_slip(bit_slip),
.locked(descrambler_locked_tmp),
.data_in(data_2_descrambler),
.data_out(descrambled_data_out_tmp)
);
endmodule
`default_nettype wire |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg printclk;
// verilator lint_on GENCLK
ps ps (printclk);
reg [7:0] a;
wire [7:0] z;
l1 u (~a,z);
always @ (posedge clk) begin
printclk <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
printclk <= 1'b1;
end
if (cyc==2) begin
a <= 8'b1;
end
if (cyc==3) begin
if (z !== 8'hf8) $stop;
//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
`ifdef USE_PUBLIC
`define PUBLIC /*verilator public*/
`else
`define PUBLIC
`endif
module ps (input printclk);
`INLINE_MODULE
// Check that %m stays correct across inlines
always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
endmodule
module l1 (input [7:0] a, output [7:0] z `PUBLIC);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
assign z = z0+z1;
l2 u0 (a, z0); l2 u1 (a, z1);
endmodule
module l2 (input [7:0] a, output [7:0] z `PUBLIC);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l3 u0 (a, z0); l3 u1 (a1, z1);
endmodule
module l3 (input [7:0] a, output [7:0] z `PUBLIC);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l4 u0 (a, z0); l4 u1 (a1, z1);
endmodule
module l4 (input [7:0] a, output [7:0] z `PUBLIC);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
endmodule
module l5 (input [7:0] a, output [7:0] z `PUBLIC);
`INLINE_MODULE
parameter PARAM = 5;
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
assign z = a;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLRTN_FUNCTIONAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ms__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ms__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_FUNCTIONAL_V |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module rx_dcoffset
#(parameter WIDTH=16,
parameter ADDR=8'd0,
parameter alpha_shift=20)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [WIDTH-1:0] in, output [WIDTH-1:0] out);
wire set_now = set_stb & (ADDR == set_addr);
reg fixed; // uses fixed offset
wire [WIDTH-1:0] fixed_dco;
localparam int_width = WIDTH + alpha_shift;
reg [int_width-1:0] integrator;
wire [WIDTH-1:0] quantized;
always @(posedge clk)
if(rst)
begin
fixed <= 0;
integrator <= {int_width{1'b0}};
end
else if(set_now)
begin
fixed <= set_data[31];
if(set_data[30])
integrator <= {set_data[29:0],{(int_width-30){1'b0}}};
end
else if(~fixed)
integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out};
round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
(.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out());
add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
(.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out());
endmodule // rx_dcoffset
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND4BB_PP_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000008; int n, m, k, d, i, j, e; int tmp[N], pos[N], p[N], c[N]; char s[N]; int main() { scanf( %s %d , s, &m); n = strlen(s); while (m--) { scanf( %d%d , &k, &d); for (i = 0; i < n; i++) { c[i] = (i + 1) % n; pos[i] = p[i] = i; } int t = 0; for (i = 0; i < d; i++) for (j = i; j < k; t++, j += d) p[t] = j; for (i = 0; i < n; ++i) { c[i] = p[c[i]]; } for (e = n - k + 1; e; e >>= 1) { for (i = 0; i < n; ++i) tmp[i] = c[i]; if (e & 1) for (i = 0; i < n; ++i) pos[i] = c[pos[i]]; for (i = 0; i < n; ++i) c[i] = tmp[c[i]]; } for (i = 0; i < n; ++i) tmp[(i + n - k + 1) % n] = s[pos[i]]; for (i = 0; i < n; ++i) putchar(s[i] = (char)tmp[i]); putchar( n ); } } |
#include <bits/stdc++.h> using namespace std; int seq[100050]; int n; int l[40], r[40]; int dp[100050]; bool chk() { for (int i = 1; i <= n; ++i) if (seq[i] != i) return false; return true; } void dfs(int dep) { if (chk()) { printf( %d n , dep); for (int i = dep; i >= 1; --i) printf( %d %d n , l[i], r[i]); exit(0); } if (dep == 3) return; for (int i = 1; i <= n - 1; ++i) { if (seq[i] != i && (abs(seq[i] - seq[i - 1]) != 1 || abs(seq[i] - seq[i + 1]) != 1)) { for (int j = i + 1; j <= n; ++j) if (seq[j] != j && (abs(seq[j] - seq[j + 1]) != 1 || abs(seq[j] - seq[j - 1]) != 1)) { l[dep + 1] = i; r[dep + 1] = j; reverse(seq + i, seq + j + 1); dfs(dep + 1); reverse(seq + i, seq + j + 1); } } } } int main() { seq[0] = -1; scanf( %d , &n); seq[n + 1] = -1; for (int i = 1; i <= n; ++i) scanf( %d , &seq[i]); dfs(0); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_BEHAVIORAL_PP_V |
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
// ###############################################################
// # FUNCTION: Synchronous clock divider that divides by integer
// ###############################################################
module clock_divider(/*AUTOARG*/
// Outputs
clkout,
// Inputs
clkin, divcfg, reset
);
input clkin; // Input clock
input [3:0] divcfg; // Divide factor (1-128)
input reset; // Counter init
output clkout; // Divided clock phase aligned with clkin
reg clkout_reg;
reg [7:0] counter;
reg [7:0] divcfg_dec;
reg [3:0] divcfg_reg;
wire div_bp;
wire posedge_match;
wire negedge_match;
// ###################
// # Decode divcfg
// ###################
always @ (divcfg[3:0])
casez (divcfg[3:0])
4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
default : divcfg_dec[7:0] = 8'b00000000; // others
endcase
always @ (posedge clkin or posedge reset)
if(reset)
counter[7:0] <= 8'b00000001;
else if(posedge_match)
counter[7:0] <= 8'b00000001;// Self resetting
else
counter[7:0] <= (counter[7:0] + 8'b00000001);
assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
always @ (posedge clkin or posedge reset)
if(reset)
clkout_reg <= 1'b0;
else if(posedge_match)
clkout_reg <= 1'b1;
else if(negedge_match)
clkout_reg <= 1'b0;
//Divide by one bypass
assign div_bp = (divcfg[3:0]==4'b0000);
assign clkout = div_bp ? clkin : clkout_reg;
endmodule // clock_divider
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "baudgen.vh"
//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- ____________________| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------->
//--
//---------------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (BAUDRATE >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; deque<int> d; string mot; int n; void f(int i) { if (i == n) return; else { f(i + 1); if (mot[i] == l ) { d.push_back(i + 1); } else { d.push_front(i + 1); } } } int main() { cin >> mot; n = mot.size(); f(0); for (int i = 0; i < n; i++) cout << d[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Point { double x, y, z; }; double len[10000]; double sum[10000]; int n; Point point[10001], potter; double vp, vs; double getDist(Point &a, Point &b) { double x = a.x - b.x; double y = a.y - b.y; double z = a.z - b.z; return sqrt(x * x + y * y + z * z); } double getGapConst(Point &tar, Point &vec) { if (!(abs(vec.x - 0.0) < 1e-10)) return tar.x / vec.x; if (!(abs(vec.y - 0.0) < 1e-10)) return tar.y / vec.y; return tar.z / vec.z; } int main(void) { scanf( %d , &n); for (int i = 0; i <= n; i++) scanf( %lf %lf %lf , &point[i].x, &point[i].y, &point[i].z); scanf( %lf %lf , &vp, &vs); scanf( %lf %lf %lf , &potter.x, &potter.y, &potter.z); if ((abs(point[0].x - potter.x) < 1e-10) && (abs(point[0].y - potter.y) < 1e-10) && (abs(point[0].z - potter.z) < 1e-10)) { printf( YES n ); printf( 0 n ); printf( %lf %lf %lf n , potter.x, potter.y, potter.z); return 0; } for (int i = 0; i < n; i++) { len[i] = getDist(point[i], point[i + 1]); if (i == 0) sum[i] = 0; else sum[i] = sum[i - 1] + len[i - 1]; } bool isFound = false; for (int i = 0; i < n; i++) { Point vec; vec.x = point[i + 1].x - point[i].x; vec.y = point[i + 1].y - point[i].y; vec.z = point[i + 1].z - point[i].z; double startRatio = sum[i] / len[i]; Point start; start.x = point[i].x - startRatio * vec.x; start.y = point[i].y - startRatio * vec.y; start.z = point[i].z - startRatio * vec.z; Point unit; unit.x = vec.x / len[i]; unit.y = vec.y / len[i]; unit.z = vec.z / len[i]; double s = 0, e = 1, mid; for (int q = 0; q < 40; q++) { mid = (s + e) / 2; Point tar; tar.x = point[i].x + vec.x * mid; tar.y = point[i].y + vec.y * mid; tar.z = point[i].z + vec.z * mid; double dist = getDist(tar, potter); double reqTime = dist / vp; Point snitch; snitch.x = start.x + unit.x * vs * reqTime; snitch.y = start.y + unit.y * vs * reqTime; snitch.z = start.z + unit.z * vs * reqTime; Point gap; gap.x = snitch.x - point[i].x; gap.y = snitch.y - point[i].y; gap.z = snitch.z - point[i].z; double gapConst = getGapConst(gap, vec); if ((abs(mid - gapConst) < 1e-10)) { isFound = true; printf( YES n ); printf( %.10lf n , reqTime); printf( %.10lf %.10lf %.10lf n , tar.x, tar.y, tar.z); break; } else if (mid > gapConst) e = mid; else s = mid; } if (isFound) break; } if (!isFound) printf( NO n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:50:10 11/03/2014
// Design Name:
// Module Name: Output_2_Disp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Multi_8CH32(input clk,
input rst,
input EN, //Write EN
input[2:0]Test, //ALU&Clock,SW[7:5]
input[63:0]point_in, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öСÊýµã
input[63:0]LES, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öÉÁ˸λ
input[31:0] Data0, //disp_cpudata
input[31:0] data1,
input[31:0] data2,
input[31:0] data3,
input[31:0] data4,
input[31:0] data5,
input[31:0] data6,
input[31:0] data7,
output [7:0] point_out,
output [7:0] LE_out,
output [31:0]Disp_num
);
reg[31:0] disp_data = 32'hAA5555AA;
reg[7:0] cpu_blink = 8'b11111111, cpu_point = 4'b00000000;
MUX8T1_32 MUX1_DispData(.I0(disp_data),
.I1(data1),
.I2(data2),
.I3(data3),
.I4(data4),
.I5(data5),
.I6(data6),
.I7(data7),
.s(Test), //ÏÔʾÐźÅÑ¡Ôñ£¬Test=SW[7:5]¿ØÖÆ
.o(Disp_num) //Æ߶ÎÂëÏÔʾÐÅÏ¢
);
MUX8T1_8 MUX2_Blink(.I0(cpu_blink),
.I1(LES[15:8]),
.I2(LES[23:16]),
.I3(LES[31:24]),
.I4(LES[39:32]),
.I5(LES[47:40]),
.I6(LES[55:48]),
.I7(LES[63:56]),
.s(Test), //ÏÔʾÐźÅÑ¡Ôñ£¬Test=SW[7:5]¿ØÖÆ
.o(LE_out) //Æ߶ÎÂëСÊýµãÏÔʾÐÅÏ¢
);
MUX8T1_8 MUX3_Point(.I0(cpu_point),
.I1(point_in[15:7]),
.I2(point_in[23:16]),
.I3(point_in[31:24]),
.I4(point_in[39:32]),
.I5(point_in[47:40]),
.I6(point_in[55:48]),
.I7(point_in[63:56]),
.s(Test), //ÏÔʾÐźÅÑ¡Ôñ£¬Test=SW[7:5]¿ØÖÆ
.o(point_out) //Æ߶ÎÂëÏÔʾÉÁ˸λָʾ
);
always@(posedge clk )begin
if(EN) begin
disp_data <= Data0; //Data0
cpu_blink <= LES[7:0];
cpu_point <= point_in[7:0];
end
else begin
disp_data <= disp_data;
cpu_blink <= cpu_blink;
cpu_point <= cpu_point;
end
end
/* always@* begin
case (Test) //ÏÔʾÐźÅÑ¡Ôñ£¬Test=SW[7:5]¿ØÖÆ
3'b000:begin
blink_out <= cpu_blink;
point_out <= cpu_point;
end
3'b001:begin
blink_out <= blink_in[7:4];
point_out <= point_in[7:4];
end
3'b010:begin
blink_out <= blink_in[11:8];
point_out <= point_in[11:8];
end
3'b011:begin
blink_out <= blink_in[15:12];
point_out <= point_in[15:12];
end
3'b100:
begin
point_out <= point_in[19:16];
blink_out <= blink_in[19:16];
end
3'b101:begin
point_out <= point_in[23:20];
blink_out <= blink_in[23:20];
end
3'b110:begin
point_out <= point_in[27:24];
blink_out <= blink_in[27:24];
end
4'b111:begin
point_out <= point_in[31:28];
blink_out <= blink_in[31:28];
end
endcase
end
*/
endmodule
/*module seven_seg_Dev_IO(input clk,
input rst,
input GPIOe0000000_we, //EN
input[2:0]Test, //ALU&Clock,SW[7:5]
input[31:0]point_in, //Õë¶Ô8¸öÏÔʾÊäÈë¸÷4¸öСÊýµã
input[31:0]blink_in,
input[31:0] Data0, //disp_cpudata
input[31:0] Test_data1,
input[31:0] Test_data2,
input[31:0] Test_data3,
input[31:0] Test_data4,
input[31:0] Test_data5,
input[31:0] Test_data6,
input[31:0] Test_data7,
output reg[3:0] point_out,
output reg[3:0] blink_out,
output reg[31:0]Disp_num=32'h12345678
);
always@(posedge clk or posedge rst) begin //ÏÔʾÐźÅÑ¡Ôñ£¬ÓÃSW[7:5]¿ØÖÆ
if(rst)
Disp_num <= 32'hAA5555AA;
else begin
point_out <= 4'b1111;
blink_out <= 4'b0000;
case (Test)
3'b000:begin
if(GPIOe0000000_we) begin Disp_num <= Data0; //Data0
blink_out <= blink_in[3:0];
point_out <= point_in[3:0];end
else begin Disp_num <= Disp_num;
blink_out <= blink_out;
point_out <= point_in[3:0]; end
end
3'b001:begin //pc[31:2]
Disp_num <= Test_data1;
blink_out <= blink_in[7:4];
point_out <= point_in[7:4];
end
3'b010:begin //counter[31:0]
Disp_num <= Test_data2;
blink_out <= blink_in[11:8];
point_out <= point_in[11:8];
end
3'b011:begin //Inst
Disp_num <= Test_data3;
blink_out <= blink_in[15:12];
point_out <= point_in[15:12];
end
3'b100: //addr_bus
begin
Disp_num <= Test_data4;
point_out <= point_in[19:16];
blink_out <= blink_in[19:16];
end
3'b101:begin //Cpu_data2bus;
Disp_num<=Test_data5;
point_out <= point_in[23:20];
blink_out <= blink_in[23:20];
end
3'b110:begin //Cpu_data4bus;
Disp_num<=Test_data6;
point_out <= point_in[27:24];
blink_out <= blink_in[27:24];
end
4'b111:begin //pc;
Disp_num<=Test_data7;
point_out <= point_in[31:28];
blink_out <= blink_in[31:28];
end
endcase
end
end
endmodule
*/ |
#include <bits/stdc++.h> using namespace std; const int MAXK = 21; long long dp[(1 << MAXK)]; int n, m; string s; long long d[MAXK][MAXK]; long long solve(int mask) { if (mask == ((1 << m) - 1)) return 0ll; long long &ret = dp[mask]; if (ret != -1) return ret; ret = 1e10; long long cost = __builtin_popcount(mask); for (int i = 0; i < m; ++i) { if ((mask & (1 << i))) continue; long long now = solve(mask | (1 << i)); for (int j = 0; j < m; ++j) { if (i == j) continue; if ((mask & (1 << j))) now += cost * d[i][j]; else now -= cost * d[i][j]; } ret = min(ret, now); } return ret; } int main() { memset(dp, -1, sizeof(dp)); ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n >> m; cin >> s; for (int i = 0; i < n - 1; ++i) { int a = s[i] - a ; int b = s[i + 1] - a ; d[a][b]++; if (a != b) d[b][a]++; } return cout << solve(0) << n , 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O2111AI_FUNCTIONAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; long long int res = 1; if (k == 1) { cout << n; } else { while (res <= n) res = (long long)(res * 2); cout << res - 1; } return 0; } |
#include <bits/stdc++.h> const long long int mx = 1e9 + 7; using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n, t; cin >> t; while (t--) { int n, k; cin >> n >> k; vector<pair<int, int>> vp, vpAns; map<int, int> mp, mpAns, mpCnt; int A[n + 2], x = n / k; for (int i = 0; i < n; i++) { cin >> A[i]; vp.push_back(make_pair(A[i], i)); } sort(vp.begin(), vp.end()); int cnt = 0, cn = 0; for (int i = 0; i < n; i++) { int a = vp[i].first, b = vp[i].second; mp[a]++; if (mp[a] > k) { vpAns.push_back(make_pair(b, 0)); continue; } cnt++; vpAns.push_back(make_pair(b, cnt)); mpCnt[cnt]++; if (cnt == k) cnt = 0; } int mn = 10000000; for (auto u : mpCnt) { mn = min(mn, u.second); } sort(vpAns.begin(), vpAns.end()); for (int i = 0; i < vpAns.size(); i++) { int b = vpAns[i].second; mpAns[b]++; if (mpAns[b] > mn) cout << 0 << ; else cout << vpAns[i].second << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int N, M, x, y; cin >> N >> M >> x >> y; x--; y--; cout << x + 1 << << y + 1 << endl; for (int i = 1; i < x; i++) cout << i + 1 << << y + 1 << endl; for (int i = x + 1; i < N; i++) cout << i + 1 << << y + 1 << endl; cout << 1 << << y + 1 << endl; int uneven = 0; for (int j = 0; j < M; j++) { if (j == y) { uneven = 1; continue; } if (j % 2 == uneven) { for (int i = 0; i < N; i++) { cout << i + 1 << << j + 1 << endl; } } if (j % 2 != uneven) { for (int i = N - 1; i > -1; i--) { cout << i + 1 << << j + 1 << endl; } } } } |
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const double eps = 1e-9; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } struct Point { int x, y; }; struct Line { int A, B, C; Line(int a = 0, int b = 1, int c = 0) : A(a), B(b), C(c) { int g = gcd(gcd(abs(A), abs(B)), abs(C)); A /= g; B /= g; C /= g; if (A < 0 || (A == 0 || B < 0)) { A = -A; B = -B; C = -C; } } }; Line getLine(const Point &a, const Point &b) { int dx = b.x - a.x; int dy = -(b.y - a.y); return Line(dy, dx, dy * a.x + dx * a.y); } Line perpLine(const Line &li, const Point &p) { int a = -li.B, b = li.A; return Line(a, b, p.x * a + p.y * b); } bool operator<(const Line &g, const Line &h) { if (g.A != h.A) return g.A < h.A; if (g.B != h.B) return g.B < h.B; return g.C < h.C; } const int maxN = 1024; int N, K; map<int, vector<Point>> circ; map<Line, map<int, int>> segs; int main() { cin >> N >> K; for (int i = (0); i < (N); i++) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; Point a{x1 * 2, y1 * 2}; Point b{x2 * 2, y2 * 2}; Line li = getLine(a, b); { if (0) fprintf(stderr, li: a %d, b %d, c %d n , li.A, li.B, li.C); }; int pa = a.x * li.B - a.y * li.A; int push_back = b.x * li.B - b.y * li.A; if (pa > push_back) swap(pa, push_back); segs[li][pa + 0]++; segs[li][push_back + 1]--; } for (int i = (0); i < (K); i++) { int x, y, r; cin >> x >> y >> r; circ[r * 2].push_back(Point{x * 2, y * 2}); } for (auto &s : segs) { s.second[INT_MIN / 2] = 0; s.second[INT_MAX / 2] = 0; { if (0) fprintf(stderr, seg n ); }; int prev = 0; for (auto &e : s.second) { { if (0) fprintf(stderr, %d: %d n , e.first, e.second); }; e.second = (prev += e.second); { if (0) fprintf(stderr, %d n , prev); }; } } int res = 0; for (const auto &ci : circ) { for (int ia = (0); ia < (int((ci.second).size())); ia++) { for (int ib = (ia + 1); ib < (int((ci.second).size())); ib++) { Point a = ci.second[ia]; Point b = ci.second[ib]; Point d{b.x - a.x, b.y - a.y}; if (d.x * d.x + d.y * d.y <= ci.first * ci.first * 4) continue; Point m{a.x + d.x / 2, a.y + d.y / 2}; { if (0) fprintf(stderr, M: %d %d n , m.x, m.y); }; Line li = perpLine(getLine(a, b), m); { if (0) fprintf(stderr, li: a %d, b %d, c %d n , li.A, li.B, li.C); }; if (!((segs).find(li) != (segs).end())) continue; int pp = m.x * li.B - m.y * li.A; { if (0) cerr << DBGDO: << ( pp ) << = << (pp) << endl; }; auto it = segs[li].upper_bound(pp); assert(it != segs[li].begin()); it--; res += it->second; } } } cout << res << endl; } |
// main control unit thant gets
module mcu(clk, clr, OP, MemRead, MemWrite, MemtoReg, ALUOp, ALUSrc, RegWrite, RegDst, Branch, JumpSignal);
input clk, clr;
input [5:0] OP;
output MemRead, MemWrite, MemtoReg, ALUSrc, RegWrite, RegDst, Branch, JumpSignal;
reg MemRead, MemWrite, MemtoReg, ALUSrc, RegWrite, RegDst, Branch, JumpSignal;
output [1:0] ALUOp;
reg [1:0] ALUOp;
always @(OP)
begin
case (OP)
6'b100011: // lw
begin
MemRead = 1;
MemWrite = 0;
MemtoReg = 1;
ALUOp = 2'b00;
ALUSrc = 1;
RegWrite = 1;
RegDst = 0;
Branch = 0;
JumpSignal = 0;
end
6'b101011: // sw
begin
MemRead = 0;
MemWrite = 1;
MemtoReg = 0;
ALUOp = 2'b00;
ALUSrc = 1;
RegWrite = 0;
Branch = 0;
JumpSignal = 0;
end
0: // add or sub
begin
MemRead = 0;
MemWrite = 0;
MemtoReg = 0;
ALUOp = 2'b10;
ALUSrc = 0;
RegWrite = 1;
RegDst = 1;
Branch = 0;
JumpSignal = 0;
end
4: // beq
begin
MemRead = 0;
MemWrite = 0;
ALUOp = 2'b01;
ALUSrc = 0;
RegWrite = 0;
Branch = 1;
JumpSignal = 0;
end
2: // j
begin
MemRead = 0;
MemWrite = 0;
RegWrite = 0;
Branch = 0;
JumpSignal = 1;
end
3: // nop
begin
MemRead = 0;
MemWrite = 0;
RegWrite = 0;
Branch = 0;
JumpSignal = 0;
end
endcase
end
initial
begin
MemRead = 0;
MemWrite = 0;
RegWrite = 0;
Branch = 0;
JumpSignal = 0;
end
endmodule
module acu(funct, ALUOp, ALUcontrol);
input [5:0] funct;
input [1:0] ALUOp;
output [2:0] ALUcontrol;
reg [2:0] ALUcontrol;
always @(funct or ALUOp)
begin
case(ALUOp)
2'b00: ALUcontrol = 3'b010;
2'b01: ALUcontrol = 3'b110;
2'b10:
begin
case(funct)
6'b100000: ALUcontrol = 3'b010;
6'b100010: ALUcontrol = 3'b110;
6'b100100: ALUcontrol = 3'b000;
6'b100101: ALUcontrol = 3'b001;
6'b101010: ALUcontrol = 3'b111;
endcase
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; char c[10005]; int main() { int i, a, b, l1, l2; a = b = l1 = l2 = 0; scanf( %d , &n); scanf( %s , &c[1]); for (i = 1; i <= n; i++) { if (c[i] == L ) a++; if (c[i] == R ) b++; } if (a == 0 && b == 0) l1 = l2 = 1; else if (a == 0) { for (i = 1; i <= n; i++) { if (c[i] == R ) { if (l1 == 0) l1 = i; l2 = i + 1; } } } else if (b == 0) { for (i = 1; i <= n; i++) { if (c[i] == L ) { if (l2 == 0) l2 = i - 1; l1 = i; } } } else { for (i = 1; i <= n; i++) { if (c[i] == R ) { if (l1 == 0) l1 = i; l2 = i; } } } printf( %d %d , l1, l2); return 0; } |
//////////////////////////////////////////////////////////////////
// //
// Generic Library SRAM with per byte write enable //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Configurable depth and width. The DATA_WIDTH must be a //
// multiple of 8. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module generic_sram_byte_en
#(
parameter DATA_WIDTH = 128,
parameter ADDRESS_WIDTH = 7
)
(
input i_clk,
input [DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
input [DATA_WIDTH/8-1:0] i_byte_enable,
output reg [DATA_WIDTH-1:0] o_read_data
);
reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];
integer i;
always @(posedge i_clk)
begin
// read
o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
// write
if (i_write_enable)
for (i=0;i<DATA_WIDTH/8;i=i+1)
begin
mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0] ;
mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1] ;
mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2] ;
mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3] ;
mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4] ;
mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5] ;
mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6] ;
mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7] ;
end
end
endmodule
|
/**
* bsg_cache_to_dram_ctrl.v
*
* @author tommy
*
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache_to_dram_ctrl
import bsg_cache_pkg::*;
import bsg_dmc_pkg::*;
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, localparam mask_width_lp=(data_width_p>>3)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, parameter dram_ctrl_addr_width_p=(addr_width_p+lg_num_cache_lp)
, localparam num_req_lp=(block_size_in_words_p/dram_ctrl_burst_len_p)
)
(
input clk_i
, input reset_i
// dram size selection
// {0:256Mb, 1:512Mb, 2:1Gb, 3:2Gb, 4:4Gb}
, input [2:0] dram_size_i
// cache side
, input [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_i
, input [num_cache_p-1:0] dma_pkt_v_i
, output logic [num_cache_p-1:0] dma_pkt_yumi_o
, output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_ready_i
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
// dmc side
, output logic app_en_o
, input app_rdy_i
, output app_cmd_e app_cmd_o
, output logic [dram_ctrl_addr_width_p-1:0] app_addr_o
, output logic app_wdf_wren_o
, input app_wdf_rdy_i
, output logic [data_width_p-1:0] app_wdf_data_o
, output logic [mask_width_lp-1:0] app_wdf_mask_o
, output logic app_wdf_end_o
, input app_rd_data_valid_i
, input [data_width_p-1:0] app_rd_data_i
, input app_rd_data_end_i
);
// round robin for dma pkts
//
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_dma_pkt_s dma_pkt;
logic rr_v_lo;
logic [lg_num_cache_lp-1:0] rr_tag_lo;
logic rr_yumi_li;
bsg_round_robin_n_to_1 #(
.width_p(dma_pkt_width_lp)
,.num_in_p(num_cache_p)
,.strict_p(0)
) cache_rr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_pkt_i)
,.v_i(dma_pkt_v_i)
,.yumi_o(dma_pkt_yumi_o)
,.v_o(rr_v_lo)
,.data_o(dma_pkt)
,.tag_o(rr_tag_lo)
,.yumi_i(rr_yumi_li)
);
logic [lg_num_cache_lp-1:0] tag_r, tag_n;
// rx module
//
logic rx_v_li;
logic rx_ready_lo;
bsg_cache_to_dram_ctrl_rx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dram_ctrl_burst_len_p(dram_ctrl_burst_len_p)
) rx (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(rx_v_li)
,.tag_i(tag_r)
,.ready_o(rx_ready_lo)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_ready_i(dma_data_ready_i)
,.app_rd_data_valid_i(app_rd_data_valid_i)
,.app_rd_data_i(app_rd_data_i)
,.app_rd_data_end_i(app_rd_data_end_i)
);
// tx module
//
logic tx_v_li;
logic tx_ready_lo;
bsg_cache_to_dram_ctrl_tx #(
.num_cache_p(num_cache_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dram_ctrl_burst_len_p(dram_ctrl_burst_len_p)
) tx (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tx_v_li)
,.tag_i(tag_r)
,.ready_o(tx_ready_lo)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_yumi_o(dma_data_yumi_o)
,.app_wdf_wren_o(app_wdf_wren_o)
,.app_wdf_rdy_i(app_wdf_rdy_i)
,.app_wdf_data_o(app_wdf_data_o)
,.app_wdf_mask_o(app_wdf_mask_o)
,.app_wdf_end_o(app_wdf_end_o)
);
// dma request
//
typedef enum logic {
WAIT,
SEND_REQ
} req_state_e;
req_state_e req_state_r, req_state_n;
logic [addr_width_p-1:0] addr_r, addr_n;
logic write_not_read_r, write_not_read_n;
logic [`BSG_SAFE_CLOG2(num_req_lp)-1:0] req_cnt_r, req_cnt_n;
always_comb begin
app_en_o = 1'b0;
app_cmd_o = WR;
rr_yumi_li = 1'b0;
tag_n = tag_r;
write_not_read_n = write_not_read_r;
rx_v_li = 1'b0;
tx_v_li = 1'b0;
req_state_n = req_state_r;
req_cnt_n = req_cnt_r;
addr_n = addr_r;
case (req_state_r)
WAIT: begin
if (rr_v_lo) begin
rr_yumi_li = 1'b1;
tag_n = rr_tag_lo;
addr_n = dma_pkt.addr;
write_not_read_n = dma_pkt.write_not_read;
req_cnt_n = '0;
req_state_n = SEND_REQ;
end
end
SEND_REQ: begin
app_en_o = (write_not_read_r
? tx_ready_lo
: rx_ready_lo);
app_cmd_o = write_not_read_r
? WR
: RD;
rx_v_li = ~write_not_read_r & rx_ready_lo & app_rdy_i;
tx_v_li = write_not_read_r & tx_ready_lo & app_rdy_i;
addr_n = (app_rdy_i & app_en_o)
? addr_r + (1 << `BSG_SAFE_CLOG2(dram_ctrl_burst_len_p*data_width_p/8))
: addr_r;
req_cnt_n = (app_rdy_i & app_en_o)
? req_cnt_r + 1
: req_cnt_r;
req_state_n = app_rdy_i & app_en_o & (req_cnt_r == num_req_lp-1)
? WAIT
: SEND_REQ;
end
endcase
end
// Append tag_r to top bits of dram address
// tag_r not used when only 1 cache exists
always_comb
case (dram_size_i)
0: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[25-$clog2(num_cache_p)-1:0]});
1: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[26-$clog2(num_cache_p)-1:0]});
2: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[27-$clog2(num_cache_p)-1:0]});
3: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[28-$clog2(num_cache_p)-1:0]});
4: app_addr_o = dram_ctrl_addr_width_p'({tag_r, addr_r[29-$clog2(num_cache_p)-1:0]});
default: app_addr_o = {tag_r, addr_r};
endcase
// sequential
//
always_ff @ (posedge clk_i) begin
if (reset_i) begin
req_state_r <= WAIT;
tag_r <= '0;
addr_r <= '0;
req_cnt_r <= '0;
write_not_read_r <= 1'b0;
end
else begin
req_state_r <= req_state_n;
tag_r <= tag_n;
addr_r <= addr_n;
req_cnt_r <= req_cnt_n;
write_not_read_r <= write_not_read_n;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_dram_ctrl)
|
#include <bits/stdc++.h> using namespace std; char ini[101], des[101]; int main() { int i, L = strlen(ini), j; gets(ini); gets(des); for (i = 0; ini[i]; i++) { for (j = i + 1; ini[j]; j++) { if (ini[i] > ini[j]) { swap(ini[i], ini[j]); } } } for (i = 0; ini[i]; i++) { if (ini[i] != 0 ) break; } if (ini[i]) { swap(ini[i], ini[0]); } if (!strcmp(ini, des)) { puts( OK ); } else { puts( WRONG_ANSWER ); } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:39:09 11/03/2014
// Design Name: spi_bonus
// Module Name: C:/ece4743/projects/spi_bonus_solution/tb_spi_bonus.v
// Project Name: spi_bonus_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spi_bonus
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_spi_bonus;
// Inputs
reg clk;
reg reset;
reg [7:0] din;
reg wren;
reg rden;
reg [1:0] addr;
reg miso;
// Outputs
wire [7:0] dout;
wire mosi;
wire sclk;
// Instantiate the Unit Under Test (UUT)
spi_bonus uut (
.clk(clk),
.reset(reset),
.din(din),
.dout(dout),
.wren(wren),
.rden(rden),
.addr(addr),
.mosi(mosi),
.miso(miso),
.sclk(sclk)
);
reg invert_mosi;
always @* begin
miso = invert_mosi? ~mosi:mosi;
end
`define FSIZE 1024
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer errors;
integer i;
reg [7:0] outdata;
integer all_vectors_done;
initial begin
clk = 0;
#100 //reset delay
forever #10 clk = ~clk;
end
reg checktrigger;
task applydata;
input [7:0] val;
begin
@(negedge clk);
infifo[head] = val;
head = head + 1;
if (head == `FSIZE) head = 0;
checktrigger = 1; //trigger output check process
din = val;
wren = 1;
addr = 2'b00;
@(negedge clk);
wren = 0;
checktrigger = 0;
@(negedge clk);
end
endtask
task getserialdata;
input [7:0] expecteddata;
begin
outdata = 0;
i = 0;
while (i != 8) begin
outdata = outdata << 1;
@(negedge sclk);
outdata[0] = mosi;
i = i + 1;
end
if (outdata != expecteddata) begin
errors = errors + 1;
$display("%t: FAIL,expected serial MOSI out of %h, found: %h",$time,expecteddata,outdata);
end else begin
$display("%t: PASS,got expected serial MOSI out of %h",$time,expecteddata);
end
end
endtask
task rddatardy; //read the data rdy flag
input expectedbit;
begin
@(negedge clk);
addr = 2;
rden = 1;
@(negedge clk);
if (dout[1] != expectedbit) begin
errors = errors + 1;
$display("%t: FAIL, reading SPI DATARDY bit, expected: %h, actual: %h.",$time,expectedbit,dout[1]);
end else begin
$display("%t: PASS, reading SPI DATARDY bit.",$time);
end
rden = 0;
end
endtask
task readdata;
input [7:0] expecteddata;
begin
//read status register, wait for DATA RDY bit to be set
@(negedge clk);
rden = 1;
addr = 2; //status register
@(negedge clk);
while (dout[1] == 0) begin
@(negedge clk); //wait for DataRdy bit
end
rden = 1;
addr = 1; //FIFO read port
@(posedge clk); //must latch FIFO out data on posedge
//no expected framing error
if (expecteddata != dout) begin
errors = errors + 1;
$display("%t: FAIL,expected serial RXFIFO out of %h, found: %h",$time,expecteddata,dout);
end else begin
$display("%t: PASS,got expected serial RXFIFO of %h",$time,expecteddata);
end
addr = 2;
rden = 0;
@(negedge clk);
end
endtask
//timeout process
initial begin
#(); //1 ms
if (all_vectors_done == 0) begin
$display("%t: ERROR -- TIMEOUT, not all data processed.",$time);
$display("The timeout is probably due to the DATARDY bit never going high.");
end
end
initial begin
// Initialize Inputs
#1
reset = 1;
din = 0;
wren = 0;
rden = 0;
addr = 0;
miso = 0;
head = 0;
tail = 0;
checktrigger = 0;
errors = 0;
invert_mosi = 0;
all_vectors_done = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
// Add stimulus here
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
applydata(8'h55); //alternating 1's and 0's
applydata(8'h62);
applydata(8'h38);
readdata(8'h55); //alternating 1's and 0's
readdata(8'h62);
readdata(8'h38);
rddatardy(0); //data ready bit should be set
invert_mosi = 1;
applydata(8'hA9);
applydata(8'hF3);
applydata(8'h2C);
readdata(~(8'hA9));
readdata(~(8'hF3));
readdata(~(8'h2C));
all_vectors_done = 1;
$display("%t: All vectors done.",$time);
if (errors != 0)
$display("%t: FAIL, had %d errors during simulation.",$time,errors);
else
$display("%t: PASS, no errors during simulation.",$time);
end
reg [7:0] checkdata;
always @(posedge checktrigger) begin
//check output
while(head != tail) begin
checkdata = infifo[tail];
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
getserialdata(checkdata);
end
end
endmodule
|
// binary_vga_controller.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module binary_vga_controller (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) binary_vga_controller (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXBP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 5001, M = 1e9 + 7; int n, F, vis[maxn], T = 1, mid, a[maxn], b[maxn], w[maxn][maxn], ans = 1; vector<int> g[maxn]; bool C[maxn]; bool dfs(int v) { vis[v] = T; for (int i = 0; i < g[v].size(); i++) if (vis[g[v][i]] != T) { C[g[v][i]] = !C[v]; if (!dfs(g[v][i])) return false; } else if (C[g[v][i]] == C[v]) return false; return true; } inline bool check(int x) { for (int i = 1; i <= n; i++) g[i].resize(0); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (w[i][j] > x) g[i].push_back(j), g[j].push_back(i); T++; for (int i = 1; i <= n; i++) if (vis[i] != T) if (!dfs(i)) return false; return true; } inline void bs(int f, int l) { while (f != l) { mid = (f + l) / 2; if (check(mid)) l = mid; else f = mid + 1; } check(f); F = f; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , a + i, b + i); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) w[i][j] = abs(a[i] - a[j]) + abs(b[i] - b[j]); bs(0, 7500); T++; ans = 1; for (int i = 1; i <= n; i++) if (vis[i] != T) dfs(i), ans = (ans << 1) % M; printf( %d n%d n , F, ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_SYMBOL_V
`define SKY130_FD_SC_LS__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int q = 1; q <= t; q++) { int n; int k; cin >> n >> k; long long a[n * k + 10]; long long ans = 0; for (int i = 1; i <= n * k; i++) cin >> a[i]; int ind = n * k - n / 2; int cnt = n / 2 + 1; int col = 0; while (ind > col) { ans += a[ind]; ind -= cnt; if (ind > 0) col += n - cnt; } cout << ans << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_HD__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long tree[3 * 100005]; bool lazy[3 * 100005]; void update(long long node, long long b, long long e, long long i, long long j, long long v) { if (i > e || j < b) { return; } if (b >= i && e <= j) { lazy[node] = true; { tree[node] = tree[node] | v; } return; } if (lazy[node]) { tree[node * 2] |= tree[node]; tree[node * 2 + 1] |= tree[node]; lazy[node * 2] = 1; lazy[node * 2 + 1] = 1; lazy[node] = 0; } update(node * 2, b, (b + e) / 2, i, j, v); update(node * 2 + 1, (b + e) / 2 + 1, e, i, j, v); tree[node] = tree[node * 2] & tree[node * 2 + 1]; } long long query(long long node, long long b, long long e, long long i, long long j) { if (i > e || j < b) { return (1LL << 33) - 1; } if (b >= i && e <= j) { return tree[node]; } if (lazy[node]) { tree[node * 2] |= tree[node]; tree[node * 2 + 1] |= tree[node]; lazy[node * 2] = 1; lazy[node * 2 + 1] = 1; lazy[node] = 0; } return query(node * 2, b, (b + e) / 2, i, j) & query(node * 2 + 1, (b + e) / 2 + 1, e, i, j); } int main() { long long n, m; cin >> n >> m; pair<long long, long long> p[m + 1]; long long a[m + 1]; memset(tree, 0, sizeof tree); memset(lazy, 0, sizeof lazy); for (long long i = 1; i <= m; i++) { long long x, y, z; cin >> x >> y >> z; update(1, 1, n, x, y, z); p[i].first = x; p[i].second = y; a[i] = z; } int f = 1; for (long long i = 1; i <= m; i++) { long long x = query(1, 1, n, p[i].first, p[i].second); if (x != a[i]) { f = 0; } } if (f == 1) { cout << YES n ; for (long long i = 1; i <= n; i++) { cout << query(1, 1, n, i, i) << ; } cout << endl; } else { cout << NO n ; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000050; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; int a[maxn], b[maxn], mi, ans1, ans2, ans3, ans, l, r; vector<int> v; char s[maxn]; void pa(int s, int e) { ans2 = 0; for (int i = s; i < e; i++) if (a[i] == mi + 1) ans2++; if (ans2 > ans) { ans = ans2; l = s, r = e; } ans3 = 0; int x = s + 1; for (int i = s + 1; i < e; i++) { if (a[i] == mi + 1) { if (ans3 + ans1 > ans) { ans = ans1 + ans3; l = x, r = i; } x = i + 1; ans3 = 0; } if (a[i] == mi + 2) ans3++; } } int main() { int n, m, i, j, k, t; scanf( %d , &n); scanf( %s , s + 1); for (i = 1; i <= n; i++) a[i] = s[i] == ( ? a[i - 1] + 1 : a[i - 1] - 1, mi = min(mi, a[i]); if (a[n] != 0) printf( 0 n1 1 n ), exit(0); for (i = n + 1; i <= 2 * n; i++) a[i] = a[i - n]; for (i = 1; i <= n; i++) if (a[i] == mi) v.push_back(i); ans = ans1 = v.size(); l = r = 1; v.push_back(v[0] + n); for (i = 0; i < v.size() - 1; i++) pa(v[i] + 1, v[i + 1]); printf( %d n%d %d n , ans, l > n ? l - n : l, r > n ? r - n : r); return 0; } |
#include <bits/stdc++.h> using namespace std; using P = pair<int, int>; int main() { int q; cin >> q; vector<P> v(q); for (int qi = 0; qi < q; qi++) { int t; cin >> t; if (t == 1) { int x; cin >> x; v[qi] = {x, 0}; } else { int x, y; cin >> x >> y; v[qi] = {-x, y}; } } reverse(v.begin(), v.end()); map<int, int> to; vector<int> ans; for (auto now : v) { if (now.first >= 0) { if (to.count(now.first)) { now.first = to[now.first]; } ans.push_back(now.first); } else { now.first *= -1; if (to.count(now.second)) { to[now.first] = to[now.second]; } else { to[now.first] = now.second; } } } reverse(ans.begin(), ans.end()); cout << ans[0]; for (int i = 1; i < (int)ans.size(); i++) { cout << << ans[i]; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T abs(T t) { return t < 0 ? -t : t; } const long long modn = 1000000007; inline long long mod(long long x) { return x % modn; } const int MAXN = 212345; int n, m, k; int s[MAXN]; int main() { scanf( %d , &n); for (int a = 0; a < n; a++) { scanf( %d , s + a); } int mx = 0; for (int i = 0; i <= n; i++) { int cnt = 0; for (int a = 0; a < n; a++) { if (a < i) cnt += (s[a] == 0); else cnt += (s[a] == 1); } mx = max(mx, cnt); } printf( %d n , mx); } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arp_cache
*/
module test_arp_cache;
// Parameters
parameter CACHE_ADDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg query_request_valid = 0;
reg [31:0] query_request_ip = 0;
reg query_response_ready = 0;
reg write_request_valid = 0;
reg [31:0] write_request_ip = 0;
reg [47:0] write_request_mac = 0;
reg clear_cache = 0;
// Outputs
wire query_request_ready;
wire query_response_valid;
wire query_response_error;
wire [47:0] query_response_mac;
wire write_request_ready;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
query_request_valid,
query_request_ip,
query_response_ready,
write_request_valid,
write_request_ip,
write_request_mac,
clear_cache
);
$to_myhdl(
query_request_ready,
query_response_valid,
query_response_error,
query_response_mac,
write_request_ready
);
// dump file
$dumpfile("test_arp_cache.lxt");
$dumpvars(0, test_arp_cache);
end
arp_cache #(
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Query cache
.query_request_valid(query_request_valid),
.query_request_ready(query_request_ready),
.query_request_ip(query_request_ip),
.query_response_valid(query_response_valid),
.query_response_ready(query_response_ready),
.query_response_error(query_response_error),
.query_response_mac(query_response_mac),
// Write cache
.write_request_valid(write_request_valid),
.write_request_ready(write_request_ready),
.write_request_ip(write_request_ip),
.write_request_mac(write_request_mac),
// Configuration
.clear_cache(clear_cache)
);
endmodule
|
#include <bits/stdc++.h> int a[500]; int temp1[500]; int temp2[500]; int sum[500]; void merge(int l, int mid, int r) { int i, j, k; for (i = l; i <= mid; i++) temp1[i - l] = a[i]; temp1[i - l] = 10000000; for (j = mid + 1; j <= r; j++) temp2[j - mid - 1] = a[j]; temp2[j - mid - 1] = 1000000; i = 0; j = 0; k = l; while (k <= r) { if (temp1[i] < temp2[j]) { a[k] = temp1[i]; i++; } else { a[k] = temp2[j]; j++; } k++; } } void sorti(int l, int r) { if (l >= r) return; int mid = (l + r) / 2; sorti(l, mid); sorti(mid + 1, r); merge(l, mid, r); } int main() { int n; scanf( %d , &n); int i, j, k; for (i = 1; i <= n; i++) scanf( %d , &a[i]); int left = 0, right = 0; for (i = 1; i <= n; i++) { sum[i] = sum[i - 1] + a[i]; } int val, val1; int ans = 360; for (i = 1; i <= n; i++) { for (j = i; j <= n; j++) { val1 = (sum[j] - sum[i - 1]); val = 360 - val1; val = val > val1 ? (val - val1) : (val1 - val); ans = ans > val ? val : ans; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; scanf( %lld , &n); scanf( %lld , &k); long long a[k + 5], mn = -1, ans1, ans2, flag = 0; for (long long i = 1; i <= k; i++) { scanf( %lld , &a[i]); if (a[i] > n) { continue; } flag = 1; long long r = n % a[i]; if (mn == -1) { mn = r; ans1 = i; ans2 = n / a[i]; continue; } if (mn > r) { mn = r; ans1 = i; ans2 = n / a[i]; } } if (flag == 0) { cout << 1 0 n ; return 0; } cout << ans1 << << ans2 << n ; } |
#include <bits/stdc++.h> using namespace std; struct P { int x; int a; }; P data[105]; bool cmp(P x, P y) { return x.x < y.x; } int main() { int n; int x, a; int po = 0, ne = 0; int res = 0; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &x, &a); data[i].x = x; data[i].a = a; if (x < 0) ++ne; else ++po; } sort(data, data + n, cmp); if (ne > po) { for (int i = n - 1; i >= n - po * 2 - 1; --i) { res += data[i].a; } } else { for (int i = 0; i < ne * 2 + 1; ++i) { res += data[i].a; } } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { ~debug() { cerr << n ; } template <class c> typename enable_if<sizeof dud<c>(0) != 1, debug&>::type operator<<(c i) { cerr << boolalpha << i; return *this; } template <class c> typename enable_if<sizeof dud<c>(0) == 1, debug&>::type operator<<(c i) { return *this << range(begin(i), end(i)); } template <class c, class b> debug& operator<<(pair<b, c> d) { return *this << ( << d.first << , << d.second << ) ; } template <class c> debug& operator<<(rge<c> d) { *this << [ ; for (auto it = d.b; it != d.e; ++it) *this << , + 2 * (it == d.b) << *it; return *this << ] ; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; cin >> TESTS; while (TESTS--) { long long int a, b, c, d; long long int n; cin >> n; cin >> a >> b >> c >> d; cout << ((max((a - b) * n, c - d) <= min(c + d, (a + b) * n)) ? Yes : No ) << n ; } return 0; } |
module wr_port_mux_8to1 (
wr_port_select,
port0_wr_en,
port0_wr_mask,
port0_wr_addr,
port0_wr_data,
port1_wr_en,
port1_wr_mask,
port1_wr_addr,
port1_wr_data,
port2_wr_en,
port2_wr_mask,
port2_wr_addr,
port2_wr_data,
port3_wr_en,
port3_wr_mask,
port3_wr_addr,
port3_wr_data,
port4_wr_en,
port4_wr_mask,
port4_wr_addr,
port4_wr_data,
port5_wr_en,
port5_wr_mask,
port5_wr_addr,
port5_wr_data,
port6_wr_en,
port6_wr_mask,
port6_wr_addr,
port6_wr_data,
port7_wr_en,
port7_wr_mask,
port7_wr_addr,
port7_wr_data,
muxed_port_wr_en,
muxed_port_wr_mask,
muxed_port_wr_addr,
muxed_port_wr_data
);
output muxed_port_wr_en;
output [63:0] muxed_port_wr_mask;
output [9:0] muxed_port_wr_addr;
output [2047:0] muxed_port_wr_data;
input [15:0] wr_port_select;
input port0_wr_en;
input [63:0] port0_wr_mask;
input [9:0] port0_wr_addr;
input [2047:0] port0_wr_data;
input port1_wr_en;
input [63:0] port1_wr_mask;
input [9:0] port1_wr_addr;
input [2047:0] port1_wr_data;
input port2_wr_en;
input [63:0] port2_wr_mask;
input [9:0] port2_wr_addr;
input [2047:0] port2_wr_data;
input port3_wr_en;
input [63:0] port3_wr_mask;
input [9:0] port3_wr_addr;
input [2047:0] port3_wr_data;
input port4_wr_en;
input [63:0] port4_wr_mask;
input [9:0] port4_wr_addr;
input [2047:0] port4_wr_data;
input port5_wr_en;
input [63:0] port5_wr_mask;
input [9:0] port5_wr_addr;
input [2047:0] port5_wr_data;
input port6_wr_en;
input [63:0] port6_wr_mask;
input [9:0] port6_wr_addr;
input [2047:0] port6_wr_data;
input port7_wr_en;
input [63:0] port7_wr_mask;
input [9:0] port7_wr_addr;
input [2047:0] port7_wr_data;
reg muxed_port_wr_en;
reg [63:0] muxed_port_wr_mask;
reg [9:0] muxed_port_wr_addr;
reg [2047:0] muxed_port_wr_data;
always @ (
wr_port_select or
port0_wr_en or
port0_wr_mask or
port0_wr_addr or
port0_wr_data or
port1_wr_en or
port1_wr_mask or
port1_wr_addr or
port1_wr_data or
port2_wr_en or
port2_wr_mask or
port2_wr_addr or
port2_wr_data or
port3_wr_en or
port3_wr_mask or
port3_wr_addr or
port3_wr_data or
port4_wr_en or
port4_wr_mask or
port4_wr_addr or
port4_wr_data or
port5_wr_en or
port5_wr_mask or
port5_wr_addr or
port5_wr_data or
port6_wr_en or
port6_wr_mask or
port6_wr_addr or
port6_wr_data or
port7_wr_en or
port7_wr_mask or
port7_wr_addr or
port7_wr_data
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_mask <= port0_wr_mask & {64{port0_wr_en}};
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_mask <= port1_wr_mask & {64{port1_wr_en}};
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_mask <= port2_wr_mask & {64{port2_wr_en}};
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_mask <= port3_wr_mask & {64{port3_wr_en}};
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_mask <= port4_wr_mask & {64{port4_wr_en}};
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_mask <= port5_wr_mask & {64{port5_wr_en}};
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_mask <= port6_wr_mask & {64{port6_wr_en}};
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_mask <= port7_wr_mask & {64{port7_wr_en}};
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
end
16'b0000:
begin
muxed_port_wr_en <= 1'b0;
muxed_port_wr_mask <= 64'b0;
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {2048{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_mask <= {64{1'bx}};
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {2048{1'bx}};
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; map<pair<int, char>, int> table; int main() { string home, away; int n, x, y, i; char card, team; cin >> home >> away; cin >> n; for (i = 0; i < n; i++) { cin >> x >> team >> y >> card; if (card == y ) table[make_pair(y, team)]++; if (card == r ) { if (table[make_pair(y, team)] < 2) table[make_pair(y, team)] = 2; else continue; } if (table[make_pair(y, team)] == 2) { if (team == a ) cout << away << ; else cout << home << ; cout << y << << x << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int n, k, par[N]; int64_t f[N], g[N]; vector<pair<int, int> > ke[N]; vector<int64_t> c[N]; void dfs(int u) { int64_t sum = 0; for (auto e : ke[u]) if (e.second != par[u]) { int v = e.second, w = e.first; par[v] = u; dfs(v); sum += f[v]; c[u].push_back(g[v] + w - f[v]); } sort(c[u].begin(), c[u].end(), greater<int64_t>()); for (int i = 0; i < k - 1 && i < (int)c[u].size() && c[u][i] > 0; ++i) sum += c[u][i]; f[u] = g[u] = sum; if (k <= (int)c[u].size() && c[u][k - 1] > 0) f[u] += c[u][k - 1]; } int main() { int T; scanf( %d , &T); while (T--) { scanf( %d%d , &n, &k); for (int i = 1; i < n; ++i) { int u, v, w; scanf( %d%d%d , &u, &v, &w); ke[u].push_back(make_pair(w, v)); ke[v].push_back(make_pair(w, u)); } dfs(1); printf( %I64d n , f[1]); for (int i = 1; i <= n; ++i) ke[i].clear(), c[i].clear(), par[i] = 0; } } |
//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80
`timescale 1 ns / 1 ps
module tb;
reg [13:0] WrAddress = 14'b0;
reg [13:0] RdAddress = 14'b0;
reg [7:0] Data = 8'b0;
reg WE = 0;
reg RdClock = 0;
reg RdClockEn = 0;
reg Reset = 0;
reg WrClock = 0;
reg WrClockEn = 0;
wire [7:0] Q;
integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0;
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
ram u1 (.WrAddress(WrAddress), .RdAddress(RdAddress), .Data(Data), .WE(WE),
.RdClock(RdClock), .RdClockEn(RdClockEn), .Reset(Reset), .WrClock(WrClock),
.WrClockEn(WrClockEn), .Q(Q)
);
initial
begin
WrAddress <= 0;
#100;
@(Reset == 1'b0);
for (i1 = 0; i1 < 32774; i1 = i1 + 1) begin
@(posedge WrClock);
#1 WrAddress <= WrAddress + 1'b1;
end
end
initial
begin
RdAddress <= 0;
#100;
@(Reset == 1'b0);
for (i2 = 0; i2 < 32774; i2 = i2 + 1) begin
@(posedge RdClock);
#1 RdAddress <= RdAddress + 1'b1;
end
end
initial
begin
Data <= 0;
#100;
@(Reset == 1'b0);
for (i3 = 0; i3 < 16387; i3 = i3 + 1) begin
@(posedge WrClock);
#1 Data <= Data + 1'b1;
end
end
initial
begin
WE <= 1'b0;
@(Reset == 1'b0);
for (i4 = 0; i4 < 16387; i4 = i4 + 1) begin
@(posedge WrClock);
#1 WE <= 1'b1;
end
WE <= 1'b0;
end
always
#5.00 RdClock <= ~ RdClock;
initial
begin
RdClockEn <= 1'b0;
#100;
@(Reset == 1'b0);
RdClockEn <= 1'b1;
end
initial
begin
Reset <= 1'b1;
#100;
Reset <= 1'b0;
end
always
#5.00 WrClock <= ~ WrClock;
initial
begin
WrClockEn <= 1'b0;
#100;
@(Reset == 1'b0);
WrClockEn <= 1'b1;
end
endmodule |
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: 6850TX.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ()
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
//
////////////////////////////////////////////////////////////////////////////////
module UART_TX(
BAUD_CLK,
RESET_N,
TX_DATA,
TX_START,
TX_DONE,
TX_STOP,
TX_WORD,
TX_PAR_DIS,
TX_PARITY,
TX_BUFFER
);
input BAUD_CLK;
input RESET_N;
output TX_DATA;
reg TX_DATA;
input TX_START;
output TX_DONE;
reg TX_DONE;
input TX_STOP;
input TX_WORD;
input TX_PAR_DIS;
input TX_PARITY;
input [7:0] TX_BUFFER;
reg [6:0] STATE;
reg [2:0] BIT;
wire PARITY;
reg TX_START0;
reg TX_START1;
assign PARITY = ((TX_BUFFER[0] ^ TX_BUFFER[1])
^ (TX_BUFFER[2] ^ TX_BUFFER[3]))
^ ((TX_BUFFER[4] ^ TX_BUFFER[5])
^ (TX_BUFFER[6] ^ (TX_BUFFER[7] & TX_WORD))) // clear bit #8 if only 7 bits
^ TX_PARITY;
always @ (negedge BAUD_CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
STATE <= 7'b0000000;
TX_DATA <= 1'b1;
TX_DONE <= 1'b1;
BIT <= 3'b000;
TX_START0 <= 1'b0;
TX_START1 <= 1'b0;
end
else
begin
TX_START0 <= TX_START;
TX_START1 <= TX_START0;
case (STATE)
7'b0000000:
begin
BIT <= 3'b000;
TX_DATA <= 1'b1;
if(TX_START1)
begin
TX_DONE <= 1'b0;
STATE <= 7'b0000001;
end
end
7'b0000001:
begin
TX_DATA <= 1'b0;
STATE <= 7'b0000010;
end
7'b0010001:
begin
TX_DATA <= TX_BUFFER[BIT];
STATE <= 7'b0010010;
end
7'b0100000:
begin
BIT <= BIT + 1'b1;
if(BIT != {2'b11, TX_WORD})
STATE <= 7'b0010001;
else
if(!TX_PAR_DIS)
STATE <= 7'b0100001; // do parity
else
STATE <= 7'b0110001; // do stop
end
// Start parity bit
7'b0100001:
begin
TX_DATA <= PARITY;
STATE <= 7'b0100010;
end
// start stop
7'b0110001:
begin
TX_DONE <= 1'b1;
TX_DATA <= 1'b1;
STATE <= 7'b0110010;
end
// end of first stop bit
7'b0111111:
begin
if(!TX_STOP)
STATE <= 7'b1001111;
else
STATE <= 7'b1000000;
end
7'b1001111:
begin
STATE <= 7'b0000000;
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void print(vector<long long int> &v) { long long int n = v.size(); for (long long int i = 0; i < n; i++) cout << v[i] << ; cout << n ; ; return; } vector<long long int> parent(200001); vector<long long int> size1(200001); long long int find(long long int a) { if (a == parent[a]) return a; return parent[a] = find(parent[a]); } void union1(long long int a, long long int b) { long long int a1 = find(a); long long int b1 = find(b); if (a1 == b1) return; long long int t1 = size1[a1]; long long int t2 = size1[b1]; if (t1 < t2) { parent[a1] = b1; size1[b1] += size1[a1]; } else { parent[b1] = a1; size1[a1] += size1[b1]; } return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int n; cin >> n; for (long long int i = 0; i < n + 1; i++) { parent[i] = i; size1[i] = 1; } vector<string> v(n); vector<vector<bool> > ar(n, vector<bool>(26, 0)); for (long long int i = 0; i < n; i++) { cin >> v[i]; long long int p = v[i].length(); for (long long int j = 0; j < p; j++) { ar[i][v[i][j] - a ] = 1; } } for (long long int j = 0; j < 26; j++) { long long int prev = -1; for (long long int i = 0; i < n; i++) { if (ar[i][j] == 1) { if (prev == -1) prev = i; else { union1(prev, i); } } } } set<long long int> st; for (long long int i = 0; i < n; i++) { st.insert(find(i)); } cout << st.size() << n ; ; return 0; } |
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