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//`timescale 1 ns / 100 ps
`timescale 10ns / 1ns
`include "const.v"
`define SCALE 6
module sum_tb;
wire sclk_n;
wire cs_n;
reg start;
reg from_device;
wire test0, test1;
wire [11:0] data;
wire [`W-1:0] clk_scaler;
wire irq;
// stimuls
reg clk;
// fixme: пока просто по модулю 8
assign clk_scaler = 6-1;//`DIV_MAX - 1;
initial begin
clk = 0;
// rst = 0;
from_device = 0;
// #10 rst = 1;
// #10 rst = 0;
// fixme: понять и возможно переделать
// http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
// !!!
start <= 1; // time 0 nonblocking assignment
@(posedge clk); // Wait to get past time 0
@(negedge clk) start = 0; // rst_n low for one clock cycle
end
always
#10 clk = ~clk;
// $stop or $finish
always @( posedge clk ) begin
from_device <= $random; // можно просто генерить биты
// а там как попадет
end
base_fsm s0(
.clk( clk ), .start( start ), .clk_scaler( clk_scaler ),
.sclk_n(sclk_n), .cs_n( cs_n ),
.from_device(from_device),
.test0( test0 ),
.test1( test1 ),
.data( data ), .irq( irq ) );
endmodule |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; vector<pair<int, int> > opt[18 * MAX]; map<pair<int, int>, vector<pair<int, int> > > mp; int par[MAX]; int col[MAX]; int sz[MAX]; int an[MAX]; vector<int> roll_back_num; vector<pair<pair<int, pair<int, int> >, pair<int, pair<int, int> > > > roll_back; void insert(int t, int l, int r, int a, int b, int c, int d) { if (l > b || r < a) { return; } if (l >= a && r <= b) { opt[t].push_back(make_pair(c, d)); return; } int mid = (l + r) / 2; insert(t * 2, l, mid, a, b, c, d); insert(t * 2 + 1, mid + 1, r, a, b, c, d); } int not_cor; int find(int x) { while (x != par[x]) { x = par[x]; } return x; } int color(int x) { int ans = 0; while (x != par[x]) { ans ^= col[x]; x = par[x]; } return (ans ^ col[x]); } void unite(int a, int b) { int ra = find(a), rb = find(b); int ca = color(a), cb = color(b); if (ra == rb) { if (ca == cb) { not_cor++; roll_back_num.push_back(-1); } } else { if (sz[ra] > sz[rb]) { swap(a, b); swap(ra, rb); swap(ca, cb); } roll_back.push_back({{ra, {ra, sz[ra]}}, {rb, {col[ra], sz[rb]}}}); par[ra] = rb; sz[rb] += sz[ra]; if (ca == cb) { col[ra] ^= 1; } } } void solve(int t, int l, int r) { int curn = roll_back_num.size(); int cur = roll_back.size(); for (auto it : opt[t]) { unite(it.first, it.second); } if (l == r) { if (not_cor) { an[l] = 0; } else { an[l] = 1; } } else { int mid = (l + r) / 2; solve(2 * t, l, mid); solve(2 * t + 1, mid + 1, r); } while (roll_back_num.size() > curn) { not_cor += roll_back_num.back(); roll_back_num.pop_back(); } while (roll_back.size() > cur) { pair<pair<int, pair<int, int> >, pair<int, pair<int, int> > > tmp = roll_back.back(); par[tmp.first.first] = tmp.first.second.first; sz[tmp.first.first] = tmp.first.second.second; col[tmp.first.first] = tmp.second.second.first; sz[tmp.second.first] = tmp.second.second.second; roll_back.pop_back(); } } int main() { int n, q; scanf( %d %d , &n, &q); for (int i = 1; i <= q; i++) { int a, b; scanf( %d %d , &a, &b); if (a > b) { swap(a, b); } vector<pair<int, int> >& tmp = mp[make_pair(a, b)]; if (tmp.empty() || (((tmp.back()).second) != -1)) { tmp.push_back(make_pair(i, -1)); } else { (tmp.back()).second = (i - 1); } } for (auto it : mp) { for (auto it1 : it.second) { if (it1.second == -1) { it1.second = q; } insert(1, 1, q, it1.first, it1.second, it.first.first, it.first.second); } } for (int i = 1; i <= n; i++) { sz[i] = 1; par[i] = i; } solve(1, 1, q); for (int i = 1; i <= q; i++) { if (an[i] == 0) { printf( NO n ); } else { printf( YES n ); } } return 0; } |
module spiral_8(
i_data,
o_data_9,
o_data_25,
o_data_43,
o_data_57,
o_data_70,
o_data_80,
o_data_87,
o_data_90
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [17:0] i_data;
output signed [17+7:0] o_data_9;
output signed [17+7:0] o_data_25;
output signed [17+7:0] o_data_43;
output signed [17+7:0] o_data_57;
output signed [17+7:0] o_data_70;
output signed [17+7:0] o_data_80;
output signed [17+7:0] o_data_87;
output signed [17+7:0] o_data_90;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [24:0] w1,
w4,
w5,
w8,
w9,
w16,
w25,
w36,
w35,
w40,
w45,
w3,
w43,
w48,
w57,
w96,
w87,
w70,
w80,
w90;
assign w1 = i_data;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign w16 = w1 << 4;
assign w25 = w9 + w16;
assign w36 = w9 << 2;
assign w35 = w36 - w1;
assign w40 = w5 << 3;
assign w45 = w5 + w40;
assign w3 = w4 - w1;
assign w43 = w3 + w40;
assign w48 = w3 << 4;
assign w57 = w9 + w48;
assign w96 = w3 << 5;
assign w87 = w96 - w9;
assign w70 = w35 << 1;
assign w80 = w5 << 4;
assign w90 = w45 << 1;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign o_data_9=w9;
assign o_data_25=w25;
assign o_data_43=w43;
assign o_data_57=w57;
assign o_data_70=w70;
assign o_data_80=w80;
assign o_data_87=w87;
assign o_data_90=w90;
endmodule |
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output phy_rst_n_0,
inout mdio_0_io,
output mdio_0_mdc,
inout mdio_1_io,
output mdio_1_mdc,
inout mdio_2_io,
output mdio_2_mdc,
inout mdio_3_io,
output mdio_3_mdc,
input [3:0]rgmii_0_rd,
input rgmii_0_rx_ctl,
input rgmii_0_rxc,
output [3:0]rgmii_0_td,
output rgmii_0_tx_ctl,
output rgmii_0_txc,
input [3:0]rgmii_1_rd,
input rgmii_1_rx_ctl,
input rgmii_1_rxc,
output [3:0]rgmii_1_td,
output rgmii_1_tx_ctl,
output rgmii_1_txc,
input [3:0]rgmii_2_rd,
input rgmii_2_rx_ctl,
input rgmii_2_rxc,
output [3:0]rgmii_2_td,
output rgmii_2_tx_ctl,
output rgmii_2_txc,
input [3:0]rgmii_3_rd,
input rgmii_3_rx_ctl,
input rgmii_3_rxc,
output [3:0]rgmii_3_td,
output rgmii_3_tx_ctl,
output rgmii_3_txc,
input btn_rst_n
);
/*
reg[23:0] cnt_user;
reg[23:0] cnt_gtref;
reg[23:0] cnt_200m;
wire clk_200,ref_clk;
wire userclk2_out,gtref_clk_out;
wire btn_rst;
assign btn_rst = !btn_rst_n;
always @(posedge userclk2_out) begin
cnt_user <= cnt_user + 1'b1;
end
always @(posedge gtref_clk_out) begin
cnt_gtref <= cnt_gtref + 1'b1;
end
always @(posedge ref_clk) begin
cnt_200m <= cnt_200m + 1'b1;
end
assign pl_led[0] = cnt_user[23];
assign pl_led[1] = cnt_gtref[23];
assign pl_pmod[0] = cnt_200m[23];
assign pl_pmod[1] = 1'b1;
IBUFDS ibufds_clk200(
.I (clk200m_p),
.IB (clk200m_n),
.O (clk_200)
);
BUFG bufg_clk200(
.I (clk_200),
.O (ref_clk)
);
*/
onetsw_1_wrapper i_onetsw_1_wrapper(
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.mdio_0_io (mdio_0_io ),
.mdio_0_mdc (mdio_0_mdc ),
.mdio_1_io (mdio_1_io ),
.mdio_1_mdc (mdio_1_mdc ),
.mdio_2_io (mdio_2_io ),
.mdio_2_mdc (mdio_2_mdc ),
.mdio_3_io (mdio_3_io ),
.mdio_3_mdc (mdio_3_mdc ),
.phy_rst_n_0 (phy_rst_n_0),
.phy_rst_n_1 (),
.phy_rst_n_2 (),
.phy_rst_n_3 (),
.rgmii_0_rd (rgmii_0_rd ),
.rgmii_0_rx_ctl (rgmii_0_rx_ctl ),
.rgmii_0_rxc (rgmii_0_rxc ),
.rgmii_0_td (rgmii_0_td ),
.rgmii_0_tx_ctl (rgmii_0_tx_ctl ),
.rgmii_0_txc (rgmii_0_txc ),
.rgmii_1_rd (rgmii_1_rd ),
.rgmii_1_rx_ctl (rgmii_1_rx_ctl ),
.rgmii_1_rxc (rgmii_1_rxc ),
.rgmii_1_td (rgmii_1_td ),
.rgmii_1_tx_ctl (rgmii_1_tx_ctl ),
.rgmii_1_txc (rgmii_1_txc ),
.rgmii_2_rd (rgmii_2_rd ),
.rgmii_2_rx_ctl (rgmii_2_rx_ctl ),
.rgmii_2_rxc (rgmii_2_rxc ),
.rgmii_2_td (rgmii_2_td ),
.rgmii_2_tx_ctl (rgmii_2_tx_ctl ),
.rgmii_2_txc (rgmii_2_txc ),
.rgmii_3_rd (rgmii_3_rd ),
.rgmii_3_rx_ctl (rgmii_3_rx_ctl ),
.rgmii_3_rxc (rgmii_3_rxc ),
.rgmii_3_td (rgmii_3_td ),
.rgmii_3_tx_ctl (rgmii_3_tx_ctl ),
.rgmii_3_txc (rgmii_3_txc ),
.ext_rst (1'b0)
);
endmodule |
`include "../defined.vh"
module ALU
(
a_in ,
b_in ,
alu_function ,
c_alu
);
input [31:0]a_in;
input [31:0]b_in;
input [3:0]alu_function;
output reg [31:0]c_alu;
wire signed [31:0]a_in_s, b_in_s;
assign a_in_s=a_in;
assign b_in_s=b_in;
wire [31:0] b_b_not;
wire [31:0] adder_out;
wire cout;
reg cin;
assign b_b_not = (cin)?~b_in:b_in;
ADD
#(
.N(32)
)
ADD_
(
.A(a_in),
.B(b_b_not),
.CI(cin),
.S(adder_out),
.CO(cout)
);
always@(*)
begin
c_alu<=32'b0;
cin <= 0;
case(alu_function)
`ALU_NOTHING:
c_alu<=32'b0;
`ALU_ADD:
begin
cin <= 0;
c_alu<=adder_out;//a_in+b_in;
end
`ALU_SUBTRACT:
begin
cin <= 1;
c_alu<=adder_out;//a_in-b_in;
end
`ALU_LESS_THAN://TODO:check
begin
cin <= 1;
c_alu<={31'b0, ~cout};//(a_in<b_in)?1:32'b0;
end
`ALU_LESS_THAN_SIGNED://TODO:check
begin
cin <= 1;
c_alu<={31'b0, (a_in[31]&~b_in[31] | adder_out[31]&(~a_in[31]^b_in[31]))};//(a_in_s<b_in_s)?1:32'b0;
end
`ALU_OR:
c_alu<=a_in|b_in;
`ALU_AND:
c_alu<=a_in&b_in;
`ALU_XOR:
c_alu<=a_in^b_in;
`ALU_NOR:
c_alu<=~(a_in|b_in);
default:
c_alu<=32'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, m, p, t = 0; cin >> n >> m >> k; vector<long long int> v; for (long long int i = 0; i < m; i++) { cin >> p; v.push_back(p); } sort(v.begin(), v.end()); long long int c = 0, s = 0; while (s != m) { long long int y; if ((v[s] - t) % k == 0) y = (v[s] - t) / k; else y = (v[s] - t) / k + 1; long long int q = t; for (long long int i = s; i < m; i++) { long long int x; if ((v[i] - q) % k == 0) x = (v[i] - q) / k; else x = (v[i] - q) / k + 1; if (y == x) { s++; t++; } else { break; } } c++; } cout << c << endl; } |
#include bits/stdc++.h using namespace std; #define ll long long int #define pb push_back #define ppb pop_back #define pf push_front #define ppf pop_front #define all(x) (x).begin(),(x).end() #define uniq(v) (v).erase(unique(all(v)),(v).end()) #define sz(x) (int)((x).size()) #define fr first #define sc second #define pii pair<int,int> #define rep(i,a,b) for(int i=a;i<b;i++) #define mem1(a) memset(a,-1,sizeof(a)) #define mem0(a) memset(a,0,sizeof(a)) #define ppc __builtin_popcount #define ppcll __builtin_popcountll template<typename T,typename T1>T max_self(T &a,T1 b){if(b>a)a=b;return a;} template<typename T,typename T1>T min_self(T &a,T1 b){if(b<a)a=b;return a;} const long long int INF=1e9; const int N=0; const int modn=1e9+7; void solve(){ int n,m;cin>>n>>m; string s,t; cin>>s>>t; int left[m],right[m]; int i=0,j=0; while(j<m) {while(s[i]!=t[j]) i++; left[j]=i; j++,i++; } i=n-1; j=m-1; while(~j) { while(s[i]!=t[j]) i--; right[j]=i; i--,j--; } int ans=0; //rep(i,0,m) //cout<<left[i]<< ; rep(i,1,m) max_self(ans,right[i]-left[i-1]); cout<<ans<< n ; } int main(){ ios_base::sync_with_stdio(false); cin.tie(0);cout.tie(0); int t=1; //cin>>t; while(t--) solve(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire bit_in = crc[0];
wire [30:0] vec_in = crc[31:1];
wire [123:0] wide_in = {crc[59:0],~crc[63:0]};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire exp_bit_out; // From reference of t_embed1_child.v
wire exp_did_init_out; // From reference of t_embed1_child.v
wire [30:0] exp_vec_out; // From reference of t_embed1_child.v
wire [123:0] exp_wide_out; // From reference of t_embed1_child.v
wire got_bit_out; // From test of t_embed1_wrap.v
wire got_did_init_out; // From test of t_embed1_wrap.v
wire [30:0] got_vec_out; // From test of t_embed1_wrap.v
wire [123:0] got_wide_out; // From test of t_embed1_wrap.v
// End of automatics
// A non-embedded master
/* t_embed1_child AUTO_TEMPLATE(
.\(.*_out\) (exp_\1[]),
.is_ref (1'b1));
*/
t_embed1_child reference
(/*AUTOINST*/
// Outputs
.bit_out (exp_bit_out), // Templated
.vec_out (exp_vec_out[30:0]), // Templated
.wide_out (exp_wide_out[123:0]), // Templated
.did_init_out (exp_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b1)); // Templated
// The embeded comparison
/* t_embed1_wrap AUTO_TEMPLATE(
.\(.*_out\) (got_\1[]),
.is_ref (1'b0));
*/
t_embed1_wrap test
(/*AUTOINST*/
// Outputs
.bit_out (got_bit_out), // Templated
.vec_out (got_vec_out[30:0]), // Templated
.wide_out (got_wide_out[123:0]), // Templated
.did_init_out (got_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b0)); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0,
got_wide_out !== exp_wide_out,
got_vec_out !== exp_vec_out,
got_bit_out !== exp_bit_out,
got_did_init_out !== exp_did_init_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result,
got_vec_out, exp_vec_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else if (cyc<90) begin
if (result != 64'h0) begin
$display("Bit mismatch, result=%x\n", result);
$stop;
end
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
//Child prints this: $write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1 ns / 1 ps
module axis_histogram #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 14
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata,
output wire bram_porta_we
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [1:0] int_case_reg, int_case_next;
reg int_tready_reg, int_tready_next;
reg int_wren_reg, int_wren_next;
reg int_zero_reg, int_zero_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_case_reg <= 2'd0;
int_tready_reg <= 1'b0;
int_wren_reg <= 1'b1;
int_zero_reg <= 1'b1;
end
else
begin
int_addr_reg <= int_addr_next;
int_case_reg <= int_case_next;
int_tready_reg <= int_tready_next;
int_wren_reg <= int_wren_next;
int_zero_reg <= int_zero_next;
end
end
always @*
begin
int_addr_next = int_addr_reg;
int_case_next = int_case_reg;
int_tready_next = int_tready_reg;
int_wren_next = int_wren_reg;
int_zero_next = int_zero_reg;
case(int_case_reg)
0:
begin
// write zeros
int_addr_next = int_addr_reg + 1'b1;
if(&int_addr_reg)
begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_zero_next = 1'b0;
int_case_next = 2'd1;
end
end
1:
begin
if(s_axis_tvalid)
begin
int_addr_next = s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
int_tready_next = 1'b0;
int_case_next = 2'd2;
end
end
2:
begin
int_wren_next = 1'b1;
int_case_next = 2'd3;
end
3:
begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_case_next = 2'd1;
end
endcase
end
assign s_axis_tready = int_tready_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = int_wren_reg ? int_addr_reg : s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
assign bram_porta_wrdata = int_zero_reg ? {(BRAM_DATA_WIDTH){1'b0}} : (bram_porta_rddata + 1'b1);
assign bram_porta_we = int_zero_reg ? 1'b1 : (int_wren_reg & ~&bram_porta_rddata);
endmodule
|
/* wb_arbiter_tb. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
`default_nettype none
module wb_arbiter_tb
#(parameter NUM_MASTERS = 5,
parameter AUTORUN = 1);
localparam aw = 32;
localparam dw = 32;
localparam MEMORY_SIZE_BITS = 8;
localparam MEMORY_SIZE_WORDS = 2**MEMORY_SIZE_BITS;
parameter TRANSACTIONS_PARAM = 1000;
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [2:0] wbs_m2s_cti;
wire [1:0] wbs_m2s_bte;
wire [dw-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire wbs_s2m_err;
wire wbs_s2m_rty;
wire [NUM_MASTERS*aw-1:0] wbm_m2s_adr;
wire [NUM_MASTERS*dw-1:0] wbm_m2s_dat;
wire [NUM_MASTERS*4-1:0] wbm_m2s_sel;
wire [NUM_MASTERS-1:0] wbm_m2s_we ;
wire [NUM_MASTERS-1:0] wbm_m2s_cyc;
wire [NUM_MASTERS-1:0] wbm_m2s_stb;
wire [NUM_MASTERS*3-1:0] wbm_m2s_cti;
wire [NUM_MASTERS*2-1:0] wbm_m2s_bte;
wire [NUM_MASTERS*dw-1:0] wbm_s2m_dat;
wire [NUM_MASTERS-1:0] wbm_s2m_ack;
wire [NUM_MASTERS-1:0] wbm_s2m_err;
wire [NUM_MASTERS-1:0] wbm_s2m_rty;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wire [NUM_MASTERS-1:0] done_int;
wire done;
generate
if (AUTORUN) begin
vlog_tb_utils vtu();
vlog_tap_generator #("wb_arbiter.tap", 1) vtg();
initial begin
#100 run;
vtg.ok("wb_arbiter: All tests passed!");
$finish;
end
end
endgenerate
integer TRANSACTIONS;
task run;
integer idx;
begin
wb_rst = 1'b0;
@(posedge done);
$display("Average wait times");
for(idx=0;idx<NUM_MASTERS;idx=idx+1)
$display("Master %0d : %f",idx, ack_delay[idx]/num_transactions[idx]);
end
endtask
always #5 wb_clk <= ~wb_clk;
genvar i;
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : masters
initial begin
@(negedge wb_rst);
if($value$plusargs("transactions=%d", TRANSACTIONS))
transactor.set_transactions(TRANSACTIONS);
transactor.display_settings;
transactor.run();
transactor.display_stats;
end
wb_bfm_transactor
#(.MEM_HIGH((i+1)*MEMORY_SIZE_WORDS-1),
.AUTORUN (0),
.MEM_LOW (i*MEMORY_SIZE_WORDS))
transactor
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_o (wbm_m2s_adr[i*aw+:aw]),
.wb_dat_o (wbm_m2s_dat[i*dw+:dw]),
.wb_sel_o (wbm_m2s_sel[i*4+:4]),
.wb_we_o (wbm_m2s_we[i] ),
.wb_cyc_o (wbm_m2s_cyc[i]),
.wb_stb_o (wbm_m2s_stb[i]),
.wb_cti_o (wbm_m2s_cti[i*3+:3]),
.wb_bte_o (wbm_m2s_bte[i*2+:2]),
.wb_dat_i (wbm_s2m_dat[i*dw+:dw]),
.wb_ack_i (wbm_s2m_ack[i]),
.wb_err_i (wbm_s2m_err[i]),
.wb_rty_i (wbm_s2m_rty[i]),
//Test Control
.done(done_int[i]));
end // block: slaves
endgenerate
assign done = &done_int;
wb_arbiter
#(.num_masters(NUM_MASTERS))
wb_arbiter0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_cti_i (wbm_m2s_cti),
.wbm_bte_i (wbm_m2s_bte),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
.wbm_err_o (wbm_s2m_err),
.wbm_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
assign slave_writes = wb_mem_model0.writes;
assign slave_reads = wb_mem_model0.reads;
time start_time[NUM_MASTERS-1:0];
time ack_delay[NUM_MASTERS-1:0];
integer num_transactions[NUM_MASTERS-1:0];
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : wait_time
initial begin
ack_delay[i] = 0;
num_transactions[i] = 0;
while(!done) begin
@(posedge wbm_m2s_cyc[i]);
start_time[i] = $time;
@(posedge wbm_s2m_ack[i]);
ack_delay[i] = ack_delay[i] + $time-start_time[i];
num_transactions[i] = num_transactions[i]+1;
end
end
end
endgenerate
wb_bfm_memory #(.DEBUG (0),
.mem_size_bytes(MEMORY_SIZE_WORDS*(dw/8)*NUM_MASTERS))
wb_mem_model0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Funnel Shifter and Color Selector
// File : ded_funcol.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module instantiates the funnel shifter and color selector
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_funcol
#(parameter BYTES = 4)
(
input mclock, // Clock for delaying RAD
input [1:0] stpl_4, // stipple mode bit 01 = planar, 10 = packed
input [1:0] apat_4, // should be moved to here from ded_top_misc
input ps8_4,
ps16_4,
ps32_4,
input lt_actv_4,
input [31:0] fore_4, // foreground register output
input [31:0] back_4, // foreground register output
input solid_4,
input [(BYTES<<3)-1:0] pc_col, // color select from pix cache
`ifdef BYTE16 input [6:0] rad,
`elsif BYTE8 input [5:0] rad,
`else input [4:0] rad, `endif
input [(BYTES<<3)-1:0] bsd0,bsd1, // cache data output
output [(BYTES<<3)-1:0] col_dat, // frame buffer data output
output [BYTES-1:0] trns_msk, // transparentcy mask
output [BYTES-1:0] cx_sel // color expand selector (for test)
);
wire [(BYTES<<3)-1:0] fs_dat; // funnel shift data to color selector
/****************************************************************/
/* DATAPATH FUNNEL SHIFTER */
/****************************************************************/
ded_funshf #
(
.BYTES (BYTES)
)
U_FUNSHF
(
.mclock (mclock),
.rad (rad),
.bsd0 (bsd0),
.bsd1 (bsd1),
.apat8_4 (apat_4[0]),
.apat32_4 (apat_4[1]),
.bsout (fs_dat),
.cx_sel (cx_sel)
);
/****************************************************************/
/* DATAPATH COLOR SELECTOR */
/****************************************************************/
ded_colsel #
(
.BYTES (BYTES)
)
U_COLSEL
(
.mclock (mclock),
.ps8_4 (ps8_4),
.ps16_4 (ps16_4),
.ps32_4 (ps32_4),
.stpl_4 (stpl_4),
.lt_actv_4 (lt_actv_4),
.fore_4 (fore_4),
.back_4 (back_4),
.fs_dat (fs_dat),
.cx_sel (cx_sel),
.pc_col (pc_col),
.solid_4 (solid_4),
.col_dat (col_dat),
.trns_msk (trns_msk));
endmodule // DED_FUNCOL
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 50; const long long Mod = 1e9 + 7; struct node { long long to, next, w; } edge[maxn * 2]; struct Edge { long long u, v; } t[maxn]; long long k = 0, head[maxn]; void add(long long u, long long v) { edge[++k].to = v; edge[k].next = head[u]; head[u] = k; } long long T, p[maxn], m, n; long long ans = 0, sz[maxn], cnt[maxn]; void dfs(long long x, long long f, long long opt) { sz[x] = 1; for (long long i = head[x]; i; i = edge[i].next) { if (edge[i].to == f) continue; dfs(edge[i].to, x, i); sz[x] += sz[edge[i].to]; } if (opt == 0) return; cnt[opt] = sz[x] * (n - sz[x]); if (cnt[opt] == 0 && opt != 0) cnt[opt] = n - 1; } int main() { cin >> T; while (T--) { k = 0; memset(head, 0, sizeof(head)); memset(cnt, 0, sizeof(cnt)); cin >> n; for (long long i = 1; i <= n - 1; i++) { long long u, v; cin >> u >> v; add(u, v); add(v, u); } cin >> m; for (long long i = 1; i <= m; i++) cin >> p[i]; sort(p + 1, p + 1 + m); long long cnt1 = n - 1 - m; if (cnt1 <= 0) cnt1 = 0; dfs(1, 1, 0); sort(cnt + 1, cnt + 1 + k); while (m > n - 1) { p[m - 1] = (p[m - 1] * p[m]) % Mod; m--; } long long ans = 0, opt = 0; for (long long i = k / 2 + 1; i <= k; i++) { if (cnt1) { ans = (ans + cnt[i] * 1) % Mod; cnt1--; } else { ans = (ans + cnt[i] * p[++opt] % Mod) % Mod; } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1050; int s[maxn][maxn]; int main(int argc, char const *argv[]) { int n, a, b; cin >> n >> a >> b; if (a != 1 && b != 1) { printf( NO n ); return 0; } if (n == 1) { printf( YES n0 n ); return 0; } if (a == 1 && b == 1 && n <= 3) { printf( NO n ); return 0; } printf( YES n ); if (a == 1 && b == 1) { for (int i = 1; i < n; ++i) { s[i][i + 1] = s[i + 1][i] = 1; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { printf( %d , s[i][j]); } printf( n ); } } else if (a == 1) { for (int i = b; i <= n; ++i) { for (int j = b; j <= n; ++j) { s[i][j] = 1; } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { s[i][j] = 1 - s[i][j]; } s[i][i] = 0; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { printf( %d , s[i][j]); } printf( n ); } } else { for (int i = a; i <= n; ++i) { for (int j = a; j <= n; ++j) { s[i][j] = 1; } } for (int i = 1; i <= n; ++i) s[i][i] = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { printf( %d , s[i][j]); } printf( n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)1E5 + 5; int MOD = (int)1E9 + 7; namespace CHT { struct cnode { int s; int e; int ls; int rs; int res; } nodes[N * 40]; void copy(int s, int d) { nodes[d].s = nodes[s].s; nodes[d].e = nodes[s].e; nodes[d].ls = nodes[s].ls; nodes[d].rs = nodes[s].rs; nodes[d].res = nodes[s].res; } int roots[N << 1]; int allo = 0; int build(int s, int e) { if (s == e) { nodes[allo] = {s, e, -1, -1, 0}; return allo++; } int m = s + e >> 1; int temp = allo++; int l = build(s, m); int r = build(m + 1, e); nodes[temp] = {s, e, l, r, 0}; return temp; } void add(int i, int pos, int val) { roots[i] = allo++; int c1 = roots[i - 1]; int c2 = roots[i]; while (1) { copy(c1, c2); nodes[c2].res += val; if (nodes[c1].s == nodes[c1].e) break; int m = nodes[c1].s + nodes[c1].e >> 1; if (pos <= m) { nodes[c2].ls = allo++; c2 = nodes[c2].ls; c1 = nodes[c1].ls; } else { nodes[c2].rs = allo++; c2 = nodes[c2].rs; c1 = nodes[c1].rs; } } } int query(int s, int e, int r) { if (s == nodes[r].s && e == nodes[r].e) return nodes[r].res; int m = nodes[r].s + nodes[r].e >> 1; if (e <= m) { return query(s, e, nodes[r].ls); } else if (s >= m + 1) { return query(s, e, nodes[r].rs); } else { int p1 = query(s, m, nodes[r].ls); int p2 = query(m + 1, e, nodes[r].rs); return p1 + p2; } } } // namespace CHT using namespace CHT; namespace fastIO { void read(int &n) { char ch = ; int q = 0, w = 1; for (; (ch != - ) && ((ch < 0 ) || (ch > 9 )); ch = getchar()) ; if (ch == - ) w = -1, ch = getchar(); for (; ch >= 0 && ch <= 9 ; ch = getchar()) q = q * 10 + ch - 48; n = q * w; } void read(long long &n) { char ch = ; long long q = 0, w = 1; for (; (ch != - ) && ((ch < 0 ) || (ch > 9 )); ch = getchar()) ; if (ch == - ) w = -1, ch = getchar(); for (; ch >= 0 && ch <= 9 ; ch = getchar()) q = q * 10 + ch - 48; n = q * w; } void write(long long x) { if (x == 0) { putchar( 0 ); return; } if (x < 0) x = -x, putchar( - ); int d[21]; d[0] = 0; while (x) d[++d[0]] = x % 10, x /= 10; for (; d[0]; d[0]--) putchar(d[d[0]] + 0 ); } }; // namespace fastIO using namespace fastIO; vector<int> vs[N]; void solve() { int n, k, temp, q; read(n); read(k); roots[0] = build(1, n); for (int i = 1; i <= n; i++) { read(temp); vs[temp].push_back(i); if (vs[temp].size() > k) { add(2 * i - 1, vs[temp][vs[temp].size() - 1 - k], -1); } else { add(2 * i - 1, 1, 0); } add(2 * i, i, 1); } read(q); int last = 0; for (int i = 0; i < q; i++) { int a, b; read(a), read(b); a = (last + a) % n + 1; b = (last + b) % n + 1; if (a > b) swap(a, b); last = query(a, b, roots[2 * b]); write(last); printf( n ); } } int main() { solve(); return 0; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module replicates pixels in video data to enlarge the image. *
* *
******************************************************************************/
module altera_up_video_scaler_multiply_width (
// Inputs
clk,
reset,
stream_in_channel,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 15; // Image's Channel Width
parameter DW = 15; // Image's data width
parameter MCW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] stream_in_channel;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output reg [CW: 0] stream_out_channel;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [CW: 0] channel;
reg [DW: 0] data;
reg startofpacket;
reg endofpacket;
reg valid;
reg [MCW:0] enlarge_width_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_channel <= 'h0;
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_channel <= {channel, enlarge_width_counter};
stream_out_data <= data;
if (|(enlarge_width_counter))
stream_out_startofpacket <= 1'b0;
else
stream_out_startofpacket <= startofpacket;
if (&(enlarge_width_counter))
stream_out_endofpacket <= endofpacket;
else
stream_out_endofpacket <= 1'b0;
stream_out_valid <= valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
channel <= 'h0;
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
channel <= stream_in_channel;
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
valid <= stream_in_valid;
end
end
always @(posedge clk)
begin
if (reset)
enlarge_width_counter <= 'h0;
else if ((stream_out_ready | ~stream_out_valid) & valid)
enlarge_width_counter <= enlarge_width_counter + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = (~valid) |
((&(enlarge_width_counter)) & (stream_out_ready | ~stream_out_valid));
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Dual ported, Harvard architecture
module ram_harvard2
#(parameter AWIDTH=15,
parameter RAM_SIZE=32768)
(input wb_clk_i,
input wb_rst_i,
// Instruction fetch port.
input [AWIDTH-1:0] if_adr,
output reg [31:0] if_data,
// Data access port.
input [AWIDTH-1:0] dwb_adr_i,
input [31:0] dwb_dat_i,
output reg [31:0] dwb_dat_o,
input dwb_we_i,
output dwb_ack_o,
input dwb_stb_i,
input [3:0] dwb_sel_i);
reg ack_d1;
reg stb_d1;
assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
always @(posedge wb_clk_i)
if(wb_rst_i)
ack_d1 <= 1'b0;
else
ack_d1 <= dwb_ack_o;
always @(posedge wb_clk_i)
if(wb_rst_i)
stb_d1 <= 0;
else
stb_d1 <= dwb_stb_i;
reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
// Port 1, Read only
always @(posedge wb_clk_i)
if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]];
// Port 2, R/W
always @(posedge wb_clk_i)
if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
endmodule // ram_harvard
|
#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; for (int i = 1; n; i++) { if (i & 1) printf( %d 2 n , i), n--; else if (n == 1) printf( %d 1 n , i), n = 0; else printf( %d 1 n%d 3 n , i, i), n -= 2; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; bool go(int x, multiset<int> &hand, deque<int> &dq) { if (hand.find(x) == hand.end()) return false; hand.erase(hand.find(x)); hand.insert(dq.front()); dq.pop_front(); dq.push_back(x); return true; } multiset<int> hand; deque<int> dq; int Try() { multiset<int> hand1 = hand; deque<int> dq1 = dq; int pos = -1; for (int i = 0; i < n; i++) { if (dq[i] == 1) pos = i; } if (pos == -1) return -1; for (int i = pos; i < n; i++) if (dq[i] != i - pos + 1) return -1; int done = n - pos; int ans = 0; while (done < n) { ++done; ++ans; if (!go(done, hand1, dq1)) return -1; } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; hand.insert(x); } for (int i = 1; i <= n; i++) { int x; cin >> x; dq.push_back(x); } int ans = Try(); if (ans != -1) { cout << ans << endl; return 0; } ans = 0; while (hand.find(1) == hand.end()) { assert(go(0, hand, dq)); ans++; } int mx = n; for (int i = 0; i < n; i++) { if (dq[i] == 0) continue; int cur = i + 1 + (n + 1 - dq[i]); mx = max(mx, cur); } cout << ans + mx << endl; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cout.tie(0); cin.tie(0); long long k; cin >> k; long long sum = 0; map<long long, long long> m; vector<long long> ssum(k, 0), g(5005 * k, -1); vector<vector<long long>> a(k); vector<pair<long long, long long>> v; for (long long i = 0; i < k; ++i) { long long n; cin >> n; a[i].resize(n); for (long long j = 0; j < n; ++j) { cin >> a[i][j]; m[a[i][j]] = v.size(); v.emplace_back(a[i][j], i); ssum[i] += a[i][j]; } sum += ssum[i]; } if (sum % k) { cout << No n ; return 0; } sum /= k; for (long long i = 0; i < k; ++i) { for (long long j = 0; j < (long long)a[i].size(); ++j) { if (m.count(sum - ssum[i] + a[i][j])) { long long id = m[sum - ssum[i] + a[i][j]], u = m[a[i][j]]; if (u != id && v[u].second == v[id].second) continue; g[u] = id; } } } long long timer = 0; vector<long long> dp(1 << k, 0), par(1 << k, 0), head(1 << k, -1); vector<long long> vis(v.size() + 5, 0); for (long long i = 0; i < k; ++i) { for (auto j : a[i]) { long long mask = 0, u = m[j]; ++timer; if (vis[u] || g[u] == -1) continue; while (~u && !vis[u]) { vis[u] = timer; u = g[u]; } if (u == -1 || vis[u] != timer) continue; long long c = 0, x = u, good = 1; while (x != u || !c) { if ((mask >> v[x].second) & 1) good = 0; mask |= (1 << v[x].second); x = g[x]; ++c; } if (good) { dp[mask] = 1; head[mask] = u; } } } dp[0] = 1; for (long long i = 0; i < (1 << k); ++i) { for (long long s = i; s; s = (s - 1) & i) { if (dp[s] && dp[i ^ s]) { dp[i] = 1; par[i] = s; } } } if (!dp[(1 << k) - 1]) { cout << No n ; return 0; } vector<pair<long long, long long>> ans(k); function<void(long long)> getans = [&](long long mask) { if (~head[mask]) { long long u = head[mask], x = g[u]; ans[v[x].second].first = v[x].first; ans[v[x].second].second = v[u].second + 1; while (u != x) { ans[v[g[x]].second].first = v[g[x]].first; ans[v[g[x]].second].second = v[x].second + 1; x = g[x]; } } else { getans(par[mask]); getans(mask ^ par[mask]); } }; getans((1 << k) - 1); cout << Yes n ; for (long long i = 0; i < k; ++i) cout << ans[i].first << << ans[i].second << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; std::mt19937 rnd( (int)std::chrono::steady_clock::now().time_since_epoch().count()); long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MOD = 1000000007; void inc(int& a, int b) { if ((a += b) >= MOD) a -= MOD; } void dec(int& a, int b) { inc(a, MOD - b); } int qx, qy, xdim, ydim; int inv[6 + 1]; int calcformula(int x, int y) { int ret = max(max((x + 1) / 2, (y + 1) / 2), (x + y + 2) / 3); if (ret % 2 != (x + y) % 2) ++ret; return ret; } int calc(int x, int y) { if (x == 1 && y == 0 || x == 0 && y == 1) return 3; if (x == 1 && y == 1) return xdim > 3 || ydim > 3 ? 4 : 0; if (x == 2 && y == 2) return 4; if (x == 3 && y == 0 && xdim == 4 || x == 0 && y == 3 && ydim == 4) return 5; return calcformula(x, y); } int divup(int num, int den) { if (den < 0) num = -num, den = -den; return num >= 0 ? (num + den - 1) / den : num / den; } int divdn(int num, int den) { if (den < 0) num = -num, den = -den; return num >= 0 ? num / den : (num - den + 1) / den; } int makesamepar(int a, int b) { if ((a & 1) != (b & 1)) ++a; return a; } int cnt(int lo, int hi) { return hi - lo + 1; } int sum(int lo, int hi) { return (long long)(lo + hi) * (hi - lo + 1) / 2 % MOD; } int sumsq(int n) { return (long long)n * (n + 1) % MOD * (2 * n + 1) % MOD * inv[6] % MOD; } int sumsq(int lo, int hi) { int ret = 0; inc(ret, sumsq(hi)); if (lo != 0) dec(ret, sumsq(lo - 1)); return ret; } int calcsumstupid(int xlim, int ylim) { int ret = 0; for (int x = (0); x <= (xlim); ++x) for (int y = (0); y <= (ylim); ++y) inc(ret, calc(x, y)); return ret; } int calcsum(int xlim, int ylim) { int ret = 0; for (int dx = (0); dx < (12); ++dx) if (dx <= xlim) for (int dy = (0); dy < (6); ++dy) if (dy <= ylim) { int A = (xlim - dx) / 12, B = (ylim - dy) / 6, D = divup(divup(dx, 2) - divup(dx + dy, 3), 2) - 1, E = makesamepar(divup(dx, 2), dx + dy); int cur = 0; { int xlo = max(0, B - D), xhi = A, ylo = 0, yhi = B; if (xlo <= xhi && ylo <= yhi) { cur = (cur + (long long)cnt(xlo, xhi) * cnt(ylo, yhi) % MOD * E) % MOD; cur = (cur + (long long)cnt(ylo, yhi) * sum(xlo, xhi) % MOD * 6) % MOD; } } { int xlo = max(0, -D), xhi = min(A, B - D - 1); if (xlo <= xhi) { cur = (cur + (long long)cnt(xlo, xhi) * E % MOD * (D + 1)) % MOD; cur = (cur + (long long)sum(xlo, xhi) * E) % MOD; cur = (cur + (long long)sum(xlo, xhi) * 6 % MOD * (D + 1)) % MOD; cur = (cur + (long long)sumsq(xlo, xhi) * 6) % MOD; } } inc(ret, cur); } for (int dx = (0); dx < (12); ++dx) if (dx <= xlim) for (int dy = (0); dy < (6); ++dy) if (dy <= ylim) { int A = (xlim - dx) / 12, B = (ylim - dy) / 6, C = divup(divup(dx, 2) - divup(dx + dy, 3), 2), D = divup(dx + dy, 3) - divup(dy, 2), E = makesamepar(divup(dx + dy, 3), dx + dy); int cur = 0; { int xlo = max(0, divup(B - D, 4)), xhi = A, ylo = 0, yhi = B; if (xlo <= xhi && ylo <= yhi) { cur = (cur + (long long)cnt(xlo, xhi) * cnt(ylo, yhi) % MOD * E) % MOD; cur = (cur + (long long)cnt(ylo, yhi) * sum(xlo, xhi) % MOD * 4) % MOD; cur = (cur + (long long)cnt(xlo, xhi) * sum(ylo, yhi) % MOD * 2) % MOD; } } { int xlo = max(0, divup(-D, 4)), xhi = min(A, divup(B - D, 4) - 1); if (xlo <= xhi) { cur = (cur + (long long)cnt(xlo, xhi) * E % MOD * (D + 1)) % MOD; cur = (cur + (long long)sum(xlo, xhi) * E % MOD * 4) % MOD; cur = (cur + (long long)sumsq(xlo, xhi) * 16) % MOD; cur = (cur + (long long)sum(xlo, xhi) * (D + 1) % MOD * 4) % MOD; cur = (cur + (long long)sumsq(xlo, xhi) * 16) % MOD; cur = (cur + (long long)sum(xlo, xhi) * (2 * D + 1) % MOD * 4) % MOD; cur = (cur + (long long)cnt(xlo, xhi) * D % MOD * (D + 1)) % MOD; } } { int xlo = max(0, max(B - C + 1, divup(B - D, 4))), xhi = A, ylo = 0, yhi = B; if (xlo <= xhi && ylo <= yhi) { cur = (cur - (long long)cnt(xlo, xhi) * cnt(ylo, yhi) % MOD * E % MOD + MOD) % MOD; cur = (cur - (long long)cnt(ylo, yhi) * sum(xlo, xhi) % MOD * 4 % MOD + MOD) % MOD; cur = (cur - (long long)cnt(xlo, xhi) * sum(ylo, yhi) % MOD * 2 % MOD + MOD) % MOD; } } { int xlo = max(0, max(1 - C, divup(C - D - 1, 3))), xhi = min(A, B - C); if (xlo <= xhi) { cur = (cur - (long long)cnt(xlo, xhi) * E % MOD * C % MOD + MOD) % MOD; cur = (cur - (long long)sum(xlo, xhi) * E % MOD + MOD) % MOD; cur = (cur - (long long)sumsq(xlo, xhi) * 4 % MOD + MOD) % MOD; cur = (cur - (long long)sum(xlo, xhi) * C % MOD * 4 % MOD + MOD) % MOD; cur = (cur - (long long)sumsq(xlo, xhi) % MOD + MOD) % MOD; cur = (cur - (long long)sum(xlo, xhi) * (2 * C - 1) % MOD + MOD) % MOD; cur = (cur - (long long)cnt(xlo, xhi) * (C - 1) % MOD * C % MOD + MOD) % MOD; } } { int xlo = max(0, divup(-D, 4)), xhi = min(A, min(divup(B - D, 4) - 1, divup(C - D - 1, 3) - 1)); if (xlo <= xhi) { cur = (cur - (long long)cnt(xlo, xhi) * E % MOD * (D + 1) % MOD + MOD) % MOD; cur = (cur - (long long)sum(xlo, xhi) * E % MOD * 4 % MOD + MOD) % MOD; cur = (cur - (long long)sumsq(xlo, xhi) * 16 % MOD + MOD) % MOD; cur = (cur - (long long)sum(xlo, xhi) * (D + 1) % MOD * 4 % MOD + MOD) % MOD; cur = (cur - (long long)sumsq(xlo, xhi) * 16 % MOD + MOD) % MOD; cur = (cur - (long long)sum(xlo, xhi) * (2 * D + 1) % MOD * 4 % MOD + MOD) % MOD; cur = (cur - (long long)cnt(xlo, xhi) * D % MOD * (D + 1) % MOD + MOD) % MOD; } } inc(ret, cur); } for (int dx = (0); dx < (6); ++dx) if (dx <= xlim) for (int dy = (0); dy < (12); ++dy) if (dy <= ylim) { int A = (xlim - dx) / 6, B = (ylim - dy) / 12, C = divdn(divup(dx + dy, 3) - divup(dy, 2), 2) + 1, E = makesamepar(divup(dy, 2), dx + dy); int cur = 0; { int xlo = 0, xhi = min(A, -C), ylo = 0, yhi = B; if (xlo <= xhi && ylo <= yhi) { cur = (cur + (long long)cnt(xlo, xhi) * cnt(ylo, yhi) % MOD * E) % MOD; cur = (cur + (long long)cnt(xlo, xhi) * sum(ylo, yhi) % MOD * 6) % MOD; } } { int xlo = max(0, -C + 1), xhi = min(A, B - C); if (xlo <= xhi) { cur = (cur + (long long)cnt(xlo, xhi) * E % MOD * (B - C + 1)) % MOD; cur = (cur - (long long)sum(xlo, xhi) * E % MOD + MOD) % MOD; cur = (cur + (long long)cnt(xlo, xhi) * (C + B) % MOD * (B - C + 1) % MOD * 3) % MOD; cur = (cur - (long long)sum(xlo, xhi) * (2 * C - 1) % MOD * 3 % MOD + MOD) % MOD; cur = (cur - (long long)sumsq(xlo, xhi) * 3 % MOD + MOD) % MOD; } } inc(ret, cur); } vector<pair<int, int>> special; special.push_back(make_pair(1, 0)); special.push_back(make_pair(0, 1)); special.push_back(make_pair(1, 1)); special.push_back(make_pair(3, 0)); special.push_back(make_pair(0, 3)); special.push_back(make_pair(2, 2)); for (int i = (0); i < (((int)(special).size())); ++i) { int x, y; tie(x, y) = special[i]; if (x <= xlim && y <= ylim) { dec(ret, calcformula(x, y)); inc(ret, calc(x, y)); } } return ret; } void precalc() { inv[1] = 1; for (int i = (2); i <= (6); ++i) inv[i] = (long long)(MOD - MOD / i) * inv[MOD % i] % MOD; } int solve() { int ret = 0; inc(ret, calcsum(xdim - 1, ydim - 1)); dec(ret, calcsum(xdim - 1, qy - 1)); dec(ret, calcsum(qx - 1, ydim - 1)); inc(ret, calcsum(qx - 1, qy - 1)); return ret; } void run() { scanf( %d%d%d%d , &qx, &qy, &xdim, &ydim); --qx, --qy; printf( %d n , solve()); } void verifycalc() { for (xdim = 3; xdim <= 20; ++xdim) for (ydim = 3; ydim <= 20; ++ydim) { vector<vector<int>> d(xdim, vector<int>(ydim, INT_MAX)); queue<pair<int, int>> q; d[0][0] = 0, q.push(make_pair(0, 0)); while (!q.empty()) { int x, y; tie(x, y) = q.front(); q.pop(); for (int dx = (-2); dx <= (+2); ++dx) for (int dy = (-2); dy <= (+2); ++dy) if (dx * dx + dy * dy == 5) { int nx = x + dx, ny = y + dy; if (nx < 0 || nx >= xdim || ny < 0 || ny >= ydim) continue; if (d[nx][ny] == INT_MAX) d[nx][ny] = d[x][y] + 1, q.push(make_pair(nx, ny)); } } for (int x = (0); x < (xdim); ++x) for (int y = (0); y < (ydim); ++y) if (d[x][y] == INT_MAX) { assert(xdim == 3 && ydim == 3 && x == 1 && y == 1); d[x][y] = 0; } for (int x = (0); x < (xdim); ++x) for (int y = (0); y < (ydim); ++y) assert(d[x][y] == calc(x, y)); printf( done (%d,%d) n , xdim, ydim); } } void verifysum() { for (xdim = 3; xdim <= 100; ++xdim) { for (ydim = 3; ydim <= 100; ++ydim) for (int dx = (1); dx <= (min(xdim, 3)); ++dx) for (int dy = (1); dy <= (min(ydim, 3)); ++dy) { int have = calcsum(xdim - dx, ydim - dy); int want = calcsumstupid(xdim - dx, ydim - dy); assert(have == want); } printf( done xdim=%d n , xdim); } } int main() { precalc(); int ncase; scanf( %d , &ncase); for (int i = (1); i <= (ncase); ++i) run(); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; ll solve(ll n) { --n; ll index = n / 3; ll off = 1; for (; index - off >= 0; off <<= 2) { index -= off; } ll fi = index + off; ll se = off << 1; for (ll place = off >> 2; place >= 1; place >>= 2) { ll t = (index / place) % 4; if (t == 0) { se += 0 * place; } else if (t == 1) { se += 2 * place; } else if (t == 2) { se += 3 * place; } else if (t == 3) { se += 1 * place; } } ll th = fi ^ se; if (n % 3 == 0) return fi; else if (n % 3 == 1) return se; else return th; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { ll n; cin >> n; cout << solve(n) << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hd__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_V |
/*
* Author : Tom Stanway-Mayers
* Description : FIFO
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_fifo
#(
parameter C_FIFO_PASSTHROUGH = 0,
parameter C_FIFO_WIDTH = 1,
parameter C_FIFO_DEPTH_X = 1,
//
parameter C_FIFO_DEPTH = 2**C_FIFO_DEPTH_X
)
(
// global
input wire clk_i,
input wire reset_i,
// control and status
input wire flush_i,
output wire empty_o,
output reg full_o,
// write port
input wire wr_i,
input wire [C_FIFO_WIDTH-1:0] din_i,
// read port
input wire rd_i,
output wire [C_FIFO_WIDTH-1:0] dout_o
);
//--------------------------------------------------------------
// interface assignments
// status signals
reg empty_int;
// pointers
reg [C_FIFO_DEPTH_X:0] rd_ptr_q;
reg [C_FIFO_DEPTH_X:0] wr_ptr_q;
// memory
reg [C_FIFO_WIDTH-1:0] mem[C_FIFO_DEPTH-1:0];
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
generate if (C_FIFO_PASSTHROUGH) begin
assign empty_o = (empty_int == 1'b1 ? ~wr_i : empty_int);
assign dout_o = (empty_int == 1'b1 ? din_i : mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]]);
end else begin
assign empty_o = empty_int;
assign dout_o = mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]];
end endgenerate
//--------------------------------------------------------------
// status signals
//--------------------------------------------------------------
always @ (*) begin
empty_int = 1'b0;
full_o = 1'b0;
if (rd_ptr_q[C_FIFO_DEPTH_X-1:0] == wr_ptr_q[C_FIFO_DEPTH_X-1:0]) begin
if (rd_ptr_q[C_FIFO_DEPTH_X] == wr_ptr_q[C_FIFO_DEPTH_X]) begin
empty_int = 1'b1;
end else begin
full_o = 1'b1;
end
end
end
//--------------------------------------------------------------
// pointers
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
end else begin
if (flush_i) begin
rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
end else begin
if (rd_i) begin
rd_ptr_q <= rd_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
if (wr_i) begin
wr_ptr_q <= wr_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
end
end
end
//--------------------------------------------------------------
// memory
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (wr_i) begin
mem[wr_ptr_q[C_FIFO_DEPTH_X-1:0]] <= din_i;
end
end
//--------------------------------------------------------------
// asserts
//--------------------------------------------------------------
`ifdef RV_ASSERTS_ON
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
`RV_ASSERT(((full_o & wr_i) == 1'b0), "FIFO written when full!")
`RV_ASSERT(((empty_o & rd_i) == 1'b0), "FIFO read when empty!")
end
`endif
endmodule
|
module x (/*AUTOARG*/);
// Which Internal Bank
`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
command address
always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
begin : PeelIntBnkAddr
case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
2'b01: // 2-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
end
2'b10: // 4-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
end
default: // 8-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
#include <bits/stdc++.h> using namespace std; bool comp(pair<double, int> &a, pair<double, int> &b) { if (a.first != b.first) return a.first > b.first; return a.second < b.second; } void solve() { int n; double t1, t2, k; cin >> n >> t1 >> t2 >> k; vector<pair<double, int>> p(n); for (int i = 0; i < (n); i++) { double a, b; cin >> a >> b; p[i].second = i + 1; p[i].first = max(a * t1 - (a * t1 * k) / 100 + b * t2, b * t1 - (b * t1 * k) / 100 + a * t2); } sort(p.begin(), p.end(), comp); for (auto x : p) cout << x.second << << setprecision(2) << fixed << x.first << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; int people = n - x; int wizards = x; people *= 100; wizards *= 100; int needed = max(0, n * y - wizards); cout << (needed + 99) / 100 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<pair<int, int>> v; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; v.push_back(make_pair(a, b)); } int x1 = v[0].first; int y1 = v[0].second; vector<int> p1, p2; for (int i = 1; i < m; i++) { int a = v[i].first; int b = v[i].second; if (x1 != a && x1 != b) { p1.push_back(i); } if (y1 != a && y1 != b) { p2.push_back(i); } } if (p1.size() == 0 || p2.size() == 0) { cout << YES << endl; return 0; } x1 = v[p1[0]].first; y1 = v[p1[0]].second; int c1 = 0, c2 = 0, c3 = 0, c4 = 0; for (int i = 1; i < p1.size(); i++) { int a = v[p1[i]].first; int b = v[p1[i]].second; if (x1 != a && x1 != b) { c1++; } if (y1 != a && y1 != b) { c2++; } } x1 = v[p2[0]].first; y1 = v[p2[0]].second; for (int i = 1; i < p2.size(); i++) { int a = v[p2[i]].first; int b = v[p2[i]].second; if (x1 != a && x1 != b) { c3++; } if (y1 != a && y1 != b) { c4++; } } if (c1 == 0 || c2 == 0) { cout << YES << endl; } else if (c3 == 0 || c4 == 0) { cout << YES << endl; } else { cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int prime[1000000]; bool status[1000100]; int pos; void sieve() { int i, j; for (i = 0; i < 1000100; i++) { status[i] = false; } int sq = sqrt(1000100); for (i = 4; i <= 1000100; i += 2) { status[i] = true; } for (i = 3; i <= sq; i += 2) { if (status[i] == false) { for (j = 2 * i; j <= 1000100; j += i) { status[j] = true; } } } status[1] = true; pos = 1; for (int z = 1; z <= 1000100; z++) { if (status[z] == false) { prime[pos++] = z; } } } int main() { sieve(); long long n; while (cin >> n) { long long ans = 1; for (int i = 1; i < pos; i++) { if (n == 1) break; bool f = false; while (n % prime[i] == 0) { f = true; n /= prime[i]; } if (f) ans *= prime[i]; } if (n > 1) ans *= n; cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> struct rge { T b, e; }; template <class T> rge<T> range(T i, T j) { return rge<T>{i, j}; }; template <class A, class B> ostream &operator<<(ostream &os, pair<A, B> p) { return os << ( << p.first << , << p.second << ) ; } template <class T> ostream &operator<<(ostream &os, rge<T> d) { os << [ ; for (auto it = d.b; it != d.e; it++) os << (it == d.b ? : , ) << *it; return os << ] ; } const int N = 1e5 + 5; const long long inf = 1e18; long long stones[N], frogs[N]; int n, jump; bool can(long long x) { for (int i = (1); i <= ((n)); i += (+1)) { frogs[i] = 0; } frogs[0] = x; int l = 0, r = 1; while (l < n) { while (frogs[l] > 0) { while (r <= n && stones[r] - frogs[r] <= 0) { r++; } if (l + jump < r) { return false; } long long add = min(frogs[l], stones[r] - frogs[r]); frogs[r] += add; frogs[l] -= add; } l++; r = max(l + 1, r); } return true; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0), cout.precision(15); cin >> n >> jump; for (int i = (1); i <= ((n - 1)); i += (+1)) { cin >> stones[i]; } stones[n] = inf; long long lo = 0, hi = inf; while (lo + 1 < hi) { long long mid = (lo + hi) / 2; if (can(mid)) { lo = mid; } else { hi = mid; } } while (can(lo + 1)) { lo++; } cout << lo << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int tree[1000005 << 2]; int mn[1000005 << 2]; int mx[1000005 << 2]; int pos; char s[1000005]; void pushup(int rt) { tree[rt] = tree[(2 * rt)] + tree[(2 * rt + 1)]; mn[rt] = min(mn[(2 * rt)], tree[(2 * rt)] + mn[(2 * rt + 1)]); mx[rt] = max(mx[(2 * rt)], tree[(2 * rt)] + mx[(2 * rt + 1)]); } void update(int rt, int l, int r, int x, int v) { if (l == r) { tree[rt] = mn[rt] = mx[rt] = v; return; } if (x <= ((l + r) / 2)) update((2 * rt), l, ((l + r) / 2), x, v); else update((2 * rt + 1), ((l + r) / 2) + 1, r, x, v); pushup(rt); } int main() { scanf( %d , &n); pos = 1; scanf( %s , s + 1); char opt[5]; for (int i = 1; i <= n; ++i) { opt[1] = s[i]; if (opt[1] == R ) ++pos; else if (opt[1] == L ) { if (pos > 1) --pos; } else { if (opt[1] == ( ) update(1, 1, n, pos, 1); else if (opt[1] == ) ) update(1, 1, n, pos, -1); else update(1, 1, n, pos, 0); } if (tree[1] != 0 || mn[1] < 0) printf( -1 ); else printf( %d , mx[1]); } printf( n ); return 0; } |
`include "elink_constants.vh"
module etx_clocks (/*AUTOARG*/
// Outputs
tx_lclk_io, tx_lclk90, tx_lclk_div4, cclk_p, cclk_n, etx_nreset,
etx_io_nreset, chip_nreset, tx_active,
// Inputs
sys_nreset, soft_reset, sys_clk
);
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_TXCLK = 300;
parameter FREQ_CCLK = 600;
parameter TXCLK_PHASE = 90; //txclk phase shift
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
parameter PLATFORM = `CFG_PLATFORM;
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Don't touch these! (derived parameters)
parameter MMCM_VCO_MULT = 12; //TX + CCLK
localparam real SYSCLK_PERIOD = 1000.000000 / FREQ_SYSCLK;
localparam integer TXCLK_DIVIDE = MMCM_VCO_MULT * FREQ_SYSCLK / FREQ_TXCLK;
localparam integer CCLK_DIVIDE = MMCM_VCO_MULT * FREQ_SYSCLK / FREQ_CCLK;
//Input clock, reset, config interface
input sys_nreset; // por reset (hw)
input soft_reset; // rx enable signal (sw)
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
//TX Clocks
output tx_lclk_io; // tx clock for high speeed IO
output tx_lclk90; // tx output clock shifted by 90 degrees
output tx_lclk_div4; // tx slow clock for logic
//Epiphany "free running" clock
output cclk_p, cclk_n;
//Reset
output etx_nreset; // reset for tx core logic
output etx_io_nreset; // io reset (synced to high speed clock)
output chip_nreset; // reset fpr Epiphany chip
output tx_active; // enable for rx path (ensures active clock)
//############
//# WIRES
//############
//CCLK
wire cclk_reset;
wire cclk_mmcm;
wire cclk_bufio;
wire cclk_oddr;
//TX
wire tx_lclk_mmcm;
wire tx_lclk90_mmcm;
wire tx_lckl_div4_mmcm;
//MMCM & PLL
wire cclk_fb;
//wire cclk_fb_out;
wire lclk_fb_i;
wire pll_reset;
wire mmcm_locked;
reg mmcm_locked_reg;
reg mmcm_locked_sync;
wire lclk_locked;
wire tx_nreset;
wire mmcm_reset;
wire tx_lclk_div4_mmcm;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
reg [2:0] reset_state;
reg [1:0] reset_pipe_lclkb;
reg [1:0] reset_pipe_lclk_div4b;
//wrap around counter that generates a 1 cycle heartbeat
//free running counter...
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
//two clock synchronizer
always @ (posedge sys_clk)
begin
mmcm_locked_reg <= mmcm_locked;
mmcm_locked_sync <= mmcm_locked_reg;
end
`define TX_RESET_ALL 3'b000
`define TX_START_CCLK 3'b001
`define TX_STOP_CCLK 3'b010
`define TX_DEASSERT_RESET 3'b011
`define TX_HOLD_IT 3'b100 //???
`define TX_ACTIVE 3'b101
//Reset sequence state machine
always @ (posedge sys_clk or negedge sys_nreset)
if(!sys_nreset)
reset_state[2:0] <= `TX_RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`TX_RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `TX_START_CCLK;
`TX_START_CCLK :
if(mmcm_locked_sync)
reset_state[2:0] <= `TX_STOP_CCLK;
`TX_STOP_CCLK :
reset_state[2:0] <= `TX_DEASSERT_RESET;
`TX_DEASSERT_RESET :
reset_state[2:0] <= `TX_HOLD_IT;
`TX_HOLD_IT :
if(mmcm_locked_sync)
reset_state[2:0] <= `TX_ACTIVE;
`TX_ACTIVE:
if(soft_reset)
reset_state[2:0] <= `TX_RESET_ALL; //stay there until nex reset
endcase // case (reset_state[2:0])
//reset mmcm (async)
assign mmcm_reset = (reset_state[2:0]==`TX_RESET_ALL) |
(reset_state[2:0]==`TX_STOP_CCLK) |
(reset_state[2:0]==`TX_DEASSERT_RESET)
;
//reset chip (active low)
assign chip_nreset = (reset_state[2:0]==`TX_DEASSERT_RESET) |
(reset_state[2:0]==`TX_HOLD_IT) |
(reset_state[2:0]==`TX_ACTIVE);
//reset the elink
assign tx_nreset = ~(reset_state[2:0] != `TX_ACTIVE);
assign tx_active = (reset_state[2:0] == `TX_ACTIVE);
//#############################
//#RESET SYNCING
//#############################
oh_rsync rsync_io (// Outputs
.nrst_out (etx_io_nreset),
// Inputs
.clk (tx_lclk_io),
.nrst_in (tx_nreset));
oh_rsync rsync_core (// Outputs
.nrst_out (etx_nreset),
// Inputs
.clk (tx_lclk_div4),
.nrst_in (tx_nreset));
generate
if(TARGET=="XILINX")
begin
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
MMCME2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(SYSCLK_PERIOD),
.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), //cclk_c
.CLKOUT1_DIVIDE(TXCLK_DIVIDE), //tx_lclk
.CLKOUT2_DIVIDE(TXCLK_DIVIDE), //tx_lclk90
.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), //tx_lclk_div4
.CLKOUT4_DIVIDE(128), //N/A
.CLKOUT5_DIVIDE(128), //N/A
.CLKOUT6_DIVIDE(128), //N/A
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(TXCLK_PHASE),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) mmcm_cclk
(
.CLKOUT0(cclk_mmcm),
.CLKOUT0B(),
.CLKOUT1(tx_lclk_mmcm),
.CLKOUT1B(),
.CLKOUT2(tx_lclk90_mmcm),//goes directly to IO
.CLKOUT2B(),
.CLKOUT3(tx_lclk_div4_mmcm),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.PWRDWN(1'b0),
.RST(mmcm_reset), //reset
.CLKFBIN(cclk_fb),
.CLKFBOUT(cclk_fb), //feedback clock
.CLKFBOUTB(), //inverted output feedback clock
.CLKIN1(sys_clk), //input clock
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(mmcm_locked), //locked indicator
.PSCLK(1'b0),
.PSEN(1'b0),
.PSDONE(),
.PSINCDEC(1'b0),
.CLKFBSTOPPED(),
.CLKINSTOPPED()
);
//Tx clock buffers
BUFG i_lclk_bufg (.I(tx_lclk_mmcm), .O(tx_lclk_io)); //300MHz
BUFG i_lclk_div4_bufg (.I(tx_lclk_div4_mmcm),.O(tx_lclk_div4)); //75MHz
BUFG i_lclk90_bufg (.I(tx_lclk90_mmcm), .O(tx_lclk90)); //300MHz 90deg clock
// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
//###########################
// CCLK
//###########################
//CCLK bufio
BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_mmcm));
//CCLK oddr
if(PLATFORM=="ULTRASCALE")
begin : gen_ultrascale
ODDRE1 oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.D1 (1'b1),
.D2 (1'b0));
end
else
begin : gen_zynq
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
//CCLK differential buffer
OBUFDS cclk_obuf (.O (cclk_p),
.OB (cclk_n),
.I (cclk_oddr)
);
end // if (TARGET=="XILINX")
else
begin
assign cclk_p = sys_clk;
assign cclk_n = sys_clk;
assign tx_lclk_io = sys_clk;
assign tx_lclk_div4 = sys_clk;
assign tx_lclk90 = sys_clk;
end
endgenerate
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; int lowbit(int a) { return a & (-a); } int getans(char c, int l, int r, string &s) { if (l == r) { return s[l] != c; } int len = r - l + 1; int cnt = 0; for (int i = l; i < l + len / 2; i++) { if (s[i] != c) cnt++; } int ans = cnt + getans(c + 1, l + len / 2, r, s); cnt = 0; for (int i = l + len / 2; i <= r; i++) { if (s[i] != c) cnt++; } ans = min(ans, cnt + getans(c + 1, l, l + len / 2 - 1, s)); return ans; } int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; cout << getans( a , 0, n - 1, s) << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); ; int t, n; string s, p; cin >> t; while (t--) { cin >> n; cin >> s; for (int j = 0; j < (2 * n - 1); j += 2) { cout << s[j]; } cout << n ; } } |
`include "project_include.v"
module fx3_bus_in_command #(
parameter ADDRESS_WIDTH = 8 //256 coincides with the maximum DMA
//size for USB 3.0
)(
input clk,
input rst,
//Control
input i_in_path_cmd_enable,
output o_in_path_cmd_busy,
output o_in_path_cmd_finished,
//Flow Control for In Path
output o_read_flow_cntrl,
//Data
input [31:0] i_data,
//Data Valid Flag
input i_data_valid,
//Master Interface
output reg [7:0] o_command,
output reg [7:0] o_flag,
output reg [31:0] o_rw_count,
output reg [31:0] o_address,
output reg o_command_rdy_stb,
//Write side FIFO interface
output o_in_ready,
input i_in_activate,
output [23:0] o_in_packet_size,
output [31:0] o_in_data,
input i_in_strobe
);
//Local Parameters
localparam IDLE = 4'h0;
localparam READ_COMMAND = 4'h1;
localparam READ_COUNT = 4'h2;
localparam READ_ADDRESS = 4'h3;
localparam READ_CHECKSUM = 4'h4;
localparam READ_DATA = 4'h5;
localparam FINISHED = 4'h6;
//Registers/Wires
reg [3:0] state;
reg [15:0] r_id_word;
reg [31:0] r_checksum;
reg [31:0] r_cmd_checksum;
wire w_finished;
reg [31:0] r_read_data_count;
//PPFIFO
wire [1:0] w_write_ready;
reg [1:0] r_write_activate;
wire [23:0] w_write_fifo_size;
reg r_write_strobe;
reg [31:0] r_write_data;
reg [23:0] r_write_count;
//Submodules
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (ADDRESS_WIDTH )
)pp_in(
.reset (rst ),
//Write Side
.write_clock (clk ),
.write_ready (w_write_ready ),
.write_activate (r_write_activate ),
.write_fifo_size (w_write_fifo_size ),
.write_strobe (r_write_strobe ),
.write_data (r_write_data ),
//Read Side
.read_clock (clk ),
.read_strobe (i_in_strobe ),
.read_ready (o_in_ready ),
.read_activate (i_in_activate ),
.read_count (o_in_packet_size ),
.read_data (o_in_data )
);
//Asynchronous Logic
assign o_read_flow_cntrl = (r_write_activate > 0);
//assign w_finished = (((r_read_data_count == o_rw_count) ||
// (w_write_ready == 2'b11)) &&
// i_read_fx3_finished);
assign o_in_path_cmd_busy = ((state != IDLE) && (state != FINISHED));
assign o_in_path_cmd_finished = (state == FINISHED);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
r_id_word <= 0;
o_flag <= 0;
o_command <= 0;
o_rw_count <= 0;
o_address <= 0;
r_checksum <= 0;
r_cmd_checksum <= 0;
o_command_rdy_stb <= 0;
r_write_activate <= 0;
r_write_strobe <= 0;
r_write_data <= 0;
r_write_count <= 0;
r_read_data_count <= 0;
end
else begin
//Strobes
o_command_rdy_stb <= 0;
r_write_strobe <= 0;
//Grab a ppfifo if available
if ((w_write_ready > 0) && (r_write_activate == 0)) begin
r_write_count <= 0;
if (w_write_ready[0]) begin
r_write_activate[0] <= 1;
end
else begin
r_write_activate[1] <= 1;
end
end
else begin
//a FIFO is activated
if (r_write_count < w_write_fifo_size) begin
if (r_write_strobe) begin
r_write_count <= r_write_count + 1;
end
end
else begin
//Release the current FIFO it's full
r_write_activate <= 0;
end
end
case (state)
IDLE: begin
r_read_data_count <= 0;
if (i_in_path_cmd_enable) begin
state <= READ_COMMAND;
end
end
READ_COMMAND: begin
if (i_data_valid) begin
r_id_word <= i_data[31:16];
o_flag <= i_data[15:8];
o_command <= i_data[7:0];
state <= READ_COUNT;
end
end
READ_COUNT: begin
if (i_data_valid) begin
o_rw_count <= i_data;
state <= READ_ADDRESS;
end
end
READ_ADDRESS: begin
if (i_data_valid) begin
o_address <= i_data;
state <= READ_CHECKSUM;
end
end
READ_CHECKSUM: begin
if (i_data_valid) begin
r_checksum <= i_data;
o_command_rdy_stb <= 1;
if (o_command == `WRITE_COMMAND) begin
r_write_count <= `COMMAND_LENGTH;
state <= READ_DATA;
$display("Reading data from the host");
end
else begin
//Don't need to put anything in the PPFIFO
state <= FINISHED;
end
end
end
READ_DATA: begin
if (r_read_data_count < o_rw_count) begin
if (i_data_valid) begin
r_write_strobe <= 1;
r_write_data <= i_data;
r_read_data_count <= r_read_data_count + 1;
end
end
else begin
if (r_write_activate > 0) begin
r_write_activate <= 0;
end
state <= FINISHED;
end
end
FINISHED: begin
if (!i_in_path_cmd_enable) begin
state <= IDLE;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MX = 2e5 + 3; long long n, k, arr[MX], sum; multiset<long long> st; string s; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (long long i = 0; i < n; i++) cin >> arr[i]; cin >> s; st.insert(-arr[0]); for (long long i = 1; i < n; i++) { if (s[i] == s[i - 1]) st.insert(-arr[i]); else { long long a = 0; for (auto u : st) { if (a == k) break; sum -= u; a++; } st.clear(); st.insert(-arr[i]); } } long long a = 0; for (auto u : st) { if (a == k) break; sum -= u; a++; } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; string st; long ans, tans, n, ttl, qpos; int main() { ios_base::sync_with_stdio(0); cin >> n; cin >> st; for (int i = 0; i < st.size(); i++) if (st[i] == H ) ++ttl; ans = 1000000; for (int stp = 0; stp < n; stp++) { tans = 0; qpos = stp; for (int i = 1; i <= ttl; i++) { if (st[qpos] == T ) ++tans; ++qpos; if (qpos == n) qpos = 0; } ans = min(ans, tans); } cout << ans << endl; cin.get(); cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 500005, M = 60; int q, fa[N], n = 1; double dp[N][M + 5]; int main() { ios::sync_with_stdio(false); cin >> q; int opt, pos; for (int i = 0; i <= M; i++) dp[1][i] = 1; for (int _ = 1; _ <= q; _++) { cin >> opt >> pos; if (opt == 1) { fa[++n] = pos; for (int i = 0; i <= M; i++) dp[n][i] = 1; double pre = 1; int pp = n; for (int i = 0, cur = pos; cur && i <= M; i++, cur = fa[cur]) { double tmp = dp[cur][i]; dp[cur][i] /= 0.5 * (pre + 1); if (i) dp[cur][i] *= 0.5 * (1 + dp[pp][i - 1]); else dp[cur][i] *= 0.5; pp = cur; pre = tmp; } } else { double ans = 0; for (int i = 1; i <= M; i++) ans += (dp[pos][i] - dp[pos][i - 1]) * i; printf( %.10lf n , ans); } } return 0; } |
//======================================================================
//
// blockmem1rw1.v
// --------------
// Synchronous block memory with one read and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem1r1w(
input wire clk,
input wire [07 : 0] read_addr,
output wire [31 : 0] read_data,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
reg [31 : 0] mem [0 : 255];
reg [31 : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data <= mem[read_addr];
end
endmodule // blockmem1r1w
//======================================================================
// EOF blockmem1r1w.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; vector<double> p; double g; int n; int main() { cin >> n; p.resize(n + 1); for (int i = 0; i <= n; i++) cin >> p[i]; g = p[n / 2]; for (int i = 0; i <= (n - 1) / 2; i++) for (int j = n - (n - 1) / 2; j <= n; j++) g = max(g, (p[i] * (2 * j - n) + p[j] * (n - 2 * i)) / (j - i) / 2); cout << g; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); long long mn, mx, n, m; cin >> n >> m; mx = n - m; mx++; mx = (mx * (mx - 1)) / 2; mn = n / m; long long temp = n / m; if (n % m != 0) { mn = (n % m) * ((mn * (mn + 1)) / 2); m -= (n % m); mn += m * ((temp * (temp - 1)) / 2); } else mn = m * ((temp * (temp - 1)) / 2); cout << mn << << mx << endl; return 0; } |
#include <bits/stdc++.h> #define ll long long #define ld long double #define lchild 2*node #define rchild 2*node+1 #define mid (l+r)/2 #define mod 1000000007 #define mx 200007 #define pii pair<int,int> #define pci pair<int,int> #define ff first #define ss second #define piii pair<int,pii> using namespace std; int t1[mx][21], lg2[mx], t2[mx][21]; int arr[mx]; void f( int n ) { int i, j, k, m, l, r, q; lg2[1] = 0; for (i = 2; i <= n; i++) lg2[i] = lg2[i / 2] + 1; for (i = 1; i <= n; i++) t1[i][0] = arr[i], t2[i][0] = arr[i]; for (j = 1; j <= 20; j++) for (i = 1; i + (1 << (j - 1)) <= n; i++) t1[i][j] = min(t1[i][j - 1], t1[i + (1 << (j - 1))][j - 1]); for (j = 1; j <= 20; j++) for (i = 1; i + (1 << (j - 1)) <= n; i++) t2[i][j] = max(t2[i][j - 1], t2[i + (1 << (j - 1))][j - 1]); } int squery1( int l, int r ) { // int ans = min(ans, t[l][i]), l += (1 << i); int k = lg2[r - l + 1]; int ans = min(t1[l][k], t1[r - (1 << k) + 1][k]); return ans; } int squery2( int l, int r ) { // int ans = min(ans, t[l][i]), l += (1 << i); int k = lg2[r - l + 1]; int ans = max(t2[l][k], t2[r - (1 << k) + 1][k]); return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int tc; cin >> tc; while (tc--) { int n; cin >> n; for ( int i = 1; i <= n; i++ ) cin >> arr[i]; f(n); int pre[n + 5], suff[n + 5]; pre[1] = arr[1]; suff[n] = arr[n]; for ( int i = 2; i <= n; i++ ) pre[i] = max( pre[i - 1], arr[i] ); for ( int i = n - 1; i >= 1; i-- ) suff[i] = max( suff[i + 1], arr[i] ); bool f= 0; int out, lf, rt; for ( int i = 2; i < n; i++ ) { int x = arr[i]; int baam = i, daan = i; int l = 1, r = i; if ( i > 1 ) { int ans = i; while (l <= r) { int q = squery1( mid, i ); if (q != x) l = mid + 1; else ans = mid, r = mid - 1; } baam = ans; } l = i, r = n; if ( i < n ) { int ans = i; while (l <= r) { int q = squery1( i, mid ); // cout<<x<< <<l<< <<r<< <<q<<endl; if (q != x) r = mid - 1; else ans = mid, l = mid + 1; } daan = ans; } baam= max( baam, 2 ); daan= min( daan, n-1 ); if( baam<i and arr[baam]==arr[i] ) baam++; if( daan>i and arr[daan]==arr[i] ) daan--; if( pre[baam-1]==suff[daan+1] and pre[baam-1]==arr[i] ) { f= 1; out= daan-baam+1; lf= baam-1; rt= n-daan; break; } // cout<<i<< <<baam<< <<daan<< <<pre[baam-1]<< <<suff[daan+1]<<endl; } if(f) cout<< YES n <<lf<< <<out<< <<rt<< n ; else cout<< NO n ; } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_ddr_dnrcn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_ddr_dnrcn(si ,vdd18 ,cbd ,so ,pad ,sclk ,oe ,above ,
clk ,se ,global_reset_n );
input [8:1] cbd ;
output so ;
output pad ;
output above ;
input si ;
input vdd18 ;
input sclk ;
input oe ;
input clk ;
input se ;
input global_reset_n ;
supply0 vss ;
wire net093 ;
wire sclk1 ;
wire sclk2 ;
wire scan1 ;
wire net051 ;
wire net056 ;
wire net059 ;
wire vf ;
wire net062 ;
wire abvref ;
bw_u1_soff_4x I257 (
.q (sclk1 ),
.so (net093 ),
.ck (clk ),
.d (sclk ),
.se (se ),
.sd (si ) );
bw_u1_soffr_4x I260 (
.q (sclk2 ),
.so (scan1 ),
.ck (clk ),
.d (sclk1 ),
.se (se ),
.sd (net093 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I263 (
.q (above ),
.so (so ),
.ck (clk ),
.d (net062 ),
.se (se ),
.sd (scan1 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I268 (
.z (net051 ),
.a (sclk2 ) );
bw_u1_nand2_4x I269 (
.z (net062 ),
.a (net056 ),
.b (net059 ) );
bw_u1_nand2_4x I270 (
.z (net059 ),
.a (net051 ),
.b (above ) );
bw_u1_nand2_4x I271 (
.z (net056 ),
.a (abvref ),
.b (sclk2 ) );
bw_io_ddr_pad_txrx_zctl I304 (
.vrefcode ({{4 {vf }} ,vss ,vss ,vss ,vss } ),
.cbu ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.cbd ({cbd } ),
.out (abvref ),
.pad (pad ),
.vdd_h (vdd18 ),
.data (vss ),
.oe (oe ),
.odt_enable (vss ) );
bw_io_ddr_rptr_vddcom I319 (
.vdd18 (vdd18 ),
.vdd_com (vf ) );
endmodule
|
//======================================================================
//
// tb_hc.v
// --------
// Testbench for the hc top level wrapper.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_hc();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The DUT address map.
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h08;
parameter CTRL_INIT_BIT = 0;
parameter CTRL_NEXT_BIT = 1;
parameter CTRL_ENCDEC_BIT = 2;
parameter CTRL_KEYLEN_BIT = 3;
parameter ADDR_STATUS = 8'h09;
parameter STATUS_READY_BIT = 0;
parameter STATUS_VALID_BIT = 1;
parameter ADDR_CONFIG = 8'h0a;
parameter ADDR_KEY0 = 8'h10;
parameter ADDR_KEY1 = 8'h11;
parameter ADDR_KEY2 = 8'h12;
parameter ADDR_KEY3 = 8'h13;
parameter ADDR_KEY4 = 8'h14;
parameter ADDR_KEY5 = 8'h15;
parameter ADDR_KEY6 = 8'h16;
parameter ADDR_KEY7 = 8'h17;
parameter ADDR_BLOCK0 = 8'h20;
parameter ADDR_BLOCK1 = 8'h21;
parameter ADDR_BLOCK2 = 8'h22;
parameter ADDR_BLOCK3 = 8'h23;
parameter ADDR_RESULT0 = 8'h30;
parameter ADDR_RESULT1 = 8'h31;
parameter ADDR_RESULT2 = 8'h32;
parameter ADDR_RESULT3 = 8'h33;
parameter HC_128_BIT_KEY = 0;
parameter HC_256_BIT_KEY = 1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [31 : 0] read_data;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
hc dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
// $display("ctrl_reg: init = 0x%01x, next = 0x%01x", dut.init_reg, dut.next_reg);
// $display("config_reg: encdec = 0x%01x, length = 0x%01x ", dut.encdec_reg, dut.keylen_reg);
// $display("");
//
// $display("block: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
// dut.block_reg[0], dut.block_reg[1], dut.block_reg[2], dut.block_reg[3]);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h0;
tb_write_data = 32'h0;
end
endtask // init_sim
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// write_block()
//
// Write the given block to the dut.
//----------------------------------------------------------------
task write_block(input [127 : 0] block);
begin
write_word(ADDR_BLOCK0, block[127 : 96]);
write_word(ADDR_BLOCK1, block[95 : 64]);
write_word(ADDR_BLOCK2, block[63 : 32]);
write_word(ADDR_BLOCK3, block[31 : 0]);
end
endtask // write_block
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// read_result()
//
// Read the result block in the dut.
//----------------------------------------------------------------
task read_result;
begin
read_word(ADDR_RESULT0);
result_data[127 : 096] = read_data;
read_word(ADDR_RESULT1);
result_data[095 : 064] = read_data;
read_word(ADDR_RESULT2);
result_data[063 : 032] = read_data;
read_word(ADDR_RESULT3);
result_data[031 : 000] = read_data;
end
endtask // read_result
//----------------------------------------------------------------
// init_key()
//
// init the key in the dut by writing the given key and
// key length and then trigger init processing.
//----------------------------------------------------------------
task init_key(input [255 : 0] key, input key_length);
begin
if (DEBUG)
begin
$display("key length: 0x%01x", key_length);
$display("Initializing key expansion for key: 0x%016x", key);
end
write_word(ADDR_KEY0, key[255 : 224]);
write_word(ADDR_KEY1, key[223 : 192]);
write_word(ADDR_KEY2, key[191 : 160]);
write_word(ADDR_KEY3, key[159 : 128]);
write_word(ADDR_KEY4, key[127 : 96]);
write_word(ADDR_KEY5, key[95 : 64]);
write_word(ADDR_KEY6, key[63 : 32]);
write_word(ADDR_KEY7, key[31 : 0]);
if (key_length)
begin
write_word(ADDR_CONFIG, 8'h02);
end
else
begin
write_word(ADDR_CONFIG, 8'h00);
end
write_word(ADDR_CTRL, 8'h01);
#(100 * CLK_PERIOD);
end
endtask // init_key
//----------------------------------------------------------------
// hc_test()
//
// Main test task will perform complete NIST test of HC.
//----------------------------------------------------------------
task hc_test;
begin
$display("HC 128 bit key tests");
$display("---------------------");
$display("");
$display("HC 256 bit key tests");
$display("---------------------");
$display("");
end
endtask // hc_test
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for HC started =-");
$display(" =============================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
hc_test();
display_test_results();
$display("");
$display("*** HC simulation done. ***");
$finish;
end // main
endmodule // tb_hc
//======================================================================
// EOF tb_hc.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1000 * 1000 * 1000; const long long inf64 = 1ll * inf * inf; const long long mod = 1e9 + 7; mt19937 rng(0); long long binpow(long long a, long long p, long long mod = 998244353) { if (p == 0) return 1; if (p % 2 == 0) { long long t = binpow(a, p / 2); return t * t % mod; } else { return binpow(a, p - 1) * a % mod; } } long long invert(long long x) { return binpow(x, 998244351); } pair<long long, long long> add(pair<long long, long long> a, pair<long long, long long> b) { pair<long long, long long> ans; ans.first = a.first * b.second + b.first * a.second; ans.second = a.second * b.second; ans.first %= 998244353; ans.second %= 998244353; return ans; } pair<long long, long long> multi(pair<long long, long long> a, pair<long long, long long> b) { return {a.first * b.first % 998244353, a.second * b.second % 998244353}; } void run() { long long n; cin >> n; vector<vector<long long>> a(n); vector<vector<long long>> poses(1e6 + 10); for (long long i = 0; i < n; i++) { long long k; cin >> k; a[i].resize(k); for (long long j = 0; j < k; j++) { cin >> a[i][j]; poses[a[i][j]].push_back(i); } } pair<long long, long long> ans = {0, 1}; for (long long i = 0; i < n; ++i) { pair<long long, long long> t = {1, n}; for (long long k = 0; k < a[i].size(); ++k) { pair<long long, long long> r = {1, a[i].size()}; pair<long long, long long> e = {poses[a[i][k]].size(), n}; ans = add(ans, multi(multi(t, r), e)); } } cout << ans.first * invert(ans.second) % 998244353; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; for (long long i = 0; i < t; i++) { run(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, a[110][110], dp[110][110]; bool vis[110][110]; long long dfs(long long x, long long y, long long num) { if (a[x][y] < num) return (long long)3000000000000000000; if (x == n - 1 && y == m - 1) return a[x][y] - num; if (dp[x][y] != -1) return dp[x][y]; long long ret = (long long)3000000000000000000; if (y + 1 < m) { ret = min(ret, dfs(x, y + 1, num + 1)); } if (x + 1 < n) { ret = min(ret, dfs(x + 1, y, num + 1)); } return dp[x][y] = min((long long)3000000000000000000, ret + a[x][y] - num); } long long solve() { long long ans = (long long)3000000000000000000; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] - i - j <= a[0][0]) { memset(dp, -1, sizeof dp); ans = min(ans, dfs(0, 0, a[i][j] - i - j)); } } } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } cout << solve() << n ; } } |
#include <bits/stdc++.h> const int N = 100000 + 1; struct Point { int x, y; Point(int x = 0, int y = 0) : x(x), y(y) {} Point &operator-=(const Point &o) { x -= o.x; y -= o.y; return *this; } int quadrant() const { if (y != 0) { return y > 0; } return x < 0; } }; long long det(const Point &a, const Point &b) { return (long long)a.x * b.y - (long long)a.y * b.x; } bool operator<(const Point &a, const Point &b) { if (a.quadrant() == b.quadrant()) { return det(a, b) > 0; } return a.quadrant() < b.quadrant(); } Point operator-(Point a, const Point &b) { return a -= b; } std::istream &operator>>(std::istream &in, Point &p) { return in >> p.x >> p.y; } int n, m; Point points[N]; int edge_count, first_edge[N], to[N << 1], flow[N << 1], next_edge[N << 1]; void add_edge(int u, int v) { to[edge_count] = v; flow[edge_count] = 0; next_edge[edge_count] = first_edge[u]; first_edge[u] = edge_count++; } bool visit[N]; int construct(int u) { int size = 1; visit[u] = true; for (int iter = first_edge[u]; iter != -1; iter = next_edge[iter]) { int v = to[iter]; if (!visit[v]) { int ret = construct(v); flow[iter] = -ret; flow[iter ^ 1] = -flow[iter]; size += ret; } } return size; } int cycle[N]; std::map<std::pair<int, int>, int> edges; std::vector<int> sums[N]; int main() { std::cin >> n >> m; edge_count = 0; memset(first_edge, -1, sizeof(first_edge)); for (int i = 0; i < m; ++i) { int a, b; scanf( %d%d , &a, &b); a--, b--; add_edge(a, b); add_edge(b, a); } for (int i = 0; i < n; ++i) { std::cin >> points[i]; } int bottom_id = 0; for (int i = 0; i < n; ++i) { if (points[i].x < points[bottom_id].x) { bottom_id = i; } } points[n++] = points[bottom_id] - Point(1, 0); add_edge(bottom_id, n - 1); add_edge(n - 1, bottom_id); memset(visit, 0, sizeof(visit)); construct(n - 1); for (int u = 0; u < n; ++u) { std::vector<std::pair<Point, int> > order; for (int iter = first_edge[u]; iter != -1; iter = next_edge[iter]) { int v = to[iter]; order.push_back(std::make_pair(points[v] - points[u], iter)); } std::sort(order.begin(), order.end()); sums[u].push_back(0); for (int i = 0; i < (int)order.size(); ++i) { int iter = order[i].second; edges[std::make_pair(u, to[iter])] = i + 1; sums[u].push_back(sums[u].back() + flow[iter]); } } int q; std::cin >> q; while (q--) { int m; scanf( %d , &m); for (int i = 0; i < m; ++i) { scanf( %d , cycle + i); cycle[i]--; } long long area = 0; for (int i = 0; i < m; ++i) { area += det(points[cycle[i]], points[cycle[(i + 1) % m]]); } if (area < 0) { std::reverse(cycle, cycle + m); } int answer = 0; for (int i = 0; i < m; ++i) { int u = cycle[i]; int from = edges[std::make_pair(u, cycle[(i + m - 1) % m])]; int to = edges[std::make_pair(u, cycle[(i + 1) % m])]; if (from <= to) { answer += sums[u][to - 1]; answer -= sums[u][from]; } else { answer += sums[u][(int)sums[u].size() - 1]; answer -= sums[u][from]; answer += sums[u][to - 1]; } } printf( %d n , answer); } return 0; } |
module prometheus_fx3_stream_in(
input rst_n,
input clk_100,
input stream_in_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
output o_gpif_we_n_stream_in_,
output [31:0] data_out_stream_in
);
reg [2:0]current_stream_in_state;
reg [2:0]next_stream_in_state;
reg [31:0]data_gen_stream_in;
//parameters for StreamIN mode state machine
parameter [2:0] stream_in_idle = 3'd0;
parameter [2:0] stream_in_wait_flagb = 3'd1;
parameter [2:0] stream_in_write = 3'd2;
parameter [2:0] stream_in_write_wr_delay = 3'd3;
assign o_gpif_we_n_stream_in_ = ((current_stream_in_state == stream_in_write) && (i_gpif_out_ch0_rdy_d == 1'b1)) ? 1'b0 : 1'b1;
//stream_in mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_stream_in_state <= stream_in_idle;
end else begin
current_stream_in_state <= next_stream_in_state;
end
end
//StreamIN mode state machine combo
always @(*)begin
next_stream_in_state = current_stream_in_state;
case(current_stream_in_state)
stream_in_idle:begin
if((stream_in_mode_selected) & (i_gpif_in_ch0_rdy_d == 1'b1))begin
next_stream_in_state = stream_in_wait_flagb;
end else begin
next_stream_in_state = stream_in_idle;
end
end
stream_in_wait_flagb :begin
if (i_gpif_out_ch0_rdy_d == 1'b1)begin
next_stream_in_state = stream_in_write;
end else begin
next_stream_in_state = stream_in_wait_flagb;
end
end
stream_in_write:begin
if(i_gpif_out_ch0_rdy_d == 1'b0)begin
next_stream_in_state = stream_in_write_wr_delay;
end else begin
next_stream_in_state = stream_in_write;
end
end
stream_in_write_wr_delay:begin
next_stream_in_state = stream_in_idle;
end
endcase
end
//data generator counter for Partial, ZLP, StreamIN modes
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
data_gen_stream_in <= 32'd0;
end else if((o_gpif_we_n_stream_in_ == 1'b0) & (stream_in_mode_selected)) begin
data_gen_stream_in <= data_gen_stream_in + 1;
end else if (!stream_in_mode_selected) begin
data_gen_stream_in <= 32'd0;
end
end
assign data_out_stream_in = data_gen_stream_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; double PI = acos(-1); vector<int> adj[100005]; bool vis[100005]; map<pair<int, int>, long long> edge; map<pair<int, int>, pair<long long, int>> weight; long long mod = 1e9 + 7; int n, k; long long dfs(int node) { vis[node] = 1; long long ans = 1; for (auto v : adj[node]) { if (!vis[v]) { long long a = dfs(v); edge[{v, node}] = a; edge[{node, v}] = a; ans += a; } } if (ans > 1) ans--; return ans; } void clc() { for (int i = 0; i <= n; i++) { adj[i].clear(); vis[i] = 0; } edge.clear(); weight.clear(); } void test_case() { long long sum = 0, ans = 1e8, s; cin >> n >> s; pair<int, int> arr[n]; vector<long long> v1, v2; v1.push_back(0), v2.push_back(0); for (int i = 0; i < n - 1; i++) { int x, y, c, w; cin >> x >> y >> c >> w; adj[x].push_back(y), adj[y].push_back(x); arr[i] = {x, y}; weight[{x, y}] = {c, w}, weight[{y, x}] = {c, w}; } dfs(1); for (int i = 0; i < n; i++) { long long x = edge[{arr[i].first, arr[i].second}], y = weight[{arr[i].first, arr[i].second}].first; sum += x * y; while (y) { if (weight[{arr[i].first, arr[i].second}].second == 1) v1.push_back(x * y - x * (y / 2)); else v2.push_back(x * y - x * (y / 2)); y /= 2; } } sort(v1.begin() + 1, v1.end()); sort(v2.begin() + 1, v2.end()); reverse(v1.begin() + 1, v1.end()); reverse(v2.begin() + 1, v2.end()); for (int i = 1; i < v1.size(); i++) v1[i] += v1[i - 1]; for (int i = 1; i < v2.size(); i++) v2[i] += v2[i - 1]; for (int i = 0; i < v2.size(); i++) { long long pos = lower_bound(v1.begin(), v1.end(), sum - s - v2[i]) - v1.begin(); if (pos == v1.size()) continue; ans = min(ans, pos + 2 * i); } cout << ans << n ; clc(); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { test_case(); } return 0; } |
#include <bits/stdc++.h> int a[15][200000][15]; int b[15] = {0}; int main() { a[1][0][0] = 0; b[1] = 1; int n; scanf( %d , &n); for (int i = 0; i < n; i++) { for (int j = 0; j < b[i]; j++) { int m = 0; for (int k = 0; k <= i; k++) if (a[i][j][k] > m) m = a[i][j][k]; m++; if (j % 2 == 0) { for (int k = 0; k <= i; k++) a[i + 1][b[i + 1]][k] = a[i][j][k]; a[i + 1][b[i + 1]][i + 1] = 0; b[i + 1]++; for (int r = m; r > 0; r--) { for (int k = 0; k <= i; k++) a[i + 1][b[i + 1]][k] = a[i][j][k]; a[i + 1][b[i + 1]][i + 1] = r; b[i + 1]++; } } else { for (int r = 1; r <= m; r++) { for (int k = 0; k <= i; k++) a[i + 1][b[i + 1]][k] = a[i][j][k]; a[i + 1][b[i + 1]][i + 1] = r; b[i + 1]++; } for (int k = 0; k <= i; k++) a[i + 1][b[i + 1]][k] = a[i][j][k]; a[i + 1][b[i + 1]][i + 1] = 0; b[i + 1]++; } } } printf( %d n , b[n]); for (int i = 0; i < b[n]; i++) { int m = 0; for (int j = 1; j <= n; j++) if (a[n][i][j] > m) m = a[n][i][j]; for (int j = 0; j <= m; j++) { if (j > 0) printf( , ); printf( { ); bool first = true; for (int k = 1; k <= n; k++) if (a[n][i][k] == j) { if (first) first = false; else printf( , ); printf( %d , k); } printf( } ); } printf( n ); } } |
// =======================================================================
// Department of Electrical and Computer Engineering
// Portland State University
//
// Course name: ECE 510 - Pre-Silicon Validation
// Term & Year: Spring 2015
// Instructor : Tareque Ahmad
//
// Project: PDP8 Hardware Simulator top level testbench
//
//
// Filename: top.sv
// Description: TBD
// Created by: Tareque Ahmad
// Date: May 03, 2015
//
// Copyright: Tareque Ahmad
// =======================================================================
`include "pdp8_pkg.sv"
import pdp8_pkg::*;
module top ();
wire clk;
wire reset_n;
wire stall;
wire [`ADDR_WIDTH-1:0] PC_value;
wire ifu_rd_req;
wire [`ADDR_WIDTH-1:0] ifu_rd_addr;
wire [`DATA_WIDTH-1:0] ifu_rd_data;
wire exec_rd_req;
wire [`ADDR_WIDTH-1:0] exec_rd_addr;
wire [`DATA_WIDTH-1:0] exec_rd_data;
wire exec_wr_req;
wire [`ADDR_WIDTH-1:0] exec_wr_addr;
wire [`DATA_WIDTH-1:0] exec_wr_data;
wire [`ADDR_WIDTH-1:0] base_addr;
pdp_mem_opcode_s pdp_mem_opcode;
pdp_op7_opcode_s pdp_op7_opcode;
clkgen_driver #(
.CLOCK_PERIOD(10),
.RESET_DURATION(500)) clkgen_driver (
.clk (clk),
.reset_n (reset_n));
// memory_pdp memory_pdp (.*); //for determinsitic
instr_decode instr_decode(.*);
test_instr_decode test_instr_decode(.*);
endmodule |
/*
PC to FPGA Command Table
Command Description Operand
data_bus_in[7:4] data_bus[3:0]
---------------- -------------------------------- --------------------
0 - Unused / illegal N/A
1 - Request panel selector data N/A
2 - Set panel address {2'b0, panel_addr}
3 - Set row address row_addr
4 - Set chunk address chunk_addr
5 - Set nibble 0 of chunk nibble
6 - Set nibble 1 of chunk nibble
7 - Set nibble 2 of chunk nibble
8 - Set nibble 3 of chunk nibble
9 - Set nibble 4 of chunk nibble
10 - Set nibble 5 of chunk nibble
11 - Set nibble 6 of chunk nibble
12 - Set nibble 7 of chunk nibble
13 - Write chunk N/A
14 - Unused / illegal N/A
15 - Unused / illegal N/A
FPGA to PC Command Table
Command Description Operand
data_bus_out[7:4] data_bus[3:0]
----------------- -------------------------------- --------------------
0 - Unused / illegal N/A
1 - Set panel 0 number panel_switches[3:0]
2 - Set panel 1 number panel_switches[7:4]
3 - Set panel 2 number panel_switches[11:8]
4 - Set panel 3 number panel_switches[15:12]
5 - Unused / illegal N/A
6 - Unused / illegal N/A
7 - Unused / illegal N/A
8 - Unused / illegal N/A
9 - Unused / illegal N/A
10 - Unused / illegal N/A
10 - Unused / illegal N/A
11 - Unused / illegal N/A
12 - Unused / illegal N/A
13 - Unused / illegal N/A
14 - Unused / illegal N/A
15 - Unused / illegal N/A
*/
module usb_controller
(
input clk,
input reset_n,
input [15:0] panel_switches_raw,
input rxf_n_raw,
input txe_n_raw,
input [7:0] data_bus_in_raw,
output [7:0] data_bus_out,
output rd_n,
output wr_n,
output data_out_enable,
output [31:0] chunk_data,
output [3:0] chunk_addr,
output chunk_write_enable,
output [3:0] row_addr,
output [1:0] panel_addr,
output [4:0] state_out,
output panel_select_request
);
wire rxf_n, txe_n;
wire command_write_enable, clear_psr;
wire [15:0] panel_switches;
wire [7:0] data_bus_in;
wire [15:0] command_select;
assign chunk_write_enable = command_select[13] & command_write_enable;
synchronizer #(.WIDTH(16)) panel_sw_sync
(.clk(clk), .in(panel_switches_raw), .out(panel_switches));
synchronizer #(.WIDTH(8)) data_bus_input_sync
(.clk(clk), .in(data_bus_in_raw), .out(data_bus_in));
synchronizer #(.WIDTH(2)) rx_tx_sync
(.clk(clk), .in({rxf_n_raw, txe_n_raw}), .out({rxf_n, txe_n}));
usb_sequencer seq
(.clk(clk),
.reset_n(reset_n),
.rxf_n(rxf_n),
.txe_n(txe_n),
.panel_select_request(panel_select_request),
.panel_switches(panel_switches),
.data_out(data_bus_out),
.rd_n(rd_n),
.wr_n(wr_n),
.data_out_enable(data_out_enable),
.command_write_enable(command_write_enable),
.clear_psr(clear_psr),
.state_out(state_out));
decoder #(.WIDTH(4)) command_decoder
(.addr(data_bus_in[7:4]), .y(command_select));
jk_flipflop panel_select_request_register
(.clk(clk),
.reset_n(reset_n),
.j(command_select[1] & command_write_enable),
.k(clear_psr),
.q(panel_select_request));
register_with_write_enable #(.WIDTH(2)) panel_addr_command_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[2] & command_write_enable),
.d(data_bus_in[1:0]),
.q(panel_addr));
register_with_write_enable #(.WIDTH(4)) row_addr_command_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[3] & command_write_enable),
.d(data_bus_in[3:0]),
.q(row_addr));
register_with_write_enable #(.WIDTH(4)) chunk_addr_command_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[4] & command_write_enable),
.d(data_bus_in[3:0]),
.q(chunk_addr));
genvar i;
generate
for (i=0; i<8; i=i+1)
begin : nibble_registers
register_with_write_enable #(.WIDTH(4)) nibble_register
(.clk(clk),
.reset_n(reset_n),
.write_enable(command_select[i+5] & command_write_enable),
.d(data_bus_in[3:0]),
.q(chunk_data[4*i+3:4*i]));
end
endgenerate
endmodule // usb_controller
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110; static int N, M, P, val[MAXN], cut[MAXN]; int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= N; i++) scanf( %d , &val[i]); for (int i = 1, odd = 0, evn = 0; i < N; i++) { ((val[i] & 1) ? odd : evn) += 1; if (odd == evn) cut[P++] = abs(val[i + 1] - val[i]); } sort(cut, cut + P); for (int i = 0, sum = 0; i < P; i++) if ((sum += cut[i]) > M) return printf( %d n , i), 0; printf( %d n , P); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int a[100010], b[100010]; int main() { int n, k, m; scanf( %d%d , &n, &k); int val = 1; for (int i = 0; i < k; i++) val *= 10; m = n / k; for (int i = 0; i < m; i++) scanf( %d , &a[i]); for (int i = 0; i < m; i++) scanf( %d , &b[i]); long long ans = 1; for (int i = 0; i < m; i++) { int t = (val - (val % a[i])) / a[i]; if (val % a[i]) t++; int num = (a[i] - (val / 10 * b[i]) % a[i]) % a[i]; if ((val / 10) <= num) { ans = ans * t % mod; continue; } int tt = ((val / 10 - num) - ((val / 10 - num) % a[i])) / a[i]; if ((val / 10 - num) % a[i]) tt++; ans = ans * (t - tt) % mod; } printf( %d n , ans); return 0; } |
`include "defines.v"
module arbitor (
input `rmatrix_w rmatrix0,
input `rmatrix_w rmatrix1,
input `rmatrix_w rmatrix2,
input `rmatrix_w rmatrix3,
input `rmatrix_w rmatrix4,
input `control_w control0_in,
input `control_w control1_in,
input `control_w control2_in,
input `control_w control3_in,
input `control_w control4_in,
input clk,
input rst,
output reg `control_w control0_out,
output reg `control_w control1_out,
output reg `control_w control2_out,
output reg `control_w control3_out,
output reg `control_w control4_out,
output reg `routecfg_w route_config);
// Priority Comparator
wire [1:0] p0, p1, p2, p3;
// Round robin register
reg [1:0] rr;
// Gold flit counters
reg `gold_w gold;
reg `l_w lcount;
// Arbitor Tree
wire `amatrix_w amatrix1, amatrix2, amatrix3,
amatrix4, amatrix5;
wire `routecfg_w rc1, rc2, rc3, rc4, rc5;
priority_comparator pc(.control0(control0_in),
.control1(control1_in),
.control2(control2_in),
.control3(control3_in),
.rr(rr),
.priority0(p0),
.priority1(p1),
.priority2(p2),
.priority3(p3));
arbitor_cell prior0(.priority({1'b0, p0}),
.rmatrix0(rmatrix0),
.rmatrix1(rmatrix1),
.rmatrix2(rmatrix2),
.rmatrix3(rmatrix3),
.rmatrix4(rmatrix4),
.valid0(control0_in[`valid_f]),
.valid1(control1_in[`valid_f]),
.valid2(control2_in[`valid_f]),
.valid3(control3_in[`valid_f]),
.valid4(control4_in[`valid_f]),
.amatrix_o(`amatrix_n'd0),
.rco(`routecfg_n'h7FFF),
.amatrix_n(amatrix1),
.rcn(rc1));
arbitor_cell prior1(.priority({1'b0, p1}),
.rmatrix0(rmatrix0),
.rmatrix1(rmatrix1),
.rmatrix2(rmatrix2),
.rmatrix3(rmatrix3),
.rmatrix4(rmatrix4),
.valid0(control0_in[`valid_f]),
.valid1(control1_in[`valid_f]),
.valid2(control2_in[`valid_f]),
.valid3(control3_in[`valid_f]),
.valid4(control4_in[`valid_f]),
.amatrix_o(amatrix1),
.rco(rc1),
.amatrix_n(amatrix2),
.rcn(rc2));
arbitor_cell prior2(.priority({1'b0, p2}),
.rmatrix0(rmatrix0),
.rmatrix1(rmatrix1),
.rmatrix2(rmatrix2),
.rmatrix3(rmatrix3),
.rmatrix4(rmatrix4),
.valid0(control0_in[`valid_f]),
.valid1(control1_in[`valid_f]),
.valid2(control2_in[`valid_f]),
.valid3(control3_in[`valid_f]),
.valid4(control4_in[`valid_f]),
.amatrix_o(amatrix2),
.rco(rc2),
.amatrix_n(amatrix3),
.rcn(rc3));
arbitor_cell prior3(.priority({1'b0, p3}),
.rmatrix0(rmatrix0),
.rmatrix1(rmatrix1),
.rmatrix2(rmatrix2),
.rmatrix3(rmatrix3),
.rmatrix4(rmatrix4),
.valid0(control0_in[`valid_f]),
.valid1(control1_in[`valid_f]),
.valid2(control2_in[`valid_f]),
.valid3(control3_in[`valid_f]),
.valid4(control4_in[`valid_f]),
.amatrix_o(amatrix3),
.rco(rc3),
.amatrix_n(amatrix4),
.rcn(rc4));
arbitor_cell prior4(.priority(3'b100),
.rmatrix0(rmatrix0),
.rmatrix1(rmatrix1),
.rmatrix2(rmatrix2),
.rmatrix3(rmatrix3),
.rmatrix4(rmatrix4),
.valid0(control0_in[`valid_f]),
.valid1(control1_in[`valid_f]),
.valid2(control2_in[`valid_f]),
.valid3(control3_in[`valid_f]),
.valid4(control4_in[`valid_f]),
.amatrix_o(amatrix4),
.rco(rc4),
.amatrix_n(amatrix5),
.rcn(rc5));
initial begin
rr = 0;
gold = 0;
lcount = 0;
route_config = 0;
end
always @(posedge clk) begin
if (rst) begin
rr <= 0;
gold <= 0;
lcount <= 0;
route_config <= 0;
control0_out <= 0;
control1_out <= 0;
control2_out <= 0;
control3_out <= 0;
control4_out <= 0;
end else begin
// This increments the the round robin register. Utilize overflow
// to reset the counter
rr <= rr + 1;
// We increment l until you hit the limit. Then gold will be
// incremented by 1 and l is reset
if (lcount == `l_limit) begin
lcount <= 0;
gold <= gold + 1;
end else begin
lcount <= lcount + 1;
end
// Recalculate if the flit will be gold and set the bit as needed
if ({control0_in[`src_f], control0_in[`pkt_f]} == gold) begin
control0_out <= control0_in | `gold_on_mask;
end else begin
control0_out <= control0_in & `gold_off_mask;
end
if ({control1_in[`src_f], control1_in[`pkt_f]} == gold) begin
control1_out <= control1_in | `gold_on_mask;
end else begin
control1_out <= control1_in & `gold_off_mask;
end
if ({control2_in[`src_f], control2_in[`pkt_f]} == gold) begin
control2_out <= control2_in | `gold_on_mask;
end else begin
control2_out <= control2_in & `gold_off_mask;
end
if ({control3_in[`src_f], control3_in[`pkt_f]} == gold) begin
control3_out <= control3_in | `gold_on_mask;
end else begin
control3_out <= control3_in & `gold_off_mask;
end
if ({control4_in[`src_f], control4_in[`pkt_f]} == gold) begin
control4_out <= control4_in | `gold_on_mask;
end else begin
control4_out <= control4_in & `gold_off_mask;
end
end
route_config <= rc5;
end
endmodule
module arbitor_cell(
input [2:0] priority,
input `rmatrix_w rmatrix0,
input `rmatrix_w rmatrix1,
input `rmatrix_w rmatrix2,
input `rmatrix_w rmatrix3,
input `rmatrix_w rmatrix4,
input valid0,
input valid1,
input valid2,
input valid3,
input valid4,
input `amatrix_w amatrix_o,
input `routecfg_w rco,
output `amatrix_w amatrix_n,
output `routecfg_w rcn);
wire `rmatrix_w smatrix; // The route matrix we will use
wire [2:0] selected; // Selected port to use
wire svalid;
// Select the current priorities routing matrix
assign smatrix = (priority == 3'd0) ? rmatrix0 :
(priority == 3'd1) ? rmatrix1 :
(priority == 3'd2) ? rmatrix2 :
(priority == 3'd3) ? rmatrix3 :
(priority == 3'd4) ? rmatrix4 : `rmatrix_n'bX;
// Select which valid line to use
assign svalid = (priority == 3'd0) ? valid0 :
(priority == 3'd1) ? valid1 :
(priority == 3'd2) ? valid2 :
(priority == 3'd3) ? valid3 :
(priority == 3'd4) ? valid4 : 1'b0;
// Select the route to take. Prioritize X directions over Y directions
// 0 = North
// 1 = South
// 2 = East
// 3 = West
// 4 = Resource
// 7 = Invalid
assign selected = (svalid == 1'b0) ? 3'd7 :
// At Destination
(~|(smatrix) && ~amatrix_o[4]) ? 3'd4 :
// To Target
(smatrix[0] && ~amatrix_o[0]) ? 3'd0 :
(smatrix[1] && ~amatrix_o[1]) ? 3'd1 :
(smatrix[2] && ~amatrix_o[2]) ? 3'd2 :
(smatrix[3] && ~amatrix_o[3]) ? 3'd3 :
// Misroute
(~amatrix_o[0]) ? 3'd0 :
(~amatrix_o[1]) ? 3'd1 :
(~amatrix_o[2]) ? 3'd2 :
(~amatrix_o[3]) ? 3'd3 : 3'd7;
// Update the route computed table
assign rcn = (selected == 3'd0) ? {rco[`routecfg_4], rco[`routecfg_3],
rco[`routecfg_2], rco[`routecfg_1],
priority} :
(selected == 3'd1) ? {rco[`routecfg_4], rco[`routecfg_3],
rco[`routecfg_2], priority,
rco[`routecfg_0]} :
(selected == 3'd2) ? {rco[`routecfg_4], rco[`routecfg_3],
priority, rco[`routecfg_1],
rco[`routecfg_0]} :
(selected == 3'd3) ? {rco[`routecfg_4], priority,
rco[`routecfg_2], rco[`routecfg_1],
rco[`routecfg_0]} :
(selected == 3'd4) ? {priority, rco[`routecfg_3],
rco[`routecfg_2], rco[`routecfg_1],
rco[`routecfg_0]} :
(selected == 3'd7) ? rco : rco;
// Update the assigned matrix
assign amatrix_n = (selected == 3'd0) ? amatrix_o | `amatrix_n'd1 :
(selected == 3'd1) ? amatrix_o | `amatrix_n'd2 :
(selected == 3'd2) ? amatrix_o | `amatrix_n'd4 :
(selected == 3'd3) ? amatrix_o | `amatrix_n'd8 :
(selected == 3'd4) ? amatrix_o | `amatrix_n'd16:
amatrix_o;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; char c[2001][2001]; int sum1[2001][2001], sum2[2001][2001]; int f[2001][2001][2]; int mod = 1000000007; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %c , &c[i][j]); } } if (n == 1 && m == 1 && c[1][1] == . ) { cout << 1 << endl; return 0; } for (int i = n; i >= 1; i--) { for (int j = m; j >= 1; j--) { if (c[i][j] == R ) { sum1[i][j] = sum1[i][j + 1] + 1; sum2[i][j] = sum2[i + 1][j] + 1; } else { sum1[i][j] = sum1[i][j + 1]; sum2[i][j] = sum2[i + 1][j]; } } } for (int i = 1; i < n; i++) { if (sum2[i][m] == 0) f[i][m][0] = 1; } for (int i = 1; i < m; i++) { if (sum1[n][i] == 0) f[n][i][1] = 1; } for (int i = n - 1; i >= 1; i--) { for (int j = m - 1; j >= 1; j--) { f[i][j][0] += f[i + 1][j][1]; f[i][j][1] += f[i][j + 1][0]; f[i][j][0] %= mod; f[i][j][1] %= mod; if (c[i + 1][j] == R ) { f[i][j][0] += (f[i + 1][j][0] - f[n - sum2[i + 1][j] + 1][j][1] + mod) % mod; } else { f[i][j][0] += f[i + 1][j][0]; } if (c[i][j + 1] == R ) { f[i][j][1] += (f[i][j + 1][1] - f[i][m - sum1[i][j + 1] + 1][0] + mod) % mod; } else { f[i][j][1] += f[i][j + 1][1]; } f[i][j][0] %= mod; f[i][j][1] %= mod; } } cout << (f[1][1][0] + f[1][1][1]) % mod << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int m, n, sum = 0, i = 1, k; cin >> n >> m; k = m; while (m >= i) { m -= i; i = (i % n) + 1; } cout << m << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; double p[600][600], pp[600][600]; double f[600][600]; bool checkInRound(int I, int K, int Round) { int i = I - 1; int k = K - 1; if (i / (1 << Round) != k / (1 << Round)) return false; if (i / (1 << (Round - 1)) == k / (1 << (Round - 1))) return false; return true; } int main() { memset(f, 0, sizeof(f)); int N; cin >> N; int SL = 1 << N; for (int i = 1; i <= SL; i++) { int temp; for (int j = 1; j <= SL; j++) { scanf( %d , &temp); p[i][j] = temp * 0.01; } } int Round = N; for (int i = 1; i <= SL; i++) { if (i % 2) { f[i][1] = p[i][i + 1]; } else { f[i][1] = p[i][i - 1]; } } for (int i = 1; i <= SL; i++) pp[i][1] = f[i][1]; for (int R = 2; R <= Round; R++) { for (int i = 1; i <= SL; i++) { for (int k = 1; k <= SL; k++) { if (checkInRound(i, k, R)) { pp[i][R] += pp[i][R - 1] * pp[k][R - 1] * p[i][k]; } } } } for (int R = 2; R <= Round; R++) { for (int i = 1; i <= SL; i++) { double mem = 0; for (int k = 1; k <= SL; k++) { if (checkInRound(i, k, R)) { f[i][R] += pp[i][R - 1] * pp[k][R - 1] * p[i][k] * (1 << (R - 1)); mem = max(mem, f[k][R - 1]); } } f[i][R] += mem + f[i][R - 1]; } } double ans = 0; for (int i = 1; i <= SL; i++) ans = max(ans, f[i][Round]); printf( %.12f , ans); } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: phy_ck_iob.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:33 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock forwarding to memory
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_ck_iob.v,v 1.4 2010/02/26 08:58:33 pboya Exp $
**$Date: 2010/02/26 08:58:33 $
**$Author: pboya $
**$Revision: 1.4 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_ck_iob.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_ck_iob #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter WRLVL = "OFF", // Enable write leveling
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter IODELAY_GRP = "IODELAY_MIG" // May be assigned unique name
// when mult IP cores in design
)
(
input clk_mem, // full rate core clock
input clk, // half rate core clock
input rst, // half rate core clk reset
output ddr_ck_p, // forwarded diff. clock to memory
output ddr_ck_n // forwarded diff. clock to memory
);
wire ck_p_odelay;
wire ck_p_oq;
wire ck_p_out;
//*****************************************************************
// Note on generation of Control/Address signals - there are
// several possible configurations that affect the configuration
// of the OSERDES and possible ODELAY for each output (this will
// also affect the CK/CK# outputs as well
// 1. DDR3, write-leveling: This is the simplest case. Use
// OSERDES without the ODELAY. Initially clock/control/address
// will be offset coming out of FPGA from DQ/DQS, but DQ/DQS
// will be adjusted so that DQS-CK alignment is established
// 2. DDR2 or DDR3 (no write-leveling): Both DQS and DQ will use
// ODELAY to delay output of OSERDES. To match this,
// CK/control/address must also delay their outputs using ODELAY
// (with delay = 0)
//*****************************************************************
OBUFDS u_obuf_ck
(
.O (ddr_ck_p),
.OB (ddr_ck_n),
.I (ck_p_out)
);
OSERDESE1 #
(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("BUF"),
.DATA_WIDTH (4),
.DDR3_DATA (0),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"),
.ODELAY_USED (0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (1)
)
u_oserdes_ck_p
(
.OCBEXTEND (),
.OFB (),
.OQ (ck_p_oq),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TQ (),
.CLK (clk_mem),
.CLKDIV (clk),
.CLKPERF (),
.CLKPERFDELAY (),
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.D5 (),
.D6 (),
.ODV (1'b0),
.OCE (1'b1),
.RST (rst),
// Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
// (for all other OSERDES used in design, these are no-connects):
// ensures that CK/CK# outputs are not X at start of simulation
// Certain DDR2 memory models may require that CK/CK# be valid
// throughout simulation
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TFB (),
.TCE (1'b1),
.WC (1'b0)
);
generate
if ((DRAM_TYPE == "DDR3") && (WRLVL == "ON")) begin: gen_ck_wrlvl
//*******************************************************
// CASE1: DDR3, write-leveling
//*******************************************************
assign ck_p_out = ck_p_oq;
end else begin: gen_ck_nowrlvl
//*******************************************************
// CASE2: No write leveling (DDR2 or DDR3)
//*******************************************************
assign ck_p_out = ck_p_odelay;
(* IODELAY_GROUP = IODELAY_GRP *) IODELAYE1 #
(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("O"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (REFCLK_FREQ),
.SIGNAL_PATTERN ("CLOCK")
)
u_iodelay_ck_p
(
.DATAOUT (ck_p_odelay),
.C (1'b0),
.CE (1'b0),
.DATAIN (),
.IDATAIN (),
.INC (1'b0),
.ODATAIN (ck_p_oq),
.RST (1'b0),
.T (),
.CNTVALUEIN (),
.CNTVALUEOUT (),
.CLKIN (),
.CINVCTRL (1'b0)
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t ();
// See also t_math_width
// This shows the uglyness in width warnings across param modules
// TODO: Would be nice to also show relevant parameter settings
p #(.WIDTH(4)) p4 (.in(4'd0));
p #(.WIDTH(5)) p5 (.in(5'd0));
//====
localparam [3:0] XS = 'hx; // User presumably intended to use 'x
//====
wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax
wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is
//====
localparam WIDTH = 6;
wire one_bit;
wire [2:0] shifter = 1;
wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
//====
// We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
wire one = 1;
wire [2:0] cnt = (one + one + one + one);
// Not harmless > or >= compared with something wider (as different results if "a" wider)
localparam [40:0] THREE = 3;
int a;
initial for (a = 0; a > THREE; ++a) $display(a);
initial for (a = 0; a >= THREE; ++a) $display(a);
initial if (THREE) $stop;
endmodule
module p
#(parameter WIDTH=64)
(input [WIDTH-1:0] in);
wire [4:0] out = in;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long range(long long L) { switch (L & 3) { case 0: return L; case 1: return 1; case 2: return L + 1; case 3: return 0; } } int main() { for (int N; cin >> N;) { long long sum = 0; for (int i = 0; i < (int)(N); ++i) { long long m, x; cin >> x >> m; long long b = range(x - 1); long long a = range(x + m - 1); sum ^= b; sum ^= a; } if (sum == 0) cout << bolik << endl; else cout << tolik << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 50; long long g[maxn]; int ans, n; inline int ctz(long long s) { return s ? __builtin_ctzll(s) : 8 * sizeof(long long); } void BronKerbosch(long long clique, long long allow, long long forbid) { if (!allow && !forbid) { ans = max(ans, __builtin_popcountll(clique)); return; } if (!allow) return; int pivot = ctz(allow | forbid); long long choose = allow & ~g[pivot]; for (int u = ctz(choose); u < n; u += ctz(choose >> (u + 1)) + 1) { BronKerbosch(clique | (1LL << u), allow & g[u], forbid & g[u]); allow ^= 1LL << u; forbid |= 1LL << u; } } int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); int k; long long x; cin >> n >> k; memset(g, 0, sizeof(g)); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> x; g[i] ^= (x << j); } } BronKerbosch(0LL, (1LL << n) - 1, 0LL); printf( %.9f n , 1.0 * k * k * (ans - 1) / (2 * ans)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_TB_V
`define SKY130_FD_SC_HS__CLKBUF_TB_V
/**
* clkbuf: Clock tree buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { set<int> s; int n; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; s.insert(x); } set<int>::iterator it, it1, it2; it = s.begin(); it1 = it; it1++; it2 = s.end(); it2--; if (s.size() == 1) cout << 0 << endl; else if (s.size() == 2) { int e = *it1 - (*it); if (e % 2 == 0) e /= 2; cout << e; } else if (s.size() == 3) { int a = (*it); int b = (*it1); int c = (*it2); if (b - a == c - b) cout << b - a << endl; else cout << -1 << endl; } else cout << -1 << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_SYMBOL_V
`define SKY130_FD_SC_LS__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_SYMBOL_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE");
end
end
end
assign fire_2state_1 = (test_expr == 1'b0);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
|
#include <bits/stdc++.h> using namespace std; int A[1000000]; map<char, int> M; int main() { for (int i = 0; i <= 63; i++) for (int j = 0; j <= 63; j++) A[i & j]++; for (int i = 0; i <= 9; i++) M[i + 0 ] = i; for (int i = 0; i < 26; i++) M[i + A ] = i + 10; for (int i = 0; i < 26; i++) M[i + a ] = i + 36; M[ _ ] = 63, M[ - ] = 62; string s; cin >> s; long long ans = 1; long long mod = 1e9 + 7; for (int i = 0; i < s.size(); i++) ans = ans * A[M[s[i]]] % mod; cout << ans << endl; return 0; } |
module top (
input wire clk,
input wire [7:0] sw,
output wire [7:0] led,
output wire [3:0] io_out,
input wire [3:0] io_inp
);
// PLL (to get clock division and still keep 50% duty cycle)
wire fb;
wire clk_ddr;
wire clk_ddr_nobuf;
PLLE2_ADV # (
.CLKFBOUT_MULT (16),
.CLKOUT0_DIVIDE (64) // 25MHz
) pll (
.CLKIN1 (clk),
.CLKFBIN (fb),
.CLKFBOUT (fb),
.CLKOUT0 (clk_ddr_nobuf)
);
BUFG bufg (.I(clk_ddr_nobuf), .O(clk_ddr));
// Heartbeat
reg [23:0] cnt;
always @(posedge clk_ddr)
cnt <= cnt + 1;
assign led[7] = cnt[23];
// IDELAYCTRL
IDELAYCTRL idelayctrl (
.REFCLK (clk_ddr),
.RDY (led[6])
);
// Testers
ioddr_tester #(.DDR_CLK_EDGE("SAME_EDGE"))
tester0 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[0]), .Q(io_out[0]), .D(io_inp[0]));
ioddr_tester #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), .USE_IDELAY(1))
tester1 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[1]), .Q(io_out[1]), .D(io_inp[1]));
ioddr_tester #(.DDR_CLK_EDGE("OPPOSITE_EDGE"))
tester2 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[2]), .Q(io_out[2]), .D(io_inp[2]));
ioddr_tester #(.USE_PHY_ODDR(0))
tester3 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[3]), .Q(io_out[3]), .D(io_inp[3]));
// Unused LEDs
assign led[5:4] = |sw;
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long int; template <class TH> void _dbg(const char *sdbg, TH h) { cerr << sdbg << = << h << n ; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cerr << *sdbg++; cerr << = << h << , ; _dbg(sdbg + 1, a...); } template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto vv : V) os << vv << , ; return os << ] ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.st << , << P.nd << ) ; } const int MAXN = 3003; string t, s; int n, m; LL dp[MAXN][MAXN]; LL mod = 998244353; bool vis[MAXN][MAXN]; LL dfs(int i, int j) { (i, j); if (j == i - 1) { return 1; } if (vis[i][j]) { return dp[i][j]; } vis[i][j] = true; char last = s[(j - i) + 1]; LL actRes = 0; if (i > m || last == t[i]) { actRes += dfs(i + 1, j); actRes %= mod; } if (j > m || last == t[j]) { actRes += dfs(i, j - 1); actRes %= mod; } dp[i][j] = actRes; return dp[i][j]; } int main() { cin >> s >> t; n = s.size(); m = t.size(); s = # + s; t = # + t; LL res = dfs(1, n); res = 0; for (int i = m; i <= n; ++i) { res += dp[1][i]; res %= mod; } cout << res << endl; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in4.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
|
module EXMEM_Reg (
input clk,
input flush,
input stall,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] ALU_output_i,
output [32-1:0] ALU_output_o,
input [32-1:0] ALU_data_2_i,
output [32-1:0] ALU_data_2_o,
input [5-1:0] RegFwd_i,
output [5-1:0] RegFwd_o
);
Latch #(.width(2)) EXMEM_MEM_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (MEM_ctrl_i),
.data_o (MEM_ctrl_o)
);
Latch #(.width(2)) EXMEM_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch EXMEM_ALU_output (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (ALU_output_i),
.data_o (ALU_output_o)
);
Latch EXMEM_ALU_data_2 (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (ALU_data_2_i),
.data_o (ALU_data_2_o)
);
Latch #(.width(5)) EXMEM_RegFwd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (RegFwd_i),
.data_o (RegFwd_o)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_SYMBOL_V
`define SKY130_FD_SC_LP__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops ) #pragma GCC target( avx,avx2,sse,sse2 ) using namespace std; using vi = vector<long long>; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); long long powmod(long long a, long long b, long long mod) { if (b == 0 || a == 1) { if (mod == 1) return 0; else return 1; } if (b % 2 == 0) { long long k = powmod(a, b / 2, mod); return (k * k) % mod; } else { long long k = powmod(a, b / 2, mod); return ((k * k) % mod * a) % mod; } } long long gcd(long long a, long long b) { if (a == 0) return b; if (b == 0) return a; if (a > b) return gcd(a % b, b); else return gcd(b % a, a); } long long prime(long long p) { if (p == 1) return 0; for (long long i = 2; i * i <= p; i++) { if (p % i == 0 && i < p) return i; } return 1; } long long inv(long long a, long long mod) { return powmod(a, mod - 2, mod); } long long random_modul() { uniform_int_distribution<long long> u1(1e9, 2e9); long long pepega = u1(rnd); while (prime(pepega) != 1) pepega = u1(rnd); return pepega; } template <typename T1> void ifmax(T1& max, T1 kek) { if (kek > max) max = kek; return; } template <typename T1> void ifmin(T1& min, T1 kek) { if (kek < min) min = kek; return; } template <typename T1> istream& operator>>(std::istream& in, pair<T1, T1>& a) { in >> a.first >> a.second; return in; } template <typename T1> istream& operator>>(std::istream& in, vector<T1>& a) { for (long long i = 0; i < a.size(); i++) in >> a[i]; return in; } template <typename T1> ostream& operator<<(std::ostream& out, vector<T1>& b) { for (long long i = 0; i < b.size(); i++) out << b[i]; return out; } template <typename T1> void sort(vector<T1>& m) { sort(m.begin(), m.end()); } template <typename T1> void reverse(vector<T1>& m) { reverse(m.begin(), m.end()); } long long mod = 1000000007; long long fac[200005]; long long inv_fac[200005]; long long co(long long a, long long b) { long long ans = 1; ans *= fac[b]; ans *= inv_fac[b - a]; ans %= mod; ans *= inv_fac[a]; return ans % mod; } void solve() { string a, b; cin >> a >> b; long long s1 = a.size(); long long s2 = b.size(); string ans; for (long long i = 1; i <= s1; i++) { for (long long j = 1; j <= s2; j++) { string cur = ; for (long long k = 0; k < i; k++) cur += a[k]; for (long long k = 0; k < j; k++) cur += b[k]; if (i == 1 && i == j) ans = cur; else ans = min(ans, cur); } } cout << ans; return; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(10); long long multitest = 0; long long tututu; tututu = 1; long long combinatorics = 0; if (combinatorics) { fac[1] = 1; fac[0] = 1; for (long long i = 2; i < 200005; i++) { fac[i] = fac[i - 1] * i; fac[i] %= mod; } for (long long i = 0; i < 200005; i++) { inv_fac[i] = inv(fac[i], mod); } } if (multitest) cin >> tututu; for (long long qwerty = 0; qwerty < tututu; qwerty++) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_4_V
`define SKY130_FD_SC_HS__FILL_DIODE_4_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_diode_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_diode_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_4_V
|
#include <bits/stdc++.h> using namespace std; using LL = long long; using LD = long double; void err() { cerr << 033[39;0m << endl; } template <typename T, typename... A> void err(T a, A... x) { cerr << a << ; err(x...); } const int N = 1e6 + 10; struct Node { map<int, Node*> link; Node* fa; int count; } pool[N]; int cnt; Node* new_node(Node* fa) { Node* ret = pool + cnt++; ret->fa = fa; ret->link.clear(); ret->count = 0; return ret; } int stk[N], top; int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; while (T--) { int n; cin >> n; top = 0; LL ans = 0; auto cur = new_node(nullptr); cur->count = 1; for (decay<decltype(n)>::type i = (0), _i = (n); i < _i; ++i) { int c; cin >> c; if (top == 0 || stk[top - 1] != c) { if (!cur->link[c]) { cur->link[c] = new_node(cur); } cur = cur->link[c]; ans += cur->count++; stk[top++] = c; } else { cur = cur->fa; ans += cur->count++; --top; } } cout << ans << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7, M = 1e6 + 7, fo = 1e6; template <class T> inline void read(T &re) { char ch; while ((ch = getchar()) < 0 || ch > 9 ) ; re = ch - 48; while ((ch = getchar()) >= 0 && ch <= 9 ) re = (re << 3) + (re << 1) + ch - 48; } int num[N], tim[N], fa[N], tot, hd[N]; long long f[N]; struct road { int to, nxt, val; } r[N]; struct TreeStructure { long long sum[M]; inline void update(int x, long long ad) { for (register int i = x; i <= fo; i += i & -i) sum[i] += ad; } inline long long query(int x) { long long ret = 0; for (register int i = x; i; i -= i & -i) ret += sum[i]; return ret; } } st, sc; inline void ade(int x, int y, int z) { r[++tot].to = y; r[tot].nxt = hd[x]; r[tot].val = z; hd[x] = tot; } inline void DpOnTree(int x, long long t) { st.update(tim[x], 1ll * tim[x] * num[x]); sc.update(tim[x], num[x]); int L = 0, R = fo, mid, ans; while (L <= R) { mid = (L + R) >> 1; if (st.query(mid) <= t) { ans = mid; L = mid + 1; } else R = mid - 1; } f[x] = sc.query(ans); if (ans != fo) f[x] += (t - st.query(ans)) / (ans + 1); long long mx = 0, mx2 = 0; for (register int i = hd[x], u; i; i = r[i].nxt) { u = r[i].to; if (t - 2 * r[i].val < 0) continue; DpOnTree(u, t - 2 * r[i].val); if (f[u] >= mx) mx2 = mx, mx = f[u]; else if (f[u] > mx2) mx2 = f[u]; } if (x != 1) f[x] = max(f[x], mx2); else f[x] = max(f[x], mx); st.update(tim[x], -1ll * tim[x] * num[x]); sc.update(tim[x], -num[x]); } int main() { int n, w; long long T; read(n); read(T); for (register int i = 1; i <= n; ++i) read(num[i]); for (register int i = 1; i <= n; ++i) read(tim[i]); for (register int i = 2; i <= n; ++i) { read(fa[i]); read(w); ade(fa[i], i, w); } DpOnTree(1, T); printf( %lld , f[1]); } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; void debug_out() { clog << n ; } template <typename H, typename... T> void debug_out(H head, T... tail) { clog << << head; debug_out(tail...); } template <typename T> ostream &operator<<(ostream &os, const vector<T> &vec) { for (auto &i : vec) os << i << ; return os; } template <typename T> ostream &operator<<(ostream &os, const vector<vector<T>> &vec) { if (!vec.empty()) os << vec[0]; for (size_t i = 1; i < vec.size(); ++i) os << n << vec[i]; return os; } template <typename T, typename U> ostream &operator<<(ostream &os, const pair<T, U> &p) { os << p.first << << p.second; return os; } template <typename T> ostream &operator<<(ostream &os, const set<T> &s) { for (auto &i : s) os << i << ; return os; } struct SegmentTree { int n; vector<int> mi; vector<int64_t> sum; vector<int> push_value; SegmentTree(int _n) : n(_n) { mi.resize(4 * n); sum.resize(4 * n); push_value.resize(4 * n); } void push(int v, int tl, int tr) { if (push_value[v]) { push_value[v * 2] = push_value[v * 2 + 1] = push_value[v]; int mid = tl + tr >> 1; mi[v * 2] = mi[v * 2 + 1] = push_value[v]; sum[v * 2] = 1LL * (mid - tl + 1) * push_value[v]; sum[v * 2 + 1] = 1LL * (tr - mid) * push_value[v]; push_value[v] = 0; } } void update(int l, int r, int val) { update(1, 0, n - 1, l, r, val); } void update(int v, int tl, int tr, int l, int r, int val) { if (l > r) return; if (tl == l && tr == r) { push_value[v] = val; sum[v] = 1LL * (r - l + 1) * val; mi[v] = val; } else { push(v, tl, tr); int mid = tl + tr >> 1; update(v * 2, tl, mid, l, min(mid, r), val); update(v * 2 + 1, mid + 1, tr, max(mid + 1, l), r, val); mi[v] = min(mi[v * 2], mi[v * 2 + 1]); sum[v] = sum[v * 2] + sum[v * 2 + 1]; } } int ask(int l, int r, int y) { return ask(1, 0, n - 1, l, r, y); } int ask(int v, int tl, int tr, int l, int r, int y) { if (mi[v] >= y || l > r) return -1; if (tl == tr) return tl; push(v, tl, tr); int mid = tl + tr >> 1; int ans = ask(v * 2, tl, mid, l, min(mid, r), y); if (ans == -1) ans = ask(v * 2 + 1, mid + 1, tr, max(mid + 1, l), r, y); return ans; } int query(int l, int r, int &y) { return query(1, 0, n - 1, l, r, y); } int query(int v, int tl, int tr, int l, int r, int &y) { if (mi[v] > y || l > r) return 0; if (tl == tr) return y -= sum[v], 1; if (tl == l && tr == r && y >= sum[v]) return y -= sum[v], (r - l + 1); push(v, tl, tr); int mid = tl + tr >> 1; int ans = query(v * 2, tl, mid, l, min(mid, r), y); ans += query(v * 2 + 1, mid + 1, tr, max(mid + 1, l), r, y); return ans; } int get_element(int pos) { return get_element(1, 0, n - 1, pos); } int get_element(int v, int tl, int tr, int pos) { if (tl == tr) return sum[v]; push(v, tl, tr); int mid = tl + tr >> 1; if (pos <= mid) return get_element(v * 2, tl, mid, pos); return get_element(v * 2 + 1, mid + 1, tr, pos); } void print_tree() { cout << { ; if (n) cout << get_element(1, 0, n - 1, 0); for (int i = 1; i < n; ++i) cout << , << get_element(1, 0, n - 1, i); cout << } n ; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; SegmentTree st(n); for (int i = 0; i < n; ++i) { int val; cin >> val; st.update(i, i, val); } while (q--) { int type, x, y; cin >> type >> x >> y; --x; if (type == 1) { int pos = st.ask(0, x, y); if (pos != -1) st.update(pos, x, y); } else { int ans = st.query(x, n - 1, y); cout << ans << n ; } } return 0; } |
/*
* master_rd_monitor.v
*
* Created on: 20.11.2016
* Author: Alexander Antonov <>
* License: See LICENSE file for details
*/
module master_rd_monitor
#(
parameter MNUM = 0
)
(
input clk_i,
input rst_i,
input master_req,
input [31:0] master_addr,
input master_cmd,
input [31:0] master_wdata,
input master_ack,
input [31:0] master_rdata,
input master_resp,
output rdreq_fifo_full
);
wire rdreq_fifo_empty;
wire [31:0] rdreq_fifo_rdata;
fifo
#(
.B(32),
.W(8)
) rdreq_fifo (
.clk(clk_i),
.reset(rst_i),
.rd(master_resp),
.wr(master_req & master_ack & !master_cmd),
.w_data(master_addr),
.empty(rdreq_fifo_empty),
.full(rdreq_fifo_full),
.r_data(rdreq_fifo_rdata)
);
integer trans_num;
always @(posedge clk_i)
begin
if (master_resp)
begin
trans_num <= trans_num + 1;
if (rdreq_fifo_empty) $fatal("Unexpected response in Master %d: 0x%x", MNUM, master_rdata);
else
begin
if (rdreq_fifo_rdata == master_rdata) $display("Response number %d received in Master %d - correct! Expected output: 0x%x, real output: 0x%x", trans_num, MNUM, rdreq_fifo_rdata, master_rdata);
else $fatal("Response received in Master %d - incorrect! Expected output: 0x%x, real output: 0x%x", MNUM, rdreq_fifo_rdata, master_rdata);
end
end
end
initial
begin
trans_num = 0;
end
endmodule
|
module ulight_fifo (
auto_start_external_connection_export,
clk_clk,
clock_sel_external_connection_export,
counter_rx_fifo_external_connection_export,
counter_tx_fifo_external_connection_export,
data_flag_rx_external_connection_export,
data_info_external_connection_export,
data_read_en_rx_external_connection_export,
fifo_empty_rx_status_external_connection_export,
fifo_empty_tx_status_external_connection_export,
fifo_full_rx_status_external_connection_export,
fifo_full_tx_status_external_connection_export,
fsm_info_external_connection_export,
led_pio_test_external_connection_export,
link_disable_external_connection_export,
link_start_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
pll_0_locked_export,
pll_0_outclk0_clk,
reset_reset_n,
timecode_ready_rx_external_connection_export,
timecode_rx_external_connection_export,
timecode_tx_data_external_connection_export,
timecode_tx_enable_external_connection_export,
timecode_tx_ready_external_connection_export,
write_data_fifo_tx_external_connection_export,
write_en_tx_external_connection_export);
output auto_start_external_connection_export;
input clk_clk;
output [2:0] clock_sel_external_connection_export;
input [5:0] counter_rx_fifo_external_connection_export;
input [5:0] counter_tx_fifo_external_connection_export;
input [8:0] data_flag_rx_external_connection_export;
input [13:0] data_info_external_connection_export;
output data_read_en_rx_external_connection_export;
input fifo_empty_rx_status_external_connection_export;
input fifo_empty_tx_status_external_connection_export;
input fifo_full_rx_status_external_connection_export;
input fifo_full_tx_status_external_connection_export;
input [5:0] fsm_info_external_connection_export;
output [4:0] led_pio_test_external_connection_export;
output link_disable_external_connection_export;
output link_start_external_connection_export;
output [12:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [7:0] memory_mem_dq;
inout memory_mem_dqs;
inout memory_mem_dqs_n;
output memory_mem_odt;
output memory_mem_dm;
input memory_oct_rzqin;
output pll_0_locked_export;
output pll_0_outclk0_clk;
input reset_reset_n;
input timecode_ready_rx_external_connection_export;
input [7:0] timecode_rx_external_connection_export;
output [7:0] timecode_tx_data_external_connection_export;
output timecode_tx_enable_external_connection_export;
input timecode_tx_ready_external_connection_export;
output [8:0] write_data_fifo_tx_external_connection_export;
output write_en_tx_external_connection_export;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; const long long INF = (long long)1e14 + 5; long long N, cur = 1, last = 0, ans[MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> N; for (int i = 1; i <= N; i += 2) { long long x; cin >> x; while (cur * cur <= INF) { long long l = last + 1, r = cur - 1, found = -1; while (l <= r) { long long m = (l + r) >> 1; if (cur * cur - m * m == x) { found = m; break; } else if (cur * cur - m * m > x) l = m + 1; else r = m - 1; } if (found != -1) { ans[i] = found * found - last * last; ans[i + 1] = x; last = cur; cur++; break; } cur++; } if (cur * cur > INF) { cout << No n ; return 0; } } cout << Yes n ; for (int i = 1; i <= N; i++) { cout << ans[i] << (i + 1 <= N ? : n ); } } |
module memory_writemask(/*AUTOARG*/
// Outputs
we,
// Inputs
write, datamode, addr
);
input write;
input [1:0] datamode;
input [2:0] addr;
output [7:0] we;
reg [7:0] we;
//Write mask
always@*
casez({write, datamode[1:0],addr[2:0]})
//Byte
6'b100000 : we[7:0] = 8'b00000001;
6'b100001 : we[7:0] = 8'b00000010;
6'b100010 : we[7:0] = 8'b00000100;
6'b100011 : we[7:0] = 8'b00001000;
6'b100100 : we[7:0] = 8'b00010000;
6'b100101 : we[7:0] = 8'b00100000;
6'b100110 : we[7:0] = 8'b01000000;
6'b100111 : we[7:0] = 8'b10000000;
//Short
6'b10100? : we[7:0] = 8'b00000011;
6'b10101? : we[7:0] = 8'b00001100;
6'b10110? : we[7:0] = 8'b00110000;
6'b10111? : we[7:0] = 8'b11000000;
//Word
6'b1100?? : we[7:0] = 8'b00001111;
6'b1101?? : we[7:0] = 8'b11110000;
//Double
6'b111??? : we[7:0] = 8'b11111111;
default : we[7:0] = 8'b00000000;
endcase // casez ({write, datamode[1:0],addr[2:0]})
endmodule // memory_writemask
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_TB_V
`define SKY130_FD_SC_HD__OR4BB_TB_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__or4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_TB_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//
//-------------------------------------------------------------------
//
// Filename : mc_ctrl.v
// Author : Yufeng Bai
// Email :
// Created On : 2015-01-19
//
//-------------------------------------------------------------------
//
// Modified : 2015-08-31 by HLL
// Description : mvd added
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_ctrl (
clk ,
rstn ,
mc_start_i ,
mc_done_o ,
mvd_access_o ,
chroma_start_o ,
chroma_sel_o ,
chroma_done_i ,
tq_start_o ,
tq_sel_o ,
tq_done_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] mc_start_i ; // mc start
output [1-1:0] mc_done_o ; // mc done
output mvd_access_o ;
output [1-1:0] chroma_start_o ; // chroma interpolation start
output [1-1:0] chroma_sel_o ; // chroma interpolation select: 0:cb, 1:cr
input [1-1:0] chroma_done_i ; // chroma interpolation done
output [1-1:0] tq_start_o ; // tq start
output [2-1:0] tq_sel_o ; // tq sel: 00:luma, 10:cb, 11:cr
input [1-1:0] tq_done_i ; // tq done
// ********************************************
//
// PARAMETER DECLARATION
//
// ********************************************
parameter IDLE = 3'd0;
parameter TQ_LUMA = 3'd1;
parameter MC_CB = 3'd2;
parameter TQ_CB = 3'd3;
parameter MC_CR = 3'd4;
parameter TQ_CR = 3'd5;
parameter DONE = 3'd6;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3-1:0] current_state, next_state;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always @(*) begin
next_state = IDLE;
case(current_state)
IDLE : begin
if ( mc_start_i)
next_state = TQ_LUMA;
else
next_state = IDLE;
end
TQ_LUMA: begin
if ( tq_done_i)
next_state = MC_CB;
else
next_state = TQ_LUMA;
end
MC_CB: begin
if ( chroma_done_i)
next_state = TQ_CB;
else
next_state = MC_CB;
end
TQ_CB: begin
if ( tq_done_i)
next_state = MC_CR;
else
next_state = TQ_CB;
end
MC_CR: begin
if ( chroma_done_i)
next_state = TQ_CR;
else
next_state = MC_CR;
end
TQ_CR: begin
if ( tq_done_i)
next_state = DONE;
else
next_state = TQ_CR;
end
DONE: begin
next_state = IDLE;
end
endcase
end
assign mc_done_o = (current_state == DONE);
assign chroma_start_o = (current_state == TQ_LUMA && next_state == MC_CB) ||
(current_state == TQ_CB && next_state == MC_CR) ;
assign chroma_sel_o = (current_state == MC_CR) ? 1'b1 : 1'b0;
assign tq_start_o = (current_state == IDLE && next_state == TQ_LUMA)||
(current_state == MC_CB && next_state == TQ_CB) ||
(current_state == MC_CR && next_state == TQ_CR) ;
assign tq_sel_o = (current_state == TQ_LUMA) ? 2'b00 :
(current_state == TQ_CB ) ? 2'b10 :
(current_state == TQ_CR ) ? 2'b11 : 2'b00;
assign mvd_access_o = ( current_state == TQ_LUMA );
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
current_state <= IDLE;
end
else begin
current_state <= next_state;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, h, p[N], q[N], bit[N]; void update(int x, int v) { for (; x < n; x += (x + 1) & -(x + 1)) bit[x] += v; } int sum(int x) { int res = 0; for (; x >= 0; x -= (x + 1) & -(x + 1)) res += bit[x]; return res; } void solve() { fill(bit, bit + n, 0); for (int i = n - 1; i >= 0; i--) { int x = sum(p[i] - 1); update(p[i], 1); p[i] = x; } fill(bit, bit + n, 0); for (int i = n - 1; i >= 0; i--) { int x = sum(q[i] - 1); update(q[i], 1); q[i] = x; } for (int i = n - 1; i >= 0; i--) { int c = (p[i] + q[i]) / (n - i); p[i] = (p[i] + q[i]) % (n - i); if (i > 0) { p[i - 1] += c; } } fill(bit, bit + n, 0); for (int i = 0; i < n; i++) update(i, 1); for (int i = 0; i < n; i++) { if (i) printf( ); int lo = 0, hi = n; while (lo < hi) { int m = lo + (hi - lo) / 2; if (p[i] + 1 <= sum(m)) hi = m; else lo = m + 1; } printf( %d , lo); update(lo, -1); } printf( n ); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , p + i); for (int i = 0; i < n; i++) scanf( %d , q + i); solve(); return 0; } |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; using namespace std; const double eps = 1e-6; const long long mod = 1e9 + 7; const int maxn = 1e5 + 100; const int maxe = 1e6 + 100; struct node { int to; int next; }; bool dp[maxn][2], cir; vector<int> V[maxn]; int vis[maxn][2]; int Next[maxn][2], n, m; inline bool dfs(int x, int s) { if (!V[x].size()) return s == 1; if (vis[x][s] == 2) return dp[x][s]; vis[x][s] = 1; bool t = 0; for (int i = 0; i < V[x].size(); i++) { int v = V[x][i]; if (vis[v][s ^ 1] == 1) { cir = 1; continue; } if (dfs(v, s ^ 1)) { t = 1; Next[x][s] = v; } } vis[x][s] = 2; return dp[x][s] = t; } inline void print(int x, int s) { printf( %d , x); if (Next[x][s]) { print(Next[x][s], s ^ 1); } } void Solve() { cin >> n >> m; int xx, v; for (int i = 1; i <= n; i++) { cin >> xx; for (int j = 0; j < xx; j++) { cin >> v; V[i].push_back(v); } } int st; cin >> st; if (dfs(st, 0)) { puts( Win ); print(st, 0); } else if (cir) puts( Draw ); else puts( Lose ); } int main() { int Case = 1, cases; while (Case--) { Solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(T x) { return x * x; } const double EPS = 1e-9; const int INF = 1000 * 1000 * 1000; const long long LINF = INF * 1ll * INF; const double DINF = 1e200; const double PI = 3.1415926535897932384626433832795l; int gcd(int a, int b) { return a ? gcd(b % a, a) : b; } long long gcd(long long a, long long b) { return a ? gcd(b % a, a) : b; } long long gcdex(long long a, long long b, long long &x, long long &y) { if (!a) { x = 0, y = 1; return b; } long long k = b / a; long long g = gcdex(b - k * a, a, y, x); x -= k * y; return g; } long long inv(long long a, long long m) { assert(m > 1); long long x, y, g; g = gcdex(a, m, x, y); return (x % (m / g) + m / g) % m / g; } long long crt(long long a1, long long m1, long long a2, long long m2) { long long a = (a2 - a1 % m2 + m2) % m2; long long x, y, g; g = gcdex(m1, m2, x, y); if (a % g) return -1; long long m = m1 / g * m2; assert(x + m2 >= 0); x = a / g * (x + m2) % m2; long long r = (a1 + x * m1) % m; assert(r % m1 == a1 && r % m2 == a2); return r; } long long powmod(long long a, long long p, long long m) { assert(p >= 0); long long r = 1; while (p) { if (p & 1) r = r * a % m; p >>= 1; a = a * a % m; } return r; } bool isprime(long long a) { if (a <= 1) return false; for (long long i = 2; i * i <= a; ++i) { if (a % i == 0) return false; } return true; } long long sqrtup(long long a) { if (!a) return 0; long long x = max(0ll, (long long)sqrt((double)a)); while (x * x >= a) --x; while ((x + 1) * (x + 1) < a) ++x; return x + 1; } long long isqrt(long long a) { if (a <= 0) { assert(!a); return 0; } long long x = (long long)sqrt((double)a); while (sqr(x + 1) <= a) ++x; while (x * x > a) --x; return x; } long long sgn(long long x) { return x < 0 ? -1 : x > 0 ? 1 : 0; } double randf() { double m = RAND_MAX + 1.; return (((rand() + .5) / m + rand()) / m + rand()) / m; } int rand30() { assert(RAND_MAX >= (1 << 15) - 1); return ( int)((((uint32_t)rand()) * (1u + (uint32_t)RAND_MAX) + (uint32_t)rand()) & ((1u << 30) - 1)); } template <class T> void smin(T &a, T b) { a = min(a, b); } template <class T> void smax(T &a, T b) { a = max(a, b); } template <class T> ostream &operator<<(ostream &s, const vector<T> &v); template <class A, class B> ostream &operator<<(ostream &s, const pair<A, B> &p); template <class K, class V> ostream &operator<<(ostream &s, const map<K, V> &m); template <class T> ostream &operator<<(ostream &s, const set<T> &m); template <class T, size_t N> ostream &operator<<(ostream &s, const array<T, N> &a); template <class... T> ostream &operator<<(ostream &s, const tuple<T...> &t); template <class T> ostream &operator<<(ostream &s, const vector<T> &v) { s << [ ; for (int i = 0; i < (((int)(v).size())); ++i) { if (i) s << , ; s << v[i]; } s << ] ; return s; } template <class A, class B> ostream &operator<<(ostream &s, const pair<A, B> &p) { s << ( << p.first << , << p.second << ) ; return s; } template <class K, class V> ostream &operator<<(ostream &s, const map<K, V> &m) { s << { ; bool f = false; for (const auto &it : m) { if (f) s << , ; f = true; s << it.first << : << it.second; } s << } ; return s; } template <class T> ostream &operator<<(ostream &s, const set<T> &m) { s << { ; bool f = false; for (const auto &it : m) { if (f) s << , ; f = true; s << it; } s << } ; return s; } template <class T> ostream &operator<<(ostream &s, const multiset<T> &m) { s << { ; bool f = false; for (const auto &it : m) { if (f) s << , ; f = true; s << it; } s << } ; return s; } template <class T, class V, class C> ostream &operator<<(ostream &s, const priority_queue<T, V, C> &q) { auto a = q; s << { ; bool f = false; while (!a.empty()) { if (f) s << , ; f = true; s << a.top(); a.pop(); } return s << } ; } template <class T, size_t N> ostream &operator<<(ostream &s, const array<T, N> &a) { s << [ ; for (int i = 0; i < (((int)(a).size())); ++i) { if (i) s << , ; s << a[i]; } s << ] ; return s; } template <class T> ostream &operator<<(ostream &s, const deque<T> &a) { s << [ ; for (int i = 0; i < (((int)(a).size())); ++i) { if (i) s << , ; s << a[i]; } s << ] ; return s; } template <size_t n, class... T> struct put1 { static ostream &put(ostream &s, const tuple<T...> &t) { s << get<sizeof...(T) - n>(t); if (n > 1) s << , ; return put1<n - 1, T...>::put(s, t); } }; template <class... T> struct put1<0, T...> { static ostream &put(ostream &s, const tuple<T...> &t) { return s; } }; template <class... T> ostream &operator<<(ostream &s, const tuple<T...> &t) { s << ( ; put1<sizeof...(T), T...>::put(s, t); s << ) ; return s; } ostream &put3(ostream &s, const char *, bool) { return s; } template <class U, class... T> ostream &put3(ostream &s, const char *f, bool fs, U &&u, T &&...t) { while (*f == ) ++f; if (!fs) s << , ; auto nf = f; int d = 0; while (*nf && (*nf != , || d)) { if (*nf == ( ) ++d; else if (*nf == ) ) --d; ++nf; } auto nf2 = nf; while (nf2 > f && *(nf2 - 1) == ) --nf; fs = *f == ; if (!fs) { s.write(f, nf2 - f); s << = ; }; s << u; if (fs) s << ; if (*nf) ++nf; return put3(s, nf, fs, forward<T>(t)...); } mt19937 mtrng; struct comp { vector<int> V; vector<pair<int, int>> E; }; struct tree { vector<pair<int, int>> T; tree(int n) : T(n * 4) {} void init(int a, int b, int k, const vector<int> &A) { if (b == a + 1) { T[k] = make_pair(A[a], a); return; } int c = (a + b) / 2; init(a, c, k * 2 + 1, A); init(c, b, k * 2 + 2, A); T[k] = max(T[k * 2 + 1], T[k * 2 + 2]); } pair<int, int> getmax(int l, int r, int a, int b, int k) { if (l >= b || r <= a) return make_pair(0, -1); if (l <= a && r >= b) return T[k]; int c = (a + b) / 2; return max(getmax(l, r, a, c, k * 2 + 1), getmax(l, r, c, b, k * 2 + 2)); } void setv(int p, int v, int a, int b, int k) { if (b == a + 1) { T[k] = make_pair(v, p); return; } int c = (a + b) / 2; if (p < c) setv(p, v, a, c, k * 2 + 1); else setv(p, v, c, b, k * 2 + 2); T[k] = max(T[k * 2 + 1], T[k * 2 + 2]); } }; int main(int argc, char **argv) { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(20); srand(35964); mtrng.seed(765674737); int n, m, tc; cin >> n >> m >> tc; vector<int> P; P.resize(n); for (int i = 0; i < (n); ++i) cin >> P[i]; vector<pair<pair<int, int>, int>> E(m); for (int i = 0; i < (m); ++i) { cin >> E[i].first.first >> E[i].first.second; --E[i].first.first; --E[i].first.second; } vector<pair<int, int>> Q(tc); for (int i = 0; i < (tc); ++i) { cin >> Q[i].first >> Q[i].second; --Q[i].second; if (Q[i].first == 2) E[Q[i].second].second = 1; } vector<int> v2c(n); vector<comp> cs(n); for (int i = 0; i < (n); ++i) { v2c[i] = i; cs[i].V.push_back(i); } auto mer = [&](int a, int b, int q) { if (a == b) return; if (((int)(cs[a].V).size()) < ((int)(cs[b].V).size())) swap(a, b); for (pair<int, int> x : cs[b].E) cs[a].E.push_back(make_pair(x.first, x.second + ((int)(cs[a].V).size()))); if (q != -1) cs[a].E.push_back(make_pair(q, ((int)(cs[a].V).size()))); for (int v : cs[b].V) { v2c[v] = a; cs[a].V.push_back(v); } cs[b].V.clear(); cs[b].E.clear(); }; for (auto e : E) { if (e.second) continue; mer(v2c[e.first.first], v2c[e.first.second], -1); } for (int q = tc - 1; q >= 0; --q) { if (Q[q].first != 2) continue; pair<int, int> e = E[Q[q].second].first; int a = v2c[e.first], b = v2c[e.second]; mer(a, b, q); } set<int> B; vector<int> v2i(n); vector<int> i2v; vector<pair<int, int>> ev; B.insert(0); for (comp &c : cs) { if (!((int)(c.V).size())) continue; for (pair<int, int> e : c.E) ev.push_back(make_pair(e.first, e.second + ((int)(i2v).size()))); for (int v : c.V) { v2i[v] = ((int)(i2v).size()); i2v.push_back(v); } B.insert(((int)(i2v).size())); } assert(((int)(i2v).size()) == n); sort((ev).begin(), (ev).end()); tree T(n); vector<int> A(n); for (int i = 0; i < (n); ++i) A[i] = P[i2v[i]]; T.init(0, n, 0, A); int ei = 0; for (int q = 0; q < (tc); ++q) { if (Q[q].first == 1) { int i = v2i[Q[q].second]; auto it = B.upper_bound(i); int b = *it; --it; int a = *it; pair<int, int> t = T.getmax(a, b, 0, n, 0); T.setv(t.second, 0, 0, n, 0); cout << t.first << n ; } else if (ei < ((int)(ev).size()) && ev[ei].first == q) { B.insert(ev[ei].second); ++ei; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRTP_PP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module t_block_memory;
// Inputs
reg clock;
reg reset;
reg enable;
reg [4:0] row1;
reg [4:0] row2;
reg [4:0] col1;
reg [4:0] col2;
reg [1:0] func;
reg [1:0] stage;
// Outputs
wire [2:0] block1;
wire [2:0] block2;
wire busy;
// Instantiate the Unit Under Test (UUT)
block_memory uut (
.clock(clock),
.reset(reset),
.enable(enable),
.row1(row1),
.row2(row2),
.col1(col1),
.col2(col2),
.func(func),
.stage(stage),
.block1(block1),
.block2(block2),
.busy(busy)
);
always #1 clock = ~clock;
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
enable = 0;
row1 = 0;
row2 = 0;
col1 = 0;
col2 = 0;
func = 0;
stage = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
#10;
reset = 0;
#10;
// Load stage testing.
enable = 1;
func = 1;
#10;
enable = 0;
func = 0;
#200;
// Clear testing.
col1 = 8;
row1 = 8;
enable = 1;
func = 0;
#10;
// Drop testing.
enable = 1;
func = 2;
#10
enable = 0;
#100;
func = 3;
enable = 1;
#10;
enable = 0;
#200;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND4_BEHAVIORAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSHOLD_PP_BLACKBOX_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold (
X ,
RESET,
VPWR ,
VGND ,
VPB ,
VNB
);
inout X ;
input RESET;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_PP_BLACKBOX_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; inline void read(int &num) { num = 0; char ch; int flag = 1; while ((ch = getchar()) < 0 || ch > 9 ) if (ch == - ) flag *= -1; while (ch >= 0 && ch <= 9 ) num = num * 10 + ch - 0 , ch = getchar(); num *= flag; } const int MAXN = 200005; int n, num[MAXN], v[MAXN], st[MAXN], tot; long long ans; bool vis[MAXN], had[MAXN]; void dfs(int u) { if (vis[u]) { int mn = 0x7f7f7f7f; do { mn = min(mn, num[st[tot]]); had[st[tot]] = 1; } while (st[tot--] != u); ans += mn; return; } vis[u] = 1; st[++tot] = u; if (had[v[u]]) { had[u] = 1; return; } dfs(v[u]); had[u] |= had[v[u]]; } int main() { read(n); for (int i = 1; i <= n; i++) scanf( %d , &num[i]); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); for (int i = 1; i <= n; i++) if (!vis[i]) dfs(i); printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; template <typename T> void chkmax(T &x, T y) { x = x > y ? x : y; } template <typename T> void chkmin(T &x, T y) { x = x > y ? y : x; } template <typename T> void update(T &x, T y, T mod) { x = x + y > mod ? x + y - mod : x + y; } template <typename T> void multi(T &x, T y, T mod) { x = 1ll * x * y % mod; } const int INF = (1ll << 30); template <typename T> void read(T &x) { x = 0; bool f = 1; char ch; do { ch = getchar(); if (ch == - ) f = 0; } while (ch > 9 || ch < 0 ); do { x = x * 10 + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); x = f ? x : -x; } template <typename T> void write(T x) { if (x < 0) x = ~x + 1, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } const int N = 1e5 + 7; struct Segment_Tree { int l, r, sum, rem, mul, fac[20]; } t[N << 2]; int n, m, mod, cnt, tot, phi, a[N], P[N], tmp[N], prime[N]; bool vis[N]; inline int calc(int x) { for (int i = 1; i <= tot; i++) { tmp[i] = 0; while (x % P[i] == 0) { x /= P[i]; tmp[i]++; } } return x; } inline int qpow(int a, int b) { long long ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % mod; a = 1ll * a * a % mod; b >>= 1; } return ret % mod; } inline void mul(int p, int mul, int rem, int *tmp) { multi(t[p].rem, rem, mod); for (int i = 1; i <= tot; i++) t[p].fac[i] += tmp[i]; multi(t[p].sum, mul, mod); multi(t[p].mul, mul, mod); } inline void divide(int p, int y, int *tmp) { multi(t[p].rem, qpow(y, phi - 1), mod); int tp = t[p].rem; for (int i = 1; i <= tot; i++) { t[p].fac[i] -= tmp[i]; multi(tp, qpow(P[i], t[p].fac[i]), mod); } t[p].sum = tp % mod; } inline void pushdown(int p) { if (t[p].mul != 1 || t[p].rem != 1) { mul((p << 1), t[p].mul, t[p].rem, t[p].fac); mul((p << 1 | 1), t[p].mul, t[p].rem, t[p].fac); t[p].mul = t[p].rem = 1; for (int i = 1; i <= tot; i++) t[p].fac[i] = 0; } } inline void build(int p, int l, int r) { t[p].l = l; t[p].r = r; t[p].mul = t[p].rem = 1; if (l == r) { t[p].sum = a[l] % mod; t[p].rem = calc(a[l]); for (int i = 1; i <= tot; i++) t[p].fac[i] = tmp[i]; return; } pushdown(p); int mid = (t[p].l + t[p].r) >> 1; build((p << 1), l, mid); build((p << 1 | 1), mid + 1, r); t[p].sum = (t[(p << 1)].sum + t[(p << 1 | 1)].sum) % mod; } inline void multi(int p, int l, int r, int x, int k, int *tmp) { if (l <= t[p].l && t[p].r <= r) { mul(p, k, x, tmp); return; } pushdown(p); int mid = (t[p].l + t[p].r) >> 1; if (l <= mid) multi((p << 1), l, r, x, k, tmp); if (r > mid) multi((p << 1 | 1), l, r, x, k, tmp); t[p].sum = (t[(p << 1)].sum + t[(p << 1 | 1)].sum) % mod; } inline void divide(int p, int x, int y, int *tmp) { if (t[p].l == t[p].r) { divide(p, y, tmp); return; } pushdown(p); int mid = (t[p].l + t[p].r) >> 1; if (x <= mid) divide((p << 1), x, y, tmp); else divide((p << 1 | 1), x, y, tmp); t[p].sum = (t[(p << 1)].sum + t[(p << 1 | 1)].sum) % mod; } inline int query(int p, int l, int r) { if (l <= t[p].l && t[p].r <= r) return t[p].sum; pushdown(p); int mid = (t[p].l + t[p].r) >> 1, ans = 0; if (l <= mid) update(ans, query((p << 1), l, r), mod); if (r > mid) update(ans, query((p << 1 | 1), l, r), mod); return ans; } inline void init(int NN) { for (int i = 2; i <= NN; i++) { if (!vis[i]) { prime[++cnt] = i; } for (int j = 1; j <= cnt && prime[j] * i <= NN; j++) { vis[i * prime[j]] = true; if (i % prime[j] == 0) break; } } } inline int getphi(int x) { int ans = x; for (int i = 1; i <= cnt && prime[i] * prime[i] <= x; i++) { if (x % prime[i] == 0) { ans = 1ll * ans * (prime[i] - 1) / prime[i]; while (x % prime[i] == 0) x /= prime[i]; } } if (x != 1) ans = 1ll * ans * (x - 1) / x; return ans; } inline void divide(int x) { for (int i = 1; i <= cnt && prime[i] * prime[i] <= x; i++) { if (x % prime[i] == 0) { while (x % prime[i] == 0) x /= prime[i]; P[++tot] = prime[i]; } } if (x != 1) P[++tot] = x; } int main() { read(n); read(mod); init(1e5); divide(mod); phi = getphi(mod); for (int i = 1; i <= n; i++) read(a[i]); build(1, 1, n); read(m); for (int i = 1, opt, l, r, x; i <= m; i++) { read(opt); if (opt == 1) { read(l); read(r); read(x); multi(1, l, r, calc(x), x, tmp); } if (opt == 2) { read(l); read(x); divide(1, l, calc(x), tmp); } if (opt == 3) { read(l); read(r); printf( %d n , query(1, l, r) % mod); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int dir_4[4][2] = {{1, 0}, {0, 1}, {-1, 0}, {0, -1}}; const int dir_8[8][2] = {{1, 0}, {1, 1}, {0, 1}, {-1, 1}, {-1, 0}, {-1, -1}, {0, -1}, {1, -1}}; int par[200010], r[200010], lar[200010]; void init() { for (int i = 0; i < 200010; i++) { par[i] = i; r[i] = 0; lar[i] = 1; } } int find(int x) { if (par[x] == x) return x; return par[x] = find(par[x]); } bool same(int x, int y) { return find(x) == find(y); } void unit(int x, int y) { if (same(x, y)) return; x = find(x); y = find(y); if (r[x] < r[y]) { par[x] = y; lar[y] += lar[x]; } else { par[y] = x; lar[x] += lar[y]; if (r[x] == r[y]) { r[x]++; } } } int main() { static int n; static int a[200010]; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } init(); bool used[200010]; for (int i = 0; i < 200010; i++) { used[i] = false; } vector<pair<int, int> > vec; for (int i = 1; i <= n; i++) { vec.push_back(pair<int, int>(a[i], i)); } sort(vec.begin(), vec.end()); reverse(vec.begin(), vec.end()); int ans[200010]; int k = 1; for (int i = 0; i < vec.size(); i++) { pair<int, int> p = vec[i]; used[p.second] = true; if (used[p.second - 1]) { unit(p.second, p.second - 1); } if (used[p.second + 1]) { unit(p.second, p.second + 1); } for (; k <= lar[find(p.second)]; k++) { ans[k] = p.first; } } for (int i = 1; i <= n; i++) { printf( %d , ans[i]); } puts( ); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, M = 1e9 + 7; int n, a[N]; long long bigmod(long long b, long long p) { long long t = 1; for (; p; b = (b * b) % M, p >>= 1) if (p & 1) t = (t * b) % M; return t; } long long go(int now) { vector<int> div; for (int i = 1; i * i <= now; i++) { if (now % i == 0) { div.push_back(i); if (i * i != now) div.push_back(now / i); } } div.push_back(N); sort(div.begin(), div.end()); long long last = 1, cur = 1; for (int i = 0; i < div.size() - 1; i++) { int x = lower_bound(a, a + n, div[i]) - a; int y = lower_bound(a, a + n, div[i + 1]) - a; long long tmp = bigmod(i + 1, y - x); cur *= tmp; cur %= M; } int sz = div.size() - 2; div[sz] = N; for (int i = 0; i < div.size() - 2; i++) { int x = lower_bound(a, a + n, div[i]) - a; int y = lower_bound(a, a + n, div[i + 1]) - a; long long tmp = bigmod(i + 1, y - x); last *= tmp; last %= M; } return (cur - last + M) % M; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 1; for (int i = 1; i < N; i++) { ans += go(i); ans %= M; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100005]; int ans[100005]; string s[100005]; map<string, int> h; vector<pair<int, int> > v; string res[6] = { S , M , L , XL , XXL , XXXL }; int main() { memset(ans, -1, sizeof(ans)); ios_base::sync_with_stdio(false); cin.tie(NULL); h[ S ] = 0; h[ M ] = 1; h[ L ] = 2; h[ XL ] = 3; h[ XXL ] = 4; h[ XXXL ] = 5; for (int i = 0; i < 6; i++) cin >> a[i]; int n; cin >> n; bool ok = 1; for (int i = 1; i <= n; i++) { cin >> s[i]; string t[2]; t[0] = ; t[1] = ; int k = 0; int m = s[i].length(); for (int j = 0; j < m; j++) { if (s[i][j] == , ) k++; else t[k] += s[i][j]; } if (t[1] == ) { ans[i] = h[t[0]]; a[h[t[0]]]--; if (a[h[t[0]]] < 0) ok = 0; } else v.push_back(pair<int, int>(h[t[0]], i)); } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { int j = v[i].second, x = v[i].first; if (a[x] > 0) ans[j] = x, a[x]--; else ans[j] = x + 1, a[x + 1]--; } for (int i = 0; i < 6; i++) if (a[i] < 0) ok = 0; if (!ok) printf( NO n ); else { cout << YES << n ; for (int i = 1; i <= n; i++) cout << res[ans[i]] << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:54:08 01/30/2016
// Design Name:
// Module Name: alu_control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu_control(
input [5:0] ALUOp,
input [5:0] funct,
output wire [3:0] ALUcontrolOut
);
assign ALUcontrolOut = (ALUOp == 6'b000100) ? 4'b0001 : //SUB para BEQ
(ALUOp == 6'b000101) ? 4'b0001 : //SUB para BNE
(ALUOp == 6'b001000) ? 4'b0000 : //ADDI
(ALUOp == 6'b001010) ? 4'b0110 : //SLTI
(ALUOp == 6'b001100) ? 4'b0010 : //ANDI
(ALUOp == 6'b001101) ? 4'b0011 : //ORI
(ALUOp == 6'b001110) ? 4'b0100 : //XORI
(ALUOp == 6'b001111) ? 4'b1101 : //LUI
(ALUOp == 6'b100000) ? 4'b0000 : //ADD para LB
(ALUOp == 6'b100001) ? 4'b0000 : //ADD para LH
(ALUOp == 6'b100011) ? 4'b0000 : //ADD para LW
(ALUOp == 6'b100100) ? 4'b0000 : //ADD para LBU
(ALUOp == 6'b100101) ? 4'b0000 : //ADD para LHU
(ALUOp == 6'b100111) ? 4'b0000 : //ADD para LWU
(ALUOp == 6'b101000) ? 4'b0000 : //ADD para SB
(ALUOp == 6'b101001) ? 4'b0000 : //ADD para SH
(ALUOp == 6'b101011) ? 4'b0000 : //ADD para SW
(ALUOp == 6'b000011) ? 4'b0000 : //ADD para JAL
( (funct == 6'b100000) ? 4'b0000 : //ADD
(funct == 6'b100010) ? 4'b0001 : //SUB
(funct == 6'b100100) ? 4'b0010 : //AND
(funct == 6'b100101) ? 4'b0011 : //OR
(funct == 6'b100110) ? 4'b0100 : //XOR
(funct == 6'b100111) ? 4'b0101 : //NOR
(funct == 6'b101010) ? 4'b0110 : //SLT
(funct == 6'b000000) ? 4'b0111 : //SLL
(funct == 6'b000010) ? 4'b1000 : //SRL
(funct == 6'b000011) ? 4'b1001 : //SRA
(funct == 6'b000100) ? 4'b1010 : //SLLV
(funct == 6'b000110) ? 4'b1011 : //SRLV
(funct == 6'b000111) ? 4'b1100 : //SRAV
(funct == 6'b001001) ? 4'b0000 : //ADD para JALR
4'b1111); // --> Para identificar errores
endmodule |
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