text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; long long pwr(long long base, long long p, long long mod = (1000000007LL)) { long long ans = 1; while (p) { if (p & 1) ans = (ans * base) % mod; base = (base * base) % mod; p /= 2; } return ans; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long nCr(long long n, long long r) { long long C[r + 1]; memset(C, 0, sizeof(C)); C[0] = 1; for (long long i = 1; i <= n; i++) for (long long j = min(i, r); j > 0; j--) C[j] = C[j] + C[j - 1]; return C[r]; } bool isPrime(long long n) { if (n <= 1) return false; if (n == 2) return true; if (n % 2 == 0) return false; long long m = sqrt(n); for (long long i = 3; i <= m; i += 2) if (n % i == 0) return false; return true; } long long M(long long a) { return (a % (1000000007LL)); } bool isPowerOfTwo(long long x) { return x && (!(x & (x - 1))); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); int n; cin >> n; vector<int> v(n); for (long long i = 0; i < (long long)(n); ++i) cin >> v[i]; vector<int> ans(n + 1); for (long long i = 0; i < (long long)(n); ++i) { vector<int> color_total(n + 1); int best = 0; for (int j = i; j < n; j++) { color_total[v[j]]++; if (color_total[v[j]] > color_total[best]) { best = v[j]; } else if (color_total[v[j]] == color_total[best]) { if (v[j] < best) { best = v[j]; } } ans[best]++; } } for (long long i = 1; i <= (long long)(n); ++i) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long min(long long a, long long b) { if (a < b) return a; else return b; } static long long gcd(long long a, long long b) { long long r; while (b != 0) { r = a % b; a = b; b = r; } return a; } long long lcm(long long a, long long b) { long long temp = gcd(a, b); return temp ? (a / temp * b) : 0; } int solve() { long long n; cin >> n; long long k; cin >> k; long long maxans = (n * (n - 1)) / 2LL; if (k > maxans) { cout << Impossible ; return 0; } long long cnt = 0; long long tmp; for (long long i = 1; i <= n; i++) { if (((i * (i - 1)) / 2LL) <= k) { tmp = i; } else { break; } } long long open = tmp; cnt = open; k = k - ((tmp * (tmp - 1)) / 2LL); string s; for (int i = 0; i < open; i++) { s.push_back( ( ); } if (open >= 1) { s.push_back( ) ); open--; } while (k > 0 && open > 0 && cnt <= n) { if (open <= k) { s.push_back( ( ); s.push_back( ) ); cnt++; k = k - open; } else { open--; s.push_back( ) ); } } if (k == 0 && cnt <= n) { for (int i = 0; i < open; i++) { s.push_back( ) ); } for (int i = 0; i < (n - cnt); i++) { s.push_back( ( ); s.push_back( ) ); } cout << s; return 0; } else { cout << Impossible ; return 0; } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:31:14 05/03/2016
// Design Name:
// Module Name: uart_rx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_uart_rx8to8(
clk,
rst_n,
uart_ctl,
rs_rx,
data_in,
data_sign
);
input clk;
input rst_n;
input [2:0] uart_ctl;
input rs_rx;
output [7:0] data_in;
output data_sign;
parameter bps9600_2 = 13'd2604,
bps19200_2 = 13'd1301,
bps38400_2 = 13'd650,
bps57600_2 = 13'd433,
bps115200_2 = 13'd217,
bps256000_2 = 13'd97;
parameter IDLE = 2'b01,
TRAN = 2'b10;
reg [1:0] state;
reg bps_sel, sign_sel;
reg [12:0] cnt;
reg [4:0] tran_cnt;
reg [7:0] data_in;
reg data_sign;
wire recv_comp;
assign recv_comp = (tran_cnt == 19 && bps_sel);
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
state <= IDLE;
end
else begin
case(state)
IDLE : state <= ~rs_rx ? TRAN : IDLE;
TRAN : state <= recv_comp ? IDLE : TRAN;
default: state <= IDLE;
endcase
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bps_sel <= 1'b0;
sign_sel <= 1'b0;
cnt <= 'h0;
tran_cnt <= 'h0;
end
else begin
if(state == TRAN ) begin
case(uart_ctl)
3'h0: if(cnt == bps9600_2) begin
cnt <= 'h0;
bps_sel <= ~sign_sel;
sign_sel <= ~sign_sel;
tran_cnt <= tran_cnt + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
bps_sel <= 1'b0;
end
3'h1: if(cnt == bps19200_2) begin
cnt <= 'h0;
bps_sel <= ~sign_sel;
sign_sel <= ~sign_sel;
tran_cnt <= tran_cnt + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
bps_sel <= 1'b0;
end
3'h2: if(cnt == bps38400_2) begin
cnt <= 'h0;
bps_sel <= ~sign_sel;
sign_sel <= ~sign_sel;
tran_cnt <= tran_cnt + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
bps_sel <= 1'b0;
end
3'h3: if(cnt == bps57600_2) begin
cnt <= 'h0;
bps_sel <= ~sign_sel;
sign_sel <= ~sign_sel;
tran_cnt <= tran_cnt + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
bps_sel <= 1'b0;
end
3'h4: if(cnt == bps115200_2) begin
cnt <= 'h0;
bps_sel <= ~sign_sel;
sign_sel <= ~sign_sel;
tran_cnt <= tran_cnt + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
bps_sel <= 1'b0; end
3'h5: if(cnt == bps256000_2) begin
cnt <= 'h0;
bps_sel <= ~sign_sel;
sign_sel <= ~sign_sel;
tran_cnt <= tran_cnt + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
bps_sel <= 1'b0;
end
default: begin
cnt <= 'h0;
tran_cnt <= 0;
bps_sel <= 'h0;
sign_sel <= 'h0;
end
endcase
end
else begin
cnt <= 'h0;
sign_sel <= 'h0;
bps_sel <= 1'b0;
tran_cnt <= 'h0;
bps_sel <= 1'b0;
end
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_in <= 'h0;
data_sign <= 'h0;
end
else begin
if(bps_sel)begin
if(tran_cnt > 2 && tran_cnt <= 18) data_in[tran_cnt[4:1] - 1] <= rs_rx;
data_sign <= (tran_cnt == 19 ) ? 1'b1 : 1'b0;
end
else data_sign <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; map<int, int> num; int main() { cin >> n; int minNum = 1000 * 1000 * 1000 + 1; for (int i = 0; i < n; i++) { int tmp; cin >> tmp; num[tmp]++; minNum = min(minNum, tmp); } for (int i = minNum; n > 0; i++) { if (num[i] == 0 || num[i] > num[i + 1]) { cout << NO << endl; return 0; } num[i + 1] -= num[i]; n -= 2 * num[i]; } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1100; char str[N]; int G[N][N]; int sum_r[N], sum_c[N]; int n, m; bool vis[N][N]; bool no() { int r0 = n, c0 = m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { sum_r[i] += G[i][j]; } if (sum_r[i]) r0--; } for (int j = 1; j <= m; j++) { for (int i = 1; i <= n; i++) { sum_c[j] += G[i][j]; } if (sum_c[j]) c0--; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (G[i][j]) { int k = j; while (k <= m && G[i][k]) k++; if (k - j != sum_r[i]) return true; break; } } } for (int j = 1; j <= m; j++) { for (int i = 1; i <= n; i++) { if (G[i][j]) { int k = i; while (k <= n && G[k][j]) k++; if (k - i != sum_c[j]) return true; break; } } } for (int i = 1; i <= n; i++) { if (sum_r[i] == 0) { if (c0 == 0) return true; } } for (int j = 1; j <= m; j++) { if (sum_c[j] == 0) { if (r0 == 0) return true; } } return false; } vector<pair<int, int> > dir = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; void dfs(int x, int y) { vis[x][y] = 1; for (auto [dx, dy] : dir) { int nx = x + dx, ny = y + dy; if (vis[nx][ny]) continue; if (G[nx][ny] && 0 < nx && nx <= n && 0 < ny && ny <= m) dfs(nx, ny); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , str + 1); for (int j = 1; j <= m; j++) { G[i][j] = str[j] == # ? 1 : 0; } } if (no()) { puts( -1 ); return 0; } int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (G[i][j] && !vis[i][j]) { dfs(i, j); ans++; } } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 55; int v[N][N], x[N << 1], y[N << 1], n, m, q; int main() { scanf( %d , &n); v[1][1] = 1; v[1][2] = v[n][n] = 0; m = n * 2 - 4; for (int i = 3; i <= n; i += 2) { printf( ? %d %d %d %d n , i - 2, 1, i, 1); fflush(stdout); scanf( %d , &q); v[i][1] = q ^ 1 ^ v[i - 2][1]; printf( ? %d %d %d %d n , i - 2, 2, i, 2); fflush(stdout); scanf( %d , &q); v[i][2] = q ^ 1 ^ v[i - 2][2]; } for (int i = 2; i <= n; i += 2) { printf( ? %d %d %d %d n , i, 1, i + 1, 2); fflush(stdout); scanf( %d , &q); v[i][1] = q ^ 1 ^ v[i + 1][2]; printf( ? %d %d %d %d n , i - 1, 1, i, 2); fflush(stdout); scanf( %d , &q); v[i][2] = q ^ 1 ^ v[i - 1][1]; } for (int i = 1; i <= n; ++i) { for (int j = 3; j <= n; ++j) { printf( ? %d %d %d %d n , i, j - 2, i, j); fflush(stdout); scanf( %d , &q); v[i][j] = q ^ 1 ^ v[i][j - 2]; } } for (int i = 1; i <= n; ++i) x[i] = i, y[i] = 1; for (int i = n + 1; i < (n << 1); ++i) x[i] = n, y[i] = i + 1 - n; for (int i = 1; i <= m; ++i) { q = 0; for (int j = 0; j < 4; ++j) q ^= v[x[i + j]][y[i + j]]; if (q == 0) { printf( ? %d %d %d %d n , x[i], y[i], x[i + 3], y[i + 3]); fflush(stdout); scanf( %d , &q); if (v[x[i]][y[i]] ^ v[x[i + 3]][y[i + 3]] ^ q) break; for (int j = 1; j <= n; ++j) { for (int k = 1; k <= n; ++k) { if ((j + k) % 2 == 0) continue; v[j][k] ^= 1; } } break; } } printf( ! n ); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) printf( %d , v[i][j]); printf( n ); } } |
#include <bits/stdc++.h> using namespace std; int n, m, x, y; bool a[401][401]; bool viz[401]; int dist[401]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n >> m; while (m--) { cin >> x >> y; a[x][y] = a[y][x] = 1; } queue<int> q; q.push(1); viz[1] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 1; i <= n; i++) if (!viz[i] && (a[u][i] ^ a[1][n])) { q.push(i); viz[i] = 1; dist[i] = dist[u] + 1; } } return cout << ((!viz[n]) ? -1 : max(1, dist[n])), 0; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; }; void __print(long x) { cerr << x; }; void __print(long long x) { cerr << x; }; void __print(unsigned x) { cerr << x; }; void __print(unsigned long x) { cerr << x; }; void __print(unsigned long long x) { cerr << x; }; void __print(float x) { cerr << x; }; void __print(double x) { cerr << x; }; void __print(long double x) { cerr << x; }; void __print(char x) { cerr << << x << ; }; void __print(const char *x) { cerr << << x << ; }; void __print(const string &x) { cerr << << x << ; }; void __print(bool x) { cerr << (x ? true : false ); } long long powmod(long long a, long long b) { long long res = 1; a %= 1000000007; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } long long string_to_int(string s) { long long ans = 0; long long p = 1; for (long long i = s.size() - 1; i >= 0; i--) { ans += (s[i] - 0 ) * p; p *= 10; } return ans; } long long fast_pow(long long a, long long b) { if (b == 1) return a; if (b == 0) return 1; long long x = fast_pow(a, b / 2); x *= x; if (b & 1) x *= a; return x; } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { long long f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void t_c_c() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, k; cin >> n >> m >> k; long long arr[m]; for (long long i = 0; i < m; i++) { cin >> arr[i]; } long long days = 0; long long pages = k; long long point = 0; long long x = 0; long long xx = 0; for (long long i = 0; i < m;) { if (arr[i] - x <= pages) { while (arr[i] - xx <= pages) { ; x++; i++; } xx = x; days++; } else { long long factor = ((arr[i] - x) - pages) / k; pages += (((arr[i] - x) - pages) % k == 0 ? factor * k : (factor + 1) * k); } } cout << days << n ; } int32_t main() { t_c_c(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int d[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; int n, m, c[2005][2005]; char s[2005][2005]; bool vis[2005][2005]; bool judge(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m && s[x][y] == . ; } queue<pair<int, int> > q; void bfs(int x, int y) { vis[x][y] = 1; q.push(make_pair(x, y)); while (!q.empty()) { pair<int, int> p = q.front(); q.pop(); for (int k = 0; k < 4; k++) { int tx = p.first + d[k][0]; int ty = p.second + d[k][1]; if (judge(tx, ty) && !vis[tx][ty]) { vis[tx][ty] = 1; if (k == 0) { s[p.first][p.second] = < ; s[tx][ty] = > ; } else if (k == 1) { s[p.first][p.second] = > ; s[tx][ty] = < ; } if (k == 2) { s[p.first][p.second] = ^ ; s[tx][ty] = v ; } if (k == 3) { s[p.first][p.second] = v ; s[tx][ty] = ^ ; } for (int i = 0; i < 4; i++) { int ttx = tx + d[i][0]; int tty = ty + d[i][1]; if (judge(ttx, tty) && !vis[ttx][tty]) { c[ttx][tty]--; if (c[ttx][tty] == 1) { q.push(make_pair(ttx, tty)); vis[ttx][tty] = 1; } } } break; } } } } bool has_ans() { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (s[i][j] == . ) return 0; return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (s[i][j] == * ) continue; for (int k = 0; k < 4; k++) if (judge(i + d[k][0], j + d[k][1])) c[i][j]++; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (c[i][j] == 1 && !vis[i][j]) bfs(i, j); if (has_ans()) for (int i = 0; i < n; i++) printf( %s n , s[i]); else printf( Not unique n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int f[11][11][4][100010]; int n; char s[100010]; char c[100010]; int ch(char s) { if (s == A ) return 0; else if (s == C ) return 1; else if (s == T ) return 2; else if (s == G ) return 3; return -1; } void Add(int *tr, int x, int d) { for (; x <= n; x += x & (-x)) { tr[x] += d; } } int Sum(int *tr, int x) { if (x == 0) return 0; int s = 0; while (x) { s += tr[x]; x -= x & (-x); } return s; } int main() { scanf( %s , s); n = strlen(s); for (int i = n - 1; i >= 0; i--) s[i + 1] = s[i]; s[0] = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= 10; j++) Add(f[j][i % j][ch(s[i])], i, 1); int q, x, d, l, r; scanf( %d , &q); while (q--) { scanf( %d , &x); if (x == 1) { scanf( %d%s , &d, c); for (int i = 1; i <= 10; i++) Add(f[i][d % i][ch(s[d])], d, -1); s[d] = c[0]; for (int i = 1; i <= 10; i++) Add(f[i][d % i][ch(s[d])], d, 1); } else { scanf( %d%d%s , &l, &r, c); int len = strlen(c); int ans = 0; for (int i = 0; i < len; i++) ans += Sum(f[len][(l + i) % len][ch(c[i])], r) - Sum(f[len][(l + i) % len][ch(c[i])], l - 1); printf( %d n , ans); } } return 0; } |
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores Simple Programmable Interrupt Controller ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: simple_pic.v,v 1.3 2002-12-24 10:26:51 rherveille Exp $
//
// $Date: 2002-12-24 10:26:51 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/12/22 16:11:03 rherveille
// *** empty log message ***
//
//
//
// This is a simple Programmable Interrupt Controller.
// The number of interrupts is depending on the databus size.
// There's one interrupt input per databit (i.e. 16 interrupts for a 16
// bit databus).
// All attached devices share the same CPU priority level.
//
//
//
// Registers:
//
// 0x00: EdgeEnable Register
// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source
// '0' = level triggered interrupt source
// 0x01: PolarityRegister
// bits 7:0 R/W Polarity '1' = high level / rising edge
// '0' = low level / falling edge
// 0x02: MaskRegister
// bits 7:0 R/W Mask '1' = interrupt masked (disabled)
// '0' = interrupt not masked (enabled)
// 0x03: PendingRegister
// bits 7:0 R/W Pending '1' = interrupt pending
// '0' = no interrupt pending
//
// A CPU interrupt is generated when an interrupt is pending and its
// MASK bit is cleared.
//
//
//
// HOWTO:
//
// Clearing pending interrupts:
// Writing a '1' to a bit in the interrupt pending register clears the
// interrupt. Make sure to clear the interrupt at the source before
// writing to the interrupt pending register. Otherwise the interrupt
// will be set again.
//
// Priority based interrupts:
// Upon reception of an interrupt, check the interrupt register and
// determine the highest priority interrupt. Mask all interrupts from the
// current level to the lowest level. This negates the interrupt line, and
// makes sure only interrupts with a higher level are triggered. After
// completion of the interrupt service routine, clear the interrupt source,
// the interrupt bit in the pending register, and restore the MASK register
// to it's previous state.
//
// Addapt the core for fewer interrupt sources:
// If less than 8 interrupt sources are required, than the 'is' parameter
// can be set to the amount of required interrupts. Interrupts are mapped
// starting at the LSBs. So only the 'is' LSBs per register are valid. All
// other bits (i.e. the 8-'is' MSBs) are set to zero '0'.
// Codesize is approximately linear to the amount of interrupts. I.e. using
// 4 instead of 8 interrupt sources reduces the size by approx. half.
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
module simple_pic #(parameter int NUM_IRQ=32) (
clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o,
irq
);
//
// Inputs & outputs
//
// 8bit WISHBONE bus slave interface
input clk_i; // clock
input rst_i; // reset (asynchronous active low)
input cyc_i; // cycle
input stb_i; // strobe (cycle and strobe are the same signal)
input [ 2:1] adr_i; // address
input we_i; // write enable
input [ 31:0] dat_i; // data output
output [ 31:0] dat_o; // data input
output ack_o; // normal bus termination
output int_o; // interrupt output
//
// Interrupt sources
//
input [NUM_IRQ:1] irq; // interrupt request inputs
//
// Module body
//
reg [NUM_IRQ:1] pol, edgen, pending, mask; // register bank
reg [NUM_IRQ:1] lirq, dirq; // latched irqs, delayed latched irqs
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(NUM_IRQ > 32)
$display("simple_pic: max. 32 interrupt sources supported.");
end
// synopsys translate_on
//
// latch interrupt inputs
always @(posedge clk_i)
lirq <= irq;
//
// generate delayed latched irqs
always @(posedge clk_i)
dirq <= lirq;
//
// generate actual triggers
function trigger;
input edgen, pol, lirq, dirq;
reg edge_irq, level_irq;
begin
edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq);
level_irq = pol ? lirq : ~lirq;
trigger = edgen ? edge_irq : level_irq;
end
endfunction
reg [NUM_IRQ:1] irq_event;
integer n;
always @(posedge clk_i)
for(n=1; n<=NUM_IRQ; n=n+1)
irq_event[n] <= trigger(edgen[n], pol[n], lirq[n], dirq[n]);
//
// generate wishbone register bank writes
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
pol <= {{NUM_IRQ}{1'b0}}; // clear polarity register
edgen <= {{NUM_IRQ}{1'b0}}; // clear edge enable register
mask <= {{NUM_IRQ}{1'b1}}; // mask all interrupts
end
else if(wb_wr) // wishbone write cycle??
case (adr_i) // synopsys full_case parallel_case
2'b00: edgen <= dat_i[NUM_IRQ-1:0]; // EDGE-ENABLE register
2'b01: pol <= dat_i[NUM_IRQ-1:0]; // POLARITY register
2'b10: mask <= dat_i[NUM_IRQ-1:0]; // MASK register
2'b11: ; // PENDING register is a special case (see below)
endcase
// pending register is a special case
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
pending <= {{NUM_IRQ}{1'b0}}; // clear all pending interrupts
else if ( wb_wr & (&adr_i) )
pending <= (pending & ~dat_i[NUM_IRQ-1:0]) | irq_event;
else
pending <= pending | irq_event;
//
// generate dat_o
reg [31:0] dat_o;
always @(posedge clk_i)
case (adr_i) // synopsys full_case parallel_case
2'b00: dat_o <= { {{32-NUM_IRQ}{1'b0}}, edgen};
2'b01: dat_o <= { {{32-NUM_IRQ}{1'b0}}, pol};
2'b10: dat_o <= { {{32-NUM_IRQ}{1'b0}}, mask};
2'b11: dat_o <= { {{32-NUM_IRQ}{1'b0}}, pending};
endcase
//
// generate ack_o
reg ack_o;
always @(posedge clk_i)
ack_o <= wb_acc & !ack_o;
//
// generate CPU interrupt signal
reg int_o;
always @(posedge clk_i)
int_o <= |(pending & ~mask);
endmodule
|
#pragma GCC optimize( O3 , Ofast , no-stack-protector , unroll-loops , omit-frame-pointer , inline ) //Optimization flags #pragma GCC option( arch=native , tune=native , no-zero-upper ) //Enable AVX // #pragma GCC target( avx2 ) //Enable AVX #include <bits/stdc++.h> #define int long long using namespace std; const int MOD = 1e9 + 7; const int MAXN = 110; int C[MAXN]; int B[MAXN]; int T[MAXN]; int dp[MAXN][MAXN*MAXN]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int N; cin >> N; for(int i = 1 ; i <= N ; i++) { cin >> C[i]; } for(int i = 2 ; i <= N ; i++) { cin >> B[i]; T[i] = T[i-1]+B[i]; } for(int i = 1 ; i <= N ; i++) { T[i] += T[i-1]; } int ini = -T[N]/N - 50; int fin = (100*N-T[N])/N + 50; map<int,int> mp; for(int X = ini ; X <= fin ; X++) { for(int j = 0 ; j <= 10000 ; j++) { dp[0][j] = 1; } for(int i = 1 ; i <= N ; i++) { for(int j = 0 ; j <= 10000 ; j++) { dp[i][j] = 0; if(j-T[i] >= X*i) { int val = 0; if(j-C[i]-1 >= 0)val = dp[i-1][j-C[i]-1]; dp[i][j] = (dp[i-1][j]+MOD-val); dp[i][j] %= MOD; } } for(int j = 1 ; j <= 10000 ; j++) { dp[i][j] += dp[i][j-1]; dp[i][j] %= MOD; } } mp[X] = dp[N][10000]; } int Q; cin >> Q; for(int i = 1 ; i <= Q ; i++) { int X; cin >> X; if(X < ini)cout << mp[ini] << n ; else if(X > fin)cout << 0 << n ; else cout << mp[X] << n ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const int INF = 1e9; const int mx = 300001; int n, q; vector<int> a, t[mx]; int count(int l, int r, int val) { vector<int>::iterator bg = t[val].begin(), en = t[val].end(); return upper_bound(bg, en, r) - lower_bound(bg, en, l); } struct node { vector<vector<pair<int, int> > > a; node *l, *r; node() : a(vector<vector<pair<int, int> > >()), l(NULL), r(NULL) {} }; vector<pair<int, int> > best; vector<int> roll, cnt; const int maxk = 5; node *T; void add(int x) { cnt[x]++; roll.push_back(x); for (int i = 0; i < maxk; ++i) { if (best[i].second == x) { best.erase(best.begin() + i, best.begin() + i + 1); break; } } best.push_back({cnt[x], x}); sort(best.begin(), best.end()); if (best.size() > maxk) best.erase(best.begin(), best.begin() + 1); } void clear() { for (auto pos : roll) { cnt[pos]--; } roll.clear(); best.clear(); for (int i = 0; i < maxk; ++i) { best.push_back({0, 0}); } } node *build(int tl, int tr) { if (tl == tr) return new node(); else { node *res = new node(); int tm = (tl + tr) >> 1; for (int i = tm; i >= tl; --i) { add(a[i]); (res->a).push_back(best); } clear(); reverse((res->a).begin(), (res->a).end()); for (int i = tm + 1; i <= tr; ++i) { add(a[i]); (res->a).push_back(best); } clear(); res->l = build(tl, tm); res->r = build(tm + 1, tr); return res; } } int get(node *root, int l, int r, int k, int tl, int tr) { if (l == r) return a[l]; int tm = (tl + tr) >> 1; if (r <= tm) return get(root->l, l, r, k, tl, tm); if (l >= tm + 1) return get(root->r, l, r, k, tm + 1, tr); int ans = INF; vector<pair<int, int> > v1 = (root->a)[l - tl], v2 = (root->a)[r - tl]; for (auto p : v1) { if (count(l, r, p.second) > k) ans = min(ans, p.second); } for (auto p : v2) { if (count(l, r, p.second) > k) ans = min(ans, p.second); } if (ans == INF) ans = -1; return ans; } int main() { scanf( %d%d , &n, &q); a.resize(n); cnt.resize(n + 1); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); t[a[i]].push_back(i); } clear(); T = build(0, n - 1); int l, r, k; for (int i = 0; i < q; ++i) { scanf( %d%d%d , &l, &r, &k); l--; r--; k = (r - l + 1) / k; printf( %d n , get(T, l, r, k, 0, n - 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; void func(void) { freopen( input.c , r , stdin); freopen( output.c , w , stdout); } void print(vector<long long> &v) { cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { printf( %lld , v[i]); } printf( n ); } void print(vector<pair<long long, long long> > &v) { cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { printf( %lld %lld n , v[i].first, v[i].second); } } void print(double d) { cout << fixed << setprecision(10) << d << endl; } void print(string s, double d) { cout << s << ; cout << fixed << setprecision(10) << d << endl; } const int N = 1e5 + 100; struct info { long long day, cost, place; bool operator<(info k1) const { return day < k1.day; } }; vector<info> in; vector<info> out; set<pair<long long, long long> > outFlight[N]; long long inFlight[N]; int main() { long long n, q, i, j = 0, temp, t, k, ans = 0, sum = 0, x, y, z, cnt = 0, m, fg = 0, mx = 0, mx1 = 0, mn = 8e18, mn1 = 8000000000000000000; scanf( %lld %lld %lld , &n, &m, &k); for (int i = 0; i < m; i++) { scanf( %lld %lld , &x, &y); scanf( %lld %lld , &z, &t); info xx; xx.day = x; xx.place = y; if (y == 0) xx.place = z; xx.cost = t; if (y) in.push_back(xx); else out.push_back(xx); } sort(in.begin(), in.end()); sort(out.begin(), out.end()); for (int i = 0; i < N; i++) inFlight[i] = 1e10; int ok = 0; for (int i = 0; i < out.size(); i++) { outFlight[out[i].place].insert({out[i].cost, i}); } long long outSum = 0; long long inSum = 0; for (int i = 1; i <= n; i++) { if (outFlight[i].size() == 0) { printf( -1 n ); return 0; } auto it = outFlight[i].begin(); pair<long long, long long> p = *it; outSum += p.first; } cnt = 0; for (int i = 0; i < in.size(); i++) { long long now = in[i].day; long long place = in[i].place; long long cost = in[i].cost; if (inFlight[place] == 1e10) { inFlight[place] = cost; inSum += cost; cnt++; } else { inSum -= inFlight[place]; inFlight[place] = min(inFlight[place], cost); inSum += inFlight[place]; } now += k + 1; fg = 0; for (; ok < out.size(); ok++) { if (out[ok].day >= now) break; auto it = outFlight[out[ok].place].begin(); pair<long long, long long> p = *it; outSum -= p.first; p = {out[ok].cost, ok}; outFlight[out[ok].place].erase(p); if (outFlight[out[ok].place].size() == 0) { fg = 1; break; } it = outFlight[out[ok].place].begin(); p = *it; outSum += p.first; } if (fg) break; if (cnt == n) { mn = min(mn, inSum + outSum); } } if (mn == 8e18) mn = -1; cout << mn << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_SYMBOL_V
/**
* udp_dff$PR_pp$PG: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double pi = 3.14159265359; using namespace std; int main() { ios::sync_with_stdio(false); string a, b; cin >> a >> b; string c(a.size(), 0 ); int count = 0; for (unsigned int i = 0; i < a.size(); i++) if (a[i] == b[i]) c[i] = a[i], count++; if ((a.size() - count) % 2) cout << impossible ; else { bool ok = 0; for (unsigned int i = 0; i < a.size(); i++) if (a[i] != b[i] && !ok) c[i] = a[i], ok = 1; else if ((a[i] != b[i] && ok)) c[i] = b[i], ok = 0; cout << c << n ; } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_gtp_pipe_drp.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_drp.v
// Description : GTP PIPE DRP Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- GTP PIPE DRP Module -----------------------------------------------
module pcieCore_gtp_pipe_drp #
(
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 1'd0 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 2:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 2:0] fsm = 0;
//---------- DRP Address -------------------------------
localparam ADDR_RX_DATAWIDTH = 9'h011;
//---------- DRP Mask ----------------------------------
localparam MASK_RX_DATAWIDTH = 16'b1111011111111111; // Unmask bit [ 11]
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_LOAD = 1;
localparam FSM_READ = 2;
localparam FSM_RRDY = 3;
localparam FSM_WRITE = 4;
localparam FSM_WRDY = 5;
localparam FSM_DONE = 6;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
1'd0 :
begin
addr_reg <= ADDR_RX_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_DATAWIDTH) | data_rx_datawidth;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if (index == INDEX_MAX)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
#include <bits/stdc++.h> using namespace std; void ga(int N, int *A) { for (int i(0); i < N; i++) cin >> A[i]; } int main(void) { ios_base::sync_with_stdio(false); string num; getline(cin, num); int ln = num.length(); int b = 0; int st = 0; int en = ln; bool dot = 0; for (char e : num) { dot = dot or (e == . ); } for (int i(0); i < ln; i++) { if (num[i] != 0 ) { st = i; break; } } for (int i = ln - 1; i > 0; i--) { if (num[i] != 0 ) { en = i + 1; break; } }; ; if (num[st] == . ) { b--; for (int i(st + 1); i < ln; i++) { if (num[i] != 0 ) { st = i; break; } b--; } cout << num[st] << (en - st - 1 == 0 ? : . ) << num.substr(st + 1, en - st - 1) << E << b << endl; return 0; } else { b--; for (int i(st); i < ln; i++) { if (num[i] == . ) { en--; num.erase(i, 1); break; } b++; }; for (int i = en - 1; i >= 0; i--) { if (num[i] != 0 ) { ; en = i + 1; break; } } cout << num[st] << (en - st - 1 == 0 ? : . ) << num.substr(st + 1, en - st - 1) << (b == 0 ? : E + to_string(b)) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; const int mod = 1e9 + 7; int n, m, d, k, x, ans, pos[N], a[30]; bool f[1 << 20]; int cal(int x) { int res = 0; for (int i = (0); i < (m); i++) if (x & (1 << i)) res++; return res; } int main() { scanf( %d%d%d , &n, &m, &d); for (int i = (0); i < (m); i++) { scanf( %d , &k); for (int j = (0); j < (k); j++) { scanf( %d , &x); pos[x] = i; } } for (int i = (1); i < (d + 1); i++) a[pos[i]]++; for (int i = (d); i < (n + 1); i++) { if (i > d) a[pos[i]]++, a[pos[i - d]]--; ; x = 0; for (int j = (0); j < (m); j++) if (!a[j]) x += (1 << j); f[x] = 1; } ans = m; for (int i = (1 << m) - 1; i >= 1; i--) { if (f[i]) { for (int j = (0); j < (m); j++) if ((1 << j) & i) { f[i - (1 << j)] = 1; } } else ans = min(ans, cal(i)); } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, c1, c2, v, q; long long xs, xe, ye, ys; long long pos1[100005]; long long pos2[100005]; long long solve(int pos, int v) { long long ans = abs(pos - xe) + abs(pos - xs); long long y = abs(ye - ys); ans += (y - 1) / v + 1; return ans; } int main() { cin >> n >> m >> c1 >> c2 >> v; for (int i = 0; i < c1; i++) cin >> pos1[i]; for (int i = 0; i < c2; i++) cin >> pos2[i]; cin >> q; while (q--) { int id; cin >> ys >> xs >> ye >> xe; long long ans = 999999999999; if (ys == ye) ans = abs(xe - xs); else { if (c1) { id = upper_bound(pos1, pos1 + c1, xs) - pos1; if (id != c1) ans = min(ans, solve(pos1[id], 1)); if (id - 1 >= 0) ans = min(ans, solve(pos1[id - 1], 1)); id = upper_bound(pos1, pos1 + c1, xe) - pos1; if (id != c1) ans = min(ans, solve(pos1[id], 1)); if (id - 1 >= 0) ans = min(ans, solve(pos1[id - 1], 1)); } if (c2) { id = upper_bound(pos2, pos2 + c2, xs) - pos2; if (id != c2) ans = min(ans, solve(pos2[id], v)); if (id - 1 >= 0) ans = min(ans, solve(pos2[id - 1], v)); id = upper_bound(pos2, pos2 + c2, xe) - pos2; if (id != c2) ans = min(ans, solve(pos2[id], v)); if (id - 1 >= 0) ans = min(ans, solve(pos2[id - 1], v)); } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); long long n, m, p; cin >> n >> m >> p; long long a; long long b; long long u = 0, v = 0; for (long long i = 1; i <= n; i++) { cin >> a; if (u == 0 && a % p != 0) { u = i; } } for (long long i = 1; i <= m; i++) { cin >> b; if (v == 0 && b % p != 0) { v = i; } } cout << u + v - 2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 500010; int ans[N]; void solve() { int n; cin >> n; int d = 0; for (int i = 0; i <= 30; i++) { ans[i] = (1 << i); } int sum = 0; for (int i = 0; i <= 30; i++) { sum += ans[i]; if (sum >= n) { d = i; break; } } int extra = sum - n; for (int i = d; i >= 1; i--) { long long need = (ans[i] - ans[i - 1] + 0ll) * (d - i + 1ll); if (extra > need) { extra -= need; for (int j = d; j >= i; j--) ans[j] = ans[i - 1]; } else { int dv = (extra / (d - i + 1)); int c = (extra % (d - i + 1)); for (int j = d; j >= i; j--) ans[j] -= dv; for (int j = i; j < i + c; j++) ans[j]--; break; } } cout << d << n ; for (int i = 1; i <= d; i++) cout << ans[i] - ans[i - 1] << ; cout << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tt; cin >> tt; while (tt--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; char s[N]; int n, m, t[N]; int a[N * 4], b[N * 4], ab[N * 4], ba[N * 4], aba[N * 4], tag[N * 4]; void pushup(int now) { a[now] = max(a[(now << 1)], a[(now << 1 | 1)]); b[now] = min(b[(now << 1)], b[(now << 1 | 1)]); ab[now] = max(ab[(now << 1)], max(ab[(now << 1 | 1)], a[(now << 1)] - 2 * b[(now << 1 | 1)])); ba[now] = max(ba[(now << 1)], max(ba[(now << 1 | 1)], a[(now << 1 | 1)] - 2 * b[(now << 1)])); aba[now] = max(max(aba[(now << 1)], aba[(now << 1 | 1)]), max(ab[(now << 1)] + a[(now << 1 | 1)], ba[(now << 1 | 1)] + a[(now << 1)])); } void build(int now, int l, int r) { if (l + 1 == r) { a[now] = b[now] = t[l]; ab[now] = ba[now] = -t[l]; return; } int mid = (l + r) >> 1; build((now << 1), l, mid); build((now << 1 | 1), mid, r); pushup(now); } void down(int now, int val) { a[now] += val; b[now] += val; ab[now] -= val; ba[now] -= val; tag[now] += val; } void pushdown(int now) { down((now << 1), tag[now]); down((now << 1 | 1), tag[now]); tag[now] = 0; } void Insert(int now, int l, int r, int a, int b, int val) { if (a <= l && b >= r - 1) { down(now, val); return; } int mid = (l + r) >> 1; pushdown(now); if (a < mid) Insert((now << 1), l, mid, a, b, val); if (b >= mid) Insert((now << 1 | 1), mid, r, a, b, val); pushup(now); } int main() { int x, y, z; scanf( %d%d , &n, &m); n = n * 2 - 2; scanf( %s , s + 1); for (int i = 1; i <= n; ++i) if (s[i] == ( ) t[i] = t[i - 1] + 1; else t[i] = t[i - 1] - 1; build(1, 1, n + 1); printf( %d n , aba[1]); for (int i = 0; i < m; ++i) { scanf( %d%d , &x, &y); if (x > y) swap(x, y); if (s[x] == ( ) z = -2; else z = 2; Insert(1, 1, n + 1, x, y - 1, z); swap(s[x], s[y]); printf( %d n , aba[1]); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const int inf = 1000000010; const int MAXN = 300010; struct edge { int u, v, c, t, res; } E[MAXN]; int n, m, k, u, v, x, y, t, a, b, N; int comp[MAXN * 2]; bool mark[MAXN * 2]; int del[MAXN * 2]; int del2[MAXN * 2]; unordered_map<int, int> deg[MAXN]; unordered_map<int, vector<int>> GRAPH[MAXN]; vector<int> GRAPH2[MAXN]; vector<int> G[2 * MAXN]; vector<int> GR[2 * MAXN]; vector<int> topol; void add_edge(int x, int y) { G[x].push_back(y); GR[y].push_back(x); } void add(int x, int y) { add_edge(x ^ 1, y); add_edge(y ^ 1, x); } void add2(int x, int y) { add_edge(x ^ 1, y); add_edge(y ^ 1, x); del[x ^ 1]++; del[y ^ 1]++; del2[y]++; del2[x]++; } void dfs1(int node) { mark[node] = 1; for (int v : G[node]) if (!mark[v]) dfs1(v); topol.push_back(node); } void dfs2(int node, int id) { comp[node] = id; for (int v : GR[node]) if (!comp[v]) dfs2(v, id); } bool check(int T) { for (int i = 0; i < 2 * MAXN; i++) { while (del[i]) { G[i].pop_back(); del[i]--; } while (del2[i]) { GR[i].pop_back(); del2[i]--; } } for (int i = 1; i <= m; i++) if (E[i].t > T) add2(2 * i ^ 1, 2 * i ^ 1); memset(comp, 0, sizeof(comp)); memset(mark, 0, sizeof(mark)); topol.clear(); for (int i = 2; i < 2 * MAXN; i++) if (!mark[i]) dfs1(i); reverse(topol.begin(), topol.end()); int id = 1; for (int v : topol) if (!comp[v]) dfs2(v, id++); for (int i = 2; i < 2 * N + 2; i++) if (comp[i] == comp[i ^ 1]) return 0; for (int i = 1; i <= m; i++) E[i].res = (comp[2 * i] > comp[2 * i + 1]); return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> u >> v >> x >> y; E[i] = {u, v, x, y}; deg[u][x]++; deg[v][x]++; GRAPH[u][x].push_back(i); GRAPH[v][x].push_back(i); GRAPH2[u].push_back(i); GRAPH2[v].push_back(i); } for (int i = 1; i <= n; i++) for (pair<int, int> p : deg[i]) if (p.second > 2) return cout << No << n , 0; for (int i = 1; i <= n; i++) for (auto it : GRAPH[i]) if (it.second.size() == 2) add(it.second[0] * 2, it.second[1] * 2); N = m; for (int i = 1; i <= n; i++) if (GRAPH2[i].size() >= 2) { k = GRAPH2[i].size(); for (int j = 0; j < k; j++) { int a = GRAPH2[i][j]; add(2 * a ^ 1, 2 * (++N)); if (j) add(2 * (N - 1) ^ 1, 2 * N); if (j) add(2 * a ^ 1, 2 * (N - 1) ^ 1); } } int dwn = -1, up = inf; while (up - dwn > 1) { int mid = (dwn + up) / 2; if (check(mid)) up = mid; else dwn = mid; } if (!check(up)) return cout << No << n , 0; vector<int> out; for (int i = 1; i <= m; i++) if (E[i].res) out.push_back(i); cout << Yes n << up << << out.size() << n ; for (int i : out) cout << i << ; cout << n ; return 0; } |
/*--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- File Name : diffeq.v
-- Author(s) : P. Sridhar
-- Affiliation : Laboratory for Digital Design Environments
-- Department of Electrical & Computer Engineering
-- University of Cincinnati
-- Date Created : June 1991.
-- Introduction : Behavioral description of a differential equation
-- solver written in a synthesizable subset of VHDL.
-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ.
-- Obtained from the Highlevel Synthesis Workshop
-- Repository.
--
-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
-- Date Modified : Sept, 91.
--
-- Disclaimer : This comes with absolutely no guarantees of any
-- kind (just stating the obvious ...)
--
-- Acknowledgement : The Distributed Synthesis Systems research at
-- the Laboratory for Digital Design Environments,
-- University of Cincinnati, is sponsored in part
-- by the Defense Advanced Research Projects Agency
-- under order number 7056 monitored by the Federal
-- Bureau of Investigation under contract number
-- J-FBI-89-094.
--
--------------------------------------------------------------------------
-------------------------------------------------------------------------*/
module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
input clk;
input reset;
input [31:0]aport;
input [31:0]dxport;
output [31:0]xport;
output [31:0]yport;
output [31:0]uport;
reg [31:0]xport;
reg [31:0]yport;
reg [31:0]uport;
wire [31:0]temp;
assign temp = uport * dxport;
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1)
begin
xport <= 0;
yport <= 0;
uport <= 0;
end
else
if (xport < aport)
begin
xport <= xport + dxport;
yport <= yport + temp;//(uport * dxport);
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/);
// verilator lint_off LITENDIAN
// verilator lint_off WIDTH
reg [63:0] sum;
reg [2:1] [4:3] array [5:6] [7:8];
reg [1:2] [3:4] larray [6:5] [8:7];
bit [31:0] depth1_array [0:0];
function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d);
crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]};
endfunction
initial begin
sum = 0;
// We use 'index_' as the prefix for all loop vars,
// this allows t_foreach.pl to confirm that all loops
// have been unrolled and flattened away and no loop vars
// remain in the generated .cpp
foreach (depth1_array[index_a]) begin
sum = crc(sum, index_a, 0, 0, 0);
// Ensure the index never goes out of bounds.
// We used to get this wrong for an array of depth 1.
assert (index_a != -1);
assert (index_a != 1);
end
`checkh(sum, 64'h0);
sum = 0;
foreach (array[index_a]) begin
sum = crc(sum, index_a, 0, 0, 0);
end
`checkh(sum, 64'h000000c000000000);
sum = 0;
foreach (array[index_a,index_b]) begin
sum = crc(sum, index_a, index_b, 0, 0);
end
`checkh(sum, 64'h000003601e000000);
sum = 0;
foreach (array[index_a,index_b,index_c]) begin
sum = crc(sum, index_a, index_b, index_c, 0);
end
`checkh(sum, 64'h00003123fc101000);
sum = 0;
foreach (array[index_a,index_b,index_c,index_d]) begin
sum = crc(sum, index_a, index_b, index_c, index_d);
end
`checkh(sum, 64'h0030128ab2a8e557);
//
sum = 0;
foreach (larray[index_a]) begin
sum = crc(sum, index_a, 0, 0, 0);
end
`checkh(sum, 64'h0000009000000000);
sum = 0;
foreach (larray[index_a,index_b]) begin
sum = crc(sum, index_a, index_b, 0, 0);
sum = sum + {4'b0,index_a[7:0], 4'h0,index_b[7:0]};
end
`checkh(sum, 64'h000002704b057073);
sum = 0;
foreach (larray[index_a,index_b,index_c]) begin
sum = crc(sum, index_a, index_b, index_c, 0);
end
`checkh(sum, 64'h00002136f9000000);
sum = 0;
foreach (larray[index_a,index_b,index_c,index_d]) begin
sum = crc(sum, index_a, index_b, index_c, index_d);
end
`checkh(sum, 64'h0020179aa7aa0aaa);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, mp; cin >> n >> m >> k; mp = n / 2 + 1; if (n % 2 == 0 || mp > m) { cout << 0; return 0; } int ans = 0, i, a[10005]; for (i = 0; i < n; i++) cin >> a[i]; int min = a[0]; for (i = 0; i < n; i++) if (i % 2 == 0) if (a[i] < min) min = a[i]; for (i = 0; i < k; i++) { int num = m / mp; if (min == 0) break; if (num <= min) { min -= num; ans += num; } else { ans += min; min = 0; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; long long mod = 1000000007; long long sols = 0, ti = 0; for (int i = s.size() - 1; i >= 0; i--) { if (s[i] == b ) ti++; else { sols += ti; ti *= 2; sols %= mod; ti %= mod; } } cout << sols << endl; } |
#include <bits/stdc++.h> using namespace std; inline void PAUSE() { char tmp; cin >> tmp; } int M[100001]; int f[100001]; int main() { int n; scanf( %d , &n); for (int i = 0; i <= 100000; i++) { M[i] = -1; } int x, k; for (int i = 0; i < n; i++) { scanf( %d %d , &x, &k); if (x - M[k] > 1) { cout << NO ; return 0; } M[k] = x > M[k] ? x : M[k]; f[k] = 1; } cout << YES ; PAUSE(); return 0; } |
/*******************************************************************************
* Module: pll_base
* Date:2014-05-01
* Author: Andrey Filippov
* Description: PLLE2_BASE wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* pll_base.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pll_base.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module pll_base#(
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", // "OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT = 1, // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT0_DIVIDE = 1, // CLK0 outout divide, integer 1..128
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE" // Delays "DONE" signal until MMCM is locked
)
(
input clkin, // General clock input
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkfbout, // dedicate feedback output
output locked // PLL locked output
);
PLLE2_BASE #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_BASE_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst) // input
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_0_V
`define SKY130_FD_SC_LP__NOR3_0_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_0 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_0 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_0_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "seq_rec/seq_rec.v"
`include "seq_rec/seq_rec_core.v"
`include "utils/cdc_pulse_sync.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam SEQ_GEN_BASEADDR = 32'h1000; //0x1000
localparam SEQ_GEN_HIGHADDR = 32'h3000-1; //0x300f
localparam SEQ_REC_BASEADDR = 32'h3000;
localparam SEQ_REC_HIGHADDR = 32'h5000 - 1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire EX_START_PULSE;
pulse_gen
#(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(BUS_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire [7:0] SEQ_OUT;
seq_gen
#(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(8*1024),
.OUT_BITS(8)
) i_seq_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(BUS_CLK),
.SEQ_OUT(SEQ_OUT)
);
seq_rec
#(
.BASEADDR(SEQ_REC_BASEADDR),
.HIGHADDR(SEQ_REC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(8*1024),
.IN_BITS(8)
) i_seq_rec
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(BUS_CLK),
.SEQ_IN(SEQ_OUT)
);
initial begin
$dumpfile("seq.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { int a, b, n; cin >> a >> b >> n; if (n % 3 == 0) cout << a << endl; else if (n % 3 == 1) cout << b << endl; else cout << (a ^ b) << endl; } } |
#include <bits/stdc++.h> using namespace std; vector<long long> readvec(long long length, long long off = 0); template <typename T> string ts(T v); int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n; long long z; cin >> n >> z; vector<long long> v = readvec(n); sort(v.begin(), v.end()); long long left = 0; long long right = v.size() / 2; long long ans = 0; while (true) { if (left >= v.size() / 2 || right >= v.size()) break; if (v[right] - v[left] >= z) { ans++; left++; right++; } else { right++; } } cout << ans << endl; } template <typename T> string ts(T v) { stringstream ss; ss << [ ; for (auto it = v.begin(); it != v.end(); it++) { if (it != v.begin()) ss << , ; ss << *it; } ss << ] ; return ss.str(); } vector<long long> readvec(long long length, long long off) { vector<long long> v; for (long long i = 0; i < length; i++) { long long x; cin >> x; v.push_back(x + off); } return v; } |
#include <bits/stdc++.h> using namespace std; long double dist(long double x1, long double y1, long double x2, long double y2) { long double D = ((x2 - x1) * (x2 - x1)) + ((y2 - y1) * (y2 - y1)); return sqrt(D); } int main() { const int inf = 1e9; int n; cin >> n; vector<pair<int, pair<pair<int, int>, long double>>> v; for (int i = 0; i < n; i++) { int x, y, t; long double p; cin >> x >> y >> t >> p; v.push_back({t, {{x, y}, p}}); } sort(v.begin(), v.end()); long double ans = 0.0; vector<long double> dp(n + 1, 0.0); for (int i = 1; i <= n; i++) dp[i] = v[i - 1].second.second; dp[0] = 0; for (int i = 0; i < n; i++) { for (int j = i - 1; j >= 0; j--) { long double x1 = (v[i].second.first.first), x2 = (v[j].second.first.first); long double y1 = v[i].second.first.second, y2 = v[j].second.first.second; if (dist(x1, y1, x2, y2) <= (long double)(v[i].first - v[j].first)) { dp[i + 1] = max(dp[i + 1], dp[j + 1] + v[i].second.second); } } ans = max(ans, dp[i + 1]); } cout << setprecision(14) << ans << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_8_V
`define SKY130_FD_SC_LS__DECAPHE_8_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog wrapper for decaphe with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_8_V
`define SKY130_FD_SC_HS__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_8 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_8_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = LLONG_MAX; struct minimum_cost_bipartite_matching { int nl, nr; long long mc = 0; vector<int> ml, mr, ly; minimum_cost_bipartite_matching(int nl, int nr, vector<vector<long long>> &c) : nl(nl), nr(nr), ml(nl, -1), mr(nr, -1), ly(nr) { vector<long long> s(nl), t(nr); for (int i = 0; i < nl; i++) { int x = i, y = -1; vector<bool> u(nr); vector<long long> md(nr, inf); while (x != -1) { long long ny = -1, d = inf; for (int j = 0; j < nr; j++) if (!u[j]) { long long v = c[x][j] - s[x] - t[j]; if (v < md[j]) md[j] = v, ly[j] = y; if (md[j] < d) d = md[j], ny = j; } s[i] += d; mc += d; for (int j = 0; j < nr; j++) if (u[j]) s[mr[j]] += d, t[j] -= d; else md[j] -= d; y = ny; u[y] = true; x = mr[y]; } while (y != -1) { mr[y] = ly[y] != -1 ? mr[ly[y]] : i; ml[mr[y]] = y; y = ly[y]; } } } }; int charToInt(char c) { return c >= a && c <= z ? c - a : c - A + 26; } char intToChar(int c) { return c < 26 ? a + c : A + c - 26; } int main() { int n, k; cin >> n >> k; string s[2]; cin >> s[0] >> s[1]; vector<vector<long long>> c(k, vector<long long>(k)); for (int i = 0; i < n; i++) c[charToInt(s[0][i])][charToInt(s[1][i])]--; minimum_cost_bipartite_matching mcbm(k, k, c); cout << -mcbm.mc << n ; for (int i = 0; i < k; i++) cout << intToChar(mcbm.ml[i]); cout << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; if (n - a > b + 1) { cout << b + 1 << endl; } else { cout << n - a << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int ms = 1001000; bool hole[ms]; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); long long n, m, k; cin >> n; if (n == 1 || n == 2) { cout << 0; return 0; } cout << (n + 1) / 2 - 1; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w12_d3_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w12_d3_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd4;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w12_d3_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w12_d3_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// file: ddr3_clkgen.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______267.325____251.827
// CLK_OUT2___400.000______0.000______50.0______180.270____251.827
// CLK_OUT3___100.000______0.000______50.0______231.478____251.827
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ddr3_clkgen,clk_wiz_v4_1,{component_name=ddr3_clkgen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module ddr3_clkgen
(// Clock in ports
input clk50in,
// Clock out ports
output clk50,
output clk400,
output clk100,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf
(.O (clkin1),
.I (clk50in));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (8),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (1),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (4),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Status and control signals
.LOCKED (LOCKED),
.RST (RESET),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (clk50),
.I (clkout0));
BUFG clkout2_buf
(.O (clk400),
.I (clkout1));
BUFG clkout3_buf
(.O (clk100),
.I (clkout2));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 155; int n; int a[N], b[N], A, B; int main() { scanf( %d , &n); a[0] = 1; for (int i = 1; i <= n; i++) { for (int j = 0; j <= A; j++) b[j + 1] = (b[j + 1] + a[j]) % 2; B = max(B, A + 1); swap(A, B); for (int j = 0; j <= A; j++) swap(a[j], b[j]); } printf( %d n , A); for (int i = 0; i <= A; i++) printf( %d%c , a[i], i == A ? n : ); printf( %d n , B); for (int i = 0; i <= B; i++) printf( %d%c , b[i], i == B ? n : ); return 0; } |
#include <bits/stdc++.h> int n; char str[250000]; int main() { while (~scanf( %d , &n)) { scanf( %s , str); int len = strlen(str); int sum1 = 0, sum2 = 0; for (int i = 0; i < len; i++) { if (str[i] == < ) { sum1++; } else { break; } } for (int i = len - 1; i >= 0; i--) { if (str[i] == > ) { sum2++; } else { break; } } printf( %d n , sum1 + sum2); } return 0; } |
//
//
// Accumulators are given 2 bits of growth. If fast edge transitions are expected to occur (which, for
// oversampling Sigma-Deltas, is generally a bad thing), this will need to be increased.
//
// 3 dB bandwidth for 64 oversampling is about Fclk / 202, it seems.
module SigmaDelta2ndOrder #(
parameter WIDTH = 16, ///< Input width
parameter GAIN = 7.0/6.0, ///< Gain parameter
parameter GROWTH = 2, ///< Growth bits on accumulators
parameter CLAMP = 0 ///< Clamp accumulators
)
(
input clk,
input rst,
input en,
input signed [WIDTH-1:0] in,
output sdOut
);
// For 2nd order sigma-delta modulators, signal to noise ratio (SNR) must be
// balanced against stability. Choosing a GAIN of one would theoretically
// maximize SNR, but the feedback loop would be completely unstable. A GAIN of
// 1.16 has been found to be the best trade-off for this particular type of
// sigma-delta. See [1]. Specifically, page 2330, gamma=2.33, scaled to 1.16 in
// our design. Be wary: I had to rearrange the order such that the scaled value
// was applied to the first integrator instead of the second, so this result may
// not 100% match the theory in the paper, and this still represents a tradeoff.
// If you really need to squeeze out that extra 1 dB of performance, consider
// tuning your own sigma-delta modulator, and use a higher order loop.
//
// [1] S. Hein and A. Zakhor, "On the stability of sigma delta modulators," IEEE
// Trans Signal Proc., vol. 41, no. 7, pp. 2322-2348, July 1993.
localparam integer GAIN1 = 2.0**(WIDTH-1);
localparam integer GAIN2 = 2.0**(WIDTH-1)*GAIN;
localparam ACC1_WIDTH = WIDTH+GROWTH;
localparam ACC2_WIDTH = WIDTH+2*GROWTH;
reg signed [ACC1_WIDTH-1:0] acc1;
reg signed [ACC2_WIDTH-1:0] acc2;
wire signed [ACC1_WIDTH:0] acc1Calc;
wire signed [ACC2_WIDTH:0] acc2Calc;
assign acc1Calc = acc1 + in + $signed(acc2[ACC2_WIDTH-1] ? GAIN1 : -GAIN1);
assign acc2Calc = acc2 + acc1Calc + $signed(acc2[ACC2_WIDTH-1] ? GAIN2 : -GAIN2);
initial begin
acc1 = 'd0;
acc2 = 'd0;
end
always @(posedge clk) begin
if (rst) begin
acc1 <= 'd0;
acc2 <= 'd0;
end else if (en) begin
if (CLAMP) begin
acc1 <= (^acc1Calc[ACC1_WIDTH-:2]) ? {acc1Calc[ACC1_WIDTH], {(ACC1_WIDTH-1){acc1Calc[ACC1_WIDTH-1]}}}
: acc1Calc;
acc2 <= (^acc2Calc[ACC2_WIDTH-:2]) ? {acc2Calc[ACC2_WIDTH], {(ACC2_WIDTH-1){acc2Calc[ACC2_WIDTH-1]}}}
: acc2Calc;
end
else begin
acc1 <= acc1Calc;
acc2 <= acc2Calc;
end
end
end
// Use the sign bit as the output
assign sdOut = ~acc2[WIDTH+2*GROWTH-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_SYMBOL_V
`define SKY130_FD_SC_HDLL__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_Add_Subt();
parameter PERIOD = 10;
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;// */
/*parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;// */
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Add_Subtract_Function #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) uut(
.clk(clk),
.rst(rst),
.beg_FSM(beg_FSM),
.ack_FSM(ack_FSM),
.Data_X(Data_X),
.Data_Y(Data_Y),
.add_subt(add_subt),
.r_mode(r_mode),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.ready(ready),
.final_result_ieee(final_result_ieee)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
add_subt = 0;
// // Wait 100 ns for global reset to finish
// #100 rst = 0;
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
// Wait 100 ns for global reset to finish
#100 rst = 0;
//Add stimulus here
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_FSM = 0;
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Cont_CLK = Cont_CLK + 1;
ack_FSM = 0;
end
else if(Cont_CLK ==2) begin
ack_FSM = 0;
beg_FSM = 1;
Cont_CLK = Cont_CLK +1 ;
end
else begin
ack_FSM = 0;
Cont_CLK = Cont_CLK + 1;
beg_FSM = 0;
end
if(ready==1) begin
ack_FSM = 1;
Cont_CLK = 0;
end
if(ready==1 && ack_FSM) begin
Cont_CLK = 0;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31A_TB_V
`define SKY130_FD_SC_HS__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 A3 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 A3 = 1'b0;
#320 B1 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B1 = 1'b1;
#440 A3 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B1 = 1'bx;
#560 A3 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31A_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s[10]; s[0] = O-|-OOOO ; s[1] = O-|O-OOO ; s[2] = O-|OO-OO ; s[3] = O-|OOO-O ; s[4] = O-|OOOO- ; s[5] = -O|-OOOO ; s[6] = -O|O-OOO ; s[7] = -O|OO-OO ; s[8] = -O|OOO-O ; s[9] = -O|OOOO- ; int n; cin >> n; if (n == 0) cout << s[0] << endl; while (n != 0) { int z = n % 10; cout << s[z] << endl; n /= 10; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int N = 2e5 + 10; const long long mod = 1e9 + 7; const long long mod2 = 998244353; const long long inf = 8e18; const int LOG = 22; long long pw(long long a, long long b, long long M) { return (!b ? 1 : (b & 1 ? (a * pw(a * a % M, b / 2, M)) % M : pw(a * a % M, b / 2, M))); } int v[N], dp[N], cnt[N], cu[N], Fi[N], kol[N], L[N], A[N]; void solve() { map<int, int> mp; int n; cin >> n; A[0] = -1; for (int i = 0; i <= n + 1; i++) { if (i && i <= n) { cin >> v[i]; A[i] = v[i]; } dp[i] = cnt[i] = cu[i] = Fi[i] = L[i] = kol[i] = 0; } sort(A + 1, A + n + 1); int ptr = 0; for (int i = 1; i <= n; i++) { if (A[i] != A[i - 1]) { ptr++; } mp[A[i]] = ptr; } for (int i = n; ~(i - 1); i--) { v[i] = mp[v[i]]; Fi[v[i]] = i; cnt[v[i]]++; } int ans = 0; for (int i = 1; i <= n; i++) { dp[i] = max(dp[L[v[i]]], cu[v[i] - 1]) + 1; if (cnt[v[i] - 1] == cu[v[i] - 1]) { dp[i] = max(dp[i], kol[v[i] - 1] + 1); } ans = max(ans, dp[i]); L[v[i]] = i; ++cu[v[i]]; if (cu[v[i]] == cnt[v[i]]) { kol[v[i]] = dp[Fi[v[i]]] + cnt[v[i]] - 1; } } cout << n - ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int q; cin >> q; while (q--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_4_V
`define SKY130_FD_SC_HDLL__MUX2_4_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int q[2005], a[2005], cum[2005]; int cnt = 1, n; set<int> use; set<pair<int, int> > s; set<pair<int, int> >::iterator it; map<int, vector<int> > mp; long long diff(int dif) { return (dif * 1LL * (dif + 1)) / 2; } int main() { scanf( %d , &n); int cur = 0; for (int i = 0; i < n; i++) { int ti; scanf( %d , &ti); int ok = 1, ni = ti; while (ni > 0) { if (!(ni % 10 == 4 || ni % 10 == 7)) { ok = 0; break; } ni /= 10; } if (ok == 1) { if (cur > 0) { q[cnt] = cur; a[cnt] = 0; cnt++; cur = 0; } mp[ti].push_back(cnt); q[cnt] = 1; a[cnt] = ti; cnt++; } else cur++; } if (cur > 0) { q[cnt] = cur; a[cnt] = 0; cnt++; } cum[0] = 0; for (int i = 1; i < cnt; i++) { cum[i] = cum[i - 1] + q[i]; } long long ret = 0; for (int i = 1; i < cnt; i++) { if (q[i] >= 2) { for (int j = 1; j < q[i]; j++) { ret += j * 1LL * (j + 1) / 2 * (q[i] - j); } for (int j = 1; j < q[i]; j++) { ret += j * 1LL * (cum[cnt - 1] - cum[i]) * 1LL * (q[i] - j); ret += (q[i] - j) * 1LL * (cum[i - 1]) * 1LL * j; } } s.clear(); use.clear(); long long sum = diff(cum[i - 1]); if (i > 1) s.insert(make_pair(1, i - 1)); for (int j = i; j < cnt; j++) { if (a[j] == 0) { if (i != j) { ret += sum * 1LL * q[j] * 1LL * q[i]; } else { ret += sum * 1LL * q[i] * 1LL * (q[i] + 1) / 2; } } else { if (use.find(a[j]) == use.end()) { int len = mp[a[j]].size(); for (int k = 0; k < len; k++) { int pos = mp[a[j]][k]; if (pos >= i) break; it = s.lower_bound(make_pair(pos + 1, 0)); if (it != s.begin()) { it--; if ((*it).second >= pos) { int pa = (*it).second, pb = (*it).first; sum -= diff(cum[pa] - cum[pb - 1]); s.erase(*it); if (pa > pos) { s.insert(make_pair(pos + 1, pa)); sum += diff(cum[pa] - cum[pos]); } if (pb < pos) { s.insert(make_pair(pb, pos - 1)); sum += diff(cum[pos - 1] - cum[pb - 1]); } } } } use.insert(a[j]); } ret += sum * 1LL * q[i]; } if (i != j) { if (!s.empty()) { it = s.end(); it--; if ((*it).second == i - 1) { int pos = cum[i - 1] - cum[(*it).first - 1]; ret += q[j] * 1LL * pos * 1LL * q[i] * 1LL * (q[i] - 1) / 2; } } } } } printf( %I64d n , ret); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, tmp; cin >> n; multiset<int> a; for (int i = 0; i < n; i++) { cin >> tmp; a.insert(tmp); } int ans = 0; while (!a.empty()) { int h = 0; while (a.lower_bound(h) != a.end()) { a.erase(a.lower_bound(h)); h++; } if (h) ans++; } cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:02:46 05/18/2016
// Design Name: MAIN
// Module Name: Y:/TEOCOA/EXPR8/TEST.v
// Project Name: EXPR8
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MAIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST;
// Inputs
reg clk_100;
reg Step_BTN;
reg rst;
//reg [2:0] SW;
// Outputs
//wire [7:0] LED;
wire [31:0] F;
// Instantiate the Unit Under Test (UUT)
MAIN uut (
.clk_100(clk_100),
.Step_BTN(Step_BTN),
.rst(rst),
//.SW(SW),
//.LED(LED)
.F(F)
);
initial begin
// Initialize Inputs
clk_100 = 1;
Step_BTN = 1;
rst = 1;
//SW = 0;
// Wait 100 ns for global reset to finish
#200;
rst = 0;
#100;
end
always #50 clk_100 = ~clk_100;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> ostream& operator<<(ostream& os, const pair<A, B>& x) { return os << ( << x.first << , << x.second << ) ; } const int MOD = 998244353; long long modex(long long a, long long p, long long m = MOD) { if (!p) return 1; if (p & 1) return a * modex(a, p - 1, m) % m; long long v = modex(a, p >> 1, m); return v * v % m; } namespace fft { const int mod = 998244353; const int gen = 3; vector<int> rev(1, 0), roots; int base = 0; void precompute(int nbase) { if (nbase <= base) return; rev.resize(1 << nbase); for (int i = 0; i < (1 << nbase); ++i) { rev[i] = rev[i >> 1] >> 1 | ((i & 1) << nbase - 1); } roots.resize(1 << nbase); for (; base < nbase; ++base) { int len = 1 << base; long long root = modex(gen, (mod - 1) >> base + 1, mod); roots[len] = 1; for (int i = 1; i < len; ++i) roots[len + i] = roots[len + i - 1] * root % mod; } } void fft(vector<int>& a) { int n = a.size(); assert((n & (n - 1)) == 0); int zeros = __builtin_ctz(n); precompute(zeros); int shift = base - zeros; for (int i = 0; i < n; ++i) { if (i < (rev[i] >> shift)) swap(a[i], a[rev[i] >> shift]); } for (int len = 1; len < n; len <<= 1) for (int i = 0; i < n; i += 2 * len) for (int j = 0; j < len; ++j) { int u = a[i + j], v = (long long)a[i + j + len] * roots[len + j] % mod; a[i + j] = u + v >= mod ? u + v - mod : u + v; a[i + j + len] = u - v < 0 ? u - v + mod : u - v; } } vector<int> multiply(vector<int> a, vector<int> b) { if (a.empty() || b.empty()) return {}; int sz = a.size() + b.size() - 1; int n = sz == 1 ? 1 : 1 << (32 - __builtin_clz(sz - 1)); bool eq = (a == b); a.resize(n); fft(a); if (eq) b = a; else { b.resize(n); fft(b); } long long inv = modex(n, mod - 2, mod); for (int i = 0; i < n; ++i) a[i] = (long long)a[i] * b[i] % mod * inv % mod; fft(a); reverse(a.begin() + 1, a.end()); a.resize(sz); return a; } vector<int> multiply(const vector<int>& a, const vector<int>& b, int m) { assert(m == mod); return multiply(a, b); } }; // namespace fft vector<int> B; vector<int> multiplyAll(int s, int e) { if (s == e) { return {1, B[s]}; } int m = (s + e) >> 1; auto a = multiplyAll(s, m); auto b = multiplyAll(m + 1, e); return fft::multiply(a, b); } int sub(int x, int y) { x -= y; if (x < 0) x += MOD; return x; } int main() { int n, k; scanf( %d%d , &n, &k); vector<int> A(n); B = vector<int>(n); for (int i = 0; i < n; ++i) { scanf( %d , &A[i]); A[i] %= MOD; } int Q; scanf( %d , &Q); while (Q--) { int t, q, a, b, d; scanf( %d%d%d%d , &t, &q, &a, &b); if (t == 1) { b %= MOD; for (int i = 0; i < n; ++i) B[i] = sub(q, A[i]); B[a - 1] = sub(q, b); } else { scanf( %d , &d); d %= MOD; for (int i = 0; i < n; ++i) B[i] = sub(q, A[i]); for (int i = a - 1; i < b; ++i) B[i] = sub(B[i], d); } auto p = multiplyAll(0, n - 1); printf( %d n , p[k]); } } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output rx_irq,
output tx_irq,
input uart_rxd,
output uart_txd
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_irq),
.tx_data(tx_data),
.tx_wr(tx_wr),
.tx_done(tx_irq)
);
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[0] == 1'b0);
parameter default_divisor = clk_freq/baud/16;
always @(posedge sys_clk) begin
if(sys_rst) begin
divisor <= default_divisor;
csr_do <= 32'd0;
end else begin
csr_do <= 32'd0;
if(csr_selected) begin
case(csr_a[0])
1'b0: csr_do <= rx_data;
1'b1: csr_do <= divisor;
endcase
if(csr_we) begin
if(csr_a[0] == 1'b1)
divisor <= csr_di[15:0];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; const int K = 23; const long long INF = 1e18; int id[N], a[N], b[N], w[N]; int n, m; vector<int> pos[N]; long long dp[N]; int ls[N * K], rs[N * K], rootcnt = 0; long long vs[N * K]; void copy(int root, int newroot) { ls[newroot] = ls[root]; rs[newroot] = rs[root]; vs[newroot] = vs[root]; } void updates(int root, int& newroot, int l, int r, int pos, int v) { newroot = ++rootcnt; copy(root, newroot); vs[newroot] += v; if (l == r || v == 0) return; int m = (l + r) >> 1; if (pos <= m) updates(ls[root], ls[newroot], l, m, pos, v); else updates(rs[root], rs[newroot], m + 1, r, pos, v); } long long querys(int lt, int rt, int l, int r, int a, int b) { if (l == a && r == b) { return vs[rt] - vs[lt]; } int m = (l + r) >> 1; if (b <= m) return querys(ls[lt], ls[rt], l, m, a, b); else if (a > m) return querys(rs[lt], rs[rt], m + 1, r, a, b); else { return querys(ls[lt], ls[rt], l, m, a, m) + querys(rs[lt], rs[rt], m + 1, r, m + 1, b); } } long long val[N << 2]; long long tag[N << 2]; void build(int root, int l, int r) { val[root] = -INF; tag[root] = 0; if (l == r) return; int m = (l + r) >> 1; build((root << 1), l, m); build((root << 1 | 1), m + 1, r); } void pushdown(int root) { long long c = tag[root]; tag[root] = 0; val[(root << 1)] += c; tag[(root << 1)] += c; val[(root << 1 | 1)] += c; tag[(root << 1 | 1)] += c; } void setv(int root, int l, int r, int pos, long long v) { if (l == r) { val[root] = v; return; } pushdown(root); int m = (l + r) >> 1; if (pos <= m) setv((root << 1), l, m, pos, v); else setv((root << 1 | 1), m + 1, r, pos, v); val[root] = max(val[(root << 1)], val[(root << 1 | 1)]); } void update(int root, int l, int r, int a, int b, long long v) { if (v == 0) return; if (a > b) return; if (l == a && r == b) { val[root] += v; tag[root] += v; return; } pushdown(root); int m = (l + r) >> 1; if (b <= m) update((root << 1), l, m, a, b, v); else if (a > m) update((root << 1 | 1), m + 1, r, a, b, v); else { update((root << 1), l, m, a, m, v); update((root << 1 | 1), m + 1, r, m + 1, b, v); } val[root] = max(val[(root << 1)], val[(root << 1 | 1)]); } long long query(int root, int l, int r, int a, int b) { if (a > b) return -INF; if (l == a && r == b) return val[root]; pushdown(root); int m = (l + r) >> 1; if (b <= m) return query((root << 1), l, m, a, b); else if (a > m) return query((root << 1 | 1), m + 1, r, a, b); else return max(query((root << 1), l, m, a, m), query((root << 1 | 1), m + 1, r, m + 1, b)); } bool hasAns() { int len = 0; for (int i = 1; i <= n && len < m; i++) { if (a[i] == b[len + 1]) len++; } return len == m; } int root[N]; long long lessSum(int l, int r, int v) { if (l > r || v <= 0) return 0; return querys(root[l - 1], root[r], 1, n, 1, v); } void solve() { scanf( %d , &n); root[0] = 0; for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) { scanf( %d , w + i); updates(root[i - 1], root[i], 1, n, a[i], max(0, w[i])); } scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d , b + i), id[b[i]] = i; for (int i = 1; i <= n; i++) { if (id[a[i]]) pos[id[a[i]]].push_back(i); } if (!hasAns()) { printf( NO n ); return; } printf( YES n ); for (int i = 1; i <= n; i++) dp[i] = -INF; build(1, 1, n); for (auto p : pos[m]) { dp[p] = lessSum(p + 1, n, b[m]) + w[p]; setv(1, 1, n, p, dp[p]); } for (int i = m - 1; i >= 1; i--) { vector<int> vec; for (auto j : pos[i + 1]) vec.push_back(j); for (auto j : pos[i]) vec.push_back(j); sort(vec.begin(), vec.end()); for (int j = (int)vec.size() - 2; j >= 0; j--) { update(1, 1, n, vec[j + 1], n, lessSum(vec[j] + 1, vec[j + 1] - 1, b[i])); if (a[vec[j]] == b[i]) { dp[vec[j]] = query(1, 1, n, vec[j + 1], n) + w[vec[j]]; if (w[vec[j]] > 0) { update(1, 1, n, vec[j + 1], n, w[vec[j]]); } } } for (int j = (int)vec.size() - 2; j >= 0; j--) { update(1, 1, n, vec[j + 1], n, -lessSum(vec[j] + 1, vec[j + 1] - 1, b[i])); if (a[vec[j]] == b[i]) { if (w[vec[j]] > 0) { update(1, 1, n, vec[j + 1], n, -w[vec[j]]); } } } for (auto j : pos[i + 1]) { setv(1, 1, n, j, -INF); } assert(val[1] == -INF); for (auto j : pos[i]) { setv(1, 1, n, j, dp[j]); } } long long ans = 0; for (int i = 1; i <= n; i++) ans += w[i]; ans -= val[1]; printf( %lld n , ans); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; void inout() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; } int main() { inout(); long long n, i, u, v; cin >> n; map<long long, long long> prv, nxt, cnt1, cnt2; vector<long long> ans(n + 5); for (i = 0; i < n; i++) { cin >> u >> v; prv[v] = u; nxt[u] = v; cnt1[u]++; cnt2[v]++; } for (auto k : cnt1) if (cnt1[k.first] > cnt2[k.first]) ans[1] = k.first; for (auto k : cnt2) if (cnt1[k.first] < cnt2[k.first]) ans[n] = k.first; i = 3; while (i <= n) { ans[i] = nxt[ans[i - 2]]; i += 2; } i = n + n % 2 - 2; while (i > 0) { ans[i] = prv[ans[i + 2]]; i -= 2; } for (i = 1; i <= n; i++) cout << ans[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int l, r, p, prim[100], cnt, a[4000000], n, f[4000000], ans; bool ok[4000000]; void DFS(int x, long long now) { if (x > cnt) return; while (now <= r) { DFS(x + 1, now); now = now * prim[x]; if (now <= r) a[++n] = now; } } int main() { scanf( %d%d%d , &l, &r, &p); for (int i = 2; i <= p; ++i) { bool OK = true; for (int j = 2; j * j <= i; ++j) if (i % j == 0) { OK = false; break; } if (OK) prim[++cnt] = i; } a[++n] = 1; DFS(1, 1); sort(a + 1, a + n + 1); for (int i = 2; i <= n; ++i) f[i] = p + 1; for (int q = 1; q <= p; ++q) { int now = 1; for (int i = 1; i <= n; ++i) { long long tmp = a[i] * q; while (now <= n && a[now] < tmp) ++now; if (now > n) break; if (a[now] == tmp && f[now] > f[i] + 1) { f[now] = f[i] + 1; if (f[now] + q <= p) ok[now] = 1; } } } for (int i = 1; i <= n; ++i) if (a[i] >= l && ok[i]) ++ans; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100000; struct node { int n; int i; node(int n, int i) : n(n), i(i) {} node() {} bool operator<(const node& n1) const { return n < n1.n; } bool is_happy() const { int a = n; while (a) { if (a % 10 != 7 && a % 10 != 4) return false; a /= 10; } return true; } }; node nodes[maxn]; int rev[maxn]; inline void sw(int i, int j, vector<pair<int, int> >& ans) { ans.push_back(pair<int, int>(nodes[i].i, nodes[j].i)); swap(nodes[i].i, nodes[j].i); rev[nodes[i].i] = i; rev[nodes[j].i] = j; } int main() { int n; scanf( %d , &n); bool sorted = true; int x = -1, prev; for (int i = 0; i < n; i++) { prev = x; scanf( %d , &x); if (prev > x) sorted = false; nodes[i] = node(x, i); } if (sorted) { printf( 0 n ); return 0; } sort(nodes, nodes + n); for (int i = 0; i < n; i++) { rev[nodes[i].i] = i; } int happy = -1; for (int i = 0; i < n; i++) { if (nodes[i].is_happy()) { happy = i; break; } } if (happy == -1) { printf( -1 n ); return 0; } vector<pair<int, int> > ans; for (int i = 0; i < n; i++) if (i != happy && nodes[i].i != i) { if (rev[i] != happy) sw(rev[i], happy, ans); sw(happy, i, ans); } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) { printf( %d %d n , ans[i].first + 1, ans[i].second + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, arr[300010], lft[300010], rgt[300010], mx = 0, cnt = 0; stack<long long> s1, s2; set<long long> st; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; for (int i = 0; i < n; i++) lft[i] = -1, rgt[i] = n; for (int i = 0; i < n; i++) { while (!s1.empty() && (arr[i] % arr[s1.top()])) rgt[s1.top()] = i, s1.pop(); s1.push(i); } for (int i = n - 1; i >= 0; i--) { while (!s2.empty() && (arr[i] % arr[s2.top()])) lft[s2.top()] = i, s2.pop(); s2.push(i); } for (int i = 0; i < n; i++) mx = max(mx, rgt[i] - lft[i] - 2); for (int i = 0; i < n; i++) if (rgt[i] - lft[i] - 2 == mx) st.insert(lft[i] + 2); cout << st.size() << << mx << n ; for (auto u : st) cout << u << ; return 0; } |
module inport #(parameter X_LOCAL = 2, parameter Y_LOCAL = 2)
(
input wire clka,
input wire rsta,
input wire [1:0] diff_pair_din,
input wire [47:0] channel_din,
output wire request_dout,
output wire x_hit_dout,
output wire y_hit_dout,
output wire [47:0] packet_dout
);
//---- Signal declaration
// Port flow_handler
wire request_unreg;
// Segmentation Registers
reg [47:0] input_pipe_reg = 48'b0;
// Register for arbitration request
reg request_reg;
// Port flow_handler
input_flow_handler inport_flow_handler
(
.clka (clka),
.rsta (rsta),
.diff_pair_p(diff_pair_din[1]),
.diff_pair_n(diff_pair_din[0]),
.pipe_en (request_unreg)
); // flow_handler
// Registered outputs
assign packet_dout = input_pipe_reg[47:0];
assign request_dout = request_reg;
// Derived outputs
assign x_hit_dout = (input_pipe_reg[47:44] == X_LOCAL) ? 1'b1 : 1'b0;
assign y_hit_dout = (input_pipe_reg[43:40] == Y_LOCAL) ? 1'b1 : 1'b0;
//---- Memory Elements
// Segmentation Registers
always @(posedge clka)
if (request_unreg)
input_pipe_reg <= channel_din;
// Register for arbitration request
always @(posedge clka)
request_reg <= request_unreg;
endmodule
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sync_clock_converter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_axic_sync_clock_converter # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex6",
parameter integer C_PAYLOAD_WIDTH = 32,
parameter integer C_S_ACLK_RATIO = 1,
parameter integer C_M_ACLK_RATIO = 1 ,
parameter integer C_MODE = 0 // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE,
// Slave side
input wire S_ACLK,
input wire S_ARESETN,
input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
input wire S_VALID,
output wire S_READY,
// Master side
input wire M_ACLK,
input wire M_ARESETN,
output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
output wire M_VALID,
input wire M_READY
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam [1:0] ZERO = 2'b10;
localparam [1:0] ONE = 2'b11;
localparam [1:0] TWO = 2'b01;
localparam [1:0] INIT = 2'b00;
localparam integer P_LIGHT_WT = 0;
localparam integer P_FULLY_REG = 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru
assign M_PAYLOAD = S_PAYLOAD;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end else begin : gen_sync_clock_converter
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire slow_aclk;
wire slow_areset;
wire s_areset_r;
wire m_areset_r;
reg s_tready_r;
wire s_tready_ns;
reg m_tvalid_r;
wire m_tvalid_ns;
reg [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;
reg [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;
wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns;
wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns;
reg m_tready_hold;
wire m_tready_sample;
wire load_tpayload;
wire load_tstorage;
wire load_tpayload_from_tstorage;
reg [1:0] state;
reg [1:0] next_state;
reg s_aresetn_r = 1'b0; // Reset delay register
always @(posedge S_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
s_aresetn_r <= 1'b0;
end else begin
s_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign s_areset_r = ~s_aresetn_r;
reg m_aresetn_r = 1'b0; // Reset delay register
always @(posedge M_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
m_aresetn_r <= 1'b0;
end else begin
m_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign m_areset_r = ~m_aresetn_r;
if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi
assign slow_aclk = M_ACLK;
end else begin : gen_slowclk_si
assign slow_aclk = S_ACLK;
end
assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;
assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;
assign s_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;
assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign m_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;
// Output flop for S_READY, value is encoded into state machine.
assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];
always @(posedge S_ACLK) begin
if (s_areset_r) begin
s_tready_r <= 1'b0;
end
else begin
s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;
end
end
assign S_READY = s_tready_r;
// Output flop for M_VALID
assign m_tvalid_ns = next_state[0];
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tvalid_r <= 1'b0;
end
else begin
m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;
end
end
assign M_VALID = m_tvalid_r;
// Hold register for M_READY when M_ACLK is fast.
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tready_hold <= 1'b0;
end
else begin
m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;
end
end
assign m_tready_sample = (M_READY ) | m_tready_hold;
// Output/storage flops for PAYLOAD
assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :
load_tpayload_from_tstorage ? m_tstorage_r :
S_PAYLOAD;
assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;
always @(posedge slow_aclk) begin
m_tpayload_r <= m_tpayload_ns;
m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;
end
assign M_PAYLOAD = m_tpayload_r;
// load logic
assign load_tstorage = C_MODE && (state != TWO);
assign load_tpayload = m_tready_sample || (state == ZERO);
assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;
// State machine
always @(posedge slow_aclk) begin
state <= next_state;
end
always @* begin
if (slow_areset) begin
next_state = INIT;
end else begin
case (state)
INIT: begin
next_state = ZERO;
end
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
next_state = C_MODE ? ONE : TWO; // Push from empty
end
else begin
next_state = ZERO;
end
end
// One transaction stored locally
ONE: begin
if (C_MODE == 0) begin
next_state = TWO; // State ONE is inaccessible when C_MODE=0
end
else if (m_tready_sample & ~S_VALID) begin
next_state = ZERO; // Read out one so move to ZERO
end
else if (~m_tready_sample & S_VALID) begin
next_state = TWO; // Got another one so move to TWO
end
else begin
next_state = ONE;
end
end
// Storage registers full
TWO: begin
if (m_tready_sample) begin
next_state = C_MODE ? ONE : ZERO; // Pop from full
end
else begin
next_state = TWO;
end
end
endcase // case (state)
end
end
end // gen_sync_clock_converter
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long extgcd(long long a, long long b, long long& x, long long& y) { if (b == 0) { x = 1; y = 0; return a; } long long x1, y1; long long d = extgcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool isPowerOfTwo(long long n) { if (n == 0) return false; return (ceil(log2(n)) == floor(log2(n))); } long long powm(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return res; } long long divide(long long a, long long b) { return (a % 1000000007) * powm(b, 1000000007 - 2) % 1000000007; } long long mul(long long a, long long b) { return ((a % 1000000007) * (b % 1000000007)) % 1000000007; } long long add(long long a, long long b) { return (a % 1000000007 + b % 1000000007) % 1000000007; } long long Totfun(long long n) { long long z = n; if (n % 2 == 0) { while (n % 2 == 0) { n /= 2; } z /= 2; } for (long long i = 3; i <= sqrt(n); i += 2) { if (isPrime(i) && n % i == 0) { while (n % i == 0) { n /= i; } z -= z / i; } } if (n > 1) { z -= z / n; } return z; } long long fact[100001]; long long nCr(long long n, long long r) { if (r > n || r < 0) return 0; long long z = fact[n]; z = mul(z, powm(fact[n - r], 1000000007 - 2)); z = mul(z, powm(fact[r], 1000000007 - 2)); return z; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, a = 0, b = 0, c = 0, z = 1; cin >> n; string s; cin >> s; for (long long i = 0; i < n; i++) { if (s[i] == a ) a = add(a, z); else if (s[i] == b ) b = add(b, a); else if (s[i] == c ) c = add(c, b); else { c = add(3 * c, b); b = add(3 * b, a); a = add(3 * a, z); z = mul(z, 3); } } cout << c << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, l, skg = 0, skr = 0, sky = 0, skb = 0, kr = 0, kg = 0, kb = 0, ky = 0, pg = 0, pr = 0, py = 0, pb = 0; char s[120], r[4]; scanf( %s , s); l = strlen(s); if (l % 4 == 0) { for (i = 0; i < l; i += 4) { kg = 0; kb = 0; ky = 0; kr = 0; if (s[i] == G || s[i + 1] == G || s[i + 2] == G || s[i + 3] == G ) kg++; if (s[i] == B || s[i + 1] == B || s[i + 2] == B || s[i + 3] == B ) kb++; if (s[i] == Y || s[i + 1] == Y || s[i + 2] == Y || s[i + 3] == Y ) ky++; if (s[i] == R || s[i + 1] == R || s[i + 2] == R || s[i + 3] == R ) kr++; if (kg == 0) skg++; if (kb == 0) skb++; if (ky == 0) sky++; if (kr == 0) skr++; } printf( %d %d %d %d , skr, skb, sky, skg); return 0; } else { for (i = 0; i < l; i++) { if (s[i] == G ) { pg = i + 1; if (pg > 4) { pg = pg % 4; if (pg == 0) pg = 4; } } if (s[i] == Y ) { py = i + 1; if (py > 4) { py = py % 4; if (py == 0) py = 4; } } if (s[i] == R ) { pr = i + 1; if (pr > 4) { pr = pr % 4; if (pr == 0) pr = 4; } } if (s[i] == B ) { pb = i + 1; if (pb > 4) { pb = pb % 4; if (pb == 0) pb = 4; } } } if (pg == 0) { for (i = 1; i <= 4; i++) { if (pr != i && py != i && pb != i) { pg = i; break; } } } if (pb == 0) { for (i = 1; i <= 4; i++) { if (pr != i && py != i && pg != i) { pb = i; break; } } } if (pr == 0) { for (i = 1; i <= 4; i++) { if (pg != i && py != i && pb != i) { pr = i; break; } } } if (py == 0) { for (i = 1; i <= 4; i++) { if (pr != i && pg != i && pb != i) { py = i; break; } } } for (i = 0; i < (l / 4) * 4; i += 4) { kg = 0; kb = 0; ky = 0; kr = 0; if (s[i] == G || s[i + 1] == G || s[i + 2] == G || s[i + 3] == G ) kg++; if (s[i] == B || s[i + 1] == B || s[i + 2] == B || s[i + 3] == B ) kb++; if (s[i] == Y || s[i + 1] == Y || s[i + 2] == Y || s[i + 3] == Y ) ky++; if (s[i] == R || s[i + 1] == R || s[i + 2] == R || s[i + 3] == R ) kr++; if (kg == 0) skg++; if (kb == 0) skb++; if (ky == 0) sky++; if (kr == 0) skr++; } for (i = (l / 4) * 4; i < (l / 4) * 4 + l % 4; i++) { if (s[i] == ! ) { if ((i - (l / 4) * 4) + 1 == pg) skg++; if ((i - (l / 4) * 4) + 1 == py) sky++; if ((i - (l / 4) * 4) + 1 == pr) skr++; if ((i - (l / 4) * 4) + 1 == pb) skb++; } } printf( %d %d %d %d , skr, skb, sky, skg); return 0; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5005; int id[maxn][maxn]; char s[maxn][maxn]; char c[maxn]; int l[maxn], r[maxn], u[maxn], d[maxn]; int n, m, t; void init() { int i, j; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { l[id[i][j]] = id[i][j - 1]; r[id[i][j]] = id[i][j + 1]; u[id[i][j]] = id[i - 1][j]; d[id[i][j]] = id[i + 1][j]; } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (s[i][j] == . ) { r[l[id[i][j]]] = r[id[i][j]]; l[r[id[i][j]]] = l[id[i][j]]; u[d[id[i][j]]] = u[id[i][j]]; d[u[id[i][j]]] = d[id[i][j]]; } } } } void del(int k) { r[l[k]] = r[k]; l[r[k]] = l[k]; u[d[k]] = u[k]; d[u[k]] = d[k]; } int dfs(int cur) { if (cur == 0) return 0; del(cur); if (c[cur] == U ) return dfs(u[cur]) + 1; if (c[cur] == D ) return dfs(d[cur]) + 1; if (c[cur] == L ) return dfs(l[cur]) + 1; if (c[cur] == R ) return dfs(r[cur]) + 1; return 0; } void work() { int i, j; int ans, max = 0, num; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (s[i][j] != . ) { init(); ans = dfs(id[i][j]); if (ans > max) { max = ans; num = 1; } else if (ans == max) num++; } } } printf( %d %d n , max, num); } int main() { int i, j; while (scanf( %d%d , &n, &m) != EOF) { for (i = 1; i <= n; i++) scanf( %s , &s[i][1]); t = 0; memset(id, 0, sizeof(id)); for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { t++; id[i][j] = t; c[t] = s[i][j]; } } work(); } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; void output(long long x) { if (x < 0) putchar( - ), x = -x; if (x == 0) { putchar( 0 ); return; } int a[20], num = 0; while (x) a[++num] = x % 10, x /= 10; while (num > 0) putchar( 0 + a[num--]); } inline long long myInt() { char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); int flag = 1; if (c == - ) flag = -1, c = getchar(); long long x = 0; while (isdigit(c)) { x = (x * 10) + (c - 0 ); c = getchar(); } if (-1 == flag) return -x; return x; } const long long mod = 1000000007; const int N = 2005; int h, w, n; struct node { int x, y; }; node a[N]; long long f[N]; long long p[200005]; long long myPow(long long x, long long y) { long long ans = 1; while (y) { if (y & 1) ans = ans * x % mod; x = x * x % mod; y >>= 1; } return ans; } long long reverse(long long x) { return myPow(x, mod - 2); } long long C(long long x, long long y) { if (x < y) return 0; if (x == y || y == 0) return 1; return p[x] * reverse(p[y] * p[x - y] % mod) % mod; } long long cal(node from, node to) { int xx = ((from.x - to.x) >= 0 ? (from.x - to.x) : -(from.x - to.x)); int yy = ((from.y - to.y) >= 0 ? (from.y - to.y) : -(from.y - to.y)); return C(xx + yy, xx); } int cmp(node a, node b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } int main() { h = myInt(); w = myInt(); n = myInt(); for (int i = 1; i <= n; i++) { a[i].x = myInt(); a[i].y = myInt(); } p[0] = 1; for (int i = 1; i <= 200000; i++) { p[i] = p[i - 1] * i % mod; } sort(a + 1, a + n + 1, cmp); node E; E.x = h; E.y = w; for (int i = n; i >= 1; i--) { for (int j = i + 1; j <= n; j++) { if (a[i].x <= a[j].x && a[i].y <= a[j].y) { f[i] -= cal(a[i], a[j]) * f[j]; f[i] %= mod; } } f[i] += cal(a[i], E); f[i] %= mod; } node S; S.x = 1; S.y = 1; long long ans = 0; for (int i = 1; i <= n; i++) { ans += f[i] * cal(S, a[i]); ans %= mod; } if (ans < 0) ans += mod; ans = cal(S, E) - ans; ans %= mod; if (ans < 0) ans += mod; printf( %d n , (int)ans); } |
#include <bits/stdc++.h> using namespace std; const int N = 30; int n, m, T; string s[N], t[N]; int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < m; i++) cin >> t[i]; cin >> T; while (T--) { int x; cin >> x; x--; cout << s[x % n] << t[x % m] << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O311A_PP_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; string FILE_NAME = testcase.A ; string NAME; string itos(int n) { stringstream ss; ss << n; return ss.str(); } const int dx[] = {0, 1, 0, -1}; const int dy[] = {-1, 0, 1, 0}; bool is_right(vector<pair<int, int> > p) { vector<int> len2(3, 0); for (int i = 0; i < (3); i++) { int x0 = p[i].first, y0 = p[i].second; int x1 = p[(i + 1) % 3].first, y1 = p[(i + 1) % 3].second; len2[i] = (x0 - x1) * (x0 - x1) + (y0 - y1) * (y0 - y1); } sort(len2.begin(), len2.end()); return ((len2[2] == len2[0] + len2[1]) && (sqrt(len2[2]) + 1e-8 < sqrt(len2[0]) + sqrt(len2[1]))); } bool search_right_triangle(vector<pair<int, int> > p) { for (int i = 0; i < (3); i++) { for (int k = 0; k < (4); k++) { vector<pair<int, int> > q = p; q[i].first += dx[k]; q[i].second += dy[k]; if (is_right(q)) return true; } } return false; } int main() { vector<pair<int, int> > p(3); for (int i = 0; i < (3); i++) { cin >> p[i].first >> p[i].second; } if (is_right(p)) { cout << RIGHT << endl; } else if (search_right_triangle(p)) { cout << ALMOST << endl; } else { cout << NEITHER << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; const int LIM = 100005; long long power(long long x, long long n) { long long res = 1; while (n) { if (n & 1) { res = res * x % mod; } x = x * x % mod; n >>= 1; } return (res % mod); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 0; cin >> t; while (t--) { long long n = 0, x = 0, y = 0; cin >> n >> x >> y; vector<long long> v; long long dif = y - x; long long c = n - 1; long long d = 0; for (c = n - 1; c >= 1; c--) { if (dif % c == 0) { d = dif / c; break; } } for (long long i = x; i <= y; i += d) { v.push_back(i); n--; } long long now = x - d; for (; n > 0;) { if (now <= 0) break; else { v.push_back(now); now -= d; n--; } } now = y + d; for (; n > 0;) { if (now <= 0) break; else { v.push_back(now); now += d; n--; } } sort(v.begin(), v.end()); for (long long i = 0; i < v.size(); i++) { cout << v[i] << ; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; bool a[20][2][1 << 17]; int ans = 1234, ami, apl; void solve(int ind, int mx, int mi, int pl, int res) { if (ind > 18) { return; } if (mx == 0) { if (res < ans) { ans = res; ami = mi; apl = pl; } return; } for (int j = 0; j < (int)(2); ++j) for (int i = 0; i < (int)(mx + 1); ++i) { a[ind + 1][j][i] = false; } bool ok = true; for (int j = 0; j < (int)(2); ++j) for (int i = 1; i <= mx; i += 2) if (a[ind][j][i]) { ok = false; } int nmx = 0; if (ok) { for (int j = 0; j < (int)(2); ++j) for (int i = 0; i < (int)(mx + 1); ++i) if (a[ind][j][i]) { int ni = i >> 1; if (ni != 0) { a[ind + 1][j][ni] = true; nmx = max(nmx, ni); } } solve(ind + 1, nmx, mi, pl, res); } else { for (int i = 0; i < (int)(mx + 1); ++i) if (a[ind][0][i]) { int ni = i >> 1; if (ni != 0) { a[ind + 1][0][ni] = true; nmx = max(nmx, ni); } } for (int i = 0; i < (int)(mx + 1); ++i) if (a[ind][1][i]) { int ni = i; if (ni & 1) { ++ni; } ni >>= 1; if (ni != 0) { a[ind + 1][1][ni] = true; nmx = max(nmx, ni); } } solve(ind + 1, nmx, mi, pl | (1 << ind), res + 1); nmx = 0; for (int j = 0; j < (int)(2); ++j) for (int i = 0; i < (int)(mx + 1); ++i) { a[ind + 1][j][i] = false; } for (int i = 0; i < (int)(mx + 1); ++i) if (a[ind][1][i]) { int ni = i >> 1; if (ni != 0) { a[ind + 1][1][ni] = true; nmx = max(nmx, ni); } } for (int i = 0; i < (int)(mx + 1); ++i) if (a[ind][0][i]) { int ni = i; if (ni & 1) { ++ni; } ni >>= 1; if (ni != 0) { a[ind + 1][0][ni] = true; nmx = max(nmx, ni); } } solve(ind + 1, nmx, mi | (1 << ind), pl, res + 1); } } int main() { scanf( %d , &n); int mx = 0; for (int i = 0; i < (int)(n); ++i) { int x; scanf( %d , &x); if (x > 0) { a[0][0][x] = true; mx = max(mx, x); } if (x < 0) { a[0][1][-x] = true; mx = max(mx, -x); } } solve(0, mx, 0, 0, 0); printf( %d n , ans); for (int i = 0; i < (int)(20); ++i) if (apl & (1 << i)) { printf( %d , 1 << i); } else if (ami & (1 << i)) { printf( %d , -(1 << i)); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR4BB_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_BLACKBOX_V
|
module computer(
RESET,
CLOCK_50,
PS2_CLK,
PS2_DAT,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_CLK,
LED,
VGA_B,
VGA_G,
VGA_R
);
input wire RESET;
input wire CLOCK_50;
input wire PS2_CLK;
input wire PS2_DAT;
output wire VGA_HS;
output wire VGA_VS;
output wire VGA_BLANK_N;
output wire VGA_CLK;
output wire [7:0] LED;
output wire [7:0] VGA_B;
output wire [7:0] VGA_G;
output wire [7:0] VGA_R;
wire scan_ready;
wire [7:0] scan_code;
wire w_reset;
wire [15:0] SYNTHESIZED_WIRE_31;
wire [15:0] SYNTHESIZED_WIRE_32;
wire SYNTHESIZED_WIRE_5;
wire [14:0] SYNTHESIZED_WIRE_6;
wire [15:0] SYNTHESIZED_WIRE_7;
wire [7:0] SYNTHESIZED_WIRE_33;
wire [12:0] SYNTHESIZED_WIRE_9;
wire [15:0] SYNTHESIZED_WIRE_11;
wire [15:0] SYNTHESIZED_WIRE_13;
wire [14:0] SYNTHESIZED_WIRE_34;
wire [15:0] SYNTHESIZED_WIRE_17;
wire [10:0] SYNTHESIZED_WIRE_18;
wire [10:0] SYNTHESIZED_WIRE_19;
wire memory_ready;
wire memory_ready_n;
wire reset_n;
wire clk_25;
wire [23:0] SYNTHESIZED_WIRE_28;
assign VGA_CLK = clk_25;
assign reset_n = ~RESET;
assign memory_ready_n = ~memory_ready;
assign w_reset = memory_ready_n | reset_n;
clock_25 pixel_clock(
.CLOCK_50(CLOCK_50),
.CLOCK_25(clk_25));
ps2decoder kb_decoder(
.reset(w_reset),
.i_clock(PS2_CLK),
.i_data(PS2_DAT),
.scan_ready(scan_ready),
.scan_code(scan_code));
ascii b2v_ascii(
.clk(CLOCK_50),
.scan_ready(scan_ready),
.scan_code(scan_code),
.ascii(SYNTHESIZED_WIRE_33));
cpu b2v_cpu_inst(
.clk(CLOCK_50),
.reset(w_reset),
.inM(SYNTHESIZED_WIRE_31),
.instruction(SYNTHESIZED_WIRE_32),
.writeM(SYNTHESIZED_WIRE_5),
.addressM(SYNTHESIZED_WIRE_6),
.areg(SYNTHESIZED_WIRE_11),
.dreg(SYNTHESIZED_WIRE_13),
.outM(SYNTHESIZED_WIRE_7),
.pc(SYNTHESIZED_WIRE_34));
memory b2v_data_memory(
.clk(CLOCK_50),
.load(SYNTHESIZED_WIRE_5),
.address(SYNTHESIZED_WIRE_6),
.in(SYNTHESIZED_WIRE_7),
.keyboard(SYNTHESIZED_WIRE_33),
.screen_read_address(SYNTHESIZED_WIRE_9),
.ready(memory_ready),
.out(SYNTHESIZED_WIRE_31),
.read_value(SYNTHESIZED_WIRE_17));
leds b2v_debug_leds(
.count(scan_code),
.led_0(LED[0]),
.led_1(LED[1]),
.led_2(LED[2]),
.led_3(LED[3]),
.led_4(LED[4]),
.led_5(LED[5]),
.led_6(LED[6]),
.led_7(LED[7]));
frame_buffer b2v_fb(
.clk(CLOCK_50),
.areg(SYNTHESIZED_WIRE_11),
.data_register(SYNTHESIZED_WIRE_31),
.dreg(SYNTHESIZED_WIRE_13),
.instruction(SYNTHESIZED_WIRE_32),
.keyboard(SYNTHESIZED_WIRE_33),
.pc(SYNTHESIZED_WIRE_34),
.read_value(SYNTHESIZED_WIRE_17),
.vga_h(SYNTHESIZED_WIRE_18),
.vga_v(SYNTHESIZED_WIRE_19),
.pixel_out(SYNTHESIZED_WIRE_28),
.read_address(SYNTHESIZED_WIRE_9));
instruction_memory b2v_program_memory(
.clk(CLOCK_50),
.read_address(SYNTHESIZED_WIRE_34),
.q(SYNTHESIZED_WIRE_32));
vga_controller b2v_vga(
.reset(w_reset),
.sys_clk(w_reset),
.vga_clk(VGA_CLK),
.pixel(SYNTHESIZED_WIRE_28),
.blank_n(VGA_BLANK_N),
.HS(VGA_HS),
.VS(VGA_VS),
.blue(VGA_B),
.green(VGA_G),
.next_pixel_h(SYNTHESIZED_WIRE_18),
.next_pixel_v(SYNTHESIZED_WIRE_19),
.red(VGA_R));
endmodule
|
#include <bits/stdc++.h> using namespace std; void cline() { cout << n ; } template <typename T, typename... V> void cline(T t, V... v) { cout << t; if (sizeof...(v)) cout << ; cline(v...); } void cspc() { cout << ; } template <typename T, typename... V> void cspc(T t, V... v) { cout << t; if (sizeof...(v)) cout << ; cspc(v...); } int n; int a[105]; int dp[104][52][52][2]; int calc(int indx, int even, int odd, int pre) { if (indx == n) return 0; if (dp[indx][even][odd][pre] != -1) return dp[indx][even][odd][pre]; if (indx == 0) { if (a[indx] == 0) { if (even == 0) { return dp[indx][even][odd][pre] = calc(indx + 1, even, odd - 1, 1); } else if (odd == 0) { return dp[indx][even][odd][pre] = calc(indx + 1, even - 1, odd, 0); } else { return dp[indx][even][odd][pre] = min(calc(indx + 1, even, odd - 1, 1), calc(indx + 1, even - 1, odd, 0)); } } else { return dp[indx][even][odd][pre] = calc(indx + 1, even, odd, a[indx] % 2); } } else { if (a[indx] == 0) { if (even == 0) { if (pre % 2 == 0) { return dp[indx][even][odd][pre] = calc(indx + 1, even, odd - 1, 1) + 1; } else { return dp[indx][even][odd][pre] = calc(indx + 1, even, odd - 1, 1); } } else if (odd == 0) { if (pre % 2 == 1) { return dp[indx][even][odd][pre] = calc(indx + 1, even - 1, odd, 0) + 1; } else { return dp[indx][even][odd][pre] = calc(indx + 1, even - 1, odd, 0); } } else { if (pre % 2 != 0) { return dp[indx][even][odd][pre] = min(calc(indx + 1, even, odd - 1, 1), calc(indx + 1, even - 1, odd, 0) + 1); } else { return dp[indx][even][odd][pre] = min(calc(indx + 1, even, odd - 1, 1) + 1, calc(indx + 1, even - 1, odd, 0)); } } } else { if (a[indx] % 2 != pre % 2) { return dp[indx][even][odd][pre] = calc(indx + 1, even, odd, a[indx] % 2) + 1; } else { return dp[indx][even][odd][pre] = calc(indx + 1, even, odd, a[indx] % 2); } } } } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; int even = n / 2, odd = (n + 1) / 2; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] % 2 == 0) even--; else odd--; if (a[i] == 0) even++; } for (int in1 = 0; in1 < 104; in1++) { for (int in2 = 0; in2 < 52; in2++) { for (int in3 = 0; in3 < 52; in3++) { dp[in1][in2][in3][0] = -1; dp[in1][in2][in3][1] = -1; } } } cspc(calc(0, even, odd, 0)); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; int main() { int n, co = 1; std::vector<pair<long long, long long>> v; cin >> n; for (int i = 0; i < n; i++) { long long a, b; cin >> a >> b; v.push_back(make_pair(a, b)); } for (int i = 1; i < n; i++) { if (v[i].first - v[i].second > v[i - 1].first) { co++; } else if (v[i].first + v[i].second < v[i + 1].first) { v[i].first = v[i].first + v[i].second; co++; } else if (i == n - 1) { co++; } } cout << co; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 107; int n, k; int f[N][N]; int main() { int i, j, tmp; bool ok = 0; cin >> k; f[1][2] = f[2][1] = 1; tmp = 0; for (i = 3; i <= 100; i++) { f[1][i] = f[i][1] = 1; for (j = 2; j < i; j++) { if (tmp + j - 1 > k) break; tmp += j - 1; f[i][j] = f[j][i] = 1; if (tmp == k) { ok = 1; break; } } if (ok) break; } cout << i << endl; k = i; for (i = 1; i <= k; i++) { for (j = 1; j < k; j++) { cout << f[i][j]; } cout << f[i][k] << endl; } return 0; } |
module hazardcontroller(clk,rsd,rsd2,rtd,rtd2,rse,rse2,rte,rte2,branchd,branchd2,regwritee,regwritee2,memtorege,memtorege2,regwritem,regwritem2,
memtoregm,memtoregm2,regwritew,regwritew2,writerege,writerege2,writeregm,writeregm2,writeregw,writeregw2,stalld,stalld2,
stallf,stallf2,stalle,stalle2,stallm,stallm2,stallw,stallw2,flushe,flushe2,forwardad,forwardad2,forwardbd,forwardbd2,forwardae,forwardae2,forwardbe,forwardbe2,
memwritem,memwritem2,memwritee,memwritee2,hit,hit2,miss,miss2,dirty,dirty2,we2,we2_2,we3,we3_2,multen,multen2,multready,multready2,swstalle,lwstalle,branchstalld);
input clk,branchd,regwritee,regwritem,regwritew,memtorege,memtoregm,hit,miss,dirty,memwritem,memwritee,multen,multready;
input clk,branchd2,regwritee2,regwritem2,regwritew2,memtorege2,memtoregm2,hit2,miss2,dirty2,memwritem2,memwritee2,multen2,multready2;
input [4:0] rsd,rtd,rse,rte,writerege,writeregm,writeregw;
input [4:0] rsd2,rtd2,rse2,rte2,writerege2,writeregm2,writeregw2;
output reg stallf,stalld,stalle,stallm,stallw,flushe,we2,we3;
output reg stallf2,stalld2,stalle2,stallm2,stallw2,flushe2,we2_2,we3_2;
output reg [1:0] forwardad,forwardbd;
output reg [1:0] forwardad2,forwardbd2;
output reg [2:0] forwardae,forwardbe;
output reg [2:0] forwardae2,forwardbe2;
output reg swstalle,lwstalle,branchstalld;
reg lwstalld;
reg[5:0] count = 6'd20; // Used for 20 cycle main memory stall count
initial begin
count<=6'd20;
lwstalld <= 1'b0;
branchstalld <= 1'b0;
flushe <= 1'b0;
stalld <= 1'b0;
stallf <= 1'b0;
stalle <= 1'b0;
stallm <= 1'b0;
stallw <= 1'b0;
lwstalle <= 1'b0;
swstalle <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
forwardad <= 2'b0;
forwardbd <= 2'b0;
forwardae <= 3'b00;
forwardbe <= 3'b00;
flushe2 <= 1'b0;
stalld2 <= 1'b0;
stallf2 <= 1'b0;
stalle2 <= 1'b0;
stallm2 <= 1'b0;
stallw2 <= 1'b0;
we2_2 <= 1'b0;
we3_2 <= 1'b0;
forwardad2 <= 2'b0;
forwardbd2 <= 2'b0;
forwardae2 <= 3'b00;
forwardbe2 <= 3'b00;
end
// forwarding sources to D stage (branch equality)
always @( rsd, rsd2, rtd, rtd2, writeregm, regwritem, writeregm2, regwritem2 ) begin
forwardad <= 2'b00; forwardbd <= 2'b00;
forwardad2 <= 2'b00; forwardbd2 <= 2'b00;
if (rsd !=0 & (rsd == writeregm) & regwritem) // 1-->5
forwardad <= 2'b01;
else if (rtd !=0 & (rtd == writeregm) & regwritem) // 1-->5
forwardbd <= 2'b01;
if (rsd !=0 & (rsd == writeregm2) & regwritem2) // 1-->6
forwardad <= 2'b10;
else if (rtd !=0 & (rtd == writeregm2) & regwritem2) // 1-->6
forwardbd <= 2'b10;
if (rsd2 !=0 & (rsd2 == writeregm) & regwritem) // 2-->5
forwardad2 <= 2'b10;
else if (rtd2 !=0 & (rtd2 == writeregm) & regwritem) // 2-->5
forwardbd2 <= 2'b10;
if (rsd2 !=0 & (rsd2 == writeregm2) & regwritem2) // 2-->6
forwardad2 <= 2'b01;
else if (rtd2 !=0 & (rtd2 == writeregm2) & regwritem2) // 2-->6
forwardbd2 <= 2'b01;
end
// forwarding sources to E stage (ALU)
always @( rse, rse2, rte, rte2, writeregm, regwritem, writeregw, regwritew, regwritee ) begin
forwardae <= 2'b00; forwardbe <= 2'b00;
forwardae2 <= 2'b00; forwardbe2 <= 2'b00;
//if (rse != 0) begin
if ((rse == writeregm2) & regwritem2) // 4-->1
forwardae <= 3'b011;
else if ((rse == writeregm) & regwritem) // 3-->1
forwardae <= 3'b010;
else if ((rse == writeregw2) & regwritew2) // 6-->1
forwardae <= 3'b100;
else if ((rse == writeregw) & regwritew) // 5-->1
forwardae <= 3'b001;
if ((rse2 == writerege) & regwritee) // 1-->2
forwardae2 <= 3'b011;
else if ((rse2 == writeregm2) & regwritem2) // 4-->2
forwardae2 <= 3'b010;
else if ((rse2 == writeregm) & regwritem) // 3-->2
forwardae2 <= 3'b100;
else if ((rse2 == writeregw2) & regwritew2) // 6-->2
forwardae2 <= 3'b001;
else if ((rse2 == writeregw) & regwritew) // 5-->2
forwardae2 <= 3'b101;
//end
//if (rte != 0) begin
if ((rte == writeregm2) & regwritem2) // 4-->1
forwardbe <= 3'b011;
else if ((rte == writeregm) & regwritem) // 3-->1
forwardbe <= 3'b010;
else if ((rte == writeregw2) & regwritew2) // 6-->1
forwardbe <= 3'b100;
else if ((rte == writeregw) & regwritew) // 5-->1
forwardbe <= 3'b001;
if ((rte2 == writerege) & regwritee) // 1-->2
forwardbe2 <= 3'b011;
else if ((rte2 == writeregm2) & regwritem2) // 4-->2
forwardbe2 <= 3'b010;
else if ((rte2 == writeregm) & regwritem) // 3-->2
forwardbe2 <= 3'b100;
else if ((rte2 == writeregw2) & regwritew2) // 6-->2
forwardbe2 <= 3'b001;
else if ((rte2 == writeregw) & regwritew) // 5-->2
forwardbe2 <= 3'b101;
//end
end
// stall for cache
always @(posedge clk, memtoregm, memwritem) begin
if ((memtoregm || memwritem) && count>6'd19) begin
stallm = 1'b1;
count = count - 1;
end
else if ((memtoregm || memwritem) && count>6'd0) begin // Need to wait 1 cycle before valid dirty, hit, miss
if ((((miss || miss2) && dirty) || count>6'd18) || ((!hit || !hit2) && dirty && memtoregm)) begin
stallm = 1'b1;
count = count - 6'b1;
end
else if ((miss || miss2) && count==6'd1) begin
we2 = 1'b1;
count = count - 6'd1;
end
else if ((!hit || !hit2) && count==6'd1) begin
we3 = 1'b1;
count = count - 6'd1;
end
else if ((miss || miss2) || (!hit || !hit2))
count = 6'd0; // No write to main memory needed, just read, so no 20 cycles
end
else begin
we2 = 1'b0;
we3 = 1'b0;
stallm = 1'b0;
count = 6'd20;
end
end
// stalls
always @( memtorege, memwritee, rte, rse, rte, rtd, branchd, regwritee, writerege, rsd, memtoregm, writeregm, stallm,
memtorege2, memwritee2, rte2, rse2, rte2, rtd2, branchd2, regwritee2, writerege2, rsd2, memtoregm2, writeregm2, stallm2) begin
lwstalld = (memtorege && ((rte == rsd) || (rte == rtd))) || (memtorege2 && ((rte2 == rsd2) || (rte2 == rtd2)));
lwstalle = (memtorege && memtorege2 && !memtoregm);
swstalle = (memwritee && memwritee2 && !memwritem);
branchstalld = (branchd && (regwritee && ( (writerege == rsd) || (writerege == rtd) ))) ||
(branchd && (regwritee2 && ( (writerege2 == rsd) || (writerege2 == rtd) ))) ||
(branchd2 && (regwritee && ( (writerege == rsd2) || (writerege == rtd2) ))) ||
(branchd2 && (regwritee2 && ( (writerege2 == rsd2) || (writerege2 == rtd2) )));
stalle = lwstalle || swstalle || stallm || (multen && !multready);
stallw = stallm;
stalld = lwstalld || branchstalld || stalle;
stallf = stalld; // stalling D stalls all previous stages
flushe = branchstalld; // stalling D flushes next stage
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ImaDRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ImaDRAM (
data,
inclock,
outclock,
rdaddress,
wraddress,
wren,
q);
input [7:0] data;
input inclock;
input outclock;
input [13:0] rdaddress;
input [13:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "2"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL rdaddress[13..0]
// Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL wraddress[13..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ImaDRAM_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a, b, c, n; int main() { ios_base::sync_with_stdio(false); ; cin >> a >> b >> c >> n; if (a - c < 0 || b - c < 0) return cout << -1, 0; if (a + b - c >= n) return cout << -1, 0; cout << n - (a + b - c); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 410; const int inf = 0x7fffffff; int a[maxn]; int n; int main() { int ans = inf; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 2; i <= n; i++) for (int j = i; j <= n; j++) { int x = a[i - 1] - 1, y = 0; for (int k = i; k <= j; k++) { int t = x / a[k]; y += t; x -= t * a[k]; } x = a[i - 1] - 1 - x + a[j]; y++; if (x < ans) { int o = x; for (int k = 1; k <= n; k++) { int t = x / a[k]; y -= t; x -= t * a[k]; } if (y < 0) ans = o; } } if (ans == inf) puts( -1 ); else printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_6_V
`define SKY130_FD_SC_HDLL__A21O_6_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_6 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_6 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_6_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, i, j, t; char c; string s; cin >> k; for (i = 1; i < k; i++) { for (j = 1; j < k; j++) { if (j > 1) { cout << ; } t = i * j; s = ; while (t > 0) { c = t % k + 0 ; s = c + s; t /= k; } cout << s; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; int k = 0, l = 0, n; cin >> a >> b; n = a.size(); for (int i = 0; i < n; i++) { if (a[i] == 4 && b[i] == 7 ) { k++; } else if (a[i] == 7 && b[i] == 4 ) { l++; } } int p = max(k, l); cout << p << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BEHAVIORAL_PP_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B ;
input SLEEP;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire nor_teb_SLEEP;
wire zgnd ;
wire zpwr ;
// Name Output Other arguments
nor nor0 (nor_teb_SLEEP, TE_B, SLEEP );
bufif1 bufif10 (zgnd , A, VPWR );
bufif0 bufif00 (zpwr , zgnd, VGND );
bufif1 bufif11 (Z , zpwr, nor_teb_SLEEP);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; bool debug = true; const int dx[] = {0, 1, 0, -1, 1, 1, -1, -1, 0}; const int dy[] = {1, 0, -1, 0, -1, 1, 1, -1, 0}; template <typename X> inline X square(const X& a) { return a * a; } int scan_d() { bool minus = false; int result = 0; char ch; ch = getchar(); while (true) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } if (ch == - ) minus = true; else result = ch - 0 ; while (true) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = (result << 3) + (result << 1) + (ch - 0 ); } if (minus) return -result; else return result; } long scan_ld() { bool minus = false; long result = 0; char ch; ch = getchar(); while (true) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } if (ch == - ) minus = true; else result = ch - 0 ; while (true) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = (result << 3) + (result << 1) + (ch - 0 ); } if (minus) return -result; else return result; } long long scan_lld() { bool minus = false; long long result = 0; char ch; ch = getchar(); while (true) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } if (ch == - ) minus = true; else result = ch - 0 ; while (true) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = (result << 3) + (result << 1) + (ch - 0 ); } if (minus) return -result; else return result; } long long unsigned scan_llu() { long long unsigned result = 0; char ch; ch = getchar(); while (true) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } result = ch - 0 ; while (true) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = (result << 3) + (result << 1) + (ch - 0 ); } return result; } void print_d(int n) { if (n < 0) { n = -n; putchar( - ); } int i = 10; char output_buffer[10]; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 10); } void print_ld(long n) { if (n < 0) { n = -n; putchar( - ); } int i = 11; char output_buffer[11]; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 11); } void print_lld(long long n) { if (n < 0) { n = -n; putchar( - ); } int i = 21; char output_buffer[21]; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 21); } void print_llu(long long unsigned n) { int i = 21; char output_buffer[21]; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 21); } void println_d(int n) { if (n < 0) { n = -n; putchar( - ); } int i = 10; char output_buffer[11]; output_buffer[10] = n ; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 11); } void println_ld(long n) { if (n < 0) { n = -n; putchar( - ); } int i = 11; char output_buffer[12]; output_buffer[11] = n ; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 12); } void println_lld(long long n) { if (n < 0) { n = -n; putchar( - ); } int i = 21; char output_buffer[22]; output_buffer[21] = n ; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 22); } void println_llu(long long unsigned n) { int i = 21; char output_buffer[22]; output_buffer[21] = n ; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 22); } char sp; void printsp_d(int n) { if (n < 0) { n = -n; putchar( - ); } int i = 10; char output_buffer[11]; output_buffer[10] = sp; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 11); } void printsp_ld(long n) { if (n < 0) { n = -n; putchar( - ); } int i = 11; char output_buffer[12]; output_buffer[11] = sp; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 12); } void printsp_lld(long long n) { if (n < 0) { n = -n; putchar( - ); } int i = 21; char output_buffer[22]; output_buffer[21] = sp; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 22); } void printsp_llu(long long unsigned n) { int i = 21; char output_buffer[22]; output_buffer[21] = sp; do { output_buffer[--i] = (n % 10) + 0 ; n /= 10; } while (n); do { putchar(output_buffer[i]); } while (++i < 22); } long long cal[100005][15], dp[105][105][15]; vector<pair<int, int> > ind; int main() { int n, q, c, j, i, x, y, x1, x2, y1, y2, t; long long ans = 0; n = scan_d(); q = scan_d(); c = scan_d(); for (i = 0; i < n; i++) { x = scan_d(); y = scan_d(); t = scan_d(); cal[i][0] = t; dp[x][y][0] += t; ind.push_back(make_pair(x, y)); } for (i = 1; i <= c + 3; i++) { for (j = 0; j < n; j++) { cal[j][i] = (cal[j][i - 1] + 1) % (c + 1); dp[ind[j].first][ind[j].second][i] += (cal[j][i]); } } for (t = 0; t <= c + 3; t++) { for (i = 1; i <= 100; i++) { for (j = 1; j <= 100; j++) { dp[i][j][t] += dp[i][j - 1][t]; } } } while (q--) { ans = 0; t = scan_d(); x1 = scan_d(); y1 = scan_d(); x2 = scan_d(); y2 = scan_d(); if (y1 > y2) swap(y1, y2); if (x1 > x2) swap(x1, x2); t %= (c + 1); for (i = x1; i <= x2; i++) { ans += (dp[i][y2][t] - dp[i][y1 - 1][t]); } println_lld(ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> G[505000], S[505000]; unordered_map<int, int> f[505000]; int n, m, dep[505000], fa[505000], bel[505000], used[505000]; void dfs(int x, int fff) { fa[x] = fff; dep[x] = dep[fff] + 1; for (auto y : G[x]) if (y != fff) { if (!dep[y]) dfs(y, x); else if (dep[y] > dep[x]) { for (;; y = fa[y]) { bel[y] = x; S[x].push_back(y); if (y == x) break; } } } } deque<int> q; void add(int x) { for (; !q.empty() && q.back() < x;) q.pop_back(); q.push_back(x); } void del(int x) { if (q.front() == x) q.pop_front(); } int gaof(int fff, int x) { if (f[x].count(fff)) return f[x][fff]; if (!bel[x]) { if (!used[x]) { used[x] = 1; int res = 0; for (auto y : G[x]) if (y != fff) res = max(res, gaof(x, y) + 1); return f[x][fff] = res; } int now = 0; for (auto y : G[x]) now = max(now, gaof(x, y) + 1); f[x][0] = now; now = 0; for (auto y : G[x]) { f[x][y] = max(f[x][y], now); now = max(now, gaof(x, y) + 1); } now = 0; for (auto it = G[x].rbegin(); it != G[x].rend(); ++it) { int y = *it; f[x][y] = max(f[x][y], now); now = max(now, gaof(x, y) + 1); } return f[x][fff]; } int b = bel[x]; vector<int>& T = S[b]; int sz = T.size(); if (!used[b]) { used[b] = 1; int id = find(T.begin(), T.end(), x) - T.begin(); int res = 0; for (int i = 0; i < sz; ++i) { int d = abs(i - id); d = min(d, sz - d); int u = T[i]; res = max(res, d); for (auto v : G[u]) if (!(u == x && v == fff) && bel[v] != b) res = max(res, gaof(u, v) + d + 1); } return f[x][fff] = res; } vector<int> mx, nex, pre; mx.resize(sz); nex.resize(sz); pre.resize(sz); for (int i = 0; i < sz; ++i) { int u = T[i]; for (auto v : G[u]) if (bel[v] != b) mx[i] = max(mx[i], gaof(u, v) + 1); } q.clear(); int l = sz / 2; for (int i = 0; i < sz * 2; ++i) { add(mx[i % sz] + i); if (i >= l) { del(mx[(i - l) % sz] + (i - l)); nex[(i - l) % sz] = q.front() - (i - l); } } q.clear(); for (int i = sz * 2; i > 0; --i) { add(mx[i % sz] - i); if (i + l <= sz * 2) { del(mx[(i + l) % sz] - (i + l)); pre[(i + l) % sz] = q.front() + (i + l); } } for (int i = 0; i < sz; ++i) { int u = T[i]; for (auto v : G[u]) if (bel[v] != b) f[u][v] = max(pre[i], nex[i]); f[u][0] = max(max(pre[i], nex[i]), mx[i]); int now = 0; for (auto v : G[u]) { if (bel[v] == b) continue; f[u][v] = max(f[u][v], now); now = max(now, gaof(u, v) + 1); } now = 0; for (auto it = G[u].rbegin(); it != G[u].rend(); ++it) { int v = *it; if (bel[v] == b) continue; f[u][v] = max(f[u][v], now); now = max(now, gaof(u, v) + 1); } } return f[x][fff]; } int main() { cin >> n >> m; int u, v; for (int i = 1; i <= m; ++i) { scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } dfs(1, 0); for (int i = 1; i <= n; ++i) { printf( %d , gaof(0, i)); } puts( ); } |
#include <bits/stdc++.h> using namespace std; int fact(int x); int main() { int a, b; cin >> a >> b; int m = min(a, b); cout << fact(m); } int fact(int x) { int sum = 1; for (int i = 2; i < x; i++) sum *= i; return sum * x; } |
#include <bits/stdc++.h> using namespace std; unsigned long long ans; int n, i, j, k, u, v; int size[80011], fa[80011]; vector<int> e[80011]; void dfs(int now) { unsigned long long o = 0; size[now] = 1; for (int i = 0; i < e[now].size(); i++) if (e[now][i] != fa[now]) { fa[e[now][i]] = now; dfs(e[now][i]); o += (unsigned long long)size[now] * size[e[now][i]]; size[now] += size[e[now][i]]; } ans -= o * (o + 2LL * size[now] * (n - size[now])); } int main() { scanf( %d , &n); for (i = 1; i < n; i++) { scanf( %d%d , &u, &v); e[u].push_back(v); e[v].push_back(u); } ans = (n - 1LL) * n / 2; ans *= ans; dfs(1); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[5][5], sum, add, ex; char c[5][5]; int main() { for (int i = 1; i <= 4; i++) for (int j = 1; j <= 4; j++) { cin >> c[i][j]; if (c[i][j] == x ) { a[i][j] = 4; sum++; } else if (c[i][j] == o ) { a[i][j] = 1; add++; } } if (sum == add) ex = 8; else ex = 2; for (int i = 1; i <= 4; i++) for (int j = 1; j <= 2; j++) if (a[i][j] + a[i][j + 1] + a[i][j + 2] == ex) { cout << YES ; return 0; } for (int i = 1; i <= 2; i++) for (int j = 1; j <= 4; j++) if (a[i][j] + a[i + 1][j] + a[i + 2][j] == ex) { cout << YES ; return 0; } if (a[1][1] + a[2][2] + a[3][3] == ex) { cout << YES ; return 0; } if (a[2][2] + a[3][3] + a[4][4] == ex) { cout << YES ; return 0; } if (a[1][4] + a[2][3] + a[3][2] == ex) { cout << YES ; return 0; } if (a[2][3] + a[3][2] + a[4][1] == ex) { cout << YES ; return 0; } if (a[3][1] + a[2][2] + a[1][3] == ex) { cout << YES ; return 0; } if (a[4][2] + a[3][3] + a[2][4] == ex) { cout << YES ; return 0; } if (a[2][1] + a[3][2] + a[4][3] == ex) { cout << YES ; return 0; } if (a[1][2] + a[2][3] + a[3][4] == ex) { cout << YES ; return 0; } cout << NO ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_8_V
`define SKY130_FD_SC_HD__CLKBUF_8_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD1_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long l1, l2, r1, r2, q; long long p1, p2; int main() { scanf( %lld , &q); for (int i = 1; i <= q; i++) { scanf( %lld%lld%lld%lld , &l1, &r1, &l2, &r2); p1 = l1; p2 = l2; if (p1 == p2) p2 = r2; printf( %lld %lld n , p1, p2); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
// Delay Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_V |
`timescale 1 ns / 1 ps
module hapara_axis_id_generator_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4,
// Parameters of Axi Master Bus Interface M00_AXIS
parameter integer C_M00_AXIS_TDATA_WIDTH = 32
// parameter integer C_M00_AXIS_START_COUNT = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready,
// Ports of Axi Master Bus Interface M00_AXIS
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire m00_axis_tvalid,
output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
// output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
output wire m00_axis_tlast,
input wire m00_axis_tready
);
wire En;
wire Finish;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] orgX;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] orgY;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] lengthX;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] lengthY;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] org;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] len;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] numOfSlv;
// Instantiation of Axi Bus Interface S00_AXI
hapara_axis_id_generator_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) hapara_axis_id_generator_v1_0_S00_AXI_inst (
.En(En),
.Finish(Finish),
.org(org),
.len(len),
.numOfSlv(numOfSlv),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Instantiation of Axi Bus Interface M00_AXIS
hapara_axis_id_generator_v1_0_M00_AXIS # (
.C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
// .C_M_START_COUNT(C_M00_AXIS_START_COUNT)
) hapara_axis_id_generator_v1_0_M00_AXIS_inst (
.En(En),
.Finish(Finish),
.org(org),
.len(len),
.numOfSlv(numOfSlv),
.M_AXIS_ACLK(m00_axis_aclk),
.M_AXIS_ARESETN(m00_axis_aresetn),
.M_AXIS_TVALID(m00_axis_tvalid),
.M_AXIS_TDATA(m00_axis_tdata),
// .M_AXIS_TSTRB(m00_axis_tstrb),
.M_AXIS_TLAST(m00_axis_tlast),
.M_AXIS_TREADY(m00_axis_tready)
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 100; int n, p, k; int dp[2][maxn][55][55]; int maks[2][2][maxn][55]; int tmaks[2][maxn]; int question[2][maxn]; int main() { scanf( %d %d %d , &n, &p, &k); int cnt, x; int res = 0; for (int i = 0; i < 2; ++i) { scanf( %d , &cnt); while (cnt--) { scanf( %d , &x); question[i][x] = 1; } } if (p > 2 * ceil(n / k)) { for (int i = 1; i <= n; ++i) res += (question[0][i] || question[1][i]); cout << res << endl; return 0; } int now = 0; memset(dp, 0xc0, sizeof dp); memset(maks, 0xc0, sizeof maks); memset(tmaks, 0xc0, sizeof tmaks); maks[1][0][0][0] = maks[1][1][0][0] = tmaks[1][0] = 0; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= p; ++j) { tmaks[now][j] = -0x3f3f3f3f; for (int r = 0; r <= k; ++r) { maks[now][0][j][r] = maks[now][1][j][r] = -0x3f3f3f3f; for (int r1 = 0; r1 <= k; ++r1) dp[now][j][r][r1] = -0x3f3f3f3f; } } for (int j = 0; j <= p; ++j) { for (int r1 = 0; r1 <= k; ++r1) { for (int r2 = 0; r2 <= k; ++r2) { int &cur = dp[now][j][r1][r2]; if (r1 > 1 && r2 > 1 && j >= 2) cur = max(cur, dp[!now][j][r1 - 1][r2 - 1] + (question[0][i] || question[1][i])); if ((r1 == 0 || r1 == 1) && j >= r1 && !(r2 == 0 || r2 == 1)) cur = max(cur, maks[!now][0][j - r1][r2 - 1] + (question[1][i] || (question[0][i] && r1))); if ((r2 == 0 || r2 == 1) && j >= r2 && !(r1 == 0 || r1 == 1)) cur = max(cur, maks[!now][1][j - r2][r1 - 1] + ((question[1][i] && r2) || question[0][i])); if ((r1 == 0 || r1 == 1) && (r2 == 0 || r2 == 1) && j >= r1 + r2) cur = max(cur, tmaks[!now][j - r1 - r2] + ((question[0][i] && r1) || (question[1][i] && r2))); tmaks[now][j] = max(tmaks[now][j], cur); maks[now][0][j][r2] = max(maks[now][0][j][r2], cur); maks[now][1][j][r1] = max(maks[now][1][j][r1], cur); res = max(res, cur); } } } now = !now; } printf( %d n , res); } |
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