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#include<bits/stdc++.h> using namespace std; int main(){ int T; cin>>T; while(T--){ long long int N; cin>>N; int sum1=0,i=1,count=0; while(true){ sum1+=i;count++; if(sum1>=N){break;} i+=2; } cout<<count<< n ; } return 0; } |
module minsoc_wb_32_8_bridge(
wb_32_sel_i,
wb_32_dat_i, wb_32_dat_o, wb_32_adr_i,
wb_8_dat_i, wb_8_dat_o, wb_8_adr_i
);
input [3:0] wb_32_sel_i;
input [31:0] wb_32_dat_i;
output reg [31:0] wb_32_dat_o;
input [31:0] wb_32_adr_i;
output reg [7:0] wb_8_dat_i;
input [7:0] wb_8_dat_o;
output [31:0] wb_8_adr_i;
reg [1:0] wb_8_adr;
// put output to the correct byte in 32 bits using select line
always @(wb_32_sel_i or wb_8_dat_o)
case (wb_32_sel_i)
4'b0001: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o};
4'b0010: wb_32_dat_o <= #1 {16'b0, wb_8_dat_o , 8'b0};
4'b0100: wb_32_dat_o <= #1 {8'b0, wb_8_dat_o , 16'b0};
4'b1000: wb_32_dat_o <= #1 {wb_8_dat_o , 24'b0};
4'b1111: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o};
default: wb_32_dat_o <= #1 0;
endcase // case(wb_sel_i)
always @(wb_32_sel_i or wb_32_dat_i)
begin
case (wb_32_sel_i)
4'b0001 : wb_8_dat_i = wb_32_dat_i[7:0];
4'b0010 : wb_8_dat_i = wb_32_dat_i[15:8];
4'b0100 : wb_8_dat_i = wb_32_dat_i[23:16];
4'b1000 : wb_8_dat_i = wb_32_dat_i[31:24];
default : wb_8_dat_i = wb_32_dat_i[7:0];
endcase // case(wb_sel_i)
case (wb_32_sel_i)
4'b0001 : wb_8_adr = 2'h3;
4'b0010 : wb_8_adr = 2'h2;
4'b0100 : wb_8_adr = 2'h1;
4'b1000 : wb_8_adr = 2'h0;
default : wb_8_adr = 2'h0;
endcase // case(wb_sel_i)
end
assign wb_8_adr_i = { wb_32_adr_i[31:2] , wb_8_adr };
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int a[1000005]; map<int, int> ht; map<int, int>::reverse_iterator its; long long mul(long long a, long long b) { long long res = 1; while (b) { if (b % 2 == 1) res = (res * a) % mod; a = (a * a) % mod; b /= 2; } return res; } int main() { int n; scanf( %d , &n); long long nf = 1; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); ht[a[i]]++; nf = (nf * i) % mod; } int add = 0; long long ans = 0; for (its = ht.rbegin(); its != ht.rend(); its++) { if (add != 0) ans = (ans + nf * its->second % mod * mul((its->second + add) % mod, mod - 2) % mod * its->first % mod) % mod; add += its->second; } printf( %lld n , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_TB_V
`define SKY130_FD_SC_MS__A21OI_TB_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ms__a21oi dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 10; const int mod = 1e9 + 7; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + c - 0 , c = getchar(); return x * f; } int inc(int x, int y) { return (x + y >= mod) ? (x + y - mod) : (x + y); } int del(int x, int y) { return (x - y < 0) ? (x - y + mod) : (x - y); } namespace math { int qpow(int a, int x, int mo) { int res = 1; while (x) { if (x & 1) res = 1ll * res * a % mod; a = 1ll * a * a % mod; x >>= 1; } return res; } int Fac[N], invFac[N]; void Finit(int n) { Fac[0] = 1; invFac[0] = 1; for (int i = 1; i <= n; i++) Fac[i] = 1ll * Fac[i - 1] * i % mod; invFac[n] = qpow(Fac[n], mod - 2, mod); for (int i = n - 1; i >= 1; i--) invFac[i] = 1ll * invFac[i + 1] * (i + 1) % mod; } int C(int n, int m) { if (m == 0) return 1; if (n < m || m < 0) return 0; return (int)(1ll * Fac[n] * invFac[m] % mod * invFac[n - m] % mod); } } // namespace math bitset<N> p[N]; int c[N][N]; int main() { int n = read(), m = read(), R = read(); int siz = 1e3; math::Finit(n); vector<int> X(n + 1), Y(n + 1), Z(n + 1); for (int i = 1; i <= n; i++) X[i] = read(), Y[i] = read(), Z[i] = read(); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (max(abs(X[i] - X[j]), abs(Y[i] - Y[j])) <= R) p[i].set(j); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { c[i][j] = math::C(n - (p[i] | p[j]).count(), m); } } int res = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { int o = inc(del(del(math::C(n, m), c[i][i]), c[j][j]), c[i][j]); res = inc(res, 1ll * o * Z[i] % mod * Z[j] % mod); } } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; int i, j, n, m, a, b, tmp; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int main() { cin >> n >> m >> a >> b; tmp = n * m / gcd(n, m); cout << b / tmp - (a - 1) / tmp; return 0; } |
#include <bits/stdc++.h> const int MOD = 1e9 + 7; const int INF = 1e9 + 7; const int MAXN = 1e3 + 5; const double eps = 1e-14; using namespace std; int a[MAXN][5], acp[5], acVasya[5], price[5], curAc[5], curP[5]; int n; int ans = INF + 1; bool cmpFrac(int x, int y, int p, int q) { return (x * q > y * p); } int problem_price(int x, int y) { if (cmpFrac(x, y, 1, 2)) return 500; else if (cmpFrac(x, y, 1, 4)) return 1000; else if (cmpFrac(x, y, 1, 8)) return 1500; else if (cmpFrac(x, y, 1, 16)) return 2000; else if (cmpFrac(x, y, 1, 32)) return 2500; else return 3000; } bool ok(int k) { for (int i = 0; i < 5; i++) { curAc[i] = acp[i]; if (acVasya[i]) { curAc[i] += k; } } for (int i = 0; i < 5; i++) { curP[i] = problem_price(curAc[i], n + k); } int VasyaS = 0, PetyaS = 0; for (int i = 0; i < 5; i++) { if (a[0][i] != -1) { VasyaS += curP[i] - (curP[i] / 250 * a[0][i]); } if (a[1][i] != -1) PetyaS += curP[i] - (curP[i] / 250 * a[1][i]); } if (VasyaS > PetyaS) return true; else return false; } void solve() { cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < 5; j++) { cin >> a[i][j]; if (a[i][j] != -1) { acp[j]++; } } } for (int j = 0; j < 5; j++) { if (a[0][j] != -1 && a[1][j] != -1 && a[0][j] > a[1][j]) { acVasya[j] = 1; } } for (int i = 0; i < 1e6; i++) { if (ok(i)) { cout << i; return; } } if (ans == INF + 1) cout << -1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); if (!1) { freopen( 474 .in , r , stdin); freopen( 474 .out , w , stdout); } int t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long ara[200005]; long long aray[200005]; int main() { long long a, b, c, d, t, i, j, k, n, m; cin >> t; while (t--) { long long ans = 0; cin >> n >> m >> k; a = n / k; if (m > a) { m -= a; if (m % (k - 1) == 0) { ans = a - ((m / (k - 1))); } else { ans = a - ((m / (k - 1))) - 1; } } else { ans = m; } cout << ans << endl; } return 0; } |
//-----------------------------------------------------
// Design Name : syn_fifo
// File Name : syn_fifo.v
// Function : Synchronous (single clock) FIFO
//-----------------------------------------------------
`default_nettype none
module sync_fifo #(
parameter DATA_WIDTH = 8,
parameter FIFO_DEPTH = 16
)(
input wire i_clk,
input wire i_rst,
input wire i_rd_en,
input wire i_wr_en,
input wire [DATA_WIDTH-1:0] i_data_in,
output wire o_full,
output wire o_empty,
output reg [DATA_WIDTH-1:0] o_data_out = 0
);
parameter ADDR_WIDTH = $clog2(FIFO_DEPTH);
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer = 0;
reg [ADDR_WIDTH-1:0] rd_pointer = 0;
reg [ADDR_WIDTH:0] status_cnt = 0;
reg [DATA_WIDTH-1:0] mem [FIFO_DEPTH-1:0];
//-----------Variable assignments---------------
assign o_full = (status_cnt == (FIFO_DEPTH-1));
assign o_empty = (status_cnt == 0);
//-----------Code Start---------------------------
always @ (posedge i_clk or posedge i_rst)
begin: WRITE_POINTER
if (i_rst)
wr_pointer <= 0;
else if (i_wr_en)
wr_pointer <= wr_pointer + 1;
end
always @ (posedge i_clk or posedge i_rst)
begin: READ_POINTER
if (i_rst)
rd_pointer <= 0;
else if (i_rd_en)
rd_pointer <= rd_pointer + 1;
end
always @ (posedge i_clk or posedge i_rst)
begin: STATUS_COUNTER
if (i_rst)
status_cnt <= 0;
else if (i_rd_en && (!i_wr_en) && (status_cnt != 0))
status_cnt <= status_cnt - 1;
else if (i_wr_en && (!i_rd_en) && (status_cnt != FIFO_DEPTH))
status_cnt <= status_cnt + 1;
end
always @ (posedge i_clk)
begin: RAM
if (i_wr_en)
mem[wr_pointer] <= i_data_in;
if (i_rd_en)
o_data_out <= mem[rd_pointer];
end
endmodule
`default_nettype wire
/*---------- Testbench ----------------
sync_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) myFIFO (
.i_clk(i_clk),
.i_rst(i_rst),
.i_rd_en(i_rd_en),
.i_wr_en(i_wr_en),
.i_data_in(i_data_in),
.o_full(o_full),
.o_empty(o_empty),
.o_data_out(o_data_out)
);
-------------------------------------*/
|
#include <bits/stdc++.h> using namespace std; map<int, int> m; pair<bool, char> check(int a, string s) { int flag = 0; char x = s[a], e; for (long long int i = 1 + (x - a ); i < 26; i++) { if (m.count(i)) { return {true, char(i + a )}; } } return {false, f }; } int main() { ios_base ::sync_with_stdio(false), cin.tie(NULL), cout.tie(0); int a, b; cin >> a >> b; string s; cin >> s; for (long long int i = 0; i < s.size(); i++) { m[s[i] - a ]++; } if (a < b) { cout << s; sort(s.begin(), s.end()); for (long long int i = 0; i < b - a; i++) cout << s[0]; } else { int k = 0; char e; for (long long int i = b - 1; i >= 0; i--) { pair<bool, char> p = check(i, s); if (p.first) { e = p.second; k = i; break; } } for (long long int i = 0; i < k; i++) cout << s[i]; cout << e; sort(s.begin(), s.end()); if (b - k - 1 > 0) { for (long long int i = 0; i < b - k - 1; i++) cout << s[0]; } } return 0; } |
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/18/2016
Founction: I2C top module
Note:
****************************************************************************/
module I2C_MASTER_reduced(clk,rst_n,sda,scl,RD_EN,WR_EN,receive_status
);
input clk;
input rst_n;
input RD_EN;
input WR_EN;
reg WR,RD;
output scl;
output receive_status;
inout sda;
wire scl_wire;
wire scl;
wire[7:0] data;
reg[7:0] data_reg;
reg read_status_reg;
reg write_status_reg;
wire receive_status;
wire [3:0] main_state;
wire [4:0] i2c_state;
wire sda_en;
wire sda_in;
wire sda_out;
assign sda_in = (!sda_en) ? sda : 1'bz;
assign sda = sda_en ? ((sda_out == 1'b1)? 1'bz:1'b0) : 1'bz;
assign scl = scl_wire ? 1'bz: 1'b0;
wire scl_fallingedge;
//----------------- i2c statemachine -------------------------------
//i2c data in big endian mode
parameter data_7 = 4'h0;
parameter data_0 = 4'h7;
parameter data_act = 4'h8;
//----------------- main statemachine ------------------------------
parameter idle_status =4'h0;
parameter start_status =4'h1;
parameter address_status =4'h2;
parameter read_status =4'h3;
parameter write_status =4'h4;
parameter stop_status =4'h5;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)begin
WR <= 1'b0;
RD <= 1'b0;
data_reg <= 'h0;
read_status_reg <= 1'b0;
write_status_reg <= 1'b0;
end
else
begin
if(RD_EN)
begin
if (main_state == read_status)
begin
//try read more bits to fix the issue in i2c speed
if (data_reg == 'h20 && i2c_state == data_7 && scl_fallingedge)
begin
//stop after read 32 data
RD <= 1'b0;
read_status_reg <= 1'b1;
end
else
begin
if (scl_fallingedge && i2c_state == data_0)
data_reg <= data_reg + 1;
end
end
else if (main_state == idle_status)
begin
if (~read_status_reg)
begin
RD <= 1'b1;
WR <= 1'b0;
data_reg <= 'h0;
end
else
begin
//read all data done stop here only reset can recovery
RD <= 1'b0;
WR <= 1'b0;
data_reg <= 'h0;
end
end
else
data_reg <= 'h0;
end
else if(WR_EN)
begin
if (main_state == write_status)
begin
if (data_reg == 'h20 && i2c_state == data_7 && scl_fallingedge)
begin
//stop after send 32 data
WR <= 1'b0;
write_status_reg <= 1'b1;
end
else
begin
if (scl_fallingedge && i2c_state == data_0)
data_reg <= data_reg + 1;
end
end
else if (main_state == idle_status)
begin
if (~write_status_reg)
begin
RD <= 1'b0;
WR <= 1'b1;
data_reg <= 'h0;
end
else
begin
RD <= 1'b0;
WR <= 1'b0;
data_reg <= 'h0;
end
end
else
data_reg <= 'h0;
end
else
begin
RD <= 1'b0;
WR <= 1'b0;
data_reg <= 'h0;
write_status_reg <= 1'b0;
read_status_reg <= 1'b0;
end
end
end
assign data = WR_EN ? data_reg : 8'hz;
I2C_wr_reduced I2C_wr_reduced_instance(
.sda_in(sda_in),
.sda_out(sda_out),
.sda_en(sda_en),
.scl(scl_wire),
.reset_n(rst_n),
.clock(clk),
.WR(WR),
.RD(RD),
.data(data),
.scl_fallingedge(scl_fallingedge),
.main_state(main_state),
.i2c_state(i2c_state),
.debug(receive_status)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { int n; scanf( %d , &n); int c1 = 0, c2 = 0; for (int i = 0; i < n; ++i) { int a; scanf( %d , &a); if (a == 1) ++c1; else ++c2; } int ans = min(c2, c1); c1 -= ans; if (c1 > 0) ans += c1 / 3; printf( %d n , ans); return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
#include <bits/stdc++.h> using namespace std; template <typename T> T in() { char ch; T n = 0; bool ng = false; while (1) { ch = getchar(); if (ch == - ) { ng = true; ch = getchar(); break; } if (ch >= 0 && ch <= 9 ) break; } while (1) { n = n * 10 + (ch - 0 ); ch = getchar(); if (ch < 0 || ch > 9 ) break; } return (ng ? -n : n); } template <typename T> inline T Dis(T x1, T y1, T x2, T y2) { return sqrt((x1 - x2 * x1 - x2) + (y1 - y2 * y1 - y2)); } template <typename T> inline T POW(T B, T P) { if (P == 0) return 1; if (P & 1) return B * POW(B, P - 1); else return (POW(B, P / 2) * POW(B, P / 2)); } template <typename T> inline T ABS(T a) { if (a < 0) return -a; else return a; } template <typename T> inline T Gcd(T a, T b) { if (a < 0) return Gcd(-a, b); if (b < 0) return Gcd(a, -b); return (b == 0) ? a : Gcd(b, a % b); } template <typename T> inline T Lcm(T a, T b) { if (a < 0) return Lcm(-a, b); if (b < 0) return Lcm(a, -b); return a * (b / Gcd(a, b)); } long long Bigmod(long long base, long long power, long long MOD) { long long ret = 1; while (power) { if (power & 1) ret = (ret * base) % MOD; base = (base * base) % MOD; power >>= 1; } return ret; } long long ModInverse(long long number, long long MOD) { return Bigmod(number, MOD - 2, MOD); } int Set(int N, int pos) { return N = N | (1 << pos); } int Reset(int N, int pos) { return N = N & ~(1 << pos); } bool Chkbit(int N, int pos) { return (bool)(N & (1 << pos)); } bool isVowel(char ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } bool isConst(char ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } int toInt(string s) { int sm; stringstream ss(s); ss >> sm; return sm; } long long int toLlint(string s) { long long int sm; stringstream ss(s); ss >> sm; return sm; } const int N = int(2e6) + 15; int cmp(int *r, int a, int b, int l) { return (r[a] == r[b]) && (r[a + l] == r[b + l]); } int wa[N], wb[N], wws[N], wv[N]; int rnk[N], height[N]; void DA(int *r, int *sa, int n, int m) { int i, j, p, *x = wa, *y = wb, *t; for (i = 0; i < m; i++) wws[i] = 0; for (i = 0; i < n; i++) wws[x[i] = r[i]]++; for (i = 1; i < m; i++) wws[i] += wws[i - 1]; for (i = n - 1; i >= 0; i--) sa[--wws[x[i]]] = i; for (j = 1, p = 1; p < n; j *= 2, m = p) { for (p = 0, i = n - j; i < n; i++) y[p++] = i; for (i = 0; i < n; i++) if (sa[i] >= j) y[p++] = sa[i] - j; for (i = 0; i < n; i++) wv[i] = x[y[i]]; for (i = 0; i < m; i++) wws[i] = 0; for (i = 0; i < n; i++) wws[wv[i]]++; for (i = 1; i < m; i++) wws[i] += wws[i - 1]; for (i = n - 1; i >= 0; i--) sa[--wws[wv[i]]] = y[i]; for (t = x, x = y, y = t, p = 1, x[sa[0]] = 0, i = 1; i < n; i++) x[sa[i]] = cmp(y, sa[i - 1], sa[i], j) ? p - 1 : p++; } } void calheight(int *r, int *sa, int n) { int i, j, k = 0; for (i = 1; i <= n; i++) rnk[sa[i]] = i; for (i = 0; i < n; height[rnk[i++]] = k) for (k ? k-- : 0, j = sa[rnk[i] - 1]; r[i + k] == r[j + k]; k++) ; } int sa[N], data[N], n; void Deal() { DA(data, sa, n + 1, 128); calheight(data, sa, n); } char s[2000002]; int Len; struct z { int opn, cls; }; z Tree[2000002 * 4]; void Update(int id, int l, int r, int pos) { if (l == r) { if (s[pos] == ( ) { Tree[id].opn = 1; } else Tree[id].cls = 1; return; } int mid = (l + r) / 2; int lft = 2 * id; int rgt = lft + 1; if (pos <= mid) { Update(lft, l, mid, pos); } else { Update(rgt, mid + 1, r, pos); } int mn = min(Tree[lft].opn, Tree[rgt].cls); Tree[id].cls = Tree[lft].cls + Tree[rgt].cls - mn; Tree[id].opn = Tree[rgt].opn + Tree[lft].opn - mn; return; } z Query(int id, int l, int r, int st, int ed) { if (st <= l && ed >= r) { return Tree[id]; } int mid = (l + r) / 2; int lft = 2 * id; int rgt = lft + 1; if (ed <= mid) { return Query(lft, l, mid, st, ed); } else if (st > mid) { return Query(rgt, mid + 1, r, st, ed); } else { z a, b, c; a = Query(lft, l, mid, st, ed); b = Query(rgt, mid + 1, r, st, ed); int mn = min(a.opn, b.cls); c.cls = a.cls + b.cls - mn; c.opn = b.opn + a.opn - mn; return c; } } int dp[2000002], Close[2000002], len, dp1[2000002]; void Solve() { int Last = -1, Last1 = -1; for (int i = Len + 1 - 1; i >= 1; i--) { if (s[i] == ) ) Last = -1; else if (Last == -1) { Last = i; } dp[i] = (Last == -1 ? 0 : (Last - i + 1)); if (s[i] == ( ) Last1 = -1; else if (Last1 == -1) { Last1 = i; } dp1[i] = (Last1 == -1 ? 0 : (Last1 - i + 1)); } } int A[4 * 2000002]; void Update(int id, int l, int r, int pos, int val) { if (l == r) { A[id] = height[pos]; return; } int mid = (l + r) / 2; int lft = 2 * id; int rgt = lft + 1; if (pos <= mid) { Update(lft, l, mid, pos, val); } else { Update(rgt, mid + 1, r, pos, val); } A[id] = min(A[lft], A[rgt]); return; } int Lcp(int id, int l, int r, int st, int ed) { if (st <= l && ed >= r) { return A[id]; } int mid = (l + r) / 2; int lft = 2 * id; int rgt = lft + 1; if (ed <= mid) { return Lcp(lft, l, mid, st, ed); } else if (st > mid) { return Lcp(rgt, mid + 1, r, st, ed); } else { int a, b; a = Lcp(lft, l, mid, st, ed); b = Lcp(rgt, mid + 1, r, st, ed); return min(a, b); } } int HandleJhamela(int id, int id1, int Opn, int mx) { int Suru = id + min(len, dp[id]), Suru1 = id1 + min(len, dp[id1]); int Rnk = rnk[Suru - 1], Rnk1 = rnk[Suru1 - 1]; int L1 = len + mx - Opn - Close[id], L2 = len + mx - Opn - Close[id1]; int f = 0; if (Rnk > Rnk1) swap(Rnk, Rnk1), f = 1; int lcp = Lcp(1, 1, n, Rnk + 1, Rnk1); if (f) swap(Rnk, Rnk1); if (lcp >= min(L1, L2)) { int diff = abs(L2 - L1); if (L1 < L2) { if (dp1[id1 + min(len, dp[id1]) + lcp] < diff) return id1; else return id; } else { if (dp1[id + min(len, dp[id]) + lcp] < diff) return id; else return id1; } } else { if (Rnk < Rnk1) return id; else return id1; } } int main() { n = 0; scanf( %s , &s); len = strlen(s); for (int i = len + 1 - 1; i >= 1; i--) s[i] = s[i - 1]; Len = len * 2; for (int i = len + 1; i < Len + 1; i++) s[i] = s[i - len]; Solve(); for (int i = 1; i < Len + 1; i++) { Update(1, 1, Len, i); data[n] = (int)s[i]; n++; } data[n] = 0; Deal(); for (int i = 1; i < n; i++) Update(1, 1, n, i, height[i]); int mx = (1 << 28), Open = 0, Id = 0; for (int i = 1; i < len + 1; i++) { z ans = Query(1, 1, Len, i, (i + len - 1)); int Cst = ans.cls + ans.opn; Close[i] = ans.opn; int CntOpn = ans.cls + (min(len, dp[i])); if (mx > Cst) { mx = Cst; Open = CntOpn; Id = i; } else if (mx == Cst && CntOpn > Open) { Open = CntOpn; Id = i; } else if (mx == Cst && CntOpn == Open) { Id = HandleJhamela(Id, i, CntOpn, mx); } } for (int i = 0; i < Open; i++) { printf( ( ); } int baki = len + mx - Open - Close[Id]; int St = Id + dp[Id]; for (int i = 0; i < baki; i++) { printf( %c , s[St + i]); } for (int i = 0; i < Close[Id]; i++) { printf( ) ); } printf( n ); return 0; } |
`include "bsg_defines.v"
`include "bsg_clk_gen.vh"
module bsg_dmc_clk_rst_gen
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p = 2
,parameter `BSG_INV_PARAM(num_lines_p ))
(input bsg_tag_s async_reset_tag_i
,input bsg_tag_s [num_lines_p-1:0] bsg_dly_tag_i
,input bsg_tag_s [num_lines_p-1:0] bsg_dly_trigger_tag_i
,input bsg_tag_s bsg_ds_tag_i
// asynchronous reset for dram controller
,output async_reset_o
// clock input and delayed clock output (for dqs), generating 90-degree phase
// shift
,input [num_lines_p-1:0] clk_i
,output [num_lines_p-1:0] clk_o
// 2x clock input from clock generator and 1x clock output
,input clk_2x_i
,output clk_1x_o);
localparam debug_level_lp = 0;
genvar i;
bsg_tag_client_unsync #(.width_p(1)) btc_async_reset
(.bsg_tag_i ( async_reset_tag_i )
,.data_async_r_o ( async_reset_o ));
// Clock Generator (CG) Instance
for(i=0;i<num_lines_p;i++) begin: dly_lines
bsg_dly_line #(.num_adgs_p(num_adgs_p)) dly_line_inst
(.bsg_tag_i ( bsg_dly_tag_i[i] )
,.bsg_tag_trigger_i ( bsg_dly_trigger_tag_i[i] )
,.async_reset_i ( async_reset_o )
,.clk_i ( clk_i[i] )
,.clk_o ( clk_o[i] ));
end
`declare_bsg_clk_gen_ds_tag_payload_s(2)
bsg_clk_gen_ds_tag_payload_s ds_tag_payload_r;
wire ds_tag_payload_new_r;
// fixme: maybe wire up a default and deal with reset issue?
// downsampler bsg_tag interface
bsg_tag_client #
(.width_p ( $bits(bsg_clk_gen_ds_tag_payload_s) )
,.default_p ( 0 )
,.harden_p ( 1 ))
btc_ds
(.bsg_tag_i ( bsg_ds_tag_i )
,.recv_clk_i ( clk_2x_i )
,.recv_reset_i ( 1'b0 ) // node must be programmed by bsg tag
,.recv_new_r_o ( ds_tag_payload_new_r ) // we don't require notification
,.recv_data_r_o ( ds_tag_payload_r ));
if (debug_level_lp > 1)
always_ff @(negedge clk_2x_i) begin
if (ds_tag_payload_new_r)
$display("## bsg_clk_gen downsampler received configuration state: %b",ds_tag_payload_r);
end
// clock downsampler
//
// we allow the clock downsample reset to be accessed via bsg_tag; this way
// we can turn it off by holding reset high to save power.
//
bsg_counter_clock_downsample #
(.width_p ( 2 )
,.harden_p ( 1 ))
clk_gen_ds_inst
(.clk_i ( clk_2x_i )
,.reset_i ( ds_tag_payload_r.reset )
,.val_i ( 2'd0 )
,.clk_r_o ( clk_1x_o ));
endmodule
`BSG_ABSTRACT_MODULE(bsg_dmc_clk_rst_gen)
|
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Register.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2003-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: Register
// Desc: If you don't know, I can't help you.
// Author: <a href="http://www.gdgib.com/">Greg Gibeling</a>
// Version: $Revision: 26904 $
//------------------------------------------------------------------------------
module Register(Clock, Reset, Set, Enable, In, Out);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 32,
Initial = {Width{1'bx}},
AsyncReset = 0,
AsyncSet = 0,
ResetValue = {Width{1'b0}},
SetValue = {Width{1'b1}};
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Inputs & Outputs
//--------------------------------------------------------------------------
input Clock, Enable, Reset, Set;
input [Width-1:0] In;
output reg [Width-1:0] Out = Initial;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Behavioral Register
//--------------------------------------------------------------------------
generate if (AsyncReset) begin:AR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Reset or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock or posedge Reset) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end else begin:SR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end endgenerate
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrbp (
RESET_B,
CLK ,
D ,
Q ,
Q_N
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 10; long long bit[maxn]; void update(long long idx, long long v) { while (idx <= maxn) { bit[idx] += v; idx += idx & -idx; } } long long query(long long idx) { long long ans = 0; while (idx > 0) { ans += bit[idx]; idx -= idx & -idx; } return ans; } long long inter(long long l, long long r) { return query(r) - query(l - 1); } void solve() { long long n, m; cin >> n >> m; memset(bit, 0, sizeof bit); vector<pair<long long, pair<long long, long long> > > hor(n), vert(m); vector<pair<long long, pair<long long, long long> > > ord; long long ans = 1; for (long long i = 0; i < n; i++) { cin >> hor[i].first >> hor[i].second.first >> hor[i].second.second; if ((hor[i].second.first + hor[i].second.second) == 1e6) ans++; } for (long long i = 0; i < m; i++) { cin >> vert[i].first >> vert[i].second.first >> vert[i].second.second; if ((vert[i].second.first + vert[i].second.second) == 1e6) ans++; } for (long long i = 0; i < m; i++) { vert[i].first++; vert[i].second.first++; vert[i].second.second++; } for (long long i = 0; i < n; i++) { hor[i].first++; hor[i].second.first++; hor[i].second.second++; } for (long long i = 0; i < (long long)vert.size(); i++) { ord.push_back({vert[i].first, {1, i}}); } for (long long i = 0; i < (long long)hor.size(); i++) { ord.push_back({hor[i].second.first, {0, i}}); ord.push_back({hor[i].second.second, {2, i}}); } sort(ord.begin(), ord.end()); for (long long i = 0; i < (long long)ord.size(); i++) { long long x = ord[i].first; long long tipo = ord[i].second.first; long long ind = ord[i].second.second; if (tipo == 1) { long long y1 = vert[ind].second.first; long long y2 = vert[ind].second.second; ans += inter(y1, y2); } else { long long y = hor[ind].first; if (tipo == 2) update(y, -1); else update(y, 1); } } cout << ans << endl; } int32_t main() { cin.tie(0); ios::sync_with_stdio(0); long long tc = 1; while (tc--) solve(); } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18 + 1e17; const long long mod = 1e9 + 7; long long modInverse(long long a, long long m) { long long m0 = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long powm(long long a, long long b) { a = a % mod; long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return (res % mod); } const long long N = 5e3 + 6; int n, k, water; vector<int> v; int dp[N][2], dpr[N][2]; int arr[N]; bool brr[N]; int ip = 1e9; void makedp() { dp[0][0] = 1; dp[0][1] = -1; for (int i = 0; i < n; i++) { int x = arr[i] % k; memset(dpr, -1, sizeof(dpr)); dpr[0][0] = 1; for (int j = 1; j < k; j++) { if (dp[j][0] == 0 && dp[(j - x + k) % k][0] == 1) { dpr[j][0] = 1; dpr[j][1] = i; } else { dpr[j][0] = dp[j][0]; dpr[j][1] = dp[j][1]; } } swap(dpr, dp); } } bool check() { int tt = 0; for (int i = 0; i < n; i++) tt += arr[i]; if (tt < water || dp[water % k][0] == 0) { cout << NO n ; return true; ; } return false; } void find() { int val = water % k; int x = dp[val][1]; while (x != -1) { v.push_back(dp[val][1]); val = (val - arr[x] % k + k) % k; x = dp[val][1]; } } void seperate() { memset(brr, 0, sizeof(brr)); int tt = 0; for (int i : v) { brr[i] = 1; tt += arr[i]; } for (int i = 1; i < v.size(); i++) cout << ip << << v[i] + 1 << << v[0] + 1 << n ; int mark = -1; int tc = 0; for (int i = 0; i < n; i++) if (!brr[i]) { mark = i; tc += arr[i]; } for (int i = 0; i < n; i++) if (!brr[i] && mark != i) cout << ip << << i + 1 << << mark + 1 << n ; if (v.size() == 0) v.push_back(0); if (tt > water) cout << (tt - water) / k << << v[0] + 1 << << (0 == v[0] ? 2 : 1) << n ; else if (tt < water) cout << (water - tt) / k << << mark + 1 << << v[0] + 1 << n ; } void solve() { cin >> n >> k >> water; for (int i = 0; i < n; i++) cin >> arr[i]; makedp(); if (check()) return; cout << YES n ; find(); seperate(); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; for (long long i = 1; i <= t; i++) { solve(); } } |
//--------------------------------------------------------------------------------
// transmitter.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Takes 32bit (one sample) and sends it out on the serial port.
// End of transmission is signalled by taking back the busy flag.
// Supports xon/xoff flow control.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module transmitter(
clock, trxClock, reset, disabledGroups,
write, wrdata, id, xon, xoff,
// outputs
tx, busy);
parameter [31:0] FREQ = 100000000;
parameter [31:0] BAUDRATE = 115200;
parameter BITLENGTH = FREQ / BAUDRATE;
input clock;
input trxClock;
input reset;
input write; // Data write request
input [31:0] wrdata; // Write data
input [3:0] disabledGroups;
input id; // ID output request
input xon; // Flow control request
input xoff; // Resume output request
output tx; // Serial tx data
output busy; // Busy flag
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
//
// Registers...
//
reg [31:0] sampled_wrdata, next_sampled_wrdata;
reg [3:0] sampled_disabledGroups, next_sampled_disabledGroups;
reg [3:0] bits, next_bits;
reg [2:0] bytesel, next_bytesel;
reg paused, next_paused;
reg byteDone, next_byteDone;
reg busy, next_busy;
reg [9:0] txBuffer, next_txBuffer;
assign tx = txBuffer[0];
reg [9:0] counter, next_counter; // Big enough for FREQ/BAUDRATE (100Mhz/115200 ~= 868)
wire counter_zero = ~|counter;
reg writeByte;
//
// Byte select mux...
//
reg [7:0] byte;
reg disabled;
always #1
begin
byte = 0;
disabled = 0;
case (bytesel[1:0]) // synthesys parallel_case
2'h0 : begin byte = sampled_wrdata[7:0]; disabled = sampled_disabledGroups[0]; end
2'h1 : begin byte = sampled_wrdata[15:8]; disabled = sampled_disabledGroups[1]; end
2'h2 : begin byte = sampled_wrdata[23:16]; disabled = sampled_disabledGroups[2]; end
2'h3 : begin byte = sampled_wrdata[31:24]; disabled = sampled_disabledGroups[3]; end
endcase
end
//
// Send one byte...
//
always @ (posedge clock)
begin
counter = next_counter;
bits = next_bits;
byteDone = next_byteDone;
txBuffer = next_txBuffer;
end
always #1
begin
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_counter = counter;
if (writeByte)
begin
next_counter = BITLENGTH;
next_bits = 0;
next_byteDone = FALSE;
next_txBuffer = {1'b1,byte,1'b0}; // 8 bits, no parity, 1 stop bit (8N1)
end
else if (counter_zero)
begin
next_counter = BITLENGTH;
next_txBuffer = {1'b1,txBuffer[9:1]};
if (bits == 4'hA)
next_byteDone = TRUE;
else next_bits = bits + 1'b1;
end
else if (trxClock)
next_counter = counter + 1'b1;
end
//
// Control FSM for sending 32 bit words...
//
parameter [1:0] IDLE = 0, SEND = 1, POLL = 2;
reg [1:0] state, next_state;
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
state = IDLE;
sampled_wrdata = 32'h0;
sampled_disabledGroups = 4'h0;
bytesel = 3'h0;
busy = FALSE;
paused = FALSE;
end
else
begin
state = next_state;
sampled_wrdata = next_sampled_wrdata;
sampled_disabledGroups = next_sampled_disabledGroups;
bytesel = next_bytesel;
busy = next_busy;
paused = next_paused;
end
end
always #1
begin
next_state = state;
next_sampled_wrdata = sampled_wrdata;
next_sampled_disabledGroups = sampled_disabledGroups;
next_bytesel = bytesel;
next_busy = (state != IDLE) || write || paused;
next_paused = xoff | (paused & !xon); // set on xoff, reset on xon
writeByte = FALSE;
case(state) // when write is '1', data will be available with next cycle
IDLE :
begin
next_sampled_wrdata = wrdata;
next_sampled_disabledGroups = disabledGroups;
next_bytesel = 2'h0;
if (write)
next_state = SEND;
else if (id) // send our signature/ID code (in response to the query command)
begin
next_sampled_wrdata = 32'h534c4131; // "SLA1"
next_sampled_disabledGroups = 4'b0000;
next_state = SEND;
end
end
SEND :
begin
writeByte = TRUE;
next_bytesel = bytesel+1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone && !paused)
next_state = (bytesel[2]) ? IDLE : SEND;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; char s[105]; cin >> s; vector<int> a; string ans = ; int j, ct = 0; for (int i = 0; i <= n - 1;) { if (s[i] == o && s[i + 1] == g && s[i + 2] == o && i <= n - 3) { ct = 0; for (j = i + 3; j < n - 1;) { if (s[j] == g && s[j + 1] == o ) { ct = 1; j = j + 2; i = j; } else { i = j; break; } } i = j; if (ct == 1) { ans += *** ; } else { ans += *** ; } } else { ans += s[i]; i++; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); srand(time(NULL)); ; long long t = 1; while (t--) { long long n; cin >> n; long long a[n], b[n]; for (long long i = 0; i < n; i++) cin >> a[i]; multiset<long long> s; for (long long i = 0; i < n; i++) cin >> b[i], s.insert(b[i]); vector<long long> c(n); for (long long i = 0; i < n; i++) { multiset<long long>::iterator it = s.begin(); long long ans = (a[i] + *it) % n, num = *it; it = s.lower_bound(n - a[i]); if (it != s.end() && (a[i] + *it) % n < ans) { ans = (a[i] + *it) % n; num = *it; } c[i] = ans; s.erase(s.find(num)); } for (long long i = 0; i < n; i++) cout << c[i] << ; cout << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int maxn = 2000000; int l, lsub; char str[maxn + 1]; long long dpw[maxn + 1], dpb[maxn + 1], now, nob, ans0, ansb, ans, ranansb, ranans0; int main() { scanf( %d%d , &l, &lsub); scanf( %s , str); now = -1; nob = -1; for (long long i = 0; i < l; i++) ans0 = 1; for (long long i = 0; i < l; i++) { if (str[i] == X ) { long long temp = 0; if (i - now >= lsub) { temp = 1; if (i >= lsub) temp = dpw[i - lsub]; } ranans0 = ans0 * 2 - temp; while (ranans0 < 0) ranans0 += mod; long long temp1 = 0; if (i - nob >= lsub) { if (i >= lsub) temp1 = dpb[i - lsub]; } ranansb = ansb * 2 + temp - temp1; while (ranansb < 0) ranansb += mod; ans *= 2; ans %= mod; ans += temp1; ans %= mod; dpw[i] = ans0 % mod; dpb[i] = (ansb + temp) % mod; ans0 = ranans0 % mod; ansb = ranansb % mod; } if (str[i] == B ) { long long temp = 0; if (i - now >= lsub) { temp = 1; if (i >= lsub) temp = dpw[i - lsub]; } nob = i; ranans0 = ans0 - temp; while (ranans0 < 0) ranans0 += mod; ranansb = ansb + temp; dpw[i] = 0; dpb[i] = (ansb + temp) % mod; ans0 = ranans0 % mod; ansb = ranansb % mod; } if (str[i] == W ) { long long temp1 = 0; if (i - nob >= lsub) { if (i >= lsub) temp1 = dpb[i - lsub]; } now = i; ranans0 = ans0; ranansb = ansb - temp1; while (ranansb < 0) ranansb += mod; ans += temp1; ans %= mod; dpw[i] = ans0 % mod; dpb[i] = 0; ans0 = ranans0 % mod; ansb = ranansb % mod; } } cout << ans << endl; return 0; } |
module uartmm(input clk,
input rst,
input RX,
output TX,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
reg [7:0] uart_din_r;
reg uart_valid_r;
reg uart_ready_r;
reg [7:0] input_axis_tdata;
reg input_axis_tvalid;
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
reg output_axis_tready;
uart _uart (
.clk(clk),
.rst(~rst),
.rxd(RX),
.txd(TX),
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
// 100MHz
.prescale(100000000/(115200*8)));
assign strobe_b_next = (addr_b == 65537) | (addr_b == 65538) | (addr_b == 65539);
assign data_b_next = (addr_b == 65537)?uart_valid_r:
(addr_b == 65538)?uart_ready_r:
(addr_b == 65539)?uart_din_r:0;
always @(posedge clk)
if (~rst) begin
uart_din_r <= 0;
uart_valid_r <= 0;
uart_ready_r <= 0;
input_axis_tdata <= 0;
input_axis_tvalid <= 0;
output_axis_tready <= 0;
end else begin
data_b <= data_b_next;
strobe_b <= strobe_b_next;
if (input_axis_tvalid) begin
input_axis_tvalid <= 0;
end
if (output_axis_tvalid & ~output_axis_tready) begin
output_axis_tready <= 1;
end
uart_ready_r <= input_axis_tready; // delay
if (output_axis_tvalid) begin
output_axis_tready <= 0;
uart_din_r <= output_axis_tdata;
uart_valid_r <= 1;
end else if ((addr_b == 65539) & ~data_b_we & uart_valid_r) begin
uart_valid_r <= 0;
end else if ((addr_b == 65539) & data_b_we & input_axis_tready & ~input_axis_tvalid) begin
input_axis_tdata <= data_b[7:0];
input_axis_tvalid <= 1;
end
end
endmodule
module ledwriter (input clk,
input rst,
output reg [15:0] LED,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
always @(posedge clk)
if (~rst) begin
LED <= 0;
end else begin
if (addr_b == 65540)
LED <= data_b_in[15:0];
end
endmodule
module socram(input clk,
input rst,
output reg [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
parameter RAM_DEPTH = 8192 * 2;
parameter INIT_FILE = "../../custom.hex";
reg [31:0] mem [0:RAM_DEPTH-1];
initial begin
if (INIT_FILE != "")
$readmemh(INIT_FILE, mem);
end
always @(posedge clk)
begin
if (data_b_we & (addr_b[31:16] == 0)) begin
mem[addr_b] <= data_b_in;
end
data_a <= mem[addr_a];
data_b <= mem[addr_b];
strobe_b <= (addr_b[31:16] == 0);
end
endmodule
module generic_mul ( a, b, clk, pdt);
parameter size = 32, level = 5;
input [size-1 : 0] a;
input [size-1 : 0] b;
input clk;
output [2*size-1 : 0] pdt;
reg [size-1 : 0] a_int, b_int;
reg [2*size-1 : 0] pdt_int [level-1 : 0];
integer i;
assign pdt = pdt_int [level-1];
always @ (posedge clk)
begin
a_int <= a;
b_int <= b;
pdt_int[0] <= a_int * b_int;
for(i =1;i <level;i =i +1)
pdt_int [i] <= pdt_int [i-1];
end
endmodule
module hls_Mul(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
reg [31:0] p0t;
reg [31:0] p1t;
reg [31:0] tmp1;
reg [31:0] tmp2;
reg [31:0] tmp3;
reg [31:0] tmp4;
assign out = tmp4;
generic_mul #(.size(32),.level(3)) mul1 (.clk(clk),
.a(p0),
.b(p1),
.pdt(out));
endmodule
module mul16x16 (input [15:0] a,
input [15:0] b,
output [31:0] o);
assign o = a * b;
endmodule // mul16x16
`include "../rtl/mul.v"
module hls_MulFSM(input clk,
input reset,
input req,
output ack,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
mul32x32_fsm S(.clk(clk),
.rst(reset),
.req(req),
.ack(ack),
.p0(p0),
.p1(p1),
.out(out));
endmodule // hls_MulFSM
module hlsblockram (input clk,
input [ABITWIDTH-1:0] readaddr1,
output reg [BITWIDTH-1:0] readout1,
input [ABITWIDTH-1:0] writeaddr1,
input [BITWIDTH-1:0] writein1,
input we
);
parameter SIZE = 32;
parameter BITWIDTH = 32;
parameter ABITWIDTH = 32;
reg [BITWIDTH-1:0] mem [0:SIZE-1];
// Expect 2-port (1ro+1wo) to be inferred
always @(posedge clk)
begin
if (we) begin
mem[writeaddr1] = writein1;
end
readout1 <= mem[readaddr1];
end
endmodule // toyblockram
`include "../rtl/div2.v"
// 8-stage integher division pipeline
module hls_Div(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire div0, ovf;
wire [31:0] rem;
div_pipelined2 #(.WIDTH(32)) d(.clk(clk),
.rst(reset),
.z(p0),
.d(p1),
.quot(out),
.rem(rem));
endmodule
// 8-stage integher division pipeline
module hls_Rem(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire [31:0] quot;
div_pipelined2 #(.WIDTH(32)) d(.clk(clk),
.rst(reset),
.z(p0),
.d(p1),
.quot(quot),
.rem(out));
endmodule
module sevenseg(input clk100mhz,
input [2:0] addr,
input [7:0] data,
input we,
output reg [7:0] seg,
output reg [7:0] an);
reg [7:0] mem[0:7];
always @(posedge clk100mhz)
begin
if (we) mem[addr] <= data;
end
reg [15:0] counter;
wire [2:0] caddr;
reg [2:0] pcaddr;
assign caddr = counter[15:13];
always @(posedge clk100mhz)
begin
counter <= counter + 1;
if (caddr != pcaddr) begin
// Common anode must be driven to low
if (caddr == 0) an <= (255-1);
else an <= (an << 1)|1'b1;
seg <= ~(mem[caddr]);
pcaddr <= caddr;
end
end
endmodule // sevenseg
module sevensegmm(input clk,
input rst,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we,
output [7:0] seg,
output [7:0] an);
wire [2:0] addr;
wire [7:0] data;
wire we;
sevenseg s7 (.clk100mhz(clk),
.addr(addr),
.data(data),
.we(we),
.seg(seg), .an(an));
assign we = (addr_b == 65553)?data_b_we:0;
assign data = data_b_in[7:0];
assign addr = data_b_in[10:8];
endmodule // sevensegmm
`ifdef ENABLE_SOUND
`include "soundctl.v"
`endif
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../lib/radar_config.vh"
module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
rx_adc_i_i,rx_adc_q_i,
rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o);
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
// Transmit subsystem
output tx_side_o; // Transmitter slot
output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
output io_tx_ena_o; // Transmit/Receive switching
// Receive subsystem
input [15:0] rx_adc_i_i; // I channel input from ADC
input [15:0] rx_adc_q_i; // Q channel input from ADC
output rx_strobe_o; // Indicates output samples ready for Rx FIFO
output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
// Application control
wire reset; // Master application reset
wire tx_side; // Transmitter slot
wire debug_enabled; // Enable debugging mode;
wire tx_enable; // Transmitter enable
wire rx_enable; // Receiver enable
wire tx_ctrl; // Transmitter on control
wire rx_ctrl; // Receiver on control
wire [15:0] pulse_num; // Count of pulses since tx_enabled
// Configuration
wire [15:0] ampl; // Pulse amplitude
wire [31:0] fstart; // Chirp start frequency
wire [31:0] fincr; // Chirp per strobe frequency increment
radar_control controller
(.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
.reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
.ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num),
.io_tx_ena_o(io_tx_ena_o));
radar_tx transmitter
( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o),
.ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr),
.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
radar_rx receiver
( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled),
.pulse_num_i(pulse_num),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
.rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
endmodule // radar
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using uint = unsigned int; using ull = unsigned long long; template <typename T> using pair2 = pair<T, T>; using pii = pair<int, int>; using pli = pair<ll, int>; using pll = pair<ll, ll>; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); inline void fmin(ll &x, ll y) { if (y < x) x = y; } inline void fmax(ll &x, ll y) { if (y > x) x = y; } double startTime; double getCurrentTime() { return ((double)clock() - startTime) / CLOCKS_PER_SEC; } const ll INF = 0x3f3f3f3f3f3f3f3f; const int N = 100100; const int M = (1 << 7) + 7; vector<int> a[N]; int n, k, p; int ppc[M]; ll dp[2][M]; int main() { for (int i = 0; i < M; i++) ppc[i] = ppc[i / 2] + (i & 1); scanf( %d%d%d , &n, &p, &k); for (int i = 0; i < n; i++) { a[i].resize(p + 1); scanf( %d , &a[i][0]); } for (int i = 0; i < n; i++) for (int j = 1; j <= p; j++) scanf( %d , &a[i][j]); sort(a, a + n); reverse(a, a + n); for (int mask = 0; mask < 1 << p; mask++) dp[0][mask] = -INF; dp[0][0] = 0; for (int i = 0; i < n; i++) { for (int mask = 0; mask < 1 << p; ++mask) dp[1][mask] = -INF; for (int mask = 0; mask < (1 << p); ++mask) { for (int j = 0; j < p; j++) { if (mask & (1 << j)) continue; fmax(dp[1][mask | (1 << j)], dp[0][mask] + a[i][j + 1]); } ll w = dp[0][mask]; if (ppc[mask] + k > i) w += a[i][0]; fmax(dp[1][mask], w); } for (int mask = 0; mask < (1 << p); ++mask) dp[0][mask] = dp[1][mask]; } printf( %lld n , dp[0][(1 << p) - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; class SuffixArrayBuilder { int n, gap; string s; vector<int> pos; public: SuffixArrayBuilder(string &s) : s(s) {} bool operator()(int i, int j) { if (pos[i] != pos[j]) return pos[i] < pos[j]; i += gap; j += gap; return ((i < n && j < n) ? pos[i] < pos[j] : i > j); } vector<int> buildSA() { n = (int)(s).size(); vector<int> sa(n), tmp(n); pos.resize(n); for (int i = (0); i <= ((int)(sa).size() - 1); ++i) sa[i] = i, pos[i] = s[i]; for (gap = 1;; gap *= 2) { sort(sa.begin(), sa.end(), ref(*this)); for (int i = (0); i <= (n - 2); ++i) tmp[i + 1] = tmp[i] + (*this)(sa[i], sa[i + 1]); for (int i = (0); i <= (n - 1); ++i) pos[sa[i]] = tmp[i]; if (tmp.back() == n - 1) return sa; } } vector<int> buildLCP(vector<int> &sa) { vector<int> lcp(n - 1); for (int i = 0, k = 0; i < n; ++i) if (pos[i] != n - 1) { for (int j = sa[pos[i] + 1]; s[i + k] == s[j + k];) k++; lcp[pos[i]] = k; if (k) k--; } return lcp; } }; vector<long long int> solve(string &p, string &q, string &r) { string s = p + # + q + $ + r; SuffixArrayBuilder Builder(s); vector<int> SA = Builder.buildSA(); vector<int> LCP = Builder.buildLCP(SA); int n = (int)(s).size(); int cnt[3][n]; int len[] = {0, (int)(p).size() + 1, (int)(q).size() + 1, (int)(r).size() + 1}; for (int i = (1); i <= (3); ++i) len[i] += len[i - 1]; for (int i = (0); i <= (2); ++i) for (int j = (0); j <= (n - 1); ++j) { cnt[i][j] = ((j) ? cnt[i][j - 1] : 0); cnt[i][j] += (SA[j] >= len[i] && SA[j] < len[i + 1] - 1); } vector<pair<int, int> > ord; for (int i = (0); i <= ((int)(LCP).size() - 1); ++i) ord.push_back(make_pair(LCP[i], i)); sort(ord.begin(), ord.end()); set<int> S; S.insert(-1); S.insert(n - 1); int m = min({(int)(p).size(), (int)(q).size(), (int)(r).size()}); vector<long long int> agg(m, 0); for (int i = (0); i <= ((int)(ord).size() - 1); ++i) { int pos = ord[i].second, L, R; auto it = S.lower_bound(pos); R = *it; it--; L = *it; long long int left[3], right[3], whole[3]; for (int i = (0); i <= (2); ++i) { left[i] = cnt[i][pos] - ((L >= 0) ? cnt[i][L] : 0); right[i] = cnt[i][R] - cnt[i][pos]; whole[i] = cnt[i][R] - ((L >= 0) ? cnt[i][L] : 0); } long long int ans = whole[0] * whole[1] * whole[2] - left[0] * left[1] * left[2] - right[0] * right[1] * right[2]; ans %= 1000000007; ans = (ans + 1000000007) % 1000000007; int val = ord[i].first; if (val > 0) { agg[val - 1] += ans; agg[val - 1] %= 1000000007; } S.insert(pos); } for (int i = (m - 2); i >= (0); --i) agg[i] = (agg[i] + agg[i + 1]) % 1000000007; return agg; } int main() { ios_base::sync_with_stdio(0); string p, q, r; cin >> p >> q >> r; vector<long long int> ans = solve(p, q, r); for (int i = (0); i <= ((int)(ans).size() - 1); ++i) cout << ans[i] << ; return 0; } |
`default_nettype none
`include "core.h"
module execute_mul(
input wire [4:0] iCMD,
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [31:0] oDATA,
output wire [4:0] oFLAGS
);
wire [63:0] mul_tmp;
wire mul_sf_l;
wire mul_cf_l;
wire mul_of_l;
wire mul_pf_l;
wire mul_zf_l;
wire mul_sf_h;
wire mul_cf_h;
wire mul_of_h;
wire mul_pf_h;
wire mul_zf_h;
assign mul_tmp = iDATA_0 * iDATA_1;
assign mul_sf_l = mul_tmp[31];
assign mul_cf_l = mul_tmp[32];
assign mul_of_l = mul_tmp[31] ^ mul_tmp[32];
assign mul_pf_l = mul_tmp[0];
assign mul_zf_l = (mul_tmp == {64{1'b0}})? 1'b1 : 1'b0;
assign mul_sf_h = mul_tmp[63];
assign mul_cf_h = 1'b0;
assign mul_of_h = 1'b0;
assign mul_pf_h = mul_tmp[32];
assign mul_zf_h = (mul_tmp == {64{1'b0}})? 1'b1 : 1'b0;
assign oFLAGS = (iCMD == `EXE_MUL_MULH || iCMD == `EXE_MUL_UMULH)? {mul_sf_h, mul_of_h, mul_cf_h, mul_pf_h, mul_zf_h} : {mul_sf_l, mul_of_l, mul_cf_l, mul_pf_l, mul_zf_l};
assign oDATA = (iCMD == `EXE_MUL_MULH || iCMD == `EXE_MUL_UMULH)? mul_tmp[63:32] : mul_tmp[31:0];
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, a; cin >> n >> a; map<int, int> my; set<int> rem; int ca = 0; for (int i = 0; i < n; ++i) { int x; cin >> x; if (x == a) { ++ca; } else { if (rem.find(x) != rem.end()) continue; my[x]++; if (my[x] <= ca) { my.erase(x); rem.insert(x); } } } if (my.empty()) { cout << -1 n ; return 0; } else { for (auto it : my) { if (it.second >= ca) { cout << it.first << n ; return 0; } } } cout << -1 n ; } |
// MBT 9/3/2016
//
// note: this does a reduction
//
`define bsg_andr_macro(bits) \
if (harden_p && (width_p<=bits)) \
begin: macro \
wire [bits-1:0] widen = bits ' (i); \
bsg_rp_tsmc_40_reduce_and_b``bits andr(.i(widen),.o); \
end
module bsg_reduce #(parameter `BSG_INV_PARAM(width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter harden_p = 0
)
(input [width_p-1:0] i
, output o
);
// synopsys translate_off
initial
assert( $countones({xor_p & 1'b1, and_p & 1'b1, or_p & 1'b1}) == 1)
else $error("bsg_scan: only one function may be selected\n");
// synopsys translate_on
if (xor_p)
begin: xorr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = ^i;
end:xorr
else if (and_p)
begin: andr
if (width_p < 4)
begin: notmacro
assign o = &i;
end else
`bsg_andr_macro(4) else
`bsg_andr_macro(6) else
`bsg_andr_macro(8) else
`bsg_andr_macro(9) else
`bsg_andr_macro(12) else
`bsg_andr_macro(16) else
begin: notmacro
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = &i;
end
end
else if (or_p)
begin: orr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = |i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_reduce)
|
`timescale 1ns / 10ps
module piso_shift_register_testbench;
reg clk, reset_n, load_a, load_b, shift;
reg [7:0] par_in_a, par_in_b;
wire ser_out;
piso_shift_register uut
(.clk(clk), .reset_n(reset_n), .par_in_a(par_in_a), .par_in_b(par_in_b),
.load_a(load_a), .load_b(load_b), .shift(shift), .ser_out(ser_out));
always begin // 50MHz clock
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end
initial begin
load_a = 0;
load_b = 0;
par_in_a = 0;
par_in_b = 0;
shift = 0;
reset_n = 0;
#40;
reset_n = 1;
par_in_a = 8'b10101110;
#20;
load_a = 1;
#20;
load_a = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
#20;
shift = 1;
#20;
shift = 0;
$stop;
end // initial begin
endmodule // piso_testbench
|
#include <bits/stdc++.h> using namespace std; vector<int long long> fact(1000001); int long long sm, a, b, n; bool check() { int long long m = sm; while (m) { if (m % 10 != b && m % 10 != a) return 0; m /= 10; } return 1; } int long long inc(int long long t, int long long p) { if (p == 0) return 1; if (p % 2 == 0) { int long long e = inc(t, p / 2); return (e * e) % 1000003; } else { return (inc(t, p - 1) * t) % 1000003; } } int long long comb(int long long i, int long long m) { return (fact[m] * (inc(((fact[m - i] * fact[i]) % 1000003), 1000003 - 2) % 1000003)) % 1000003; } int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); int long long a, b; cin >> a >> b; fact[0] = fact[1] = 1; for (long long i = 2; i <= 1000000; i++) fact[i] = i * fact[i - 1], fact[i] %= 1000003; cout << comb(b, a + b) - 1 << endl; } |
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* Simple testcase for SGMII TBI logic
*/
module testbench();
reg rst;
reg clk_125mhz;
reg clk_125mhz_gen;
integer cycle_count;
initial
begin
rst = 1;
clk_125mhz_gen = 0;
$dumpfile("results.vcd");
$dumpvars(0);
cycle_count = 0;
#125 rst = 0;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#23 rst = 1;
#23 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen;
#125 clk_125mhz_gen = ~clk_125mhz_gen; rst = 0;
while (1)
begin
#125 clk_125mhz_gen = ~clk_125mhz_gen;
cycle_count = (clk_125mhz_gen) ? cycle_count : cycle_count + 1;
if (cycle_count > 35000)
begin
$display("*** ERROR: Cycle Count Max ***");
$finish();
end
end
end
always @ (clk_125mhz_gen)
clk_125mhz <= clk_125mhz_gen;
reg
//
// Slightly faster clock
//
reg clk_126mhz;
reg clk_126mhz_gen;
initial
begin
clk_126mhz_gen = 0;
while (1)
#124 clk_126mhz_gen = ~clk_126mhz_gen;
end
always @ (clk_126mhz_gen)
clk_126mhz <= clk_126mhz_gen;
//
// Slightly slower clock
//
reg clk_124mhz;
reg clk_124mhz_gen;
initial
begin
clk_124mhz_gen = 0;
while (1)
#126 clk_124mhz_gen = ~clk_124mhz_gen;
end
always @ (clk_124mhz_gen)
clk_124mhz <= clk_124mhz_gen;
//
// Test state machine
//
integer tstate;
reg [7:0] gmii_txd_main;
reg gmii_tx_en_main;
reg gmii_tx_err_main;
wire [7:0] gmii_rxd_main;
wire gmii_rx_dv_main;
wire gmii_rx_err_main;
wire autoneg_complete_main;
wire [15:0] config_reg_main;
wire autoneg_complete_loop;
wire [15:0] config_reg_loop;
always @ (posedge clk_125mhz or posedge rst)
if (rst)
tstate <= 0;
else
case (tstate)
20: if (autoneg_complete_main) tstate <= tstate + 1;
25: if (autoneg_complete_loop) tstate <= tstate + 1;
default: tstate <= tstate + 1;
endcase
always @ (posedge clk_125mhz or posedge rst)
if (rst)
begin
gmii_txd_main <= 8'd0;
gmii_tx_en_main <= 1'b0;
gmii_tx_err_main <= 1'b0;
end
else
case (tstate)
30:
if (config_reg_main != 16'h4001)
begin
$display(" !!! BAD AUTONEG Value from MAIN !!!");
$finish();
end
31:
if (config_reg_loop != 16'h4001)
begin
$display(" !!! BAD AUTONEG Value from LOOP !!!");
$finish();
end
40:
begin
gmii_txd_main <= 8'h77;
gmii_tx_en_main <= 1'b1;
end
41: gmii_txd_main <= 8'h88;
42: gmii_txd_main <= 8'h99;
43: gmii_txd_main <= 8'h50;
44: gmii_txd_main <= 8'h51;
45: gmii_txd_main <= 8'h52;
46: gmii_tx_en_main <= 1'b0;
60:
begin
gmii_txd_main <= 8'h99;
gmii_tx_en_main <= 1'b1;
end
61: gmii_txd_main <= 8'h88;
62: gmii_txd_main <= 8'h77;
63: gmii_txd_main <= 8'h20;
64:
begin
gmii_txd_main <= 8'h21;
gmii_tx_err_main <= 1'b1;
end
65:
begin
gmii_txd_main <= 8'h22;
gmii_tx_err_main <= 1'b0;
end
66: gmii_tx_en_main <= 1'b0;
100:
begin
gmii_txd_main <= 8'd0;
gmii_tx_en_main <= 1'b1;
end
101: gmii_txd_main <= 8'd1;
102: gmii_txd_main <= 8'd2;
103: gmii_txd_main <= 8'd3;
104: gmii_txd_main <= 8'd4;
105: gmii_txd_main <= 8'd5;
106: gmii_txd_main <= 8'd6;
107: gmii_txd_main <= 8'd7;
108: gmii_txd_main <= 8'd8;
109: gmii_txd_main <= 8'd9;
110: gmii_txd_main <= 8'd10;
111: gmii_txd_main <= 8'd11;
112: gmii_txd_main <= 8'd12;
113: gmii_txd_main <= 8'd13;
114: gmii_txd_main <= 8'd14;
115: gmii_txd_main <= 8'd15;
116: gmii_txd_main <= 8'd16;
117: gmii_txd_main <= 8'd17;
118: gmii_txd_main <= 8'd18;
119: gmii_txd_main <= 8'd19;
120: gmii_txd_main <= 8'd20;
121: gmii_txd_main <= 8'd21;
122: gmii_txd_main <= 8'd22;
123: gmii_txd_main <= 8'd23;
124: gmii_txd_main <= 8'd24;
125: gmii_txd_main <= 8'd25;
126: gmii_txd_main <= 8'd26;
127: gmii_txd_main <= 8'd27;
128: gmii_txd_main <= 8'd28;
129: gmii_txd_main <= 8'd29;
130: gmii_txd_main <= 8'd30;
131: gmii_txd_main <= 8'd31;
132: gmii_txd_main <= 8'd32;
133: gmii_txd_main <= 8'd33;
134: gmii_txd_main <= 8'd34;
135: gmii_txd_main <= 8'd35;
136: gmii_txd_main <= 8'd36;
137: gmii_txd_main <= 8'd37;
138: gmii_txd_main <= 8'd38;
139: gmii_txd_main <= 8'd39;
140: gmii_tx_en_main <= 1'b0;
10000: $finish();
default: ;
endcase
//
// DUT instance - loopback one to the other
//
wire [7:0] gmii_txd_loop;
wire gmii_tx_en_loop;
wire gmii_tx_err_loop;
wire [9:0] tbi_rxd;
wire [9:0] tbi_txd;
sgmii_tbi #(.LINK_TIMER(16'd1100)) sgmii_tbi_main
(
.clk_125mhz(clk_125mhz),
.rst(rst),
.autoneg_complete(autoneg_complete_main),
.config_reg(config_reg_main),
.gmii_rxd(gmii_rxd_main),
.gmii_rx_dv(gmii_rx_dv_main),
.gmii_rx_err(gmii_rx_err_main),
.gmii_txd(gmii_txd_main),
.gmii_tx_en(gmii_tx_en_main),
.gmii_tx_err(gmii_tx_err_main),
.tbi_rx_clk(clk_124mhz),
.tbi_rxd(tbi_rxd),
.tbi_tx_clk(clk_126mhz),
.tbi_txd(tbi_txd)
);
sgmii_tbi #(.LINK_TIMER(16'd1000)) sgmii_tbi_loopback
(
.clk_125mhz(clk_125mhz),
.rst(rst),
.autoneg_complete(autoneg_complete_loop),
.config_reg(config_reg_loop),
.gmii_rxd(gmii_txd_loop),
.gmii_rx_dv(gmii_tx_en_loop),
.gmii_rx_err(gmii_tx_err_loop),
.gmii_txd(gmii_txd_loop),
.gmii_tx_en(gmii_tx_en_loop),
.gmii_tx_err(gmii_tx_err_loop),
.tbi_rx_clk(clk_126mhz),
.tbi_rxd(tbi_txd),
.tbi_tx_clk(clk_124mhz),
.tbi_txd(tbi_rxd)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/26/2017 08:55:11 PM
// Design Name:
// Module Name: BRANCH_PREDICTOR
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BRANCH_PREDICTOR #(
parameter ADDRESS_WIDTH = 32 ,
parameter HIGH = 1'b1 ,
parameter LOW = 1'b0
) (
input CLK ,
input [ADDRESS_WIDTH - 1 : 0] PC ,
input [ADDRESS_WIDTH - 1 : 0] PC_EXECUTION ,
input [ADDRESS_WIDTH - 1 : 0] PC_PREDICT_LEARN ,
input PC_PREDICT_LEARN_SELECT ,
output [ADDRESS_WIDTH - 1 : 0] PC_PREDICTED ,
output PC_PREDICTOR_STATUS
);
reg [ADDRESS_WIDTH - 1 : 0] pc_predicted_reg ;
reg pc_predictor_status_reg ;
initial
begin
pc_predicted_reg = 32'b0 ;
pc_predictor_status_reg = LOW ;
end
always@(*)
begin
end
always@(CLK)
begin
end
assign PC_PREDICTED = pc_predicted_reg ;
assign PC_PREDICTOR_STATUS = pc_predictor_status_reg ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; while (k--) { int n; cin >> n; vector<int> h(n); for (int i = 0; i < n; i++) cin >> h[i]; sort(h.begin(), h.end()); reverse(h.begin(), h.end()); int ans = 0; for (int i = 0; i < n; i++) { int w1 = i + 1; if (h[i] >= w1) { ans = max(ans, w1); } } cout << ans << endl; } return 0; } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module num (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [12 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("num.mif"),
.C_INIT_FILE("num.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(5778),
.C_READ_DEPTH_A(5778),
.C_ADDRA_WIDTH(13),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(5778),
.C_READ_DEPTH_B(5778),
.C_ADDRB_WIDTH(13),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("2"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.652585 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(13'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1 ns / 1 ps
module fillbox_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h10000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0,
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
// input wire m00_axi_init_axi_txn,
output wire m00_axi_txn_done,
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready,
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// user signals
wire [27:0] vram;
wire [9:0] width;
wire [9:0] height;
wire [15:0] color;
wire start;
wire done;
assign m00_axi_txn_done = done;
// Instantiation of Axi Bus Interface M00_AXI
fillbox_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) fillbox_v1_0_M00_AXI_inst (
// user part start
.vram(vram),
.width(width),
.height(height),
.color(color),
.INIT_AXI_TXN(start),
.TXN_DONE(done),
// user part end
.ERROR(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Instantiation of Axi Bus Interface S00_AXI
fillbox_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) fillbox_v1_0_S00_AXI_inst (
// user part start
.vram(vram),
.width(width),
.height(height),
.color(color),
.start(start),
.done(done),
// user part end
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
//-----------------------------------------------------------------------------
// File : wb_master.v
// Creation date : 15.05.2017
// Creation time : 14:00:41
// Description : A verilog master that has a register array of data it uses to write to a slave. Each data is written to different address, and then read to verify it worked. Address space is assumed to be contiguous.
// Created by : TermosPullo
// Tool : Kactus2 3.4.104 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:communication.template:wb_master:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.template/wb_master/1.0/wb_master.1.0.xml
//-----------------------------------------------------------------------------
module wb_master #(
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter DATA_WIDTH = 32, // The width of the both transferred and inputted data.
parameter BASE_ADDRESS = 'h0F00, // The first referred address of the master.
parameter SEND_ERR_ADDR = 0 // If one, the initial phase will use an erroneous address.
) (
// Interface: wb_master
input ack_i, // Slave asserts acknowledge.
input [DATA_WIDTH-1:0] dat_i, // Data from slave to master.
input err_i, // Indicates abnormal cycle termination.
output reg [ADDR_WIDTH-1:0] adr_o, // The address of the data.
output reg cyc_o, // Asserted by master for transfer.
output reg [DATA_WIDTH-1:0] dat_o, // Data from master to slave.
output reg stb_o, // Asserted by master for transfer.
output reg we_o, // Write = 1, Read = 0.
// Interface: wb_system
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i, // The mandatory reset, as this is synchronous logic.
// These ports are not in any interface
input start, // Input used to signal that is is ok to start the masters.
output reg done // Output used to signal that the masters are done sending.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam AUB = 8; // Bits in a byte.
localparam AU_IN_DATA = DATA_WIDTH/AUB; // Bytes in data.
localparam MAX_WAIT = 1000; // Wait for slave only for this many iterations.
// We have as data to send as parameterized.
reg [DATA_WIDTH-1:0] register_file [DATA_COUNT-1:0];
// Used to iterate register file.
reg [$clog2(DATA_COUNT)-1:0] iterator;
// The current state.
reg [2:0] state;
// Used in loops.
integer index;
// In simulations, we may opt to wait only so many iterations before
integer wait_count;
// The available states.
parameter [2:0]
S_START = 3'd0, // The initial state.
S_BOGUS_INIT = 3'd1, // Write to address that is likely wrong.
S_WAIT_BOGUS_ACK = 3'd2, // Waiting ack for the bogus cycle.
S_WRITE_INIT = 3'd3, // Initiating a write to slave.
S_WAIT_WRITE_ACK = 3'd4, // Waiting ack for write from slave.
S_READ_INIT = 3'd5, // Initiating a read to slave.
S_WAIT_READ_ACK = 3'd6; // Waiting ack for write from slave.
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
// Initialize register_file with data.
for (index = 0; index < DATA_COUNT; index = index + 1) begin
register_file[index] = {AU_IN_DATA{index[AUB-1:0]}};
end
// Initally waiting for start signal.
state <= S_START;
// Everything else is zero.
dat_o <= 0;
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
done <= 0;
iterator <= 0;
adr_o <= 0;
wait_count = 0;
end
else begin
case(state)
S_START: begin
// Once it has started, initiate a write.
if (SEND_ERR_ADDR) begin
state <= S_BOGUS_INIT;
end
else begin
state <= S_WRITE_INIT;
end
// Nothing is done yet.
done <= 0;
// Reset iterator, so that we may go through the array.
iterator <= 0;
end
S_BOGUS_INIT: begin
// Assert signals indicating we are ready to transfer.
cyc_o <= 1;
stb_o <= 1;
// We are writing to slave.
we_o <= 1;
// Put in a bogus address
adr_o <= BASE_ADDRESS - 10;
// Next we shall wait for acknowledgement.
state <= S_WAIT_BOGUS_ACK;
// Reset wait.
wait_count = 0;
end
S_WAIT_BOGUS_ACK: begin
if (err_i == 1'b1) begin
// Error signal received! Deassert initiator signals.
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
// Next we will proceed to non-bogus addresses.
state <= S_WRITE_INIT;
end
// Wait only for so long.
if (wait_count > MAX_WAIT)
$stop;
wait_count = wait_count + 1;
end
S_WRITE_INIT: begin
// Assert signals indicating we are ready to transfer.
cyc_o <= 1;
stb_o <= 1;
// We are writing to slave.
we_o <= 1;
// Take output data from the register array.
dat_o <= register_file[iterator];
// Offset our base address by the iterator, thus placing each iteration on separate location on slave.
// Also, multiply with addressable units, so that the iterations wont overlap.
adr_o <= (iterator * AU_IN_DATA) + BASE_ADDRESS;
// Next we shall wait for acknowledgement.
state <= S_WAIT_WRITE_ACK;
// Reset wait.
wait_count = 0;
end
S_WAIT_WRITE_ACK: begin
if (ack_i == 1'b1) begin
// Acknowledgement received! Deassert initiator signals.
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
// Next we will read.
state <= S_READ_INIT;
end
// Wait only for so long.
if (wait_count > MAX_WAIT)
$stop;
wait_count = wait_count + 1;
end
S_READ_INIT: begin
// Assert signals indicating we are ready to transfer.
cyc_o <= 1;
stb_o <= 1;
// We are reading from slave.
we_o <= 0;
// Next we shall wait for acknowledgement.
state <= S_WAIT_READ_ACK;
end
S_WAIT_READ_ACK: begin
if (ack_i == 1'b1) begin
// Acknowledgement received! Deassert initiator signals.
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
// It was read from the same address as was written, so it should be the same data.
if (register_file[iterator] != dat_i) begin
$display("ERROR: Wrong answer from slave: %X", dat_i);
$stop;
end
if (iterator == DATA_COUNT-1) begin
// We have gone through the whole register array, means we are done.
done <= 1;
// But we will wait for signal to start again.
$stop();
end
else begin
// More data to send, means we increase iterator...
iterator <= iterator + 1;
// ...and initiate next write.
state <= S_WRITE_INIT;
// Reset wait.
wait_count = 0;
end
end
// Wait only for so long.
if (wait_count > MAX_WAIT)
$stop;
wait_count = wait_count + 1;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int _I() { int x; scanf( %d , &x); return x; } long long _L() { long long x; scanf( %lld , &x); return x; } long long gcd(long long a, long long b) { while (b) b ^= a ^= b ^= a %= b; return a; } long long lcm(long long x, long long y) { x /= gcd(x, y); return x * y; } int kdx[8] = {-2, -2, -1, -1, 1, 1, 2, 2}; int kdy[8] = {-1, 1, -2, 2, -2, 2, -1, 1}; long long _pow(long long a, long long b) { if (b == 0) return 1; long long ret = 1; ret *= _pow(a, b / 2); ret = ret * ret; if (b & 1) { ret *= a; } return ret; } bool inrng(long long x, long long y, long long c) { return (x <= c && c <= y); } bool inRng(int a, int b, int x, int y) { return (inrng(a, b, x) || inrng(a, b, y) || inrng(x, y, a) || inrng(x, y, b)); } struct data { int x = 0, y = 0; }; int cases; map<char, int> mp; void lipu_mira() { long long i, j, a, b, n, k, v, x, ans = 0, now; a = _L(); b = _L(); k = _L(); if (a > b) swap(a, b); x = a; v = b - a; ans += x; k -= x; if (k < v) { puts( -1 ); return; } else if (k == v) { ans += (k - (k & 1)); } else { if (v & 1) ans += (k - 1); else { if (k & 1) { ans += k - 2; } else ans += k; } } printf( %lld n , ans); } int main() { int t = _I(); while (t--) lipu_mira(); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:01 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axi_gpio_0_0 -prefix
// design_1_axi_gpio_0_0_ design_1_axi_gpio_0_0_stub.v
// Design : design_1_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module design_1_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio2_io_i[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
input [3:0]gpio2_io_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int A[n][m], B[n][m], C[n][m]; vector<int> a, b; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> A[i][j]; a.push_back(A[i][j]); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> B[i][j]; b.push_back(B[i][j]); } } sort(a.begin(), a.end()); sort(b.begin(), b.end()); for (int i = 0; i < a.size(); i++) { if (a[i] != b[i]) { cout << NO << endl; return 0; } } if (n >= m) { for (int i = 0; i < n; i++) { long long x = 0; for (int j = 0; j < min(i + 1, m); j++) { x ^= (long long)(A[i - j][j] ^ B[i - j][j]); } if (x) { cout << NO << endl; return 0; } } for (int i = 0; i < m - 1; i++) { long long x = 0; for (int j = 1; j + i < m; j++) { x ^= (long long)(A[n - j][j + i] ^ B[n - j][j + i]); } if (x) { cout << NO << endl; return 0; } } } else { for (int i = 0; i < m; i++) { long long x = 0; for (int j = 0; j < min(i + 1, n); j++) { x ^= (long long)(A[j][i - j] ^ B[j][i - j]); } if (x) { cout << NO << endl; return 0; } } for (int i = 0; i < n - 1; i++) { long long x = 0; for (int j = 1; j + i < n; j++) { x ^= (long long)(A[j + i][m - j] ^ B[j + i][m - j]); } if (x) { cout << NO << endl; return 0; } } } cout << YES << endl; } |
#include <bits/stdc++.h> using namespace std; long long i, j, k, l, m, n, s, t, p, q, a, b, aa, bb, d; char c[2222222]; int main() { t = 1; while (gets(c) != 0) { for (i = 0; c[i] != 0; i++) if (c[i] != ) break; if (c[i] == # ) { if (t == 0) puts( ); puts(c); t = 1; } else { for (i = 0; c[i] != 0; i++) if (c[i] != ) cout << c[i]; t = 0; } } if (t == 0) puts( ); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a[222222]; scanf( %d n , &n); pair<int, int> p; vector<pair<int, int> > v, v1; for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); p.first = x; p.second = 0; v.push_back(p); } reverse(v.begin(), v.end()); int maxi = v[0].first, pos = 0; ; for (int i = 0; i < v.size(); i++) { if (pos != i) { if (maxi >= v[i].first) v[i].second = maxi - v[i].first + 1; if (maxi < v[i].first) { maxi = v[i].first; pos = i; } } } reverse(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) printf( %d , v[i].second); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A222O_PP_BLACKBOX_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////
//
// Main
//
//////////////////////////////////////////////////////////////////////////////
module test();
integer count;
bit test_clk;
// Create a test clock
always #01.8 test_clk = ~test_clk;
//**********************************************************************
// Testing.
// Shift a moving set of ones up the input vector. At each shift
// the outputs should change, which is checked by the assertions
// below. This test doesnt care which output changes, as that was
// checked to be accurate by formal means.
//**********************************************************************
initial begin
count=0;
end
always @(posedge test_clk) begin
count++;
end
//**********************************************************************
// SV assertions
//**********************************************************************
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
lane_inputs);
end // UNMATCHED !!
endproperty //FIXME
property p_sup_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(sup_inputs) |-> !$stable(sup_outputs);
endproperty
a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
sup_inputs);
end
endproperty
endmodule // test
|
#include <bits/stdc++.h> using namespace std; long long s(long long x) { long long sum = 0; while (x) { sum += x % 10; x /= 10; } return sum; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long T; T = 1; while (T--) { long long n, i, x, ans = -1; cin >> n; x = sqrt(n); for (i = 1; i <= 90; i++) { long long l, r; l = 1; r = x; while (l <= r) { long long m = l + (r - l) / 2; long long z = m * m + m * i; if (z == n && s(m) == i) ans = m, r = m - 1; else if (z < n) l = m + 1; else r = m - 1; } } cout << ans << n ; } return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SOC_NIOS_II_mult_cell (
// inputs:
M_mul_src1,
M_mul_src2,
clk,
reset_n,
// outputs:
M_mul_cell_result
)
;
output [ 31: 0] M_mul_cell_result;
input [ 31: 0] M_mul_src1;
input [ 31: 0] M_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_result;
wire [ 31: 0] M_mul_cell_result_part_1;
wire [ 15: 0] M_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[15 : 0]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEII",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[31 : 16]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEII",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign M_mul_cell_result = {M_mul_cell_result_part_1[31 : 16] +
M_mul_cell_result_part_2,
M_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int inf = (int)1e9; const double inf1 = 1e-9; const int ss = (int)1e6 + 3; int main() { string s; getline(cin, s); int sz = s.find( . ); int z1 = 0; if (sz == -1) { sz = s.size(); z1 = -1; } string res; int z = 0; if (s[0] == - ) { res = ( ; z = 1; } res += $ ; for (int i = z; i < (sz - z) % 3 + z; ++i) res += s[i]; if ((sz - z) % 3 != 0) res += , ; string tmp; for (int i = (sz - z) % 3 + z; i < sz; i += 3) { res += s[i]; res += s[i + 1]; res += s[i + 2]; res += , ; } res.erase(res.size() - 1, 1); res += . ; s += 00 ; res += s[sz + 1 + z1]; res += s[sz + 2 + z1]; if (s[0] == - ) { res += ) ; } cout << res; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_TB_V
`define SKY130_FD_SC_HS__DFRTN_TB_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__dfrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_TB_V
|
/*
-- ============================================================================
-- FILE NAME : spm.v
-- DESCRIPTION : spm RAMÄ£¿é
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ???????
-- ============================================================================
*/
/********** ͨÓÃÍ·Îļþ **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** Ä£¿éÍ·Îļþ**********/
`include "spm.h"
/********** Ä£¿é **********/
module spm (
/********** ÊäÈëÊä³ö²ÎÊý **********/
input wire clk, // ʱÖÓ
/********** ¶Ë¿ÚA : IF½×¶Î **********/
input wire [`SpmAddrBus] if_spm_addr, // ?????
input wire if_spm_as_, // ??????????`??
input wire if_spm_rw, // ?i???????
input wire [`WordDataBus] if_spm_wr_data, // ?????z???`??
output wire [`WordDataBus] if_spm_rd_data, // ?i???????`??
/********** ¶Ë¿ÚB : MEM½×¶Î **********/
input wire [`SpmAddrBus] mem_spm_addr, // ?????
input wire mem_spm_as_, // ??????????`??
input wire mem_spm_rw, // ?i???????
input wire [`WordDataBus] mem_spm_wr_data, // ?????z???`??
output wire [`WordDataBus] mem_spm_rd_data // ?i???????`??
);
/********** ?????z???????? **********/
reg wea; // ??`?? A
reg web; // ??`?? B
/********** ?????z????????????? **********/
always @(*) begin
/* ¶Ë¿ÚA */
if ((if_spm_as_ == `ENABLE_) && (if_spm_rw == `WRITE)) begin
wea = `MEM_ENABLE; // ?????z?????
end else begin
wea = `MEM_DISABLE; // ?????z??o??
end
/* ¶Ë¿ÚB */
if ((mem_spm_as_ == `ENABLE_) && (mem_spm_rw == `WRITE)) begin
web = `MEM_ENABLE; // ?????z?????
end else begin
web = `MEM_DISABLE; // ?????z??o??
end
end
/********** Xilinx FPGA Block RAM :->altera_dpram **********/
altera_dpram x_s3e_dpram (
/********** ¶Ë¿ÚA : IF????`?? **********/
.clock_a (clk), // ????a?
.address_a (if_spm_addr), // ?????
.data_a (if_spm_wr_data), // ?????z???`????????A??
.wren_a (wea), // ?????z???????????`???
.q_a (if_spm_rd_data), // ?i???????`??
/********** ¶Ë¿ÚB : MEM????`?? **********/
.clock_b (clk), // ????a?
.address_b (mem_spm_addr), // ?????
.data_b (mem_spm_wr_data), // ?????z???`??
.wren_b (web), // ?????z?????
.q_b (mem_spm_rd_data) // ?i???????`??
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level module of pwm16
//
// ====================================================================
module sirv_pwm16_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_pwm16 u_sirv_pwm16(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_interrupts_0_1 (io_interrupts_0_1 ),
.io_interrupts_0_2 (io_interrupts_0_2 ),
.io_interrupts_0_3 (io_interrupts_0_3 ),
.io_gpio_0 (io_gpio_0 ),
.io_gpio_1 (io_gpio_1 ),
.io_gpio_2 (io_gpio_2 ),
.io_gpio_3 (io_gpio_3 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, cnt = 0; cin >> n; for (long long i = 2; i <= sqrt(n); i++) { long long int temp[n]; if ((i * i * i) <= n) cnt++; } cout << cnt + 1 << endl; } void opti() { long long int n; cin >> n; set<int> a; for (int i = 1; i * i <= n; i++) { a.insert(i * i); } for (int i = 1; i * i * i <= n; i++) { a.insert(i * i * i); } cout << a.size() << endl; } int main() { int t; cin >> t; while (t--) opti(); return 0; } |
`timescale 1 ns / 1 ps
module psd_counter #
(
parameter integer PERIOD = 256,
parameter integer PERIOD_WIDTH = 8,
parameter integer N_CYCLES = 2048,
parameter integer N_CYCLES_WIDTH = 11
)
(
input wire clk,
input wire s_axis_tvalid,
input wire [32-1:0] s_axis_tdata,
output wire m_axis_tvalid,
output wire [32-1:0] m_axis_tdata,
output reg [PERIOD_WIDTH+1:0] addr,
output reg [N_CYCLES_WIDTH-1:0] cycle_index,
output reg first_cycle,
output reg last_cycle
);
reg [PERIOD_WIDTH-1:0] cnt;
reg [N_CYCLES_WIDTH-1:0] cycle_index_reg;
initial cnt = 0;
initial cycle_index_reg = 0;
always @(posedge clk) begin
addr <= {{cnt}, {2'b0}};
cycle_index <= cycle_index_reg;
first_cycle <= ((cnt < PERIOD) && (cycle_index_reg == 0));
last_cycle <= ((cnt < PERIOD) && (cycle_index_reg == N_CYCLES - 1));
end
always @(posedge clk) begin
if (s_axis_tvalid) begin
if (cnt < PERIOD - 1) begin
cnt <= cnt + 1;
end else begin
cnt <= 0;
if (cycle_index < N_CYCLES - 1) begin
cycle_index_reg <= cycle_index_reg + 1;
end else begin
cycle_index_reg <= 0;
end
end
end
end
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
endmodule
|
`timescale 1ns / 1ps
// Name: WcaStrobe.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaDspStrobe(
clock,
reset, //Resets the counter.
strobe_in, //
enable,
rate, //Strobe rate.
strobe_out, //strobe signal.
count //Optional Strobe Counter output.
);
parameter INITIAL_VAL = 24'd0;
parameter INCREMENT_VAL = 24'h1;
input wire clock, reset, enable, strobe_in;
input wire [23: 0] rate;
output wire strobe_out;
output reg [23:0] count;
assign strobe_out = count == rate;
always @(posedge clock)
if(reset | ~enable | strobe_out)
count <= #1 INITIAL_VAL;
else if( strobe_in)
count <= #1 count + INCREMENT_VAL;
//Implment internal counter.
/*
DspCounter24 dspctcor( .clk(clock), .up( 1'b0), .load( strobe | reset), .l( rate), .q( count) );
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> p, h, st; vector<vector<int>> adj; int gst(int curr, int prev) { int res = p[curr]; for (int next : adj[curr]) { if (next != prev) { res += gst(next, curr); } } return st[curr] = res; } int dfs(int curr, int prev, int& res) { int g = st[curr] + h[curr]; if (g % 2) res = 0; int gv = g / 2; if (gv < 0 || gv > st[curr]) res = 0; int cgv = 0; for (int next : adj[curr]) { if (next != prev) { cgv += dfs(next, curr, res); } } if (cgv > gv) res = 0; return gv; } string solve() { cin >> n >> m; adj.clear(); adj.resize(n + 1); p.assign(n + 1, 0); h.assign(n + 1, 0); st.assign(n + 1, 0); for (int i = 1; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) cin >> h[i]; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } gst(1, 0); int res = 1; dfs(1, 0, res); if (!res) return NO ; return YES ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { cout << solve() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using int64 = long long int; const int kModulo = 1000000007; struct Edge { int from, to; }; vector<int> Inverse(const vector<int>& a) { const int n = a.size(); vector<int> result(n); for (int i = 0; i < n; ++i) { result[a[i] - 1] = i; } return result; } vector<int> ComputePhi(const int n) { vector<int> phi(n + 1); for (int i = 0; i <= n; ++i) { phi[i] = i; } for (int i = 2; i <= n; ++i) { if (phi[i] != i) { continue; } for (int j = i; j <= n; j += i) { phi[j] = (phi[j] / i) * (i - 1); } } return phi; } vector<vector<int>> ComputeDivisors(const int n) { vector<vector<int>> divisors(n + 1); for (int i = 1; i <= n; ++i) { for (int j = i; j <= n; j += i) { divisors[j].push_back(i); } } return divisors; } int64 ModInverse(const int64 x) { int64 u = x; int64 v = kModulo; int64 p1 = 1, q1 = 0; int64 p2 = 0, q2 = 1; while (v != 0) { const int64 q = u / v; const int64 p3 = p1 - q * p2; const int64 q3 = q1 - q * q2; const int64 r = u - q * v; u = v; v = r; p1 = p2; p2 = p3; q1 = q2; q2 = q3; } if (p1 < 0) { p1 += kModulo; } if (p1 >= kModulo) { p1 -= kModulo; } return p1; } vector<int64> ComputeCoefs(const vector<int>& phi) { const int n = phi.size(); vector<int> mu(n + 1, 1); for (int i = 2; i <= n; ++i) { if (phi[i] != i - 1) { continue; } for (int j = i; j <= n; j += i) { mu[j] = -mu[j]; } const int64 ii = static_cast<int64>(i) * i; for (int64 j = ii; j <= n; j += ii) { mu[j] = 0; } } vector<int64> c(n + 1); for (int g = 1; g <= n; ++g) { const int64 cur = (g * ModInverse(phi[g])) % kModulo; for (int d = g; d <= n; d += g) { c[d] += mu[d / g] * cur; if (c[d] < 0) { c[d] += kModulo; } if (c[d] >= kModulo) { c[d] -= kModulo; } } } return c; } class Tree { public: explicit Tree(const vector<int>& a) : a_(a), a_inv_(Inverse(a)), phi_(ComputePhi(a.size())), divisors_(ComputeDivisors(a.size())), coef_(ComputeCoefs(phi_)), edges_(a.size()) {} void AddEdge(const int from, const int to) { edges_[from].push_back({from, to}); edges_[to].push_back({to, from}); } int Build() { const int n = edges_.size(); layer_.assign(n, n); centroid_parent_.assign(n, -1); subtree_size_.assign(n, -1); Build(0, -1, 0); int max_layer = 0; for (int node = 0; node < n; ++node) { max_layer = max(max_layer, layer_[node]); } for (int layer = 0; layer <= max_layer; ++layer) { root_.assign(n, -1); root_child_.assign(n, -1); root_depth_.assign(n, -1); subtree_.assign(n, 0); for (int node = 0; node < n; ++node) { if (layer_[node] == layer) { ComputeRootAndRootChild(node, -1, layer, node, -1, 0); } } for (int g = 1; g <= n; ++g) { for (int i = g; i <= n; i += g) { const int node = a_inv_[i - 1]; const int64 value = (coef_[g] * phi_[i]) % kModulo; if (root_[node] != -1) { subtree_[root_[node]] += value; } if (root_child_[node] != -1) { subtree_[root_child_[node]] += value; } } for (int i = g; i <= n; i += g) { const int u = a_inv_[i - 1]; const int root = root_[u]; if (root == -1) { continue; } const int root_child = root_child_[u]; int64 cur_answer = subtree_[root]; if (root_child != -1) { cur_answer -= subtree_[root_child]; } cur_answer %= kModulo; cur_answer = (cur_answer * 2 * phi_[a_[u]]) % kModulo; cur_answer = (cur_answer * root_depth_[u]) % kModulo; answer_ = answer_ + cur_answer; if (answer_ < 0) { answer_ = answer_ + kModulo; } if (answer_ >= kModulo) { answer_ = answer_ - kModulo; } } for (int i = g; i <= n; i += g) { const int node = a_inv_[i - 1]; if (root_[node] != -1) { subtree_[root_[node]] = 0; } if (root_child_[node] != -1) { subtree_[root_child_[node]] = 0; } } } } answer_ = (answer_ * ModInverse(n)) % kModulo; answer_ = (answer_ * ModInverse(n - 1)) % kModulo; return answer_; } private: void Build(const int node, const int parent, const int layer) { const int centroid = FindCentroid(node, layer); layer_[centroid] = layer; centroid_parent_[centroid] = parent; for (const Edge& edge : edges_[centroid]) { const int child = edge.to; if (layer_[child] >= layer) { Build(child, centroid, layer + 1); } } } int FindCentroid(const int node, const int layer) { const int max_size = ComputeSubtreeSize(node, -1, layer) / 2; int parent = -1; int centroid = node; while (true) { bool found = false; for (const Edge& edge : edges_[centroid]) { const int child = edge.to; if (layer_[child] < layer || child == parent) { continue; } if (subtree_size_[child] > max_size) { parent = centroid; centroid = child; found = true; break; } } if (!found) { return centroid; } } } int ComputeSubtreeSize(const int node, const int parent, const int layer) { int size = 1; for (const Edge& edge : edges_[node]) { const int child = edge.to; if (layer_[child] < layer || child == parent) { continue; } size += ComputeSubtreeSize(child, node, layer); } subtree_size_[node] = size; return size; } void ComputeRootAndRootChild(const int node, const int parent, const int layer, const int root, const int root_child, const int depth) { root_[node] = root; root_child_[node] = root_child; root_depth_[node] = depth; for (const Edge& edge : edges_[node]) { const int child = edge.to; if (layer_[child] < layer || child == parent) { continue; } ComputeRootAndRootChild(child, node, layer, root, root_child != -1 ? root_child : child, depth + 1); } } const vector<int> a_; const vector<int> a_inv_; const vector<int> phi_; const vector<vector<int>> divisors_; const vector<int64> coef_; vector<vector<Edge>> edges_; vector<int> layer_; vector<int> centroid_parent_; vector<int> subtree_size_; vector<int> root_; vector<int> root_child_; vector<int> root_depth_; vector<int64> subtree_; int answer_ = 0; }; namespace io { char* position_; char* buffer_limit_; bool FetchChunk() { static char buffer_[1024]; const auto count = fread(buffer_, sizeof(char), 1024, stdin); if (count > 0) { buffer_limit_ = buffer_ + count; } else { buffer_[0] = 0 ; buffer_limit_ = buffer_ + 1; } position_ = buffer_; return count > 0; } const bool unused_ = FetchChunk(); template <typename T> T Read() { while ( 0 <= *position_ && *position_ <= ) { if (++position_ == buffer_limit_) { FetchChunk(); }; } const bool negate = (*position_ == - ); if (negate) { if (++position_ == buffer_limit_) { FetchChunk(); }; } T result = 0; while ( 0 <= *position_ && *position_ <= 9 ) { result = 10 * result + (*position_ - 0 ); if (++position_ == buffer_limit_) { FetchChunk(); }; } return negate ? -result : result; } } // namespace io int main() { const int n = io::Read<int>(); vector<int> a(n); for (int i = 0; i < n; ++i) { a[i] = io::Read<int>(); } Tree t(a); for (int i = 0; i < n - 1; ++i) { const int u = io::Read<int>() - 1; const int v = io::Read<int>() - 1; t.AddEdge(u, v); } cout << t.Build() << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_MS__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; #define Input(v, n) fr(i, n) cin >> v[i]; #define checkk(v, n) fr(i, n) cout << v[i] << << endl; #define sort(v) sort(v.begin(), v.end()); #define int long long int #define double long double #define fr(i, n) for (int i = 0; i < n; i++) #define frr(i, s, e) for (int i = s; i <= e; i++) #define rfr(i, s, e) for (int i = s; i >= e; i--) #define fix(f,n) fixed<<setprecision(n)<<f #define endl n #define pb push_back #define mp make_pair #define mod 1000000007 int test; double v,ans; void add(double &c,double &m,double &p,int i,double t){ if(i==0){ if(m==0) p+=t; else { t=t/2.0; m+=t,p+=t; } } else{ if(c==0) p+=t; else { t=t/2.0; c+=t,p+=t; } } } void calc(double c,double m,double p,double val,double count){ if(c<0.000001) c=0; if(m<0.000001) m=0; double t1=c,t2=m,t3=p; ans+=(count*(val*p)); if(c!=0){ double nan=val*c; if(c<=v) add(c,m,p,0,c),c=0,calc(c,m,p,nan,count+1.0); else add(c,m,p,0,v),c=c-v,calc(c,m,p,nan,count+1.0); } c=t1,m=t2,p=t3; if(m!=0){ double nan=val*m; if(m<=v) add(c,m,p,1,m),m=0,calc(c,m,p,nan,count+1.0); else add(c,m,p,1,v),m=m-v,calc(c,m,p,nan,count+1.0); } } void solve() { ans=0.0; double c,m,p; cin>>c>>m>>p>>v; calc(c,m,p,1.0,1.0); cout<<fix(ans,12)<<endl; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cin>>test; //test=1; while (test--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k, x; long long inp[200005]; long long precom[64][2]; long long num; long long ans; int main() { cin >> n >> k >> x; long long i, j, kl; for (i = 0; i < n; ++i) { scanf( %lld , &inp[i]); for (j = 0; j < 63; ++j) { if (((long long)1 << j) & inp[i]) precom[j][0]++; } } long long pos = 0; long long ans, tmpans; ans = 0; for (j = 0; j < n; ++j) { num = inp[j]; for (i = 0; i < k; ++i) { num *= x; } for (kl = 0; kl < 64; ++kl) { precom[kl][1] = 0; if ((num & ((long long)1 << kl)) && !(inp[j] & ((long long)1 << kl))) { precom[kl][1] = 1; } if (!(num & ((long long)1 << kl)) && (inp[j] & ((long long)1 << kl))) precom[kl][1] = -1; } tmpans = 0; for (kl = 0; kl < 64; ++kl) { if (precom[kl][0] + precom[kl][1]) tmpans += ((long long)1 << kl); } if (tmpans > ans) { ans = tmpans; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; char s[92], sl[10][10], str[10]; bool cmp(char* a, char* b) { for (int i = 0; i < 10; i++) if (a[i] != b[i]) return false; return true; } int main() { scanf( %s , &s); for (int i = 0; i < 10; i++) scanf( %s , sl[i]); for (int i = 0; i < 80; i += 10) { for (int k = 0; k < 10; k++) str[k] = s[i + k]; for (int i = 0; i < 10; i++) if (cmp(str, sl[i])) { printf( %d , i); break; } } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_int.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
module testcase;
// Testcase INDEPENDENT code - common to all testcases
//#####################################################
// Variables
// Testbench reporting events & signals
event severe_err_event;
event err_event;
event wrn_event;
event msg_event;
event val_event;
event testbench_log_written;
reg [7999: 0] tim;
reg [7999: 0] severe_err_msg;
reg [7999: 0] msg;
integer val;
// Testcase reporting events & signals
event testcase_log_written;
event test_end;
reg [1599: 0] test_name;
reg error_detected;
// Module for writing to log files
uart_log log ();
defparam log.testcase_name = "uart_interrupts";
// Log
initial
fork
begin: init_log
reg ok;
// Delay allows all other blocks in this fork - join block to execute
#1;
log.start_log(ok);
if (ok !== 1'b1)
begin
`SEVERE_ERROR("Failed to open log file(s)!");
disable init_log;
end
testcase_init;
testcase_test;
log.end_log;
# 100;
$finish;
end
begin
forever
begin
@(test_name);
error_detected = 1'b0;
log.report_test_name(test_name);
log.verbose_test_name(test_name);
-> testcase_log_written;
end
end
begin
forever
begin
@(test_end);
if (error_detected)
begin
log.tests_failed = log.tests_failed + 1'b1;
end
else
begin
log.tests_ok = log.tests_ok + 1'b1;
log.report_test_ok;
end
-> testcase_log_written;
end
end
begin
@(severe_err_event);
error_detected = 1'b1;
-> test_end;
@(testcase_log_written);
log.report_test_failed(severe_err_msg);
if (testcase.log.free == 0)
begin
wait (testcase.log.free);
severe_err_msg = "Failed to write to log file(s)!";
end
log.verbose_severe_err(tim, severe_err_msg);
-> testbench_log_written;
# 100; $finish;
end
begin
forever
begin
@(err_event);
error_detected = 1'b1;
-> test_end;
@(testcase_log_written);
log.report_test_failed(msg);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_err(tim, msg);
-> testbench_log_written;
`PROMPT;
end
end
begin
forever
begin
@(wrn_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_wrn(tim, msg);
-> testbench_log_written;
end
end
begin
forever
begin
@(msg_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_msg(tim, msg);
-> testbench_log_written;
end
end
begin
forever
begin
@(val_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_val(tim, msg, val);
-> testbench_log_written;
end
end
join
// Testcase (DEPENDENT) code
//###########################
// Initialization
task testcase_init;
begin:init
test_name = "Initialization of UART.";
@(testcase_log_written);
//
testbench_utilities.do_reset;
testbench_utilities.disable_clk_generators(1, 1, 1, 1);
testbench_utilities.set_device_tx_rx_clk_divisor(32'h1000);
testbench_utilities.set_wb_clock_period(100);
testbench_utilities.enable_clk_generators(1, 1, 1, 1);
#100;
testbench_utilities.release_reset;
//
uart_wb_utilities.write_dlr(16'h1000);
uart_wb_utilities.write_ier(8'h07);
uart_wb_utilities.write_fcr(8'hC0);
uart_wb_utilities.write_lcr(8'h03);
//
uart_device_utilities.set_rx_length(8);
uart_device_utilities.disable_rx_parity;
uart_device_utilities.set_rx_second_stop_bit(0);
//
uart_device_utilities.set_tx_length(8);
uart_device_utilities.disable_tx_parity;
uart_device_utilities.correct_tx_parity;
uart_device_utilities.correct_tx_frame;
uart_device_utilities.generate_tx_glitch(0);
-> test_end;
@(testcase_log_written);
end
endtask // testcase_init
// Testcase
task testcase_test;
begin:test
test_name = "Interrupt test.";
@(testcase_log_written);
fork
begin: test
uart_wb_utilities.write_char(8'hAA);
@(testbench.int_aserted);
`TC_MSG("INT ASSERTED!");
uart_wb_utilities.write_char(8'hAA);
@(testbench.int_released);
`TC_MSG("INT RELEASED!");
@(testbench.int_aserted);
`TC_MSG("INT ASSERTED!");
uart_wb_utilities.read_iir;
@(testbench.int_released);
`TC_MSG("INT RELEASED!");
end
begin: wait_end
@(testbench.i_uart_device.device_received_packet);
@(testbench.i_uart_device.device_received_packet);
repeat(2) @(testbench.i_uart_device.rx_clk);
disable test;
disable wait_clk;
end
begin: wait_clk
testbench_utilities.wait_for_num_of_wb_clk(32'h450000);
disable test;
disable wait_end;
end
join
repeat (4) @(posedge testbench.wb_clk);
# 100;
-> test_end;
@(testcase_log_written);
end
endtask // testcase_test
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long x, y, a, b; cin >> x >> y >> a >> b; if (2 * a < b) { cout << a * (x + y) << n ; ; return; } else { cout << b * min(x, y) + a * abs(x - y) << n ; ; } } int main() { int t; cin >> t; for (int i = 0; i < t; i++) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { string n; cin >> n; if (n[0] != - ) { cout << n; } else { char max = 0 ; int mem; for (int i = n.length() - 2; i < n.length(); ++i) { if (n[i] >= max) { max = n[i]; mem = i; } } string merge = n.substr(0, mem) + n.substr(mem + 1, n.length()); int result = atoi(merge.c_str()); cout << result; } return 0; } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state = 1'b0;
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (qualifier & fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
prev_test_expr <= {width{1'b0}};
end
else begin
if (qualifier) begin
prev_test_expr <= test_expr;
end
end
end
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("qualifier covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (qualifier == 1'b1));
assign fire_cover_2 = ((OVL_COVER_SANITY_ON > 0) && (qualifier == 1'b1) && (test_expr != prev_test_expr));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Edge_Detection_Router_Controller (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[1000005]; char l[1000005]; char r[1000005]; int f[1000005]; int okl[1000005]; int okr[1000005]; int mod = 998244353; char ss[2000005]; int heigh[2000005]; int sa[2000005]; int Rank[2000005]; int length; int val[30]; int c[2000005]; int temp[2][2000005]; void suffix_array() { int A = 250; int* Rank = temp[0]; int* new_rank = temp[1]; for (int i = 0; i < A; ++i) c[i] = 0; for (int i = 0; i < length; ++i) c[Rank[i] = ss[i]]++; for (int i = 1; i < A; ++i) c[i] += c[i - 1]; for (int i = length - 1; i >= 0; --i) sa[--c[ss[i]]] = i; for (int n = 1; n < length; n *= 2) { for (int i = 0; i < A; ++i) c[i] = 0; for (int i = 0; i < length; ++i) c[Rank[i]]++; for (int i = 1; i < A; ++i) c[i] += c[i - 1]; int* sa2 = new_rank; int r = 0; for (int i = length - n; i < length; ++i) sa2[r++] = i; for (int i = 0; i < length; ++i) if (sa[i] >= n) sa2[r++] = sa[i] - n; for (int i = length - 1; i >= 0; --i) sa[--c[Rank[sa2[i]]]] = sa2[i]; new_rank[sa[0]] = r = 0; for (int i = 1; i < length; ++i) { if (!(Rank[sa[i - 1]] == Rank[sa[i]] && sa[i - 1] + n < length && Rank[sa[i - 1] + n] == Rank[sa[i] + n])) r++; new_rank[sa[i]] = r; } swap(Rank, new_rank); if (r == length - 1) break; A = r + 1; } } void lcp_array() { for (int i = 0; i < length; ++i) Rank[sa[i]] = i; for (int i = 0, lcp = 0, h = 0; i < length; i++) if (Rank[i] == 0) heigh[0] = 0; else { int j = sa[Rank[i] - 1]; if (lcp > 0) lcp--; while (ss[i + lcp] == ss[j + lcp]) lcp++; heigh[Rank[i]] = lcp; } } int dp[1000005]; int okzero; int main() { scanf( %s , a); scanf( %s , l); if (l[0] == 0 && l[1] == 0) l[0] = 1 , okzero = 1; scanf( %s , r); int lena = strlen(a), lenl = strlen(l), lenr = strlen(r); for (int i = 0; a[i] != 0; i++) ss[i] = a[i]; ss[lena] = $ ; for (int i = 0; l[i] != 0; i++) ss[i + lena + 1] = l[i]; length = lena + lenl + 1; ss[length] = 0; suffix_array(); int st = 0; for (int i = 0; i < length; i++) { if (sa[i] == lena + 1) st = i; } lcp_array(); int now = 1e9; for (int i = st + 1; i < length; i++) { now = min(now, heigh[i]); if (sa[i] < lena) { if (a[sa[i] + now] < l[now]) { okl[sa[i]] = 0; } else { okl[sa[i]] = 1; } } } now = 1e9; for (int i = st - 1; i >= 0; i--) { now = min(heigh[i + 1], now); if (sa[i] < lena) { if (a[sa[i] + now] < l[now]) { okl[sa[i]] = 0; } else { okl[sa[i]] = 1; } } } for (int i = 0; r[i] != 0; i++) ss[i + lena + 1] = r[i]; length = lena + lenr + 1; ss[length] = 0; suffix_array(); st = 0; for (int i = 0; i < length; i++) { if (sa[i] == lena + 1) st = i; } lcp_array(); now = 1e9; for (int i = st + 1; i < length; i++) { now = min(now, heigh[i]); if (sa[i] < lena) { if (a[sa[i] + now] <= r[now] || r[now] == 0) { okr[sa[i]] = 1; } else { okr[sa[i]] = 0; } } } now = 1e9; for (int i = st - 1; i >= 0; i--) { now = min(heigh[i + 1], now); if (sa[i] < lena) { if (a[sa[i] + now] <= r[now] || r[now] == 0) { okr[sa[i]] = 1; } else { okr[sa[i]] = 0; } } } int l = 0, r = -1; long long sum = 0; if (lenl == 1) { if (okl[r + 1]) { if (a[r + 1] != 0 ) sum += 1; r++; } } for (int i = 0; a[i] != 0; i++) { dp[i] = sum; if (a[i] == 0 && okzero) { if (i == 0) dp[i]++; else dp[i] += dp[i - 1]; dp[i] %= mod; } while (1) { if (i - r + 1 > lenl) { if (a[r + 1] != 0 ) { if (r == -1) sum++; else sum += dp[r]; } r++; } else if (i - r + 1 == lenl) { if (okl[r + 1]) { if (a[r + 1] != 0 ) { if (r == -1) sum++; else sum += dp[r]; } r++; } else { break; } } else { break; } } while (1) { if (i - l + 2 > lenr) { if (a[l] != 0 ) { if (l == 0) sum--; else sum -= dp[l - 1]; } l++; } else if (i - l + 2 == lenr) { if (!okr[l]) { if (a[l] != 0 ) { if (l == 0) sum--; else sum -= dp[l - 1]; } l++; } else { break; } } else { break; } } sum = (sum % mod + mod) % mod; } printf( %d n , dp[lena - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) int main(int argc, char **argv) { ifstream from; const int nmin = 2, nmax = 300, kmin = 1, kmax = 300; int n, rt, rt1, rt2, i, j, j0, j1, k; int err = 0; char ch; cin >> n; vector<vector<int>> d(n); for (i = 0; i < n; i++) d[i].resize(n); for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { cin >> d[i][j]; } } cin >> k; vector<int> a(k); vector<int> b(k); vector<int> c(k); for (i = 0; i < k; i++) { cin >> a[i] >> b[i] >> c[i]; a[i]--; b[i]--; } vector<long long> q(k); for (i = 0; i < k; i++) { if (d[a[i]][b[i]] > c[i]) { d[a[i]][b[i]] = c[i]; d[b[i]][a[i]] = c[i]; } q[i] = 0; for (j0 = 0; j0 < n - 1; j0++) { for (j1 = j0 + 1; j1 < n; j1++) { rt1 = d[j0][a[i]] + d[a[i]][b[i]] + d[b[i]][j1]; rt2 = d[j0][b[i]] + d[a[i]][b[i]] + d[a[i]][j1]; rt = (rt1 < rt2) ? rt1 : rt2; if (rt < d[j0][j1]) { d[j0][j1] = rt; d[j1][j0] = rt; } q[i] += d[j0][j1]; } } } for (i = 0; i < k - 1; i++) { cout << q[i] << ; } cout << q[k - 1] << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_MS__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 500; const int dr[] = {0, 1, 0, -1}; const int dc[] = {1, 0, -1, 0}; bool vis[MAXN + 5][MAXN + 5]; char grid[MAXN + 5][MAXN + 5]; int W, H; vector<pair<char, pair<int, int> > > ans; inline void put(char ch, int i, int j) { ans.push_back(make_pair(ch, make_pair(i, j))); } void buildRed(int i, int j) { if (i < 0 || j < 0 || i >= H || j >= W) return; if (grid[i][j] == # ) return; if (vis[i][j]) return; vis[i][j] = true; for (int dir = 0; dir < 4; dir++) buildRed(i + dr[dir], j + dc[dir]); put( D , i + 1, j + 1); put( R , i + 1, j + 1); return; } int main() { int c, c2; scanf( %d%d , &H, &W); for (c = 0; c < H; c++) scanf( %s , grid[c]); for (c = 0; c < H; c++) for (c2 = 0; c2 < W; c2++) if (grid[c][c2] == . ) put( B , c + 1, c2 + 1); for (c = 0; c < H; c++) for (c2 = 0; c2 < W; c2++) if (!vis[c][c2] && grid[c][c2] == . ) { vis[c][c2] = true; for (int dir = 0; dir < 4; dir++) buildRed(c + dr[dir], c2 + dc[dir]); } printf( %d n , ans.size()); for (c = 0; c < ans.size(); c++) printf( %c %d %d n , ans[c].first, ans[c].second.first, ans[c].second.second); return 0; } |
#include <bits/stdc++.h> using namespace std; char a[100001]; int n, f = 1, x, ans; int main() { cin >> a; n = strlen(a); for (int i = 0; i < n; i++) { if (a[i] < 0 || a[i] > 9 ) { ans += x * f; x = 0; if (a[i] == - ) f = -1; if (a[i] == + ) f = 1; x = x * 10 + a[i] - 0 ; } if (a[i] >= 0 && a[i] <= 9 ) { x *= 10; x += a[i] - 0 ; } } ans += x * f; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1000000 + 20; int pos[MAX_N], mark[MAX_N]; int inter[MAX_N]; set<int> D; long long ans; int n, k; void add(int x) { for (; x <= n; x += x & (-x)) ++inter[x]; } int get(int x) { if (x < 1) return 0; int res = 0; for (; x > 0; x -= x & (-x)) res += inter[x]; return res; } int main() { ios::sync_with_stdio(false); cin >> n >> k; for (int i = 0; i < n; i++) { int x; cin >> x; pos[x] = i + 1; } for (int i = 0; i < k; ++i) { int x; cin >> x; mark[x] = 1; } D.insert(0); D.insert(n + 1); for (int i = 1; i <= n; ++i) { if (mark[i]) D.insert(pos[i]); else { int l, r; set<int>::iterator it = D.lower_bound(pos[i]); r = *it - 1; --it; l = *it + 1; ans += r - l + 1 - get(r) + get(l - 1); add(pos[i]); } } cout << ans << endl; return 0; } |
// file: design_1_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000______50.0______233.189____265.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
module design_1_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_design_1_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_0_0;
wire clkfbout_buf_design_1_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT (32),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (8.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
.I (clkfbout_design_1_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_0_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; class Point { public: int x; int y; Point(int x = 0, int y = 0) : x(x), y(y) {} friend Point operator-(Point a, Point b) { return Point(b.x - a.x, b.y - a.y); } }; int getBit(int mask, int num) { return ((mask & (1 << num)) ? 1 : 0); } int innerProduct(Point a, Point b) { return a.x * b.x + a.y * b.y; } int sqr(int x) { return x * x; } int squareDist(Point a, Point b) { return sqr(a.x - b.x) + sqr(b.y - a.y); } bool checkEdges(vector<Point> figure) { figure.push_back(figure.front()); figure.push_back(*(figure.begin() + 1)); for (int i = 0; i + 2 < figure.size(); ++i) if (innerProduct(figure[i + 1] - figure[i], figure[i + 2] - figure[i + 1]) != 0) return false; return true; } bool checkEdgesEquality(vector<Point> figure) { figure.push_back(figure.front()); for (int i = 0; i + 2 < figure.size(); ++i) if (squareDist(figure[i], figure[i + 1]) != squareDist(figure[i + 1], figure[i + 2])) return false; return true; } bool checkRectangleEdges(vector<Point> figure) { figure.push_back(figure.front()); if (squareDist(figure[0], figure[1]) == squareDist(figure[2], figure[3]) && squareDist(figure[1], figure[2]) == squareDist(figure[3], figure[4])) return true; else return false; } bool checkSquare(vector<Point> square) { vector<int> sm; sm.push_back(0); sm.push_back(1); sm.push_back(2); sm.push_back(3); do { vector<Point> sq; for (int i = 0; i < 4; ++i) sq.push_back(square[sm[i]]); if (checkEdges(sq) && checkEdgesEquality(sq)) return true; } while (next_permutation(sm.begin(), sm.end())); return false; } bool checkRectangle(vector<Point> rectangle) { vector<int> sm; sm.push_back(0); sm.push_back(1); sm.push_back(2); sm.push_back(3); do { vector<Point> sq; for (int i = 0; i < 4; ++i) sq.push_back(rectangle[sm[i]]); if (checkEdges(sq) && checkRectangleEdges(sq)) return true; } while (next_permutation(sm.begin(), sm.end())); return false; } bool check(vector<Point> square, vector<Point> rectangle) { if (checkSquare(square) && checkRectangle(rectangle)) return true; return false; } int main() { vector<Point> v; int a, b; for (int i = 0; i < 8; ++i) { cin >> a >> b; v.push_back(Point(a, b)); } int i = 0; while (i < 1 << 8) { vector<Point> square, rectangle; vector<int> resSquare, resRectangle; for (int j = 0; j < 8; ++j) { if (getBit(i, j)) square.push_back(v[j]); else rectangle.push_back(v[j]); } if (square.size() == 4 && rectangle.size() == 4 && check(square, rectangle)) { for (int j = 0; j < 8; ++j) { if (getBit(i, j)) resSquare.push_back(j); else resRectangle.push_back(j); } cout << YES << endl; for (int j = 0; j < 4; ++j) cout << resSquare[j] + 1 << ; cout << endl; for (int j = 0; j < 4; ++j) cout << resRectangle[j] + 1 << ; return 0; } ++i; } cout << NO ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_PP_SYMBOL_V
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_router.v
//
// Description:
// Contains SI-side write command queue.
// Target MI-slot index is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input is transferred to MI-slot output selected by queue output.
//--------------------------------------------------------------------------
//
// Structure:
// wdata_router
// axic_reg_srl_fifo
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_9_wdata_router #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_MASTER_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_data_fifo_v2_1_7_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
)
wrouter_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int n, b; cin >> n >> b; int a[n], maxx = b; for (int x = 0; x < n; x++) cin >> a[x]; for (int x = 0; x < n; x++) { for (int y = x + 1; y < n; y++) maxx = max(maxx, (b / a[x]) * a[y] + (b % a[x])); } cout << maxx; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
$write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out32, out10,
// Inputs
in
);
input [1:0] in;
output [1:0] out32;
output [1:0] out10;
assign out32 = in[3:2];
assign out10 = in[1:0];
endmodule
|
//AUTHOR: Tariq Bashir
//
//for unambiguous codes (lcbbc)
//released into the public under GPL
`timescale 1ns/1ps
module lcbbc
#(parameter N = 3,
parameter depth=1024,
parameter width=N, //same as N
parameter addr_sz=$clog2(depth)
)
(input clk,
input rst, //positive reset
input [N-1:0] n,
input [N/2-1:0] min_hd,
input start,
output reg [N-1:0] codes
);
localparam [2:0]
IDLE = 0,
CALC_HD = 1,
CLOCK_CALC_HD = 2,
FIND_CODE = 3,
RD_MEM = 4,
OUTPUT_CODES = 5,
CLOCK_OUTPUT_CODES = 6,
DONE = 7;
reg [2:0] state, nxt_state;
reg [N-1:0] counterl, nxt_counterl, counterh, nxt_counterh;
reg [addr_sz-1:0] codelength, nxt_codelength;
reg [addr_sz-1:0] count, nxt_count;
//sequential block
always @(posedge clk)
if(rst)
begin
state <= #1 IDLE;
counterl <= #1 0;
codelength <= #1 0;
count <= #1 0;
counterh <= #1 0;
end
else
begin
state <= #1 nxt_state;
counterl <= #1 nxt_counterl;
counterh <= #1 nxt_counterh;
codelength <= #1 nxt_codelength;
count <= #1 nxt_count;
end
reg [N-1:0] summation;
reg [N-1:0] candidate;
reg wr_en, rd_en;
reg [width-1:0] d_in;
reg [addr_sz-1:0] wr_addr;
reg [width-1:0] d_out;
reg [addr_sz-1:0] rd_addr, r_addr;
reg [width-1:0] code_array[0:depth-1];
//memory
always @(posedge clk)
begin
if (wr_en)
begin
code_array[wr_addr] <= #1 d_in;
end
else if (rd_en)
begin
d_out <= #1 code_array[rd_addr];
end
end // always @ (posedge clk)
//Finite STATE MACHINE
always@*
begin
//defaults
nxt_state = state;
nxt_counterl = counterl;
nxt_counterh = counterh;
nxt_count = count;
nxt_codelength = codelength;
case(state)
IDLE:
begin
if(start)
begin
wr_addr = 0;
wr_en = 1;
d_in = 0;
nxt_codelength = 1;
nxt_state = CALC_HD;
end
end
CALC_HD:
begin
wr_en = 0;
if( (counterh == 1 ) || (codelength == depth -1) )
nxt_state = OUTPUT_CODES;
else
begin
if(counterl == 2**N-1)
nxt_counterh = counterh + 1;
summation = sum(counterl ^ counterh); //function call
if( summation >= min_hd )
begin
//HD[counterl] = counterl;
candidate = counterl;
nxt_counterl = counterl + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_counterl = counterl + 1;
nxt_state = CLOCK_CALC_HD;
end
end // else: !if( (counterh == 1 ) || (codelength == depth -1) )
end // case: CALC_HD
CLOCK_CALC_HD:
begin
nxt_state = CALC_HD;
end
FIND_CODE:
begin
if(count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_state = RD_MEM;
end
else if(count == codelength)
begin
wr_en = 1;
d_in = candidate;
wr_addr = codelength;
nxt_codelength = codelength + 1;
nxt_count = 0;
nxt_state = CALC_HD;
end
end //FIND_CODE
RD_MEM:
begin
rd_en = 0;
summation = sum(d_out ^ candidate);
if (summation >= min_hd)
begin
nxt_count = count + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_count = 0;
nxt_state = CALC_HD;
end
end
OUTPUT_CODES:
begin
if( count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_count = count + 1;
nxt_state = CLOCK_OUTPUT_CODES;
end
else
nxt_state = DONE;
end // case: OUTPUT_CODE
CLOCK_OUTPUT_CODES:
begin
rd_en = 0;
codes = d_out;
nxt_state = OUTPUT_CODES;
end
DONE:
begin
$display($time,": Done \n");
$finish;
end
endcase // case (state)
end // always@ *
function [N-1:0] sum(input [N-1:0] input_vector);
integer k;
reg [N-1:0] temp;
begin
temp = 0;
for(k=0; k < N; k=k+1)
begin
temp = temp + input_vector[k];
end
sum = temp;
end
endfunction // sum
endmodule // lcbbc
|
module encoder ( b, c );
input [5:0] b;
output [18:0] c;
wire c_15_, c_6_, c_5_, c_4_, c_3_, c_2_, c_1_, c_0_, n20, n21, n22, n23;
assign c[11] = c_15_;
assign c[15] = c_15_;
assign c[13] = c_6_;
assign c[6] = c_6_;
assign c[5] = c_5_;
assign c_5_ = b[5];
assign c[4] = c_4_;
assign c_4_ = b[4];
assign c[3] = c_3_;
assign c_3_ = b[3];
assign c[2] = c_2_;
assign c_2_ = b[2];
assign c[1] = c_1_;
assign c_1_ = b[1];
assign c[0] = c_0_;
assign c_0_ = b[0];
XOR2X1 U23 ( .A(c_4_), .B(c[14]), .Y(c[9]) );
XOR2X1 U24 ( .A(c_5_), .B(n20), .Y(c[8]) );
XOR2X1 U25 ( .A(c_5_), .B(c_4_), .Y(c[7]) );
XOR2X1 U26 ( .A(n21), .B(n22), .Y(c_6_) );
XOR2X1 U27 ( .A(c_1_), .B(n20), .Y(c[18]) );
XOR2X1 U28 ( .A(c_2_), .B(c_3_), .Y(n20) );
XOR2X1 U29 ( .A(n22), .B(n23), .Y(c[17]) );
XOR2X1 U30 ( .A(c_5_), .B(c_2_), .Y(n23) );
XOR2X1 U31 ( .A(c_4_), .B(c_2_), .Y(c_15_) );
XOR2X1 U32 ( .A(c_0_), .B(c_3_), .Y(c[14]) );
XOR2X1 U33 ( .A(c_1_), .B(n21), .Y(c[12]) );
XOR2X1 U34 ( .A(c_0_), .B(c_5_), .Y(n21) );
XOR2X1 U35 ( .A(c_5_), .B(c[16]), .Y(c[10]) );
XOR2X1 U36 ( .A(c_3_), .B(n22), .Y(c[16]) );
XOR2X1 U37 ( .A(c_1_), .B(c_4_), .Y(n22) );
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: io_cell.v
//
// *Module Description:
// I/O cell model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module io_cell (
// INOUTs
pad, // I/O Pad
// OUTPUTs
data_in, // Input value
// INPUTs
data_out_en, // Output enable
data_out // Output value
);
// INOUTs
//=========
inout pad; // I/O Pad
// OUTPUTs
//=========
output data_in; // Input value
// INPUTs
//=========
input data_out_en; // Output enable
input data_out; // Output value
//=============================================================================
// 1) I/O CELL
//=============================================================================
assign data_in = pad;
assign pad = data_out_en ? data_out : 1'bz;
endmodule // io_cell
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; vector<long long> num; long long gcd(long long x, long long y) { if (y > x) return gcd(y, x); return x % y ? gcd(y, x % y) : y; } int a[3]; vector<vector<int> > grid; vector<vector<int> > dist; void bfs(int x, vector<bool>& vis) { int n = vis.size(); queue<int> q; q.push(a[x]); vis[a[x]] = 1; dist[a[x]][x] = 0; int step = 1; while (q.size()) { int t = q.size(); while (t--) { int tmp = q.front(); q.pop(); for (int i = 0; i < grid[tmp].size(); i++) { int next = grid[tmp][i]; if (!vis[next]) { dist[next][x] = step; vis[next] = 1; q.push(next); } } } step++; } return; } long long shu[63]; int find(long long x) { for (int i = 0; i < 63; i++) { if (shu[i] >= x) return i; } return 63; } long long zhuan(string s) { int n = s.size(); long long ans = 0; for (int i = 0; i < n; i++) { ans = ans * 2 + (long long)(s[i] - 0 ); } return ans; } int main() { int n; cin >> n; while (n--) { long long t; cin >> t; t--; long long pos = t % 3; t = t / 3; long long sum = 1; int cnt = 1; while (sum <= t) { t -= sum; sum *= 4; cnt += 2; } string ans = ; if (pos == 0) ans += 1 ; else { if (pos == 1) ans += 10 ; else ans += 11 ; } string str[12] = { 00 , 01 , 10 , 11 , 00 , 10 , 11 , 01 , 00 , 11 , 01 , 10 }; while (ans.size() < cnt) { ans.insert((pos == 0 ? 1 : 2), str[pos * 4 + t % 4]); t /= 4; } cout << zhuan(ans) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; getline(cin, s1); getline(cin, s2); int yek1 = 0, yek2 = 0; for (int i = 0; i < s1.size(); i++) { if (s1[i] == 1 ) yek1++; } for (int i = 0; i < s2.size(); i++) { if (s2[i] == 1 ) yek2++; } if (yek1 % 2 == 1) yek1++; if (yek1 >= yek2) { cout << YES ; return 0; } cout << NO ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 5; int a[maxn]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } while (m--) { int l, r, x; scanf( %d%d%d , &l, &r, &x); int cnt1 = 0, cnt2 = 0; for (int i = l; i <= r; i++) { if (a[i] < a[x]) cnt1++; if (a[i] == a[x]) cnt2++; } if (cnt1 + l - 1 < x && cnt2 + cnt1 + l - 1 >= x) puts( Yes ); else puts( No ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_PP_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, m; int s[505][505]; int main() { scanf( %d%d , &n, &m); char c = getchar(); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { c = getchar(); if (c == S ) s[i][j] = 0; else if (c == W ) s[i][j] = 1; else s[i][j] = 2; } getchar(); } bool f = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (s[i][j] == 1) { if (i > 1 && s[i - 1][j] == 0) f = 1; if (j > 1 && s[i][j - 1] == 0) f = 1; if (i < n && s[i + 1][j] == 0) f = 1; if (j < m && s[i][j + 1] == 0) f = 1; } } } if (f) { printf( No n ); return 0; } printf( Yes n ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (s[i][j] == 0) { printf( S ); } else if (s[i][j] == 1) printf( W ); else printf( D ); } printf( n ); } return 0; } |
module axi_to_reg_bus
(
input reset,
input clk, //register bus clk
input s_axi_aclk, //axi interface clk
input s_axi_aresetn,
//------------------------------//
//AXI-lite Slave interface
//------------------------------//
// Write address channel
input [31:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_awvalid,
output s_axi_awready,
// Write Data Channel
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wvalid,
output s_axi_wready,
// Write Response Channel
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
// Read Address channel
input [31:0] s_axi_araddr,
input [2:0] s_axi_arprot,
input s_axi_arvalid,
output s_axi_arready,
// Read Data Channel
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready,
//------------------------------//
//Register bus
//------------------------------//
output reg reg_req,
output reg reg_rd_wr_L,
output reg [31:0] reg_addr,
output reg [31:0] reg_wr_data,
input reg_ack,
input [31:0] reg_rd_data
);
//------------------------------//
//AXI-lite Slave interface
//------------------------------//
// Write address channel
wire [31:0] awaddr;
wire [2:0] awprot;
wire awvalid;
reg awready;
// Write Data Channel
wire [31:0] wdata;
wire [3:0] wstrb;
wire wvalid;
reg wready;
// Write Response Channel
reg [1:0] bresp;
reg bvalid;
wire bready;
// Read Address channel
wire [31:0] araddr;
wire [2:0] arprot;
wire arvalid;
reg arready;
// Read Data Channel
reg [31:0] rdata;
reg [1:0] rresp;
reg rvalid;
wire rready;
reg_access_fifo reg_access_fifo (
.m_aclk (clk),
.s_aclk (s_axi_aclk),
.s_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.m_axi_awaddr (awaddr),
.m_axi_awprot (awprot),
.m_axi_awvalid (awvalid),
.m_axi_awready (awready),
.m_axi_wdata (wdata),
.m_axi_wstrb (wstrb),
.m_axi_wvalid (wvalid),
.m_axi_wready (wready),
.m_axi_bresp (bresp),
.m_axi_bvalid (bvalid),
.m_axi_bready (bready),
.m_axi_araddr (araddr),
.m_axi_arprot (arprot),
.m_axi_arvalid (arvalid),
.m_axi_arready (arready),
.m_axi_rdata (rdata),
.m_axi_rresp (rresp),
.m_axi_rvalid (rvalid),
.m_axi_rready (rready)
);
reg reg_req_i;
reg reg_rd_wr_L_i;
reg [31:0] reg_addr_i;
reg [3:0] state;
localparam AXI_IDLE = 4'h0;
localparam AXI_WD = 4'h1;
localparam AXI_B = 4'h2;
localparam AXI_B_RET = 4'h3;
localparam AXI_RD = 4'h4;
localparam AXI_RD_RET = 4'h5;
always @(posedge clk)begin
if (reset) begin
awready <= 1'b0;
wready <= 1'b0;
bvalid <= 1'b0;
bresp <= 2'b00;
arready <= 1'b0;
rvalid <= 1'b0;
rresp <= 2'b00;
rdata <= 32'h0;
reg_req <= 1'b0;
reg_rd_wr_L <= 1'b1;
reg_addr <= 32'b0;
reg_wr_data <= 32'b0;
reg_req_i <= 1'b0;
reg_rd_wr_L_i <= 1'b1;
reg_addr_i <= 32'b0;
state <= AXI_IDLE;
end
else begin
case (state)
AXI_IDLE : begin
awready <= 1'b1;
arready <= 1'b1;
if (awvalid) begin
awready <= 1'b0;
reg_req_i <= 1'b1;
reg_rd_wr_L_i <= 1'b0;
reg_addr_i <= awaddr;
state <= AXI_WD;
wready <= 1'b1;
end
else if (arvalid) begin
arready <= 1'b0;
reg_req <= 1'b1;
reg_rd_wr_L <= 1'b1;
reg_addr <= araddr;
state <= AXI_RD;
end
end
AXI_WD : begin
if (wvalid) begin
reg_req <= reg_req_i;
reg_rd_wr_L <= reg_rd_wr_L_i;
reg_addr <= reg_addr_i;
reg_wr_data <= wdata;
reg_req_i <= 1'b0;
wready <= 1'b0;
state <= AXI_B;
end
end
AXI_B : begin
if(reg_ack) begin
reg_req <= 1'b0; //disable after ack is valid.
bvalid <= 1'b1;
state <=AXI_B_RET;
end
end
AXI_B_RET:begin
if(bready) begin
bvalid <= 1'b0;
state <= AXI_IDLE;
awready <= 1'b1;
arready <= 1'b1;
end
end
AXI_RD : begin
if(reg_ack) begin
reg_req <= 1'b0; //disable after ack is valid.
rvalid <= 1'b1;
rdata <= reg_rd_data;
state <= AXI_RD_RET;
end
end
AXI_RD_RET:begin
if(rready) begin
rvalid <= 1'b0;
rdata <= 32'h0;
state <= AXI_IDLE;
awready <= 1'b1;
arready <= 1'b1;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.precision(10); cout << fixed; int n, neg = 0; cin >> n; vector<int> a(2 * n - 1); bool zero = false; long long sum = 0; for (int i = 0; i < 2 * n - 1; ++i) { cin >> a[i]; if (a[i] == 0) zero = true; else if (a[i] < 0) neg++, a[i] *= -1; sum += a[i]; } neg %= n; if (zero) neg = 0; vector<bool> vis(2 * n); queue<int> q; q.push(neg); vis[neg] = 1; int ans = neg; while (!q.empty()) { int k = q.front(); q.pop(); if (k % n == 0) { ans = 0; break; } ans = min(ans, k); for (int x = 2 * n - 1 - k; x >= n - k; --x) { int k2 = k + 2 * x - n; if (k2 > 0 && k2 < 2 * n && !vis[k2]) { vis[k2] = 1; q.push(k2); } } } sort(begin(a), end(a)); for (int i = 0; i < ans; ++i) sum -= 2 * a[i]; cout << sum << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int vis[200005]; pair<int, int> seg[200005]; vector<pair<int, pair<int, int> > > v; int main() { ios::sync_with_stdio(0); cin.tie(0); long long m, n, i, j, t, x, y, w, k, l, r; cin >> n >> k; for (i = 0; i < n; i++) { cin >> l >> r; v.push_back({l, {i, 1}}); v.push_back({r + 1, {i, -1}}); seg[i].first = l; seg[i].second = r + 1; } sort(v.begin(), v.end()); vector<int> ans; priority_queue<pair<int, int> > pq; int count = 0; for (i = 0; i < v.size();) { x = v[i].first; while (i < v.size() && x == v[i].first) { if (vis[v[i].second.first]) { i++; continue; } if (v[i].second.second == 1) { pq.push({seg[v[i].second.first].second, v[i].second.first}); } count += v[i].second.second; i++; } if (count > k) { int rem = count - k; count = k; while (true) { if (vis[pq.top().second] == 1) { pq.pop(); continue; } rem--; ans.push_back(pq.top().second); vis[pq.top().second] = 1; pq.pop(); if (rem == 0) break; } } } cout << ans.size() << n ; sort(ans.begin(), ans.end()); for (auto x : ans) { cout << x + 1 << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 5; int tree[4 * MAXN], n, m, a[MAXN], size = 0, less1[MAXN]; vector<int> del, nums; void initialize(int l, int r, int node) { tree[node] = r - l + 1; if (r == l) return; int mid = (l + r) / 2; initialize(l, mid, 2 * node); initialize(mid + 1, r, 2 * node + 1); } int elim(int node) { while (node >= 1) { tree[node]--; node /= 2; } } void find(int l, int r, int sum, int node) { if (l == r) { nums[l] = -2; elim(node); return; } int mid = (l + r) / 2; if (tree[2 * node] >= sum) find(l, mid, sum, 2 * node); else find(mid + 1, r, sum - tree[2 * node], 2 * node + 1); } int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < m; ++i) { cin >> a[i]; } for (int i = 0; i < MAXN; ++i) less1[i] = 0; for (int i = 0; i < m - 1; ++i) for (int k = a[i]; k < a[i + 1]; ++k) less1[k] = i + 1; for (int i = a[m - 1]; i < MAXN; ++i) less1[i] = m; for (int i = 0; i < n; ++i) { int x; cin >> x; if (x == -1) { del.push_back(less1[size]); size -= less1[size]; } else { nums.push_back(x); size++; } } if (nums.size() == 0) { cout << Poor stack! << endl; return 0; } initialize(0, nums.size() - 1, 1); for (int i = 0; i < del.size(); ++i) for (int j = del[i] - 1; j >= 0; --j) find(0, nums.size() - 1, a[j], 1); int ct = 0; for (int i = 0; i < nums.size(); ++i) { if (nums[i] != -2) { cout << nums[i]; ++ct; } } if (ct == 0) cout << Poor stack! ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; long long n; long long res, rem; long long narr[100001]; long long tempint; int main() { scanf( %I64d , &n); for (int i = 0; i < n; ++i) scanf( %I64d , narr + i); sort(narr, narr + n); reverse(narr, narr + n); for (int i = 0; i < n; ++i) res += narr[i]; tempint = n - 1; for (int i = 0; i < n; ++i, tempint -= 2) res += 2 * narr[i] * (tempint); long long ores = res, on = n; while (1) { rem = ores % on; if (rem == 0) { break; } ores = on; on = rem; } printf( %I64d %I64d , res / on, n / on); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_SYMBOL_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_SYMBOL_V
|
//-------------------------------------------------------------------
//-- echowire1_tb.v
//-- Banco de pruebas para el eco cableado del puerto serie y las
//-- comprobaciones de las señales DTR y RTS
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
module echowire1_tb();
//-- Declaracion de los cables
reg dtr = 0;
reg rts = 0;
reg rx = 0;
wire tx, led1, led2;
//-- Instanciar el componente
echowire1
dut(
.dtr(dtr),
.rts(rts),
.D1(led1),
.D2(led2),
.tx(tx),
.rx(rx)
);
//-- Generar cambios en dtr. Los mismos deben reflejarse en el cable D1
always
#2 dtr <= ~dtr;
//-- Generar cambios en rts. Se deben reflejar en el cable D2
always
#3 rts = ~rts;
//-- Generar cambios en rs. Se reflejan en TX
always
#1 rx <= ~rx;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("echowire1_tb.vcd");
$dumpvars(0, echowire1_tb);
# 200 $display("FIN de la simulacion");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND4_BEHAVIORAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_BEHAVIORAL_V |
#include<bits/stdc++.h> using namespace std; typedef long long ll; const int maxn=405; const int P=998244353; ll dp[2][maxn][maxn][3][3],sum[maxn][maxn]; int cur,las,n,c[26]; void add(ll &dpp,ll add) { add%=P; while(add<0) add+=P; dpp+=add; while(dpp>=P) dpp-=P; } int main() { scanf( %d ,&n); for(int i=0;i<26;++i) scanf( %d ,&c[i]); dp[0][0][0][0][0]=1; las=1;cur=0; for(int i=1;i<=n;++i) { swap(las,cur); for(int j=0;j<=i;++j) for(int k=0;k<=i;++k) for(int l=0;l<3;++l) for(int m=0;m<3;++m) dp[cur][j][k][l][m]=0; for(int j=0;j<=i;++j) for(int k=0;k<=i;++k) for(int l=0;l<3;++l) for(int m=0;m<3;++m) { if(!dp[las][j][k][l][m])continue; add(dp[cur][j][k][m][0],1LL*dp[las][j][k][l][m]*((l||(i<=2))?24:23)%P); if(l!=1) add(dp[cur][j+1][k][m][1],dp[las][j][k][l][m]); if(l!=2) add(dp[cur][j][k+1][m][2],dp[las][j][k][l][m]); } } for(int i=0;i<=n;++i) for(int j=0;j<=n;++j) for(int k=0;k<3;++k) for(int kk=0;kk<3;++kk) add(sum[i][j],dp[cur][i][j][k][kk]); for(int i=n;i>=0;--i) for(int j=n;j>=0;--j) add(sum[i][j],sum[i+1][j]+sum[i][j+1]-sum[i+1][j+1]); ll res=1; for(int i=1;i<=n;++i) res=res*((i<=2)?26:25)%P; for(int i=0;i<26;++i) add(res,-sum[c[i]+1][0]); for(int i=0;i<26;++i) for(int j=i+1;j<26;++j) add(res,sum[c[i]+1][c[j]+1]); res+=P; res%=P; printf( %lld n ,res); } |
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_buf (
input wire clk_50,
input wire reset_n,
// port for ftl_wbs (external clock) (should be SDHC)
input wire bram_wbs_clk,
input wire [15:0] bram_wbs_addr,
input wire bram_wbs_wren,
input wire [31:0] bram_wbs_data,
output wire [31:0] bram_wbs_q,
// port to ftl_physical
input wire [15:0] bram_physical_addr,
input wire bram_physical_wren,
input wire [31:0] bram_physical_data,
output wire [31:0] bram_physical_q
);
`include "ftl_const.vh"
// 131072 byte bram (2^15=32768 x 32bit word)
ftl_bram_block_dp #(32, 15) ifbram (
.a_clk ( bram_wbs_clk ),
.a_wr ( bram_wbs_wren ),
.a_addr ( bram_wbs_addr ),
.a_din ( bram_wbs_data ),
.a_dout ( bram_wbs_q ),
.b_clk ( clk_50 ),
.b_wr ( bram_physical_wren ),
.b_addr ( bram_physical_addr ),
.b_din ( bram_physical_data ),
.b_dout ( bram_physical_q )
);
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 998244353; int main() { ios_base::sync_with_stdio(false); long long r, s, p; cin >> r >> s >> p; double dp[r + 1][s + 1][p + 1]; int visited[r + 1][s + 1][p + 1]; for (int i = 0; i < r + 1; i++) { for (int j = 0; j < s + 1; j++) { for (int k = 0; k < p + 1; k++) { dp[i][j][k] = 0; visited[i][j][k] = 0; } } } dp[r][s][p] = 1; visited[r][s][p] = 1; queue<pair<pair<double, double>, double> > q; q.push(make_pair(make_pair(r, s), p)); while (!q.empty()) { int sz = q.size(); for (int i = 0; i < sz; i++) { pair<pair<double, double>, double> curp = q.front(); q.pop(); double rr = curp.first.first; double ss = curp.first.second; double rp = curp.second; if ((int)rr > 0 && (int)ss > 0) { dp[(int)rr][(int)ss - 1][(int)rp] += dp[(int)rr][(int)ss][(int)rp] * (((rr * ss)) / ((rr * ss + rp * rr + ss * rp))); if (visited[(int)rr][(int)ss - 1][(int)rp] == 0) { q.push(make_pair(make_pair(rr, ss - 1), rp)); visited[(int)rr][(int)ss - 1][(int)rp] = 1; } } if ((int)rr > 0 && (int)rp > 0) { dp[(int)rr - 1][(int)ss][(int)rp] += dp[(int)rr][(int)ss][(int)rp] * (((rr * rp)) / ((rr * ss + rp * rr + ss * rp))); if (visited[(int)rr - 1][(int)ss][(int)rp] == 0) { q.push(make_pair(make_pair(rr - 1, ss), rp)); visited[(int)rr - 1][(int)ss][(int)rp] = 1; } } if ((int)rp > 0 && (int)ss > 0) { dp[(int)rr][(int)ss][(int)rp - 1] += dp[(int)rr][(int)ss][(int)rp] * (((rp * ss)) / ((rr * ss + rp * rr + ss * rp))); if (visited[(int)rr][(int)ss][(int)rp - 1] == 0) { q.push(make_pair(make_pair(rr, ss), rp - 1)); visited[(int)rr][(int)ss][(int)rp - 1] = 1; } } } } double ans1, ans2, ans3; ans1 = ans2 = ans3 = 0; for (int i = 1; i <= r; i++) { ans1 += dp[i][0][0]; } for (int i = 1; i <= s; i++) { ans2 += dp[0][i][0]; } for (int i = 1; i <= p; i++) { ans3 += dp[0][0][i]; } std::cout << std::setprecision(9) << ans1 << << ans2 << << ans3; return 0; } |
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: mangle_1.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: mangle_1.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
// Test of \escaped identifiers
module a;
wire \a.b ;
m \c.d (\a.b );
initial
begin
\c.d . \y.z <= 1'b1;
#1;
if (\a.b === 1'b1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
module m(x);
output x;
reg \y.z ;
assign x = \y.z ;
endmodule
|
#include <bits/stdc++.h> int main() { std::map<char, long> commands; commands.insert(std::pair<char, long>( > , 8)); commands.insert(std::pair<char, long>( < , 9)); commands.insert(std::pair<char, long>( + , 10)); commands.insert(std::pair<char, long>( - , 11)); commands.insert(std::pair<char, long>( . , 12)); commands.insert(std::pair<char, long>( , , 13)); commands.insert(std::pair<char, long>( [ , 14)); commands.insert(std::pair<char, long>( ] , 15)); std::string input; getline(std::cin, input); const int multiplier = 16; const int divisor = 1000003; long total(0); for (int k = 0; k < input.size(); k++) { total = multiplier * total + commands[input[k]]; total %= divisor; } printf( %ld n , total); return 0; } |
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