text stringlengths 59 71.4k |
|---|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, k; scanf( %d , &t); while (t--) { scanf( %d %d , &n, &k); if (n == k || n == 1 || n == 2) { cout << Alice n ; continue; } if (k % 3) { if (!(n % 3)) { cout << Bob n ; continue; } cout << Alice n ; continue; } if ((n % (k + 1)) % 3 == 0 && n % (k + 1) != k) { cout << Bob n ; continue; } cout << Alice n ; continue; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s, t; cin >> s >> t; int cost = 0; for (int i = 0; i < n;) { if (s[i] != t[i]) { if (i + 1 < n && s[i] != s[i + 1] && s[i + 1] != t[i + 1]) { i += 2; } else { i++; } cost++; } else { i++; } } cout << cost << endl; return 0; } |
`timescale 1ns / 1ps
module AXI_DDR2(
// Common
input CLK, // system clock
input CLK_200MHZ, // 200MHZ
input RST, // active high system reset
// AXI-4 SLAVE Interface
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [4-1:0] axi_wstrb,
output axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [3-1:0] axi_arprot,
output axi_rvalid,
input axi_rready,
output [32-1:0] axi_rdata,
// DDR2 interface
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_p,
inout [1:0] ddr2_dqs_n
);
wire mem_init_calib_complete;
wire mem_ui_clk;
wire axi_wready_int;
wire axi_awready_int;
wire axi_rvalid_int;
wire axi_bvalid_int;
wire axi_arready_int;
assign axi_wready = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_wready_int : 1'b0 );
assign axi_awready = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_awready_int : 1'b0);
assign axi_rvalid = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_rvalid_int : 1'b0);
assign axi_bvalid = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_bvalid_int : 1'b0);
assign axi_arready = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_arready_int : 1'b0);
ddr_axi Inst_DDR_AXI (
.ddr2_dq (ddr2_dq),
.ddr2_dqs_p (ddr2_dqs_p),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_cke (ddr2_cke),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
//-- Inputs
.sys_clk_i (CLK_200MHZ),
.sys_rst (RST),
//-- user interface signals
/*.app_addr (mem_addr),
.app_cmd (mem_cmd),
.app_en (mem_en),
.app_wdf_data (mem_wdf_data),
.app_wdf_end (mem_wdf_end),
.app_wdf_mask (mem_wdf_mask),
.app_wdf_wren (mem_wdf_wren),
.app_rd_data (mem_rd_data),
.app_rd_data_end (mem_rd_data_end),
.app_rd_data_valid (mem_rd_data_valid),
.app_rdy (mem_rdy),
.app_wdf_rdy (mem_wdf_rdy),*/
.app_sr_req (1'b0),
//.app_sr_active (open),
.app_ref_req (1'b0),
// .app_ref_ack (open),
.app_zq_req (1'b0),
// .app_zq_ack (open),
.ui_clk (mem_ui_clk),
.ui_clk_sync_rst (mem_ui_rst),
.device_temp_i (12'b000000000000),
.init_calib_complete (mem_init_calib_complete),
// .user .interface .signals
//.mmcm_locked, // IDK
.aresetn(RST),
// .Slave .Interface .Write .Address .Ports
.s_axi_awid(0),
.s_axi_awaddr(axi_awaddr),
.s_axi_awlen(0),
.s_axi_awsize(2),
.s_axi_awburst(0),
.s_axi_awlock(0),
.s_axi_awcache(0),
.s_axi_awprot(axi_awprot),
.s_axi_awqos(0),
.s_axi_awvalid(axi_awvalid),
.s_axi_awready(axi_awready_int),
// .Slave .Interface .Write .Data .Ports
.s_axi_wdata(axi_wdata),
.s_axi_wstrb(axi_wstrb),
.s_axi_wlast(1),
.s_axi_wvalid(axi_wvalid),
.s_axi_wready(axi_wready_int),
// .Slave .Interface .Write .Response .Ports
.s_axi_bready(axi_bready),
//.s_axi_bid(0),
//.s_axi_bresp(0),
.s_axi_bvalid(axi_bvalid_int),
// .Slave .Interface .Read .Address .Ports
.s_axi_arid(0),
.s_axi_araddr(axi_araddr),
.s_axi_arlen(0),
.s_axi_arsize(2),
.s_axi_arburst(0),
.s_axi_arlock(0),
.s_axi_arcache(0),
.s_axi_arprot(axi_arprot),
.s_axi_arqos(0),
.s_axi_arvalid(axi_arvalid),
.s_axi_arready(axi_arready_int),
// .Slave .Interface .Read .Data .Ports
.s_axi_rready(axi_rready),
//.s_axi_rid(0),
.s_axi_rdata(axi_rdata),
//.s_axi_rresp(0),
//.s_axi_rlast(1),
.s_axi_rvalid(axi_rvalid_int));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFSBP_PP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100 + 3; int n, m, k, ns[MAX]; long long dp[MAX][MAX][MAX], cs[MAX][MAX]; long long solve(int cur = 0, int pre = 0, int rem = k) { if (cur == n && rem == 0) return 0; if (rem < 0 || (cur == n && rem != 0)) return 1e18; long long &ret = dp[cur][pre][rem]; if (ret != -1) return ret; if (ns[cur] == 0) { ret = 1e18; for (int i = 1; i <= m; i++) ret = min(ret, solve(cur + 1, i, rem - (pre != i)) + cs[cur][i - 1]); } else { if (ns[cur] == pre) ret = solve(cur + 1, pre, rem); else ret = solve(cur + 1, ns[cur], rem - 1); } return ret; } int main() { scanf( %d%d%d , &n, &m, &k); memset(dp, -1, sizeof(dp)); for (int i = 0; i < n; i++) { scanf( %d , &ns[i]); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %d , &cs[i][j]); } } long long ans = solve(); if (ans == 1e18) printf( -1 ); else printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; map<int, int> m; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; m[a[i]]++; } int chek[32]; chek[0] = 2; for (int i = 1; i < 32; i++) { chek[i] = chek[i - 1] * 2; } int sm = 0, coun = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < 32; j++) { int h = chek[j] - a[i]; if (m.find(h) != m.end()) { if (h == a[i] && m[a[i]] > 1) { coun++; break; } if (h != a[i]) { coun++; break; } } } } cout << n - coun << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char s[100010]; int n; int main() { scanf( %d , &n); scanf( %s , s + 1); sort(s + 1, s + n + 1); printf( %s n , s + 1); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> t; while (t--) { cin >> n; if (n % 7) cout << (n / 7) + 1 << n ; else cout << n / 7 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> st; int main() { ios::sync_with_stdio(0); int n, x; cin >> n; for (int i = 0; i < n; i++) { cin >> x; if (st.empty()) st.push_back(x); else { st.push_back(x); while (st.size() > 1) { if (st[int(st.size()) - 1] != st[int(st.size()) - 2]) break; st.pop_back(); st[int(st.size()) - 1]++; } } } cout << int(st.size()) << n ; for (auto v : st) cout << v << ; return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 11405 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4096,
w4095,
w256,
w3839,
w15356,
w11517,
w16,
w11533,
w128,
w11405;
assign w1 = i_data0;
assign w11405 = w11533 - w128;
assign w11517 = w15356 - w3839;
assign w11533 = w11517 + w16;
assign w128 = w1 << 7;
assign w15356 = w3839 << 2;
assign w16 = w1 << 4;
assign w256 = w1 << 8;
assign w3839 = w4095 - w256;
assign w4095 = w4096 - w1;
assign w4096 = w1 << 12;
assign o_data0 = w11405;
//multiplier_block area estimate = 9024.52305565;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long x1, y1; long long d = gcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } bool find_any_solution(long long a, long long b, long long c, long long &x0, long long &y0, long long &g) { g = gcd(abs(a), abs(b), x0, y0); if (c % g) { return false; } x0 *= c / g; y0 *= c / g; if (a < 0) x0 = -x0; if (b < 0) y0 = -y0; return true; } int32_t main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long a, b, c, x, y, g; cin >> a >> b >> c; if (!find_any_solution(a, b, -c, x, y, g)) { cout << -1 << endl; } else { cout << x << << y << endl; } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { if (a < 0) return gcd(-a, b); if (b < 0) return gcd(a, -b); return (b == 0) ? a : gcd(b, a % b); } template <class T> inline T lcm(T a, T b) { if (a < 0) return lcm(-a, b); if (b < 0) return lcm(a, -b); return a * (b / gcd(a, b)); } template <class T> T power(T N, T P) { return (P == 0) ? 1 : N * power(N, P - 1); } long long toInt64(string s) { long long r = 0; istringstream sin(s); sin >> r; return r; } double LOG(long long N, long long B) { return (log10l(N)) / (log10l(B)); } string itoa(long long a) { if (a == 0) return 0 ; string ret; for (long long i = a; i > 0; i = i / 10) ret.push_back((i % 10) + 48); reverse(ret.begin(), ret.end()); return ret; } vector<string> token(string a, string b) { const char *q = a.c_str(); while (count(b.begin(), b.end(), *q)) q++; vector<string> oot; while (*q) { const char *e = q; while (*e && !count(b.begin(), b.end(), *e)) e++; oot.push_back(string(q, e)); q = e; while (count(b.begin(), b.end(), *q)) q++; } return oot; } int Set(int N, int pos) { return N = N | (1 << pos); } int reset(int N, int pos) { return N = N & ~(1 << pos); } int check(int N, int pos) { return (bool)(N & (1 << pos)); } int toggle(int N, int pos) { if (check(N, pos)) return N = reset(N, pos); return N = Set(N, pos); } void pbit(int N) { printf( ( ); for (int i = 10; i >= 0; i--) { bool x = check(N, i); cout << x; } puts( ) ); } int fx[] = {0, 0, 1, -1, 1, -1, 1, -1}; int fy[] = {-1, 1, 0, 0, -1, -1, 1, 1}; int main() { int n; cin >> n; int u = 1, c = 1; for (int i = 1; i <= (int)n - 1; i++) { for (int j = 1; j <= (int)c; j++) { u++; if (u > n) u = 1; } cout << u << ; c++; } puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVER_PP_BLACKBOX_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int t, n; int a[200001]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); bool flag = false; for (int i = 2; i <= n; i++) if (abs(a[i] - a[i - 1]) > 1) { flag = true; printf( YES n ); printf( %d %d n , i - 1, i); break; } if (!flag) printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, count[8] = {0}; cin >> n; for (int i = 0; i < n; i++) { cin >> x; count[x] = count[x] + 1; } if ((count[5] == 0) && (count[7] == 0) && (count[2] >= count[4]) && (count[1] == count[4] + count[6]) && (count[2] + count[3] == count[4] + count[6])) { for (int i = 0; i < count[4]; i++) { cout << 1 2 4 << endl; } count[2] -= count[4]; for (int i = 0; i < count[2]; i++) { cout << 1 2 6 << endl; } for (int i = 0; i < count[3]; i++) { cout << 1 3 6 << endl; } } else { cout << -1 << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_TB_V
`define SKY130_FD_SC_HVL__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_TB_V
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "fadder.v"
`include "shl8.v"
module mul4x4(
input [3 : 0] a,
input [3 : 0] b,
output [7 : 0] res);
wire [2 : 0] shift_carry, sum_carry;
wire [7 : 0] a0, a1, a2, a3, sum0, sum1;
assign a0 = {4'b0, b[0] ? a : {3'b0}};
shl8 shifta1(
.a({4'b0, b[1] ? a : {3'b0}}),
.shift(3'b001),
.res(a1),
.carry(shift_carry[0]));
shl8 shifta2(
.a({4'b0, b[2] ? a : {3'b0}}),
.shift(3'b010),
.res(a2),
.carry(shift_carry[1]));
shl8 shifta3(
.a({4'b0, b[3] ? a : {3'b0}}),
.shift(3'b011),
.res(a3),
.carry(shift_carry[2]));
fadder #(.WIDTH(8)) adder1(
.a(a0),
.b(a1),
.sub_enable(1'b0),
.carry_in(1'b0),
.res(sum0),
.carry_out(sum_carry[0]));
fadder #(.WIDTH(8)) adder2(
.a(sum0),
.b(a2),
.sub_enable(1'b0),
.carry_in(1'b0),
.res(sum1),
.carry_out(sum_carry[1]));
fadder #(.WIDTH(8)) adder3(
.a(sum1),
.b(a3),
.sub_enable(1'b0),
.carry_in(1'b0),
.res(res),
.carry_out(sum_carry[2]));
endmodule
|
/* Solution by:- --------------Sannidhay Vashal ----------------NIT SRINAGAR */ #include<iostream> #include<vector> #include<algorithm> #include<stack> #include<queue> #include<map> #include<math.h> #include<climits> #include<set> #include<cstring> #include<unordered_map> #include <cstdlib> #include<cmath> #define fio ios_base::sync_with_stdio(false);cin.tie(NULL) #define ll long long int #define ull unsigned long long int #define cinll(x) ll x;cin>>x; #define cini(x) int x;cin>>x; #define cins(x) string x;cin>>x; #define vect(x) vector<ll> x; #define vect1(x) vector<ll> x;x.push_back(0); #define pb(x) push_back(x) #define mp(x,y) make_pair(x,y) #define MAX 1e18 #define MIN -1000000007 #define MOD 1000000007 using namespace std; bool compare(pair<ll,ll> a,pair<ll,ll> b){ return a.second<b.second; } int main(){ cinll(t); while(t--){ cinll(n); vector<ll> arr; unordered_map<ll,ll> mapit; vector<pair<ll,ll>> ans; for(ll i=0;i<n;i++) { cinll(x); arr.pb(x); mapit[x]++; } ll anss = -1; for(ll i=0;i<n;i++){ if(mapit[arr[i]]==1) ans.pb(mp(i+1,arr[i])); } sort(ans.begin(),ans.end(),compare); if(ans.size()>=1) anss = ans[0].first; cout<<anss<< n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int ct[2][6] = {0}; for (int i = 0; i < n; i++) { int tmp; scanf( %d , &tmp); ct[0][tmp]++; } for (int i = 0; i < n; i++) { int tmp; scanf( %d , &tmp); ct[1][tmp]++; } int diff = 0; int flag = 0; for (int i = 1; i <= 5; i++) { if (ct[0][i] != ct[1][i]) { int tmp = abs(ct[0][i] - ct[1][i]); if (tmp % 2 != 0) flag = 1; diff += tmp / 2; } } if (flag == 0) cout << diff / 2; else cout << -1; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_mul_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_CLK_EN
`define FPGA_SYN_CLK_DFF
`endif
module sparc_mul_dp(
ecl_mul_rs1_data,
ecl_mul_rs2_data,
spu_mul_op1_data,
spu_mul_op2_data,
valid,
spick,
byp_sel,
byp_imm,
acc_imm,
acc_actc2,
acc_actc3,
acc_actc5,
acc_reg_enb,
acc_reg_rst,
acc_reg_shf,
x2,
mul_data_out,
rst_l,
si,
so,
se,
rclk
);
input [63:0] ecl_mul_rs1_data; // EXU mul operand 1
input [63:0] ecl_mul_rs2_data; // EXU mul operand 2
input [63:0] spu_mul_op1_data; // SPU mul operand 1
input [63:0] spu_mul_op2_data; // SPU mul operand 2
input valid; // begin cyc0 of MUL operation
input spick; // Internal pick signals of exu, spu multiplier
input byp_sel; // SPU bypass ACCUM[63:0] as operand
input byp_imm; // SPU bypss action from mout immediately
input acc_imm; // SPU accumlate from mout immediately
input acc_actc2, acc_actc3; // accumulate enable for LSB-32 and All-96
input acc_actc5; // accumulate enable for LSB-32 and All-96
input acc_reg_enb; // ACCUM register enable
input acc_reg_rst; // ACCUM register reset
input acc_reg_shf; // ACCUM shift right 64-bit
input x2; // for op1*op2*2
input rst_l; // system reset
input si; // si
input se; // scan_enable
input rclk;
output so; // so
output [63:0] mul_data_out; // Multiplier outputs
wire [63:0] mul_op1_d, mul_op2_d, bypreg;
wire [63:32] mux1_reg, mux1_mou;
wire [96:0] mux2_reg, areg;
wire [135:0] mout, acc_reg_in, acc_reg;
wire op2_s0, op2_s1, op2_s2;
wire acc_reg_shf2, clk_enb1;
wire clk;
assign clk = rclk ;
///////////////////////////////////////////////////////////////////////////////
////// op1 inputs mux between EXU and SPU
///////////////////////////////////////////////////////////////////////////////
assign mul_op1_d = ({64{spick}} & spu_mul_op1_data) |
({64{~spick}} & ecl_mul_rs1_data );
///////////////////////////////////////////////////////////////////////////////
////// op2 inputs mux between EXU, SPU and bypass from ACCUM register
///////////////////////////////////////////////////////////////////////////////
assign op2_s0 = ~spick;
assign op2_s1 = spick & byp_sel ;
assign op2_s2 = spick & ~byp_sel ;
assign mul_op2_d = (op2_s0 & op2_s1)|(op2_s0 & op2_s2)|(op2_s1 & op2_s2) ? 64'hxx :
(op2_s0 ? ecl_mul_rs2_data :
(op2_s1 ? bypreg :
(op2_s2 ? spu_mul_op2_data : 64'hxx)
));
///////////////////////////////////////////////////////////////////////////////
////// Accumulate input muxes
///////////////////////////////////////////////////////////////////////////////
// MUX1: Pass acc_reg[31:0] at cyc2 of SPU accumulate, otherwise acc_reg[63:32]
assign mux1_reg[63:32] = acc_actc2 ? acc_reg[31:0]
: acc_reg[63:32] ;
// Bypass mout[31:0] (mul core output) of MAC1 at cyc5 when the lower 32-bit
// are ready but not lateched into acc_reg yet.
//
// MAC1: cyc1 |cyc2 |cyc3 | cyc4 | cyc5 | cyc6
// | | | | mout[31:0] | acc_reg[128:0]
// | | | | bypass | latched out
//
// MAC2: | cyc1 | cyc2 |
// | | ACCUM from |
// | | mout[31:0] |
//
assign mux1_mou[63:32] = (acc_actc2 & acc_actc5) ? mout[31:0]
: mout[63:32] ;
// MUX2: Immediate bypass from mout (output of mul core)
assign mux2_reg[96:0] = acc_imm ? {mout[128:64],mux1_mou[63:32]}
: {acc_reg[128:64],mux1_reg[63:32]};
// Enable of accumulate reg input to multipler core
assign areg[96:32] = mux2_reg[96:32] & {65{acc_actc3}} ;
assign areg[31:0] = mux2_reg[31:0] & {32{(acc_actc3 | acc_actc2)}};
///////////////////////////////////////////////////////////////////////////////
////// Multiplier core connection
///////////////////////////////////////////////////////////////////////////////
mul64 mulcore(.rs1_l (~mul_op1_d),
.rs2 (mul_op2_d),
.valid (valid),
.areg (areg),
.accreg (acc_reg[135:129]),
.x2 (x2),
.out (mout),
.rclk (clk),
.si (),
.so (),
.se (se),
.mul_rst_l (rst_l),
.mul_step (1'b1)
);
///////////////////////////////////////////////////////////////////////////////
///// ACCUM register and right shift muxes
///////////////////////////////////////////////////////////////////////////////
dff_s dffshf (.din (acc_reg_shf),
.clk (clk),
.q (acc_reg_shf2),
.se (se),
.si (),
.so ()
);
assign acc_reg_in = acc_reg_shf ? {64'b0,acc_reg[135:64]}
: mout ;
assign mul_data_out = acc_reg_shf2 ? acc_reg[63:0]
: mout[63:0] ;
`ifdef FPGA_SYN_CLK_DFF
dffre_s #(136) accum (.din (acc_reg_in),
.rst (acc_reg_rst),
.en (acc_reg_enb | acc_reg_rst), .clk(clk), //manually fixed
.q (acc_reg),
.se (se),
.si (),
.so ()
);
`else
dffr_s #(136) accum (.din (acc_reg_in),
.rst (acc_reg_rst),
.clk (clk_enb1),
.q (acc_reg),
.se (se),
.si (),
.so ()
);
`endif
`ifdef FPGA_SYN_CLK_EN
`else
clken_buf ckbuf_1(.clk(clk_enb1), .rclk(clk), .enb_l(~(acc_reg_enb | acc_reg_rst)), .tmb_l(~se));
`endif
assign bypreg = byp_imm ? mout[63:0]
: acc_reg[63:0] ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_0_V
`define SKY130_FD_SC_LP__MUX2_0_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_0 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_0 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_0_V
|
module Datapath_FunctionUnit(
output [WORD_WIDTH-1:0] F,
output V, C, N, Z,
input [WORD_WIDTH-1:0] A,
input [WORD_WIDTH-1:0] B,
input [3:0] FS
);
/*
* F - Function unit output data Size: WORD_WIDTH
* A - Function unit input data A Size: WORD_WIDTH
* B - Function unit input data B Size: WORD_WIDTH
* FS - Function unit function selector Size: 4 bit
* N - Negative Output Flag Size: 1 bit
* Z - Zero Flag Size: 1 bit
* C - Carry Flag - Overflow without signal Size: 1 bit
* V - Overflow Flag - Overflow with signal Size: 1 bit
*/
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
wire [WORD_WIDTH-1:0] V_temp;
assign V_temp = A[WORD_WIDTH-2:0]+B[WORD_WIDTH-2:0];
assign V = V_temp[WORD_WIDTH-1];
assign N = F[WORD_WIDTH-1];
assign Z = (!F)?1'b1:1'b0;
Datapath_FunctionUnit_ArithmeticLogicUnit_Behavioral ULA0(F,C,A,B,FS);
defparam ULA0.WORD_WIDTH = WORD_WIDTH;
defparam ULA0.DR_WIDTH = DR_WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<int> V(n); for (int i = 0; i < m; ++i) { int k; cin >> k; V[k - 1]++; } int mn = 1e9; for (int i = 0; i < n; ++i) mn = min(mn, V[i]); cout << mn << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; clock_t time_p = clock(); void time_taken() { time_p = clock() - time_p; cerr << Time Taken : << (float)(time_p) / CLOCKS_PER_SEC << n ; } const long long mod = 1e9 + 7; const long long INF = 1e18; void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int mn = *min_element((a).begin(), (a).end()); vector<int> inds, b; for (int i = 0; i < n; i++) { if (a[i] % mn == 0) inds.push_back(i), b.push_back(a[i]); } sort((b).begin(), (b).end()); int j = 0; for (int x : inds) { a[x] = b[j++]; } if (is_sorted((a).begin(), (a).end())) { cout << YES << n ; } else { cout << NO << n ; } } int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); int t; cin >> t; while (t--) { solve(); } time_taken(); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:46:25 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_alu_0_0/RAT_alu_0_0_stub.v
// Design : RAT_alu_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "alu,Vivado 2016.4" *)
module RAT_alu_0_0(A, B, C_IN, Sel, SUM, C_FLAG, Z_FLAG)
/* synthesis syn_black_box black_box_pad_pin="A[7:0],B[7:0],C_IN,Sel[3:0],SUM[7:0],C_FLAG,Z_FLAG" */;
input [7:0]A;
input [7:0]B;
input C_IN;
input [3:0]Sel;
output [7:0]SUM;
output C_FLAG;
output Z_FLAG;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Manually created global mem, to avoid qsys hex generation bug
// qsys will always generate a .hex file to initialize the
// altsyncram - EVEN if you specify not to init the ram,
// for big ram's, this causes qsys to hang
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module bram_512x33M (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter DEPTH = 33554432;
parameter NWORDS_A = 33554432;
parameter ADDR_WIDTH = 25; // this should be $clog( DEPTH ), but qsys dies;
output [512: 0] readdata;
// ADDR_WIDTH
input [ 24: 0] address;
input [ 63: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [511: 0] writedata;
reg [511: 0] readdata;
wire [511: 0] readdata_ram;
wire wren;
always @(posedge clk)
begin
if (clken)
readdata <= readdata_ram;
end
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata_ram),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = DEPTH,
the_altsyncram.numwords_a = NWORDS_A,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 512,
the_altsyncram.width_byteena_a = 64,
the_altsyncram.widthad_a = ADDR_WIDTH;
//////////////// END SIMULATION-ONLY CONTENTS
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module state_machine_counter #(
parameter INTR_TYPE = 1'b1
)(
clk,
reset_n,
pulse_irq_counter_stop,
global_enable_reg,
counter_start,
counter_stop,
enable,
c_idle,
level_reset,
data_store
);
input wire clk;
input wire reset_n;
input wire pulse_irq_counter_stop;
input wire global_enable_reg;
input wire counter_start;
input wire counter_stop;
output reg enable;
output reg level_reset;
output reg data_store;
output reg c_idle;
reg [1:0] state ;
reg [1:0] next_state ;
localparam IDLE =2'b00;
localparam START =2'b01;
localparam STOP =2'b10;
localparam STORE =2'b11;
//State machine Sequential logic
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n) state <= IDLE;
else state<= next_state;
end
//State Machine Transitional conditions
always @(state or counter_start or counter_stop or pulse_irq_counter_stop or global_enable_reg)
begin
case (state)
IDLE: if (counter_start==1'b0 || global_enable_reg == 1'b0 || pulse_irq_counter_stop==1'b1) begin
next_state = IDLE; // active low reset signal
end else begin
next_state = START;
end
START: if (global_enable_reg == 1'b0) begin
next_state = IDLE;
end
else if ((INTR_TYPE == 0 & counter_stop==1'b1) |(INTR_TYPE == 1 & pulse_irq_counter_stop==1'b1))
begin
next_state = STOP;
end
else
begin
next_state = START;
end
STOP: begin
next_state = STORE;
end
STORE: begin
next_state = IDLE;
end
default:next_state = IDLE;
endcase
end
//combo logic function to control counter
always @ (state) begin
case (state)
IDLE: begin
enable = 1'b0;
level_reset = 1'b0;
data_store = 1'b0;
c_idle = 1'b1;
end
START: begin
enable = 1'b1;
level_reset = 1'b1;
data_store = 1'b0;
c_idle = 1'b0;
end
STOP: begin
enable = 1'b0;
level_reset = 1'b1;
data_store = 1'b0;
c_idle = 1'b0;
end
STORE: begin
enable = 1'b0;
level_reset = 1'b1;
data_store = 1'b1;
c_idle = 1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> int main() { int k, x, n; scanf( %d %d , &n, &k); int p = k; while (p >= 1) { x = k * n / p + p; if (n == ((x / k) * (x % k))) break; p--; } printf( %d , x); } |
#include<bits/stdc++.h> using namespace std; const int maxn=4e3+100; typedef long long ll; ll l[maxn],r[maxn],d[maxn]; int main() { int n,m,k;cin>>n>>m>>k; for(int i=1;i<=m;i++)cin>>l[i]>>r[i]; ll ans=0; for(int i=1,j=k;j<=n;i++,j++)//枚举第一个区间 { ll sum=0,w; memset(d,0,sizeof(d)); for(int p=1;p<=m;p++) { w = max(0ll, min(r[p], 1ll*j)+1 - max(l[p], 1ll*i)); sum += w; if(w<r[p]-l[p]+1)d[l[p]+w]++,d[l[p]+k]--,d[r[p]+1]--,d[r[p]+1+k-w]++; } for(int q=1;q<=n;q++)d[q]+=d[q-1]; ll imax=0; for(int q=1;q<=n;q++)d[q]+=d[q-1],imax=max(imax,1ll*d[q]); ans=max(ans,sum+imax); } cout<<ans<<endl; } |
#include <bits/stdc++.h> using namespace std; int mod; unsigned long long work(vector<int> &x) { sort(x.begin(), x.end()); int n = x.size(); int m = x.end() - unique(x.begin(), x.end()); unsigned long long ret = 1; for (int i = 2; i <= n; i++) { unsigned long long tmp = i; while (m > 0 && tmp % 2 == 0) tmp /= 2, m--; ret = ret * tmp % mod; } return ret; } int main() { vector<pair<int, int> > vec; int n; scanf( %d , &n); for (int i = 0; i < n; i++) { int a; scanf( %d , &a); vec.push_back(pair<int, int>(a, i)); } for (int i = 0; i < n; i++) { int b; scanf( %d , &b); vec.push_back(pair<int, int>(b, i)); } scanf( %d , &mod); sort(vec.begin(), vec.end()); unsigned long long ans = 1; for (int i = 0; i < n + n;) { int nexti = i; vector<int> tmp; while (nexti < n + n && vec[i].first == vec[nexti].first) { tmp.push_back(vec[nexti].second); nexti++; } ans = ans * work(tmp) % mod; i = nexti; } printf( %d n , (int)ans); return 0; } |
#include <bits/stdc++.h> using namespace std; map<pair<int, int>, pair<int, int> > p; int res[100 + 10][100 + 10]; int main() { int n, m, q, k, d, t, tem1, tem2, tem3, tem4, y = 1, sum = 0, ans = 0; string s, c; scanf( %d%d%d , &n, &m, &q); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { p[{i, j}] = {i, j}; } } for (int i = 0; i < q; i++) { scanf( %d%d , &tem1, &tem2); tem2--; if (tem1 != 3) { if (tem1 == 1) { pair<int, int> here = p[{tem2, 0}]; for (int j = 0; j < m - 1; j++) { p[{tem2, j}] = p[{tem2, j + 1}]; } p[{tem2, m - 1}] = here; } else { pair<int, int> here = p[{0, tem2}]; for (int j = 0; j < n - 1; j++) { p[{j, tem2}] = p[{j + 1, tem2}]; } p[{n - 1, tem2}] = here; } } else { scanf( %d%d , &tem3, &tem4); tem3--; pair<int, int> here = p[{tem2, tem3}]; res[here.first][here.second] = tem4; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { printf( %d , res[i][j]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } template <typename T> void printV(const T &t) { std::copy(t.cbegin(), t.cend(), std::ostream_iterator<typename T::value_type>(std::cout, )); cout << n ; } template <typename T> void printVV(const T &t) { for (int i = 0; i < t.size(); i++) { printf( %d: , i); printV(t[i]); } } template <typename T, typename S> void printVP(vector<pair<T, S>> vp) { if (vp.empty()) { cout << n ; return; } for (int i = 0; i < vp.size() - 1; i++) { cout << ( << vp[i].first << << vp[i].second << ) ; } cout << ( << vp[vp.size() - 1].first << << vp[vp.size() - 1].second << ) n ; } template <typename T> void printVVP(vector<vector<pair<T, T>>> vvp) { for (int i = 0; i < vvp.size(); i++) { cout << i << : ; printVP(vvp[i]); } } vector<string> split(const string &s, char delim) { vector<string> result; stringstream ss(s); string item; while (getline(ss, item, delim)) { result.push_back(item); } return result; } bool is_number(const string &s) { string::const_iterator it = s.begin(); while (it != s.end() && isdigit(*it)) ++it; return !s.empty() && it == s.end(); } void fast() { ios::sync_with_stdio(false); cin.tie(NULL); } bool isValid(int r, int c, int R, int C) { return (r >= 0 && r < R && c >= 0 && c < C); } struct Can { long long x, r, id; }; bool compareByX(const Can &lhs, const Can &rhs) { return lhs.x < rhs.x; } class Person { public: string name, speak; unordered_set<string> understands; friend ostream &operator<<(ostream &os, const Person &p) { os << p.name << ( << p.speak << ): ; for (auto s : p.understands) os << << s; return os; } }; vector<pair<int, int>> deltas = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}}; const int INF = 1e9 + 10; const long long inf = 1e18 + 10; const long double PI = 3.14159265359; int main() { int N; cin >> N; vector<int> A(N), B(N); for (int i = 0; i < (N); ++i) { cin >> A[i]; B[i] = A[i]; } sort(B.begin(), B.end()); unordered_map<int, int> m; for (int i = 0; i < (N); ++i) m[B[i]] = i; vector<int> C(N); for (int i = 0; i < (N); ++i) { C[i] = B[(m[A[i]] + 1) % N]; } printV(C); } |
// simulates multiplier ip core provided by xilinx
module mpemu(
input wire clk,
input wire [23:0] mpcand_i,
input wire [23:0] mplier_i,
output wire [27:0] mprod_o);
`ifndef NO_IP
// A: signed 24 bit
// B: signed 24 bit
// P: Custom Output Width MSB=46 LSB=19
// Pipeline Stages 5
mp mp(
.clk(clk),
.a(mpcand_i),
.b(mplier_i),
.p(mprod_o));
`else
reg [23:0] delay_a[4:0];
reg [23:0] delay_b[4:0];
always @(posedge clk) begin
delay_a[0] <= mpcand_i;
delay_a[1] <= delay_a[0];
delay_a[2] <= delay_a[1];
delay_a[3] <= delay_a[2];
delay_a[4] <= delay_a[3];
delay_b[0] <= mplier_i;
delay_b[1] <= delay_b[0];
delay_b[2] <= delay_b[1];
delay_b[3] <= delay_b[2];
delay_b[4] <= delay_b[3];
end
wire [23:0] delayed_a = delay_a[4];
wire [23:0] delayed_b = delay_b[4];
wire [46:0] prod_full = $signed(delayed_a) * $signed(delayed_b);
assign mprod_o = prod_full[46:19];
`endif
endmodule
module mpemu_scale(
input wire clk,
input wire [23:0] mpcand_i,
input wire [31:0] scale_i,
output wire [31:0] mprod_o);
`ifndef NO_IP
// A: signed 24 bit
// B: unsigned 32 bit
// P: Custom Output Width MSB=55 LSB=24
// Pipeline Stages 6
mp_scale mp_scale(
.clk(clk),
.a(mpcand_i),
.b(scale_i),
.p(mprod_o));
`else
reg [23:0] delay_a[6:0];
reg [31:0] delay_b[6:0];
always @(posedge clk) begin
delay_a[0] <= mpcand_i;
delay_a[1] <= delay_a[0];
delay_a[2] <= delay_a[1];
delay_a[3] <= delay_a[2];
delay_a[4] <= delay_a[3];
delay_a[5] <= delay_a[4];
delay_a[6] <= delay_a[5];
delay_b[0] <= scale_i;
delay_b[1] <= delay_b[0];
delay_b[2] <= delay_b[1];
delay_b[3] <= delay_b[2];
delay_b[4] <= delay_b[3];
delay_b[5] <= delay_b[4];
delay_b[6] <= delay_b[5];
end
wire [23:0] delayed_a = delay_a[5];
wire [31:0] delayed_b = delay_b[5];
wire signed [32:0] delayed_b_signed = {1'b0, delay_b[5]};
// for saturated delay
wire [23:0] delayed_a2 = delay_a[6];
wire [31:0] delayed_b2 = delay_b[6];
wire signed [55:0] prod_full = $signed(delayed_a) * $signed(delayed_b_signed);
assign mprod_o = prod_full[55:24];
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; int t; int n; long long dp[500010][2]; long long x; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> t; while (t--) { cin >> n; for (int i = 1; i <= n + 1; i++) { dp[i][0] = 0; dp[i][1] = 0; } dp[0][0] = 1; long long ans = 0; for (int i = 1; i <= n; i++) { cin >> x; x++; dp[x][0] = (dp[x][0] + dp[x][0]) % mod; dp[x][0] = (dp[x][0] + dp[x - 1][0]) % mod; dp[x][1] = (dp[x][1] + dp[x][1]) % mod; dp[x + 2][1] = (dp[x + 2][1] + dp[x + 2][1]) % mod; if (x > 1) { dp[x][1] = (dp[x][1] + dp[x - 2][0]) % mod; } } for (int i = 1; i <= n + 1; i++) { ans = (ans + dp[i][0]) % mod; ans = (ans + dp[i][1]) % mod; } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int k, a, b, v; cin >> k >> a >> b >> v; int x = (a + v - 1) / v; int t, y; t = b / (k - 1); y = t * k; while (y > x) { b--; t = b / (k - 1); y = t * k; } int c; c = b % (k - 1) + 1; int m; if (x > c + y) m = x - (c + y); else m = 0; if (y < x) cout << m + t + 1; else cout << m + t; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_in2_gt_in1_3b.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Three bit comparison of two inputs that can have any value.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_in2_gt_in1_3b (
din1,
din2,
din2_neq_din1,
din2_gt_din1
);
input [2:0] din1; // input 1- 3 bits
input [2:0] din2; // input 2- 3 bits
output din2_neq_din1; // input 2 doesn't equal input 1
output din2_gt_din1; // input 2 is greater than input 1
wire [2:0] din2_eq_din1;
wire din2_neq_din1;
wire din2_gt_din1;
assign din2_eq_din1[2:0]= (~(din1 ^ din2));
assign din2_neq_din1= (!(&din2_eq_din1));
assign din2_gt_din1= ((!din1[2]) && din2[2])
|| (din2_eq_din1[2] && (!din1[1]) && din2[1])
|| ((&din2_eq_din1[2:1]) && (!din1[0]) && din2[0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_2_V
`define SKY130_FD_SC_MS__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, a, b, c, d, mn, mx; cin >> a >> b >> c >> d; mn = min(b, d); b -= mn; d -= mn; if (d > b) { for (i = 0; i < 1000; i++) { if (d % a == 0) { cout << d + mn; return 0; } d += c; } } else if (d < b) { for (i = 0; i < 1000; i++) { if (b % c == 0) { cout << b + mn; return 0; } b += a; } } else if (d == b) { cout << d + mn; return 0; } cout << -1 ; return 0; } |
#include <bits/stdc++.h> using namespace std; using Int = long long; constexpr static int mod = 1e9 + 7; constexpr static int inf = (1 << 30) - 1; constexpr static Int infll = (1LL << 61) - 1; int Competitive_Programming = (ios_base::sync_with_stdio(false), cin.tie(nullptr), cout << fixed << setprecision(15), 0); #pragma GCC target( avx2 ) #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) int main() { Int N, D, M; cin >> N >> D >> M; vector<Int> a(N); vector<Int> low, high; for (int i = 0; i < N; i++) { cin >> a[i]; if (a[i] > M) high.push_back(a[i]); else low.push_back(a[i]); } sort(low.rbegin(), low.rend()); sort(high.rbegin(), high.rend()); vector<Int> lowsum(low.size() + 1), highsum(high.size() + 1); for (int i = 0; i < low.size(); i++) lowsum[i + 1] = lowsum[i] + low[i]; for (int i = 0; i < high.size(); i++) highsum[i + 1] = highsum[i] + high[i]; Int ans = 0, hsz = highsum.size(), lsz = lowsum.size(); for (int i = 0; i < lsz; i++) ans = max(ans, highsum[min(hsz - 1, (N - i + D) / (D + 1))] + lowsum[i]); cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double PI = acos(-1), eps = 1e-6; const int dx[4] = {-1, 1, 0, 0}, dy[4] = {0, 0, -1, 1}; const int N = 1e6 + 5, M = 2e6 + 5, mod = 1e9 + 7; int n; int p[N], c[N]; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int T; cin >> T; while (T--) { cin >> n; bool success = true; for (int i = 1, d = 0; i <= n; i++) { cin >> p[i] >> c[i]; if (p[i] < c[i] || p[i] < p[i - 1] || c[i] < c[i - 1] || p[i] - c[i] < d) success = false; d = p[i] - c[i]; } cout << (success ? YES : NO ) << endl; } return 0; } |
// -----------------------------------------------------------
// PLI byte transport HDL interface
//
// @author jyeap, gkwan
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(.PURPOSE(PURPOSE)) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_9_3 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_HD__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, k, ans, a[2000]; int main() { cin >> n >> k; ans = k; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) ans = max(ans, k / a[i] * a[j] + k % a[i]); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout << 2001 n ; for (int i = 1; i <= 1000; i++) { cout << i << 1 << i << 2 n ; } cout << 1 1 1 2 n ; for (int i = 1; i <= 1000; i++) { cout << i << 1 << i << 2 n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[4] = {0, 0, 1, -1}; int dy[4] = {1, -1, 0, 0}; const int mod = (int)1e9 + 7; long long INF64 = 3e18; void smxl(long long &a, long long b) { if (a < b) a = b; } void smnl(long long &a, long long b) { if (a > b) a = b; } void adsl(long long &a, long long b) { a += b; if (a >= mod) a -= mod; } void misl(long long &a, long long b) { a -= b; if (a >= mod) a -= mod; if (a < 0) a += mod; } void smx(long long &a, long long b) { if (a < b) a = b; } void smn(long long &a, long long b) { if (a > b) a = b; } void ads(long long &a, long long b) { a += b; if (a >= mod) a -= mod; } void mis(long long &a, long long b) { a -= b; if (a >= mod) a -= mod; if (a < 0) a += mod; } long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long egcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = egcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long mbinp(long long a, long long b) { a %= mod; if (b == 0) return 1; long long ans = mbinp(a, b / 2); long long tmp = (ans * ans) % mod; if (b % 2) return ((tmp * a) % mod); return ((tmp) % mod); } long long C(int n, int m) { long long ret = 1; for (int i = 1; i <= m; i++) { ret *= (n - i + 1); ret /= i; } return ret; } long long binp(long long a, int b) { long long res = 1; while (b) { if (b & 1) { if (res < INF64 / a) res *= a; else return INF64; } if (b > 1) { if (a < INF64 / a) a *= a; else return INF64; } b >>= 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; vector<int> primes(100, 0); vector<int> mu(100, 0); for (int i = 2; i < 100; i++) { if (primes[i] == 0) { mu[i]++; for (int j = 2 * i; j < 100; j += i) { primes[j] = 1; if (mu[j] != -1) mu[j]++; } for (int z = i * i; z < 100; z += i * i) mu[z] = -1; } } mu[1] = 2; vector<pair<long long, int> > all(n); for (int i = 0; i < n; i++) { cin >> all[i].first; all[i].second = i; } sort(all.rbegin(), all.rend()); vector<long long> poss(62); for (int i = 3; i < 62; i++) poss[i] = (long long)ceil(pow((long double)1e18, 1.0 / i)); vector<long long> ans(n); for (int i = 0; i < n; i++) { long long skr = -1; long long low = 0; long long hi = 1e9 + 10; while (low <= hi) { long long mid = (low + hi) / 2; if (mid * mid <= all[i].first) { if (mid > skr) skr = mid; low = mid + 1; } else hi = mid - 1; } poss[1] = all[i].first; poss[2] = skr; for (int j = 3; j < 62; j++) { while (poss[j] > 0 && binp(poss[j], j) > all[i].first) poss[j]--; } long long out = 0; for (int j = 1; j < 62; j++) { out += (poss[j] - 1) * (mu[j] == -1 ? 0 : (mu[j] % 2 == 1 ? -1 : 1)); } ans[all[i].second] = out; } for (int i = 0; i < n; i++) cout << ans[i] << n ; } |
// fpgaTop_ml605.v - ssiegel 2009-03-17
// 2012-02-11 ssiegel Added MDIO port
// 2014-01-26 ssiegel Added UART port
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire sys1_clkp, // sys1 Clock +
input wire sys1_clkn, // sys1 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [3:0] pci_exp_txp, // PCIe lanes...
output wire [3:0] pci_exp_txn,
input wire [3:0] pci_exp_rxp,
input wire [3:0] pci_exp_rxn,
output wire [12:0] led, // LEDs ml605
output wire [ 3:0] lcd_db, // LCD databus
output wire lcd_e, // LCD enable
output wire lcd_rs, // LCD register-select
output wire lcd_rw, // LCD read-not-write
input wire ppsExtIn, // PPS in
output wire ppsOut, // PPS out
output wire upads_rts, // USB UART...
output wire upads_tx,
input wire upads_cts_arg,
input wire upads_rx_arg,
output wire gmii_rstn, // Alaska GMII...
output wire gmii_gtx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire mdio_mdc, // Alaska MDIO...
inout wire mdio_mdd,
output wire [23:0] flash_addr,
inout wire [15:0] flash_io_dq,
input wire flash_wait,
output wire flash_we_n,
output wire flash_oe_n,
output wire flash_ce_n,
inout wire [63:0] ddr3_dq, // DDR3 DRAM...
output wire [12:0] ddr3_addr,
output wire [2:0] ddr3_ba,
output wire ddr3_ras_n,
output wire ddr3_cas_n,
output wire ddr3_we_n,
output wire ddr3_reset_n,
output wire [0:0] ddr3_cs_n,
output wire [0:0] ddr3_odt,
output wire [0:0] ddr3_cke,
output wire [7:0] ddr3_dm,
inout wire [7:0] ddr3_dqs_p,
inout wire [7:0] ddr3_dqs_n,
output wire [0:0] ddr3_ck_p,
output wire [0:0] ddr3_ck_n,
output wire flp_com_sclk, // FMC150 in LPC Slot...
output wire flp_com_sdc2m,
output wire flp_cdc_csb,
output wire flp_dac_csb,
input wire flp_cdc_sdi,
input wire flp_dac_sdi,
// input wire [3:0] flp_sdi_sdm2c,
// output wire [3:0] flp_csb
output wire flp_cdc_rstn,
output wire flp_cdc_pdn,
// output wire dac0_txena, //TODO These 7
// output wire dac0_dclkp,
// output wire dac0_dclkn,
// output wire dac0_framep,
// output wire dac0_framen,
// output wire [7:0] dac0_dap,
// output wire [7:0] dac0_dan,
//output wire flp_mon_rstn,
//output wire flp_mon_intn,
//output wire flp_adc_rstn,
input wire flp_cdc_clk_p,
input wire flp_cdc_clk_n,
//input wire flp_cdc_pllstat,
output wire flp_cdc_refen
);
//FIXME:
assign flp_cdc_pdn = 1'b1;
assign flp_cdc_refen = 1'b1;
wire flpCDC_sclkn, flpCDC_sclkgate;
wire flpDAC_sclkn, flpDAC_sclkgate;
assign flp_com_sclk = (flpCDC_sclkn && flpCDC_sclkgate) || (flpDAC_sclkn && flpDAC_sclkgate);
wire flpCDC_com_sdc2m, flpDAC_com_sdc2m;
assign flp_com_sdc2m = (flpCDC_com_sdc2m && flpCDC_sclkgate) || (flpDAC_com_sdc2m && flpDAC_sclkgate);
// Instance and connect mkFTop...
mkFTop_ml605 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.sys1_clkp (sys1_clkp),
.sys1_clkn (sys1_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.lcd_db (lcd_db),
.lcd_e (lcd_e),
.lcd_rs (lcd_rs),
.lcd_rw (lcd_rw),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut),
.upads_rts (upads_rts),
.upads_tx (upads_tx),
.upads_cts_arg (upads_cts_arg),
.upads_rx_arg (upads_rx_arg),
.gmii_rstn (gmii_rstn),
.gmii_tx_txd (gmii_txd),
.gmii_tx_tx_en (gmii_tx_en),
.gmii_tx_tx_er (gmii_tx_er),
.gmii_rx_rxd_i (gmii_rxd),
.gmii_rx_rx_dv_i (gmii_rx_dv),
.gmii_rx_rx_er_i (gmii_rx_er),
.gmii_tx_tx_clk (gmii_gtx_clk),
.gmii_rx_clk (gmii_rx_clk),
.mdio_mdc (mdio_mdc),
.mdio_mdd (mdio_mdd),
.flash_addr (flash_addr),
.flash_io_dq (flash_io_dq),
.flash_fwait_i (flash_wait),
.flash_we_n (flash_we_n),
.flash_oe_n (flash_oe_n),
.flash_ce_n (flash_ce_n),
.dram_io_dq (ddr3_dq),
.dram_addr (ddr3_addr),
.dram_ba (ddr3_ba),
.dram_ras_n (ddr3_ras_n),
.dram_cas_n (ddr3_cas_n),
.dram_we_n (ddr3_we_n),
.dram_reset_n (ddr3_reset_n),
.dram_cs_n (ddr3_cs_n),
.dram_odt (ddr3_odt),
.dram_cke (ddr3_cke),
.dram_dm (ddr3_dm),
.dram_io_dqs_p (ddr3_dqs_p),
.dram_io_dqs_n (ddr3_dqs_n),
.dram_ck_p (ddr3_ck_p),
.dram_ck_n (ddr3_ck_n),
.flpCDC_sclkn (flpCDC_sclkn), // Use the inverted clock for slow-balanced setup/hold
.flpCDC_sclkgate (flpCDC_sclkgate),
.flpCDC_sdo (flpCDC_com_sdc2m),
.flpCDC_csb (flp_cdc_csb),
.flpCDC_sdi_arg (flp_cdc_sdi),
.flpDAC_sclkn (flpDAC_sclkn), // Use the inverted clock for slow-balanced setup/hold
.flpDAC_sclkgate (flpDAC_sclkgate),
.flpDAC_sdo (flpDAC_com_sdc2m),
.flpDAC_csb (flp_dac_csb),
.flpDAC_sdi_arg (flp_dac_sdi),
// .dac0_txena (dac0_txena), //TODO These 7
// .dac0_dclkp (dac0_dclkp),
// .dac0_dclkn (dac0_dclkn),
// .dac0_framep (dac0_framep),
// .dac0_framen (dac0_framen),
// .dac0_dap (dac0_dap),
// .dac0_dan (dac0_dan),
.flpCDC_srst (flp_cdc_rstn), // The srst from SPICore32 active-low
//.flp_cdc_pdn (flp_cdc_pdn),
//.flp_mon_rstn (flp_mon_rstn),
//.flp_mon_intn (flp_mon_intn),
//.flp_adc_rstn (flp_adc_rstn),
.flp_cdc_clk_p (flp_cdc_clk_p),
.flp_cdc_clk_n (flp_cdc_clk_n)
//.flp_cdc_pllstat (flp_cdc_pllstat),
//.flp_cdc_refen (flp_cdc_refen)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
`define SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_xlconcat_0_0 (
In0,
dout
);
input wire [0 : 0] In0;
output wire [0 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(1),
.NUM_PORTS(1)
) inst (
.In0(In0),
.In1(1'B0),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// -----------------------------------------------
// False path marker module
// This module creates a level of flops for the
// targetted clock, and cut the timing path to the
// flops using embedded SDC constraint
//
// Only use this module to clock cross the path
// that is being clock crossed properly by correct
// concept.
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_false_path_marker
#(
parameter MARKER_WIDTH = 1
)
(
input reset,
input clk,
input [MARKER_WIDTH - 1 : 0] data_in,
output [MARKER_WIDTH - 1 : 0] data_out
);
(* ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \" set_false_path -to [get_registers *altera_tse_false_path_marker:*|data_out_reg*]\"" *)
(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
assign data_out = data_out_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data_out_reg <= {MARKER_WIDTH{1'b0}};
end
else
begin
data_out_reg <= data_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 511111; int num[maxn]; int q[maxn]; int main() { int i, j, n, m, k; scanf( %d%d , &n, &m); memset(num, 0, sizeof(num)); num[0] = 1; for (i = 1; i <= n; i++) { scanf( %d , &k); for (j = 500000; j >= k; j--) { if (num[j - k]) num[j] = 1; } } int tot = 0; for (i = 0; i <= 500000; i++) if (num[i]) q[++tot] = i; q[0] = 0; int tt = 0; int ans = 0; q[++tot] = 1111111111; for (i = 1; i <= tot;) { if (q[i] - ans <= m) { i++; } else { i--; if (ans == q[i]) break; ans = q[i]; tt++; } } printf( %d %d n , ans, tt); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 04/22/09 revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module IOBUF (O, IO, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
bufif0 T1 (IO, I, T);
buf B1 (O, IO);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end // initial begin
endmodule
|
`include "assert.vh"
`include "stack.vh"
module Stack_tb();
parameter WIDTH = 8;
parameter DEPTH = 1; // frames (exponential)
localparam MAX_STACK = (1 << DEPTH+1) - 1;
reg clk = 0;
reg reset;
reg [ 1:0] op;
reg [WIDTH-1:0] data;
wire [WIDTH-1:0] tos;
wire [1:0] status;
wire [1:0] error;
stack #(
.WIDTH(WIDTH),
.DEPTH(DEPTH)
)
dut(
.clk(clk),
.reset(reset),
.op(op),
.data(data),
.tos(tos),
.status(status),
.error(error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("stack_tb.vcd");
$dumpvars(0, Stack_tb);
// `status` is `empty` by default
`assert(status, `EMPTY);
// Underflow
op <= `POP;
data <= 0;
#2
`assert(error, `UNDERFLOW);
// Push
op <= `PUSH;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h00);
op <= `PUSH;
data <= 1;
#2
`assert(status, `NONE);
`assert(tos , 8'h01);
op <= `PUSH;
data <= 2;
#2
`assert(status, `FULL);
`assert(tos , 8'h02);
// Top of Stack
op <= `NONE;
#2
`assert(status, `FULL);
`assert(tos , 8'h02);
// Overflow
op <= `PUSH;
data <= 3;
#2
`assert(error, `OVERFLOW);
`assert(tos , 8'h02);
// Pop
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h01);
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
// Replace
op <= `REPLACE;
data <= 4;
#2
`assert(error, `UNDERFLOW);
op <= `PUSH;
data <= 5;
#2
`assert(status, `NONE);
`assert(tos , 8'h05);
op <= `REPLACE;
data <= 6;
#2
`assert(status, `NONE);
`assert(tos , 8'h06);
op <= `NONE;
#2
`assert(status, `NONE);
`assert(tos , 8'h06);
// Reset
reset <= 1;
#2
reset <= 0;
`assert(status, `EMPTY);
$finish;
end
endmodule
|
#include <bits/stdc++.h> const int INF = (int)(1e9); const long long INFLL = (long long)(1e18); const double EPS = 1e-13; using namespace std; int main() { ios_base::sync_with_stdio(false); int n, k; cin >> n >> k; vector<int> b(n); for (int i = 0; i < n; i++) cin >> b[i]; vector<int> a; for (int i = 0; i < n; i++) if (b[i] == 0) a.push_back(i); for (int i = n - 1; i >= 0; i--) if (b[i] > 0) { int cnt = 0; int index = -1; for (int j = 0; j < a.size(); j++) { if (a[j] >= i + k) cnt++; if (cnt == b[i]) { index = j + 1; break; } } a.insert(a.begin() + index, i); } for (int i = 0; i < n; i++) cout << a[i] + 1 << ; cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O2BB2AI_PP_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_PP_BLACKBOX_V
|
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1ns / 1ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #
(
// depth of synchronizer
parameter N = 2
)
(
input wire clk,
input wire rst,
output wire out
);
(* srl_style = "register" *)
reg [N-1:0] sync_reg = {N{1'b1}};
assign out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
sync_reg <= {N{1'b1}};
end else begin
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int t, next; } a[800010]; struct hhhh { int l, r; } h[200010]; vector<pair<int, int> > v[400010]; vector<int> g[400010]; long long ans[400010]; int fa[400010], son[400010], dep[400010], top[400010], size[400010]; int fat[400010][20], head[400010], id[400010], c[400010], len[400010], n, m, tt, tot; char s[400010]; inline int rd() { int x = 0; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) ; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return x; } inline void print(long long x) { static char s[233]; if (!x) { putchar( 0 ); putchar( n ); return; } int tot = 0; for (; x; x /= 10) s[++tot] = x % 10 + 0 ; for (; tot; tot--) putchar(s[tot]); putchar( n ); } inline void add(int x, int y) { a[++tot].t = y; a[tot].next = head[x]; head[x] = tot; } namespace sam { int ch[400010][26], fa[400010], len[400010], tot, last; inline void init() { tot = last = 1; } inline int insert(int x) { int p = last, np = ++tot; len[np] = len[p] + 1; for (; p && !ch[p][x]; p = fa[p]) ch[p][x] = np; if (!p) fa[np] = 1; else { int q = ch[p][x]; if (len[q] == len[p] + 1) fa[np] = q; else { int nq = ++tot; memcpy(ch[nq], ch[q], sizeof(ch[q])); len[nq] = len[p] + 1; fa[nq] = fa[q]; fa[q] = fa[np] = nq; for (; p && ch[p][x] == q; p = fa[p]) ch[p][x] = nq; } } return last = np; } inline void build() { for (int i = 2; i <= tot; i++) add(fa[i], i); } } // namespace sam inline void dfs1(int x) { size[x] = 1; for (int i = head[x]; i; i = a[i].next) { int t = a[i].t; if (t == fa[x]) continue; dep[t] = dep[x] + 1; fa[t] = x; dfs1(t); size[x] += size[t]; if (size[t] > size[son[x]]) son[x] = t; } } inline void dfs2(int x, int tp) { top[x] = tp; if (son[x]) dfs2(son[x], tp); for (int i = head[x]; i; i = a[i].next) { int t = a[i].t; if (t == fa[x] || t == son[x]) continue; dfs2(t, t); } } struct bit { long long c[200010]; inline void add(int x, long long y) { for (; x <= n; x += ((x) & (-(x)))) c[x] += y; } inline void modify(int l, int r, long long hh) { add(l, hh); add(r + 1, -hh); } inline long long query(int x) { long long res = 0; for (; x > 0; x -= ((x) & (-(x)))) res += c[x]; return res; } inline long long query(int l, int r) { return query(r) - query(l - 1); } } c1, c2, c3, c4, c5; inline void work() { int hh = len[fa[c[1]]] + 1; for (int i = 1; i <= tt; i++) { int x = c[i]; for (int t : g[x]) { int k = t + hh - 1; c1.add(k, 1); c2.add(k, k); } } for (int i = 1; i <= tt; i++) { int x = c[i], now = len[x] - hh + 1; for (pair<int, int> hhh : v[x]) { int t = hhh.first, now = hhh.second; int l = h[t].l, r = h[t].r; ans[t] += c1.query(r - now) * now; ans[t] += c1.query(r - now + 1, r) * (r + 1) - c2.query(r - now + 1, r); ans[t] += c3.query(r) + c4.query(r) * r - c5.query(r); } for (int t : g[x]) { int k = t + hh - 1; c1.add(k, -1); c2.add(k, -k); c3.add(k + now, now); c4.modify(k, k + now - 1, 1); c5.modify(k, k + now - 1, k - 1); } } for (int i = 1; i <= tt; i++) { int x = c[i], now = len[x] - hh + 1; for (int t : g[x]) { int k = t + hh - 1; c3.add(k + now, -now); c4.modify(k, k + now - 1, -1); c5.modify(k, k + now - 1, -k + 1); c1.add(t, 1); } } for (int i = 1; i <= tt; i++) { int x = c[i], now = len[x] - hh + 1; for (pair<int, int> hhh : v[x]) { int t = hhh.first, now = hhh.second; int l = h[t].l, r = h[t].r; ans[t] -= c1.query(l - 1) * now; ans[t] -= c2.query(l - 1); } for (int t : g[x]) c1.add(t, -1), c2.add(t, now); } for (int i = 1; i <= tt; i++) for (int t : g[c[i]]) c2.add(t, -(len[c[i]] - hh + 1)); } inline int jump(int x, int y) { for (int i = 19; ~i; i--) if (len[fat[x][i]] >= y) x = fat[x][i]; return x; } inline void gao() { for (int i = 1; i <= sam::tot; i++) if (top[i] == i) { tt = 0; for (int j = i; j; j = son[j]) if (j > 1) c[++tt] = j; work(); } } int main() { scanf( %s , s + 1); n = strlen(s + 1); m = rd(); sam::init(); for (int i = n; i; i--) id[i] = sam::insert(s[i] - a ); sam::build(); for (int i = 1; i <= sam::tot; i++) len[i] = sam::len[i]; dfs1(1); dfs2(1, 1); for (int i = 1; i <= sam::tot; i++) fat[i][0] = fa[i]; for (int j = 1; j < 20; j++) for (int i = 1; i <= sam::tot; i++) fat[i][j] = fat[fat[i][j - 1]][j - 1]; for (int i = 1; i <= m; i++) h[i].l = rd(), h[i].r = rd(); for (int i = 1; i <= m; i++) { int hh = jump(id[h[i].l], h[i].r - h[i].l + 1); v[hh].push_back( pair<int, int>(i, (h[i].r - h[i].l + 1) - len[fa[top[hh]]])); for (int j = fa[top[hh]]; j; j = fa[top[j]]) v[j].push_back(pair<int, int>(i, len[j] - len[fa[top[j]]])); } for (int i = 1; i <= n; i++) for (int j = id[i]; j; j = fa[top[j]]) g[j].push_back(i); gao(); for (int i = 1; i <= m; i++) print(ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int h, m, n, vn; map<int, pair<int, int> > M; int group[222222], pos[222222], host[222222]; vector<int> v[222222], first[222222]; inline void add(int i, int x, int d) { int m = first[i].size(); while (x < m) { first[i][x] += d; x = x | (x + 1); } } inline int sum(int i, int x) { int m = first[i].size(), res = 0; while (x >= 0) { res += first[i][x]; x = (x & (x + 1)) - 1; } return res; } int main() { memset(host, -1, sizeof(host)); scanf( %d%d%d n , &h, &m, &n); memset(group, -1, sizeof(group)); for (int i = 0; i < h; ++i) if (group[i] == -1) { for (int j = i; group[j] == -1; j = (j + m) % h) { pos[j] = v[vn].size(); group[j] = vn; v[vn].push_back(j); } ++vn; } for (int i = 0; i < vn; ++i) { first[i].resize(int(v[i].size())); for (int j = 0; j < v[i].size(); ++j) add(i, j, 1); } long long res = 0; for (int i = 0; i < n; ++i) { char ch; int id, hash; scanf( %c %d , &ch, &id); if (ch == + ) { scanf( %d , &hash); int j = group[hash]; int k = pos[hash]; int l = k - 1, r = v[j].size(); int base = sum(j, k - 1); while (r - l > 1) { int mid = (l + r) / 2; if (sum(j, mid) > base) r = mid; else l = mid; } if (r < v[j].size()) { M[id] = make_pair(j, r); add(j, r, -1); res += r - k; } else { l = -1, r = k; while (r - l > 1) { int mid = (l + r) / 2; if (sum(j, mid) > 0) r = mid; else l = mid; } M[id] = make_pair(j, r); add(j, r, -1); res += v[j].size() - k + r; } } else if (ch == - ) { int j = M[id].first; int k = M[id].second; add(j, k, 1); } scanf( n ); } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, s, f; int m; long long a[2 * 100005]; long long duc = 1e10; inline long long get(long long pos) { if (pos <= s) return s - pos + 1; else { return n - pos + s + 1; } } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i + n] = a[i]; } cin >> s >> f; m = f - s; long long ans = 0; long long now = 0; for (int i = 1; i <= m; i++) { now += a[i]; } ans = now; long long opt = 1; int l = 1, r = m; while (l <= n) { now -= a[l]; now += a[r + 1]; if (ans <= now) { if (ans < now) duc = get(l + 1); else duc = min(duc, get(l + 1)); ans = now; } l++; r++; } cout << duc; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_c3fe_slot_0_ar_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_c3fe_slot_0_ar_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_W\
IDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_ar_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int nn[100000], np[100000][19], ni[100000], nl[100000], nh[100000], nc[100000], nv[100000], nd[100000], dist[100000]; vector<int> ne[100000]; int es[100000], ee[100000]; bool eb[100000]; int curp[100000]; int trav = 0; bool dfs(int n, int p) { ni[n] = nl[n] = nh[n] = trav++; nc[n] = 1; for (int i = 0; i < ne[n].size(); i++) { int other = es[ne[n][i]]; if (other == n) { other = ee[ne[n][i]]; } if (other == p) continue; if (ni[other] == -1) { if (dfs(other, n)) { eb[ne[n][i]] = true; } nc[n] += nc[other]; nl[n] = min(nl[n], nl[other]); nh[n] = max(nh[n], nh[other]); } else { nl[n] = min(nl[n], ni[other]); nh[n] = max(nh[n], ni[other]); } } if (nl[n] == ni[n] && nh[n] < ni[n] + nc[n]) { return true; } return false; } class queue_order { public: int n; bool bridge; queue_order(int a, bool b) { n = a; bridge = b; } }; struct cmp { bool operator()(queue_order* a, queue_order* b) { if (a->bridge == b->bridge) return false; if (a->bridge) return true; return false; } }; void condense() { int curnn = 0; priority_queue<queue_order*, vector<queue_order*>, cmp> pq; pq.push(new queue_order(0, false)); while (pq.size() > 0) { queue_order* o = pq.top(); pq.pop(); if (nn[o->n] != -1) continue; if (o->bridge) curnn++; nn[o->n] = curnn; for (int i = 0; i < ne[o->n].size(); i++) { int other = es[ne[o->n][i]]; if (other == o->n) { other = ee[ne[o->n][i]]; } if (nn[other] != -1) continue; pq.push(new queue_order(other, eb[ne[o->n][i]])); } } } void dfs2(int n, int p, int d) { curp[d] = n; nd[n] = d; for (int i = 0; i < 18; i++) { if (d - (1 << i) >= 0) { np[n][i] = curp[d - (1 << i)]; } else { np[n][18] = i - 1; break; } } for (int i = 0; i < ne[n].size(); i++) { int other = es[ne[n][i]]; if (other == n) { other = ee[ne[n][i]]; } if (other == p) continue; dfs2(other, n, d + 1); } } int main() { int n, m; scanf( %d %d , &n, &m); memset(nv, 0, n * sizeof(int)); memset(nn, -1, n * sizeof(int)); memset(ni, -1, n * sizeof(int)); memset(nc, 0, n * sizeof(int)); memset(eb, false, m * sizeof(bool)); for (int i = 0; i < m; i++) { scanf( %d %d , &es[i], &ee[i]); es[i]--; ee[i]--; ne[es[i]].push_back(i); ne[ee[i]].push_back(i); } dfs(0, 0); condense(); for (int i = 0; i < n; i++) { ne[i].clear(); } for (int i = 0; i < m; i++) { es[i] = nn[es[i]]; ee[i] = nn[ee[i]]; if (es[i] != ee[i]) { ne[es[i]].push_back(i); ne[ee[i]].push_back(i); } } int root = 0; queue<int> q; queue<int> d; q.push(root); nv[root] = 1; while (q.size() > 0) { int cur = q.front(); q.pop(); root = cur; for (int i = 0; i < ne[cur].size(); i++) { int other = es[ne[cur][i]]; if (other == cur) { other = ee[ne[cur][i]]; } if (nv[other] < 1) { nv[other] = 1; q.push(other); } } } q.push(root); d.push(0); nv[root] = 2; int maxd = 0; while (q.size() > 0) { int cur = q.front(); q.pop(); int curd = d.front(); d.pop(); maxd = curd; dist[curd] = cur; for (int i = 0; i < ne[cur].size(); i++) { int other = es[ne[cur][i]]; if (other == cur) { other = ee[ne[cur][i]]; } if (nv[other] < 2) { nv[other] = 2; q.push(other); d.push(curd + 1); } } } root = dist[maxd / 2]; dfs2(root, root, 0); int k, s, e, s2, e2; scanf( %d , &k); while (k-- > 0) { scanf( %d %d , &s, &e); s = s2 = nn[s - 1]; e = e2 = nn[e - 1]; while (s2 != e2) { if (nd[s2] < nd[e2]) { for (int i = np[e2][18]; i >= 0; i--) { if (nd[e2] - (1 << i) >= nd[s2]) { e2 = np[e2][i]; } } } else if (nd[s2] > nd[e2]) { for (int i = np[s2][18]; i >= 0; i--) { if (nd[s2] - (1 << i) >= nd[e2]) { s2 = np[s2][i]; } } } else { for (int i = np[s2][18]; i > 0; i--) { if (np[s2][i] != np[e2][i]) { s2 = np[s2][i]; e2 = np[e2][i]; } } s2 = np[s2][0]; e2 = np[e2][0]; } } printf( %d n , nd[s] + nd[e] - 2 * nd[s2]); } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_sclk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_sclk(l2clk ,int_sclk ,sclk ,ssclk_n ,se ,si_l ,
global_reset_n );
output int_sclk ;
output sclk ;
output ssclk_n ;
input l2clk ;
input se ;
input si_l ;
input global_reset_n ;
wire [2:0] scarry ;
wire [3:0] scount ;
wire [3:0] next_scount ;
wire net113 ;
wire net050 ;
wire scan_data_1 ;
wire scan_data_2 ;
wire scan_data_3 ;
wire scan_data_4 ;
wire scan_in ;
wire scan_out ;
wire net65 ;
bw_u1_soffr_4x I128 (
.q (scount[2] ),
.so (scan_data_3 ),
.ck (l2clk ),
.d (next_scount[2] ),
.se (se ),
.sd (scan_data_2 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I156 (
.z (scan_in ),
.a (si_l ) );
bw_u1_xor2_4x I159 (
.z (next_scount[1] ),
.a (scount[1] ),
.b (scarry[0] ) );
bw_u1_xor2_4x I160 (
.z (next_scount[2] ),
.a (scount[2] ),
.b (scarry[1] ) );
bw_u1_inv_2x I161 (
.z (next_scount[0] ),
.a (scount[0] ) );
bw_u1_xor2_4x I162 (
.z (next_scount[3] ),
.a (scount[3] ),
.b (scarry[2] ) );
bw_u1_inv_4x I163 (
.z (scarry[0] ),
.a (next_scount[0] ) );
bw_u1_nand2_4x I164 (
.z (net113 ),
.a (scount[0] ),
.b (scount[1] ) );
bw_u1_inv_8x I165 (
.z (int_sclk ),
.a (net113 ) );
bw_u1_inv_4x I166 (
.z (net65 ),
.a (scount[2] ) );
bw_u1_nor2_2x I167 (
.z (scarry[2] ),
.a (net65 ),
.b (net113 ) );
bw_u1_soffr_4x I171 (
.q (sclk ),
.so (scan_out ),
.ck (l2clk ),
.d (scarry[1] ),
.se (se ),
.sd (scan_data_4 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I21 (
.q (scount[0] ),
.so (scan_data_1 ),
.ck (l2clk ),
.d (next_scount[0] ),
.se (se ),
.sd (scan_in ),
.r_l (global_reset_n ) );
bw_u1_inv_5x I173 (
.z (ssclk_n ),
.a (scan_out ) );
bw_u1_inv_2x I179 (
.z (net050 ),
.a (int_sclk ) );
bw_u1_inv_5x I180 (
.z (scarry[1] ),
.a (net050 ) );
bw_u1_soffr_4x I125 (
.q (scount[1] ),
.so (scan_data_2 ),
.ck (l2clk ),
.d (next_scount[1] ),
.se (se ),
.sd (scan_data_1 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I127 (
.q (scount[3] ),
.so (scan_data_4 ),
.ck (l2clk ),
.d (next_scount[3] ),
.se (se ),
.sd (scan_data_3 ),
.r_l (global_reset_n ) );
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_uart_transceiver_0_1 -prefix
// DemoInterconnect_uart_transceiver_0_1_ DemoInterconnect_uart_transceiver_0_0_stub.v
// Design : DemoInterconnect_uart_transceiver_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uart_top,Vivado 2017.3" *)
module DemoInterconnect_uart_transceiver_0_1(i_Clk, i_RX_Serial, o_RX_Done, o_RX_Byte,
i_TX_Load, i_TX_Byte, o_TX_Active, o_TX_Serial, o_TX_Done)
/* synthesis syn_black_box black_box_pad_pin="i_Clk,i_RX_Serial,o_RX_Done,o_RX_Byte[7:0],i_TX_Load,i_TX_Byte[7:0],o_TX_Active,o_TX_Serial,o_TX_Done" */;
input i_Clk;
input i_RX_Serial;
output o_RX_Done;
output [7:0]o_RX_Byte;
input i_TX_Load;
input [7:0]i_TX_Byte;
output o_TX_Active;
output o_TX_Serial;
output o_TX_Done;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_M_V
`define SKY130_FD_SC_LP__O2BB2AI_M_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2ai_m (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2ai_m (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_M_V
|
#include <bits/stdc++.h> using namespace std; int main() { long s, n; cin >> n >> s; if (n >= s) cout << 1 n ; else { int div = s / n; (s % n == 0) ? cout << div << endl : cout << (div + 1) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long sz = 1e5 + 5; vector<long long> A(sz, 0), Lazy(4 * sz, 0), Tree(4 * sz, 0); long long n, m; void Built(long long Node, long long I, long long F) { if (I == F) { Tree[Node] = A[I]; return; } long long M = (I + F) / 2; Built(2 * Node + 1, I, M); Built(2 * Node + 2, M + 1, F); Tree[Node] = max(Tree[2 * Node + 1], Tree[2 * Node + 2]); return; } void Update(long long Node, long long I, long long F, long long L, long long R, long long Value) { if (Lazy[Node] != 0) { Tree[Node] += (Lazy[Node]); Lazy[2 * Node + 1] += Lazy[Node]; Lazy[2 * Node + 2] += Lazy[Node]; Lazy[Node] = 0; } if (L > F || R < I) { return; } if (I >= L && F <= R) { Tree[Node] += Value; Lazy[2 * Node + 1] += Value; Lazy[2 * Node + 2] += Value; return; } long long M = (I + F) / 2; Update(2 * Node + 1, I, M, L, R, Value); Update(2 * Node + 2, M + 1, F, L, R, Value); Tree[Node] = max(Tree[2 * Node + 1], Tree[2 * Node + 2]); return; } long long Query(long long Node, long long I, long long F, long long L, long long R) { if (Lazy[Node] != 0) { Tree[Node] += (Lazy[Node]); Lazy[2 * Node + 1] += Lazy[Node]; Lazy[2 * Node + 2] += Lazy[Node]; Lazy[Node] = 0; } if (L > F || R < I) return INT_MIN; if (I >= L && F <= R) { return Tree[Node]; } long long M = (I + F) / 2; return max(Query(2 * Node + 1, I, M, L, R), Query(2 * Node + 2, M + 1, F, L, R)); } int main() { cin >> n >> m; long long Min = INT_MAX; long long Max = INT_MIN; long long ansIn = -1; for (long long i = 0; i < n; i++) { cin >> A[i]; Min = min(Min, A[i]); Max = max(Max, A[i]); } long long ans = Max - Min; Built(0, 0, n - 1); vector<pair<long long, long long> > tmp(m); map<pair<long long, long long>, vector<long long> > mp; for (long long i = 0; i < m; i++) { cin >> tmp[i].first >> tmp[i].second; tmp[i].first = tmp[i].first - 1; tmp[i].second = tmp[i].second - 1; mp[{tmp[i].first, tmp[i].second}].push_back(i + 1); } sort(tmp.begin(), tmp.end()); long long i = 0, j = 0; multiset<pair<long long, long long> > Set; for (long long k = 0; k < n; k++) { while (!Set.empty()) { auto it = Set.begin(); auto p = *it; if (p.first < k) { Update(0, 0, n - 1, p.second, p.first, 1); Set.erase(it); } else break; } while (j < m && tmp[j].first <= k && tmp[j].second >= k) { Update(0, 0, n - 1, tmp[j].first, tmp[j].second, -1); Set.insert({tmp[j].second, tmp[j].first}); j++; } long long sze = Set.size(); long long x = Query(0, 0, n - 1, 0, n - 1); long long y = A[k] - sze; if (ans < x - y) { ans = x - y; ansIn = k; } } cout << ans << endl; if (ansIn == -1) { cout << 0; return 0; } vector<long long> Ans; for (long long i = 0; i < m; i++) { if (tmp[i].first <= ansIn && tmp[i].second >= ansIn) { Ans.push_back(mp[{tmp[i].first, tmp[i].second}] [mp[{tmp[i].first, tmp[i].second}].size() - 1]); mp[{tmp[i].first, tmp[i].second}].pop_back(); } } cout << Ans.size() << endl; for (auto i : Ans) cout << i << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; const int mod = 998244353; int n; int p[N]; namespace fft { struct num { double x, y; num() { x = y = 0; } num(double x, double y) : x(x), y(y) {} }; inline num operator+(num a, num b) { return num(a.x + b.x, a.y + b.y); } inline num operator-(num a, num b) { return num(a.x - b.x, a.y - b.y); } inline num operator*(num a, num b) { return num(a.x * b.x - a.y * b.y, a.x * b.y + a.y * b.x); } inline num conj(num a) { return num(a.x, -a.y); } int base = 1; vector<num> roots = {{0, 0}, {1, 0}}; vector<int> rev = {0, 1}; const double PI = acosl(-1.0); void ensure_base(int nbase) { if (nbase <= base) return; rev.resize(1 << nbase); for (int i = 0; i < (1 << nbase); i++) rev[i] = (rev[i >> 1] >> 1) + ((i & 1) << (nbase - 1)); roots.resize(1 << nbase); while (base < nbase) { double angle = 2 * PI / (1 << (base + 1)); for (int i = 1 << (base - 1); i < (1 << base); i++) { roots[i << 1] = roots[i]; double angle_i = angle * (2 * i + 1 - (1 << base)); roots[(i << 1) + 1] = num(cos(angle_i), sin(angle_i)); } base++; } } void fft(vector<num> &a, int n = -1) { if (n == -1) n = a.size(); assert((n & (n - 1)) == 0); int zeros = __builtin_ctz(n); ensure_base(zeros); int shift = base - zeros; for (int i = 0; i < n; i++) if (i < (rev[i] >> shift)) swap(a[i], a[rev[i] >> shift]); for (int k = 1; k < n; k <<= 1) { for (int i = 0; i < n; i += 2 * k) { for (int j = 0; j < k; j++) { num z = a[i + j + k] * roots[j + k]; a[i + j + k] = a[i + j] - z; a[i + j] = a[i + j] + z; } } } } vector<num> fa, fb; vector<int> multiply_mod(vector<int> &a, vector<int> &b, int m, int eq = 0) { int need = a.size() + b.size() - 1; int nbase = 0; while ((1 << nbase) < need) nbase++; ensure_base(nbase); int sz = 1 << nbase; if (sz > (int)fa.size()) fa.resize(sz); for (int i = 0; i < (int)a.size(); i++) { int x = (a[i] % m + m) % m; fa[i] = num(x & ((1 << 15) - 1), x >> 15); } fill(fa.begin() + a.size(), fa.begin() + sz, num{0, 0}); fft(fa, sz); if (sz > (int)fb.size()) fb.resize(sz); if (eq) copy(fa.begin(), fa.begin() + sz, fb.begin()); else { for (int i = 0; i < (int)b.size(); i++) { int x = (b[i] % m + m) % m; fb[i] = num(x & ((1 << 15) - 1), x >> 15); } fill(fb.begin() + b.size(), fb.begin() + sz, num{0, 0}); fft(fb, sz); } double ratio = 0.25 / sz; num r2(0, -1), r3(ratio, 0), r4(0, -ratio), r5(0, 1); for (int i = 0; i <= (sz >> 1); i++) { int j = (sz - i) & (sz - 1); num a1 = (fa[i] + conj(fa[j])); num a2 = (fa[i] - conj(fa[j])) * r2; num b1 = (fb[i] + conj(fb[j])) * r3; num b2 = (fb[i] - conj(fb[j])) * r4; if (i != j) { num c1 = (fa[j] + conj(fa[i])); num c2 = (fa[j] - conj(fa[i])) * r2; num d1 = (fb[j] + conj(fb[i])) * r3; num d2 = (fb[j] - conj(fb[i])) * r4; fa[i] = c1 * d1 + c2 * d2 * r5; fb[i] = c1 * d2 + c2 * d1; } fa[j] = a1 * b1 + a2 * b2 * r5; fb[j] = a1 * b2 + a2 * b1; } fft(fa, sz); fft(fb, sz); vector<int> res(need); for (int i = 0; i < need; i++) { long long aa = fa[i].x + 0.5; long long bb = fb[i].x + 0.5; long long cc = fa[i].y + 0.5; res[i] = (aa + ((bb % m) << 15) + ((cc % m) << 30)) % m; } return res; } }; // namespace fft struct pol { vector<int> a; pol() {} pol(const pol &oth) { a = oth.a; } bool operator<(const pol &oth) const { return a.size() <= oth.a.size(); } }; set<pol> st; int main() { cin >> n; map<int, int> rep; for (int i = 0; i < n; i++) { scanf( %d , &p[i]); rep[p[i]]++; } for (map<int, int>::iterator it = rep.begin(); it != rep.end(); it++) { int sz = it->second; pol temp; for (int i = 0; i <= sz; i++) { temp.a.push_back(1); } st.insert(temp); } while (st.size() > 1) { pol x = *st.begin(); st.erase(st.begin()); pol y = *st.begin(); st.erase(st.begin()); x.a = fft::multiply_mod(x.a, y.a, mod); st.insert(x); } long long res = 0; pol x = *st.begin(); if (x.a.size() > n / 2) res = x.a[n / 2]; cout << res << endl; return 0; } |
// ************************Declaration*************************************** //
// File name: encodeBcd10to4.v //
// Author: firedom //
// //
// Abstract: //
// encoding 10-line Decimal 4-line BCD for verilog. //
// [0:8]in: 9-port select input. //
// [0:3]out: 4-port select output. //
// //
// Reference: //
// http://www.ti.com/lit/ds/symlink/sn74148.pdf //
// //
// Modification history:(including time, version, author and abstract) //
// 2016-08-31 10:55 version 0.1 //
// 2016-08-31 21:50 version 0.2 dev.board has broken, not unit test. //
// ************************Declaration*************************************** //
module encodeBcd10to4(in, out);
input [0:8]in;
output [0:3]out;
wire and0out, and1out, and2out, and3out, and4out, and5out, and6out, and7out, and8out, and9out, and10out, and11out, and12out, nor0out;
and
andGate0(and0out, ~in[0], in[1], in[3], in[5], nor0out),
andGate1(and1out, ~in[2], in[3], in[5], nor0out),
andGate2(and2out, ~in[4], in[5], nor0out),
andGate3(and3out, ~in[6], nor0out),
andGate4(and4out, ~in[8]),
andGate5(and5out, ~in[1], in[3], in[4], nor0out),
andGate6(and6out, ~in[2], in[3], in[4], nor0out),
andGate7(and7out, ~in[5], nor0out),
andGate8(and8out, ~in[6], nor0out),
andGate9(and9out, ~in[3], nor0out),
andGate10(and10out, ~in[4], nor0out),
andGate11(and11out, ~in[5], nor0out),
andGate12(and12out, ~in[6], nor0out);
nor
norGate0(nor0out, ~in[7], ~in[8]),
norGate1(out[0], and0out, and1out, and2out, and3out, and4out),
norGate2(out[1], and5out, and6out, and7out, and8out),
norGate3(out[2], and9out, and10out, and11out, and12out);
assign out[3] = nor0out;
endmodule |
#include <bits/stdc++.h> using namespace std; struct Q { int a, b, c, d; Q(int x, int y, int z, int w) : a(x), b(y), c(z), d(w) {} }; pair<int, int> query(Q z) { int u, v; printf( %d%d%d%d n , z.a, z.b, z.c, z.d); fflush(stdout); scanf( %d%d , &u, &v); return make_pair(u, v); } pair<int, int> dist(Q e, Q f) { int bulls = 0, cows = 0; if (e.a == f.a) bulls++; if (e.b == f.b) bulls++; if (e.c == f.c) bulls++; if (e.d == f.d) bulls++; if ((e.a == f.a) || (e.a == f.b) || (e.a == f.c) || (e.a == f.d)) cows++; if ((e.b == f.a) || (e.b == f.b) || (e.b == f.c) || (e.b == f.d)) cows++; if ((e.c == f.a) || (e.c == f.b) || (e.c == f.c) || (e.c == f.d)) cows++; if ((e.d == f.a) || (e.d == f.b) || (e.d == f.c) || (e.d == f.d)) cows++; return make_pair(bulls, cows - bulls); } int main() { vector<Q> X; for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) if (i - j) { for (int k = 0; k < 10; ++k) if ((i - k) && (j - k)) { for (int l = 0; l < 10; ++l) if ((i - l) && (j - l) && (k - l)) { Q h(i, j, k, l); X.push_back(h); } } } int bulls = 0, cows = 0; while (bulls < 4) { pair<int, int> Z = query(X[0]); bulls = Z.first; cows = Z.second; vector<Q> Y; Q V = X[0]; for (int i = 0; i < X.size(); ++i) { pair<int, int> T = dist(V, X[i]); if (T.first == bulls && T.second == cows) Y.push_back(X[i]); } X = Y; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_TB_V
`define SKY130_FD_SC_LP__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_PP_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO.v
// Version : 2.3
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//-- The module designed to operate with 32 bit and 64 bit interfaces.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
)(
input user_clk,
input user_reset,
input user_lnk_up,
// AXIS
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [STRB_WIDTH-1:0] s_axis_tx_tstrb,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [STRB_WIDTH-1:0] m_axis_rx_tstrb,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
); // synthesis syn_hier = "hard"
// Local wires
wire req_compl;
wire compl_done;
wire pio_reset_n = user_lnk_up && !user_reset;
//
// PIO instance
//
PIO_EP #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) PIO_EP (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tstrb( s_axis_tx_tstrb ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tstrb( m_axis_rx_tstrb ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.req_compl_o(req_compl), // O
.compl_done_o(compl_done), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable ( cfg_bus_mstr_enable ) // I
);
//
// Turn-Off controller
//
PIO_TO_CTRL PIO_TO (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl_i( req_compl ), // I
.compl_done_i( compl_done ), // I
.cfg_to_turnoff( cfg_to_turnoff ), // I
.cfg_turnoff_ok( cfg_turnoff_ok ) // O
);
endmodule // PIO
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_blk_mem_gen_0_0 (
clka,
rsta,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input wire rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [7 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [63 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [63 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("OpenSSD2_blk_mem_gen_0_0.mif"),
.C_INIT_FILE("NONE"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(1),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(64),
.C_READ_WIDTH_A(64),
.C_WRITE_DEPTH_A(256),
.C_READ_DEPTH_A(256),
.C_ADDRA_WIDTH(8),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(64),
.C_READ_WIDTH_B(64),
.C_WRITE_DEPTH_B(256),
.C_READ_DEPTH_B(256),
.C_ADDRB_WIDTH(8),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.700549 mW")
) inst (
.clka(clka),
.rsta(rsta),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(8'B0),
.dinb(64'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(64'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
module SPI_AD(
input SPI_CLK,
input New_Word,
input [12:0] Addr,
input [7:0] Data,
output reg [7:0] q,
input RW, //1 Write; 0 :read
output reg SPI_CS,
inout reg SPI_Data,
output reg Over
);
reg [15:0] CMD;
reg [7:0] Wr_Data;
reg [7:0] SPI_Counter;
always @(negedge SPI_CLK or posedge New_Word ) begin
if(New_Word) begin
CMD <={RW,1'b0,1'b0,Addr[12:0]};
Wr_Data <= Data;
SPI_Counter <= 8'd0;
Over <= 1'b0;
SPI_CS <= 1'b1;
SPI_Data <= 1'bz;
end
else begin
if(SPI_Counter <8'd16) begin // first CMD
SPI_Counter <= SPI_Counter + 1'b1;
SPI_Data <= CMD[15];
CMD <= CMD <<1;
SPI_CS <= 1'b0;
q <= 8'd00;
end
else if(SPI_Counter <8'd24) begin //Data
SPI_Counter <= SPI_Counter + 1'b1;
if(RW) begin
q <= {q[6:0],SPI_Data};
SPI_Data <= 1'bz;
end
else begin
SPI_Data <= Wr_Data[7];
Wr_Data <= Wr_Data <<1;
end
SPI_CS <= 1'b0;
end
else if(SPI_Counter <8'd25) begin //Data
SPI_Counter <= SPI_Counter + 1'b1;
if(RW) begin
q <= {q[6:0],SPI_Data};
SPI_Data <= 1'bz;
end
SPI_CS <= 1'b1;
end
else if(SPI_Counter <8'd32) begin // interval
SPI_Counter <= SPI_Counter + 1'b1;
SPI_CS <= 1'b1;
SPI_Data <= 1'bz;
Over <= 1'b1;
end
else begin
SPI_Data <= 1'bz;
SPI_CS <= 1'b1;
Over <= 1'b1;
end
end
end
endmodule
|
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
// $Revision: #7 $
// $Date: 2010/04/27 $
// $Author: jyeap $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
// -----------------------------------------------
(* ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \" set_false_path -to [get_pins -compatibility_mode -nocase *altera_tse_reset_synchronizer_chain*|aclr]; set_false_path -to [get_pins -compatibility_mode -nocase *altera_tse_reset_synchronizer_chain*|clrn] \"" *) (*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
end
else begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
end
end
assign reset_out = altera_tse_reset_synchronizer_chain[0];
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
end
assign reset_out = altera_tse_reset_synchronizer_chain[0];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int pri[200050]; int que[200050]; int ans[200050]; int l[200050]; int r[200050]; int main() { int n; while (scanf( %d , &n) != EOF) { for (int i = 1; i <= n; i++) { scanf( %d , &pri[i]); ans[i] = 0; l[i] = r[i] = 1; } int s = 1, e = 0; for (int i = 1; i <= n; i++) { while (s <= e && pri[que[e]] >= pri[i]) { l[i] = i - que[e] + l[que[e]]; e--; } que[++e] = i; } s = 1, e = 0; for (int i = n; i >= 1; i--) { while (s <= e && pri[que[e]] >= pri[i]) { r[i] = r[que[e]] + que[e] - i; e--; } que[++e] = i; } for (int i = 1; i <= n; i++) { ans[l[i]] = max(ans[l[i]], pri[i]); ans[r[i]] = max(ans[r[i]], pri[i]); ans[r[i] + l[i] - 1] = max(ans[r[i] + l[i] - 1], pri[i]); } for (int i = n - 1; i >= 1; i--) { ans[i] = max(ans[i], ans[i + 1]); } for (int i = 1; i <= n; i++) if (i == 1) printf( %d , ans[i]); else printf( %d , ans[i]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f, mod = 1000000007; const double pi = 3.1415926535897932, eps = 1e-6; void chmax(int &x, int y) { if (x < y) x = y; } void chmin(int &x, int y) { if (x > y) x = y; } int B = 333; int n, top = 101000, cnt; string s[100005]; int val[300005], ex[300005]; long long sum[444][5]; int num[444], rea[100005]; map<int, int> mp; void calc(int x) { int lb = x * B, rb = (x + 1) * B; int now_cnt = 0; for (int(i) = (0); (i) <= (4); (i)++) sum[x][i] = 0; num[x] = 0; for (int(i) = (lb); (i) < (rb); (i)++) { if (ex[i]) { sum[x][now_cnt % 5] += rea[i]; now_cnt++; } } num[x] = now_cnt; } int main() { ios::sync_with_stdio(false); cin >> n; for (int(i) = (1); (i) <= (n); (i)++) { cin >> s[i]; if (s[i] != sum ) { cin >> val[i]; mp[val[i]] = 0; } } for (map<int, int>::iterator it = mp.begin(); it != mp.end(); it++) { rea[cnt] = it->first; it->second = cnt++; } for (int(i) = (1); (i) <= (n); (i)++) { if (s[i] == sum ) { int Top = top / B + 1; int now_cnt = 0; long long ans = 0; for (int(i) = (0); (i) <= (Top); (i)++) { ans += sum[i][(2 - now_cnt + 555555555) % 5]; now_cnt += num[i]; } cout << ans << n ; } else { val[i] = mp[val[i]]; if (s[i] == add ) { int v = val[i]; ex[v] = 1; int at = v / B; calc(at); } else { int v = val[i]; ex[v] = 0; int at = v / B; calc(at); } } } } |
/*******************************************************
* File Name : hdl/ks13.v
* Module Name : Karatsuba Multiplier
* Author : Chester Rebeiro
* Institute : Indian Institute of Technology, Madras
* Creation Time :
* Comment : Automatically generated from ks.c
********************************************************/
//`include "ks7.v"
//`include "ks6.v"
module Sks13(a, b, d);
input wire [12:0] a;
input wire [12:0] b;
output wire [24:0] d;
wire [10:0] m1;
wire [12:0] m2;
wire [12:0] m3;
wire [6:0] ahl;
wire [6:0] bhl;
Sks7 ksm1(a[6:0], b[6:0], m2);
//Sks6 ksm2(a[12:7], b[12:7], m1);
assign m1 = a[12:7] * b[12:7];
assign ahl[5:0] = a[12:7] ^ a[5:0];
assign ahl[6] = a[6];
assign bhl[5:0] = b[12:7] ^ b[5:0];
assign bhl[6] = b[6];
Sks7 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[08] = m2[08] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[09] = m2[09] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[10] = m2[10] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[11] = m2[11] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[12] = m2[12] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[13] = m1[06] ^ m2[06] ^ m3[06];
assign d[14] = m1[07] ^ m2[07] ^ m3[07] ^ m1[00];
assign d[15] = m1[08] ^ m2[08] ^ m3[08] ^ m1[01];
assign d[16] = m1[09] ^ m2[09] ^ m3[09] ^ m1[02];
assign d[17] = m1[10] ^ m2[10] ^ m3[10] ^ m1[03];
assign d[18] = m2[11] ^ m3[11] ^ m1[04];
assign d[19] = m2[12] ^ m3[12] ^ m1[05];
assign d[20] = m1[06];
assign d[21] = m1[07];
assign d[22] = m1[08];
assign d[23] = m1[09];
assign d[24] = m1[10];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_4_V
`define SKY130_FD_SC_HS__O21AI_4_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; scanf( %lld , &n); printf( 1 ); if ((n - 1) % 3 == 1) printf( 2 %lld , n - 3); else printf( 1 %lld , n - 2); return 0; } |
// wasca_mm_interconnect_0_avalon_st_adapter_005.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0_avalon_st_adapter_005 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
wasca_mm_interconnect_0_avalon_st_adapter_005_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Include definition of the control signals
`include "control.h"
// Behavioral model for the register file
module RegFileWW(rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
if(rd1en && (rd1addr!==5'dx) && (rd1addr!==5'dz))
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data=128'dz;
end
if(rd2en && (rd2addr!==5'dx) && (rd2addr!==5'dz))
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data=128'dz;
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_timer_us (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hFFFFFFFE;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 65534;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 65535;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:52:23 04/08/2015
// Design Name: factorFinder
// Module Name: S:/a/asw011/public/PrimeFactorization/test_factorFinder.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: factorFinder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_factorFinder;
// Inputs
reg [0:31] product;
reg clk;
// Outputs
wire [0:15] factorA;
wire [0:15] factorB;
wire isDone;
// Instantiate the Unit Under Test (UUT)
factorFinder uut (
.product(product),
.clk(clk),
.factorA(factorA),
.factorB(factorB),
.isDone(isDone)
);
always #5 clk = ~clk;
initial begin
// Initialize Inputs
product = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxint = 999999999; string s; int cnt[30]; int k; int main() { int i; while (cin >> s) { cin >> k; int l = s.length(); if (l <= k) { printf( 0 n ); printf( n ); continue; } for (i = 0; i < l; i++) { cnt[s[i] - a ]++; } int Min, u; while (1) { if (k == 0) break; Min = maxint; u = -1; for (i = 0; i < 26; i++) { if (cnt[i] > 0 && cnt[i] < Min) { Min = cnt[i]; u = i; } } if (Min > k) { k = 0; cnt[u] -= k; } else { cnt[u] = 0; k -= Min; } } int ans = 0; for (i = 0; i < 26; i++) { if (cnt[i] > 0) ans++; } printf( %d n , ans); for (i = 0; i < l; i++) { if (cnt[s[i] - a ] > 0) printf( %c , s[i]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << x; } void __print(const char *x) { cerr << x; } void __print(const string &x) { cerr << x; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) { cerr << (f++ ? , : ); __print(i); } cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) { cerr << , ; } _print(v...); } string go(long long i, long long n, long long dist, string nw, long long k, string ori) { ; if (dist > k) { return ; } if (nw.substr(0, i) < ori.substr(0, i)) { return ; } if (i >= n) { return nw; } for (char val = 0 ; val <= 9 ; ++val) { nw[i] = val; bool found = false; for (long long j = 0; j < i; ++j) { if (nw[j] == val) { found = true; break; } } string chk = go(i + 1, n, dist + (found == false), nw, k, ori); if ((long long)chk.size()) { return chk; } } return ; } void solve() { long long n, k; cin >> n >> k; string s = to_string(n); long long dist = 0; map<char, long long> g; for (auto ch : s) { g[ch]++; } string ans = go(0, (long long)s.size(), 0, string((long long)s.size(), 0 ), k, s); cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } inline long long toLongLong(string s) { long long v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } inline vector<char> toVC(string s) { vector<char> data(s.begin(), s.end()); return data; } vector<string> SPRIT(const string &s, const string &delim) { vector<string> result; string::size_type pos = 0; while (pos != string::npos) { string::size_type p = s.find(delim, pos); if (p == string::npos) { result.push_back(s.substr(pos)); break; } else { result.push_back(s.substr(pos, p - pos)); } pos = p + delim.size(); } return result; } string TRIM(const string &str, const char *trimCharacterList = t v r n ) { string result; string::size_type left = str.find_first_not_of(trimCharacterList); if (left != string::npos) { string::size_type right = str.find_last_not_of(trimCharacterList); result = str.substr(left, right - left + 1); } return result; } string REPLACE_STRING(const string source, const string find, const string alt) { string result = source; string::size_type pos = 0; while (pos = result.find(find, pos), pos != string::npos) { result.replace(pos, find.length(), alt); pos += alt.length(); } return result; } template <typename T> bool VECTOR_EXISTS(vector<T> vec, T data) { auto itr = std::find(vec.begin(), vec.end(), data); size_t index = distance(vec.begin(), itr); if (index != vec.size()) return true; else return false; } template <typename T> void VECTOR_REMOVE_VALUE_ALL(vector<T> &vec, T data) { vec.erase(remove(vec.begin(), vec.end(), data), vec.end()); } template <typename T> vector<T> VECTOR_REMOVE_VALUE_ALL_FAST(vector<T> vec, T data) { vector<T> vec2; for (auto &x : vec) if (x != data) vec2.push_back(x); return vec2; } bool REG_MATCH(string const &text, regex const &re) { bool result = regex_match(text, re); return result; } bool REG_MATCH(string const &text, smatch &match, regex const &re) { bool result = regex_match(text, match, re); return result; } smatch REG_SEARCH(string const &text, regex const &re) { smatch m; regex_search(text, m, re); return m; } vector<smatch> REG_ALL_SEARCH(string const &text, regex const &re) { vector<smatch> matchs; sregex_iterator iter(text.cbegin(), text.cend(), re); sregex_iterator end; for (; iter != end; iter++) matchs.push_back(*iter); return matchs; } string REG_REPLACE(string const &text, regex const &re, string const &replace) { string result = regex_replace(text, re, replace, regex_constants::format_first_only); return result; } string REG_ALL_REPLACE(string const &text, regex const &re, string const &replace) { string result = regex_replace(text, re, replace); return result; } template <typename T> vector<T> COMPRESS(vector<T> v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); return v; } template <typename T> pair<map<T, int>, map<int, T>> MAPPING(const vector<T> v) { map<T, int> zip; map<int, T> unzip; for (int i = 0; i < v.size(); i++) zip[v[i]] = i; for (int i = 0; i < v.size(); i++) unzip[i] = v[i]; return make_pair(zip, unzip); } template <typename T> vector<pair<T, int>> RUN_LENGTH(const vector<T> &v) { vector<pair<T, int>> ret; int len = v.size(); for (int i = 0, j = 0; i < len; i = j) { while (j < len && v[i] == v[j]) j++; ret.push_back(make_pair(v[i], j - i)); } return ret; } template <typename T, typename U, typename V, typename W> auto operator+(const std::pair<T, U> &l, const std::pair<V, W> &r) -> std::pair<decltype(l.first + r.first), decltype(l.second + r.second)> { return {l.first + r.first, l.second + r.second}; } template <typename T, typename U, typename V, typename W> auto operator-(const std::pair<T, U> &l, const std::pair<V, W> &r) -> std::pair<decltype(l.first - r.first), decltype(l.second - r.second)> { return {l.first - r.first, l.second - r.second}; } double ceil_n(double dIn, long long nLen) { double dOut; dOut = dIn * pow(10.0, nLen); dOut = (double)(long long)(dOut + 0.9); return dOut * pow(10.0, -nLen); } double floor_n(double dIn, long long nLen) { double dOut; dOut = dIn * pow(10.0, nLen); dOut = (double)(long long)(dOut); return dOut * pow(10.0, -nLen); } double round_n(double dIn, long long nLen) { double dOut; dOut = dIn * pow(10.0, nLen); dOut = (double)(long long)(dOut + 0.5); return dOut * pow(10.0, -nLen); } int take_a_n(long long num, int n) { string str = toString(num); return str[str.length() - n] - 0 ; } int bitcount32(int bits) { bits = (bits & 0x55555555) + (bits >> 1 & 0x55555555); bits = (bits & 0x33333333) + (bits >> 2 & 0x33333333); bits = (bits & 0x0f0f0f0f) + (bits >> 4 & 0x0f0f0f0f); bits = (bits & 0x00ff00ff) + (bits >> 8 & 0x00ff00ff); return (bits & 0x0000ffff) + (bits >> 16 & 0x0000ffff); } long long bitcount64(long long bits) { bits = (bits & 0x5555555555555555) + (bits >> 1 & 0x5555555555555555); bits = (bits & 0x3333333333333333) + (bits >> 2 & 0x3333333333333333); bits = (bits & 0x0f0f0f0f0f0f0f0f) + (bits >> 4 & 0x0f0f0f0f0f0f0f0f); bits = (bits & 0x00ff00ff00ff00ff) + (bits >> 8 & 0x00ff00ff00ff00ff); bits = (bits & 0x0000ffff0000ffff) + (bits >> 16 & 0x0000ffff0000ffff); return (bits & 0x00000000ffffffff) + (bits >> 32 & 0x00000000ffffffff); } template <class T1, class T2> inline bool chmin(T1 &a, T2 b) { if (a > b) { a = b; return true; } return false; } template <class T1, class T2> inline bool chmax(T1 &a, T2 b) { if (a < b) { a = b; return true; } return false; } template <typename T1, typename T2> istream &operator>>(istream &in, pair<T1, T2> &p) { in >> p.first >> p.second; return in; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (auto &x : v) in >> x; return in; } template <typename T1, typename T2> ostream &operator<<(ostream &out, const std::pair<T1, T2> &p) { out << [ << p.first << , << p.second << ] << n ; return out; } const double EPS = 1e-10; const double PI = acos(-1.0); const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; template <typename T> inline bool BETWEEN(const T aim, const T min, const T max) { if (min <= aim && aim <= max) { return true; } else { return false; } } template <typename T1, typename T2> inline bool IS_OUT(const T1 toY, const T1 toX, const T2 H, const T2 W) { return (toY < 0 || toY >= H || toX < 0 || toX >= W); } template <class T> inline T SQR(const T x) { return x * x; } template <class T1, class T2> inline T1 POW(const T1 x, const T2 y) { if (!y) return 1; else if ((y & 1) == 0) { return SQR(POW(x, y >> 1)); } else return POW(x, y ^ 1) * x; } template <typename T> constexpr T ABS(T x) { return x < 0 ? -x : x; } template <class Iter> bool next_partial_permutation(Iter first, Iter middle, Iter last) { reverse(middle, last); return next_permutation(first, last); } template <class Iter> bool next_combination(Iter first1, Iter last1, Iter first2, Iter last2) { if ((first1 == last1) || (first2 == last2)) { return false; } Iter m1 = last1; Iter m2 = last2; --m2; while (--m1 != first1 && !(*m1 < *m2)) { } bool result = (m1 == first1) && !(*first1 < *m2); if (!result) { while (first2 != m2 && !(*m1 < *first2)) { ++first2; } first1 = m1; std::iter_swap(first1, first2); ++first1; ++first2; } if ((first1 != last1) && (first2 != last2)) { m1 = last1; m2 = first2; while ((m1 != first1) && (m2 != last2)) { std::iter_swap(--m1, m2); ++m2; } std::reverse(first1, m1); std::reverse(first1, last1); std::reverse(m2, last2); std::reverse(first2, last2); } return !result; } template <typename T> constexpr bool ODD(T x) { return x % 2 != 0; } template <typename T> constexpr bool EVEN(T x) { return x % 2 == 0; } template <class T> inline T GCD(const T x, const T y) { if (x < 0) return GCD(-x, y); if (y < 0) return GCD(x, -y); return (!y) ? x : GCD(y, x % y); } template <class T> inline T LCM(const T x, const T y) { if (x < 0) return LCM(-x, y); if (y < 0) return LCM(x, -y); return x * (y / GCD(x, y)); } template <class T> inline T EXTGCD(const T a, const T b, T &x, T &y) { if (a < 0) { T d = EXTGCD(-a, b, x, y); x = -x; return d; } if (b < 0) { T d = EXTGCD(a, -b, x, y); y = -y; return d; } if (!b) { x = 1; y = 0; return a; } else { T d = EXTGCD(b, a % b, x, y); T t = x; x = y; y = t - (a / b) * y; return d; } } template <class T> inline T INV_MOD(const T a, const T m) { T x, y; EXTGCD(a, m, x, y); return (x + m) % m; } template <class T> inline bool ISPRIME(const T x) { if (x <= 1) return false; for (T i = 2; i * i <= x; i++) if (x % i == 0) return false; return true; } template <class T> vector<bool> ERATOSTHENES(const T n) { vector<bool> arr(n + 1, true); arr[0] = arr[1] = false; for (T i = 2; i * i <= n; i++) { if (arr[i]) { for (T j = i * 2LL; j <= n; j += i) { arr[j] = false; } } } return arr; } template <typename T> vector<bool> ERATOSTHENES(const T a, const T b) { vector<bool> small = ERATOSTHENES(b); vector<bool> prime(b - a, true); for (T i = 2; i * i <= b; i++) { if (small[i]) { for (T j = max(2LL, (a + i - 1) / i) * i; j < b; j += i) { prime[j - a] = false; } } } return prime; } template <typename T> vector<T> DIVISOR(T n) { vector<T> v; for (T i = 1; i * i <= n; ++i) { if (n % i == 0) { v.push_back(i); if (i != n / i) { v.push_back(n / i); } } } sort(v.begin(), v.end()); return v; } template <typename T> vector<vector<T>> DIVISOR_ALL(T n) { vector<vector<T>> res(n + 1); for (T i = 1; i <= n; i++) { for (T j = i; j <= n; j += i) { res[j].push_back(i); } } return res; } template <typename T> vector<pair<T, T>> FACTORIZATION(T x) { vector<pair<T, long long>> ans; for (T i = 2; i * i <= x; i++) { if (x % i == 0) { T count = 0; while (x % i == 0) { count++; x /= i; } ans.push_back(make_pair(i, count)); } } if (x != 1) ans.push_back(make_pair(x, 1)); return ans; } long long POW_MOD(long long N, long long P, long long M) { long long ret = 1; while (P > 0) { if (P & 1LL) ret = (ret * N) % M; N = (N * N) % M; P >>= 1LL; } return ret; } template <typename T> inline T NCR(T n, T r) { if (r > n - r) r = n - r; T ans = 1LL; for (T i = 0; i < r; i++) { ans = ans * (n - i) / (i + 1); } return ans; } long long NCR_MOD(long long n, long long r, long long M) { if (r > n - r) return NCR_MOD(n, n - r, M); long long numerator = 1LL; long long denominator = 1LL; for (long long i = 0; i < r; i++) { numerator *= (n - i); numerator %= M; denominator *= (i + 1); denominator %= M; } return numerator * POW_MOD(denominator, M - 2, M) % M; } int main() { int T; cin >> T; while (T--) { long long n, m, k; cin >> n >> m >> k; vector<long long> h(n); for (int i = (0); i < (n); ++i) scanf( %lld , &h[i]); bool good = true; for (int i = 0; i < n - 1; i++) { long long as = max(0LL, h[i + 1] - k); if (h[i] >= as) { m += h[i] - as; continue; } m -= (as - h[i]); if (m < 0) { good = false; } } if (good) printf( YES n ); else printf( NO n ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3_1_V
`define SKY130_FD_SC_HDLL__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_1_V
`define SKY130_FD_SC_LP__DLXBP_1_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a[100], b[100]; scanf( %d %d , &n, &m), a[0] = n - 2, b[0] = m - 2; for (int i = 1; i < max(n, m); i++) a[i] = b[i] = 2; if (n == 1) a[0] = 1; else if (n == 2) a[0] = 3, a[1] = 4; if (m == 1) b[0] = 1; else if (m == 2) b[0] = 3, b[1] = 4; for (int i = 0; i < n; i++, putchar(10)) for (int j = 0; j < m; j++) printf( %d , a[i] * b[j]); return 0; } |
#include <bits/stdc++.h> int CH, NEG; template <typename TP> inline void read(TP& ret) { ret = NEG = 0; while (CH = getchar(), CH < ! ) ; if (CH == - ) NEG = true, CH = getchar(); while (ret = ret * 10 + CH - 0 , CH = getchar(), CH > ! ) ; if (NEG) ret = -ret; } using namespace std; int n, K; struct node { int sz; int L[11LL], R[11LL]; bool operator<(const node& B) const { int i; for (i = (1); i <= (K); i++) if (R[i] > B.L[i]) break; return i > K; } bool operator>(const node& B) const { int i; for (i = (1); i <= (K); i++) if (L[i] < B.R[i]) break; return i > K; } } tmp; int tot = 0; set<node> S; set<node>::iterator it1, it2; void merge(node& A, const node& B) { A.sz += B.sz; int i; for (i = (1); i <= (K); i++) A.L[i] = std::min(A.L[i], B.L[i]), A.R[i] = std::max(A.R[i], B.R[i]); } int Add() { int i; tmp.sz = 1; for (i = (1); i <= (K); i++) read(tmp.L[i]), tmp.R[i] = tmp.L[i]; if (S.empty()) { S.insert(tmp); return 1; } it1 = S.lower_bound(tmp); while (true) { if (it1 == S.end()) break; if (*it1 > tmp) break; it2 = it1; it1++; merge(tmp, *it2); S.erase(it2); } S.insert(tmp); it1 = S.end(); it1--; return it1->sz; } int main() { S.clear(); int i; read(n), read(K); for (i = (1); i <= (n); i++) { printf( %d n , Add()); } END: getchar(), getchar(); return 0; } |
#include <bits/stdc++.h> using namespace std; int row[1010]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); memset(row, 0x3f3f3f3f, sizeof row); long long ans = 0; for (int i = (0); i < (n); ++i) { int r, c; scanf( %d %d , &r, &c); row[r] = min(c, row[r]); } for (int i = 1; i <= m; ++i) ans += ((row[i] == 0x3f3f3f3f) ? 0 : row[i]); cout << min(ans, (long long)k) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k = 0, dem = 0, s; char c[1000001]; int e[100001]; deque<int> pq; int main() { cin >> n; ; for (int i = 1; i <= n; ++i) { cin >> c[i]; if (c[i] == 8 ) { pq.push_back(i); dem++; } } s = n - 11; s /= 2; for (int i = 1; i <= n; i++) { if (s == 0 || dem == 0) break; if (c[i] == 8 ) { pq.pop_front(); dem--; s--; } } if (dem == 0 || pq.front() > n - 10) cout << NO ; else cout << YES ; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 5; long double x[maxN], y[maxN], r[maxN], val[maxN]; long double f(long double xx, long double yy) { for (int i = 0; i < 3; ++i) { val[i] = sqrt((x[i] - xx) * (x[i] - xx) + (y[i] - yy) * (y[i] - yy)) / r[i]; } val[3] = val[0]; long double answer = 0; for (int i = 0; i < 3; ++i) answer += (val[i] - val[i + 1]) * (val[i] - val[i + 1]); return answer; } int main() { for (int i = 0; i < 3; ++i) cin >> x[i] >> y[i] >> r[i]; long double pX = (x[0] + x[1] + x[2]) / 3., pY = (y[0] + y[1] + y[2]) / 3.; long double qq = 1.; while (qq > 1e-5) { if (f(pX - qq, pY) < f(pX, pY)) pX -= qq; else if (f(pX + qq, pY) < f(pX, pY)) pX += qq; else if (f(pX, pY - qq) < f(pX, pY)) pY -= qq; else if (f(pX, pY + qq) < f(pX, pY)) pY += qq; else qq *= 0.777777777; } if (f(pX, pY) > 1e-5) return 0; cout << fixed << setprecision(15) << pX << << pY << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_SYMBOL_V
`define SKY130_FD_SC_LS__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string a; cin >> a; char vowels[5] = { a , e , i , o , u }; for (int i = 0; i < a.size() - 1; ++i) { bool flag = false; for (int k = 0; k < 5; ++k) { if (a[i] == vowels[k]) { flag = true; break; } } if (a[i] == n ) flag = true; if (flag) { continue; } for (int k = 0; k < 5; ++k) { if (a[i + 1] == vowels[k]) { flag = true; break; } } if (flag == false) { cout << NO << endl; return 0; } } int n = a.size(); bool flag = false; for (int k = 0; k < 5; ++k) { if (a[n - 1] == vowels[k]) { flag = true; break; } } if (a[n - 1] == n ) flag = true; if (flag == true) cout << YES << endl; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, q; int matrix[100][100]; int ans[10000]; void fill() { for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { matrix[i][j] = i * m + j; } } } void solve_1(int i) { int temp; temp = matrix[i][m - 1]; matrix[i][m - 1] = matrix[i][0]; for (int j = m - 2; j >= 0; --j) { int new_temp = matrix[i][j]; matrix[i][j] = temp; temp = new_temp; } } void solve_2(int j) { int temp; temp = matrix[n - 1][j]; matrix[n - 1][j] = matrix[0][j]; for (int i = n - 2; i >= 0; --i) { int new_temp = matrix[i][j]; matrix[i][j] = temp; temp = new_temp; } } int main(int argc, char *argv[]) { memset(ans, 0, sizeof(ans)); scanf( %d%d%d , &n, &m, &q); fill(); while (q--) { int t; scanf( %d , &t); if (t == 1) { int n_i; scanf( %d , &n_i); n_i--; solve_1(n_i); } else if (t == 2) { int m_i; scanf( %d , &m_i); m_i--; solve_2(m_i); } else { int r, c, x; scanf( %d%d%d , &r, &c, &x); r--; c--; ans[matrix[r][c]] = x; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { printf( %d , ans[i * m + j]); } puts( ); } return 0; } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.