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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_SYMBOL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double w, h, d; const double pi = acos(-1); int main() { scanf( %lf%lf%lf , &w, &h, &d); if (d >= 90) d = 180 - d; if (w < h) swap(w, h); if (d == 0 || d == 180) printf( %.10f n , w * h); else if (d == 90) printf( %.10f n , min(w, h) * min(w, h)); else { d = d * pi / 180; double mid = 2 * atan(h / w); if (d >= mid) { printf( %.10f n , h * h / sin(d)); } else { double u = (w + h) / (1 + 1 / cos(d) + tan(d)); double v = (w - h) / (1 + 1 / cos(d) - tan(d)); double x = (u + v) / 2; double y = (u - v) / 2; printf( %.10f n , w * h - (x * x + y * y) * tan(d)); } } return 0; } |
module Microfono(clk, reset, rec, play, bclk, lrsel, data_in, data_out, ampSD, rd, wr, emptyLED, fullLED);
input wire clk;
input wire reset;
input wire rec;
input wire play;
output wire bclk;
output wire lrsel;
input wire data_in;
output wire data_out;
output wire ampSD;
output wire rd;
output wire wr;
output wire emptyLED;
output wire fullLED;
wire empty;
wire full;
wire RstN;
wire FClrN;
wire F_LastN;
wire F_SLastN;
wire F_FirstN;
reg [5:0] fifo_counter = 0;
reg fclk = 1'b0;
assign FClrN = 1'b1;
assign emptyLED = ~empty;
assign fullLED = ~full;
always @(posedge bclk) // bclk = 1MHz
begin
if (reset)
begin
fifo_counter = 0;
fclk = 1'b1;
end
else
if (fifo_counter == 2)
begin
fifo_counter = 1;
fclk = ~fclk;
end
else
begin
fifo_counter = fifo_counter + 1;
fclk = fclk;
end
end
assign lrsel = 1'b0; //mic LRSel
assign ampSD = 1'b1;
DivFreq _DivFreq(
.reset(reset),
.clk(clk),
.bclk(bclk) // reloj de 1MHz
);
fifo _fifo(
.Clk(bclk), // reloj de la fifo
.RstN(~reset),
.Data_In(data_in),
.FClrN(FClrN),
.FInN(~wr),
.FOutN(~rd),
.F_Data(data_out),
.F_FullN(full),
.F_LastN(F_LastN),
.F_SLastN(F_SLastN),
.F_FirstN(F_FirstN),
.F_EmptyN(empty)
);
FSM _FSM(
.reset(reset),
.clk(clk),
.full(~full),
.empty(~empty),
.rec(rec),
.play(play),
.wr(wr),
.rd(rd)
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_buffer #(
parameter width = 8,
parameter depth = 1 /* < log2 of the storage size, in words */
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [width-1:0] dat_i,
output pipe_stb_o,
input pipe_ack_i,
output [width-1:0] dat_o
);
reg [width-1:0] storage[0:(1 << depth)-1];
reg [depth-1:0] produce;
reg [depth-1:0] consume;
reg [depth:0] level;
wire inc = pipe_stb_i & pipe_ack_o;
wire dec = pipe_stb_o & pipe_ack_i;
always @(posedge sys_clk) begin
if(sys_rst) begin
produce <= 0;
consume <= 0;
end else begin
if(inc)
produce <= produce + 1;
if(dec)
consume <= consume + 1;
end
end
always @(posedge sys_clk) begin
if(sys_rst)
level <= 0;
else begin
case({inc, dec})
2'b10: level <= level + 1;
2'b01: level <= level - 1;
default:;
endcase
end
end
always @(posedge sys_clk) begin
if(inc)
storage[produce] <= dat_i;
end
assign dat_o = storage[consume];
assign busy = |level;
assign pipe_ack_o = ~level[depth];
assign pipe_stb_o = |level;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 100; vector<int> adj[MAXN], *vec[MAXN]; int col[MAXN], pw[MAXN], goni[MAXN], sz[MAXN]; long long sum[MAXN]; void getsz(int v = 1, int pre = -1) { sz[v] = 1; for (auto u : adj[v]) { if (u != pre) { getsz(u, v); sz[v] += sz[u]; } } } void dfs(int v, int pre, bool type) { int idx = -1; int bigchild = -1; for (auto i : adj[v]) if (sz[i] > idx && i != pre) idx = sz[i], bigchild = i; for (auto i : adj[v]) if (i != bigchild && i != pre) dfs(i, v, 0); if (bigchild != -1) { dfs(bigchild, v, 1); vec[v] = vec[bigchild]; sum[v] = sum[bigchild]; pw[v] = pw[bigchild]; } else vec[v] = new vector<int>(); vec[v]->push_back(v); goni[col[v]]++; if (goni[col[v]] == pw[v]) sum[v] += col[v]; else if (goni[col[v]] > pw[v]) { sum[v] = col[v]; pw[v] = goni[col[v]]; } for (auto i : adj[v]) if (i != bigchild && i != pre) for (auto j : *vec[i]) { goni[col[j]]++; vec[v]->push_back(j); if (goni[col[j]] == pw[v]) sum[v] += col[j]; else if (goni[col[j]] > pw[v]) { sum[v] = col[j]; pw[v] = goni[col[j]]; } } if (!type) for (auto u : *vec[v]) goni[col[u]]--; } int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> col[i]; for (int i = 0; i < n - 1; ++i) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } getsz(); dfs(1, -1, 0); for (int i = 1; i <= n; ++i) cout << sum[i] << ; } |
#include <bits/stdc++.h> using namespace std; int arr[5002]; int main() { int n, i; scanf( %d , &n); if (n <= 2) { printf( 1 n1 n ); return 0; } if (n == 3) { printf( 2 n1 3 n ); return 0; } int curr = (n & 1) ? n : n - 1; for (i = 0; i < n; i++) { if (curr < 0) curr = (n & 1) ? n - 1 : n; arr[i] = curr; curr -= 2; } printf( %d n , n); for (i = 0; i < n; i++) printf( %d , arr[i]); putchar( n ); return 0; } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: alu_mul.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alu_mul (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_mul_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { if (i % 4 == 0 || i % 4 == 1) { printf( a ); } else { printf( b ); } } } |
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
`define SLL 4'b1000 // Shift logical left
`define SRL 4'b1100 // Shift logical right
`define SRA 4'b1110 // Shift arithmetic right
`define BNE 4'b1001 // Branch if not equal
module ALUControl (ALUCtrl, ALUop, FuncCode);
input [3:0] ALUop;
input [5:0] FuncCode;
output[3:0] ALUCtrl;
reg [3:0] ALUCtrl;
always @ (ALUCtrl or ALUop or FuncCode)
begin
if(ALUop==4'b1111)
begin
case(FuncCode)
6'b100000 :ALUCtrl = `ADD;
6'b100010 :ALUCtrl = `SUB;
6'b100001 :ALUCtrl = `ADDU;
6'b100011 :ALUCtrl = `SUBU;
6'b000000 :ALUCtrl = `NOP;
6'b100100 :ALUCtrl = `AND;
6'b100101 :ALUCtrl = `OR;
6'b100110 :ALUCtrl = `XOR;
6'b000000 :ALUCtrl = `SLL; //SLL
6'b000011 :ALUCtrl = `SRA; //SRA
6'b000010 :ALUCtrl = `SRL; //SRL
6'b101010 :ALUCtrl = `SLT; //SLT
6'b101011 :ALUCtrl = `SLTU; //SLTU
endcase
end
else ALUCtrl = ALUop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_M_V
`define SKY130_FD_SC_LP__XNOR2_M_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_m (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_m (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_M_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline void wrote(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) wrote(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { wrote(x); puts( ); } const long long maxn = 111; double p[maxn], win, tim; long long n, a[maxn]; int main() { n = read(); win = 1; for (long long i = 1; i <= n; ++i) { p[i] = (a[i] = read()) * 0.01; win *= p[i]; } tim = n; for (long long it = 0; ((1 - win) > 1e-10) && (it <= 500000); it++) { tim += 1 - win; long long cho = 0; double cho_v = 0; for (long long i = 1; i <= n; ++i) { double now_v = (1 - p[i]) * a[i] * 0.01 / p[i]; if (now_v > cho_v) cho_v = now_v, cho = i; } win = 1; p[cho] += (1 - p[cho]) * a[cho] * 0.01; for (long long i = 1; i <= n; ++i) win = win * p[i]; } printf( %lf n , tim); } |
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module seven_seg_Dev_IO( input clk,
input rst,
input GPIOe0000000_we,
input [2:0] Test,
input [31:0] disp_cpudata,
input [31:0] Test_data0,
input [31:0] Test_data1,
input [31:0] Test_data2,
input [31:0] Test_data3,
input [31:0] Test_data4,
input [31:0] Test_data5,
input [31:0] Test_data6,
output[31:0] disp_num
);
endmodule
|
/*
-- ============================================================================
-- FILE NAME : id_reg.v
-- DESCRIPTION : IDXe[WpCvCWX^
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module id_reg (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** fR[hÊ **********/
input wire [`AluOpBus] alu_op, // ALUIy[V
input wire [`WordDataBus] alu_in_0, // ALUüÍ 0
input wire [`WordDataBus] alu_in_1, // ALUüÍ 1
input wire br_flag, // ªòtO
input wire [`MemOpBus] mem_op, // Iy[V
input wire [`WordDataBus] mem_wr_data, // «Ýf[^
input wire [`CtrlOpBus] ctrl_op, // §äIy[V
input wire [`RegAddrBus] dst_addr, // ÄpWX^«ÝAhX
input wire gpr_we_, // ÄpWX^«ÝLø
input wire [`IsaExpBus] exp_code, // áOR[h
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
/********** IF/IDpCvCWX^ **********/
input wire [`WordAddrBus] if_pc, // vOJE^
input wire if_en, // pCvCf[^ÌLø
/********** ID/EXpCvCWX^ **********/
output reg [`WordAddrBus] id_pc, // vOJE^
output reg id_en, // pCvCf[^ÌLø
output reg [`AluOpBus] id_alu_op, // ALUIy[V
output reg [`WordDataBus] id_alu_in_0, // ALUüÍ 0
output reg [`WordDataBus] id_alu_in_1, // ALUüÍ 1
output reg id_br_flag, // ªòtO
output reg [`MemOpBus] id_mem_op, // Iy[V
output reg [`WordDataBus] id_mem_wr_data, // «Ýf[^
output reg [`CtrlOpBus] id_ctrl_op, // §äIy[V
output reg [`RegAddrBus] id_dst_addr, // ÄpWX^«ÝAhX
output reg id_gpr_we_, // ÄpWX^«ÝLø
output reg [`IsaExpBus] id_exp_code // áOR[h
);
/********** pCvCWX^ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_ <= #1 `DISABLE_;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin
/* pCvCWX^ÌXV */
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // tbV
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_ <= #1 `DISABLE_;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin // Ìf[^
id_pc <= #1 if_pc;
id_en <= #1 if_en;
id_alu_op <= #1 alu_op;
id_alu_in_0 <= #1 alu_in_0;
id_alu_in_1 <= #1 alu_in_1;
id_br_flag <= #1 br_flag;
id_mem_op <= #1 mem_op;
id_mem_wr_data <= #1 mem_wr_data;
id_ctrl_op <= #1 ctrl_op;
id_dst_addr <= #1 dst_addr;
id_gpr_we_ <= #1 gpr_we_;
id_exp_code <= #1 exp_code;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_1_V
`define SKY130_FD_SC_LS__CLKINV_1_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_1_V
|
#include <bits/stdc++.h> using namespace std; long long ret[70]; long long qpow(long long a, long long n) { long long ret = 1; while (n) { if (n & 1) ret = ret * a; a = a * a; n >>= 1; } return ret; } void solve() { ret[0] = 1; for (long long i = 1; i < 64; i++) { ret[i] = ret[i - 1] + qpow(2, i); } } vector<long long> res; void getans() { for (long long i = 0; i < 64; i++) { long long tmp = qpow(2, i); for (long long j = i + 1; j < 64; j++) { res.push_back(ret[j] - tmp); } } } int main() { solve(); getans(); long long a, b; cin >> a >> b; sort(res.begin(), res.end()); long long pos1 = upper_bound(res.begin(), res.end(), a) - res.begin(); long long pos3 = lower_bound(res.begin(), res.end(), a) - res.begin(); long long pos2 = upper_bound(res.begin(), res.end(), b) - res.begin(); long long pos4 = lower_bound(res.begin(), res.end(), b) - res.begin(); long long ans = pos2 - pos1; if (pos3 < pos1) ans++; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 152; const int MAX2 = 11300; const int INF = 1e9 + 10; int a[MAX]; int r[MAX][MAX2]; int t[MAX][MAX2]; int main() { int n, k, s; cin >> n >> k >> s; s = min(s, MAX2 - 1); for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 0; i <= n; i++) { for (int p = 1; p <= s; p++) { r[i][p] = INF; } } for (int q = 1; q <= k; q++) { for (int i = 0; i <= n; i++) { for (int p = 0; p <= s; p++) { t[i][p] = INF; } } for (int i = q; i <= n; i++) { for (int p = 0; p <= s; p++) { if (p >= i - q) t[i][p] = min(r[i - 1][p - (i - q)] + a[i], t[i - 1][p]); else t[i][p] = t[i - 1][p]; } } for (int i = 0; i <= n; i++) { for (int p = 0; p <= s; p++) { r[i][p] = t[i][p]; } } } int res = INF; for (int p = 0; p <= s; p++) { res = min(res, r[n][p]); } cout << res << n ; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { cin >> x; } void _R(int64_t &x) { cin >> x; } void _R(double &x) { cin >> x; } void _R(long double &x) { cin >> x; } void _R(char &x) { cin >> x; } void _R(char *x) { cin >> x; } void _R(string &x) { cin >> x; } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { cout << x; } void _W(const int64_t &x) { cout << x; } void _W(const double &x) { cout << fixed << setprecision(8) << x; } void _W(const long double &x) { cout << fixed << setprecision(16) << x; } void _W(const char &x) { cout << x; } void _W(const char *x) { cout << x; } void _W(const string &x) { cout << x; } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.first); cout << ; _W(x.second); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) cout << ; } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); cout << (sizeof...(tail) ? : n ); W(tail...); } int n, k; vector<int> a; bool ok_even(int x) { int cnt = 0; for (int i = (0); i < (n); i++) { if ((cnt & 1)) { if (a[i] <= x) cnt++; } else { cnt++; } if (cnt >= k) return true; } return false; } bool ok_odd(int x) { int cnt = 0; for (int i = (0); i < (n); i++) { if ((!(cnt & 1))) { if (a[i] <= x) cnt++; } else { cnt++; } if (cnt >= k) return true; } return false; } bool ok(int x) { if (ok_even(x)) { return true; } else if (ok_odd(x)) { return true; } return false; } void solve() { R(n, k); a.resize(n); for (int i = (0); i < (n); i++) { R(a[i]); } int l = 0, r = 1e9 + 10; while (r - l > 1) { int mid = (r + l) / 2; if (ok(mid)) { r = mid; } else { l = mid; } } W(r); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; for (int testcase = 1; testcase <= t; testcase++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, +1, -1, +1, +1, -1, -1}; int dy[] = {+1, -1, 0, 0, +1, -1, +1, -1}; template <typename first, typename second> ostream &operator<<(ostream &os, const pair<first, second> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << } ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename T> ostream &operator<<(ostream &os, const multiset<T> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename first, typename second> ostream &operator<<(ostream &os, const map<first, second> &v) { os << [ ; for (auto it = v.begin(); it != v.end(); ++it) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } void faltu() { cerr << n ; } template <typename T> void faltu(T a[], int n) { for (int i = 0; i < n; ++i) cerr << a[i] << ; cerr << n ; } template <typename T, typename... hello> void faltu(T arg, const hello &...rest) { cerr << arg << ; faltu(rest...); } inline int max(int a, int b) { return (a > b) ? a : b; } struct xorSpaces { int Rank, dim; array<int, 20> basis; xorSpaces() { Rank = 0, dim = 20; fill((basis).begin(), (basis).end(), 0); } void addBasis(int n) { for (int i = dim - 1; i >= 0; i--) { if (n & (1 << i)) { if (basis[i] == 0) { basis[i] = n; Rank++; break; } else { n ^= basis[i]; } } } } xorSpaces operator+=(xorSpaces other) { if (other.Rank == 0) return other; if (Rank == 0) { return *this = other; } for (int i = dim - 1; i >= 0; i--) { if (other.basis[i]) addBasis(other.basis[i]); } return *this; } int getMax() { int ans = 0; for (int i = dim - 1; i >= 0; i--) { if (basis[i] and (ans & (1 << i)) == 0) ans ^= basis[i]; } return ans; } }; const int mx = 5e5 + 123; xorSpaces table[(mx / 20) + 123][23], s[mx], p[mx]; int a[mx]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, l, r, q; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int d = (n) / 20; for (int i = 0; i < n; i++) { if (i % 20) p[i] = p[i - 1]; p[i].addBasis(a[i]); } for (int i = n - 1; i >= 0; i--) { if (i % 20 != 19) s[i] = s[i + 1]; s[i].addBasis(a[i]); } for (int i = 0; i <= d; i++) { table[i][0] = s[i * 20]; } for (int i = 1; i <= 15; i++) { for (int j = 0; j + (1 << (i - 1)) <= d; j++) { table[j][i] = table[j][i - 1]; table[j][i] += (table[j + (1 << (i - 1))][i - 1]); } } cin >> q; while (q--) { cin >> l >> r; l--, r--; int block_l = l / 20, block_r = r / 20; xorSpaces ans; if (block_l == block_r) { for (int i = l; i <= r; i++) { ans.addBasis(a[i]); } } else { ans += (s[l]); ans += (p[r]); block_l++, block_r--; if (block_l <= block_r) { r = block_r, l = block_l; int lg = log2(r - l + 1); ans += (table[l][lg]); ans += (table[r - (1 << lg) + 1][lg]); } } cout << ans.getMax() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; const int maxn = 500100; int n; vector<int> chd[maxn + 5]; int fa[maxn + 5]; int dep[maxn + 5]; void dfs(int first) { for (auto second : chd[first]) dep[second] = dep[first] + 1, dfs(second); } struct node { node *c[2], *p; int label; long long sum; int val; int sz; node() : p(NULL), label(0), sum(0), val(0), sz(1) { memset(c, 0, sizeof c); } void update() { sum = val; sz = 1; for (int i = (0), i_end_ = (2); i < i_end_; ++i) if (c[i]) sum += c[i]->sum, sz += c[i]->sz; } void flag_label(int _label) { label += _label; val += _label; sum += (long long)sz * _label; } void push_down() { if (label) { for (int i = (0), i_end_ = (2); i < i_end_; ++i) if (c[i]) c[i]->flag_label(label); label = 0; } } int get_pos() { if (!this || !p) return 2; for (int i = (0), i_end_ = (2); i < i_end_; ++i) if (p->c[i] == this) return i; return 2; } bool is_root() { return get_pos() >= 2; } void setc(node *u, const int &v) { if (this && v < 2) c[v] = u; if (u) u->p = this; } void rotate() { node *_p = this->p; bool mark = get_pos(); _p->p->setc(this, _p->get_pos()); _p->setc(c[mark ^ 1], mark); setc(_p, mark ^ 1); _p->update(); } void relax() { static node *tmp[maxn + 5]; int top = 0; node *u = this; while (!u->is_root()) tmp[top++] = u, u = u->p; u->push_down(); while (top) tmp[--top]->push_down(); } void splay() { relax(); for (; !is_root(); rotate()) if (!p->is_root()) ((p->p->c[0] == p) == (p->c[0] == this) ? p : this)->rotate(); update(); } node *access() { node *u = this, *v = NULL; for (; u; v = u, u = u->p) u->splay(), u->setc(v, 1), u->update(); splay(); return v; } }; node nd[maxn + 5]; vector<int> all[maxn + 5]; long long ans[maxn + 5]; int main() { scanf( %d , &n); for (int i = (0), i_end_ = (n); i < i_end_; ++i) scanf( %d , fa + i), --fa[i]; int rt = -1; for (int i = (0), i_end_ = (n); i < i_end_; ++i) if (!~fa[i]) rt = i; else chd[fa[i]].push_back(i); dep[rt] = 0; dfs(rt); for (int i = (0), i_end_ = (n); i < i_end_; ++i) { nd[i].val = 0; if (~fa[i]) nd[i].p = nd + fa[i]; else nd[i].p = NULL; } for (int i = (0), i_end_ = (n); i < i_end_; ++i) all[dep[i]].push_back(i); for (int i = (0), i_end_ = (n); i < i_end_; ++i) { for (auto first : all[i]) { node *u = nd + first; u->access(); u->flag_label(1); } for (auto first : all[i]) { node *u = nd + first; u->access(); ans[first] = u->sum - dep[first] - 1; } } for (int i = (0), i_end_ = (n); i < i_end_; ++i) printf( % ll d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; int mn = min(n, m); if (mn % 2 == 0) { cout << Malvika ; } else { cout << Akshat ; } return 0; } |
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming (
clk,
reset_n,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest
);
input clk;
input reset_n;
output [7:0] source_data;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
parameter TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
parameter SYSCLK_TO_TCK_SYNC_DEPTH = 3;
// Signals in the JTAG clock domain
wire jtag_clock;
wire jtag_clock_reset_n; // system reset is synchronized with jtag_clock
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(jtag_clock),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE)
) jtag_streaming (
.tck(jtag_clock),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(jtag_clock),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(jtag_clock),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
//In rememberance to GOD// //May GOD take care to me,my family and all the creatures// #include<bits/stdc++.h> using namespace std; #define ll long long #define int ll #define mod ((int)1e9+7) #define pii pair<int,int> #define vi vector<int> #define vvi vector<vi> #define vc vector<char> #define vpi vector<pii> #define vpic vector<pair<int,char>> #define vpid vector<pair<int,double>> #define INF (ll)1e15 #define all(x) (x).begin(),(x).end() #define allr(x) (x).rbegin(),(x).rend() #define pb push_back #define rep(i, begin, end) for (__typeof(end) i = (begin) - ((begin) > (end)); i != (end) - ((begin) > (end)); i += 1 - 2 * ((begin) > (end))) #define eb emplace_back #define error(args...) { string _s = #args; replace(_s.begin(), _s.end(), , , ); stringstream _ss(_s); istream_iterator<string> _it(_ss); err(_it, args); } void err(istream_iterator<string> it) {} template<typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } #define debug(...) fprintf(stderr, __VA_ARGS__), fflush(stderr) #define time__(d) for ( auto blockTime = make_pair(chrono::high_resolution_clock::now(), true); blockTime.second; debug( %s: %lld ms n , d, chrono::duration_cast<chrono::milliseconds>(chrono::high_resolution_clock::now() - blockTime.first).count()), blockTime.second = false ) //fill memset iota function // use 1ll<<number(left shift) const int N=((int)1e6); // int primes[N]; // // int spf[N]; // vector<int> pr; // void sieve(){ // // iota(spf+2,spf+N,2); // for(ll i=2;i<N;i++){ // if(primes[i]==0){ // pr.eb(i*i); // for(ll j=i*i;j<N;j+=i){ // // if(spf[j]==j) // // spf[j]=i; // primes[j]=1; // } // } // primes[i]^=1; // } // } // nloglogn ll gcd(ll a, ll b) {if (b > a) {return gcd(b, a);} if (b == 0) {return a;} return gcd(b, a % b);} void swap(int &x, int &y) {int temp = x; x = y; y = temp;} ll mod_add(ll a, ll b, ll m) {a = a % m; b = b % m; return (((a + b) % m) + m) % m;} ll mod_mul(ll a, ll b, ll m) {a = a % m; b = b % m; return (((a * b) % m) + m) % m;} ll mod_sub(ll a, ll b, ll m) {a = a % m; b = b % m; return (((a - b) % m) + m) % m;} ll power(ll x, ll y,ll m) {ll res = 1;while (y > 0){ if (y & 1) res = (res*x)%m;y = y>>1;x = x*x%m;}return res;} //avoid it in power of 2. //logn implementation //divisors in o(sqrt(n)) and no of divisors less than 2*(n^1/2);//128(max divisors for n<=1e5) //for n>=1e5 no of divisors is less than n^1/3; // use i&1 instead of i%2 //stoll convert string to integer(long long) // if(a>b) { return a/b+fun(b,a%b);} else return b/a+fun(a,b%a); technique of mod and minus similar answer but diffent time complexity. // if(a>b) { return 1+fun(b,a-b);} else return 1+fun(a,b-a); // class cmp { public: // bool operator()(const pair<int,pii> &p1,const pair<int,pii> &p2) const { if(p1.first!=p2.first) return p1.first>p2.first;else // { // if(p1.second.first!=p2.second.first) // { // return p1.second.first>p2.second.first; // } // else // { // return p1.second.second>p2.second.second; // } // } // } // }; // instead of priority queue i use set defined with cmp class strictly using = sign in comparisons(work as multi set) //erase function with values won t work //to modify a set i use cmp class stictly without using = sign in comparions,example above!!!! //erase function with values will work /////////////////////////////////////// CODE //////////////////////////////////////////////// // int dx[] = {1,0,-1,0}; // int dy[] = {0,1,0,-1}; // vi adj[N]; // int visited[N]; // int par[N]; // int d[N]; // int binary_searching(int a,int y) // { // int start=-1; // int end=a; // while(start+1!=end) // { // int mid=(start+end)/2; // if(mid>(a-y)) // { // end=mid; // } // else // { // start=mid; // } // } // return end; // } bool palin(string s) { int n=s.size(); for(int i=0;i<n/2;i++) { if(s[i]!=s[n-i-1]) { return false; } } return true; } void solve() { string s; cin>>s; bool flag=false; for(int i=0;i<s.size();i++) { if(s[i]!= a ) { flag=true; break; } } if(!flag) { cout<< NO << n ; return; } //appling to first; string temp; // temp=s; temp= a +s; if(!palin(temp)) { cout<< YES << n ; cout<<temp<< n ; return; } temp=s+ a ; if(!palin(temp)) { cout<< YES << n ; cout<<temp<< n ; } } int32_t main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin>>t; // sieve(); // t=1; for(int i=1;i<=t;i++) { solve(); // time__( solve ); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1); struct Point { long long x, y, r; Point() {} Point(long long a, long long b, long long c) { x = a; y = b; r = c; } }; long double rad; long double cor(long double angle) { if (angle < 0) { return angle + 2 * PI; } return angle; } pair<long double, long double> fnd(Point& p) { long double kor = sqrt(p.x * p.x + p.y * p.y); if (kor > rad + p.r) { return {20, 20}; } if (rad - p.r > kor) { return {20, 20}; } else { long double an1 = acos((rad * rad + p.x * p.x + p.y * p.y - p.r * p.r) / (2 * rad * kor)); long double tmp = sqrt(p.x * p.x + p.y * p.y - p.r * p.r); long double l = cor(atan2(p.y, p.x)); return {l - an1, l + an1}; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long double d; long long n; cin >> n; cin >> d; rad = 0; vector<Point> sp(n); long long x, y, r; for (long long i = 0; i < n; ++i) { cin >> x >> y >> r; sp[i].x = x; sp[i].y = y; sp[i].r = r; } vector<pair<long double, long long> > al(0); for (long long kol = 0; kol < 2850; ++kol) { rad += d; for (long long i = 0; i < n; ++i) { pair<long double, long double> now = fnd(sp[i]); if (now.first == 20) { continue; } else if (now.first == 30) { continue; } else if (now.first < 0 && now.second > 0) { al.push_back({cor(now.first), 0}); al.push_back({2 * PI, 1}); al.push_back({0, 0}); al.push_back({now.second, 1}); } else if (now.second > 2 * PI) { al.push_back({now.first, 0}); al.push_back({2 * PI, 1}); al.push_back({0, 0}); al.push_back({now.second - 2 * PI, 1}); } else { al.push_back({now.first, 0}); al.push_back({now.second, 1}); } } } sort(al.begin(), al.end()); long long now = 0; long long mx = 0; for (auto p : al) { if (p.second == 0) { ++now; } else { --now; } mx = max(mx, now); } cout << mx << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SEDFXTP_PP_SYMBOL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_PP_SYMBOL_V
|
/****************************************************
SIM Memory Model
with byte & half_word access controller
Memory Model
Little Endian
Ex :
data = 0x01234567
-Load
load_word[0] = 0x01234567
load_hf_word[0] = 0x0123
load_byte[0] = 0x01
-Store
store_word[0], 0x89abcdef = 0x89abcdef
store_hf_word[0], 0x89ab = 0x89ab4567
store_byte[0], 0x89 = 0x89234567
****************************************************/
`default_nettype none
module sim_memory_model(
input wire iCLOCK,
input wire inRESET,
//Req
input wire iMEMORY_REQ,
output wire oMEMORY_LOCK,
input wire [1:0] iMEMORY_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
input wire [3:0] iMEMORY_MASK,
input wire iMEMORY_RW, //1:Write | 0:Read
input wire [31:0] iMEMORY_ADDR,//input wire [25:0] iMEMORY_ADDR,
//This -> Data RAM
input wire [31:0] iMEMORY_DATA,
//Data RAM -> This
output wire oMEMORY_VALID,
input wire iMEMORY_LOCK,
output wire [63:0] oMEMORY_DATA
);
parameter P_MEM_INIT_LOAD = 1; //0=not load | 1=load
parameter P_MEM_INIT_LOAD_FIEL = "binary_file.bin";
parameter P_MEM_SIZE = (134217728)/8;
wire fifo_write_full;
wire fifo_read_empty;
wire [63:0] fifo_read_data;
reg [63:0] b_mem_data[0:P_MEM_SIZE-1];
integer i;
wire system_busy = fifo_write_full;
wire system_read_condition = iMEMORY_REQ && !iMEMORY_RW && !system_busy;
wire system_write_condition = iMEMORY_REQ && iMEMORY_RW && !system_busy;
//Error Check
always@(posedge iCLOCK)begin
if(system_write_condition || system_read_condition)begin
if(P_MEM_SIZE*8 <= iMEMORY_ADDR)begin
$display("[ERROR][sim_memory_model.v] Memory model, over address. MAX_ADDR[%x], REQ_ADDR[%x]", P_MEM_SIZE*8, iMEMORY_ADDR);
end
end
end
function [63:0] func_data_mask;
input func_word_select; //0
input [3:0] func_byte_enable; //1111
input [31:0] func_new_data;
input [63:0] func_current_data;
reg [63:0] func_private_data;
begin
if(!func_word_select)begin
func_private_data[7:0] = (func_byte_enable[0])? func_new_data[7:0] : func_current_data[7:0];
func_private_data[15:8] = (func_byte_enable[1])? func_new_data[15:8] : func_current_data[15:8];
func_private_data[23:16] = (func_byte_enable[2])? func_new_data[23:16] : func_current_data[23:16];
func_private_data[31:24] = (func_byte_enable[3])? func_new_data[31:24] : func_current_data[31:24];
func_private_data[63:32] = func_current_data[63:32];
end
else begin
func_private_data[39:32] = (func_byte_enable[0])? func_new_data[7:0] : func_current_data[39:32];
func_private_data[47:40] = (func_byte_enable[1])? func_new_data[15:8] : func_current_data[47:40];
func_private_data[55:48] = (func_byte_enable[2])? func_new_data[23:16] : func_current_data[55:48];
func_private_data[63:56] = (func_byte_enable[3])? func_new_data[31:24] : func_current_data[63:56];
func_private_data[31:0] = func_current_data[31:0];
end
func_data_mask = func_private_data;
end
endfunction
//Memory Write Block
always@(posedge iCLOCK )begin
if(system_write_condition)begin
b_mem_data[iMEMORY_ADDR[25:3]] <=
func_data_mask(
iMEMORY_ADDR[2],
iMEMORY_MASK,
iMEMORY_DATA,
b_mem_data[iMEMORY_ADDR[25:3]]
);
end
end
//Memory
initial begin
#0 begin
if(P_MEM_INIT_LOAD)begin
//Load File
//$readmemh("inst_level_test_tmp.hex", b_mem_data);
$readmemh(P_MEM_INIT_LOAD_FIEL, b_mem_data);
//Endian Convert
$display("[INF][sim_memory_model.v]Please wait. Endian converting for test file.");
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert(b_mem_data[i]); //[]
end
$display("test!!!!!");
$display("[INF][sim_memory_model.v]Mem[0]->%x", b_mem_data[0]);
end
end
end
function [63:0] func_endian_convert;
input [63:0] func_data;
reg [31:0] func_tmp;
begin
func_tmp = func_data[63:32];
func_endian_convert = {
func_tmp[7:0], func_tmp[15:8], func_tmp[23:16], func_tmp[31:24],
func_data[7:0], func_data[15:8], func_data[23:16], func_data[31:24]
};
end
endfunction
mist1032sa_sync_fifo #(64, 8, 3) OUT_FIFO(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.oCOUNT(),
.iWR_EN((system_read_condition) && !fifo_write_full),
.iWR_DATA(b_mem_data[iMEMORY_ADDR[25:3]]),
.oWR_FULL(fifo_write_full),
.iRD_EN(!iMEMORY_LOCK && !fifo_read_empty),
.oRD_DATA(fifo_read_data),
.oRD_EMPTY(fifo_read_empty)
);
assign oMEMORY_VALID = !iMEMORY_LOCK && !fifo_read_empty;
assign oMEMORY_DATA = fifo_read_data;
assign oMEMORY_LOCK = fifo_write_full;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct exam { long long a; long long b; }; exam a[200000]; long long n, r, avg; bool comp(exam a, exam b) { return a.b < b.b; } int main() { cin >> n >> r >> avg; for (int i = 0; i < n; i++) cin >> a[i].a >> a[i].b; sort(a, a + n, comp); long long needed = n * avg; long long owned = 0; for (int i = 0; i < n; i++) { owned += a[i].a; } needed -= owned; long long answer = 0; int i = 0; while (needed > 0 && i < n) { if (r - a[i].a < needed) { answer += (r - a[i].a) * a[i].b; needed -= (r - a[i].a); } else { answer += (needed)*a[i].b; needed = 0; } i++; } cout << answer << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; string s; cin >> s; int c = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u ) c++; else if ((s[i] < a || s[i] > z ) && (s[i] - 0 ) % 2 != 0) { c++; } } cout << c << endl; return 0; } |
module alu (a1, a2, o, status, control, enable);
input wire [7:0] a1, a2;
output reg [7:0] o;
input wire [4:0] control;
output reg [2:0] status;
input wire enable;
wire [8:0] a1_x, a2_x, o_x;
always @ (posedge enable )
begin
case (control)
2'b00000 :begin
a1_x = {1'b0, a1};
a2_x = {1'b0, a2};
o_x = a1_x + a2_x;
o = o_x[7:0];
status[0] = o_x[8];
end
2'b00001 : o = a1 - a2;
2'b00010 : o = a1 | a2;
2'b00011 : o = a1 & a2;
2'b00100 : o = a1 ^ a2;
2'b00101 : o = ~a2;
2'b00110 : o = a1 << a2;
2'b00111 : o = a1 >> a2;
2'b01000 : o = a1 >>> a2;
2'b01001 : o = (a1 << a2) | (a1 >> (8-a2));
2'b01010 : o = (a1 >> a2) | (a1 >> (8-a2));
2'b01011 : o = a2;
2'b01100 : o = 2'b00000000;
2'b01101 : o = 2'b00000000;
2'b01110 : o = 2'b00000000;
2'b01111 : o = a2 + a1 + status[0];
2'b10000 : o = a2 - a1 - status[0];
default : o = 2'b00000000;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class t> vector<t> sort(vector<t> &a) { return sort(a.begin(), a.end()); } const int N = 200200; int a[N], b[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) cin >> b[i]; reverse(a, a + n); reverse(b, b + m); a[n] = -1; int pos = 0, mn = a[0]; while (pos < n && mn > b[0]) pos++, mn = min(mn, a[pos]); if (pos == n || mn < b[0]) { puts( 0 ); return 0; } assert(mn == b[0]); long long res = 1; for (int itr = 0; itr < m - 1; itr++) { bool f = 1; int npos = pos; while (npos < n && mn != b[itr + 1]) { npos++; mn = min(mn, a[npos]); if (f && mn < b[itr]) { f = 0; res = (res * (npos - pos)) % 998244353; } } if (npos == n || mn != b[itr + 1]) { puts( 0 ); return 0; } pos = npos; } if (*min_element(a + pos, a + n) != b[m - 1]) { puts( 0 ); return 0; } cout << res << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_2_V
`define SKY130_FD_SC_HS__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_2_V
|
`default_nettype none
/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
module XC2CAndArray(zia_in, config_bits, pterm_out);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// No configuration, all AND arrays are the same.
// Differences in bitstream ordering, if any, are handled by XC2CDevice
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/Os
input wire[39:0] zia_in;
input wire[80*56 - 1 : 0] config_bits;
output reg[55:0] pterm_out;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Shuffle the config bits back to their proper 2D form
integer nterm;
integer nrow;
integer nin;
reg[79:0] and_config[55:0];
always @(*) begin
for(nterm=0; nterm<56; nterm=nterm+1) begin
for(nin=0; nin<80; nin=nin + 1)
and_config[nterm][nin] <= config_bits[nterm*80 + nin];
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual AND array
//Higher value is !X, lower is X
always @(*) begin
for(nterm=0; nterm<56; nterm = nterm+1) begin
pterm_out[nterm] = 1; //default if no terms selected
//AND in the ZIA stuff
for(nrow=0; nrow<40; nrow=nrow+1) begin
if(!and_config[nterm][nrow*2])
pterm_out[nterm] = pterm_out[nterm] & zia_in[nrow];
if(!and_config[nterm][nrow*2 + 1])
pterm_out[nterm] = pterm_out[nterm] & ~zia_in[nrow];
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { char ch = getchar(); int w = 1, c = 0; for (; !isdigit(ch); ch = getchar()) if (ch == - ) w = -1; for (; isdigit(ch); ch = getchar()) c = (c << 3) + (c << 1) + (ch ^ 48); return w * c; } const int mod = 998244353, M = 1e6 + 10; int n; long long fac[M], inv[M]; long long C(int x, int y) { if (y > x || y < 0) return 0; return fac[x] * inv[y] % mod * inv[x - y] % mod; } char s[M]; long long fast(long long x, long long p) { long long ret = 1; for (; p; p >>= 1, x = x * x % mod) if (p & 1) ret = ret * x % mod; return ret; } int main() { scanf( %s , s + 1); n = strlen(s + 1); fac[0] = 1; for (int i = 1; i <= n; ++i) fac[i] = fac[i - 1] * i % mod; inv[n] = fast(fac[n], mod - 2); for (int i = n; i >= 1; --i) inv[i - 1] = inv[i] * i % mod; int l = 0, x = 0, y = 0, r = 0; for (int i = 1; i <= n; ++i) { if (s[i] == ( ) l++; if (s[i] == ? ) x++; } long long ans = 0; for (int i = n; i >= 1; --i) { if (s[i] == ( ) l--; if (s[i] == ) ) r++; if (s[i] == ? ) x--, y++; ans = (ans + C(x + y, y + r - l) * l + C(x + y - 1, y + r - l - 1) * x) % mod; } cout << ans << n ; return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : bram_common.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
module bram_common #
(
parameter NUM_BRAMS = 16,
parameter ADDR_WIDTH = 13,
parameter READ_LATENCY = 3,
parameter WRITE_LATENCY = 1,
parameter WRITE_PIPE = 0,
parameter READ_ADDR_PIPE = 0,
parameter READ_DATA_PIPE = 0,
parameter BRAM_OREG = 1 //parameter to enable use of output register on BRAM
)
(
input clka, // Port A Clk,
input ena, // Port A enable
input wena, // read/write enable
input [63:0] dina, // Port A Write data
output [63:0] douta,// Port A Write data
input [ADDR_WIDTH - 1:0] addra,// Write Address for TL RX Buffers,
input clkb, // Port B Clk,
input enb, // Port B enable
input wenb, // read/write enable
input [63:0] dinb, // Port B Write data
output [63:0] doutb,// Port B Write data
input [ADDR_WIDTH - 1:0] addrb // Write Address for TL RX Buffers,
);
// width of the BRAM: used bits
localparam BRAM_WIDTH = 64/NUM_BRAMS;
// unused bits of the databus
localparam UNUSED_DATA = 32 - BRAM_WIDTH;
parameter UNUSED_ADDR = (BRAM_WIDTH == 64) ? 6: (BRAM_WIDTH == 32)
? 5: (BRAM_WIDTH == 16)
? 4: (BRAM_WIDTH == 8)
? 3: (BRAM_WIDTH == 4)
? 2: (BRAM_WIDTH == 2)
? 1:0;
parameter BRAM_WIDTH_PARITY = (BRAM_WIDTH == 32) ? 36: (BRAM_WIDTH == 16)? 18: (BRAM_WIDTH == 8)? 9: BRAM_WIDTH;
//used address bits. This will be used to determine the slice of the
//address bits from the upper level
localparam USED_ADDR = 15 - UNUSED_ADDR;
wire [31:0]ex_dat_a = 32'b0;
wire [31:0]ex_dat_b = 32'b0;
generate
genvar i;
if (NUM_BRAMS == 1)
begin: generate_sdp
// single BRAM implies Simple Dual Port and width of 64
RAMB36SDP
#(
.DO_REG (BRAM_OREG)
)
ram_sdp_inst
(
.DI (dina),
.WRADDR (addra[8:0]),
.WE ({8{wena}}),
.WREN (ena),
.WRCLK (clka),
.DO (doutb),
.RDADDR (addrb[8:0]),
.RDEN (enb),
.REGCE (1'b1),
.SSR (1'b0),
.RDCLK (clkb),
.DIP (8'h00),
.DBITERR(),
.SBITERR(),
.DOP(),
.ECCPARITY()
);
end
else if (NUM_BRAMS ==2)
for (i=0; i < NUM_BRAMS; i = i+1)
begin:generate_tdp2
RAMB36
#(
.READ_WIDTH_A (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_A (BRAM_WIDTH_PARITY),
.READ_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.DOB_REG (BRAM_OREG)
)
ram_tdp2_inst
(
.DOA (douta[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.DIA (dina[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.ADDRA ({ 1'b0, addra[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEA ({4{wena}}),
.ENA (ena),
.CLKA (clka),
.DOB (doutb[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.DIB (dinb [(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH]),
.ADDRB ({ 1'b0, addrb[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEB (4'b0),
.ENB (enb),
.REGCEB (1'b1),
.REGCEA (1'b1),
// .REGCLKB (clkb),
.SSRA (1'b0),
.SSRB (1'b0),
.CLKB (clkb)
);
end
else
for (i=0; i < NUM_BRAMS; i = i+1)
begin:generate_tdp
RAMB36
#(
.READ_WIDTH_A (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_A (BRAM_WIDTH_PARITY),
.READ_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_WIDTH_B (BRAM_WIDTH_PARITY),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.DOB_REG (BRAM_OREG)
)
ram_tdp_inst
(
.DOA ({ ex_dat_a[UNUSED_DATA-1:0], douta[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.DIA ({ {UNUSED_DATA{1'b0}} ,dina[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.ADDRA ({ 1'b0, addra[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEA ({4{wena}}),
.ENA (ena),
.CLKA (clka),
.DOB ({ ex_dat_b[UNUSED_DATA-1:0], doutb[(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.DIB ({ {UNUSED_DATA{1'b0}}, dinb [(i+1)*BRAM_WIDTH-1: i*BRAM_WIDTH] }),
.ADDRB ({ 1'b0, addrb[USED_ADDR - 1:0], {UNUSED_ADDR{1'b0}} }),
.WEB (4'b0),
.ENB (enb),
.REGCEB (1'b1),
.REGCEA (1'b1),
// .REGCLKB (clkb),
.SSRA (1'b0),
.SSRB (1'b0),
.CLKB (clkb)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> int mat[110][110]; int main() { int n, k, i, j; scanf( %d %d , &n, &k); if (n * n < k) { printf( -1 n ); return 0; } for (i = 0; i < n; i++) { for (j = i; j < n; j++) { if (i == j) { if (k > 0) { k--; mat[i][j] = 1; } else break; } else { if (k >= 2) { mat[i][j] = 1; mat[j][i] = 1; k = k - 2; } else if (k == 0) break; } } } for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { printf( %d , mat[i][j]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans, l; int n, m, N, i, j, k, s[3005], a[3005][3005], b[3005]; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { scanf( %d%d , &j, &k); a[j][++s[j]] = k; } for (i = 1; i <= m; i++) sort(a[i] + 1, a[i] + s[i] + 1, greater<int>()); ans = 1LL << 60; for (i = 1; i <= n; i++) { l = 0; N = 0; for (j = 2; j <= m; j++) { for (k = 1; k < i && k <= s[j]; k++) b[N++] = a[j][k]; for (; k <= s[j]; k++) l += a[j][k]; } sort(b, b + N); for (j = 0; j < i + N - n; j++) l += b[j]; ans = min(ans, l); } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog wrapper for lsbuflv2hv_symmetric with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbuflv2hv_symmetric.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m, ans(0); int main() { cin >> n >> m; while ((n + m) >= 3 && n > 0 && m > 0) { if (n >= m) { ans++; n -= 2; m--; } else { ans++; m -= 2; n--; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mxN = 1e3 + 1; int n, d[mxN], k; vector<int> adj[mxN]; vector<string> a[mxN]; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; for (int i = 0, c; i < n; i++) { cin >> c; string s1; for (int j = 0; j < k; j++) { cin >> s1; a[c].push_back(s1); } } vector<string> s; for (int i = 0; i < n; i++) for (int j = 0; j < k; j++) s.push_back(a[i][j]); n *= k; vector<bool> ok(26); int al = 0; for (string x : s) for (char c : x) { if (!ok[c - a ]) ++al, ok[c - a ] = 1; } for (int i = 1; i < n; i++) { int n1 = s[i - 1].size(), n2 = s[i].size(), i1 = 0; for (; i1 < n1 || i1 < n2; i1++) { if (i1 >= n2 && i1 < n1) { cout << IMPOSSIBLE ; return 0; } else if (i1 >= n1 || i1 >= n2) break; if (s[i - 1][i1] == s[i][i1]) continue; adj[s[i - 1][i1] - a ].push_back(s[i][i1] - a ); d[s[i][i1] - a ]++; break; } } queue<int> qu; string ans; for (int i = 0; i < 26; i++) if (!d[i] && ok[i]) qu.push(i); while (qu.size()) { int u = qu.front(); qu.pop(); for (int x : adj[u]) { --d[x]; if (!d[x]) qu.push(x); } ans += (u + a ); } cout << (ans.size() == al ? ans : IMPOSSIBLE ); } |
#include <bits/stdc++.h> using namespace std; const int MOD9 = 1e9 + 7; const int MOD91 = 1e9 + 9; const unsigned long long MOD12 = 1e12 + 39LL; const unsigned long long MOD15 = 1e15 + 37LL; const int INF = 1e9; const int base = 1e9; const int MAX = 2e5; const long double EPS = 1e-10; string second; int n, k; int a[30][30]; int dpt[101][30][101]; int dp(int pos, int prev, int left) { if (pos == second.size()) { return 0; } if (dpt[pos][prev][left] != -1) { return dpt[pos][prev][left]; } if (left == 0) { return dpt[pos][prev][left] = dp(pos + 1, second[pos] - a , left) + a[prev][second[pos] - a ]; } int b = -INF; for (int i = (0); i < (26); ++i) { b = max(b, dp(pos + 1, i, left - (i != int(second[pos] - a ))) + a[prev][i]); } return dpt[pos][prev][left] = b; } int main() { cin >> second >> k; cin >> n; memset(dpt, -1, sizeof(dpt)); for (int i = (0); i < (n); ++i) { char x, y; int xx; cin >> x >> y >> xx; a[x - a ][y - a ] = xx; } cout << dp(0, 27, k); return 0; } |
#include <bits/stdc++.h> struct edge { int to, nxt; } e[100005], e2[100005]; int h[100005], n, cnt, hei[100005], gson[100005], node[100005], N, fa[100005]; void ins(int x, int y) { e[++cnt].nxt = h[x]; e[cnt].to = y; h[x] = cnt; } void dfs1(int x) { hei[x] = 1; for (int i = h[x]; i; i = e[i].nxt) { dfs1(e[i].to); hei[x] = std::max(hei[x], hei[e[i].to] + 1); if (hei[gson[x]] < hei[e[i].to]) gson[x] = e[i].to; } } void dfs2(int x) { node[++N] = x; for (int i = h[x]; i; i = e[i].nxt) if (e[i].to != gson[x]) dfs2(e[i].to); if (gson[x]) dfs2(gson[x]); } int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) scanf( %d , &fa[i]), ins((++fa[i]), i); dfs1(1); dfs2(1); for (int i = 1; i <= n; i++) printf( %d , node[i] - 1); printf( n%d n , n - hei[1]); for (int i = 1, j = 1, k = 0; i <= n - hei[1]; i++) { while (j <= n && fa[node[j]] == k) k = node[j++]; if (j > n) break; printf( %d , node[j] - 1); k = fa[k]; } } |
/*
* This demonstrates a basic dynamic array
*/
module main;
shortreal foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); int a[100005]; int main() { int n; scanf( %d , &n); bool one = true; for (int i = 0; i < n + 1; ++i) { scanf( %d , &a[i]); } for (int i = 1; i < n + 1; ++i) { if (a[i - 1] > 1 && a[i] > 1) { one = false; break; } } if (one) { cout << perfect ; return 0; } cout << ambiguous n0 ; int c = 2; for (int i = 1; i < n + 1; ++i) { if (a[i - 1] == 1) { for (int j = 0; j < a[i]; ++j) { printf( %d , c - 1); } c += a[i]; } else { for (int j = 0; j < a[i]; ++j) { printf( %d , c - 1); } c += a[i]; } } cout << n0 ; c = 2; for (int i = 1; i < n + 1; ++i) { if (a[i - 1] == 1) { for (int j = 0; j < a[i]; ++j) { printf( %d , c - 1); } c += a[i]; } else { for (int j = 0; j < a[i]; ++j) { printf( %d , c - ((j + 1) % a[i - 1]) - 1); } c += a[i]; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 10000; const int MAXM = 100000; const int INF = 0x3f3f3f3f; pair<int, int> nxt[3][3]; int cot[3][3]; map<pair<int, int>, pair<long long, long long> > ma; int main() { long long k; int a, b; scanf( %I64d%d%d , &k, &a, &b); a--, b--; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { int x; scanf( %d , &x); x--; nxt[i][j].first = x; } } for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { int x; scanf( %d , &x); x--; nxt[i][j].second = x; } } pair<int, int> s = pair<int, int>(a, b); pair<long long, long long> now = pair<long long, long long>(0, 0); int cc = 0; while (ma.count(s) == 0) { if (k == 0) break; k--; cot[s.first][s.second] = cc++; ma[s] = now; if ((s.first + 1) % 3 == s.second) now.second++; else if (s.first == (1 + s.second) % 3) now.first++; s = nxt[s.first][s.second]; } if (ma.count(s)) { pair<long long, long long> ans = now; now.first -= ma[s].first; now.second -= ma[s].second; long long lun = cc - cot[s.first][s.second]; long long kk = k / lun; k %= lun; ans.first += now.first * kk; ans.second += now.second * kk; now = pair<long long, long long>(0, 0); while (k--) { if ((s.first + 1) % 3 == s.second) now.second++; else if (s.first == (1 + s.second) % 3) now.first++; s = nxt[s.first][s.second]; } ans.first += now.first; ans.second += now.second; printf( %I64d %I64d n , ans.first, ans.second); } else { s = nxt[s.first][s.second]; printf( %I64d %I64d n , now.first, now.second); } } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_minimac();
/* 100MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 25MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #20 phy_rx_clk = ~phy_rx_clk;
/* 25MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #20 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
reg [3:0] phy_rx_data;
reg phy_dv;
reg phy_rx_er;
wire phy_tx_en;
wire [3:0] phy_tx_data;
wire irq_rx;
wire irq_tx;
minimac2 #(
.csr_addr(4'h0)
) ethernet (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_sel_i(4'hf),
.wb_ack_o(wb_ack_o),
.irq_rx(irq_rx),
.irq_tx(irq_tx),
.phy_tx_clk(phy_tx_clk),
.phy_tx_data(phy_tx_data),
.phy_tx_en(phy_tx_en),
.phy_tx_er(),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.phy_col(),
.phy_crs(),
.phy_mii_clk(),
.phy_mii_data()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
integer cycle;
initial cycle = 0;
always @(posedge phy_rx_clk) begin
cycle <= cycle + 1;
phy_rx_er <= 1'b0;
phy_rx_data <= cycle;
if(phy_dv) begin
//$display("rx: %x", phy_rx_data);
if((cycle % 16) == 13) begin
phy_dv <= 1'b0;
//$display("** stopping transmission");
end
end else begin
if((cycle % 16) == 15) begin
phy_dv <= 1'b1;
//$display("** starting transmission");
end
end
end
always @(posedge phy_tx_clk) begin
if(phy_tx_en)
$display("tx: %x", phy_tx_data);
end
initial begin
/* Reset / Initialize our logic */
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
phy_dv = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
csrwrite(32'h00, 0);
csrwrite(32'h08, 1);
wbwrite(32'h1000, 32'h12345678);
wbread(32'h1000);
csrwrite(32'h18, 10);
csrwrite(32'h10, 1);
#5000;
csrread(32'h08);
csrread(32'h0C);
csrread(32'h10);
csrread(32'h14);
wbread(32'h0000);
wbread(32'h0004);
wbread(32'h0008);
wbread(32'h0800);
wbread(32'h0804);
wbread(32'h0808);
$finish;
end
endmodule
|
// Copyright (c) 2006 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
reg [7:0] mem [0:1];
initial begin
mem[0] = 0;
mem[1] = 1;
$memmonitor(mem);
#1 mem[0] = 4;
#1 mem[1] = 5;
#1 $finish(0);
end
endmodule // main
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPP xxx - TMDS serial stream phase aligner
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : phasealigner.v
//
// Description : This module determines whether the Spartan-6 IOSERDES
// has validate the incoming TMDS data stream
//
//
// Note:
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2006 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ns / 1ps
module phsaligner_nok # (
parameter OPENEYE_CNT_WD = 3, // valid open eye counter width
parameter CTKNCNTWD = 4, // Control Token Counter Width
parameter SRCHTIMERWD = 12, // Idle Timer Width
parameter CHANNEL = "BLUE"
)
(
input wire rst,
input wire clk,
input wire [9:0] sdata, // 10 bit serial stream sync. to clk
output reg flipgear,
output reg bitslip,
output reg psaligned // FSM output
);
localparam CTRLTOKEN0 = 10'b1101010100;
localparam CTRLTOKEN1 = 10'b0010101011;
localparam CTRLTOKEN2 = 10'b0101010100;
localparam CTRLTOKEN3 = 10'b1010101011;
///////////////////////////////////////////////////////
// Control Token Detection
///////////////////////////////////////////////////////
reg rcvd_ctkn, rcvd_ctkn_q;
reg blnkbgn; //blank period begins
//
// Control token used for word alignment
//
//localparam WRDALGNTKN = (CHANNEL == "BLUE") ? CTRLTOKEN0 : CTRLTOKEN1;
always @ (posedge clk) begin
rcvd_ctkn <=#1 ((sdata == CTRLTOKEN0) || (sdata == CTRLTOKEN1) ||
(sdata == CTRLTOKEN2) || (sdata == CTRLTOKEN3));
rcvd_ctkn_q <=#1 rcvd_ctkn;
blnkbgn <=#1 !rcvd_ctkn_q & rcvd_ctkn;
end
/////////////////////////////////////////////////////
// Control Token Search Timer
//
// DVI 1.0 Spec. says periodic blanking should start
// no less than every 50ms or 20HZ
// 2^24 of 74.25MHZ cycles is about 200ms
/////////////////////////////////////////////////////
reg [(SRCHTIMERWD-1):0] ctkn_srh_timer;
reg ctkn_srh_rst; //FSM output
always @ (posedge clk) begin
if (ctkn_srh_rst)
ctkn_srh_timer <=#1 {SRCHTIMERWD{1'b0}};
else
ctkn_srh_timer <=#1 ctkn_srh_timer + 1'b1;
end
reg ctkn_srh_tout;
always @ (posedge clk) begin
ctkn_srh_tout <=#1 (ctkn_srh_timer == {SRCHTIMERWD{1'b1}});
end
/////////////////////////////////////////////////////
// Contorl Token Event Counter
//
// DVI 1.0 Spec. says the minimal blanking period
// is at least 128 pixels long in order to achieve
// synchronization
//
// HDMI reduces this to as little as 8
/////////////////////////////////////////////////////
reg [(CTKNCNTWD-1):0] ctkn_counter;
reg ctkn_cnt_rst; //FSM output
always @ (posedge clk) begin
if(ctkn_cnt_rst)
ctkn_counter <=#1 {CTKNCNTWD{1'b0}};
else
ctkn_counter <=#1 ctkn_counter + 1'b1;
end
reg ctkn_cnt_tout;
always @ (posedge clk) begin
ctkn_cnt_tout <=#1 (ctkn_counter == {CTKNCNTWD{1'b1}});
end
//////////////////////////////////////////////////////////
// Below starts the phase alignment state machine
//////////////////////////////////////////////////////////
localparam INIT = 6'b1 << 0;
localparam SEARCH = 6'b1 << 1; // Searching for control tokens
localparam BITSLIP = 6'b1 << 2;
localparam RCVDCTKN = 6'b1 << 3; // Received at one Control Token and check for more
localparam BLNKPRD = 6'b1 << 4;
localparam PSALGND = 6'b1 << 5; // Phase alignment achieved
localparam nSTATES = 6;
reg [(nSTATES-1):0] cstate = {{(nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(nSTATES-1):0] nstate;
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] state_ascii = "INIT ";
always @(cstate) begin
if (cstate == INIT ) state_ascii <= "INIT ";
else if (cstate == SEARCH ) state_ascii <= "SEARCH ";
else if (cstate == BITSLIP ) state_ascii <= "BITSLIP ";
else if (cstate == RCVDCTKN ) state_ascii <= "RCVDCTKN ";
else if (cstate == BLNKPRD ) state_ascii <= "BLNKPRD ";
else state_ascii <= "PSALGND ";
end
// synthesis translate_on
`endif
always @ (posedge clk or posedge rst) begin
if (rst)
cstate <= INIT;
else
cstate <=#1 nstate;
end
//////////////////////////////////////////////////////////
// Counter counts number of blank period detected
// in order to qualify the bitslip position
//////////////////////////////////////////////////////////
localparam BLNKPRD_CNT_WD = 1;
reg [(BLNKPRD_CNT_WD-1):0] blnkprd_cnt = {BLNKPRD_CNT_WD{1'b0}};
always @ (*) begin
case (cstate) //synthesis parallel_case full_case
INIT: begin
nstate = (ctkn_srh_tout) ? SEARCH : INIT;
end
SEARCH: begin
if(blnkbgn)
nstate = RCVDCTKN;
else
nstate = (ctkn_srh_tout) ? BITSLIP : SEARCH;
end
BITSLIP: begin
nstate = SEARCH;
end
RCVDCTKN: begin
if(rcvd_ctkn)
nstate = (ctkn_cnt_tout) ? BLNKPRD : RCVDCTKN;
else
nstate = SEARCH;
end
BLNKPRD: begin
nstate = (blnkprd_cnt == {BLNKPRD_CNT_WD{1'b1}}) ? PSALGND : SEARCH;
end
PSALGND: begin
nstate = PSALGND; // Phase aligned so hang around here
end
endcase
end
reg [2:0] bitslip_cnt;
always @ (posedge clk or posedge rst) begin
if(rst) begin
psaligned <=#1 1'b0; //phase alignment success flag
bitslip <=#1 1'b0;
ctkn_srh_rst <=#1 1'b1; //control token search timer reset
ctkn_cnt_rst <=#1 1'b1; //control token counter reset
bitslip <=#1 1'b0;
bitslip_cnt <=#1 3'h0;
flipgear <=#1 1'b0;
blnkprd_cnt <=#1 {BLNKPRD_CNT_WD{1'b0}};
end else begin
case (cstate) // synthesis parallel_case full_case
INIT: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b1;
bitslip <=#1 1'b0;
psaligned <=#1 1'b0;
bitslip <=#1 1'b0;
bitslip_cnt <=#1 3'h0;
flipgear <=#1 1'b0;
blnkprd_cnt <=#1 {BLNKPRD_CNT_WD{1'b0}};
end
SEARCH: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b1;
bitslip <=#1 1'b0;
psaligned <=#1 1'b0;
end
BITSLIP: begin
ctkn_srh_rst <=#1 1'b1;
bitslip <=#1 1'b1;
bitslip_cnt <=#1 bitslip_cnt + 1'b1;
flipgear <=#1 bitslip_cnt[2]; //bitslip has toggled for 4 times
end
RCVDCTKN: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b0;
end
BLNKPRD: begin
blnkprd_cnt <=#1 blnkprd_cnt + 1'b1;
end
PSALGND: begin
psaligned <=#1 1'b1;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int x, y, a, b; double dis = 0; cin >> x >> y; a = x; b = y; n--; while (n--) { cin >> x >> y; dis += (double)sqrt(pow(y - b, 2) + pow(x - a, 2)); a = x; b = y; } dis = (dis / 50) * k; printf( %.6f , dis); return 0; } |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module add_hdr
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter STAGE_NUMBER = 'hff,
parameter PORT_NUMBER = 0
)
(
in_data,
in_ctrl,
in_wr,
in_rdy,
out_data,
out_ctrl,
out_wr,
out_rdy,
// --- Misc
reset,
clk
);
input [DATA_WIDTH-1:0] in_data;
input [CTRL_WIDTH-1:0] in_ctrl;
input in_wr;
output reg in_rdy;
output reg [DATA_WIDTH-1:0] out_data;
output reg [CTRL_WIDTH-1:0] out_ctrl;
output reg out_wr;
input out_rdy;
// --- Misc
input reset;
input clk;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------ Internal Params --------
localparam WRITE = 0;
localparam READ_HDR = 1;
localparam READ = 2;
localparam LAST_WORD_BYTE_CNT_WIDTH = log2(CTRL_WIDTH);
localparam PKT_BYTE_CNT_WIDTH = log2(2048);
localparam PKT_WORD_CNT_WIDTH = PKT_BYTE_CNT_WIDTH - LAST_WORD_BYTE_CNT_WIDTH;
// ------------- Regs/ wires -----------
wire [CTRL_WIDTH-1:0] out_ctrl_local;
wire [DATA_WIDTH-1:0] out_data_local;
reg [1:0] state_nxt;
reg [1:0] state;
reg [PKT_BYTE_CNT_WIDTH-1:0] byte_cnt_rd;
reg [PKT_BYTE_CNT_WIDTH-1:0] byte_cnt_rd_nxt;
reg [PKT_WORD_CNT_WIDTH-1:0] word_cnt_rd;
reg [PKT_WORD_CNT_WIDTH-1:0] word_cnt_rd_nxt;
reg [PKT_BYTE_CNT_WIDTH-1:0] byte_cnt;
reg [PKT_BYTE_CNT_WIDTH-1:0] byte_cnt_nxt;
reg [PKT_WORD_CNT_WIDTH-1:0] word_cnt;
reg [PKT_WORD_CNT_WIDTH-1:0] word_cnt_nxt;
reg fifo_rd;
wire [`IOQ_WORD_LEN_POS - `IOQ_SRC_PORT_POS-1:0] port_number = PORT_NUMBER;
// ------------ Modules -------------
/*
hdr_fifo add_hdr_fifo (
.din({in_ctrl, in_data}),
.wr_en(in_wr),
.dout({out_ctrl_local, out_data_local}),
.rd_en(fifo_rd),
.empty(),
.full(),
.almost_full(),
.rst(reset),
.clk(clk)
);
*/
hdr_fifo add_hdr_fifo
(
.aclr ( reset ),
.clock ( clk ),
.data ( {in_ctrl, in_data} ),
.rdreq ( fifo_rd ),
.wrreq ( in_wr ),
.almost_full ( ),
.empty ( ),
.full ( ),
.q ( {out_ctrl_local, out_data_local} )
);
// ------------- Logic ------------
always @(posedge clk)
begin
state <= state_nxt;
byte_cnt <= byte_cnt_nxt;
word_cnt <= word_cnt_nxt;
byte_cnt_rd <= byte_cnt_rd_nxt;
word_cnt_rd <= word_cnt_rd_nxt;
end
always @*
begin
// Restore to previous state
state_nxt = state;
byte_cnt_nxt = byte_cnt;
word_cnt_nxt = word_cnt;
byte_cnt_rd_nxt = byte_cnt_rd;
word_cnt_rd_nxt = word_cnt_rd;
out_data = out_data_local;
out_ctrl = out_ctrl_local;
in_rdy = 1'b0;
out_wr = 1'b0;
fifo_rd = 1'b0;
if (reset) begin
state_nxt = WRITE;
byte_cnt_nxt = 'h0;
word_cnt_nxt = 'h0;
byte_cnt_rd_nxt = 'h0;
word_cnt_rd_nxt = 'h0;
end
else begin
if (in_wr) begin
if (|in_ctrl) begin
word_cnt_rd_nxt = word_cnt + 'h1;
word_cnt_nxt = 'h0;
case (in_ctrl)
'h01: byte_cnt_rd_nxt = byte_cnt + 8;
'h02: byte_cnt_rd_nxt = byte_cnt + 7;
'h04: byte_cnt_rd_nxt = byte_cnt + 6;
'h08: byte_cnt_rd_nxt = byte_cnt + 5;
'h10: byte_cnt_rd_nxt = byte_cnt + 4;
'h20: byte_cnt_rd_nxt = byte_cnt + 3;
'h40: byte_cnt_rd_nxt = byte_cnt + 2;
'h80: byte_cnt_rd_nxt = byte_cnt + 1;
endcase
byte_cnt_nxt = 'h0;
end
else begin
word_cnt_nxt = word_cnt + 'h1;
byte_cnt_nxt = byte_cnt + 'h8;
end
end
case (state)
WRITE : begin
in_rdy = 1'b1;
if (in_wr && |in_ctrl)
state_nxt = READ_HDR;
end
READ_HDR : begin
out_data = {word_cnt_rd,
port_number,
{(`IOQ_SRC_PORT_POS - PKT_BYTE_CNT_WIDTH){1'b0}}, byte_cnt_rd};
out_ctrl = STAGE_NUMBER;
out_wr = out_rdy;
fifo_rd = out_rdy;
if (out_rdy)
state_nxt = READ;
end
READ : begin
out_data = out_data_local;
out_ctrl = out_ctrl_local;
out_wr = out_rdy;
fifo_rd = out_rdy && !(|out_ctrl_local);
if (out_rdy && |out_ctrl_local)
state_nxt = WRITE;
end
endcase
end
end
endmodule // add_hdr
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; const int E = 80; vector<long long> pr, f; mt19937_64 gen(time(0)); long long a[maxn]; map<long long, long long> val; int n; long long solve(long long p) { if (val.find(p) != val.end()) return val[p]; long long ret = 0; for (int i = 0; i < n; i++) { if (a[i] < p) ret += p - a[i]; else { long long h = a[i] % p; ret += min(h, p - h); } } val[p] = ret; return ret; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &a[i]); for (int i = 0; i < n; i++) { f.push_back(a[i] + 1); if (a[i] > 1) f.push_back(a[i]); if (a[i] > 2) f.push_back(a[i] - 1); } int m = f.size(); long long ans = n; for (int _ = 0; _ < E; _++) { long long x = f[gen() % m], j = 2; f.clear(); while (j * j <= x) { if (x % j == 0) { while (x % j == 0) x /= j; pr.push_back(j); } ++j; } if (x > 1) pr.push_back(x); for (auto p : pr) ans = min(ans, solve(p)); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; long long small(long long a, long long b) { if (a < b) return a; return b; } long long large(long long a, long long b) { if (a > b) return a; return b; } long long root(long long x, vector<long long>& a) { if (a[x] == x) return x; a[x] = root(a[x], a); return (a[x]); } int main() { long long t; t = 1; while (t--) { long long n, i, c, m, x, y, a1, h, k = 0; cin >> n >> m; vector<long long> v(n + 1, 0), a(n + 1, 0); for (i = 1; i <= n; i++) { cin >> v[i]; a[i] = i; } while (m--) { cin >> x >> y; x = root(x, a); y = root(y, a); if (v[x] < v[y]) a[y] = x; else a[x] = y; } for (i = 1; i <= n; i++) { if (a[i] == i) k = k + v[i]; } cout << k << endl; } } |
#include <bits/stdc++.h> using namespace std; using namespace std; int n, a, b, ans; int main() { cin >> n; while (n--) { cin >> a >> b; a++, b--; while (b /= 4) a++; ans = max(ans, a); } cout << ans; } |
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description: A FRIc client model which can only originate transactions
*
* Functionality:
*
* Issues:
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_client_master
(
clk,
rst,
fric_in,
fric_out,
// FIXME: shouldn't I prepend something to these?
ctyp,
port,
addr,
wdat,
tstb, // transaction strobe -- initiate based on above
trdy, // tstb may only be asserted when this is already high
rstb, // reply strobe
rdat // reply data
);
// In/Out declarations
input clk;
input rst;
input [7:0] fric_in;
output [7:0] fric_out;
input [3:0] ctyp;
input [3:0] port;
input [7:0] addr;
input [15:0] wdat;
input tstb;
output trdy;
output rstb;
output [15:0] rdat;
// Parameters
parameter [3:0] fos_idle = 4'h0,
fos_wr_adr = 4'h2,
fos_wr_da0 = 4'h3,
fos_wr_da1 = 4'h4,
fos_wr_ack = 4'h5,
fos_rd_adr = 4'h7,
fos_rd_ack = 4'h8;
parameter [3:0] fis_idle = 4'h0,
fis_wr_ack = 4'h1,
fis_rd_ack = 4'h2,
fis_rd_da0 = 4'h3,
fis_rd_da1 = 4'h4;
// Regs and Wires
reg [3:0] fos_state, next_fos_state;
reg trdy;
reg [2:0] fric_out_sel;
reg [7:0] fric_out;
reg [3:0] fis_state, next_fis_state;
reg rdat_cap_high;
reg rdat_cap_low;
reg next_rstb;
reg fis_ack;
reg [7:0] fric_inr;
reg [15:0] rdat;
reg rstb;
// RTL
/****************************************************************************
* Fric Out Sequencer (fos)
*
* This model will only send reads or writes out. It will never have to ack
* anything because it only originates transactions and never responds to
* them.
*
* The FSM is fairly simple. It either sends a 4 cycle write packet or a 2
* cycle read packet. trdy is deasserted as soon as it leaves idle. The fsm
* doesn't return to idle until it gets notified of an ack from the fric in
* sequencer.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
* Note that the timing of rstb and trdy are depended on in the fric/pci
* interface. The rising edge of trdy must always be 1 cycle before rstb
*
*/
always @ (/*AS*/ctyp or fis_ack or fos_state or tstb)
begin
// FSM default outputs
next_fos_state = fos_state;
trdy = 1'b0;
fric_out_sel = 0;
case(fos_state)
fos_idle:
begin
if(tstb==1'b1 && ctyp==4'b0010) begin
fric_out_sel = 1;
next_fos_state = fos_wr_adr;
end else if(tstb==1'b1 && ctyp==4'b0011) begin
fric_out_sel = 1;
next_fos_state = fos_rd_adr;
end else begin
trdy = 1'b1;
end
end
fos_wr_adr:
begin
fric_out_sel = 2;
next_fos_state = fos_wr_da0;
end
fos_wr_da0:
begin
fric_out_sel = 3;
next_fos_state = fos_wr_da1;
end
fos_wr_da1:
begin
fric_out_sel = 4;
next_fos_state = fos_wr_ack;
end
fos_wr_ack:
begin
fric_out_sel = 0;
if(fis_ack==1'b1) begin
trdy = 1'b1;
next_fos_state = fos_idle;
end
end
fos_rd_adr:
begin
fric_out_sel = 2;
next_fos_state = fos_rd_ack;
end
fos_rd_ack:
begin
fric_out_sel = 0;
if(fis_ack==1'b1) begin
trdy = 1'b1;
next_fos_state = fos_idle;
end
end
default:
begin
end
endcase // case(fos_state)
end // always @ (...
always @ (posedge clk)
begin
if(rst==1'b1)
begin
fos_state <= fos_idle;
fric_out <= 0;
end
else
begin
fos_state <= next_fos_state;
case(fric_out_sel)
3'h0: fric_out <= 8'h00;
3'h1: fric_out <= {ctyp, port};
3'h2: fric_out <= addr;
3'h3: fric_out <= wdat[7:0];
3'h4: fric_out <= wdat[15:8];
default: fric_out <= 8'h00;
endcase // case(fric_out_sel)
end
end // always @ (posedge clk)
/****************************************************************************
* Fric In Sequencer (fis)
*
* This model will only get ACK packets in. It will never get a read or write
* because it is only a master.
*
* This machine simply waits for read or write acks. Any other packet ctyp is
* an error. For a read ack, the rdat is registered and the rstb is asserted.
* This model doesn't yet have any mechanism to support interrupts!
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
* Note that the timing of rstb and trdy are depended on in the fric/pci
* interface. The rising edge of trdy must always be 1 cycle before rstb
*/
always @ (/*AS*/fis_state or fric_inr)
begin
// FSM default outputs
next_fis_state = fis_state;
rdat_cap_high = 0;
rdat_cap_low = 0;
next_rstb = 0;
fis_ack = 0;
case(fis_state)
fis_idle:
begin
if(fric_inr[7:4]==4'b0100)
next_fis_state = fis_wr_ack;
else if(fric_inr[7:4]==4'b0101)
next_fis_state = fis_rd_ack;
end
fis_wr_ack:
begin
fis_ack = 1'b1;
next_fis_state = fis_idle;
end
fis_rd_ack:
begin
next_fis_state = fis_rd_da0;
end
fis_rd_da0:
begin
rdat_cap_low = 1'b1;
next_fis_state = fis_rd_da1;
end
fis_rd_da1:
begin
rdat_cap_high = 1'b1;
next_rstb = 1'b1;
fis_ack = 1'b1;
next_fis_state = fis_idle;
end
default:
begin
end
endcase // case(fis_state)
end // always @ (...
always @ (posedge clk)
begin
if(rst==1'b1)
begin
fis_state <= fis_idle;
fric_inr <= 0;
rdat <= 0;
rstb <= 0;
end
else
begin
fis_state <= next_fis_state;
fric_inr <= fric_in;
if(rdat_cap_high==1'b1)
rdat[15:8] <= fric_inr;
if(rdat_cap_low==1'b1)
rdat[7:0] <= fric_inr;
rstb <= next_rstb;
end
end // always @ (posedge clk)
/****************************************************************************
* Subblock
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_client_slave
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: KOA_c
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.04
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
// 3. Changed the adder-sub description
//////////////////////////////////////////////////////////////////////////////////
module KOA_c_2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 54, parameter precision = 1)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if ((SW<=18) && (precision == 0)) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else if ((SW<=7) && (precision == 1)) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_c_2 #(.SW(SW/2), .precision(precision) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c_2 #(.SW(SW/2), .precision(precision)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
KOA_c_2 #(.SW(SW/2+1), .precision(precision)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
assign Result[4*(SW/2):0] = {Q_left,Q_right} + /*result_left_mult,result_right_mult*/
{leftside1, //zero padding
Q_middle[2*(SW/2)+1:0] -
{zero1, /*result_left_mult//*/Q_left} -
{zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]},
rightside1}; //zero padding
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_c_2 #(.SW(SW/2), .precision(precision)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c_2 #(.SW((SW/2)+1), .precision(precision)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//multiplication for middle
KOA_c_2 #(.SW(SW/2+2), .precision(precision)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
assign Result[4*(SW/2)+2:0] = {/*result_left_mult,result_right_mult*/Q_left,Q_right} +
{leftside2, Q_middle -
{zero2, /*result_left_mult//*/Q_left} -
{zero1, /*result_right_mult//*/Q_right} ,
rightside2};
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int parent[200005], par[200005], root; int find(int i) { if (parent[i] != i) parent[i] = find(parent[i]); return parent[i]; } void merge(int x, int y) { int xroot = find(x); int yroot = find(y); if (xroot == yroot) { if (!root) root = xroot; par[x] = root; } else parent[xroot] = yroot; } int main() { int n, temp[200005], dsu[200005], k = 0, cnt = 0; cin >> n; for (int i = 1; i <= n; i++) parent[i] = i; for (int i = 1; i <= n; i++) { cin >> par[i]; temp[i] = par[i]; if (par[i] == i) root = i; } for (int i = 1; i <= n; i++) { if (par[i] == i) { if (i == root) { } else par[i] = root; } else merge(i, par[i]); } for (int i = 1; i <= n; i++) if (temp[i] != par[i]) cnt++; cout << cnt << n ; for (int i = 1; i <= n; i++) cout << par[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> ydidicreate; int dontknowy[100000]; int main() { int tt; cin >> tt; while (tt--) { int n, k; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; ; sort(a, a + n); int f[k]; for (int i = 0; i < k; i++) cin >> f[i]; ; sort(f, f + k); long long ans = 0; int l = n - 1, m = 0; int pos; for (int i = 0; i < k; i++) { if (f[i] == 1) { ans += (2 * a[l]); l--; } else { pos = i; break; } } for (int i = k - 1; i >= 0; i--) { if (f[i] == 1) break; ans += a[l]; l--; ans += a[m]; m++; f[i] -= 2; while (f[i]--) { m++; } } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; long long n, u, col[300005], dp[300005][2]; vector<long long> graph[300005]; void dfs(long long u) { dp[u][col[u]] = 1; for (long long i = 0; i < graph[u].size(); i++) { long long v = graph[u][i]; dfs(v); dp[u][1] = (((dp[u][1] * dp[v][0]) % 1000000007 + (dp[u][0] * dp[v][1]) % 1000000007) % 1000000007 + (dp[u][1] * dp[v][1]) % 1000000007) % 1000000007; dp[u][0] = (dp[u][0] * ((dp[v][0] + dp[v][1]) % 1000000007)) % 1000000007; } } int main() { scanf( %lld , &n); for (long long i = 1; i < n; i++) { scanf( %lld , &u); graph[u].push_back(i); } for (long long i = 0; i < n; i++) scanf( %lld , &col[i]); dfs(0); printf( %lld n , dp[0][1]); return 0; } |
#include <bits/stdc++.h> using namespace std; int row[1010]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); memset(row, 0x3f3f3f3f, sizeof row); long long ans = 0; for (int i = (0); i < (n); ++i) { int r, c; scanf( %d %d , &r, &c); row[r] = min(c, row[r]); } for (int i = 1; i <= m; ++i) ans += ((row[i] == 0x3f3f3f3f) ? 0 : row[i]); cout << min(ans, (long long)k) << endl; return 0; } |
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
/*
* Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
* TxD_data is latched so that it doesn't have to stay valid while it is being sent
*/
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 9600;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
/* ============================== */
`ifdef SIMULATION
/* output one bit per clock cycle */
wire BitTick = 1'b1;
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state < 4) | (TxD_state[3] & TxD_shift[0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int oo = numeric_limits<int>::max(); const long long M = 998244353, MAXN = 1e6 + 10; long long n, c[MAXN]; long long mp(long long a, long long e) { long long ret = 1; while (e) { if (e % 2) ret = ret * a % M; a = a * a % M; e /= 2; } return ret; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); cin >> n; c[0] = 1; for (int i = 0; i < n; i++) c[i + 1] = c[i] * (n - i) % M * mp(i + 1, M - 2) % M; long long ans = 0; for (int i = 1; i <= n; i++) { long long add = (i + 1) % 2 ? -1 : 1; add *= c[i]; add = add * mp(3, n * (n - i) + i) % M; ans = (ans + add) % M; } ans = ans * 2 % M; for (int i = 0; i < n; i++) { long long add = (i + 1) % 2 ? -1 : 1; add *= c[i]; long long inner = (mp(1 - mp(3, i), n) - mp(-mp(3, i), n)) % M; add = 3 * add * inner % M; ans = (ans + add) % M; } while (ans < 0) ans += M; cout << ans << n ; return 0; } |
module rnd_vec_gen(
clk,
init,
save,
restore,
next,
out
);
parameter OUT_SIZE = 16; // size of output port, independent of LFSR register size
parameter LFSR_LENGTH = 55; // LFSR
parameter LFSR_FEEDBACK = 24; // definition
input clk;
input init; // positive initialization strobe, synchronous to clock, its length will determine initial state
input save,restore,next; // strobes for required events: positive, one clock cycle long
reg init2;
output [OUT_SIZE-1:0] out;
wire [OUT_SIZE-1:0] out;
reg [OUT_SIZE-1:0] rndbase_main [0:LFSR_LENGTH-1];
reg [OUT_SIZE-1:0] rndbase_store [0:LFSR_LENGTH-1];
//`define simple_rnd
`ifdef simple_rnd
reg [OUT_SIZE-1:0] back,front;
always @(posedge clk)
begin
if( restore )
front <= back;
else if( save )
back <= front;
else if( next )
front <= (front!=0)?(front + 1):2;
end
assign out = front;
`else
assign out = rndbase_main[0];
always @(posedge clk)
begin
init2 <= init;
if( init && !init2 ) // begin of initialization
begin
rndbase_main[0][0] <= 1'b1; // any non-zero init possible
end
else if( init && init2 ) // continue of initialization
begin
shift_lfsr;
end
else // no init, normal work
begin
if( restore ) // restore event: higher priority
begin
integer i;
for(i=0;i<LFSR_LENGTH;i=i+1)
rndbase_main[i] <= rndbase_store[i];
end
else
begin
if( save ) // save current state
begin
integer j;
for(j=0;j<LFSR_LENGTH;j=j+1)
rndbase_store[j] <= rndbase_main[j];
end
else if( next ) // step to next value
begin
shift_lfsr;
end
end
end
end
task shift_lfsr;
begin
reg [OUT_SIZE-1:0] sum;
reg [LFSR_LENGTH-1:0] lsbs;
integer i;
for(i=0;i<LFSR_LENGTH;i=i+1)
lsbs[i] = rndbase_main[i][0];
sum = rndbase_main[LFSR_LENGTH-1] + rndbase_main[LFSR_FEEDBACK-1];
for(i=1;i<LFSR_LENGTH;i=i+1)
rndbase_main[i] <= rndbase_main[i-1];
rndbase_main[0] <= { sum[OUT_SIZE-1:1], (|lsbs)?sum[0]:1'b1 };
end
endtask
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND2_PP_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f |= (ch == - ), ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f ? -x : x; } inline void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } long long n, a[200005], tot[200005], tong[105], mx, mxat, now; signed main() { n = read(); for (register long long i = 1; i <= n; i++) { a[i] = read(); now = a[i]; while (now && now % 2 == 0) { tot[i]++; now /= 2; } tong[tot[i]]++; if (tong[tot[i]] > mx) mx = tong[tot[i]], mxat = tot[i]; } write(n - mx); puts( ); for (register long long i = 1; i <= n; i++) if (tot[i] != mxat) write(a[i]), putchar( ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; string substrs(string s, int i, int j) { string a; for (int h = i; h < j + 1; h++) { a.push_back(s[h]); } return a; } int main() { int T; cin >> T; for (int zz = 0; zz < T; zz++) { string s, s1; cin >> s; vector<int> cnt[3]; for (int i = 0; i < s.length(); i++) { if (islower(s[i])) { s1.push_back( l ); cnt[0].push_back(i); } else if (isupper(s[i])) { s1.push_back( u ); cnt[1].push_back(i); } else if (isdigit(s[i])) { s1.push_back( d ); cnt[2].push_back(i); } } int num = 0; for (int i = 0; i < 3; i++) if (!cnt[i].size()) num++; if (num == 0) { cout << s << n ; continue; } else if (num == 1) { for (int i = 0; i < 3; i++) { if (!cnt[i].size()) { for (int j = 1; j < 3; j++) { if (cnt[(i + j) % 3].size() != 1) { if (i == 0) s[cnt[(i + j) % 3][0]] = a ; else if (i == 1) s[cnt[(i + j) % 3][0]] = A ; else if (i == 2) s[cnt[(i + j) % 3][0]] = 1 ; break; } } break; } } } else if (num == 2) { for (int i = 0; i < 3; i++) { if (cnt[i].size()) { if (i == 0) { s[0] = A ; s[1] = 1 ; } else if (i == 1) { s[0] = a ; s[1] = 1 ; } else if (i == 2) { s[0] = A ; s[1] = a ; } break; } } } cout << s << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, log2n, q, C[N], L[N], R[N], tot = 0, f[N][25], up[N], de2[N]; long long de[N]; struct node { long long min, sign; } a[N * 4]; pair<int, int> E[2 * N]; vector<pair<int, int> > e[N]; void add1(int x, int k) { for (; x <= n; x += x & (-x)) de[x] += k; } long long ask1(int x) { long long res = 0; for (; x; x -= x & (-x)) res += de[x]; return res; } void build(int l, int r, int now) { if (l == r) { a[now].min = ask1(l) + up[C[l]]; return; } int mid = (l + r) >> 1; build(l, mid, now << 1); build(mid + 1, r, now << 1 | 1); a[now].min = min(a[now << 1].min, a[now << 1 | 1].min); } void update(int l, int r, int now, int k) { a[now].min += k; a[now].sign += k; } void down(int l, int r, int now) { int mid = (l + r) >> 1; update(l, mid, now << 1, a[now].sign); update(mid + 1, r, now << 1 | 1, a[now].sign); a[now].sign = 0; } void add2(int l, int r, int now, int s, int t, int k) { if (s <= l && r <= t) { update(l, r, now, k); return; } down(l, r, now); int mid = (l + r) >> 1; if (s <= mid) add2(l, mid, now << 1, s, t, k); if (t > mid) add2(mid + 1, r, now << 1 | 1, s, t, k); a[now].min = min(a[now << 1].min, a[now << 1 | 1].min); } long long ask2(int l, int r, int now, int s, int t) { if (s <= l && r <= t) return a[now].min; down(l, r, now); int mid = (l + r) >> 1; long long res = 0x3f3f3f3f3f3f3f3f; if (s <= mid) res = min(ask2(l, mid, now << 1, s, t), res); if (t > mid) res = min(ask2(mid + 1, r, now << 1 | 1, s, t), res); return res; } void dfs1(int u, int fa) { f[u][0] = fa; C[++tot] = u; L[u] = tot; for (int i = 0; i < e[u].size(); i++) { int v = e[u][i].first; if (v == fa) continue; dfs1(v, u); } R[u] = tot; } void dfs2(int u, int fa) { for (int i = 0; i < e[u].size(); i++) { int v = e[u][i].first, w = e[u][i].second; if (v == fa) continue; de2[v] = de2[u] + 1; add1(L[v], w); add1(R[v] + 1, -w); dfs2(v, u); } } bool on(int u, int v) { swap(u, v); long long k = de2[u] - de2[v]; if (k < 0) return false; for (int i = 0; k; i++, k >>= 1) if (k & 1) u = f[u][i]; return (u == v); } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> q; log2n = log2(n); for (int i = 1; i <= 2 * n - 2; i++) { int u, v, w; cin >> u >> v >> w; if (i < n) E[i] = {w, v}; else E[i] = {w, u}, up[u] = w; if (i >= n) continue; e[u].push_back({v, w}); e[v].push_back({u, w}); } dfs1(1, 0); dfs2(1, 0); for (int j = 1; j <= log2n; j++) for (int i = 1; i <= n; i++) f[i][j] = f[f[i][j - 1]][j - 1]; build(1, n, 1); for (int i = 0; i < q; i++) { int c, x, y; cin >> c >> x >> y; if (c == 1) { if (x < n) { add1(L[E[x].second], -E[x].first + y); add1(R[E[x].second] + 1, E[x].first - y); add2(1, n, 1, L[E[x].second], R[E[x].second], -E[x].first + y); } else add2(1, n, 1, L[E[x].second], L[E[x].second], -E[x].first + y); E[x].first = y; } else { if (on(x, y)) cout << ask1(L[y]) - ask1(L[x]) << endl; else cout << ask2(1, n, 1, L[x], R[x]) - ask1(L[x]) + ask1(L[y]) << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> mp; set<int> s; int main(void) { int q; scanf( %d , &q); while (q--) { mp.clear(); int x; scanf( %d , &x); int t = x; int lim = sqrt(t); for (int i = 2; i <= lim; i++) { while (t % i == 0) { mp[i]++; t /= i; } } if (1 < t) mp[t]++; s.clear(); for (int i = 2; i <= lim; i++) { if (x % i == 0) { s.insert(i); s.insert(x / i); } } s.insert(x); vector<int> rep; for (auto e : mp) rep.push_back(e.first); if (rep.size() == 2) { int mult = 1; for (auto e : mp) mult *= e.first; vector<int> ds; if (mult == x) { printf( %d , mult); for (int p : rep) { for (int div : s) { if (div % p == 0) { if (div != mult) { printf( %d , div); } ds.push_back(div); } } for (int e : ds) s.erase(e); ds.clear(); } printf( n1 n ); } else { printf( %d , x); vector<int> ds; for (int p : rep) { for (int div : s) { if (div % p == 0) { if (div != mult) { if (div != x) { printf( %d , div); } } ds.push_back(div); } } for (int e : ds) s.erase(e); ds.clear(); if (p != rep.back()) printf( %d , mult); } printf( n0 n ); } } else if (rep.size() == 1) { for (int div : s) { printf( %d , div); } printf( n0 n ); } else { map<int, int> joint; for (int i = 0; i < rep.size(); i++) { joint[rep[i] * rep[(i + 1) % rep.size()]] = true; } vector<int> ds; for (int i = 0; i < rep.size(); i++) { for (int div : s) { if (div % rep[i] == 0) { if (joint.count(div) == 0) { printf( %d , div); } ds.push_back(div); } } printf( %d , rep[i] * rep[(i + 1) % rep.size()]); for (int e : ds) s.erase(e); ds.clear(); } printf( n0 n ); } } } |
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : bd_mig_7series_0_0.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module bd_mig_7series_0_0 (
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output ui_addn_clk_0,
output ui_addn_clk_1,
output ui_addn_clk_2,
output ui_addn_clk_3,
output ui_addn_clk_4,
output mmcm_locked,
input aresetn,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [3:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [3:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [3:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [3:0] s_axi_rid,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
bd_mig_7series_0_0_mig u_bd_mig_7series_0_0_mig (
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.ui_addn_clk_0 (ui_addn_clk_0),
.ui_addn_clk_1 (ui_addn_clk_1),
.ui_addn_clk_2 (ui_addn_clk_2),
.ui_addn_clk_3 (ui_addn_clk_3),
.ui_addn_clk_4 (ui_addn_clk_4),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
// Reference Clock Ports
.clk_ref_i (clk_ref_i),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, v[1010]; long double p[1010][1010], a[1010], d[1010]; int work() { int k; long double x = 1e100L; for (int i = 1; i <= n; i++) if (!v[i] && (d[i] + a[i]) / (1 - a[i]) <= x) x = (d[i] + a[i]) / (1 - a[i]), k = i; v[k] = 1, d[k] = (d[k] + a[k]) / (1 - a[k]); if (k == 1) return 1; for (int i = 1; i <= n; i++) if (!v[i]) d[i] += a[i] * p[i][k] * (d[k] + 1), a[i] *= 1 - p[i][k]; return 0; } int main() { cin >> n; for (int i = 1, x; i <= n; i++) { for (int j = 1; j <= n; j++) cin >> x, p[i][j] = 0.01L * x; a[i] = 1; } a[n] = 0; for (int i = 1; i <= n; i++) if (work()) { cout << fixed << setprecision(15) << d[1]; return 0; } } |
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; bool comp(pair<long long, long long> p1, pair<long long, long long> p2) { if (p1.first != p2.first) { return p1.first < p2.first; } else return p2.second < p1.second; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; map<long long, vector<pair<long long, long long>>> m; for (long long i = 0; i < n; i++) { long long x, y; cin >> x >> y; long long level = max(x, y); m[level].push_back({x, y}); } vector<pair<long long, long long>> v; long long dp[200006][2]; memset(dp, INT_MAX, sizeof dp); dp[0][0] = 0; dp[0][1] = 0; pair<long long, long long> p_start, p_end; p_start = {0, 0}; p_start = {0, 0}; long long i = 1; for (auto it : m) { for (auto it1 : it.second) { v.push_back(it1); } sort(v.begin(), v.end(), comp); pair<long long, long long> start = v[0]; pair<long long, long long> end = v[v.size() - 1]; long long di = abs(start.first - end.first) + abs(start.second - end.second); long long a1 = dp[i - 1][0] + abs(p_start.first - end.first) + abs(p_start.second - end.second) + di; long long a2 = dp[i - 1][1] + abs(p_end.first - end.first) + abs(p_end.second - end.second) + di; dp[i][0] = min(a1, a2); a1 = dp[i - 1][0] + abs(p_start.first - start.first) + abs(p_start.second - start.second) + di; a2 = dp[i - 1][1] + abs(p_end.first - start.first) + abs(p_end.second - start.second) + di; dp[i][1] = min(a1, a2); p_start = start; p_end = end; v.clear(); i++; } cout << min(dp[i - 1][0], dp[i - 1][1]); return 0; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_64_1.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k, a[1000005], b[1000005]; int mi[1 << 20], mx[1 << 20], p[30], cs1[30], cs2[30], dp1[1 << 20], dp2[1 << 20], cs = 0; int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= k; ++i) scanf( %1d , &cs1[i]); for (int i = 1; i <= k; ++i) scanf( %1d , &cs2[i]); for (int i = 1; i <= k; ++i) cs -= cs1[i] + cs2[i]; cs += k; for (int i = 1; i <= n; ++i) scanf( %d%d , &a[i], &b[i]); memset(mi, 63, sizeof(mi)); memset(mx, -63, sizeof(mx)); for (int i = 1; i <= k; ++i) p[i] = i; int tp = 0; for (int i = 1; i <= k; ++i) tp |= cs2[i] << (i - 1); mx[tp] = max(mx[tp], n + 1); for (int i = n; i >= 1; --i) { int p1 = 0, p2 = 0; for (int j = 1; j <= k; ++j) if (p[j] == a[i] || p[j] == b[i]) p2 = p1, p1 = j; swap(p[p1], p[p2]); int w1 = 0, w2 = 0; for (int j = 1; j <= k; ++j) w1 |= cs1[p[j]] << (j - 1), w2 |= cs2[p[j]] << (j - 1); mi[w1] = min(mi[w1], i); mx[w2] = max(mx[w2], i); } int len = 1 << k, ans = 0, l = 0, r = 0; for (int i = len - 1; i >= 0; --i) { dp1[i] = mi[i]; dp2[i] = mx[i]; int sz = 0; for (int j = 0; j < k; ++j) { if (!((1 << j) & i)) ((dp1[i] > dp1[i | (1 << j)]) && (dp1[i] = dp1[i | (1 << j)])), ((dp2[i] < dp2[i | (1 << j)]) && (dp2[i] = dp2[i | (1 << j)])); else ++sz; } if (dp2[i] - dp1[i] >= m && 2 * sz + cs >= ans) ans = 2 * sz + cs, l = dp1[i], r = dp2[i] - 1; } printf( %d n , ans); printf( %d %d n , l, r); } |
#include <bits/stdc++.h> using namespace std; vector<array<int, 2>> tree(1); int terminal[110]; unsigned long long inf = (1ull << 63) - 1; int s; struct Mat { vector<unsigned long long> data; Mat() { data.assign(s * s, inf); } }; Mat operator*(const Mat& a, const Mat& b) { Mat r; for (int i = 0; i < s; i++) { for (int k = 0; k < s; k++) { for (int j = 0; j < s; j++) { r.data[i * s + j] = min(r.data[i * s + j], a.data[i * s + k] + b.data[k * s + j]); } } } return r; } int main() { ios::sync_with_stdio(0); cin.tie(0); int g, n, m; cin >> g >> n >> m; vector<pair<int, vector<int>>> mut; vector<vector<vector<int>>> node(g); for (int i = 0; i < n; i++) { int a, k; cin >> a >> k; node[a].push_back(vector<int>(k)); mut.emplace_back(a, vector<int>()); for (int& v : node[a].back()) { cin >> v; mut.back().second.push_back(v); } } for (int i = 0; i < m; i++) { int k; cin >> k; int p = 0; while (k--) { int c; cin >> c; if (!tree[p][c]) { tree[p][c] = tree.size(); tree.push_back({0, 0}); } p = tree[p][c]; } terminal[p] = 1; } { vector<int> link(tree.size()); queue<int> q; q.push(0); while (q.size()) { int p = q.front(); q.pop(); int par = link[p]; terminal[p] |= terminal[par]; for (int c : {0, 1}) { if (!tree[p][c]) { tree[p][c] = tree[par][c]; } else { link[tree[p][c]] = p ? tree[par][c] : 0; q.push(tree[p][c]); } } } } s = tree.size(); for (int p = 0; p < s; p++) if (terminal[p]) tree[p][0] = tree[p][1] = p; vector<Mat> mat(g); for (int c : {0, 1}) { for (int i = 0; i < s; i++) { mat[c].data[i * s + tree[i][c]] = 1; } } vector<int> changed(g, 1); while (1) { int found = 0; vector<int> nchanged(g); for (auto& [a, v] : mut) { int need = 0; for (int b : v) if (changed[b]) need = 1; if (!need) continue; Mat prod = mat[v[0]]; for (int i = 1; i < (int)v.size(); i++) { prod = prod * mat[v[i]]; } for (int i = 0; i < s * s; i++) { if (prod.data[i] < mat[a].data[i]) { mat[a].data[i] = prod.data[i]; nchanged[a] = 1; found = 1; } } } changed = nchanged; if (!found) break; } for (int a = 2; a < g; a++) { unsigned long long mi = inf; for (int i = 0; i < s; i++) { if (!terminal[i]) mi = min(mi, mat[a].data[i]); } if (mi < inf) cout << NO << mi << endl; else cout << YES << endl; } } |
/* amiga_clk_xilinx.v */
/* 2012, */
module amiga_clk_xilinx (
input wire areset,
input wire inclk0,
output wire c0,
output wire c1,
output wire c2,
output wire locked
);
// internal wires
wire pll_114;
wire dll_114;
wire dll_28;
reg [1:0] clk_7 = 0;
// pll
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(17), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(29), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(15.015), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) pll (
.CLKIN(inclk0), // Clock input (from IBUFG, BUFG or DCM)
.CLKFX(pll_114) // DCM CLK synthesis out (M/D) (113.611765 MHz)
);
// dll
DCM #(
.CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(8.802), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("FIXED"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(104), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) dll (
.RST(areset),
.CLKIN(pll_114), // Clock input (from IBUFG, BUFG or DCM)
.CLK0(dll_114),
.CLKDV(dll_28),
.CLKFB(c0),
.LOCKED(locked)
);
// 7MHz clock
always @ (posedge c1) begin
clk_7 <= #1 clk_7 + 2'd1;
end
// global clock buffers
BUFG BUFG_SDR (.I(pll_114), .O(c2));
BUFG BUFG_114 (.I(dll_114), .O(c0));
BUFG BUFG_28 (.I(dll_28), .O(c1));
//BUFG BUFG_7 (.I(clk_7[1]), .O(c3));
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ext_de1_sram.v
//
// *Module Description:
// openMSP430 interface with altera DE1's external async SRAM (256kwords x 16bits)
//
// *Author(s):
// - Vadim Akimov,
module ext_de1_sram(
input clk,
// ram interface with openmsp430 core
input [ADDR_WIDTH-1:0] ram_addr,
input ram_cen,
input [1:0] ram_wen,
input [15:0] ram_din,
output reg [15:0] ram_dout,
// DE1's sram signals
inout [15:0] SRAM_DQ,
output reg [17:0] SRAM_ADDR,
output reg SRAM_UB_N,
output reg SRAM_LB_N,
output reg SRAM_WE_N,
output reg SRAM_CE_N,
output reg SRAM_OE_N
);
parameter ADDR_WIDTH = 9; // [8:0] - 512 words of 16 bits (1 kB) are only addressed by default
// we assume SRAM is fast enough to accomodate 1-cycle access rate of openmsp430. Also it must be fast
// enough to provide read data half cycle after read access begins. It is highly recommended to
// set all SRAM_ signals as "Fast Output Register" in quartus. Also set Fast Enable Register for SRAM_DQ.
// SRAM used in DE1 has zero setup and hold times for address and data in write cycle, so we can write data
// in one clock cycle.
//
// we emulate ram_cen behavior by not changing read data when ram_cen=1 (last read data remain on ram_dout)
reg [15:0] sram_dout;
reg rnw; // =1 - read, =0 - write (Read-Not_Write)
reg ena; // enable
// address is always loaded from core
always @(negedge clk)
begin
SRAM_ADDR <= { {18-ADDR_WIDTH{1'b0}}, ram_addr[ADDR_WIDTH-1:0] };
end
// some control signals
always @(negedge clk)
begin
if( !ram_cen && !(&ram_wen) )
rnw <= 1'b0;
else
rnw <= 1'b1;
ena <= ~ram_cen;
end
// store data for write cycle
always @(negedge clk)
sram_dout <= ram_din;
// bus control
assign SRAM_DQ = rnw ? {16{1'bZ}} : sram_dout;
// read cycle - data latching
always @(posedge clk)
begin
if( ena && rnw )
ram_dout <= SRAM_DQ;
end
// SRAM access signals
always @(negedge clk)
begin
if( !ram_cen )
begin
if( &ram_wen[1:0] ) // read access
begin
SRAM_CE_N <= 1'b0;
SRAM_OE_N <= 1'b0;
SRAM_WE_N <= 1'b1;
SRAM_UB_N <= 1'b0;
SRAM_LB_N <= 1'b0;
end
else // !(&ram_wen[1:0]) - write access
begin
SRAM_CE_N <= 1'b0;
SRAM_OE_N <= 1'b1;
SRAM_WE_N <= 1'b0;
SRAM_UB_N <= ram_wen[1];
SRAM_LB_N <= ram_wen[0];
end
end
else // ram_cen - idle
begin
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
SRAM_WE_N <= 1'b1;
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_TB_V
`define SKY130_FD_SC_HS__DFBBN_TB_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfbbn.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 RESET_B = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 RESET_B = 1'b0;
#260 SET_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET_B = 1'b1;
#380 RESET_B = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET_B = 1'bx;
#480 RESET_B = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__dfbbn dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class T> T __sqr(const T x) { return x * x; } template <class T, class X> inline T __pow(T a, X y) { T z = 1; for (int i = 1; i <= y; i++) { z *= a; } return z; } template <class T> inline T gcd(T a, T b) { a = abs(a); b = abs(b); if (!b) return a; return __gcd(b, a % b); } template <class T> inline T lcm(T a, T b) { a = abs(a); b = abs(b); return (a / __gcd(a, b)) * b; } inline bool ispow2(int x) { return (x != 0 && (x & (x - 1)) == 0); } template <class T> void UpdateMin(T &x, T y) { if (y < x) { x = y; } } template <class T> void UpdateMax(T &x, T y) { if (x < y) { x = y; } } template <class T, class X, class Y> inline T bigmod(T n, X m, Y mod) { unsigned long long ret = 1, a = n % mod; while (m) { if (m & 1) ret = (ret * a) % mod; m >>= 1; a = (a * a) % mod; } ret %= mod; return (T)ret; } template <class T, class Y> inline T modinv(T n, Y mod) { return bigmod(n, mod - 2, mod); } template <class T, class X> int getbit(T s, X i) { return (s >> i) & 1; } template <class T, class X> T onbit(T s, X i) { return s | (T(1) << i); } template <class T, class X> T offbit(T s, X i) { return s & (~(T(1) << i)); } template <class T> inline void read(T &n) { char c; for (c = getchar(); !(c >= 0 && c <= 9 ); c = getchar()) ; n = c - 0 ; for (c = getchar(); c >= 0 && c <= 9 ; c = getchar()) n = n * 10 + c - 0 ; } void extended_euclid(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return; } long long first, second; extended_euclid(b, a % b, first, second); x = second; y = first - (a / b) * second; } pair<long long, pair<long long, long long> > extendedEuclid(long long a, long long b) { long long x = 1, y = 0; long long xLast = 0, yLast = 1; long long q, r, m, n; while (a != 0) { q = b / a; r = b % a; m = xLast - q * x; n = yLast - q * y; xLast = x, yLast = y; x = m, y = n; b = a, a = r; } return make_pair(b, make_pair(xLast, yLast)); } const long long mod[] = {0, 1000000007, 1000000009, 1000000021, 1000000033, 1000000097, 1000000093, 1000000097, 1000000103}; const long long base[] = {0, 1000003, 1000033, 1000037, 1000039, 1000081, 1000099, 1000117, 1000121}; char s[(300000 + 20)], ans[(300000 + 20)]; vector<int> cnt[50]; int fnd[50]; int main() { int m, n; scanf( %d , &m); scanf( %s , s); n = strlen(s); int tot = 0; int cov = -1; for (int i = 0; i < n; i++) { fnd[s[i] - a ]++; cnt[s[i] - a ].push_back(i); if (i == (cov + m)) { for (int j = 0; j < 26; j++) { if (cnt[j].empty()) continue; if (cnt[j].back() <= (i - m)) continue; ans[tot++] = s[cnt[j].back()]; fnd[s[cnt[j].back()] - a ]--; cov = cnt[j].back(); break; } } } ans[tot] = 0 ; sort(ans, ans + tot); int g = tot; for (int i = 0; i < (ans[g - 1] - a ); i++) { for (int j = 0; j < fnd[i]; j++) { ans[tot++] = a + i; } } ans[tot] = 0 ; sort(ans, ans + tot); puts(ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { #ifdef LOCAL freopen( ../IO/d.in , r , stdin); // freopen( ../IO/d.out , w , stdout); #else std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.tie(nullptr); #endif int number_of_tests; cin >> number_of_tests; while (number_of_tests--) { int n; cin >> n; std::vector<int> b(n); std::vector<int> used(2 * n); for (int &i : b) cin >> i, --i, used[i] = 1; std::vector<int> unused; unused.reserve(n); for (int i = 0; i < 2 * n; ++i) { if (!used[i]) unused.push_back(i); } vector<int> c(n + 1, true); int l = -1, r = -1; auto check1 = [&](int x) { deque<int> dq(unused.begin(), unused.end()); bool ok = true; for (int i = x - 1; i >= 0; --i) { ok &= b[i] < dq.back(); dq.pop_back(); } return ok; }; auto check2 = [&](int x) { deque<int> dq(unused.begin(), unused.end()); bool ok = true; for (int i = x; i < n; ++i) { ok &= b[i] > dq.front(); dq.pop_front(); } return ok; }; int lo = -1, hi = n + 1; while (hi - lo > 1) { int x = (lo + hi) / 2; if (check1(x)) { lo = x; } else { hi = x; } } l = 0, r = lo; lo = -1, hi = n + 1; while (hi - lo > 1) { int x = (lo + hi) / 2; if (check2(x)) { hi = x; } else { lo = x; } } l = std::max(l, hi); // std::cout << l << << r << n ; std::cout << std::max(0, r - l + 1) << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ls__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_ls__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_TB_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_TB_V
|
#include <bits/stdc++.h> using namespace std; int sign(long long x) { return x < 0 ? -1 : x > 0 ? 1 : 0; } struct point { long long x, y; point(long long a = 0, long long b = 0) : x(a), y(b) {} point operator-(point q) { return point(x - q.x, y - q.y); } long long operator%(point q) { return x * q.y - y * q.x; } }; point T[1001]; long long piso(long long A, long long B) { if (B < 0) A = -A, B = -B; if (A >= 0) return A / B; else return -((-A + B - 1) / B); } long long techo(long long A, long long B) { if (B < 0) A = -A, B = -B; if (A >= 0) return (A + B - 1) / B; else return A / B; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld %lld , &T[i].x, &T[i].y); if (T[2].y > T[0].y) { for (int i = 0; i < n; i++) T[i].y = -T[i].y; swap(T[0], T[1]); reverse(T + 2, T + n); } T[n] = T[0]; long long y = T[0].y; bool sirve = true; long long le = T[0].x, ri = T[1].x; for (int i = 2; i < n; i++) { long long der = T[1].x; long long izq = T[0].x; for (int j = 2; j < i; j++) if (abs(y - T[j].y) < abs(y - T[i].y)) { long long A = T[j].y - T[i].y; long long B = T[i].x - T[j].x; long long C = T[i].x * A + T[i].y * B; der = min(der, piso(C - B * y, A)); } if (i - 1 > 1) if (T[i].y == T[i - 1].y && T[i - 2].y > T[i].y && sign((T[i] - T[i - 1]) % (T[i] - T[i - 2])) <= 0) sirve = false; for (int j = i + 1; j < n; j++) if (abs(y - T[j].y) < abs(y - T[i].y)) { long long A = T[j].y - T[i].y; long long B = T[i].x - T[j].x; long long C = T[i].x * A + T[i].y * B; izq = max(izq, techo(C - B * y, A)); } if (i + 1 < n) if (T[i].y == T[i + 1].y && T[i + 2].y > T[i].y && sign((T[i] - T[i + 1]) % (T[i] - T[i + 2])) >= 0) sirve = false; if (der < izq) sirve = false; else if (ri < izq || der < le) sirve = false; else { le = max(izq, le); ri = min(der, ri); } } int res = ri - le + 1; if (!sirve) res = 0; cout << res << endl; } |
#include <bits/stdc++.h> const int N = 1e5 + 10; using namespace std; map<int, int> mp; struct a { int x, y, z; }; vector<a> res; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) { int t; cin >> t; mp[t]++; } priority_queue<pair<int, int>> pq; for (auto it = mp.begin(); it != mp.end(); ++it) { int fi = it->second; int se = it->first; pq.push({fi, se}); } while (pq.size() >= 3) { auto xx = pq.top(); pq.pop(); auto yy = pq.top(); pq.pop(); auto zz = pq.top(); pq.pop(); a temp; temp.x = xx.second; temp.y = yy.second; temp.z = zz.second; res.push_back(temp); if (xx.first - 1) { pq.push({xx.first - 1, xx.second}); } if (yy.first - 1) { pq.push({yy.first - 1, yy.second}); } if (zz.first - 1) { pq.push({zz.first - 1, zz.second}); } } cout << res.size() << n ; for (int i = 0; i < res.size(); ++i) { int b[3]; b[0] = res[i].x; b[1] = res[i].y; b[2] = res[i].z; sort(b, b + 3); cout << b[2] << << b[1] << << b[0] << n ; } } |
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } int main() { int T = read(); while (T--) { int n = read(), a = read(), flag = 0, k; for (int i = 2; i <= n; i++) { int b = read(); if (abs(a - b) >= 2) { k = i; flag = 1; } a = b; } if (flag) cout << YES n << k - 1 << << k << endl; else cout << NO n ; } return 0; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; vector<long long> a(n, 0); vector<long long> pos(32, 0); for (long long i = 0; i < n; i++) { cin >> a[i]; long long ind = 0; long long num = a[i]; while (num != 0) { if (num % 2 == 1) pos[ind] += 1; ind++; num /= 2; } } long long f = 0; for (long long i = pos.size() - 1; i >= 0; i--) { if (pos[i] % 2 == 1) { f = 1; if (pos[i] == 1) cout << WIN n ; else { if ((pos[i] / 2) % 2 == 0) cout << WIN n ; else { if (n % 2 == 0) cout << WIN n ; else cout << LOSE n ; } } break; } } if (f == 0) cout << DRAW n ; } } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long con = -1; long long a[n + 5]; for (long long i = 1; i <= n; i++) { cin >> a[i]; } long long i = 1; for (i = 1; i < n; i++) { if (a[i + 1] == a[i]) { con = i; break; } } if (con == -1) { for (con = 1; con < n; con++) { if (a[con] > a[con + 1]) { break; } } } for (i = 1; i < con; i++) { if (a[i + 1] < a[i]) { cout << NO << n ; return 0; } } while (a[con] == a[con + 1]) { con++; } for (i = con; i < n; i++) { if (a[i + 1] >= a[i]) { cout << NO << n ; return 0; } } cout << YES << n ; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1.01e9; const double eps = 1e-9; const int N = 22; double RES = 0; double rf, re, rs; double df, de; int cnt = 0; int a[N]; int ac = 0; int b[N]; int bc = 0; int nf, ne, ns; double e[N]; double FI[200]; double EN[200]; double FIRE(int p) { double res = rf * 2; for (int i = 0; (i) < (bc); ++i) res += FI[abs(b[i] - p)]; res *= df; return res; } double ENERGY(int p) { double res = re * 2; for (int i = 0; (i) < (bc); ++i) res += EN[abs(b[i] - p)]; res *= de; return res; } void solve() { double val = 0; for (int i = 0; (i) < (ac); ++i) { double x = FIRE(a[i]); double y = ENERGY(a[i]); e[i] = x - y; val += y; } sort(e, e + ac); reverse(e, e + ac); for (int i = 0; (i) < (nf); ++i) val += e[i]; RES = max(RES, val); } void go(int x, int y, int pos, int cnt1 = 0, int cnt2 = 0) { if (x == 0 && y == 0) { cnt++; solve(); return; } if (x >= 1 && cnt1 < 2) { a[ac++] = pos; go(x - 1, y, pos + 1, cnt1 + 1, cnt2); ac--; } if (x >= 2) { a[ac++] = pos; a[ac++] = pos; go(x - 2, y, pos + 1, cnt1, cnt2); ac--; ac--; } if (y >= 1 && cnt2 < 1) { b[bc++] = pos; go(x, y - 1, pos + 1, cnt1, cnt2 + 1); bc--; } if (y >= 2) { b[bc++] = pos; b[bc++] = pos; go(x, y - 2, pos + 1, cnt1, cnt2); bc--; bc--; } if (x >= 1 && y >= 1) { a[ac++] = pos; b[bc++] = pos; go(x - 1, y - 1, pos + 1, cnt1, cnt2); ac--; bc--; } } int main() { scanf( %d%d%d , &nf, &ne, &ns); scanf( %lf%lf%lf , &rf, &re, &rs); scanf( %lf%lf , &df, &de); rf = sqrt(max(0., rf * rf - 1)); re = sqrt(max(0., re * re - 1)); rs = sqrt(max(0., rs * rs - 1)); for (int i = 0; i < 100; ++i) { double l1 = -rf; double r1 = rf; double l2 = i - rs; double r2 = i + rs; FI[i] = max(0., min(r1, r2) - max(l1, l2)); } for (int i = 0; i < 100; ++i) { double l1 = -re; double r1 = re; double l2 = i - rs; double r2 = i + rs; EN[i] = max(0., min(r1, r2) - max(l1, l2)); } go(nf + ne, ns, 0); fprintf(stderr, %d n , cnt), fflush(stderr); printf( %.10f n , RES); return 0; } |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
mulRecF16 (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
mulRecFN#(5, 11)
mulRecFN(control, a, b, roundingMode, out, exceptionFlags);
endmodule
module
mulRecF32 (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
mulRecFN#(8, 24)
mulRecFN(control, a, b, roundingMode, out, exceptionFlags);
endmodule
module
mulRecF64 (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
mulRecFN#(11, 53)
mulRecFN(control, a, b, roundingMode, out, exceptionFlags);
endmodule
module
mulRecF128 (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
mulRecFN#(15, 113)
mulRecFN(control, a, b, roundingMode, out, exceptionFlags);
endmodule
|
module crossbar
(
input wire [47:0] north_channel,
input wire [47:0] east_channel,
input wire [47:0] pe_in_channel,
// LSB selects between North and East inports
// MSB selects between PE and the selection between North and East
input wire [1:0] south_ctrl,
input wire [1:0] west_ctrl,
input wire pe_out_ctrl,
output wire [47:0] south_channel,
output wire [47:0] west_channel,
output wire [39:0] pe_out_channel
);
// South outport
wire [47:0] south_mux0_output;
m21x48 m21x48_south_mux0(
.sel (south_ctrl[0]),
.a (north_channel),
.b (east_channel),
.o (south_mux0_output)
); // m21x48_south_mux0
m21x48 m21x48_south_mux1(
.sel (south_ctrl[1]),
.a (pe_in_channel),
.b (south_mux0_output),
.o (south_channel)
); // m21x48_south_mux1
// West outport
wire [47:0] west_mux0_output;
m21x48 m21x48_west_mux0(
.sel (west_ctrl[0]),
.a (north_channel),
.b (east_channel),
.o (west_mux0_output)
); // m21x48_west_mux0
m21x48 m21x48_west_mux1(
.sel (west_ctrl[1]),
.a (pe_in_channel),
.b (west_mux0_output),
.o (west_channel)
); // m21x48_west_mux1
// PE outport
m21x40 m21x40_pe(
.sel (pe_out_ctrl),
.a (north_channel[39:0]),
.b (east_channel[39:0]),
.o (pe_out_channel)
); // m21x48_pe
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { map<char, int> mapdown, mapup, mapleft, mapright; char keys[10] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 }; int n, count1 = 0, count2 = 0, count3 = 0, count4 = 0; char str[15]; mapdown.clear(); mapup.clear(); mapleft.clear(); mapright.clear(); scanf( %d , &n); scanf( %s , str); for (int i = 0; i < 10; i++) { char c = keys[i]; if (keys[i] == 7 || keys[i] == 0 || keys[i] == 9 ) { mapdown.insert(make_pair(c, 0)); } else { mapdown.insert(make_pair(c, 1)); } } for (int i = 0; i < 10; i++) { if (keys[i] == 1 || keys[i] == 2 || keys[i] == 3 ) mapup.insert(make_pair(keys[i], 0)); else mapup.insert(make_pair(keys[i], 1)); } for (int i = 0; i < 10; i++) { if (keys[i] == 3 || keys[i] == 6 || keys[i] == 9 || keys[i] == 0 ) mapright.insert(make_pair(keys[i], 0)); else mapright.insert(make_pair(keys[i], 1)); } for (int i = 0; i < 10; i++) { if (keys[i] == 1 || keys[i] == 4 || keys[i] == 7 || keys[i] == 0 ) mapleft.insert(make_pair(keys[i], 0)); else mapleft.insert(make_pair(keys[i], 1)); } for (int i = 0; i < n; i++) { if (mapdown[str[i]] != 0) count1++; } for (int i = 0; i < n; i++) { if (mapup[str[i]] != 0) count2++; } for (int i = 0; i < n; i++) { if (mapleft[str[i]] != 0) count3++; } for (int i = 0; i < n; i++) { if (mapright[str[i]] != 0) count4++; } if (count1 == n || count2 == n || count3 == n || count4 == n) printf( NO ); else printf( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2000005; template <typename T> void read(T &x) { x = 0; int f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } template <typename T> void write(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } template <typename T> void writeln(T x) { write(x); puts( ); } int n, m1, m2, m, t; int x1[MAXN], x2[MAXN]; int mid1[MAXN], mid2[MAXN]; int pos1[MAXN], pos2[MAXN]; int dp[3][MAXN], path[3][MAXN], pos[MAXN]; int main() { read(n), read(m1), read(m2), read(t); for (int i = 1; i <= m1; i++) read(x1[i]); for (int i = 1; i <= m2; i++) read(x2[i]); pos[++m] = 0; int p1 = 1, p2 = 1; while (p1 <= m1 || p2 <= m2) { if (p1 > m1) pos[++m] = x2[p2++] + 1; else if (p2 > m2) pos[++m] = x1[p1++] + 1; else { int Min = min(x1[p1], x2[p2]); pos[++m] = Min + 1; if (Min == x1[p1]) p1++; if (Min == x2[p2]) p2++; } } if (pos[m] != n + 1) pos[++m] = n + 1; p1 = 1; for (int i = 1; i <= m1; i++) { while (x1[i] > pos[p1]) p1++; if (pos[p1] > x1[i]) mid1[p1] = x1[i]; pos1[p1] += x1[i] == pos[p1]; } p2 = 1; for (int i = 1; i <= m2; i++) { while (x2[i] > pos[p2]) p2++; if (pos[p2] > x2[i]) mid2[p2] = x2[i]; pos2[p2] += x2[i] == pos[p2]; } memset(dp, -1, sizeof(dp)); dp[1][1] = 0; for (int i = 1; i <= m - 1; i++) { if (dp[1][i] != -1 && pos2[i] == 0) { int tmp = min(dp[1][i], t); if (tmp > dp[2][i]) { dp[2][i] = tmp; path[2][i] = 1; } } if (dp[2][i] != -1 && pos1[i] == 0) { int tmp = min(dp[2][i], t); if (tmp > dp[1][i]) { dp[1][i] = tmp; path[1][i] = 1; } } if (dp[1][i] != -1) { int tmp = dp[1][i]; if (pos1[i + 1] == 0 && mid1[i + 1] == 0) tmp += pos[i + 1] - pos[i]; if (pos1[i + 1] == 0 && mid1[i + 1] != 0) { tmp += mid1[i + 1] - pos[i] - 1; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += pos[i + 1] - mid1[i + 1] + 1; } if (pos1[i + 1] != 0 && mid1[i + 1] == 0) { tmp += pos[i + 1] - pos[i] - 1; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += 1; } if (pos1[i + 1] != 0 && mid1[i + 1] != 0) { tmp += mid1[i + 1] - pos[i] - 1; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += pos[i + 1] - mid1[i + 1]; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += 1; } dp[1][i + 1] = tmp; } if (dp[2][i] != -1) { int tmp = dp[2][i]; if (pos2[i + 1] == 0 && mid2[i + 1] == 0) tmp += pos[i + 1] - pos[i]; if (pos2[i + 1] == 0 && mid2[i + 1] != 0) { tmp += mid2[i + 1] - pos[i] - 1; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += pos[i + 1] - mid2[i + 1] + 1; } if (pos2[i + 1] != 0 && mid2[i + 1] == 0) { tmp += pos[i + 1] - pos[i] - 1; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += 1; } if (pos2[i + 1] != 0 && mid2[i + 1] != 0) { tmp += mid2[i + 1] - pos[i] - 1; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += pos[i + 1] - mid2[i + 1]; if (tmp < t) tmp = -1; else tmp -= t; if (tmp != -1) tmp += 1; } dp[2][i + 1] = tmp; } } if (dp[1][m] == -1 && dp[2][m] == -1) { printf( No n ); return 0; } printf( Yes n ); int px, py; if (dp[1][m] == -1) py = 2, px = m; else py = 1, px = m; static int shifts[MAXN], cnts = 0; static int x[MAXN], y[MAXN], cnt = 0; int now = 0; while (px != 1 || py != 1) { if (path[py][px]) { cnt += now; int tx = pos[px] - dp[py][px]; for (int i = 1; i <= now; i++) { tx += t; x[cnt - i + 1] = tx; y[cnt - i + 1] = py; } py = 3 - py; now = 0; shifts[++cnts] = pos[px]; } else { if (py == 1) now += mid1[px] != 0, now += pos1[px] != 0; else now += mid2[px] != 0, now += pos2[px] != 0; px = px - 1; } } cnt += now; int tx = 0; for (int i = 1; i <= now; i++) { tx += t; x[cnt - i + 1] = tx; y[cnt - i + 1] = py; } writeln(cnts); reverse(shifts + 1, shifts + cnts + 1); for (int i = 1; i <= cnts; i++) printf( %d , shifts[i]); printf( n ); writeln(cnt); reverse(x + 1, x + cnt + 1); reverse(y + 1, y + cnt + 1); for (int i = 1; i <= cnt; i++) printf( %d %d n , x[i], y[i]); return 0; } |
module peripheral_bt(clk , rst , d_in , cs , addr , rd , wr, d_out, uart_tx, uart_rx );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output uart_rx;
output uart_tx;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and demux_4
reg uart_enable;
reg [7:0] din_uart; // data in uart
wire [7:0] dout_uart;
wire uart_busy; // out_uart
wire uart_done;
wire uart_avail;
//------------------------------------ regs and wires-------------------------------
bluetooth bt(.rx(uart_rx), .avail(uart_avail), .clk_in(clk), .reset(rst), .dout(dout_uart), .din(din_uart), .enable(uart_enable), .busy(uart_busy), .done(uart_done), .tx(uart_tx));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end //din_uart
4'h2:begin s = (cs && rd) ? 5'b00010 : 5'b00000 ;end //done
4'h4:begin s = (cs && rd) ? 5'b00100 : 5'b00000 ;end //avail
4'h6:begin s = (cs && rd) ? 5'b01000 : 5'b00000 ;end //busy
4'h8:begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end //dout_uart <asdfghjkl
default:begin s=5'b00000 ; end
endcase
end//-----------------address_decoder--------------------
wire busymachete= (uart_busy | uart_enable);
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1) begin
din_uart<=d_in[7:0];
uart_enable=1;
end
else begin
if (uart_busy)
uart_enable=0;
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
5'b01000: d_out[0]= busymachete;
5'b00010: d_out[0]= uart_done;
5'b00100: d_out[0]= uart_avail;
5'b10000: d_out[7:0] = dout_uart;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
#include <bits/stdc++.h> using namespace std; const double inf = 1e13; const double eps = 1e-9; int Sgn(double k) { return fabs(k) < eps ? 0 : (k < 0 ? -1 : 1); } int Cmp(double k1, double k2) { return Sgn(k1 - k2); } struct Point { double x, y; }; Point operator-(Point k1, Point k2) { return (Point){k1.x - k2.x, k1.y - k2.y}; } Point operator+(Point k1, Point k2) { return (Point){k1.x + k2.x, k1.y + k2.y}; } double operator*(Point k1, Point k2) { return k1.x * k2.x + k1.y * k2.y; } double operator^(Point k1, Point k2) { return k1.x * k2.y - k1.y * k2.x; } Point operator*(Point k1, double k2) { return (Point){k1.x * k2, k1.y * k2}; } Point operator/(Point k1, double k2) { return (Point){k1.x / k2, k1.y / k2}; } double GetLen(Point k) { return sqrt(k * k); } double GetDisPointToPoint(Point k1, Point k2) { return sqrt((k2 - k1) * (k2 - k1)); } Point Rotate(Point k, double ang) { return (Point){k.x * cos(ang) - k.y * sin(ang), k.x * sin(ang) + k.y * cos(ang)}; } Point Rotate90(Point k) { return (Point){-k.y, k.x}; } struct Circle { Point o; double r; }; bool IsInside(Circle k1, Circle k2) { double dis = GetDisPointToPoint(k1.o, k2.o); if (Cmp(k1.r - k2.r, dis) >= 0 || Cmp(k2.r - k1.r, dis) >= 0) return true; return false; } bool IsOutside(Circle k1, Circle k2) { double dis = GetDisPointToPoint(k1.o, k2.o); if (Cmp(dis, k1.r + k2.r) > 0) return true; return false; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cout << fixed << setprecision(10); Point s, t; cin >> s.x >> s.y >> t.x >> t.y; int n; cin >> n; vector<Circle> c(n); for (auto &it : c) cin >> it.o.x >> it.o.y >> it.r; Point mid_point = (s + t) / 2.0; Point dir = Rotate90(t - s) / GetLen(t - s); double dis_div2 = GetDisPointToPoint(s, mid_point); bool ans_flag = true; for (auto &it : c) { Circle cur = (Circle){mid_point, dis_div2}; if (!IsInside(cur, it) && !IsOutside(cur, it)) { ans_flag = false; break; } } if (ans_flag) { cout << dis_div2 << endl; return 0; } vector<pair<double, double>> record; for (auto &it : c) { bool dir_flag; if (Sgn((it.o - mid_point) * dir) > 0) dir_flag = true; else dir_flag = false; double inside_record, outside_record; Circle binary_search_cur; int binary_search_cnt = 0; double binary_search_left = -inf, binary_search_right = inf; while (Cmp(binary_search_left, binary_search_right) && binary_search_cnt++ < 100) { double binary_search_mid = (binary_search_left + binary_search_right) / 2.0; binary_search_cur.o = dir * binary_search_mid + mid_point; binary_search_cur.r = sqrt(binary_search_mid * binary_search_mid + dis_div2 * dis_div2); if (IsInside(binary_search_cur, it)) { inside_record = binary_search_mid; if (dir_flag) binary_search_right = binary_search_mid; else binary_search_left = binary_search_mid; } else { if (dir_flag) binary_search_left = binary_search_mid; else binary_search_right = binary_search_mid; } } binary_search_cnt = 0; binary_search_left = -inf, binary_search_right = inf; while (Cmp(binary_search_left, binary_search_right) && binary_search_cnt++ < 100) { double binary_search_mid = (binary_search_left + binary_search_right) / 2.0; binary_search_cur.o = dir * binary_search_mid + mid_point; binary_search_cur.r = sqrt(binary_search_mid * binary_search_mid + dis_div2 * dis_div2); if (IsOutside(binary_search_cur, it)) { outside_record = binary_search_mid; if (dir_flag) binary_search_left = binary_search_mid; else binary_search_right = binary_search_mid; } else { if (dir_flag) binary_search_right = binary_search_mid; else binary_search_left = binary_search_mid; } } if (Cmp(inside_record, outside_record) > 0) swap(inside_record, outside_record); record.push_back(make_pair(inside_record, outside_record)); } sort(record.begin(), record.end(), [&](pair<double, double> k1, pair<double, double> k2) { return Cmp(k1.first, k2.first) < 0; }); double ans = Cmp(-record[0].first, 0.0) > 0 ? -record[0].first : 0.0; double fi = record[0].first, se = record[0].second; for (int i = 1; i < record.size(); ++i) { if (Cmp(se, record[i].first) < 0) { if (Cmp(ans, fabs(se)) > 0) ans = fabs(se); if (Cmp(ans, fabs(record[i].first)) > 0) ans = fabs(record[i].first); fi = record[i].first; } if (Cmp(record[i].second, se) > 0) se = record[i].second; } if (Cmp(ans, fabs(se)) > 0) ans = fabs(se); cout << sqrt(ans * ans + dis_div2 * dis_div2) << endl; return 0; } |
`timescale 1 ps / 1 ps
module alt_mem_ddrx_input_if
#(parameter
CFG_LOCAL_DATA_WIDTH = 64,
CFG_LOCAL_ID_WIDTH = 8,
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_MEM_IF_CHIP = 1,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL"
)
(
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
itf_rd_data_id_early,
itf_rd_data_id_early_valid,
// command generator
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
cmd_id,
// write data path
wr_data_mem_full,
write_data_id,
write_data,
byte_en,
write_data_valid,
// read data path
read_data,
read_data_valid,
read_data_error,
read_data_localid,
read_data_begin,
read_data_last,
//side band
local_refresh_req,
local_refresh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_self_rfsh_req,
local_self_rfsh_chip,
local_refresh_ack,
local_deep_powerdn_ack,
local_power_down_ack,
local_self_rfsh_ack,
local_init_done,
bg_do_read,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_localid,
rfsh_req,
rfsh_chip,
deep_powerdn_req,
deep_powerdn_chip,
self_rfsh_req,
self_rfsh_chip,
rfsh_ack,
deep_powerdn_ack,
power_down_ack,
self_rfsh_ack,
init_done
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
// command channel
output itf_cmd_ready;
input [CFG_LOCAL_ADDR_WIDTH-1:0] itf_cmd_address;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] itf_wr_data;
input [CFG_LOCAL_DATA_WIDTH/8-1:0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
// read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
output [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
output itf_rd_data_id_early_valid;
// command generator
input cmd_gen_full;
output cmd_valid;
output [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
output cmd_write;
output cmd_read;
output cmd_multicast;
output [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
output cmd_priority;
output cmd_autoprecharge;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
// write data path
output [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
output [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
output write_data_valid;
input wr_data_mem_full;
output [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
// read data path
input [CFG_LOCAL_DATA_WIDTH-1:0] read_data;
input read_data_valid;
input read_data_error;
input [CFG_LOCAL_ID_WIDTH-1:0]read_data_localid;
input read_data_begin;
input read_data_last;
//side band
input local_refresh_req;
input [CFG_MEM_IF_CHIP-1:0] local_refresh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP-1:0] local_deep_powerdn_chip;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP-1:0] local_self_rfsh_chip;
output local_refresh_ack;
output local_deep_powerdn_ack;
output local_power_down_ack;
output local_self_rfsh_ack;
output local_init_done;
//side band
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
output deep_powerdn_req;
output [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
output self_rfsh_req;
output [CFG_MEM_IF_CHIP-1:0] self_rfsh_chip;
input rfsh_ack;
input deep_powerdn_ack;
input power_down_ack;
input self_rfsh_ack;
input init_done;
// command generator
wire cmd_priority;
wire [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
wire cmd_read;
wire cmd_write;
wire cmd_multicast;
wire cmd_gen_full;
wire cmd_valid;
wire itf_cmd_ready;
wire cmd_autoprecharge;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
//side band
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
wire rfsh_req;
wire [CFG_MEM_IF_CHIP-1:0] rfsh_chip;
wire deep_powerdn_req;
wire [CFG_MEM_IF_CHIP-1:0] deep_powerdn_chip;
wire self_rfsh_req;
//wire rfsh_ack;
//wire deep_powerdn_ack;
wire power_down_ack;
//wire self_rfsh_ack;
// wire init_done;
//write data path
wire itf_wr_data_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire write_data_valid;
wire [CFG_LOCAL_DATA_WIDTH/8-1:0] byte_en;
wire [CFG_LOCAL_ID_WIDTH-1:0] write_data_id;
//read data path
wire itf_rd_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] itf_rd_data;
wire itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
wire [CFG_LOCAL_ID_WIDTH-1:0] itf_rd_data_id_early;
wire itf_rd_data_id_early_valid;
// commmand generator
assign cmd_priority = itf_cmd_priority;
assign cmd_address = itf_cmd_address;
assign cmd_read = ~itf_cmd & itf_cmd_valid;
assign cmd_write = itf_cmd & itf_cmd_valid;
assign cmd_multicast = itf_cmd_multicast;
assign cmd_size = itf_cmd_burstlen;
assign cmd_valid = itf_cmd_valid;
assign itf_cmd_ready = ~cmd_gen_full;
assign cmd_autoprecharge = itf_cmd_autopercharge;
assign cmd_id = itf_cmd_id;
// side band
assign rfsh_req = local_refresh_req;
assign rfsh_chip = local_refresh_chip;
assign deep_powerdn_req = local_deep_powerdn_req;
assign deep_powerdn_chip = local_deep_powerdn_chip;
assign self_rfsh_req = local_self_rfsh_req;
assign self_rfsh_chip = local_self_rfsh_chip;
assign local_refresh_ack = rfsh_ack;
assign local_deep_powerdn_ack = deep_powerdn_ack;
assign local_power_down_ack = power_down_ack;
assign local_self_rfsh_ack = self_rfsh_ack;
assign local_init_done = init_done;
//write data path
assign write_data = itf_wr_data;
assign byte_en = itf_wr_data_byte_en;
assign itf_wr_data_ready = ~wr_data_mem_full;
assign write_data_valid = itf_wr_data_valid;
assign write_data_id = itf_wr_data_id;
// read data path
assign itf_rd_data_id = read_data_localid;
assign itf_rd_data_error = read_data_error;
assign itf_rd_data_valid = read_data_valid;
assign itf_rd_data_begin = read_data_begin;
assign itf_rd_data_last = read_data_last;
assign itf_rd_data = read_data;
assign itf_rd_data_id_early = (itf_rd_data_id_early_valid) ? bg_localid : {CFG_LOCAL_ID_WIDTH{1'b0}};
generate
begin : gen_rd_data_id_early_valid
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_LOW_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_LOW_PHASE]|bg_do_rmw_partial[AFI_INTF_LOW_PHASE]);
end
else
begin
assign itf_rd_data_id_early_valid = bg_do_read [AFI_INTF_HIGH_PHASE] & ~(bg_do_rmw_correct[AFI_INTF_HIGH_PHASE]|bg_do_rmw_partial[AFI_INTF_HIGH_PHASE]);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long i, j, flag, c, k, x, z, n, m, a[300007]; int main() { cin >> n; long long lst0 = 0, lst1 = 1; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 0) lst0 = i + 1; else lst1 = i + 1; } cout << min(lst0, lst1) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void Read(T &x) { int f = 1; char t = getchar(); while (t < 0 || t > 9 ) { if (t == - ) f = -1; t = getchar(); } x = 0; while (t >= 0 && t <= 9 ) { x = x * 10 + t - 0 ; t = getchar(); } x *= f; } const int modulo = 1000000007; const int maxn = 1000005; int p, k; int fst[maxn], v[maxn << 1], nxt[maxn << 1], e_cn; bool flag[maxn], vis[maxn], cycle; void addedge(int x, int y) { e_cn++; v[e_cn] = y, nxt[e_cn] = fst[x], fst[x] = e_cn; } void input() { Read(p), Read(k); } int pwr(long long x, long long k) { long long re = 1; while (k > 0) { if (k & 1) re = 1ll * re * x % modulo; x = 1ll * x * x % modulo; k >>= 1; } return re; } void dfs(int cn) { vis[cn] = true; cycle |= flag[cn]; for (register int i = fst[cn]; i; i = nxt[i]) { if (!vis[v[i]]) { dfs(v[i]); } } } void solve() { if (k == 0) { cout << pwr(p, p - 1) << endl; return; } if (k == 1) { cout << pwr(p, p) << endl; return; } long long ans = 1; for (register int i = 0; i < p; i++) { int x = i, y = 1ll * i * k % p; if (x == y) flag[x] = true; else addedge(x, y), addedge(y, x); } for (register int i = 0; i < p; i++) { if (!vis[i]) { cycle = false; dfs(i); if (!cycle) ans = 1ll * ans * p % modulo; } } cout << ans << endl; } int main() { input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1 << 18; const long long INF = 0x3f3f3f3f; int n, k; bool fav[MAXN]; long long dp[MAXN][18][2][2]; inline void get_max(long long &, long long); int main() { scanf( %d%d , &n, &k); for (register int i = 1; i <= k; ++i) { int tmp; scanf( %d , &tmp); fav[tmp - 1] = true; } for (int k = 0; k < (1 << n); ++k) for (int t = 1; t <= n; ++t) for (int a = 0; a <= 1; ++a) for (int b = 0; b <= 1; ++b) dp[k][t][a][b] = -INF; for (int i = 0; i < (1 << n - 1); ++i) dp[i][1][fav[i << 1]][fav[i << 1 | 1]] = dp[i][1][fav[i << 1 | 1]][fav[i << 1]] = fav[i << 1] | fav[i << 1 | 1]; for (int t = 2; t <= n; ++t) for (int k = 0; k < (1 << n - t); ++k) { for (register int a = 0; a <= 1; ++a) for (register int b = 0; b <= 1; ++b) for (register int c = 0; c <= 1; ++c) for (register int d = 0; d <= 1; ++d) { get_max(dp[k][t][a][c], dp[k << 1][t - 1][a][b] + dp[k << 1 | 1][t - 1][c][d] + (a | c) + (b | d) + max(c | b, c | d)); get_max(dp[k][t][a][b], dp[k << 1][t - 1][a][b] + dp[k << 1 | 1][t - 1][c][d] + (a | c) + (b | d) + (b | c)); get_max(dp[k][t][a][d], dp[k << 1][t - 1][a][b] + dp[k << 1 | 1][t - 1][c][d] + (a | c) + (b | d) + (d | c)); get_max(dp[k][t][c][a], dp[k << 1][t - 1][a][b] + dp[k << 1 | 1][t - 1][c][d] + (a | c) + (b | d) + max(a | b, a | d)); get_max(dp[k][t][c][b], dp[k << 1][t - 1][a][b] + dp[k << 1 | 1][t - 1][c][d] + (a | c) + (b | d) + (a | b)); get_max(dp[k][t][c][d], dp[k << 1][t - 1][a][b] + dp[k << 1 | 1][t - 1][c][d] + (a | c) + (b | d) + (a | d)); } } printf( %lld n , max(max(dp[0][n][0][0], dp[0][n][0][1] + 1), max(dp[0][n][1][0] + 1, dp[0][n][1][1] + 1))); return 0; } inline void get_max(long long &a, long long b) { a = max(a, b); } |
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