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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(20); string s; cin >> s; double x = 10 * (s[0] - 0 ) + s[1] - 0 ; double y = 10 * (s[3] - 0 ) + s[4] - 0 ; if (x < 12) { cout << fixed << x * 30 + y / 2 << << 6 * y << setprecision(10) << ; } else { cout << fixed << (x - 12) * 30 + y / 2 << << 6 * y << setprecision(10) << ; } } |
#include <bits/stdc++.h> using namespace std; long long n, m, k, mod = 1e9 + 7; map<long long, long long> mp; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); srand(time(0)); cin >> n >> k; vector<long long> a(n + 2); vector<long long> b(k + 2); for (long long i = 1; i <= n; ++i) cin >> a[i], a[i] -= i; a[0] = -2e9; a[n + 1] = 2e9; b[k + 1] = n + 1; for (long long i = 1; i <= k; ++i) cin >> b[i]; long long ans = 0; for (long long i = 0; i <= k; ++i) { long long l = b[i]; long long r = b[i + 1]; if (a[l] > a[r]) { cout << -1; exit(0); } vector<long long> v; for (long long j = l + 1; j < r; ++j) { if (a[j] > a[r] || a[j] < a[l]) continue; auto x = upper_bound(v.begin(), v.end(), a[j]); if (x == v.end()) v.push_back(a[j]); else *x = a[j]; } ans += r - l - 1 - v.size(); } cout << ans; } |
// Icarus 0.6, snapshot 20020907
// ==================================================
// -- confused by disables from within a fork -- vvp fails
//
// -- to run, incant
// iverilog tt.v
// vvp a.out
//
// Veriwell
// ========
// -- OK
//
module top;
integer simple_fail, loop_fail, fork_fail, tlp_fail;
integer tfk_fail, tfk2_fail, tfk3_fail;
integer tfk2pos, tfk2nega, tfk2negb;
integer tfk3pos, tfk3nega, tfk3negb;
integer loop_cntr, tlp_cntr;
reg fred, abort;
initial begin
#1;
simple_fail = 0;
loop_fail = 0;
fork_fail = 0;
tlp_fail = 0;
tfk_fail = 0;
tfk2_fail = 0;
tfk2pos = 0;
tfk2nega = 1;
tfk2negb = 1;
tfk3pos = 0;
tfk3nega = 1;
tfk3negb = 1;
fred = 0;
abort = 1;
#4;
fred = 1;
#4
$display("Check disable:");
if(simple_fail) $display("***** simple block FAILED *****");
else $display("***** simple block PASSED *****");
if(loop_fail) $display("***** block with loop FAILED *****");
else $display("***** block with loop PASSED *****");
if(fork_fail) $display("***** forked block FAILED *****");
else $display("***** forked block PASSED *****");
if(tlp_fail) $display("***** task with loop FAILED *****");
else $display("***** task with loop PASSED *****");
if(tfk_fail) $display("***** task with forked block FAILED *****");
else $display("***** task with forked block PASSED *****");
if(tfk2_fail) $display("***** one forked block FAILED *****");
else $display("***** one forked block PASSED *****");
if(tfk3_fail) $display("***** the other forked block FAILED *****");
else $display("***** the other forked block PASSED *****");
$display("");
$finish(0);
end
// simple block disable
initial begin: block_name
#2;
disable block_name;
simple_fail = 1;
end
// more complex: block disable inside for-loop
initial begin
#2;
begin: configloop
for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin
wait (fred);
if (abort) begin
disable configloop;
end
loop_fail = 1;
end
end // configloop block
if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr);
end
// still more complex: disable from within a forked block
initial begin
#2;
begin: forked_tasks
fork
begin
#5;
fork_fail = 1;
end
begin
@(fred);
disable forked_tasks;
fork_fail = 1;
end
join
fork_fail = 1;
end //forked_tasks
end
// disables inside tasks
initial begin
task_with_loop;
end
initial begin
task_with_fork;
end
initial begin
task_with_fork2;
if(tfk2pos || tfk2nega || tfk2negb) tfk2_fail = 1;
end
initial begin
task_with_fork3;
if(tfk3pos || tfk3nega || tfk3negb) tfk3_fail = 1;
end
task task_with_loop;
begin
#2;
begin: configtlp
for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin
wait (fred);
if (abort) begin
disable configtlp;
end
tlp_fail = 1;
end
end // configloop block
end
endtask // task_with_loop
task task_with_fork; // disable block whick calls fork
begin
#2;
begin: forked_tasks_in_task
fork
begin: alf
#5;
tfk_fail = 1;
end
begin: bet
@(fred);
disable forked_tasks_in_task;
tfk_fail = 1;
end
join
tfk_fail = 1;
end //forked_tasks_in_task
end
endtask // task_with_fork
task task_with_fork2; // disable *one* of the forked blocks
begin
#2;
begin: forked_tasks_in_task2
fork
begin: gam
#5;
tfk2pos = 1;
end
begin: delt
@(fred);
disable gam;
tfk2nega = 0;
end
join
tfk2negb = 0;
end //forked_tasks_in_task
end
endtask // task_with_fork
task task_with_fork3; // disable *one* of the forked blocks
begin
#2;
begin: forked_tasks_in_task3
fork
begin: eps
#5;
tfk3nega = 0;
end
begin: zet
@(fred);
disable zet;
tfk3pos = 1;
end
join
tfk3negb = 0;
end //forked_tasks_in_task
end
endtask // task_with_fork
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<int> v; long long s[100100]; void init() { scanf( %d , &n); scanf( %d , &k); v.resize(1 + n); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); sort(v.begin() + 1, v.end()); v[0] = 0; s[0] = v[0]; for (int i = 1; i <= n; i++) s[i] = s[i - 1] + v[i]; int pos = 1, sol = 1, best = 1, val = v[1]; for (int i = 2; i <= n; i++) { while ((long long)(i - pos + 1) * v[i] - (s[i] - s[pos - 1]) > k) pos++; if (i - pos + 1 > best) { best = i - pos + 1; val = v[i]; } } cout << best << << val << endl; } int main() { init(); return 0; } |
#include <bits/stdc++.h> using namespace std; int Read() { char c; while (c = getchar(), (c != - ) && (c < 0 || c > 9 )) ; bool neg = (c == - ); int ret = neg ? 0 : c - 48; while (c = getchar(), c >= 0 && c <= 9 ) ret = ret * 10 + c - 48; return neg ? -ret : ret; } const int MAXN = 205, MOD = 7 + 1e9; int g1[13], g2[10], g3[7], g4[4], fac[MAXN]; int T, N, K, c[15][15], f1[MAXN][MAXN], f2[MAXN][MAXN], f3[MAXN][MAXN], f4[MAXN][MAXN]; int h2[MAXN][MAXN], h3[MAXN][MAXN], h4[MAXN][MAXN]; void init() { for (int i = 0; i <= 12; i++) c[i][0] = 1; for (int i = 1; i <= 12; i++) for (int j = 1; j <= i; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % MOD; g1[0] = g2[0] = g3[0] = g4[0] = 1; for (int i = 1; i <= 12; i++) { g1[i] = c[12][i] + 4 * c[10][i - 1]; if (i > 1) g1[i] += 6 * c[8][i - 2]; if (i > 2) g1[i] += 4 * c[6][i - 3]; if (i > 3) g1[i] += c[4][i - 4]; } for (int i = 1; i <= 9; i++) { g2[i] = c[9][i] + 2 * c[7][i - 1]; if (i > 1) g2[i] += c[5][i - 2]; } for (int i = 1; i <= 6; i++) g3[i] = c[6][i] + c[4][i - 1]; for (int i = 1; i <= 3; i++) g4[i] = c[3][i]; f1[0][0] = f2[0][0] = f3[0][0] = f4[0][0] = 1; f1[0][1] = 8, f1[0][2] = 16, f1[0][3] = 8, f1[0][4] = 1; f2[0][1] = 5, f2[0][2] = 5, f2[0][3] = 1; f3[0][1] = 3, f3[0][2] = 1; f4[0][1] = 1; for (int i = 1; i <= 200; i++) { for (int j = 0; j <= 200; j++) { for (int k = 0; k <= 3; k++) if (j >= k) (f4[i][j] += (long long)f4[i - 1][j - k] * g4[k] % MOD) %= MOD; h4[i][j] = f4[i][j]; } (f4[i][1] += 1) % MOD; for (int j = 0; j <= 200; j++) { for (int k = 0; k <= 6; k++) if (j >= k) (f3[i][j] += (long long)f3[i - 1][j - k] * g3[k] % MOD) %= MOD; h3[i][j] = f3[i][j]; if (j) (f3[i][j] += (long long)h4[i][j - 1] * 2LL % MOD) %= MOD; } (f3[i][2] += 1) %= MOD; (f3[i][1] += 1) %= MOD; for (int j = 0; j <= 200; j++) { for (int k = 0; k <= 9; k++) if (j >= k) (f2[i][j] += (long long)f2[i - 1][j - k] * g2[k] % MOD) %= MOD; h2[i][j] = f2[i][j]; if (j) { (f2[i][j] += (long long)h3[i][j - 1] * 2LL % MOD) %= MOD; for (int k = 0; k <= j - 1; k++) (f2[i][j] += (long long)h4[i][k] * (long long)h4[i][j - k - 1] % MOD) %= MOD; } if (j > 1) (f2[i][j] += (long long)h4[i][j - 2] * 3LL % MOD) %= MOD; if (j) (f2[i][j] += (long long)h4[i][j - 1] * 2LL % MOD) %= MOD; } (f2[i][3] += 1) %= MOD; (f2[i][2] += 2) %= MOD; for (int j = 0; j <= 200; j++) { for (int k = 0; k <= 12; k++) if (j >= k) (f1[i][j] += (long long)f1[i - 1][j - k] * g1[k] % MOD) %= MOD; if (j) (f1[i][j] += (long long)h2[i][j - 1] * 4LL % MOD) %= MOD; if (j > 1) { (f1[i][j] += (long long)h3[i][j - 2] * 4LL % MOD) %= MOD; for (int k = 0; k <= j - 2; k++) (f1[i][j] += (long long)h4[i][k] * (long long)h4[i][j - k - 2] % MOD * 2LL % MOD) %= MOD; } if (j > 2) (f1[i][j] += (long long)h4[i][j - 3] * 4LL % MOD) %= MOD; if (j) (f1[i][j] += (long long)h3[i][j - 1] * 4LL % MOD) %= MOD; if (j > 1) (f1[i][j] += (long long)h4[i][j - 2] * 8LL % MOD) %= MOD; } (f1[i][2] += 2) %= MOD; (f1[i][3] += 4) %= MOD; (f1[i][4] += 1) %= MOD; } fac[0] = 1; for (int i = 1; i <= 200; i++) fac[i] = (long long)fac[i - 1] * i % MOD; } void work() { scanf( %d%d , &N, &K); printf( %d n , (int)((long long)f1[N][K] * fac[K] % MOD)); } int main() { init(); work(); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long int m; cin >> m; unsigned long long int A[m], Ap[m]; unsigned long long int B[m]; map<unsigned long long int, vector<unsigned long long int> > mp; for (long long int i = 0; i < m; i++) { cin >> B[i]; } for (long long int i = 0; i < m; i++) { cin >> A[i]; Ap[i] = A[i]; } sort(Ap, Ap + m); sort(B, B + m); for (int i = 0; i < m; i++) { mp[Ap[i]].push_back(B[m - 1 - i]); } for (long long int i = 0; i < m; i++) { cout << mp[A[i]].back() << ; mp[A[i]].pop_back(); } } int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_TB_V
`define SKY130_FD_SC_HS__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_TB_V
|
#include <bits/stdc++.h> using namespace std; int comp(long long a, long long b) { return a > b; } long long arr[100000], cdf[100000]; int main() { int i, m; long long k, n; cin >> n; cin >> arr[0]; for (i = 1; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n, comp); cdf[0] = arr[0]; for (i = 1; i < n; i++) { cdf[i] = arr[i] + cdf[i - 1]; } cin >> m; long long rrr = 0; for (i = 1; i < n; i++) { rrr += arr[i] * i; } int ll; for (ll = 0; ll < m; ll++) { cin >> k; long long sum = 0LL; if (k == 1) cout << rrr << ; else { int mm; long long as, t = 1; for (as = 1, mm = 1; as < n; as = as + t, mm++) { t *= k; sum += (cdf[min(as + t - 1, n - 1)] - cdf[as - 1]) * mm; } cout << sum << ; } } cout << n ; return 0; } |
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- This is a simple synchronous FIFO. --
// -----------------------------------------------------------------------------
`default_nettype none
// FWFT means "First Word Fall Through".
module zap_sync_fifo #(
parameter WIDTH = 32,
parameter DEPTH = 32,
parameter FWFT = 1,
parameter PROVIDE_NXT_DATA = 0
)
(
// Clock and reset
input wire i_clk,
input wire i_reset,
// Flow control
input wire i_ack,
input wire i_wr_en,
// Data busses
input wire [WIDTH-1:0] i_data,
output reg [WIDTH-1:0] o_data,
output reg [WIDTH-1:0] o_data_nxt,
// Flags
output wire o_empty,
output wire o_full,
output wire o_empty_n,
output wire o_full_n,
output wire o_full_n_nxt
);
// Xilinx ISE does not allow $CLOG2 in localparams.
parameter PTR_WDT = $clog2(DEPTH) + 32'd1;
parameter [PTR_WDT-1:0] DEFAULT = {PTR_WDT{1'd0}};
// Variables
reg [PTR_WDT-1:0] rptr_ff;
reg [PTR_WDT-1:0] rptr_nxt;
reg [PTR_WDT-1:0] wptr_ff;
reg empty, nempty;
reg full, nfull;
reg [PTR_WDT-1:0] wptr_nxt;
reg [WIDTH-1:0] mem [DEPTH-1:0];
wire [WIDTH-1:0] dt;
reg [WIDTH-1:0] dt1;
reg sel_ff;
reg [WIDTH-1:0] bram_ff;
reg [WIDTH-1:0] dt_ff;
// Assigns
assign o_empty = empty;
assign o_full = full;
assign o_empty_n = nempty;
assign o_full_n = nfull;
assign o_full_n_nxt = i_reset ? 1 :
!( ( wptr_nxt[PTR_WDT-2:0] == rptr_nxt[PTR_WDT-2:0] ) &&
( wptr_nxt != rptr_nxt ) );
// FIFO write logic.
always @ (posedge i_clk)
if ( i_wr_en && !o_full )
mem[wptr_ff[PTR_WDT-2:0]] <= i_data;
// FIFO read logic
generate
begin:gb1
if ( FWFT == 1 )
begin:f1
// Retimed output data compared to normal FIFO.
always @ (posedge i_clk)
begin
dt_ff <= i_data;
sel_ff <= ( i_wr_en && (wptr_ff == rptr_nxt) );
bram_ff <= mem[rptr_nxt[PTR_WDT-2:0]];
end
// Output signal steering MUX.
always @*
begin
o_data = sel_ff ? dt_ff : bram_ff;
o_data_nxt = 0; // Tied off.
end
end
else
begin:f0
always @ (posedge i_clk)
begin
if ( i_ack && nempty ) // Read request and not empty.
begin
o_data <= mem [ rptr_ff[PTR_WDT-2:0] ];
end
end
if ( PROVIDE_NXT_DATA )
begin: f11
always @ (*)
begin
if ( i_ack && nempty )
o_data_nxt = mem [ rptr_ff[PTR_WDT-2:0] ];
else
o_data_nxt = o_data;
end
end
else
begin: f22
always @* o_data_nxt = 0;
end
end
end
endgenerate
// Flip-flop update.
always @ (posedge i_clk)
begin
dt1 <= i_reset ? 0 : i_data;
rptr_ff <= i_reset ? 0 : rptr_nxt;
wptr_ff <= i_reset ? 0 : wptr_nxt;
empty <= i_reset ? 1 : ( wptr_nxt == rptr_nxt );
nempty <= i_reset ? 0 : ( wptr_nxt != rptr_nxt );
nfull <= o_full_n_nxt;
full <= !o_full_n_nxt;
end
// Pointer updates.
always @*
begin
wptr_nxt = wptr_ff + (i_wr_en && !o_full);
rptr_nxt = rptr_ff + (i_ack && !o_empty);
end
endmodule // zap_sync_fifo
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 300 * 1000 + 5; int n, k, arr[Maxn]; int main() { scanf( %d%d , &n, &k); int Min = INT_MAX, Max = 0; for (int i = 0; i < n; i++) scanf( %d , &arr[i]), Min = min(Min, arr[i]), Max = max(Max, arr[i]); sort(arr, arr + n); for (int i = Min; i > 0; i--) { bool mark = false; if (Max % i <= k) { for (int j = 2; j * i <= Max; j++) { int ind = lower_bound(arr, arr + n, i * j) - arr; ind--; if (ind >= 0) { if (arr[ind] % i > k) mark = true; } } if (!mark) { printf( %d n , i); return 0; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long dp[1 << 13][13], g[1 << 13]; bool good[1 << 13]; int parent[1 << 13], root[1 << 13], n; long long solve(int mask, int root); long long f(int mask) { if (g[mask] == -1) { if (root[mask] == -1) { g[mask] = 0; for (int i = 0; i < n; i++) if (((mask >> i) & 1) == 1) g[mask] += solve(mask ^ (1 << i), i); } else g[mask] = solve(mask ^ (1 << root[mask]), root[mask]); } return g[mask]; } long long solve(int mask, int root) { if (mask == 0) return 1; if (dp[mask][root] == -1) { dp[mask][root] = 0; for (int i = mask; i > 0; i = (i - 1) & mask) { if ((i & mask & -mask) == 0 || !good[i] || (parent[i] != -1 && parent[i] != root)) continue; dp[mask][root] += solve(mask ^ i, root) * f(i); } } return dp[mask][root]; } int u[100], v[100], a[100], b[100], c[100]; int main() { int m, q; scanf( %d %d %d , &n, &m, &q); if (n == 1) { printf( 1 n ); return 0; } for (int i = 0; i < m; i++) { scanf( %d %d , u + i, v + i); u[i]--; v[i]--; } for (int i = 0; i < q; i++) { scanf( %d %d %d , a + i, b + i, c + i); a[i]--; b[i]--; c[i]--; } for (int i = 0; i < (1 << n); i++) { good[i] = true; parent[i] = root[i] = -1; g[i] = -1; for (int j = 0; j < n; j++) dp[i][j] = -1; for (int j = 0; j < m; j++) { int w = -1; if (((i >> u[j]) & 1) == 1 && ((i >> v[j]) & 1) == 0) w = v[j]; if (((i >> v[j]) & 1) == 1 && ((i >> u[j]) & 1) == 0) w = u[j]; if (w != -1) { if (parent[i] == -1) parent[i] = w, root[i] = u[j] + v[j] - w; else good[i] = false; } } for (int j = 0; j < q; j++) { int cnt = 0; if (((i >> a[j]) & 1) == 1) cnt++; if (((i >> b[j]) & 1) == 1) cnt++; if (((i >> c[j]) & 1) == 1) cnt++; if (cnt == 2 || (cnt == 1 && ((i >> c[j]) & 1) == 1)) good[i] = false; } } printf( %I64d n , solve((1 << n) - 2, 0)); return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Test non-constant bit selects - causes compile error right now
module test;
reg clk;
reg [1:0] in0;
reg [1:0] in1;
reg sel0,sel1;
wire [1:0] q;
dff2 u1 (q,clk,in0[sel0],in1[sel1]);
initial
begin
clk = 0;
in0 = 2'b0;
in1 = 2'b0;
sel0 = 1'b0;
sel1 = 1'b1;
#8;
$display("initial val =%x",q);
#8;
if(q == 2'b0)
$display("PASSED");
else
$display("FAILED");
$finish ;
end
always #5 clk = ~clk;
endmodule
// This is just a dual dff
module dff2 (q,clk,d0,d1);
input clk,d0,d1;
output [1:0] q;
reg [1:0] q;
always @(posedge clk)
q <= {d1,d0};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O221A_PP_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND4BB_PP_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; int a[200007]; void input() { scanf( %d , &n); int i; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } } void solve() { int i; for (i = 1; i <= n; i++) { if ((a[i] % 2) == 1) { if (i != n && (a[i + 1] != 0)) { a[i]--; a[i + 1]--; } } } for (i = 1; i <= n; i++) { if ((a[i] % 2) != 0) { printf( NO n ); return; } } printf( YES n ); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long bd(string n) { string num = n; long long dec_value = 0; long long base = 1; long long len = num.length(); for (long long i = len - 1; i >= 0; i--) { if (num[i] == 1 ) dec_value += base; base = base * 2; } return dec_value; } long long db(long long n) { for (long long i = 31; i >= 0; i--) { long long k = n >> i; if (k & 1) cout << 1 ; else cout << 0 ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long l, r; cin >> l >> r; if (l < r) { long long x = 64 - (__builtin_clzll(l ^ r)); long long y = 1; long long ans = y << x; ans--; cout << ans; } else cout << 0; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_2_V
`define SKY130_FD_SC_LP__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_2_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } const int N = 30; int dx[N], dy[N], b[N], v[N][N], a[N][N], B[N][N], n, T, tot, slack[N], f[N], g[N], ret, tot2, opt[N]; pair<int, int> perm[N]; int state[185000], val[185000]; bool hungary(int x) { if (x == -1) return 1; f[x] = 1; for (int i = 0; i < n; i++) { if (g[i]) continue; int t = dx[x] + dy[i] - v[x][i]; if (!t) { g[i] = 1; if (hungary(b[i])) { b[i] = x; return 1; } } else slack[i] = min(slack[i], t); } return 0; } void dfs(int d, int s1, int s2) { int s = 0, u = perm[d].second; for (int i = 0; i < n; i++) s += dx[i] + dy[i]; if (s + opt[d] <= ret) return; if (d == n) { int r = 0; for (int i = 0; i < n; i++) r += dx[i] + dy[i]; ret = max(ret, r); } int pdx[30], pdy[30], p[30]; for (int i = 0; i < n; i++) pdx[i] = dx[i], pdy[i] = dy[i], p[i] = b[i]; if (s1 != n / 2) { for (int j = 0; j < n; j++) v[u][j] = a[u][j]; for (int i = 0; i < n; i++) dx[u] = max(dx[u], v[u][i]); memset(slack, 0x20, sizeof(slack)); for (int i = 0; i < n; i++) f[i] = g[i] = 0; while (!hungary(u)) { int d = 0x20202020; for (int j = 0; j < n; j++) if (!g[j]) d = min(d, slack[j]); for (int j = 0; j < n; j++) { if (f[j]) dx[j] -= d; if (g[j]) dy[j] += d; } for (int j = 0; j < n; j++) f[j] = g[j] = 0; } dfs(d + 1, s1 + 1, s2); for (int i = 0; i < n; i++) dx[i] = pdx[i], dy[i] = pdy[i], b[i] = p[i]; } if (s2 != n / 2) { for (int j = 0; j < n; j++) v[u][j] = B[u][j]; for (int i = 0; i < n; i++) dx[u] = max(dx[u], v[u][i]); memset(slack, 0x20, sizeof(slack)); for (int i = 0; i < n; i++) f[i] = g[i] = 0; while (!hungary(u)) { int d = 0x20202020; for (int j = 0; j < n; j++) if (!g[j]) d = min(d, slack[j]); for (int j = 0; j < n; j++) { if (f[j]) dx[j] -= d; if (g[j]) dy[j] += d; } for (int j = 0; j < n; j++) f[j] = g[j] = 0; } dfs(d + 1, s1, s2 + 1); for (int i = 0; i < n; i++) dx[i] = pdx[i], dy[i] = pdy[i], b[i] = p[i]; } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) scanf( %d , &a[i][j]); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) scanf( %d , &B[i][j]); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) v[i][j] = max(a[i][j], B[i][j]); perm[i] = make_pair(*max_element(v[i], v[i] + n), i); } sort(perm, perm + n); reverse(perm, perm + n); for (int i = 0; i < n; i++) b[i] = -1; for (int d = n - 1; d >= 0; d--) { int u = perm[d].second; for (int i = 0; i < n; i++) dx[u] = max(dx[u], v[u][i]); memset(slack, 0x20, sizeof(slack)); for (int i = 0; i < n; i++) f[i] = g[i] = 0; while (!hungary(u)) { int d = 0x20202020; for (int j = 0; j < n; j++) if (!g[j]) d = min(d, slack[j]); for (int j = 0; j < n; j++) { if (f[j]) dx[j] -= d; if (g[j]) dy[j] += d; } for (int j = 0; j < n; j++) f[j] = g[j] = 0; } opt[d] = 0; for (int i = 0; i < n; i++) opt[d] += dx[i] + dy[i]; } for (int i = 0; i < n; i++) b[i] = -1, dx[i] = dy[i] = 0; dfs(0, 0, 0); printf( %d n , ret); } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e4 + 3; const long long MOD = 998244353; int a[MAX]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; int s = 2 * n, mid = n, one = 0, left = 0; for (int i = 1; i <= k; i++) { cin >> a[i]; if (a[i] % 2) { a[i]--; left++; } } for (int i = 1; i <= k; i++) { if (a[i] >= 4) { int need = a[i] / 4; if (mid <= need) { a[i] -= mid * 4; mid = 0; } else { a[i] %= 4; mid -= need; } } } if (mid == 0) { for (int i = 1; i <= k; i++) s -= a[i] / 2; s -= left; if (s >= 0) cout << YES ; else cout << NO ; return 0; } for (int i = 1; i <= k; i++) { if (a[i] == 2) { if (s) { s--; continue; } if (mid) { mid--; left--; continue; } left += 2; } } if (s + mid * 2 >= left) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using namespace std; int main() { long long count, x, f, total = 0; std::cin >> count; long long a[count]; for (long long i = 0; i < count; i++) { std::cin >> a[i]; } std::cin >> x >> f; for (long long i = 0; i < count; i++) { total += a[i] / (f + x); if (a[i] % (x + f) > x) total++; } std::cout << total * f << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int sf[26][200005], tf[26][200005]; int main() { long long int n, i, j; cin >> n; double ans = 0.0; string s, t; cin >> s >> t; for (i = 0; i < n; ++i) { sf[s[i] - A ][i] += (i + 1); tf[t[i] - A ][i] += (i + 1); if (i) for (j = 0; j < 26; ++j) { sf[j][i] += sf[j][i - 1]; tf[j][i] += tf[j][i - 1]; } ans = ans + (n - i) * ((i ? sf[t[i] - A ][i - 1] : 0) + tf[s[i] - A ][i]); } ans = (6 * ans) / (n * (n + 1) * (2 * n + 1)); cout << fixed << setprecision(8) << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10, oo = 1e9 + 10, MOD = 1e9 + 7; void solve() { long long a, b; cin >> a >> b; if (a > b) { long long ans = 0; while (b != a) { b *= 2; ans++; if (b > a) { cout << -1 n ; return; } } int q = 0, q1 = 0; if (ans >= 3) { long long k = ans / 3; k += ans % 3; q = ans % 3; ans = k; q1 = 1; } if (q >= 2 && q1) { ans -= q / 2; } if (!q1) { ans = (ans + 1) / 2; } cout << ans << n ; } else { if (a == b) { cout << 0 n ; return; } long long ans = 0; while (a != b) { a *= 2; ans++; if (a > b) { cout << -1 n ; return; } } int q = 0, q1 = 0; if (ans >= 3) { long long k = ans / 3; k += ans % 3; q = ans % 3; ans = k; q1 = 1; } if (q >= 2 && q1) { ans -= q / 2; } if (!q1) { ans = (ans + 1) / 2; } cout << ans << n ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int N = 5010, mod = 1LL * 1000 * 1000 * 1000 + 7; long long dp[N][N], inv_fact[N], fact[N], n, k; long long Pow(long long a, long long b) { return b ? (b & 1 ? a : 1) % mod * Pow(a * a % mod, b >> 1) % mod : 1; } int C(int r, int n) { if (r > n) return 0; int num = 1; for (int i = n; i >= n - r + 1; i--) num = 1LL * num * i % mod; num = 1LL * num * inv_fact[r] % mod; return num; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); fact[0] = 1; for (int i = 1; i < N; i++) fact[i] = 1LL * fact[i - 1] * i % mod; inv_fact[N - 1] = Pow(fact[N - 1], mod - 2); for (int i = N - 2; i >= 0; i--) inv_fact[i] = 1LL * inv_fact[i + 1] * (i + 1) % mod; for (int i = 1; i < N; i++) dp[1][i] = 1; for (int i = 2; i < N; i++) for (int j = i; j < N; j++) dp[i][j] = 1LL * (dp[i - 1][j - 1] + dp[i][j - 1]) % mod * i % mod; cin >> n >> k; long long ans = 0; for (int r = 1; r <= min(k, n); r++) { long long t = Pow(2, n - r); t = 1LL * t * dp[r][k] % mod; t = 1LL * t * C(r, n) % mod; ans = (1LL * ans + t) % mod; } cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_1_V
`define SKY130_FD_SC_LP__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_BEHAVIORAL_V |
// mmio_if_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2017.05.28.12:10:00
`timescale 1 ps / 1 ps
module mmio_if_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
mmio_if_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
`timescale 1ns/1ps
module i2c_simple(reset_n,
clock,
sda_in,
scl);
input clock;
input reset_n;
input sda_in;
input scl;
reg start_bus_reg;
reg stop_bus_reg;
wire sda_risingedge;
wire scl_risingedge;
wire sda_failingedge;
wire scl_fallingedge;
reg curr, last;
always@(posedge clock)
begin
if(!reset_n) begin
curr <= 1'b0;
last <= 1'b0;
end
else begin
curr <= scl;
last <= curr;
end
end
//Raising edge
assign scl_risingedge = curr & (~last);
//failing edge
assign scl_fallingedge = ~curr & (last);
reg sda_curr, sda_last;
always@(posedge clock)
begin
if(!reset_n) begin
sda_curr <= 1'b0;
sda_last <= 1'b0;
end
else begin
sda_curr <= sda_in;
sda_last <= sda_curr;
end
end
//Raising edge
assign sda_risingedge = sda_curr & (~sda_last);
//failing edge
assign sda_fallingedge = ~sda_curr & (sda_last);
// ----------------------------------------------------------------
// to test start condition: scl=1, sda_in failing
always@(posedge clock)
begin
start_bus_reg <= sda_fallingedge & scl;
stop_bus_reg <= sda_risingedge & scl;
end
endmodule
/*
* Do not change Module name
*/
module test_i2c;
reg reset_n;
reg clock;
reg sda_in;
wire sda_out;
wire sda_en;
reg scl;
wire debug;
integer i;
/*
i2c_simple i2c_simple(.reset_n(reset_n),
.clock(clock),
.sda_in(sda),
.scl(scl));
*/
i2c_slave_op_reduced i2c_slave_op_reduced_inst(
.reset_n(reset_n),
.clock(clock),
.sda_out(sda_out),
.sda_in(sda_in),
.sda_en(sda_en),
.scl(scl),
.led(debug)
);
initial
begin
clock = 0;
scl = 0;
sda_in = 0;
//reset
#50 reset_n = 1;
#50 reset_n = 0;
#50 reset_n = 1;
//idle
#50 scl = 1;
#50 sda_in = 1;
//start
#20 sda_in = 0;
#10 scl = 0;
//abnormal testing
#50 scl = 1;
#50 sda_in = 1;
//start
#200 sda_in = 0;
#100 scl = 0;
//100K HZ means 10000ns one cuycle
//send address
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 2
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 3
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 4
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 5
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 6
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 7
#500 sda_in = 0;
#500 scl = 1;
#500 scl = 0;
//bit r/w
#500 sda_in = 0;
#500 scl = 1;
#500 scl = 0;
//bit ack
#500 sda_in = 0;
#500 scl = 1;
#500 scl = 0;
for (i=0; i< 32; i=i+1) begin
//bit 1
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 2
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 3
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 4
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 5
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 6
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 7
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 8
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit ack
//#10 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
end
//repeat start
#50 scl = 1;
#50 sda_in = 1;
//start
#100 sda_in = 0;
#100 scl = 0;
//send address
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 2
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 3
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 4
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 5
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 6
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 7
#500 sda_in = 0;
#500 scl = 1;
#500 scl = 0;
//bit r
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit ack
#500 sda_in = 0;
#500 scl = 1;
#500 scl = 0;
for (i=0; i< 32; i=i+1) begin
//bit 1
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 2
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 3
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 4
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 5
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 6
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 7
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit 8
#500 sda_in = 1;
#500 scl = 1;
#500 scl = 0;
//bit ack
#500 sda_in = 0;
#500 scl = 1;
#500 scl = 0;
end
//stop condition
#100 sda_in = 0;
#100 scl = 1;
#100 sda_in = 1;
end
always begin
//50M HZ about 20ns one cycle
#10 clock = ! clock;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int d[1503][1503][26], e[1503][26], z[1503][26]; int main() { ios::sync_with_stdio(false); int n, q, m; char c; string s; cin >> n >> s >> q; for (int i = 0; i < 26; i++) for (int j = 1; j <= n; j++) e[j][i] = e[j - 1][i] + (s[j - 1] == a + i); for (int i = 1; i <= n; i++) for (int j = i; j <= n; j++) for (int k = 0; k < 26; k++) d[i][j][k] = e[j][k] - e[i - 1][k]; for (int i = 1; i <= n; i++) for (int j = 0; j < 26; j++) { int l = 1; for (int k = 1; k <= n; k++) { while (d[l][k][j] + i < k - l + 1) l++; z[i][j] = max(z[i][j], k - l + 1); } } while (q--) cin >> m >> c, cout << z[m][c - a ] << n ; } |
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module branch_jump (
output branch_taken,
output [31:0] branch_target,
output jump,
output [31:0] jump_target,
input [31:0] inst,
input [31:0] pc,
input [31:0] rd1,
input [31:0] alu_out
);
wire [6:0] opcode = inst[6:0];
wire [2:0] funct3 = inst[9:7];
wire [11:0] split_imm = {inst[31:27], inst[16:10]};
wire [31:0] sext_split_imm = split_imm[11] ? {20'hFFFFF, split_imm} : {20'h0, split_imm};
assign jump = (opcode == `OPCODE_J ||
opcode == `OPCODE_JAL ||
opcode == `OPCODE_JALR);
wire [31:0] j_offset = inst[31] ? {6'h3F, inst[31:7], 1'b0} : {6'h0, inst[31:7], 1'b0};
assign jump_target = (opcode == `OPCODE_J || opcode == `OPCODE_JAL) ? j_offset + pc : rd1;
/* branch */
assign branch_target = pc + ($signed(sext_split_imm) << 1);
reg branch_sat;
always @ (*) begin
case (funct3)
`F3_BEQ: branch_sat = (alu_out == 0);
`F3_BNE: branch_sat = (alu_out != 0);
`F3_BLT: branch_sat = (alu_out == 1);
`F3_BGE: branch_sat = (alu_out != 1);
`F3_BLTU: branch_sat = (alu_out == 1);
`F3_BGEU: branch_sat = (alu_out != 1);
default: branch_sat = 0;
endcase
end
assign branch_taken = branch_sat && (opcode == `OPCODE_BRANCH);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_TB_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_TB_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvpwrvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 111; const double INF = 1e200; double dp[N][10 * N]; struct problem { int a, p; bool operator<(const problem &o) const { return a > o.a; } } p[N]; int n; double C, T; double solve(double x) { x /= 0.9; auto t = (sqrt(C * x) - 1) / C; t = max(t, 0.0); return x / (1 + C * t) + t; } int main() { int tc; cin >> tc; while (tc--) { cin >> n >> C >> T; for (int i = 0; i < n; i++) cin >> p[i].a >> p[i].p; sort(p, p + n); fill(dp[0], dp[N], INF); dp[0][0] = 0; int sum = 0; for (int i = n - 1; i >= 0; i--) { for (int k = n - 1 - i; k >= 0; k--) { for (int s = sum; s >= 0; s--) if (dp[k][s] < INF) { dp[k + 1][s + p[i].p] = min(dp[k + 1][s + p[i].p], dp[k][s] / 0.9 + p[i].a); } } sum += p[i].p; } int ans = 0; for (int s = sum; s > 0; s--) { for (int k = 0; k <= n; k++) { if (dp[k][s] < INF) { auto cost = k * 10 + solve(dp[k][s]); if (cost <= T) { ans = max(ans, s); } } } } cout << ans << endl; } return 0; } |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/PULLDOWN.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Resistor to GND
// /___/ /\ Filename : PULLDOWN.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module PULLDOWN (O);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
wire A;
pulldown (A);
buf (weak0,weak1) #(100,100) (O,A);
endmodule
`endcelldefine
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-11-20 19:46:17
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Simple_KOA_STAGE_1_approx
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
wire [SW/2:0] result_A_adder;
wire [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
cmult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
cmult #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
cmult #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
Approx_adder #(.W(SW/2))
A_op (
.add_sub (1'b0),
.in1 (Data_A_i[((SW/2)-1):0] ),
.in2 (Data_A_i[(SW-1) -: SW/2]),
.res (result_A_adder));
Approx_adder #(.W(SW/2))
B_op(
.add_sub (1'b0),
.in1 (Data_B_i[((SW/2)-1):0]),
.in2 (Data_B_i[(SW-1) -: SW/2]),
.res (result_B_adder));
always @* begin : EVEN
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
cmult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
cmult #(.SW(SW/2+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
cmult #(.SW(SW/2+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
Approx_adder #(.W(SW/2+1))
A_op(
.add_sub (1'b0),
.in1 (Data_A_i[((SW/2)-1):0] ),
.in2 (Data_A_i[(SW-1) -: SW/2]),
.res (result_A_adder));
Approx_adder #(.W(SW/2+1))
B_op(
.add_sub (1'b0),
.in1 (Data_B_i[((SW/2)-1):0]),
.in2 (Data_B_i[(SW-1) -: SW/2]),
.res (result_B_adder));
always @* begin : ODD
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int mat[1000010]; int row(int r) { int s = r * m, e = s + m; bool eq = false, dif = false; for (int i = s, idx = 0; i < e; i++, idx++) { if (mat[i] == -1) continue; int a = mat[i] / 2; int b = idx & 1; if (a == b) eq = true; if (a != b) dif = true; } if (eq && dif) return 0; if (eq || dif) return 1; return 2; } int col(int c) { int s = c, e = n * m + c; bool eq = false, dif = false; for (int i = s, idx = 0; i < e; i += m, idx++) { if (mat[i] == -1) continue; int a = min(mat[i], 3 - mat[i]); int b = idx & 1; if (a == b) eq = true; if (a != b) dif = true; } if (eq && dif) return 0; if (eq || dif) return 1; return 2; } int main() { while (cin >> n >> m) { char ch; for (int i = 0; i < n * m; i++) { cin >> ch; if (ch == . ) mat[i] = -1; else mat[i] = (int)(ch - 1 ); } int res = 1; for (int i = 0; i < n; i++) { res *= row(i); if (res >= 1000003) res -= 1000003; } for (int i = 0; i < m; i++) { res *= col(i); if (res >= 1000003) res -= 1000003; } cout << res % 1000003 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 300000000 + 10; bitset<MAXN> check; void Get_prime(int n) { check.set(); check[0] = check[1] = 0; for (int i = 2; i <= sqrt(n + 0.5); ++i) { if (check[i]) for (int j = 2; i * j <= n; ++j) check[i * j] = 0; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int l, r; cin >> l >> r; Get_prime(r); int cnt = 0, i; if (l <= 2 && 2 <= r) ++cnt; if (l % 4 <= 1) i = l / 4 * 4 + 1; else i = (l / 4 + 1) * 4 + 1; for (i; i <= r; i += 4) if (check[i]) ++cnt; cout << cnt; } |
#include <bits/stdc++.h> const int inf = 0x7FFFFFFF; using namespace std; int dep[2014], shortcut[20][2014]; struct Edge { int u, v, w; bool operator<(const Edge &A) const { return w < A.w; } } E[4000005]; int mp[2014][2014]; int fa[2014], d[2014]; int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } vector<int> G[2014], Q; int get_lca(int a, int b) { if (dep[a] < dep[b]) swap(a, b); for (int i = 20 - 1; i >= 0; i--) { if (dep[a] - dep[b] >> i & 1) { a = shortcut[i][a]; } } if (a == b) return a; for (int i = 20 - 1; i >= 0; i--) { if (shortcut[i][a] != shortcut[i][b]) { a = shortcut[i][a]; b = shortcut[i][b]; } } return shortcut[0][a]; } int main() { int N; scanf( %d , &N); for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) scanf( %d , &mp[i][j]); int tot = 0; for (int i = 1; i <= N; i++) for (int j = i + 1; j <= N; j++) { E[tot].u = i; E[tot].v = j; E[tot].w = mp[i][j]; tot++; } sort(E, E + tot); for (int i = 1; i <= N; i++) fa[i] = i; for (int i = 0; i < tot; i++) { int u = E[i].u; int v = E[i].v; if (find(u) != find(v)) { fa[find(u)] = find(v); G[u].push_back(v); G[u].push_back(E[i].w); G[v].push_back(u); G[v].push_back(E[i].w); } } int *parent = shortcut[0]; d[1] = 0; parent[1] = -1; dep[1] = 0; Q.push_back(1); for (int head = 0; head < int(Q.size()); head++) { int u = Q[head]; for (int i = 0; i < int(G[u].size()); i += 2) { int v = G[u][i]; int w = G[u][i + 1]; if (v != parent[u]) { parent[v] = u; dep[v] = dep[u] + 1; d[v] = d[u] + w; Q.push_back(v); } } } for (int i = 1; i < 20; i++) { for (int j = 1; j <= N; j++) { int &res = shortcut[i][j]; res = shortcut[i - 1][j]; if (~res) { res = shortcut[i - 1][res]; } } } bool ok = true; int num = 0; for (int i = 1; i <= N; i++) if (fa[i] == i) num++; if (num > 1) ok = false; for (int u = 1; ok && u <= N; u++) { if (mp[u][u] != 0) ok = false; for (int v = u + 1; ok && v <= N; v++) { if (mp[u][v] != mp[v][u]) ok = false; if (mp[u][v] == 0) ok = false; int mid = get_lca(u, v); if (d[u] + d[v] - d[mid] * 2 != mp[u][v]) ok = false; } } puts(ok ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 1000 + 10; int n, maxLevel; vector<int> edge[maxn]; vector<int> gu; int dis[maxn]; vector<int> level[maxn]; int fa[maxn]; bool used[maxn]; void print(int a[], int n, int st = 0) { for (int i = 0; i < n; i++) { if (i != 0) printf( ); printf( %d , a[i + st]); } printf( n ); } void init() { scanf( %d , &n); for (int i = 1; i <= n; i++) edge[i].clear(); for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d%d , &x, &y); edge[x].push_back(y); edge[y].push_back(x); } } void guess(vector<int> a, int &u, int &value) { printf( ? %d , int(a.size())); for (int i = 0; i < a.size(); i++) printf( %d , a[i]); printf( n ); fflush(stdout); scanf( %d%d , &u, &value); } void answer(int u1, int u2) { char s[20]; printf( ! %d %d n , u1, u2); fflush(stdout); scanf( %s , s); } void dfs(int u) { for (int i = 0; i < edge[u].size(); i++) { int v = edge[u][i]; if (dis[v] == -1) { dis[v] = dis[u] + 1; fa[v] = u; maxLevel = max(maxLevel, dis[v]); level[dis[v]].push_back(v); dfs(v); } } } void doit() { int r, len, k1, k2; gu.clear(); for (int i = 1; i <= n; i++) gu.push_back(i); guess(gu, r, len); for (int i = 0; i <= n; i++) level[i].clear(); for (int i = 0; i <= n; i++) dis[i] = -1; dis[r] = 0; level[0].push_back(r); maxLevel = 0; dfs(r); int left = (len + 1) / 2, right = min(len, maxLevel), mid, ans, u, d; while (left <= right) { mid = (left + right) >> 1; guess(level[mid], u, d); if (d <= len) { ans = mid; k1 = u; left = mid + 1; } else { right = mid - 1; } } if (ans == len) { answer(r, k1); return; } u = k1; for (int i = 1; i <= n; i++) used[i] = false; while (u != r) { used[u] = true; u = fa[u]; } gu.clear(); for (int i = 0; i < level[len - ans].size(); i++) { if (!used[level[len - ans][i]]) { gu.push_back(level[len - ans][i]); } } guess(gu, k2, d); answer(k1, k2); } int main() { int t; scanf( %d , &t); while (t--) { init(); doit(); } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module prot_eng_tx
#(parameter BASE=0)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [35:0] datain, input src_rdy_i, output dst_rdy_o,
output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
wire src_rdy_int1, dst_rdy_int1;
wire src_rdy_int2, dst_rdy_int2;
wire [35:0] data_int1, data_int2;
// Shortfifo on input to guarantee no deadlock
fifo_short #(.WIDTH(36)) head_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
.dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
.space(),.occupied() );
// Store header values in a small dual-port (distributed) ram
reg [31:0] header_ram[0:63];
reg [3:0] state;
reg [1:0] port_sel;
always @(posedge clk)
if(set_stb & ((set_addr & 8'hC0) == BASE))
header_ram[set_addr[5:0]] <= set_data;
wire [31:0] header_word = header_ram[{port_sel[1:0],state[3:0]}];
reg [15:0] pre_checksums [0:3];
always @(posedge clk)
if(set_stb & ((set_addr & 8'hCF)== (BASE+7)))
pre_checksums[set_addr[5:4]] <= set_data[15:0];
wire [15:0] pre_checksum = pre_checksums[port_sel[1:0]];
// Protocol State Machine
reg [15:0] length;
wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR
wire [15:0] udp_length = length + 8; // UDP HDR
reg sof_o;
reg [31:0] prot_data;
always @(posedge clk)
if(reset)
begin
state <= 0;
sof_o <= 0;
end
else
if(src_rdy_int1 & dst_rdy_int2)
case(state)
0 :
begin
port_sel <= data_int1[18:17];
length <= data_int1[15:0];
sof_o <= 1;
if(data_int1[16])
state <= 1;
else
state <= 12;
end
12 :
begin
sof_o <= 0;
if(data_int1[33]) // eof
state <= 0;
end
default :
begin
sof_o <= 0;
state <= state + 1;
end
endcase // case (state)
wire [15:0] ip_checksum;
add_onescomp #(.WIDTH(16)) add_onescomp
(.A(pre_checksum),.B(ip_length),.SUM(ip_checksum));
reg [15:0] ip_checksum_reg;
always @(posedge clk) ip_checksum_reg <= ip_checksum;
always @*
case(state)
1 : prot_data <= header_word; // ETH, top half ignored
2 : prot_data <= header_word; // ETH
3 : prot_data <= header_word; // ETH
4 : prot_data <= header_word; // ETH
5 : prot_data <= { header_word[31:16], ip_length }; // IP
6 : prot_data <= header_word; // IP
7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) }; // IP
8 : prot_data <= header_word; // IP
9 : prot_data <= header_word; // IP
10: prot_data <= header_word; // UDP
11: prot_data <= { udp_length, header_word[15:0]}; // UDP
default : prot_data <= data_int1[31:0];
endcase // case (state)
assign data_int2 = { data_int1[35:33] & {3{state[3]}}, sof_o, prot_data };
assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12));
assign src_rdy_int2 = src_rdy_int1 & (state != 0);
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(36)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
.dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
.space(),.occupied() );
endmodule // prot_eng_tx
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 500 + 10; const int pN = 1e6; const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; void add(long long &x, long long y) { x += y; x %= MOD; } int u, v, n, m; void Solve(int x, int y, int z) { int row = n, cul = m; int nx, ny; for (int i = 1; i <= x; i++) { nx = v; ny = row - u + 1; u = nx; v = ny; swap(row, cul); } for (int i = 1; i <= y; i++) { nx = u; ny = cul - v + 1; u = nx; v = ny; } for (int i = 1; i <= z; i++) { nx = cul - v + 1; ny = u; u = nx; v = ny; swap(row, cul); } cout << u << << v << endl; } int main() { int x, y, z, p; cin >> n >> m >> x >> y >> z >> p; x %= 4; y %= 2; z %= 4; for (int i = 0; i < p; i++) { cin >> u >> v; Solve(x, y, z); } return 0; } |
module ScanCodeControl(NewDataKB,Load, New , Borrar, EndTras, ParityCoherente, Clk , Reset);
input NewDataKB, EndTras, ParityCoherente, Clk, Reset;
output reg Load, New , Borrar;
reg [1:0]state;
parameter Sleep = 3'h0;
parameter Trasmitir = 3'h1;
parameter Wait = 3'h3;
parameter NewS = 3'h2;
always @(negedge Clk) begin
if (Reset)
state = Sleep;
else begin
case(state)
Sleep:begin
if(NewDataKB) state=Trasmitir;
else state=Sleep;
end
Trasmitir:begin
if(EndTras) begin
if(ParityCoherente)state=NewS;
else state=Sleep;
end
else state=Wait ;
end
Wait:begin
if(NewDataKB) state=Trasmitir;
else state=Wait;
end
NewS: state=Sleep;
default: state = Sleep ;
endcase
end
end
always @(state) begin
case(state)
Sleep :begin
Load=0;
Borrar=1;
New=0;
end
Wait :begin
Load=0;
Borrar=0;
New=0;
end
Trasmitir:begin
Load=1;
Borrar=0;
New=0;
end
NewS:begin
Load=0;
Borrar=0;
New=1;
end
default:
begin
Load=0;
Borrar=1;
New=0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { char x = 0 ; int fh = 1, sum = 0; for (x = getchar(); x < 0 || x > 9 ; x = getchar()) if (x == - ) fh = -1; for (; x >= 0 && x <= 9 ; x = getchar()) sum = sum * 10 + x - 0 ; return fh * sum; } const int N = 1e5 + 9; int fa[N], ch[N][2], sz[N]; long long A[N], B[N], val[N]; int n, a, rt, cnt; inline long long pd(int x) { return ch[fa[x]][1] == x; } inline void pushup(int x) { int ls = ch[x][0], rs = ch[x][1]; sz[x] = sz[ls] + sz[rs] + 1; } inline void modify(int x, long long a, long long b) { val[x] += a * (sz[ch[x][0]] + 1) + b; A[x] += a, B[x] += b; } inline void pushdown(int x) { if (A[x] || B[x]) { if (ch[x][0]) modify(ch[x][0], A[x], B[x]); if (ch[x][1]) modify(ch[x][1], A[x], B[x] + A[x] * (sz[ch[x][0]] + 1)); A[x] = B[x] = 0; } } inline void rotate(int x) { int y = fa[x], z = fa[y], kx = pd(x), ky = pd(y); if (z) ch[z][ky] = x; fa[x] = z, fa[y] = x, fa[ch[x][kx ^ 1]] = y; ch[y][kx] = ch[x][kx ^ 1]; ch[x][kx ^ 1] = y; pushup(y), pushup(x); if (z) pushup(z); } inline void splay(int x) { static int sta[N], tp; sta[tp = 1] = x; for (int y = x; fa[y]; y = fa[y]) sta[++tp] = fa[y]; while (tp) pushdown(sta[tp--]); for (; fa[x]; rotate(x)) if (fa[fa[x]]) rotate((pd(x) ^ pd(fa[x])) ? x : fa[x]); pushup(rt = x); } inline long long getv(int k) { int x = rt; while (1) { if (sz[ch[x][0]] + 1 == k) { splay(x); return val[x]; } if (sz[ch[x][0]] >= k) x = ch[x][0]; else k -= sz[ch[x][0]] + 1, x = ch[x][1]; } } inline long long getmx(int x) { if (!x) return -1e18; pushdown(x); return std::max(val[x], std::max(getmx(ch[x][0]), getmx(ch[x][1]))); } int main() { n = read(); sz[1] = rt = cnt = 1; for (register int i = 1, endi = n; i <= endi; ++i) { int a = read(); int lp = 0, rp = i - 2, ans = i - 1; while (lp <= rp) { int mid = (lp + rp) >> 1; if (getv(mid + 1) + (mid + 1LL) * a > getv(mid + 2)) rp = (ans = mid) - 1; else lp = mid + 1; } getv(ans + 1); fa[++cnt] = rt, val[cnt] = val[rt], ch[cnt][1] = ch[rt][1]; fa[ch[rt][1]] = cnt; ch[rt][1] = cnt; modify(cnt, a, 1LL * a * ans); } printf( %lld n , getmx(rt)); return 0; } |
#include <bits/stdc++.h> using namespace std; bool iss(int d) { for (int i = 2; i * i <= d; ++i) if (d % i == 0) return false; return true; } int main() { int a, b, c; scanf( %d%d%d , &a, &b, &c); vector<int> simple; for (int i = 2; i < 100; ++i) if (iss(i)) simple.push_back(i); vector<vector<int> > d(101); for (int i = 1; i <= 100; ++i) { d[i].resize(simple.size()); for (int j = 0, tmp = i; j < simple.size(); ++j) while (tmp % simple[j] == 0) { tmp /= simple[j]; d[i][j]++; } } int ans = 0; int mod = 1 << 30; for (int i = 1; i <= a; ++i) for (int j = 1; j <= b; ++j) for (int k = 1; k <= c; ++k) { int prod = 1; for (int l = 0; l < simple.size(); ++l) prod *= d[i][l] + d[j][l] + d[k][l] + 1; ans = (ans + prod) % mod; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 15; int k, n, m, x, y, ans; int dz[6] = {0, 0, 0, 0, 1, -1}; int dx[6] = {0, 0, 1, -1, 0, 0}; int dy[6] = {1, -1, 0, 0, 0, 0}; char plt[N][N][N]; bool mark[N][N][N]; bool isval(int a, int b, int c) { if (a < k && a >= 0 && b < n && b >= 0 && c < m && c >= 0 && plt[a][b][c] == . ) { return true; } return false; } void dfs(int a, int b, int c) { mark[a][b][c] = true; ans++; for (int i = 0; i < 6; i++) { if (isval(a + dz[i], b + dx[i], c + dy[i]) && !mark[a + dz[i]][b + dx[i]][c + dy[i]]) { dfs(a + dz[i], b + dx[i], c + dy[i]); } } return; } int main() { cin >> k >> n >> m; for (int i = 0; i < k; i++) { for (int j = 0; j < n; j++) { for (int l = 0; l < m; l++) { cin >> plt[i][j][l]; } } } cin >> x >> y; x--; y--; dfs(0, x, y); cout << ans << endl; return 0; } |
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Basic test for the unbounded arrays in VHDL.
module vhdl_unbounded_array_test;
vhdl_unbounded_array dut();
initial begin
#1; // wait for signal assignment
if(dut.sig_logic != 'b01010101) begin
$display("FAILED 1");
$finish;
end
if(dut.sig_integer[2] != 1) begin
$display("FAILED 2");
$finish;
end
if(dut.sig_real[1] != 2.5) begin
$display("FAILED 3");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fre() { freopen( c://test//input.in , r , stdin); freopen( c://test//output.out , w , stdout); } template <class T1, class T2> inline void gmax(T1 &a, T2 b) { if (b > a) a = b; } template <class T1, class T2> inline void gmin(T1 &a, T2 b) { if (b < a) a = b; } const int N = 0, M = 0, Z = 1e9 + 7, ms63 = 0x3f3f3f3f; int casenum, casei; long long n; void solve1e6(long long n) { int step = 0; while (n) { int x = n; int mx = 0; while (x) gmax(mx, x % 10), x /= 10; n -= mx; ++step; } printf( %d n , step); } struct A { long long x; int y; void add(const A &b) { x += b.x; y = b.y; } }; int a[20]; A f[20][10][10]; A dp(int p, int mx, int tim, int tp) { if (p == -1) { if (mx == 0) return {0, 0}; if (tim) return {0, tim - 1}; return {1, mx - 1}; } if (!tp && ~f[p][mx][tim].x) return f[p][mx][tim]; A ret = {0, tim}; int top = tp ? a[p] : 9; for (int i = top; i >= 0; --i) { ret.add(dp(p - 1, max(mx, i), ret.y, tp && i == top)); } if (!tp) f[p][mx][tim] = ret; return ret; } void solve1e18(long long n) { int p = -1; while (n) a[++p] = n % 10, n /= 10; if (p == -1) a[++p] = 0; for (int i = 0; i <= p; ++i) { for (int j = 0; j < 10; ++j) { for (int k = 0; k < 10; ++k) f[i][j][k].x = -1; } } printf( %lld n , dp(p, 0, 0, 1).x); } int main() { while (~scanf( %lld , &n)) { solve1e18(n); } return 0; } |
#include <bits/stdc++.h> int main() { long long int n; scanf( %lld , &n); printf( %lld , 6 * n * (n + 1) / 2 + 1); } |
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Dec 16 2016
//Description: MBus Member Controller
//Update History: May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Combined the following three modules into one:
// lname_mbus_member_sleep_ctrl
// lname_mbus_member_wire_ctrl
// lname_mbus_member_addr_rf
// lname_mbus_int_ctrl
// Fixed potential hold-time violation in ext_int_dout & EXTERNAL_INT
// OLD: int_busy = WAKEUP_REQ & mbus_busy_b
// ext_int_dout and EXTERNAL_INT set to mbus_busy_b @ (posedge int_busy)
// NEW: int_busy = WAKEUP_REQ & mbus_busy_b & LRC_SLEEP
// ext_int_dout and EXTERNAL_INT set to 1 @ (posedge int_busy)
// Dec 16 2016 - Updated for MBus r04
// Fixed CIN glitch issue
// Now MBUS_BUSY_B is generated in mbus_node
// Apr 28 2017 - Updated for MBus r04p1
// More explicit isolation for SLEEP_REQ
// SLEEP_REQ* and MBUS_BUSY are isolated here, rather than in mbus_isolation.
//*******************************************************************************************
`include "include/lname_mbus_def.v"
module lname_mbus_member_ctrl (
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output reg COUT,
output reg DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ,
input WAKEUP_REQ,
// Power-Gating Signals
output reg MBC_ISOLATE,
output MBC_ISOLATE_B,
output reg MBC_RESET,
output MBC_RESET_B,
output reg MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output reg EXTERNAL_INT,
// Short-Prefix
input ADDR_WR_EN,
input ADDR_CLR_B,
input [`MBUS_DYNA_WIDTH-1:0] ADDR_IN,
output reg [`MBUS_DYNA_WIDTH-1:0] ADDR_OUT,
output reg ADDR_VALID,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
wire next_mbc_isolate;
wire sleep_req_isol;
reg goingsleep;
assign MBC_SLEEP_B = ~MBC_SLEEP;
assign MBC_ISOLATE_B = ~MBC_ISOLATE;
assign MBC_RESET_B = ~MBC_RESET;
assign next_mbc_isolate = goingsleep | sleep_req_isol | MBC_SLEEP;
assign sleep_req_isol = SLEEP_REQ & MBC_ISOLATE_B;
always @ (posedge CIN or negedge RESETn) begin
if (~RESETn) begin
goingsleep <= `SD 1'b0;
MBC_SLEEP <= `SD 1'b1;
MBC_ISOLATE <= `SD 1'b1;
end
else begin
goingsleep <= `SD sleep_req_isol;
MBC_SLEEP <= `SD goingsleep;
MBC_ISOLATE <= `SD next_mbc_isolate;
end
end
always @ (negedge CIN or negedge RESETn) begin
if (~RESETn) MBC_RESET <= `SD 1'b1;
else MBC_RESET <= `SD MBC_ISOLATE;
end
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
wire RESETn_local = RESETn & CIN;
wire RESETn_local2 = RESETn & clr_ext_int_b;
// mbus_busy_b_isol
wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
// int_busy
wire int_busy = (WAKEUP_REQ & mbus_busy_b_isol & LRC_SLEEP);
// ext_int_dout
reg ext_int_dout;
always @ (posedge int_busy or negedge RESETn_local) begin
if (~RESETn_local) ext_int_dout <= `SD 0;
else ext_int_dout <= `SD 1;
end
// EXTERNAL_INT
always @ (posedge int_busy or negedge RESETn_local2) begin
if (~RESETn_local2) EXTERNAL_INT <= `SD 0;
else EXTERNAL_INT <= `SD 1;
end
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
always @* begin
if (~RESETn) COUT <= `SD 1'b1;
else if (MBC_ISOLATE) COUT <= `SD CIN;
else COUT <= `SD COUT_FROM_BUS;
if (~RESETn) DOUT <= `SD 1'b1;
else if (ext_int_dout) DOUT <= `SD 0;
else if (MBC_ISOLATE) DOUT <= `SD DIN;
else DOUT <= `SD DOUT_FROM_BUS;
end
//****************************************************************************
// SHORT ADDRESS (SHORT PREFIX) REGISTER
//****************************************************************************
wire RESETn_local3 = (RESETn & ADDR_CLR_B);
wire addr_update = (ADDR_WR_EN & (~MBC_ISOLATE));
always @ (posedge addr_update or negedge RESETn_local3) begin
if (~RESETn_local3) begin
ADDR_OUT <= `SD {`MBUS_DYNA_WIDTH{1'b1}};
ADDR_VALID <= `SD 0;
end
else begin
ADDR_OUT <= `SD ADDR_IN;
ADDR_VALID <= `SD 1;
end
end
endmodule // lname_mbus_member_ctrl
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_M_V
`define SKY130_FD_SC_LP__OR2_M_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_m (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_m (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_2_V
`define SKY130_FD_SC_MS__MUX4_2_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_2_V
|
#include <bits/stdc++.h> using namespace std; long sail(char ar[], long a, long m, long n) { for (int k = 0; k < a; k++) { if (m > 0) { if (ar[k] == E ) m--; } if (m < 0) { if (ar[k] == W ) m++; } if (n > 0) { if (ar[k] == N ) n--; } if (n < 0) { if (ar[k] == S ) n++; } if (n == 0 && m == 0) { return k + 1; } } return -1; } int main() { long a, b, c, d, e; cin >> a >> b >> c >> d >> e; char ar[100000]; for (int i = 0; i < a; i++) cin >> ar[i]; long m = d - b; long n = e - c; cout << sail(ar, a, m, n) << endl; } |
#include <bits/stdc++.h> using namespace std; long long a[35], b[35], k[35], p[35]; long long n, u, r, ans; void op1() { for (int i = 0; i < n; i++) a[i] = a[i] ^ b[i]; } void op2() { long long tmp[35]; for (int i = 0; i < n; i++) tmp[i] = a[p[i]] + r; for (int i = 0; i < n; i++) a[i] = tmp[i]; } void dfs(int t, int f) { long long x = 0; if ((t & 1) == 0) { for (int i = 0; i < n; i++) x += a[i] * k[i]; ans = max(x, ans); } if (t == 0) return; long long tmp[35]; for (int i = 0; i < n; i++) tmp[i] = a[i]; op2(); dfs(t - 1, 1); for (int i = 0; i < n; i++) a[i] = tmp[i]; if (f) { op1(); dfs(t - 1, 0); for (int i = 0; i < n; i++) a[i] = tmp[i]; } return; } int main() { cin >> n >> u >> r; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) cin >> k[i]; for (int i = 0; i < n; i++) cin >> p[i], p[i]--; ans = -100000000000000009; dfs(u, 1); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); signed main() { std::ios::sync_with_stdio(false); string str; cin >> str; long long int n = str.size(); string prf = ; vector<long long int> v(n, 0); for (long long int i = 0; i < n - 1; i++) if (str[i] != str[i + 1]) v[i] = 1; if (str[n - 1] == a ) v[n - 1] = 1; for (long long int i = 0; i < n; i++) cout << v[i] << ; } |
// --------------------------------------------------------------------
// Button Debouncer
// --------------------------------------------------------------------
module Button_Debouncer(
input clk, // "clk" is the clock
input PB, // "PB" is the glitched, asynchronous, active low push-button signal
output reg PB_state // 1 while the push-button is active (down)
);
reg PB_sync_0;
reg PB_sync_1;
reg [1:0] PB_cnt; // declare a 2-bit counter
// use two flipflops to synchronize the PB signal the "clk" clock domain
always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high
always @(posedge clk) PB_sync_1 <= PB_sync_0;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk) begin
if(PB_idle) PB_cnt <= 2'd0; // nothing's going on
else begin
PB_cnt <= PB_cnt + 2'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { int tc; int n; string str; cin >> n >> tc; cin >> str; vector<char> vc(3); vector<vector<int>> dp(6, vector<int>(n + 1, 0)); vc[0] = a ; vc[1] = b ; vc[2] = c ; int j, a = 0; do { for (int i = 0; i <= n - 1; i++) { dp[a][i + 1] = dp[a][i]; j = i % 3; if (str[i] != vc[j]) dp[a][i + 1]++; } a++; } while (next_permutation(vc.begin(), vc.end())); while (tc--) { int l, r, ans; cin >> l >> r; ans = r - l + 1; l--; for (int i = 0; i < 6; i++) { ans = min(ans, dp[i][r] - dp[i][l]); } cout << ans << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4BB_PP_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_intp2_16 (
clk,
data,
// outputs
intp2_00,
intp2_01,
intp2_02,
intp2_03,
intp2_04,
intp2_05,
intp2_06,
intp2_07,
intp2_08,
intp2_09,
intp2_10,
intp2_11,
intp2_12,
intp2_13,
intp2_14,
intp2_15);
input clk;
input [15:0] data;
// outputs
output [15:0] intp2_00;
output [15:0] intp2_01;
output [15:0] intp2_02;
output [15:0] intp2_03;
output [15:0] intp2_04;
output [15:0] intp2_05;
output [15:0] intp2_06;
output [15:0] intp2_07;
output [15:0] intp2_08;
output [15:0] intp2_09;
output [15:0] intp2_10;
output [15:0] intp2_11;
output [15:0] intp2_12;
output [15:0] intp2_13;
output [15:0] intp2_14;
output [15:0] intp2_15;
// internal registers
reg [15:0] data_s00 = 'd0;
reg [15:0] data_s01 = 'd0;
reg [15:0] data_s02 = 'd0;
reg [15:0] data_s03 = 'd0;
reg [15:0] data_s04 = 'd0;
reg [15:0] data_s05 = 'd0;
reg [15:0] data_s06 = 'd0;
reg [15:0] data_s07 = 'd0;
reg [15:0] data_s08 = 'd0;
reg [15:0] data_s09 = 'd0;
reg [15:0] data_s10 = 'd0;
reg [15:0] data_s11 = 'd0;
reg [15:0] data_s12 = 'd0;
reg [15:0] data_s13 = 'd0;
reg [15:0] data_s14 = 'd0;
reg [15:0] data_s15 = 'd0;
reg [15:0] data_s16 = 'd0;
reg [15:0] data_s17 = 'd0;
// internal signals
wire [15:0] intp2_0_s;
wire [15:0] intp2_1_s;
wire [15:0] intp2_2_s;
wire [15:0] intp2_3_s;
wire [15:0] intp2_4_s;
wire [15:0] intp2_5_s;
wire [15:0] intp2_6_s;
wire [15:0] intp2_7_s;
// delay registers
always @(posedge clk) begin
data_s00 <= data_s08;
data_s01 <= data_s09;
data_s02 <= data_s10;
data_s03 <= data_s11;
data_s04 <= data_s12;
data_s05 <= data_s13;
data_s06 <= data_s14;
data_s07 <= data_s15;
data_s08 <= data_s16;
data_s09 <= data_s17;
data_s10 <= intp2_0_s;
data_s11 <= intp2_1_s;
data_s12 <= intp2_2_s;
data_s13 <= intp2_3_s;
data_s14 <= intp2_4_s;
data_s15 <= intp2_5_s;
data_s16 <= intp2_6_s;
data_s17 <= intp2_7_s;
end
// interpolators (stage-2)
ad_mac_1 i_mac_1_0 (
.clk (clk),
.data_s0 (data_s00),
.data_s1 (data_s01),
.data_s2 (data_s02),
.data_s3 (data_s03),
.data_s4 (data_s04),
.data_s5 (data_s05),
.mac_data_0 (intp2_00),
.mac_data_1 (intp2_01));
// interpolators (stage-2)
ad_mac_1 i_mac_1_1 (
.clk (clk),
.data_s0 (data_s01),
.data_s1 (data_s02),
.data_s2 (data_s03),
.data_s3 (data_s04),
.data_s4 (data_s05),
.data_s5 (data_s06),
.mac_data_0 (intp2_02),
.mac_data_1 (intp2_03));
// interpolators (stage-2)
ad_mac_1 i_mac_1_2 (
.clk (clk),
.data_s0 (data_s02),
.data_s1 (data_s03),
.data_s2 (data_s04),
.data_s3 (data_s05),
.data_s4 (data_s06),
.data_s5 (data_s07),
.mac_data_0 (intp2_04),
.mac_data_1 (intp2_05));
// interpolators (stage-2)
ad_mac_1 i_mac_1_3 (
.clk (clk),
.data_s0 (data_s03),
.data_s1 (data_s04),
.data_s2 (data_s05),
.data_s3 (data_s06),
.data_s4 (data_s07),
.data_s5 (data_s08),
.mac_data_0 (intp2_06),
.mac_data_1 (intp2_07));
// interpolators (stage-2)
ad_mac_1 i_mac_1_4 (
.clk (clk),
.data_s0 (data_s04),
.data_s1 (data_s05),
.data_s2 (data_s06),
.data_s3 (data_s07),
.data_s4 (data_s08),
.data_s5 (data_s09),
.mac_data_0 (intp2_08),
.mac_data_1 (intp2_09));
// interpolators (stage-2)
ad_mac_1 i_mac_1_5 (
.clk (clk),
.data_s0 (data_s05),
.data_s1 (data_s06),
.data_s2 (data_s07),
.data_s3 (data_s08),
.data_s4 (data_s09),
.data_s5 (data_s10),
.mac_data_0 (intp2_10),
.mac_data_1 (intp2_11));
// interpolators (stage-2)
ad_mac_1 i_mac_1_6 (
.clk (clk),
.data_s0 (data_s06),
.data_s1 (data_s07),
.data_s2 (data_s08),
.data_s3 (data_s09),
.data_s4 (data_s10),
.data_s5 (data_s11),
.mac_data_0 (intp2_12),
.mac_data_1 (intp2_13));
// interpolators (stage-2)
ad_mac_1 i_mac_1_7 (
.clk (clk),
.data_s0 (data_s07),
.data_s1 (data_s08),
.data_s2 (data_s09),
.data_s3 (data_s10),
.data_s4 (data_s11),
.data_s5 (data_s12),
.mac_data_0 (intp2_14),
.mac_data_1 (intp2_15));
// interpolators (stage-1)
ad_intp2_8 i_intp2_8 (
.clk (clk),
.data (data),
.intp2_0 (intp2_0_s),
.intp2_1 (intp2_1_s),
.intp2_2 (intp2_2_s),
.intp2_3 (intp2_3_s),
.intp2_4 (intp2_4_s),
.intp2_5 (intp2_5_s),
.intp2_6 (intp2_6_s),
.intp2_7 (intp2_7_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_TB_V
`define SKY130_FD_SC_LP__O2BB2A_TB_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_lp__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_TB_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_src0_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_src0_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_src0_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_src0_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int dx[] = {0, 1, 0, -1}; const int dy[] = {1, 0, -1, 0}; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline long long read1() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int N = 200010; const int P = 1e9 + 7; int dp[110][110][110]; int pw[110]; int Add(int a, int b) { a += b; return a >= P ? a - P : a; } char ch[110]; int main() { int n, x; n = read(); x = read(); scanf( %s , ch + 1); for (int i = 1; i <= n; i++) dp[ch[i] - 0 ][i][i] = 1; pw[0] = pw[1] = 2; for (int i = 2; i <= x; i++) { pw[i] = (long long)(pw[i - 1]) * pw[i - 2] % P; for (int l = 1; l <= n; l++) for (int r = l; r <= n; r++) { dp[i][l][r] = Add((long long)(dp[i - 1][l][r]) * (r == n ? pw[i - 2] : 1) % P, (long long)(dp[i - 2][l][r]) * (l == 1 ? pw[i - 1] : 1) % P); for (int m = l; m <= r - 1; m++) dp[i][l][r] = Add(dp[i][l][r], (long long)(dp[i - 1][l][m]) * dp[i - 2][m + 1][r] % P); } } cout << dp[x][1][n] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_SYMBOL_V
`define SKY130_FD_SC_MS__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = (int)1e5 + 55; const int INF = (int)1e9 + 77; const int MOD = (int)1e9 + 7; const double PI = 2 * acos(0.0); const double EPS = 1e-7; const int N = (int)1e5 + 5; vector<vector<int>> adj; pair<int, int> cost[N]; int mn; bool vis[N]; long long ans; void dfs(int u) { if (vis[u]) return; vis[u] = 1; mn = min(mn, cost[u].first); for (int v : adj[u]) dfs(v); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; adj.resize(n + 1); for (int i = 1; i <= n; ++i) { int x; cin >> x; cost[i] = {x, i}; } for (int i = 0; i < m; ++i) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } for (int i = 1; i <= n; ++i) { int cur = cost[i].second; if (vis[cur]) continue; mn = INF; dfs(cur); ans += mn; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char s[100001]; int a[100001], m, l, r; scanf( %s%d , s, &m); int len = strlen(s); a[1] = 0; for (int i = 1; i < len; ++i) { if (s[i] == s[i - 1]) { a[i + 1] = a[i] + 1; } else { a[i + 1] = a[i]; } } while (m--) { scanf( %d%d , &l, &r); printf( %d n , a[r] - a[l]); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename... Args> void dbg(Args... args) { ((cout << args << ), ...); } const int N = 110; char t[N][N][N]; char f[N][N][N]; int main() { int n, m, k; cin >> n >> m >> k; for (int x = 1; x <= n; ++x) for (int y = 1; y <= m; ++y) for (int z = 1; z <= k; ++z) { cin >> t[x][y][z]; t[x][y][z] -= 0 ; } for (int x = 1; x <= n; ++x) for (int y = 1; y <= m; ++y) for (int z = 1; z <= k; ++z) { if (!t[x][y][z]) continue; bool tmp[3][3][3][3]{}; bool ok[3][3][3]{}; tmp[0][0][0][0] = 1, tmp[0][0][0][1] = 1, tmp[0][0][0][2] = 1; ok[0][0][0] = 1; for (int o = 0; o < 3; ++o) for (int p = 0; p < 3; ++p) for (int q = 0; q < 3; ++q) if (t[x + o][y + p][z + q]) { tmp[o][p][q][0] |= ((o > 0) ? ok[o - 1][p][q] : false); tmp[o][p][q][1] |= ((p > 0) ? ok[o][p - 1][q] : false); tmp[o][p][q][2] |= ((q > 0) ? ok[o][p][q - 1] : false); int good = tmp[o][p][q][0] + tmp[o][p][q][1] + tmp[o][p][q][2]; ok[o][p][q] = good; if (good == 1) { if (o == 0 && p == 1 && q == 0 || o == 0 && p == 0 && q == 1 || o == 1 && p == 0 && q == 0 || o == 0 && p == 0 && q == 0) continue; if (o > 0 and ok[o - 1][p][q]) f[x + o - 1][y + p][z + q] = 1; if (p > 0 and ok[o][p - 1][q]) f[x + o][y + p - 1][z + q] = 1; if (q > 0 and ok[o][p][q - 1]) f[x + o][y + p][z + q - 1] = 1; } } } int cnt = 0; for (int x = 1; x <= n; ++x) for (int y = 1; y <= m; ++y) for (int z = 1; z <= k; ++z) { if (f[x][y][z] == 1) ++cnt; } dbg(cnt); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_4_V
`define SKY130_FD_SC_LS__NAND3_4_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A41OI_PP_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_PP_SYMBOL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: rxlengthfifo_128x13.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rxlengthfifo_128x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [12:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [12:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [12:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [12:0] q = sub_wire1[12:0];
wire rdempty = sub_wire2;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Stratix IV",
dcfifo_mixed_widths_component.lpm_numwords = 128,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 13,
dcfifo_mixed_widths_component.lpm_widthu = 7,
dcfifo_mixed_widths_component.lpm_widthu_r = 7,
dcfifo_mixed_widths_component.lpm_width_r = 13,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "13"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "13"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "13"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "13"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 13 0 INPUT NODEFVAL "data[12..0]"
// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 13 0 data 0 0 13 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module usb_fifo_writer
#(parameter BUS_WIDTH = 16,
parameter NUM_CHAN = 2,
parameter FIFO_WIDTH = 32)
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [FIFO_WIDTH-1:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [BUS_WIDTH-1:0] usbdata_delayed ;
reg writing ;
wire [FIFO_WIDTH-1:0] usbdata_packed ;
wire WR_packed ;
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [FIFO_WIDTH-1:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
reg [31:0] usbdata_final;
reg WR_final;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
/* Parse header and forward to ram */
reg [3:0]reader_state;
reg [4:0]channel ;
reg [9:0]read_length ;
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter WAIT = 4'd2;
parameter FORWARD = 4'd3;
`define CHANNEL 20:16
`define PKT_SIZE 512
always @(posedge txclk)
begin
if (reset)
begin
reader_state <= 0;
WR_channel <= 0;
WR_done_channel <= 0;
end
else
case (reader_state)
IDLE: begin
if (WR_final)
reader_state <= HEADER;
end
// Store channel and forware header
HEADER: begin
channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL]) ;
WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN : usbdata_final[`CHANNEL])] <= 1;
//channel <= usbdata_final[`CHANNEL] ;
//WR_channel[usbdata_final[`CHANNEL]] <= 1;
ram_data <= usbdata_final;
read_length <= 10'd4 ;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
if (read_length == `PKT_SIZE)
reader_state <= IDLE;
else if (WR_final)
reader_state <= FORWARD;
end
FORWARD: begin
WR_channel[channel] <= 1;
ram_data <= usbdata_final;
read_length <= read_length + 10'd4;
reader_state <= WAIT;
end
endcase
end
endmodule |
#include <bits/stdc++.h> int main() { int n, s[10001], ss[10001]; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &s[i]); for (int i = 1; i < n; i++) { ss[i] = abs(s[i] - s[i + 1]); } ss[n] = abs(s[n] - s[1]); int t, min = 999999; for (int i = 1; i <= n; i++) { if (min > ss[i]) { min = ss[i]; t = i; } } if (t != n) printf( %d %d n , t, t + 1); else printf( %d %d n , t, 1); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read(T& x) { x = 0; int f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) f |= (ch == - ), ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x = f ? -x : x; } const int N = 3e5 + 10; const int INF = 2000000000; int n, k, i, ans, minx, maxx, miny, maxy, x[N], y[N]; int main() { read(n); minx = miny = INF, maxx = maxy = -INF; for (i = 0; i < n; ++i) { read(x[i]), read(y[i]); minx = min(minx, x[i]); miny = min(miny, y[i]); maxx = max(maxx, x[i]); maxy = max(maxy, y[i]); } for (ans = -INF, i = 0; i < n; ++i) { ans = max(ans, 2 * (maxx - x[i]) + 2 * (maxy - y[i])); ans = max(ans, 2 * (maxx - x[i]) + 2 * (y[i] - miny)); ans = max(ans, 2 * (x[i] - minx) + 2 * (maxy - y[i])); ans = max(ans, 2 * (x[i] - minx) + 2 * (y[i] - miny)); } printf( %d%c , ans, n == 3 ? n : ); for (i = 4; i <= n; ++i) printf( %d%c , 2 * (maxx - minx + maxy - miny), i == n ? n : ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } const long long L = 1e5 + 5; long long arr[L]; long long bo[L]; long long gi[L]; long long bg[L]; priority_queue<long long> val; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, b, g; cin >> b >> g; long long ans = 0; long long x = -1e18, y = 1e18; for (i = 0; i < b; i++) { bg[i] = 1; cin >> bo[i]; arr[i] = g - 1; ans += bo[i]; x = max(bo[i], x); } for (i = 0; i < g; i++) { cin >> gi[i]; ans += gi[i]; val.push(gi[i]); y = min(gi[i], y); } if (y < x) { cout << -1 << endl; return 0; } sort(bo, bo + b); i = b - 1; while (!val.empty() && i >= 0) { if (val.top() >= bo[i]) { if (arr[i] == 0) { if (bo[i] == val.top()) { ans -= bo[i]; val.pop(); } i--; continue; } arr[i]--; val.pop(); } else i--; } for (i = 0; i < b; i++) ans += arr[i] * bo[i]; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; const int MOD = 1000000007; int t, k, dp[N][N][2]; char l[N], r[N], s[N]; void add(int &a, int b) { a += b; if (a >= MOD) a -= MOD; } int dfs(int l, int pos, int f, int limit) { if (l == -1) return f; if (!limit && dp[l][pos][f] != -1) return dp[l][pos][f]; int up = limit ? (s[l] - 0 ) : 9, ret = 0; for (int i = 0; i <= up; i++) { if (i == 4 || i == 7) { int ff = f; if (pos != 1001) ff |= ((pos - l) <= k); add(ret, dfs(l - 1, l, ff, limit && (i == up))); } else { add(ret, dfs(l - 1, pos, f, limit && (i == up))); } } if (!limit) dp[l][pos][f] = ret; return ret; } int gao(char *a) { strcpy(s, a); reverse(s, s + strlen(s)); return dfs(strlen(a) - 1, 1001, 0, 1); } void sub(char *s) { int len = strlen(s), l = strlen(s) - 1; while (s[l] == 0 ) s[l] = 9 , l--; s[l]--; if (s[0] == 0 && len > 1) { for (int i = 1; i <= len; i++) s[i - 1] = s[i]; } } int main() { memset(dp, -1, sizeof(dp)); cin >> t >> k; while (t--) { cin >> l >> r; sub(l); cout << ((gao(r) - gao(l)) % MOD + MOD) % MOD << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 1e18 + 9; const long long MAX_SIZE = 1e7 + 1; long long _t = 1, _T, csn; long long max(long long a, long long b) { if (a < b) return b; return a; } long long min(long long a, long long b) { if (a > b) return b; return a; } long long mmi(long long a, long long m) { long long m0 = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long nxor(long long n) { if (n % 4 == 0) return n; if (n % 4 == 1) return 1; if (n % 4 == 2) return n + 1; return 0; } long long sum(long long n) { return ((n * (n + 1)) / 2); } long long modsum(long long n, long long m) { long long ans = n % m; ans *= (n + 1) % m; ans %= m; ans *= mmi(2, m); return ans % m; } long long leap(long long y) { if (y % 400 == 0) return 1; else if (y % 100 == 0) return 0; else if (y % 4 == 0) return 1; else return 0; } void solve(); signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); bool multicases = 0; if (multicases) cin >> _t; _T = _t; while (_t--) solve(); return 0; } void solve() { csn = _T - _t; long long n; cin >> n; ; map<string, long long> m; string s, ts; vector<vector<pair<long long, string>>> ans; for (long long i = 0; i < n; i += 1) { cin >> s; vector<pair<long long, string>> tv; for (long long j = 0; j < 9; j += 1) { for (long long k = 1; k < 9 - j + 1; k += 1) { ts = s.substr(j, k); m[ts]++; tv.emplace_back(make_pair(k, ts)); } } sort(tv.begin(), tv.end()); for (long long j = 1; j < tv.size(); j += 1) if (tv[j].second == tv[j - 1].second) m[tv[j].second]--; ans.emplace_back(tv); } for (long long i = 0; i < n; i += 1) { for (long long j = 0; j < ans[i].size(); j += 1) if (m[ans[i][j].second] == 1) { cout << ans[i][j].second << n ; ; break; } } return; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_iobuf (
input ADC_CLK,
input ADC_DCO_P, ADC_DCO_N,
(* IOB="TRUE" *)
output reg ADC_DCO,
input ADC_FCO_P, ADC_FCO_N,
(* IOB="TRUE" *)
output reg ADC_FCO,
(* IOB="TRUE" *)
input ADC_ENC,
output ADC_ENC_P, ADC_ENC_N,
input [3:0] ADC_IN_P, ADC_IN_N,
output [13:0] ADC_IN0, ADC_IN1, ADC_IN2, ADC_IN3
);
(* IOB="TRUE" *)
wire ADC_DCO_BUF;
(* IOB="TRUE" *)
wire ADC_FCO_BUF;
(* IOB="TRUE" *)
wire [3:0] ADC_IN_BUF;
(* IOB="TRUE" *)
wire ADC_ENC_BUF;
(* IOB="TRUE" *)
reg [3:0] ADC_IN;
// I/O BUFFERS
always @(negedge ADC_CLK)
ADC_DCO <= ADC_DCO_BUF;
always @(negedge ADC_CLK)
ADC_FCO <= ADC_FCO_BUF;
always @(negedge ADC_CLK)
ADC_IN <= ADC_IN_BUF;
//always @(negedge ADC_CLK)
// ADC_ENC_BUF <= ADC_ENC;
assign ADC_ENC_BUF = ADC_ENC;
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_FCO (
.O(ADC_FCO_BUF), // Clock buffer output
.I(ADC_FCO_P), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_FCO_N) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS #( // Specify the input I/O standard
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
)
IBUFDS_ADC_DCO (
.O(ADC_DCO_BUF), // Buffer output
.I(ADC_DCO_P), // Diff_p buffer input (connect directly to top-level port)
.IB(ADC_DCO_N) // Diff_n buffer input (connect directly to top-level port)
);
//BUFG ADC_BUFG_INST (.I(ADC_FCO_PB), .O(ADC_FCO));
OBUFDS #(
.IOSTANDARD("LVDS_25") // Specify the output I/O standard
) OBUFDS_ADC_ENC (
.O(ADC_ENC_P), // Diff_p output (connect directly to top-level port)
.OB(ADC_ENC_N), // Diff_n output (connect directly to top-level port)
.I(ADC_ENC_BUF) // Buffer input
);
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_0 (
.O(ADC_IN_BUF[0]), // Clock buffer output
.I(ADC_IN_P[0]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[0]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_1 (
.O(ADC_IN_BUF[1]), // Clock buffer output
.I(ADC_IN_P[1]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[1]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_2 (
.O(ADC_IN_BUF[2]), // Clock buffer output
.I(ADC_IN_P[2]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[2]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS #(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_3 (
.O(ADC_IN_BUF[3]), // Clock buffer output
.I(ADC_IN_P[3]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[3]) // Diff_n clock buffer input (connect directly to top-level port)
);
reg [1:0] fco_sync;
always @(negedge ADC_CLK) begin
fco_sync <= {fco_sync[0],ADC_FCO};
end
wire adc_des_rst;
assign adc_des_rst = fco_sync[0] & !fco_sync[1];
reg [15:0] adc_des_cnt;
always @(negedge ADC_CLK) begin
if(adc_des_rst)
adc_des_cnt[0] <= 1;
else
adc_des_cnt <= {adc_des_cnt[14:0],1'b0};
end
wire adc_load;
assign adc_load = adc_des_cnt[12];
reg [13:0] adc_out_sync [3:0];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: gen
reg [13:0] adc_des;
always @(negedge ADC_CLK) begin
adc_des <= {adc_des[12:0],ADC_IN[i]};
end
reg [13:0] adc_des_syn;
always @(negedge ADC_CLK) begin
if(adc_load)
adc_des_syn <= adc_des;
end
always @(posedge ADC_ENC)
adc_out_sync[i] <= adc_des_syn;
end
endgenerate
assign ADC_IN0 = adc_out_sync[0];
assign ADC_IN1 = adc_out_sync[1];
assign ADC_IN2 = adc_out_sync[2];
assign ADC_IN3 = adc_out_sync[3];
`ifdef SYNTHESIS_
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(ADC_CLK),
.TRIG0({ADC_IN0, adc_load, adc_des_rst, fco_sync, ADC_IN[0]})
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; string s1( ABC ), s2( ACB ), s3( BAC ), s4( BCA ), s5( CAB ), s6( CBA ); int state = 0; if (s.find(s1) != -1) state = 1; else if (s.find(s2) != -1) state = 1; else if (s.find(s3) != -1) state = 1; else if (s.find(s4) != -1) state = 1; else if (s.find(s5) != -1) state = 1; else if (s.find(s6) != -1) state = 1; else state = 0; if (state == 0) cout << No << endl; else cout << Yes << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct superset { multiset<int> m; void insert(int x) { m.insert(x); } void erase(int x) { m.erase(m.find(x)); } int query() { return *m.begin(); } }; int n, m; int val[65536 * 4]; superset cl[65536 * 4]; vector<int> g[65536 * 4]; vector<int> lis[65536 * 4]; int dfn[65536 * 4]; int DFN; int low[65536 * 4]; int st[65536 * 4], stsiz; int tot; vector<int> v[65536 * 4]; void addedge(int x, int y) { v[x].push_back(y); v[y].push_back(x); } void tarjan(int x, int p) { st[++stsiz] = x; dfn[x] = low[x] = ++DFN; for (int i = 0; i < g[x].size(); i++) { int y = g[x][i]; if (y == p) continue; if (!dfn[y]) { tarjan(y, x); if (low[y] >= dfn[x]) { ++tot; while (st[stsiz] != y) lis[tot].push_back(st[stsiz--]); stsiz--; lis[tot].push_back(y); lis[tot].push_back(x); for (int j = 0; j < lis[tot].size(); j++) addedge(lis[tot][j], tot); } low[x] = min(low[x], low[y]); } else low[x] = min(low[x], dfn[y]); } } struct segmenttree { int tree[65536 * 4 * 2 + 10]; void up(int id) { tree[id] = min(tree[id << 1], tree[id << 1 | 1]); } void update(int x, int y) { x = x + 65536 * 4 - 1; tree[x] = y; x = x / 2; while (x) up(x), x = x / 2; } int query(int a, int b, int l, int r, int id) { if (l >= a and r <= b) return tree[id]; if (b <= (l + r) / 2) return query(a, b, l, (l + r) / 2, id << 1); else if (a > (l + r) / 2) return query(a, b, (l + r) / 2 + 1, r, id << 1 | 1); else return min(query(a, b, l, (l + r) / 2, id << 1), query(a, b, (l + r) / 2 + 1, r, id << 1 | 1)); } int query(int a, int b) { return query(a, b, 1, 65536 * 4, 1); } } trcyx; int pa[65536 * 4]; int son[65536 * 4]; int siz[65536 * 4]; int lead[65536 * 4]; int len[65536 * 4]; int dep[65536 * 4]; void dfs1(int x, int p) { siz[x] = 1; dep[x] = dep[p] + 1; for (int i = 0; i < v[x].size(); i++) { if (v[x][i] == p) continue; dfs1(v[x][i], x); siz[x] += siz[v[x][i]]; if (siz[v[x][i]] > siz[son[x]]) son[x] = v[x][i]; } } void dfs2(int x, int p, int leader) { dfn[x] = ++DFN; pa[x] = p; if (!leader) leader = x; lead[x] = leader, len[leader]++; if (son[x]) dfs2(son[x], x, leader); for (int i = 0; i < v[x].size(); i++) if (v[x][i] != son[x] and v[x][i] != p) dfs2(v[x][i], x, 0); if (lis[x].size()) { for (int i = 0; i < lis[x].size(); i++) if (lis[x][i] != pa[x]) cl[x].insert(val[lis[x][i]]); val[x] = cl[x].query(); } trcyx.update(dfn[x], val[x]); } void build() { tot = n; tarjan(1, 0); dfs1(1, 0); memset(dfn, 0, sizeof(dfn)); DFN = 0; dfs2(1, 0, 0); } int solve(int x, int y) { int ans = 1e9; while (lead[x] != lead[y]) { if (dep[lead[x]] < dep[lead[y]]) swap(x, y); ans = min(ans, trcyx.query(dfn[lead[x]], dfn[x])); x = pa[lead[x]]; } if (dfn[x] > dfn[y]) swap(x, y); ans = min(ans, trcyx.query(dfn[x], dfn[y])); if (lis[x].size()) ans = min(ans, val[pa[x]]); return ans; } void change(int x, int y) { if (pa[x]) { cl[pa[x]].erase(val[x]); cl[pa[x]].insert(y); val[pa[x]] = cl[pa[x]].query(); trcyx.update(dfn[pa[x]], val[pa[x]]); } val[x] = y; trcyx.update(dfn[x], y); } int main() { int T; scanf( %d%d%d , &n, &m, &T); for (int i = 1; i <= n; i++) scanf( %d , &val[i]); while (m--) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } build(); while (T--) { char ctrl[10]; scanf( %s , ctrl); int x, y; scanf( %d%d , &x, &y); if (ctrl[0] == A ) printf( %d n , solve(x, y)); else change(x, y); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_SYMBOL_V
`define SKY130_FD_SC_HS__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, s, i, j, k; bool A[301][301]; char str[301]; int main() { scanf( %d%d%d , &n, &m, &s); for (i = 0; i < n; i++) { scanf( %s , str); for (j = 0; j < m; j++) A[i][j] = str[j] == * ; } for (i = 1; 2 * i + 1 <= min(n, m); i++) { for (j = i; j + i < n; j++) { for (k = i; k + i < m; k++) if (A[j][k] && A[j][k + i] && A[j][k - i] && A[j + i][k] && A[j - i][k]) { s--; if (!s) break; } if (!s) break; } if (!s) break; } if (s) printf( -1 n ); else { j++; k++; printf( %d %d n%d %d n%d %d n%d %d n%d %d n , j, k, j - i, k, j + i, k, j, k - i, j, k + i); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1.0); const long double EPS = 1e-14; const long long INF = 1e18; const long long MOD = 1e9 + 7; const long long p = 97; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.precision(9); long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } vector<vector<long long>> pr(n, vector<long long>(6, INF)); pr[0] = vector<long long>(6, -1); for (long long i = 1; i < n; i++) { for (long long j = 1; j <= 5; j++) { if (pr[i - 1][j] == INF) continue; for (long long z = 1; z <= 5; z++) { if (a[i] > a[i - 1]) { if (z > j) { pr[i][z] = j; } } else if (a[i] < a[i - 1]) { if (z < j) { pr[i][z] = j; } } else { if (z != j) { pr[i][z] = j; } } } } } long long last = -1; for (long long i = 1; i <= 5; i++) { if (pr[n - 1][i] != INF) last = i; } if (last == -1) { cout << -1; return 0; } long long num = n - 1; vector<long long> ans; while (num != -1) { ans.push_back(last); last = pr[num][last]; num--; } reverse(ans.begin(), ans.end()); for (long long i = 0; i < ans.size(); i++) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, i, a, b, x, y, o, z, p, q, sum, c; int main() { cin >> n; vector<long long> v; for (i = 0; i < n; i++) { cin >> x; if (x == 0) o++; else v.push_back(x); } sort(v.begin(), v.end()); a = 0; b = v.size() - 1; sum += o * (o - 1) / 2; if (v.size() > 1) { while (a < b) { if (v[a] > 0 || v[b] < 0) break; else { if (v[a] + v[b] < 0) a++; else if (v[a] + v[b] > 0) b--; else { p = 1; q = 1; x = v[a]; a++; y = v[b]; b--; while (1) { if (v[a] == x) { p++; a++; } else break; } while (1) { if (v[b] == y) { q++; b--; } else break; } sum += p * q; } } } } cout << sum; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLRBN_PP_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_PP_SYMBOL_V
|
//faux_sata_hd_phy.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module faux_sata_hd_phy (
//Inputs/Outputs
input rst, //reset
input clk,
//Data Interface
output reg [31:0] tx_dout,
output reg tx_isk,
output reg tx_set_elec_idle,
output reg rx_byte_is_aligned,
input [31:0] rx_din,
input [3:0] rx_isk,
input rx_is_elec_idle,
input comm_reset_detect,
input comm_wake_detect,
output reg tx_comm_reset,
output reg tx_comm_wake,
output [3:0] lax_state,
output reg hd_ready,
output phy_ready
);
//Parameters
parameter IDLE = 4'h0;
parameter WAIT_FOR_NO_RESET = 4'h1;
parameter SEND_INIT = 4'h2;
parameter WAIT_FOR_WAKE = 4'h3;
parameter WAIT_FOR_NO_WAKE = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter STOP_SEND_WAKE = 4'h6;
parameter SEND_CONFIGURE_END = 4'h7;
parameter WAIT_FOR_DIALTONE = 4'h8;
parameter SEND_ALIGN = 4'h9;
parameter WAIT_FOR_ALIGN = 4'hA;
parameter READY = 4'hB;
parameter SEND_FIRST_ALIGNMENT = 4'hC;
parameter SEND_SECOND_ALIGNMENT = 4'hD;
parameter INITIALIZE_TIMEOUT = 100;
//Registers/Wires
reg [3:0] state = IDLE;
reg [31:0] timer;
reg [7:0] align_count;
wire align_detected;
wire dialtone_detected;
wire timeout;
//Sub Modules
//Asynchronous Logic
assign lax_state = state;
assign align_detected = ((rx_isk > 0) && (rx_din == `PRIM_ALIGN));
assign dialtone_detected = ((rx_isk == 0) && (rx_din == `DIALTONE));
assign timeout = (timer == 0);
assign phy_ready = (state == READY);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
tx_dout <= 0;
tx_isk <= 0;
tx_set_elec_idle <= 1;
timer <= 0;
hd_ready <= 0;
rx_byte_is_aligned <= 0;
align_count <= 0;
end
else begin
tx_comm_reset <= 0;
tx_comm_wake <= 0;
rx_byte_is_aligned <= 0;
if (state == READY) begin
align_count <= align_count + 1;
end
if (timer > 0) begin
timer <= timer - 1;
end
if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
$display("faux_sata_hd: Asynchronous RESET detected");
state <= IDLE;
end
case (state)
IDLE: begin
align_count <= 0;
hd_ready <= 0;
tx_set_elec_idle <= 1;
if (comm_reset_detect) begin
//detected a reset from the host
$display("faux_sata_hd: RESET detected");
state <= WAIT_FOR_NO_RESET;
end
end
WAIT_FOR_NO_RESET: begin
if (!comm_reset_detect) begin
//host stopped sending reset
$display("faux_sata_hd: RESET deasserted");
hd_ready <= 0;
tx_set_elec_idle <= 1;
state <= SEND_INIT;
end
end
SEND_INIT: begin
//XXX: I may need to send more than one of these
$display("faux_sata_hd: send INIT");
tx_comm_reset <= 1;
state <= WAIT_FOR_WAKE;
end
WAIT_FOR_WAKE: begin
if (comm_wake_detect) begin
$display ("faux_sata_hd: WAKE detected");
state <= WAIT_FOR_NO_WAKE;
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
$display ("faux_sata_hd: WAKE deasserted");
state <= SEND_WAKE;
end
end
SEND_WAKE: begin
$display ("faux_sata_hd: send WAKE");
tx_comm_wake <= 1;
state <= STOP_SEND_WAKE;
end
STOP_SEND_WAKE: begin
$display ("faux_sata_hd: stop sending WAKE");
state <= WAIT_FOR_DIALTONE;
end
WAIT_FOR_DIALTONE: begin
if (dialtone_detected) begin
$display ("faul_sata_hd: detected dialtone");
state <= SEND_ALIGN;
end
end
SEND_ALIGN: begin
$display ("faul_sata_hd: send aligns");
tx_set_elec_idle <= 0;
tx_dout <= `PRIM_ALIGN;
tx_isk <= 1;
state <= WAIT_FOR_ALIGN;
timer <= 32'h`INITIALIZE_TIMEOUT;
rx_byte_is_aligned <= 1;
end
WAIT_FOR_ALIGN: begin
rx_byte_is_aligned <= 1;
if (align_detected) begin
$display ("faux_sata_hd: detected ALIGN primitive from host");
$display ("faux_sata_hd: Ready");
tx_dout <= `PRIM_ALIGN;
tx_isk <= 1;
timer <= 0;
state <= READY;
end
else if (timeout) begin
$display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
state <= IDLE;
end
end
READY: begin
hd_ready <= 1;
rx_byte_is_aligned <= 1;
tx_isk <= 1;
tx_dout <= `PRIM_SYNC;
if (align_count == 255) begin
tx_dout <= `PRIM_ALIGN;
state <= SEND_FIRST_ALIGNMENT;
end
end
SEND_FIRST_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_isk <= 1;
tx_dout <= `PRIM_ALIGN;
state <= SEND_SECOND_ALIGNMENT;
end
SEND_SECOND_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_isk <= 1;
tx_dout <= `PRIM_ALIGN;
state <= READY;
end
default: begin
$display ("faux_sata_hd: In undefined state!");
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.02.2016 18:21:15
// Design Name:
// Module Name: toplevelv
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module toplevel
(
GCLK,
DC,
RES,
SCLK,
SDIN,
VBAT,
VDD,
JA1,
JA2,
JA3,
JA4,
JA7,
JA8,
JA9,
JA10,
JB1,
JB2,
JB3,
JB4,
JB7,
JB8,
JB9,
JB10,
SW0,
SW1,
SW2,
SW3,
SW4,
SW5,
SW6,
SW7,
BTNC,
BTND,
BTNL,
BTNR,
BTNU,
LD0,
LD1,
LD2,
LD3,
LD4,
LD5,
LD6,
LD7
);
input wire GCLK;
inout wire JA1;
inout wire JA2;
inout wire JA3;
inout wire JA4;
inout wire JA7;
inout wire JA8;
inout wire JA9;
inout wire JA10;
inout wire JB1;
inout wire JB2;
inout wire JB3;
inout wire JB4;
inout wire JB7;
inout wire JB8;
inout wire JB9;
inout wire JB10;
input wire BTNC;
input wire BTND;
input wire BTNL;
input wire BTNR;
input wire BTNU;
output wire DC;
output wire RES;
output wire SCLK;
output wire SDIN;
output wire VBAT;
output wire VDD;
input wire SW0;
input wire SW1;
input wire SW2;
input wire SW3;
input wire SW4;
input wire SW5;
input wire SW6;
input wire SW7;
output wire LD0;
output wire LD1;
output wire LD2;
output wire LD3;
output wire LD4;
output wire LD5;
output wire LD6;
output wire LD7;
reg [127:0] str0 = "----------------";
reg [127:0] str1 = "----------------";
reg [127:0] str2 = "----------------";
reg [127:0] str3 = "----------------";
reg oled_ready = 1'b0;
assign LD7 = oled_ready;
ZedboardOLED OLED
(
.clear(BTND),
.refresh(oled_ready),
.s1(str0),
.s2(str1),
.s3(str2),
.s4(str3),
.DC(DC),
.RES(RES),
.SCLK(SCLK),
.SDIN(SDIN),
.VBAT(VBAT),
.VDD(VDD),
.CLK(GCLK)
);
wire [15:0] temp_data;
wire [15:0] x_axis_data;
wire [15:0] y_axis_data;
wire [15:0] z_axis_data;
wire [15:0] ang_x;
PmodGYRO GYRO_0
(
.clk(GCLK),
.RST(BTND),
.JA({JA4, JA3, JA2, JA1}),
.temp_data_out(temp_data),
.x_axis_out(x_axis_data),
.y_axis_out(y_axis_data),
.z_axis_out(z_axis_data),
.ang_x(ang_x)
);
wire [127:0] w_str_x;
wire [127:0] w_str_y;
wire [127:0] w_str_z;
wire [127:0] w_str_t;
wire [127:0] w_str_ax;
D2STR_D#(.len(4)) d2str_gyro_x
(
.GCLK(GCLK),
.str(w_str_x),
.d(x_axis_data)
);
D2STR_D#(.len(4)) d2str_gyro_y
(
.GCLK(GCLK),
.str(w_str_y),
.d(y_axis_data)
);
D2STR_D#(.len(4)) d2str_gyro_z
(
.GCLK(GCLK),
.str(w_str_z),
.d(z_axis_data)
);
D2STR_D#(.len(4)) d2str_gyro_t
(
.GCLK(GCLK),
.str(w_str_t),
.d(temp_data)
);
D2STR_D#(.len(4)) d2str_gyro_ax
(
.GCLK(GCLK),
.str(w_str_ax),
.d(ang_x)
);
// =============================================
// Pmod ACL
// =============================================
wire [15:0] acl_x;
wire [15:0] acl_y;
wire [15:0] acl_z;
PmodACL ACL_0
(
.CLK(GCLK),
.RST(BTND),
.SDI(JB3),
.SDO(JB2),
.SCLK(JB4),
.SS(JB1),
.x_out(acl_x),
.y_out(acl_y),
.z_out(acl_z)
);
wire [127:0] acl_x_str;
wire [127:0] acl_y_str;
wire [127:0] acl_z_str;
D2STR_D#(.len(4)) d2str_acl_x
(
.GCLK(GCLK),
.str(acl_x_str),
.d(acl_x)
);
D2STR_D#(.len(4)) d2str_acl_y
(
.GCLK(GCLK),
.str(acl_y_str),
.d(acl_y)
);
D2STR_D#(.len(4)) d2str_acl_z
(
.GCLK(GCLK),
.str(acl_z_str),
.d(acl_z)
);
// =============================================
// OLED infrastructure
// =============================================
wire oled_refresh_clk;
CLK_DIV oled_refresh_clk
(
.GCLK(GCLK),
.out(oled_refresh_clk),
.T(64'd3333333)
);
always @(posedge GCLK) begin
if (BTNC) begin
oled_ready <= 1'b1;
end
end
always @(posedge oled_refresh_clk) begin
str0 <= SW7 ? w_str_x : acl_x_str;
str1 <= SW7 ? w_str_y : acl_y_str;
str2 <= SW7 ? w_str_z : acl_z_str;
str3 <= w_str_t;
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 52; const int INF = 1e9; int mat[N][N]; int n, k; struct edge { int from, to, cap, cost, flow; edge(int from, int to, int cap, int cost) : from(from), to(to), cap(cap), cost(cost) { flow = 0; } }; vector<edge> e; vector<int> g[N]; void add_edge(int from, int to, int cap, int cost) { g[from].push_back(e.size()); e.push_back(edge(from, to, cap, cost)); g[to].push_back(e.size()); e.push_back(edge(to, from, 0, -cost)); } int d[N]; int ptr[N]; bool bfs() { d[1] = 1; queue<int> q; q.push(1); while (!q.empty()) { int v = q.front(); q.pop(); for (int id : g[v]) { int to = e[id].to; if (e[id].flow == e[id].cap) continue; if (d[to] == -1) { d[to] = d[v] + 1; q.push(to); } } } return d[n] != -1; } int dfs(int v, int flow) { if (!flow || v == n) return flow; for (; ptr[v] < (int)g[v].size(); ++ptr[v]) { int id = g[v][ptr[v]]; int to = e[id].to; if (d[to] == d[v] + 1) { int pushed = dfs(to, min(flow, e[id].cap - e[id].flow)); if (pushed) { e[id].flow += pushed; e[id ^ 1].flow -= pushed; return pushed; } } } return 0; } int dinic() { int flow = 0; while (1) { fill(d, d + N, -1); fill(ptr, ptr + N, 0); if (!bfs()) return flow; while (int pushed = dfs(1, INF)) { flow += pushed; } } return flow; } char in_que[N]; int from[N]; void show(edge e) { cout << ( << e.from << , << e.to << , << e.flow << , << e.cap << , << e.cost << ) << endl; } vector<int> spfa() { fill(d, d + N, INF); fill(in_que, in_que + N, 0); d[1] = 0; queue<int> q; q.push(1); in_que[1] = 1; while (!q.empty()) { int v = q.front(); q.pop(); in_que[v] = 0; for (int id : g[v]) { int to = e[id].to; if (e[id].cap == e[id].flow) continue; if (d[to] > d[v] + e[id].cost) { d[to] = d[v] + e[id].cost; from[to] = id; if (!in_que[to]) { in_que[to] = 1; q.push(to); } } } } if (d[n] == INF) return {}; int v = n; vector<int> ret; while (v != 1) { ret.push_back(from[v]); v = e[from[v]].from; } reverse(ret.begin(), ret.end()); return ret; } int mcf(int flow) { int cost = 0; while (1) { vector<int> kek = spfa(); if (kek.empty()) return flow; int delta = 1000000; int sum = 0; for (int id : kek) { delta = min(delta, e[id].cap - e[id].flow); sum += e[id].cost; } if (sum > 0) delta = min(delta, (k - cost) / sum); for (int id : kek) { e[id].flow += delta; e[id ^ 1].flow -= delta; cost += e[id].cost * delta; } flow += delta; if (!delta) return flow; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) { cin >> mat[i][j]; if (!mat[i][j]) continue; add_edge(i, j, mat[i][j], 0); } int din = 0; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) { if (!mat[i][j]) continue; add_edge(i, j, k, 1); } int ans = mcf(din); cout << ans; } |
#include <bits/stdc++.h> using namespace std; int n; std::vector<int> G[100005]; int color[100005]; void DFS(int s, int co) { color[s] = co; for (int i = 0; i < G[s].size(); i++) { int to = G[s][i]; if (color[to] == 0) { DFS(to, -1 * co); } } } int main(int argc, char const *argv[]) { scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } int s1 = 0; long long ans = 0; DFS(1, 1); for (int i = 1; i <= n; i++) if (color[i] == -1) s1++; printf( %lld n , 1LL * (n - s1) * s1 - 1LL * n + 1LL); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 0x7f7f7f7f7f7f7f7f; struct sta { int s; long long k, val; } p[105]; int n, m; long long b, f[(1 << 20) + 5]; bool cmp(sta a, sta b) { return a.k < b.k; } void init() { memset(f, -1, sizeof f); scanf( %d%d , &n, &m); cin >> b; int t, a; for (int i = 0; i < n; i++) { scanf( %lld%lld%d , &p[i].val, &p[i].k, &t); p[i].s = 0; for (int j = 0; j < t; j++) { scanf( %d , &a); p[i].s |= (1 << (a - 1)); } } sort(p, p + n, cmp); } long long solve() { f[0] = 0; int t = (1 << m) - 1; long long ans = inf; for (int i = 0; i < n; i++) { for (int j = 0; j <= t; j++) { if (f[j] == -1) continue; int u = p[i].s | j; if (f[u] == -1) f[u] = p[i].val + f[j]; else f[u] = min(f[u], p[i].val + f[j]); } if (f[t] != -1) ans = min(ans, f[t] + p[i].k * b); } return ans == inf ? -1 : ans; } int main() { init(); long long res = solve(); cout << res << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A222OI_BEHAVIORAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire B2 nand2_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_BEHAVIORAL_V |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math,O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; long long n, k, ans, pw[11], a[200005]; map<int, int> w[11]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout.precision(30); cerr.precision(7); ; cin >> n >> k; pw[0] = 1LL; for (int i = 1; i <= 10; i++) pw[i] = (pw[i - 1] * 10LL) % k; for (int i = 1; i <= n; i++) { cin >> a[i]; for (int j = 1; j <= 10; j++) w[j][(a[i] * pw[j]) % k]++; } for (int i = 1; i <= n; i++) { int l = (int)to_string(a[i]).size(); ans += w[l][(k - (a[i] % k)) % k]; ans -= !(((pw[l] * a[i]) % k + a[i]) % k); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { register T c = getchar(); x = 0; int t = 0; if (c == - ) t = 1, c = getchar(); for (; (c < 48 || c > 57); c = getchar()) ; for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (t) x = -x; } int main() { int n, Max = 0; read(n); string str; cin >> str; bool visited[250] = {0}; for (int i = 0; i < n; i++) { if (str[i] >= a && !visited[i]) { set<char> s; visited[i] = 1; s.insert(str[i]); for (int j = i + 1; j < n; j++) { if (str[j] <= Z ) break; visited[j] = 1; s.insert(str[j]); } if (Max < s.size()) Max = s.size(); } } cout << Max; } |
`timescale 1ns / 1ps
module ALU(A, B, ALUOp , ALUOut, Zero);
output reg [31:0] ALUOut;
output reg [0:0] Zero;
input [31:0] A, B;
input [4:0] ALUOp;
parameter ADD = 5'd0;
parameter SUB = 5'd1;
parameter ADDI = 5'd2;
parameter SUBI = 5'd3;
parameter MLT = 5'd4;
parameter MLTI = 5'd5;
parameter AND = 5'd6;
parameter OR = 5'd7;
parameter ANDI = 5'd8;
parameter ORI = 5'd9;
parameter SLR = 5'd10;
parameter SLL = 5'd11;
parameter LDR = 5'd12;
parameter STR = 5'd13;
parameter BNE = 5'd14;
parameter BEQ = 5'd15;
parameter J = 5'd16;
parameter CMP = 5'd17;
parameter NOP = 5'b11111;
parameter on = 1'd1;
parameter off = 1'd0;
initial begin
ALUOut=32'd0;
Zero=1'd0;
end
always @ (A or B or ALUOp) begin
case (ALUOp)
ADD:
begin
ALUOut = A+B;
Zero=off;
end
SUB:
begin
ALUOut = A-B;
Zero=off;
end
ADDI:
begin
ALUOut = A+B;
Zero=off;
end
SUBI:
begin
ALUOut = A-B;
Zero=off;
end
MLT:
begin
ALUOut = A*B;
Zero=off;
end
MLTI:
begin
ALUOut = A*B;
Zero=off;
end
AND:
begin
ALUOut = A&B;
Zero=off;
end
OR:
begin
ALUOut = A|B;
Zero=off;
end
ANDI:
begin
ALUOut = A&B;
Zero=off;
end
ORI:
begin
ALUOut = A|B;
Zero=off;
end
SLR:
begin
ALUOut = A>>B;
Zero=off;
end
SLL:
begin
ALUOut = A<<B;
Zero=off;
end
LDR:
begin
ALUOut = A+B;
Zero=off;
end
STR:
begin
ALUOut = A+B;
Zero=off;
end
BNE:
begin
ALUOut = 32'd0;
if(A==B) Zero=on;
else Zero=off;
end
BEQ:
begin
ALUOut = 32'd0;
if (A==B) Zero=on;
else Zero=off;
end
CMP:
begin
if (A>B) ALUOut=2'd1;
else if(A==B) ALUOut=2'd0;
else ALUOut=2'd2;
Zero=off;
end
default:
begin
ALUOut = 32'd0;
Zero=off;
end
endcase
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLYMETAL6S4S_PP_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s4s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool a[200087]; int main(void) { int n; cin >> n; for (int i = 0; i < n; i++) { int temp; cin >> temp; a[temp + 100000] = true; } int ans = 0; for (int i = 0; i <= 200000; i++) { if (i != 100000 && a[i] == true) { ans++; } } cout << ans; return 0; } |
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for bug reports:
// #943: VHDL enum values not available outside of switch statements
// #944: VHDL enum type declaration generates syntax errors
module bg943_test();
logic clk, rst, q;
e dut(clk, rst, q);
initial begin
clk = 0;
rst = 1;
#1;
clk = 1;
#1;
if(q !== 1'b0) begin
$display("FAILED 1");
$finish();
end
#1;
clk = 0;
rst = 0;
#1;
clk = 1;
#1;
if(q !== 1'b1) begin
$display("FAILED 2");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = int_fast64_t; constexpr int mod = 1e9 + 7; constexpr int inf = (1 << 30) - 1; constexpr ll infll = (1LL << 61) - 1; #pragma GCC target( avx2 ) #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) int main() { ios::sync_with_stdio(false), cin.tie(nullptr); int N; cin >> N; map<pair<int, int>, int> mp; vector<pair<int, int>> v(N); for (int i = 0; i < N; i++) { cin >> v[i].first >> v[i].second; if (mp[v[i]] != 0) { cout << mp[v[i]] << << i + 1 << n ; return 0; } mp[v[i]] = i + 1; v[i].second *= -1; } sort(v.begin(), v.end()); set<int> st; int ans1 = -1, ans2 = -1; for (int i = 0; i < N; i++) { v[i].second *= -1; st.erase(st.begin(), st.lower_bound(v[i].first)); if (!st.empty() && st.lower_bound(v[i].second) != st.end()) { ans1 = i; } st.insert(v[i].second); } if (ans1 == -1) { cout << -1 << << -1 << n ; return 0; } for (int i = 0; i < N; i++) { if (i == ans1) continue; if (v[i].first <= v[ans1].first && v[ans1].second <= v[i].second) ans2 = i; } cout << mp[v[ans1]] << << mp[v[ans2]] << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000; const int MAX = 100000 + 100; const int inf = 999999999; const int p1 = 104393321, p2 = 104393329; int n, m; int par[MAX], sizeofcom[MAX], size[MAX], a[MAX], b[MAX], d[MAX]; bool lucky(int x) { while (x > 0) { if (x % 10 == 7 || x % 10 == 4) x /= 10; else return false; } return true; } int find(int k) { if (par[k] == k) return k; else par[k] = find(par[k]); return par[k]; } int main() { ios::sync_with_stdio(0); cin >> n >> m; for (int i = (0); i < int(n); ++i) par[i] = i; int x, y; for (int i = (0); i < int(m); ++i) { cin >> x >> y; x--; y--; par[find(x)] = find(y); } for (int i = (0); i < int(n); ++i) sizeofcom[find(i)]++; for (int i = (0); i < int(n + 1); ++i) size[sizeofcom[i]]++; for (int i = (1); i < int(n + 1); ++i) if (lucky(i) && size[i]) { cout << 0 << endl; return 0; } int sz = 0; for (int i = (1); i < int(n + 1); ++i) { int tmp = 1; while (tmp <= size[i]) { a[sz] = tmp * i; b[sz++] = tmp; size[i] -= tmp; tmp *= 2; } if (size[i]) { a[sz] = size[i] * i; b[sz++] = size[i]; } } int ans = inf; for (int i = (1); i < int(n + 1); ++i) d[i] = inf; d[a[0]] = 1; for (int j = (1); j < int(sz); ++j) { for (int i = (n); i > int(0); --i) { if (a[j] <= i) d[i] = min(d[i], d[i - a[j]] + b[j]); if (lucky(i) && d[i] != inf) ans = min(ans, d[i]); } } if (ans == inf) cout << -1 << endl; else cout << ans - 1 << endl; return 0; } |
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