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#include <bits/stdc++.h> using namespace std; const int maxn = 1001010; int a[maxn]; void solve() { int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } int cnt = 0; for (int i = 0; i < n and a[i] >= i; ++i, ++cnt) { } for (int i = n - 1; i >= 0 and a[i] >= n - 1 - i; --i, ++cnt) { } cout << (cnt > n ? Yes : No ) << endl; } int main() { int t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long fpow(long long b, long long p) { if (b == 0) return 0; long long ans = 1; while (p) { if (p & 1) ans = ans * b % (998244353); b = b * b % (998244353); p /= 2; } return ans; } struct BIT { long long n; long long a[150050]; void init(long long _n) { n = _n; memset(a, 0, sizeof(a)); } void add(long long i, long long x) { while (i <= n) { a[i] += x; if (a[i] >= (998244353)) a[i] -= (998244353); i += (i & (-i)); } } long long ask(long long l, long long r) { long long ans = 0; while (r > 0) { ans += a[r]; r -= (r & (-r)); } l--; while (l > 0) { ans -= a[l]; l -= (l & (-l)); } return ans % (998244353); } } bit; long long N, N1; long long addall = 0; vector<long long> adj[150010]; long long sz[150010]; long long p[150010]; long long nxt[150010]; long long id[150010]; long long head[150010]; long long add[150010]; long long info(long long n, long long par) { sz[n] = 1; p[n] = par; pair<long long, long long> mx(0, 0); for (auto &i : adj[n]) if (i != par) { mx = max(mx, make_pair(info(i, n), i)); sz[n] += sz[i]; } nxt[n] = mx.second; return sz[n]; } void hld(long long n, long long h) { static long long nowid = 1; id[n] = nowid; nowid++; head[n] = h; if (nxt[n] != 0) hld(nxt[n], h); for (auto &i : adj[n]) if (i != p[n] && i != nxt[n]) { hld(i, i); } } long long ask(long long n) { long long ans = addall + add[n]; while (n != 0) { ans += bit.ask(id[head[n]], id[n]); n = head[n]; ans = (ans + add[p[n]] * (N - sz[n]) % (998244353) * N1) % (998244353); n = p[n]; } return ans; } signed main() { { ; ; ; ios::sync_with_stdio(false); cin.tie(0); ; ; ; } cin >> N; long long q; cin >> q; N1 = fpow(N, (998244353) - 2); for (long long i = 1; i <= N - 1; i++) { long long a, b; cin >> a >> b; adj[a].emplace_back(b); adj[b].emplace_back(a); } bit.init(N); info(1, 0); hld(1, 1); while (q--) { long long op; cin >> op; if (op == 1) { long long v, x; cin >> v >> x; addall = (addall + x * sz[v] % (998244353) * N1) % (998244353); add[v] = (add[v] + x) % (998244353); bit.add(id[v], -x * sz[v] % (998244353) * N1 % (998244353)); if (nxt[v] != 0) { bit.add(id[nxt[v]], x * (N - sz[nxt[v]]) % (998244353) * N1 % (998244353)); } } else { long long v; cin >> v; long long ans = addall + add[v]; while (v != 0) { ans += bit.ask(id[head[v]], id[v]); v = head[v]; ans = (ans + add[p[v]] * (N - sz[v]) % (998244353) * N1) % (998244353); v = p[v]; } cout << (ans + (998244353)) % (998244353) << n ; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); int test; for (cin >> test; test--;) { int m, n; cin >> m >> n; vector<vector<int>> s(m + 5, vector<int>(n + 5)); for (int i = 1; i <= m; ++i) { for (int j = 1; j <= n; ++j) { char x; cin >> x; s[i][j] = x - 0 ; } } vector<int> ans; auto f = [&](int i, int j) { s[i][j] ^= 1; ans.push_back(i); ans.push_back(j); }; auto fp = [&](pair<int, int> a) { s[a.first][a.second] ^= 1; ans.push_back(a.first); ans.push_back(a.second); }; if (m > 2) { for (int i = 1; i <= m - 2; ++i) { for (int j = 1; j < n; ++j) { if (s[i][j] == 0) continue; if (s[i][j + 1] == 1) { if (s[i + 1][j] == 1) { f(i, j); f(i + 1, j); f(i, j + 1); } else { f(i, j); f(i, j + 1); f(i + 1, j + 1); } } else { f(i, j); f(i + 1, j + 1); f(i + 1, j); } } if (s[i][n] == 1) { f(i, n); f(i + 1, n); f(i + 1, n - 1); } } for (int j = 1, i = m - 1; j < n; ++j) { if (s[i + 1][j] == 0 && s[i][j] == 0 && (!(i == m - 1 && j == n - 1))) continue; int sum = s[i][j] + s[i][j + 1] + s[i + 1][j] + s[i + 1][j + 1]; if (sum == 4) { f(i + 1, j); f(i + 1, j + 1); f(i, j + 1); f(i, j); f(i + 1, j); f(i, j + 1); f(i, j); f(i, j + 1); f(i + 1, j + 1); f(i, j); f(i + 1, j); f(i + 1, j + 1); } vector<pair<int, int>> e = { {i, j}, {i + 1, j}, {i, j + 1}, {i + 1, j + 1}}; sort(e.begin(), e.end(), [&](pair<int, int> x, pair<int, int> y) { return s[x.first][x.second] < s[y.first][y.second]; }); if (sum == 2) { if (sum == 2) { fp(e[0]); fp(e[1]); fp(e[2]); fp(e[0]); fp(e[1]); fp(e[3]); } continue; } if (sum == 3) { if (s[i][j] == 1) f(i, j); if (s[i + 1][j] == 1) f(i + 1, j); if (s[i][j + 1] == 1) f(i, j + 1); if (s[i + 1][j + 1] == 1) f(i + 1, j + 1); continue; } if (sum == 1) { fp(e[1]); fp(e[2]); fp(e[3]); fp(e[0]); fp(e[1]); fp(e[3]); fp(e[0]); fp(e[2]); fp(e[3]); } } } else { for (int j = 1; j <= n - 2; ++j) { for (int i = 1; i < m; ++i) { if (s[i][j] == 0) continue; if (s[i + 1][j] == 1) { if (s[i][j + 1] == 1) { f(i, j); f(i + 1, j); f(i, j + 1); } else { f(i, j); f(i + 1, j); f(i + 1, j + 1); } } else { f(i, j); f(i, j + 1); f(i + 1, j + 1); } } if (s[m][j] == 1) { f(m, j); f(m - 1, j + 1); f(m, j + 1); } } for (int i = 1, j = n - 1; i < m; ++i) { if (s[i][j] == 0 && s[i][j + 1] == 0 && (!(i == m - 1 && j == n - 1))) continue; int sum = s[i][j] + s[i][j + 1] + s[i + 1][j] + s[i + 1][j + 1]; if (sum == 4) { f(i + 1, j); f(i + 1, j + 1); f(i, j + 1); f(i, j); f(i + 1, j); f(i, j + 1); f(i, j); f(i, j + 1); f(i + 1, j + 1); f(i, j); f(i + 1, j); f(i + 1, j + 1); } vector<pair<int, int>> e = { {i, j}, {i + 1, j}, {i, j + 1}, {i + 1, j + 1}}; sort(e.begin(), e.end(), [&](pair<int, int> x, pair<int, int> y) { return s[x.first][x.second] < s[y.first][y.second]; }); if (sum == 2) { if (sum == 2) { fp(e[0]); fp(e[1]); fp(e[2]); fp(e[0]); fp(e[1]); fp(e[3]); } continue; } if (sum == 3) { if (s[i][j] == 1) f(i, j); if (s[i + 1][j] == 1) f(i + 1, j); if (s[i][j + 1] == 1) f(i, j + 1); if (s[i + 1][j + 1] == 1) f(i + 1, j + 1); continue; } if (sum == 1) { fp(e[1]); fp(e[2]); fp(e[3]); fp(e[0]); fp(e[1]); fp(e[3]); fp(e[0]); fp(e[2]); fp(e[3]); } } } cout << ans.size() / 6 << n ; for (int i = 0; i < ans.size(); i += 6) { cout << ans[i] << << ans[i + 1] << << ans[i + 2] << << ans[i + 3] << << ans[i + 4] << << ans[i + 5] << n ; } } } |
// nios_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int fact[200005]; long long int n; struct point { long long int x, y; }; bool cmp(struct point i1, struct point i2) { if (i1.x != i2.x) return i1.x < i2.x; else { return (i1.y < i2.y); } } long long int fact_(long long int n) { long long int ans = 1; fact[0] = fact[1] = 1; for (int i = 2; i <= n; i++) { ans = (ans * i) % 1000000007; fact[i] = ans % 1000000007; } return ans; } long long int mod_inv(long long int a, long long int b) { long long int ans = 1; while (b) { if (b % 2 == 1) ans = (ans * a) % 1000000007; a = (a * a) % 1000000007; b = b >> 1; } return ans; } long long int ncr(long long int n, long long int r) { if (n < r) return 0; if (r == 0) return n; if (r == 1) return n; if (n == r) return 1; return ((((fact[n] % 1000000007) * mod_inv(fact[r] % 1000000007, 1000000007 - 2)) % 1000000007) * mod_inv(fact[n - r] % 1000000007, 1000000007 - 2)) % 1000000007; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); vector<struct point> ar1(4), ar2(4); for (int i = 0; i < 4; i++) { long long int a, b; cin >> a >> b; ar1[i].x = a; ar1[i].y = b; } for (int i = 0; i < 4; i++) { long long int a, b; cin >> a >> b; ar2[i].x = a; ar2[i].y = b; } sort(ar1.begin(), ar1.end(), cmp); sort(ar2.begin(), ar2.end(), cmp); bool f = 0; for (int i = 0; i < 4; i++) { if (ar2[i].x >= ar1[0].x && ar2[i].y >= ar1[0].y && ar2[i].x <= ar1[3].x && ar2[i].y <= ar1[3].y) f = 1; } for (int i = 0; i < 4; i++) { if ((ar1[i].x + ar1[i].y) >= (ar2[1].x + ar2[1].y) && (ar1[i].y - ar1[i].x) >= (ar2[1].y - ar2[1].x) && (ar1[i].x + ar1[i].y) <= (ar2[2].x + ar2[2].y) && (ar1[i].y - ar1[i].x) <= (ar2[2].y - ar2[2].x)) f = 1; } point c1, c2; c1.x = (ar1[0].x + ar1[1].x) / 2; c1.y = (ar1[0].y + ar1[3].y) / 2; c2.x = (ar2[0].x + ar2[1].x) / 2; c2.y = (ar2[0].y + ar2[3].y) / 2; if (c2.x >= ar1[0].x && c2.y >= ar1[0].y && c2.x <= ar1[3].x && c2.y <= ar1[3].y) f = 1; if ((c1.x + c1.y) >= (ar2[1].x + ar2[1].y) && (c1.y - c1.x) >= (ar2[1].y - ar2[1].x) && (c1.x + c1.y) <= (ar2[2].x + ar2[2].y) && (c1.y - c1.x) <= (ar2[2].y - ar2[2].x)) f = 1; if (!f) cout << NO << endl; else { cout << YES << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k1, k2; cin >> n >> m >> k1 >> k2; if (n > m) { cout << First << endl; } else { cout << Second << endl; } } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue = @ event_identifier constant\n");
#10 ;
if(value1 != 4'h5)
$display("FAILED - always reg_lvalue = @ event_identifier constant\n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 = repeat ( 5 ) @ event_ident 4'h5 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, q, t, x, y, b, c, d; string s1, s2; long long a[3]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> s1 >> s2; int l1 = s1.length(); int l2 = s2.length(); int j = 0, k = 0; int ok = 1; int lastok = -1; while (j < l1 && k < l2) { if (s1[j] == s2[k]) { j++; k++; lastok++; } else if (k && s2[k] == s2[k - 1]) { int tmp = k; while (tmp < l2 && s2[tmp] == s2[k]) tmp++; if (tmp == l2) { ok = 0; break; } lastok = tmp - 1; k = tmp; } else if (lastok == k - 1) { ok = 0; break; } } if (j < l1) ok = 0; while (k < l2) { if (k && s2[k] != s2[k - 1]) { ok = 0; break; } k++; } cout << (ok ? YES : NO ) << endl; } return 0; } |
#include <bits/stdc++.h> int main() { std::string input( ), answer( ), output( ); getline(std::cin, input); getline(std::cin, answer); int count[10] = {0}; char minNonZero( A ); for (int k = 0; k < input.size(); k++) { ++count[input[k] - 0 ]; if (input[k] > 0 && input[k] < minNonZero) { minNonZero = input[k]; } } if (minNonZero == A ) { output = 0 ; } else { --count[minNonZero - 0 ]; output += minNonZero; for (int digit = 0; digit < 10; digit++) { while (count[digit]--) { output += ( 0 + digit); } } } if (answer == output) { puts( OK ); } else { puts( WRONG_ANSWER ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char a[250]; int k; cin >> a; cin >> k; int temp = k; int curr = 0; a[strlen(a)] = 0 ; if (strlen(a) > 1) { while (temp) { int max_v = a[curr] - 48, max_p = curr; for (int j = curr + 1; j <= curr + temp && j < strlen(a); j++) { if (a[j] - 48 > max_v) { max_v = a[j] - 48; max_p = j; } } if (max_p != curr) { for (int j = max_p; j > curr; j--) { if (temp) { swap(a[j], a[j - 1]); temp--; } else break; } } curr++; if (curr >= strlen(a)) { break; } a[strlen(a)] = 0 ; } } cout << a; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 1e3 + 7; int n, Q, m; int p[N]; int a[N], b[N]; struct Query { int t, x; } q[N]; int nd, fa[N], del[N]; int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } int rt[N]; vector<int> g[N]; int vis[N]; int st[N], ed[N], dc, rev[N]; void dfs(int x) { if (vis[x]) return; st[x] = ++dc; vis[x] = 1; rev[st[x]] = x; for (auto v : g[x]) dfs(v); ed[x] = dc; } int cnt; struct T { int ls, rs, l, r; pair<int, int> mx; } t[N * 2 + 1]; void update(int x) { t[x].mx = max(t[t[x].ls].mx, t[t[x].rs].mx); } int build(int l, int r) { int x = ++cnt; t[x].l = l, t[x].r = r; if (l == r) { t[x].mx = make_pair(p[rev[l]], l); return x; } int mid = (l + r) >> 1; t[x].ls = build(l, mid); t[x].rs = build(mid + 1, r); update(x); return x; } void change(int x, int p, int v) { if (t[x].l == t[x].r) { t[x].mx.first = v; return; } int mid = (t[x].l + t[x].r) >> 1; if (p <= mid) change(t[x].ls, p, v); else change(t[x].rs, p, v); update(x); } pair<int, int> query(int x, int l, int r) { if (l <= t[x].l && t[x].r <= r) return t[x].mx; int mid = (t[x].l + t[x].r) >> 1; pair<int, int> mx = make_pair(0, 0); if (l <= mid) mx = max(mx, query(t[x].ls, l, r)); if (r > mid) mx = max(mx, query(t[x].rs, l, r)); return mx; } int main() { scanf( %d%d%d , &n, &m, &Q); for (int i = 1; i <= n; i++) scanf( %d , &p[i]), fa[i] = i; for (int i = 1; i <= m; i++) scanf( %d%d , &a[i], &b[i]); for (int i = 1; i <= Q; i++) { scanf( %d%d , &q[i].t, &q[i].x); if (q[i].t == 2) del[q[i].x] = 1; } nd = n; for (int i = 1; i <= m; i++) if (!del[i]) { int fx = find(a[i]), fy = find(b[i]); if (fx == fy) continue; ++nd; g[nd].push_back(fx); g[nd].push_back(fy); fa[fx] = fa[fy] = fa[nd] = nd; } for (int i = Q; i >= 1; i--) { if (q[i].t == 2) { int fx = find(a[q[i].x]), fy = find(b[q[i].x]); if (fx == fy) continue; ++nd; g[nd].push_back(fx); g[nd].push_back(fy); fa[fx] = fa[fy] = fa[nd] = nd; } else rt[i] = find(q[i].x); } for (int i = nd; i >= 1; i--) dfs(i); build(1, nd); for (int i = 1; i <= Q; i++) { if (q[i].t == 1) { pair<int, int> ans = query(1, st[rt[i]], ed[rt[i]]); printf( %d n , ans.first); if (ans.second) change(1, ans.second, 0); } } } |
#include <bits/stdc++.h> using namespace std; const int N = int(500 * 1000 + 7); int n, k; vector<pair<int, int> > adj[N]; long long dp[N][2]; void dfs(int v, int p = -1) { vector<long long> x; long long curr = 0; for (auto it : adj[v]) { int to = it.first; int w = it.second; if (to == p) continue; dfs(to, v); curr += dp[to][0]; x.push_back(dp[to][1] + w - dp[to][0]); } sort(x.begin(), x.end(), greater<long long>()); for (int i = 0; i < min((int)x.size(), k); i++) { if (x[i] > 0) curr += x[i]; } dp[v][0] = dp[v][1] = curr; if (k <= (int)x.size() && x[k - 1] > 0) dp[v][1] -= x[k - 1]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int q; cin >> q; while (q--) { cin >> n >> k; for (int i = 0; i < n; i++) adj[i].clear(); for (int i = 0; i < n - 1; i++) { int u, v, w; cin >> u >> v >> w; u--; v--; adj[u].push_back({v, w}); adj[v].push_back({u, w}); } dfs(0, -1); cout << dp[0][0] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; void in(int &x) { register int c = getchar(); x = 0; for (; (c < 48 || c > 57); c = getchar()) ; for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } } const int N = 1 << 24; long long dp[N]; string s[10004]; int main() { int n, i, j, mask, full = N - 1; in(n); for (i = 0; i < n; i++) { cin >> s[i]; mask = 0; for (j = 0; j < 3; j++) mask |= 1 << (s[i][j] - a ); mask ^= full; dp[mask]++; } for (i = 0; i < 24; i++) { for (mask = N - 1; mask >= 0; mask--) if (mask & (1 << i)) { dp[mask ^ (1 << i)] += dp[mask]; } } long long ret = 0; for (i = 0; i < N; i++) ret ^= 1ll * (n - dp[i]) * (n - dp[i]); printf( %lld n , ret); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100007; struct LinkCutTree { struct Node { int L, R, P, lazyFlip; int PP; }; Node LCT[MAXN]; void normalize(int u) { assert(u != -1); if (LCT[u].L != -1) LCT[LCT[u].L].P = u; if (LCT[u].R != -1) LCT[LCT[u].R].P = u; } void setLeftChild(int p, int v) { LCT[p].L = v; normalize(p); } void setRightChild(int p, int v) { LCT[p].R = v; normalize(p); } void pushLazy(int u) { if (!LCT[u].lazyFlip) return; swap(LCT[u].L, LCT[u].R); LCT[u].lazyFlip = 0; if (LCT[u].L != -1) LCT[LCT[u].L].lazyFlip ^= 1; if (LCT[u].R != -1) LCT[LCT[u].R].lazyFlip ^= 1; } void make_tree(int v) { LCT[v].L = LCT[v].R = LCT[v].P = LCT[v].PP = -1; LCT[v].lazyFlip = 0; } void rotate(int v) { if (LCT[v].P == -1) return; int p = LCT[v].P; int g = LCT[p].P; if (LCT[p].L == v) { setLeftChild(p, LCT[v].R); setRightChild(v, p); } else { setRightChild(p, LCT[v].L); setLeftChild(v, p); } LCT[v].P = g; if (g != -1) { if (LCT[g].L == p) { setLeftChild(g, v); } else { setRightChild(g, v); } } LCT[v].PP = LCT[p].PP; LCT[p].PP = -1; } void pushEmAll(int v) { if (LCT[v].P != -1) pushEmAll(LCT[v].P); pushLazy(v); } void splay(int v) { pushLazy(v); while (LCT[v].P != -1) { int p = LCT[v].P; int g = LCT[p].P; if (g != -1) pushLazy(g); pushLazy(p); pushLazy(v); if (g == -1) { rotate(v); } else if ((LCT[p].L == v) == (LCT[g].L == p)) { rotate(p); rotate(v); } else { rotate(v); rotate(v); } } } vector<int> access(int v, bool doIt = false) { splay(v); int _v = v, _r = -1; if (LCT[v].R != -1) { if (doIt) { _r = LCT[v].R; } LCT[LCT[v].R].PP = v; LCT[LCT[v].R].P = -1; setRightChild(v, -1); } vector<int> ret; while (LCT[v].PP != -1) { int w = LCT[v].PP; splay(w); ret.push_back(w); if (LCT[w].R != -1) { LCT[LCT[w].R].PP = w; LCT[LCT[w].R].P = -1; } LCT[v].PP = -1; setRightChild(w, v); splay(v); } if (_r != -1) { splay(_v); assert(LCT[_v].R == -1); setRightChild(_v, _r); LCT[_r].PP = -1; } return ret; } int find_root(int v) { access(v); int ret = v; while (LCT[ret].L != -1) { ret = LCT[ret].L; pushLazy(ret); } access(ret); return ret; } void link(int v, int w) { access(w); setLeftChild(v, w); LCT[w].PP = -1; } void cut(int v) { access(v); if (LCT[v].L != -1) { LCT[LCT[v].L].P = -1; LCT[LCT[v].L].PP = -1; setLeftChild(v, -1); } } void make_root(int v) { access(v); int l = LCT[v].L; if (l != -1) { setLeftChild(v, -1); LCT[l].P = -1; LCT[l].PP = v; LCT[l].lazyFlip ^= 1; } } bool isConnected(int p, int q) { return find_root(p) == find_root(q); } int LCA(int p, int q) { access(p); return access(q).back(); } }; vector<pair<int, int> > edg[MAXN]; long long depth[MAXN]; LinkCutTree lct; int bap[MAXN]; vector<int> accessOrder; int st[MAXN], ed[MAXN]; int tym; void dfs(int u, int p) { st[u] = ++tym; bap[u] = p; bool called = false; for (pair<int, int> pr : edg[u]) { if (p == pr.first) continue; called = true; depth[pr.first] = depth[u] + pr.second; lct.link(pr.first, u); dfs(pr.first, u); } if (!called) accessOrder.push_back(u); ed[u] = tym; } map<long long, long long> vacancy; bool makePlace(long long l, long long r) { auto it = vacancy.lower_bound(l); if (l <= prev(it)->second) { it = prev(it); long long _l = it->first; long long _r = it->second; vacancy.erase(it); if (_l < l) vacancy[_l] = l - 1; if (l < _r) vacancy[l + 1] = _r; return true; } else { assert(it != vacancy.end()); long long _l = it->first; long long _r = it->second; if (r < _l) return false; vacancy.erase(it); if (_l < _r) vacancy[_l + 1] = _r; return true; } assert(false); } set<int> tr[4 * MAXN]; void update(int u, int l, int r, int i, int t) { tr[u].insert(t); if (l == r) return; int mid = (l + r) / 2; if (i <= mid) update(u * 2, l, mid, i, t); else update(u * 2 + 1, mid + 1, r, i, t); } int ask(int u, int l, int r, int x, int y, int t) { if (y < l || r < x) return 0; if (x <= l && r <= y) { auto it = tr[u].lower_bound(t); if (it == tr[u].begin()) return 0; return *prev(it); } int mid = (l + r) / 2; return max(ask(u * 2, l, mid, x, y, t), ask(u * 2 + 1, mid + 1, r, x, y, t)); } void printEdges(int s) { while (s != 1) { cout << s << @ << depth[s] << <- ; s = bap[s]; } cout << 1; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 1; i < n; i++) { int u, v, w; cin >> u >> v >> w; edg[u].emplace_back(v, w); edg[v].emplace_back(u, w); } for (int i = 1; i <= n; i++) lct.make_tree(i); dfs(1, 0); for (int leaf : accessOrder) { lct.access(leaf); } map<long long, vector<long long> > mp; for (int _m = 0; _m < m; _m++) { int s, t; cin >> s >> t; if (s == 1) continue; vector<int> need = lct.access(s, true); for (int p : need) { int l = ask(1, 1, n, st[p], ed[p], t); if (l > 0) mp[t + depth[p]].push_back(l + 1 + depth[p]); else mp[t + depth[p]].push_back(1); } update(1, 1, n, st[bap[s]], t); } vacancy[0] = 1e15; int ans = 0; for (pair<const long long, vector<long long> >& pr : mp) { sort(pr.second.begin(), pr.second.end()); bool okay = true; for (long long x : pr.second) { if (!makePlace(x, pr.first)) { okay = false; break; } } if (!okay) { cout << pr.first << << ans << endl; return 0; } ans += pr.second.size(); } cout << -1 << << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int const N = 8; char a[N][N + 1]; int d[N * N][N][N]; inline int in(int x) { return x >= 0 && x < N; } int main() { for (int i = 0; i < N; ++i) scanf( %s , a[i]); for (int i = 0; i < N; ++i) for (int j = 0; j < N; ++j) d[0][i][j] = (a[i][j] == M ); for (int i = 0; i + 1 < N * N; ++i) { for (int j = 0; j < N; ++j) for (int k = 0; k < N; ++k) { if (a[j][k] == A && d[i][j][k]) { cout << WIN n ; return 0; } if (a[j][k] == S && in(j + i)) d[i][j + i][k] = 0; } for (int j = 0; j < N; ++j) for (int k = 0; k < N; ++k) if (d[i][j][k]) for (int dx = -1; dx <= 1; ++dx) for (int dy = -1; dy <= 1; ++dy) if (in(j + dx) && in(k + dy) && (!in(j + dx - i) || a[j + dx - i][k + dy] != S )) d[i + 1][j + dx][k + dy] = 1; } printf( LOSE n ); return 0; } |
#include <iostream> #include <bits/stdc++.h> #include<algorithm> #define fastio ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL) #define ll long long #define MOD 1000000007 #define f first #define s second #define pb push_back #define nl n #define mem(arr, value) memset(arr, value, sizeof(arr)) #define vll vector<ll> #define vb vector<bool> #define vpll vector<pair<ll, ll>> #define vvll vector<vector<ll>> using namespace std; // DEBUG void __print(int x) { cerr << x; } void __print(ll x) { cerr << x; } void __print(double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char* x) { cerr << << x << ; } void __print(const string& x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template<typename T, typename V> void __print(const pair<T, V>& x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template<typename T> void __print(const T& x) { int _ = 0; cerr << { ; for (auto& i : x) cerr << (_++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } #ifndef ONLINE_JUDGE #define dbg(x...) cerr << [ << #x << ] = [ ; _print(x) #else #define dbg(x...) #endif bool flag = false; bool comp1(pair<pair<ll, ll>, pair<ll,ll> > a, pair<pair<ll, ll>, pair<ll, ll>> b) { return a.s.s < b.s.s; } bool comp(pair<ll,ll> a, pair<ll, ll> b) { return a.s < b.s; } struct myComp { constexpr bool operator()( pair< pair<ll,ll>, pair<ll,ll> > const& a, pair< pair<ll,ll>, pair<ll,ll> > const& b) const noexcept { return a.s.s < b.s.s; } }; ll digitSum(ll n){ll sum=0; while(n>0){sum += n%10;n=n/10;}return sum;} void dfs(vvll &adj, vb &visited, ll v, ll e) { // visited[v] = true; for (ll i=0; i<adj[v].size(); i++) { ll n = adj[v][i]; if (n==e) { flag = true; return; } dfs(adj, visited, n, e); } // return false; } bool isSubsetSum(int set[], int n, int sum) { bool subset[n + 1][sum + 1]; for (int i = 0; i <= n; i++) subset[i][0] = true; for (int i = 1; i <= sum; i++) subset[0][i] = false; for (int i = 1; i <= n; i++) { for (int j = 1; j <= sum; j++) { if (j < set[i - 1]) subset[i][j] = subset[i - 1][j]; if (j >= set[i - 1]) subset[i][j] = subset[i - 1][j] || subset[i - 1][j - set[i - 1]]; } } return subset[n][sum]; } void solve() { ll n; cin>>n; ll b[n+2]; ll sum = 0; for (ll i=0; i<n+2; i++) { cin>>b[i]; sum+=b[i]; } sort(b, b+n+2); ll aa = b[n+1]; ll bb = b[n]; ll x=-1; ll temp1 = sum - b[n+1]; for (ll i=0; i<n+1; i++) { temp1 = temp1 - b[i]; if (temp1 == aa) { x = i; break; } temp1 += b[i]; } if (x == -1) { ll temp2 = sum - b[n] - b[n+1]; if (temp2 == b[n]) { x = n; } } if (x==-1) cout<<-1<<endl; else { for (ll i=0; i<n+1; i++) { if (i==x) continue; else cout<<b[i]<< ; } cout<<endl; } } int main() { fastio; ll t=1; cin>>t; while (t-->0) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)3e5 + 7; int n, k; int x[N], y[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> x[i]; } for (int i = 1; i <= n; i++) { cin >> y[i]; } long long f, s; f = s = 0; for (int i = 1; i <= n; i++) { f = max(0LL, x[i] + f - y[i] * 1LL * k); s = max(0LL, y[i] + s - x[i] * 1LL * k); if (f > k || s > k) { puts( NO ); return 0; } } puts( YES ); } |
#include <bits/stdc++.h> const static long long INF = 0x3f3f3f3f; static inline void setio(void); long long dp[5002][5002]; int main(void) { setio(); memset(dp, 0, sizeof(dp)); long long n, m; std::cin >> n >> m; std::string s; for (long long i = 0; i < n; ++i) { std::cin >> s; for (long long j = 0, k; j < m;) { if (s[j] != 1 ) { ++j; continue; } for (k = j + 1; k < m && s[k] == 1 ; ++k) ; ++dp[j][k - 1]; j = k + 1; } } for (long long j = 0; j < m; ++j) { for (long long k = m - 2; k >= j; --k) dp[j][k] += dp[j][k + 1]; } for (long long j = 1; j < m; ++j) { for (long long k = 0; k < m; ++k) dp[j][k] += dp[j - 1][k]; } long long best = 0; for (long long i = 0; i < m; ++i) for (long long j = 0; j < m; ++j) best = std::max(best, (j - i + 1) * dp[i][j]); std::cout << best << n ; return 0; } static inline void setio(void) { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.precision(10); std::cout << std::fixed; } |
//#############################################################################
//# Function: Single Port Memory #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_sp # (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter MCW = 8, // repair/config width
parameter AW = $clog2(DEPTH) // address bus width
)
(// memory interface (single port)
input clk, // clock
input en, // memory access
input we, // write enable global signal
input [DW-1:0] wem, // write enable vector
input [AW-1:0] addr, // address
input [DW-1:0] din, // data input
output [DW-1:0] dout, // data output
// Power/repair (ASICs)
input vss, // common ground
input vdd, // periphery power rail
input vddm, // sram array power rail
input shutdown, // shutdown signal from always on domain
input [MCW-1:0] memconfig, // generic memory config
input [MCW-1:0] memrepair, // repair vector
// BIST interface (ASICs)
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din // data input
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0
asic_sram_sp #(.DW(DW),
.DEPTH(DEPTH),
.MCW(MCW))
sram_sp (// Outputs
.dout (dout[DW-1:0]),
// Inputs
.clk (clk),
.en (en),
.we (we),
.wem (wem[DW-1:0]),
.addr (addr[AW-1:0]),
.din (din[DW-1:0]),
.vdd (vdd),
.vddm (vddm),
.vss (vss),
.shutdown (shutdown),
.memconfig (memconfig[MCW-1:0]),
.memrepair (memrepair[MCW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[DW-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[DW-1:0]));
end
else
begin : g0
oh_memory_ram #(.DW(DW),
.DEPTH(DEPTH))
sram_sp (//read port
.rd_dout (dout[DW-1:0]),
.rd_clk (clk),
.rd_addr (addr[AW-1:0]),
.rd_en (en & ~we),
//write port
.wr_clk (clk),
.wr_en (en & we),
.wr_addr (addr[AW-1:0]),
.wr_wem (wem[DW-1:0]),
.wr_din (din[DW-1:0]));
end
endgenerate
endmodule // oh_memory_sp
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n / 2 * 3 << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_1_V
`define SKY130_FD_SC_LS__NAND4_1_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_1_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int c1, c2; int d1, d2; int diff1, diff2; for (int i = 0; i < 3; i++) { if ((n - i) % 3 == 0) { c2 = (n - i) / 3; c1 = n - 2 * c2; diff1 = i; break; } } for (int i = 0; i < 3; i++) { if ((n - i) % 3 == 0) { d2 = (n + i) / 3; d1 = n - 2 * d2; diff2 = i; break; } } if (diff1 < diff2) cout << c1 << << c2 << n ; else cout << d1 << << d2 << n ; } } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecb_e.v,v 1.1 2004/04/06 10:50:51 wig Exp $
// $Date: 2004/04/06 10:50:51 $
// $Log: inst_ecb_e.v,v $
// Revision 1.1 2004/04/06 10:50:51 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ecb_e
//
// No `defines in this module
module inst_ecb_e
//
// Generated module inst_ecb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int n, t, r, x, A[2000], B[2000], CODE = 0, ans = 0, z, j; void Init() { cin >> n >> t >> r; if (r > t) CODE = 1; else for (int i = 0; i < 1000; i++) { A[i] = 0; B[i] = 0; } } int main() { Init(); if (CODE == 1) { for (int i = 0; i < n; i++) cin >> x; cout << -1; } else { for (int i = 0; i < n; i++) { cin >> x; x += 500; if (B[x] < r) { j = x - 1; z = r - B[x]; while (z != 0) { if (A[j] == 0) { A[j] = 1; for (int q = j + 1; q < j + t + 1; q++) B[q]++; ans++; z--; } j--; } } } cout << ans; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int T = 1; cin >> T; while (T--) { int64_t w, h; cin >> w >> h; vector<int64_t> hor1, hor2, ver1, ver2; int64_t k; int64_t q; cin >> k; for (int i = 0; i < k; ++i) cin >> q, hor1.push_back(q); cin >> k; for (int i = 0; i < k; ++i) cin >> q, hor2.push_back(q); cin >> k; for (int i = 0; i < k; ++i) cin >> q, ver1.push_back(q); cin >> k; for (int i = 0; i < k; ++i) cin >> q, ver2.push_back(q); cout << max({(hor1.back() - hor1[0]) * h, (hor2.back() - hor2[0]) * h, (ver1.back() - ver1[0]) * w, (ver2.back() - ver2[0]) * w}) << n ; } } |
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom (addr_rd, addr_rw, clock, data, wren, q, q_rw);
input clock;
input [13:0] addr_rw;
input [7:0] data;
input wren;
input [13:0] addr_rd;
output [7:0] q;
output [7:0] q_rw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q = sub_wire0[7:0];
wire [7:0] q_rw = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (1'b0),
.wren_b (wren),
.address_a (addr_rd),
.address_b (addr_rw),
.data_a (16'h0),
.data_b (data),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "rom.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_2_V
`define SKY130_FD_SC_HDLL__NAND4B_2_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4b_2 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4b_2 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 23:15:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: Switch_Synchronizer_Bank
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Switch Synchronizer Bank
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Switch_Synchronizer_Bank
#(
parameter SWITCH_SYNC_CHANNELS = 1,
parameter CLK_RATE_HZ = 50000000, // Hz
parameter DEBOUNCE_TIME = 10000, // ns
parameter SIG_OUT_INIT = 1'b0
)
(
// Input Signals (asynchronous)
input [SWITCH_SYNC_CHANNELS-1:0] SIG_IN,
// Output Signals (synchronized to CLK domain)
output [SWITCH_SYNC_CHANNELS-1:0] SIG_OUT,
// System Signals
input CLK
);
//
// Switch Input Debounce Synchronizers
//
genvar i;
generate
begin
for (i = 0; i < SWITCH_SYNC_CHANNELS; i=i+1)
begin : sw_sync_gen
Switch_Debounce_Synchronizer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.DEBOUNCE_TIME( DEBOUNCE_TIME ),
.SIG_OUT_INIT( SIG_OUT_INIT )
)
sw_synchronizer
(
// Input Signals (asynchronous)
.SIG_IN( SIG_IN[i] ),
// Output Signals (synchronized to CLK domain)
.SIG_OUT( SIG_OUT[i] ),
// System Signals
.CLK( CLK )
);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, cnt = 0, cnt2 = 0; cin >> n; int w; for (int i = 0; i < n; i++) { cin >> w; if (w == 100) cnt++; if (w == 200) cnt2++; } if (cnt == 0 && cnt2 % 2 != 0) { cout << NO ; return 0; } if (cnt % 2 == 0) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> data; long long a, b, h, w, n, t, minVal; inline void swap(int &a, int &b) { int tmp = a; a = b; b = tmp; } inline int mini(int a, int b) { return a < b ? a : b; } bool cmp(long long a, long long b) { return a > b; } int dfs(int crt, long long th, long long tw) { if (th >= a && tw >= b || th >= b && tw >= a) return crt; if (crt >= 34 || crt >= data.size()) return -1; if (data[crt] == minVal) { while (th < a) { th *= minVal; crt++; } while (tw < b) { tw *= minVal; crt++; } return crt <= data.size() ? crt : -1; } else { int reta = 0, retb = 0; if (th < 100000) reta = dfs(crt + 1, th * data[crt], tw); if (tw < 100000) retb = dfs(crt + 1, th, tw * data[crt]); if (reta <= 0 && retb <= 0) return -1; if (reta <= 0) return retb; if (retb <= 0) return reta; return mini(reta, retb); } } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); cin >> a >> b >> h >> w >> n; if (a > b) swap(a, b); if (h > w) swap(h, w); if (h >= a && w >= b) { printf( 0 n ); return 0; } for (int i = 0; i < n; i++) { cin >> t; data.push_back(t); } sort(data.begin(), data.end(), cmp); minVal = data[mini(33, data.size() - 1)]; printf( %d n , mini(dfs(0, h, w), dfs(0, w, h))); return 0; } |
// Memory (dummy, not software configurable)
module mem_dummy_sram(
input clk,
output SRAM_CE, SRAM_OE, SRAM_WE, SRAM_UB, SRAM_LB,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
input [0:3] nb_,
input [0:15] ad_,
output [0:15] ddt_,
input [0:15] rdt_,
input w_, r_, s_,
output ok_
);
// chip and bytes always enabled
assign SRAM_CE = 0;
assign SRAM_UB = 0;
assign SRAM_LB = 0;
assign SRAM_WE = ~we;
assign SRAM_OE = ~oe;
assign ok_ = ~(ok & (~r_ | ~w_));
`define IDLE 0
`define READ 1
`define WRITE 2
`define OK 3
reg [1:0] state = `IDLE;
reg we, oe, ok;
reg [0:15] rd_data;
always @ (posedge clk) begin
case (state)
`IDLE: begin
if (~r_) begin
state <= `READ;
oe <= 1;
end else if (~w_) begin
state <= `WRITE;
we <= 1;
end
end
`READ: begin
rd_data <= SRAM_D;
ok <= 1;
state <= `OK;
end
`WRITE: begin
we <= 0;
ok <= 1;
state <= `OK;
end
`OK: begin
oe <= 0;
if (r_ & w_) begin
ok <= 0;
state <= `IDLE;
end
end
endcase
end
// address lines
assign SRAM_A[17:0] = {2'b00, ~ad_};
// data lines
assign SRAM_D = we ? ~rdt_ : 16'hzzzz;
assign ddt_ = ~r_ ? ~rd_data : 16'hffff;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9; const long double PI = acos(-1.0); const int MX = 1e5 + 5; long long mod = 1e9 + 7; pair<long long, int> tr[5 * MX]; long long lz[5 * MX]; vector<int> ids[MX]; int rnum[MX]; inline void prop(int n, int l, int r) { if (lz[n]) { tr[n].first += lz[n]; if (l != r) lz[n << 1] += lz[n], lz[n << 1 | 1] += lz[n]; lz[n] = 0; } } const long long inf = 1e15; void bld(int n, int l, int r) { if (l == r) { if (((int)(ids[l]).size())) tr[n] = {ids[l].back(), rnum[l]}; else tr[n] = {inf, 0}; return; } int m = (l + r) >> 1; bld(n << 1, l, m); bld(n << 1 | 1, m + 1, r); tr[n] = min(tr[n << 1], tr[n << 1 | 1]); } int I, L, R, V; void del(int n, int l, int r) { prop(n, l, r); if (I < l or I > r) return; if (l == r) { long long aded = tr[n].first - ids[l].back(); ids[l].pop_back(); if (((int)(ids[l]).size())) tr[n] = {ids[l].back(), rnum[l]}; else tr[n] = {inf, rnum[l]}; tr[n].first += aded; return; } int m = (l + r) >> 1; del(n << 1, l, m); del(n << 1 | 1, m + 1, r); tr[n] = min(tr[n << 1], tr[n << 1 | 1]); } void upd(int n, int l, int r) { prop(n, l, r); if (l > R or r < L) return; if (l >= L and r <= R) { lz[n] += V; prop(n, l, r); return; } int m = (l + r) >> 1; upd(n << 1, l, m); upd(n << 1 | 1, m + 1, r); tr[n] = min(tr[n << 1], tr[n << 1 | 1]); } pair<long long, int> qry(int n, int l, int r) { prop(n, l, r); if (l > R or r < L) return {inf, 0}; if (l >= L and r <= R) { return tr[n]; } int m = (l + r) >> 1; pair<long long, int> a = qry(n << 1, l, m); pair<long long, int> b = qry(n << 1 | 1, m + 1, r); tr[n] = min(tr[n << 1], tr[n << 1 | 1]); return min(a, b); } vector<int> adj[MX]; int par[MX], sz[MX], heavy[MX]; void dfs1(int u, int p) { par[u] = p; sz[u] = 1; for (int v : adj[u]) { if (v != p) { dfs1(v, u); sz[u] += sz[v]; if (sz[v] > sz[heavy[u]]) heavy[u] = v; } } } int st[MX], chain[MX], num[MX], ed[MX], cl, cn, head[MX]; void dfs(int u) { st[u] = cl; chain[u] = cn; num[u] = cl; rnum[cl++] = u; if (heavy[u]) dfs(heavy[u]); for (int v : adj[u]) { if (v != par[u] and v != heavy[u]) { head[++cn] = v; dfs(v); } } ed[u] = cl - 1; } inline int climb(int u, int v, int n) { pair<long long, int> res = {inf, 0}; while (chain[u] != chain[v]) { if (chain[v] > chain[u]) swap(u, v); R = num[u]; L = num[head[chain[u]]]; res = min(res, qry(1, 0, n - 1)); u = par[head[chain[u]]]; } if (num[v] > num[u]) swap(u, v); L = num[v], R = num[u]; res = min(res, qry(1, 0, n - 1)); if (res.first >= inf) return 0; int ret = ids[num[res.second]].back(); I = num[res.second]; del(1, 0, n - 1); return ret; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, q; cin >> n >> m >> q; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs1(1, 0); head[0] = 1; dfs(1); for (int i = 1; i <= m; i++) { int c; cin >> c; ids[num[c]].emplace_back(i); } for (int i = 0; i < n; i++) reverse((ids[i]).begin(), (ids[i]).end()); bld(1, 0, n - 1); while (q--) { int t; cin >> t; int u, v, k; if (t == 1) { cin >> u >> v >> k; vector<int> ans; while (k--) { int i = climb(u, v, n); if (i) ans.push_back(i); else break; } cout << ((int)(ans).size()); for (int i : ans) cout << << i; cout << n ; } else { cin >> u >> k; L = st[u]; R = ed[u]; V = k; upd(1, 0, n - 1); } } return 0; } |
#include <bits/stdc++.h> using namespace std; string s[110 * 110]; vector<string> v; char sub(string s1, string s2) { int dem[30]; memset(dem, 0, sizeof(dem)); for (int i = 0; i < s1.size(); i++) dem[s1[i] - a ]++; for (int i = 0; i < s2.size(); i++) dem[s2[i] - a ]--; for (int i = 0; i <= z - a ; i++) if (dem[i] == 1) return char(i + a ); } bool cmp(string s1, string s2) { return (s1.length() > s2.length()); } int main() { int n; cin >> n; if (n == 1) { cout << ? << << 1 << << 1 << endl; cout.flush(); string s; cin >> s; cout << ! << s; return 0; } cout << ? << << 1 << << n - 1 << endl; cout.flush(); int t = (n * (n - 1)) / 2; map<string, int> ma; for (int i = 1; i <= t; i++) { string s; cin >> s; sort(s.begin(), s.end()); ma[s]++; } cout << ? << << 1 << << n << endl; cout.flush(); t = (n * (n + 1)) / 2; for (int i = 1; i <= t; i++) { string s; cin >> s; sort(s.begin(), s.end()); if (ma[s] > 0) ma[s]--; else v.push_back(s); } sort(v.begin(), v.end(), cmp); cout << ! ; for (int i = 0; i < v.size() - 1; i++) cout << sub(v[i], v[i + 1]); cout << v.back(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const double INF = 1e12, EPS = 1e-9; int n; pair<int, int> p[5000]; int main() { cin >> n; for (int i = 0; i < (int)n; i++) { int a, b; cin >> a >> b; p[i] = pair<int, int>(a, b); } sort(p, p + n); int mn = 0; for (int i = 0; i < (int)n; i++) { if (p[i].second >= mn) mn = p[i].second; else mn = p[i].first; } cout << mn << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, r, i; cin >> n >> m; r = m % ((n * (n + 1) / 2)); for (i = 0; i < n; i++) { if (i + 1 > r) { cout << r; break; } else r -= i + 1; } return 0; } |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_mixer.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU mixer.
***************************************************************************************************/
module apu_mixer
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire [3:0] mute_in, // mute specific channels
input wire [3:0] pulse0_in, // pulse 0 channel input
input wire [3:0] pulse1_in, // pulse 1 channel input
input wire [3:0] triangle_in, // triangle channel input
input wire [3:0] noise_in, // noise channel input
output wire audio_out // mixed audio output
);
wire [3:0] pulse0;
wire [3:0] pulse1;
wire [3:0] triangle;
wire [3:0] noise;
reg [4:0] pulse_in_total;
reg [5:0] pulse_out;
reg [6:0] tnd_in_total;
reg [5:0] tnd_out;
reg [5:0] mixed_out;
always @*
begin
pulse_in_total = pulse0 + pulse1;
case (pulse_in_total)
5'h00: pulse_out = 6'h00;
5'h01: pulse_out = 6'h01;
5'h02: pulse_out = 6'h01;
5'h03: pulse_out = 6'h02;
5'h04: pulse_out = 6'h03;
5'h05: pulse_out = 6'h03;
5'h06: pulse_out = 6'h04;
5'h07: pulse_out = 6'h05;
5'h08: pulse_out = 6'h05;
5'h09: pulse_out = 6'h06;
5'h0A: pulse_out = 6'h07;
5'h0B: pulse_out = 6'h07;
5'h0C: pulse_out = 6'h08;
5'h0D: pulse_out = 6'h08;
5'h0E: pulse_out = 6'h09;
5'h0F: pulse_out = 6'h09;
5'h10: pulse_out = 6'h0A;
5'h11: pulse_out = 6'h0A;
5'h12: pulse_out = 6'h0B;
5'h13: pulse_out = 6'h0B;
5'h14: pulse_out = 6'h0C;
5'h15: pulse_out = 6'h0C;
5'h16: pulse_out = 6'h0D;
5'h17: pulse_out = 6'h0D;
5'h18: pulse_out = 6'h0E;
5'h19: pulse_out = 6'h0E;
5'h1A: pulse_out = 6'h0F;
5'h1B: pulse_out = 6'h0F;
5'h1C: pulse_out = 6'h0F;
5'h1D: pulse_out = 6'h10;
5'h1E: pulse_out = 6'h10;
default: pulse_out = 6'bxxxxxx;
endcase
tnd_in_total = { triangle, 1'b0 } + { 1'b0, triangle } + { noise, 1'b0 };
case (tnd_in_total)
7'h00: tnd_out = 6'h00;
7'h01: tnd_out = 6'h01;
7'h02: tnd_out = 6'h01;
7'h03: tnd_out = 6'h02;
7'h04: tnd_out = 6'h03;
7'h05: tnd_out = 6'h03;
7'h06: tnd_out = 6'h04;
7'h07: tnd_out = 6'h05;
7'h08: tnd_out = 6'h05;
7'h09: tnd_out = 6'h06;
7'h0A: tnd_out = 6'h07;
7'h0B: tnd_out = 6'h07;
7'h0C: tnd_out = 6'h08;
7'h0D: tnd_out = 6'h08;
7'h0E: tnd_out = 6'h09;
7'h0F: tnd_out = 6'h09;
7'h10: tnd_out = 6'h0A;
7'h11: tnd_out = 6'h0A;
7'h12: tnd_out = 6'h0B;
7'h13: tnd_out = 6'h0B;
7'h14: tnd_out = 6'h0C;
7'h15: tnd_out = 6'h0C;
7'h16: tnd_out = 6'h0D;
7'h17: tnd_out = 6'h0D;
7'h18: tnd_out = 6'h0E;
7'h19: tnd_out = 6'h0E;
7'h1A: tnd_out = 6'h0F;
7'h1B: tnd_out = 6'h0F;
7'h1C: tnd_out = 6'h0F;
7'h1D: tnd_out = 6'h10;
7'h1E: tnd_out = 6'h10;
7'h1F: tnd_out = 6'h11;
7'h20: tnd_out = 6'h11;
7'h21: tnd_out = 6'h11;
7'h22: tnd_out = 6'h12;
7'h23: tnd_out = 6'h12;
7'h24: tnd_out = 6'h12;
7'h25: tnd_out = 6'h13;
7'h26: tnd_out = 6'h13;
7'h27: tnd_out = 6'h14;
7'h28: tnd_out = 6'h14;
7'h29: tnd_out = 6'h14;
7'h2A: tnd_out = 6'h15;
7'h2B: tnd_out = 6'h15;
7'h2C: tnd_out = 6'h15;
7'h2D: tnd_out = 6'h15;
7'h2E: tnd_out = 6'h16;
7'h2F: tnd_out = 6'h16;
7'h30: tnd_out = 6'h16;
7'h31: tnd_out = 6'h17;
7'h32: tnd_out = 6'h17;
7'h33: tnd_out = 6'h17;
7'h34: tnd_out = 6'h17;
7'h35: tnd_out = 6'h18;
7'h36: tnd_out = 6'h18;
7'h37: tnd_out = 6'h18;
7'h38: tnd_out = 6'h19;
7'h39: tnd_out = 6'h19;
7'h3A: tnd_out = 6'h19;
7'h3B: tnd_out = 6'h19;
7'h3C: tnd_out = 6'h1A;
7'h3D: tnd_out = 6'h1A;
7'h3E: tnd_out = 6'h1A;
7'h3F: tnd_out = 6'h1A;
7'h40: tnd_out = 6'h1B;
7'h41: tnd_out = 6'h1B;
7'h42: tnd_out = 6'h1B;
7'h43: tnd_out = 6'h1B;
7'h44: tnd_out = 6'h1B;
7'h45: tnd_out = 6'h1C;
7'h46: tnd_out = 6'h1C;
7'h47: tnd_out = 6'h1C;
7'h48: tnd_out = 6'h1C;
7'h49: tnd_out = 6'h1C;
7'h4A: tnd_out = 6'h1D;
7'h4B: tnd_out = 6'h1D;
default: tnd_out = 6'bxxxxxx;
endcase
mixed_out = pulse_out + tnd_out;
end
//
// Pulse width modulation.
//
reg [5:0] q_pwm_cnt;
wire [5:0] d_pwm_cnt;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_pwm_cnt <= 6'h0;
end
else
begin
q_pwm_cnt <= d_pwm_cnt;
end
end
assign d_pwm_cnt = q_pwm_cnt + 4'h1;
assign pulse0 = (mute_in[0]) ? 4'h0 : pulse0_in;
assign pulse1 = (mute_in[1]) ? 4'h0 : pulse1_in;
assign triangle = (mute_in[2]) ? 4'h0 : triangle_in;
assign noise = (mute_in[3]) ? 4'h0 : noise_in;
assign audio_out = mixed_out > q_pwm_cnt;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long n, m; string p, s; vector<int> pos; long long exp(long long a, long long x) { if (x == 0) return 1; long long tmp = exp(a, x / 2); tmp *= tmp; tmp %= MOD; if (x % 2) tmp *= a; tmp %= MOD; return tmp; } bool z(string str) { int n = (int)str.length(); vector<int> z(n); for (int i = 1, l = 0, r = 0; i < n; ++i) { if (i <= r) z[i] = min(r - i + 1, z[i - l]); while (i + z[i] < n && str[z[i]] == str[i + z[i]]) ++z[i]; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; } for (int i = 0; i < pos.size(); ++i) { if (z[pos[i] + p.size() + 1] != p.size()) return false; } return true; } int main() { cin >> n >> m >> p; pos.assign(m, 0); for (int i = 0; i < m; ++i) { cin >> pos[i]; pos[i]--; } sort(pos.begin(), pos.end()); for (int i = 0; i < m; ++i) { while (s.size() < pos[i]) s += . ; int stp = s.size(); for (int j = stp - pos[i]; j < p.size(); ++j) { s += p[j]; } } while (s.size() < n) s += . ; s = p + # + s; if (z(s)) { int cnt = 0; for (auto i : s) cnt += i == . ; cout << exp(26, cnt); } else cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; set<int> s; s.insert(0); int a; for (int i = 1; i <= n; i++) { cin >> a; if (s.find(a) != s.end()) { s.erase(a); } s.insert(i); } cout << s.size(); } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of top
//
// Generated
// by: wig
// on: Tue Apr 1 13:31:51 2008
// cmd: /cygdrive/c/eclipse/MIX/mix_0.pl -strip -nodelta ../noassign.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: top.v,v 1.1 2008/04/01 12:53:30 wig Exp $
// $Date: 2008/04/01 12:53:30 $
// $Log: top.v,v $
// Revision 1.1 2008/04/01 12:53:30 wig
// Added testcase noassign for optimzeassignport feature
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of top
//
// No user `defines in this module
module top
//
// Generated Module TOP
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire clk;
wire clk2_i;
wire data;
wire data2_i;
wire ready0;
wire ready1;
wire ready2_0;
wire ready2_1;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for M0
m0 M0 (
.clk2_o(clk2_i),
.clk_o(clk),
.data2_o(data2_i),
.data_o(data),
.ready0_i(ready0),
.ready1_i(ready1),
.ready2_0(ready2_0),
.ready2_1(ready2_1)
);
// End of Generated Instance Port Map for M0
// Generated Instance Port Map for N0
n0 N0 (
.clk2_i_i(clk2_i),
.clk_i(clk),
.data2_i_i(data2_i),
.data_i(data),
.ready0_o(ready0),
.ready1_o(ready1),
.ready2_0_o(ready2_0),
.ready2_1_o(ready2_1)
);
// End of Generated Instance Port Map for N0
endmodule
//
// End of Generated Module rtl of top
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; char c[10][10]; int ans; int main() { cin >> c[1] >> c[2] >> c[3] >> c[4] >> c[5] >> c[6] >> c[7] >> c[8]; for (int i = 1; i <= 8; i++) { int p = 0; for (int j = 0; j < 8; j++) if (c[i][j] == B ) p++; if (p == 8) ans++; p = 0; for (int j = 1; j <= 8; j++) if (c[j][i - 1] == B ) p++; if (p == 8) ans++; } if (ans != 16) cout << ans; else cout << 8; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXK = 26; const long long MOD = 1e9 + 7; int last[MAXK], ord[MAXK]; long long sum, dp[MAXK]; void add(int c) { sum = (sum - dp[c] + MOD) % MOD; dp[c] = (dp[c] + sum + 1) % MOD; sum = (sum + dp[c]) % MOD; } int main() { ios_base::sync_with_stdio(false); int N, K; string S; cin >> N >> K >> S; memset((last), (-1), sizeof(last)); sum = 0; for (int _n((int)S.size()), i(0); i < _n; i++) { int c = S[i] - a ; last[c] = i; add(c); } iota(ord, ord + K, 0); sort(ord, ord + K, [](int a, int b) { return last[a] < last[b]; }); for (int _n(N), i(0); i < _n; i++) { int c = ord[i % K]; add(c); } cout << (sum + 1) % MOD << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long double EPS = (long double)1e-7; const long double PI = acos(0) * 2; bool isZero(const long double& x) { return abs(x) <= EPS; } int sign(const long double& x) { return isZero(x) ? 0 : (0 < x ? 1 : -1); } long long gcd(long long a, long long b) { for (; b; a %= b, swap(a, b)) { } return abs(a); } pair<long long, long long> operator+(const pair<long long, long long>& a, const pair<long long, long long>& b) { return pair<long long, long long>(a.first + b.first, a.second + b.second); } pair<long long, long long> operator-(const pair<long long, long long>& a, const pair<long long, long long>& b) { return pair<long long, long long>(a.first - b.first, a.second - b.second); } pair<long long, long long> operator*(const pair<long long, long long>& a, const long long& b) { return pair<long long, long long>(a.first * b, a.second * b); } long long operator*(const pair<long long, long long>& a, const pair<long long, long long>& b) { return a.first * b.second - b.first * a.second; } long long ccw(const pair<long long, long long>& a, const pair<long long, long long>& b, const pair<long long, long long>& c) { return a * b + b * c + c * a; } void fg(vector<int> G[], int a, int b) { G[a].emplace_back(b); G[b].emplace_back(a); } void fg(vector<pair<int, int> > G[], int a, int b, int c) { G[a].emplace_back(b, c); G[b].emplace_back(a, c); } const int MAXN = 1000055; int A[MAXN], B[MAXN]; bitset<MAXN> C; int T, N; void run() { cin >> N; for (int i = 1; i <= N; i++) { cin >> A[i]; B[i] = i - A[i]; } vector<int> V; for (int i = 1;;) { V.emplace_back(i); if (C[i]) break; C[i] = true; i = B[i]; } for (int v : V) C[v] = false; V.erase(V.begin(), find(((V).begin()), ((V).end()), V.back()) + 1); cout << ((int)(V).size()) << n ; for (int v : V) cout << v << ; cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); for (cin >> T; T--;) run(); return 0; } |
/**
* sram.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
/* Xilinx BRAM module creation */
module sram(
input wire [ 7 : 0] address, /* address bus */
input wire [ 7 : 0] data_in, /* data input bus */
input wire clk, /* clock */
input wire write_enable, /* memory write enable */
output reg [ 7 : 0] data_out /* data output bus */
);
/* 255x8 SRAM block */
reg [ 7 : 0] memory [255 : 0];
/* Xilinx BRAM module generation */
always @(posedge clk) begin
if(write_enable)
memory[address] <= data_in;
data_out <= memory[address];
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
// nios_tester_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module nios_tester_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [31:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [29:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_tester_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 130 * 1000 + 5; const int mod = 1000 * 1000 * 1000 + 7; short dp[21][32][maxN]; int mas[maxN]; int ss[6][maxN]; int a[20], b[20]; vector<int> v[6]; int c[20], d[20]; int n, m; char ans[20][20]; int p; void solve(int lev, int mask, int state) { if (lev == 0) return; int tmp = state; for (int z = 0; z < n; z++) { c[z] = tmp % p; tmp /= p; } int smask = dp[lev][mask][state]; for (int j = 0; j < n; j++) { d[j] = c[j]; if ((mask >> j & 1) != (smask >> j & 1)) { if (mask >> j & 1) d[j]--; } } int sstate = 0; for (int j = n - 1; j >= 0; j--) sstate *= p, sstate += d[j]; solve(lev - 1, smask, sstate); for (int i = 0; i < n; i++) ans[i][lev - 1] = ((mask >> i & 1) ? * : . ); } int tof[32][32], tofm[32][32]; int main() { ios::sync_with_stdio(0); cin.tie(); memset(dp, -1, sizeof dp); cin >> n >> m; for (int mask = 0; mask < (1 << n); mask++) { int bef = 0, st = 0; for (int i = 0; i < n; i++) if (mask >> i & 1) { if (bef == 0) st++; bef = 1; } else bef = 0; v[st].push_back(mask); } for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) cin >> b[i]; p = *max_element(a, a + n); p++; int stat = 0; for (int i = n - 1; i >= 0; i--) stat *= p, stat += a[i]; for (int state = 0; state < stat + 1; state++) { int tmp = state; for (int z = 0; z < n; z++) { ss[z][state] = tmp % p; if (ss[z][state] == 0) mas[state] |= (1 << z); tmp /= p; } } for (int mask = 0; mask < (1 << n); mask++) for (int smask = 0; smask < (1 << n); smask++) { int pp = 0; for (int j = 0; j < n; j++) { d[j] = 0; if ((mask >> j & 1) != (smask >> j & 1)) { if (mask >> j & 1) d[j]--, tofm[mask][smask] |= (1 << j); } } int sstate = 0; for (int j = n - 1; j >= 0; j--) sstate *= p, sstate += d[j]; tof[mask][smask] = sstate; } for (int i = 1; i < m + 1; i++) { int ind = b[i - 1]; for (int state = 0; state < stat + 1; state++) { for (auto mask : v[ind]) { for (auto smask : v[(i == 1 ? 0 : b[i - 2])]) { if (tofm[mask][smask] & mas[state]) continue; int sstate = state + tof[mask][smask]; if (dp[i - 1][smask][sstate] != -1 || (i == 1 && sstate == 0 && smask == 0)) { dp[i][mask][state] = smask; break; } } } } } int answer = -1; for (int i = 0; i < (1 << n); i++) { if (dp[m][i][stat] > -1) { answer = i; break; } } solve(m, answer, stat); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << ans[i][j]; cout << endl; } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:07:01 03/24/2015
// Design Name: hcsr04
// Module Name: /home/michael/Projects/mojo/ultrasonic-fountain/hcsr04_test.v
// Project Name: Mojo-Base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: hcsr04
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module hcsr04_test;
// Inputs
reg rst;
reg clk;
reg measure;
reg echo;
// Outputs
wire [15:0] ticks;
wire valid;
wire trigger;
wire clk_10us;
clk_divider #(.DIV(500)) clk_10usmodule(
.rst(rst),
.clk(clk),
.div_clk(clk_10us)
);
// Instantiate the Unit Under Test (UUT)
hcsr04 #(
.TRIGGER_DURATION(1),
.MAX_COUNT(3800)
) uut (
.rst(rst),
.clk(clk),
.tclk(clk_10us),
.measure(measure),
.echo(echo),
.ticks(ticks),
.valid(valid),
.trigger(trigger)
);
initial begin
// Initialize Inputs
rst = 0;
clk = 0;
measure = 0;
echo = 0;
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
measure = 0; // initial value
@(negedge rst); // wait for reset
measure = 1;
repeat(5000) @(posedge clk); //wait for trigger to finish, 10us
echo = 1;
repeat(100000) @(posedge clk); //echo for 10ms
echo = 0;
repeat (100000) @(posedge clk);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
|
#include <bits/stdc++.h> using namespace std; struct keep { int pos; int apples; }; keep inp[1000]; bool cmp(keep x, keep y) { if (x.pos < y.pos) return 1; return 0; } int main() { int n; cin >> n; int l = 0, r = 0; int sum = 0; for (int i = 0; i < n; i++) { cin >> inp[i].pos >> inp[i].apples; inp[i].pos < 0 ? l++ : r++; sum += inp[i].apples; } sort(inp, inp + n, cmp); if (l == 0) { cout << inp[0].apples; return 0; } if (r == 0) { cout << inp[n - 1].apples; return 0; } if (l - r == 1 || r - l == 1 || l == r) { cout << sum << endl; return 0; } if (l > r) { int ans = 0; int c = 0; int i; for (i = n - 1; inp[i].pos > 0; i--) { ans += inp[i].apples; c++; } int cc = 1; for (; cc <= c + 1; i--) { ans += inp[i].apples; cc++; } cout << ans; return 0; } if (r > l) { int ans = 0; int c = 0; int i; for (i = 0; inp[i].pos < 0; i++) { ans += inp[i].apples; c++; } int cc = 1; for (; cc <= c + 1; i++) { ans += inp[i].apples; cc++; } cout << ans; return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 15; int prime[maxn]; bool visit[maxn] = {false}; vector<int> prim; vector<int> nu; void init() { int pos = 0; for (int i = 2; i < maxn; i++) { if (visit[i] == false) { prime[pos++] = i; } for (int j = 0; j < pos && prime[j] * i < maxn; j++) { visit[prime[j] * i] = true; if (i % prime[j] == 0) { break; } } } } bool isprime(long long test) { for (int i = 2; i <= sqrt(test); i++) { if (test / 2 == 0) { return false; } } return true; } void find(long long test) { for (int i = 0; prime[i] <= sqrt(test); i++) { int num = 0; while (test % prime[i] == 0) { num++; test /= prime[i]; } if (num != 0) { prim.push_back(prime[i]); nu.push_back(num); } } if (isprime(test) && test > 1) { prim.push_back(test); nu.push_back(1); } } int main() { int t; init(); cin >> t; long long p, q; while (t--) { cin >> p >> q; prim.clear(); nu.clear(); find(q); if (p % q != 0) { cout << p << endl; } else { long long maxans = -100; for (int i = 0; i < prim.size(); i++) { int tmpnum = 0; long long test = p; long long ans = p; while (test % prim[i] == 0) { test /= prim[i]; tmpnum++; } int reducenum = tmpnum - nu[i] + 1; ans = ans / pow(prim[i], reducenum); maxans = max(ans, maxans); } cout << maxans << endl; } } } |
#include <bits/stdc++.h> using namespace std; int main() { long long q = 1; while (q--) { long long n, k; cin >> n >> k; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long sum = 0, ans; for (long long i = 0; i < k; i++) sum += a[i]; ans = sum; long long ind = 1; long long j = k; while (j < n) { sum -= a[j - k]; sum += a[j]; if (sum < ans) { ans = sum; ind = j - k + 2; } j++; } cout << ind << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_1_V
`define SKY130_FD_SC_HVL__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_1_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_hostif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input usb_clk,
output reg usb_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input io_we,
input [5:0] io_a
);
wire csr_selected = csr_a[13:10] == csr_addr;
reg usb_rst0;
always @(posedge sys_clk) begin
if(sys_rst) begin
usb_rst0 <= 1'b1;
csr_do <= 1'b0;
end else begin
csr_do <= 1'b0;
if(csr_selected) begin
if(csr_we)
usb_rst0 <= csr_di[0];
csr_do <= usb_rst0;
end
end
end
/* Synchronize USB Reset to the USB clock domain */
reg usb_rst1;
always @(posedge usb_clk) begin
usb_rst1 <= usb_rst0;
usb_rst <= usb_rst1;
end
/* Generate IRQs */
reg irq_flip;
always @(posedge usb_clk) begin
if(usb_rst)
irq_flip <= 1'b0;
else if(io_we && (io_a == 6'h15))
irq_flip <= ~irq_flip;
end
reg irq_flip0;
reg irq_flip1;
reg irq_flip2;
always @(posedge sys_clk) begin
irq_flip0 <= irq_flip;
irq_flip1 <= irq_flip0;
irq_flip2 <= irq_flip1;
end
assign irq = irq_flip1 != irq_flip2;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:41:22 09/24/2013
// Design Name: Clock_Divider
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_divisor.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Clock_Divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_divisor;
// Inputs
reg clock;
reg reset;
// Outputs
wire clock_out;
// Instantiate the Unit Under Test (UUT)
Clock_Divider uut (
.clock(clock),
.reset(reset),
.clock_out(clock_out)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: thomasdaede.com:user:daala_4x4_transpose:1.0
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_daala_4x4_transpose_0_0 (
axis_clk,
axis_aresetn,
s00_axis_tdata,
s00_axis_tlast,
s00_axis_tvalid,
s00_axis_tready,
m00_axis_tdata,
m00_axis_tlast,
m00_axis_tvalid,
m00_axis_tready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 axis_clk CLK" *)
input axis_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 axis_aresetn RST" *)
input axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TDATA" *)
input [255 : 0] s00_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TLAST" *)
input s00_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TVALID" *)
input s00_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TREADY" *)
output s00_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TDATA" *)
output [255 : 0] m00_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TLAST" *)
output m00_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TVALID" *)
output m00_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M00_AXIS TREADY" *)
input m00_axis_tready;
daala_4x4_transpose_v1_0 #(
.C_S00_AXIS_TDATA_WIDTH(256),
.C_M00_AXIS_TDATA_WIDTH(256)
) inst (
.axis_clk(axis_clk),
.axis_aresetn(axis_aresetn),
.s00_axis_tdata(s00_axis_tdata),
.s00_axis_tlast(s00_axis_tlast),
.s00_axis_tvalid(s00_axis_tvalid),
.s00_axis_tready(s00_axis_tready),
.m00_axis_tdata(m00_axis_tdata),
.m00_axis_tlast(m00_axis_tlast),
.m00_axis_tvalid(m00_axis_tvalid),
.m00_axis_tready(m00_axis_tready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; string a; cin >> a; if (n & 1) { cout << :( ; return 0; } int cnt1 = 1; int cnt2 = 1; if (a[0] == ) ) { cout << :( ; return 0; } a[0] = ( ; if (a.back() == ( ) { cout << :( ; return 0; } a[a.size() - 1] = ) ; for (int i = 1; i < a.size(); ++i) if (a[i] == ( ) ++cnt1; if (cnt1 > n / 2) { cout << :( ; return 0; } for (int i = 0; i < a.size(); ++i) { if (a[i] == ? ) { ++cnt1; a[i] = ( ; } if (cnt1 == n / 2) break; } if (cnt1 < n / 2) { cout << :( ; return 0; } for (int i = 0; i < a.size(); ++i) if (a[i] == ? ) a[i] = ) ; stack<int> s; for (int i = 0; i < a.size(); ++i) { if (a[i] == ( ) s.push(a[i]); else { if (s.empty()) { cout << :( ; return 0; } else { s.pop(); if (s.empty() && i != a.size() - 1) { cout << :( ; return 0; } } } } if (!s.empty()) { cout << :( ; return 0; } for (int i = 0; i < a.size(); ++i) cout << a[i]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5 * 100 + 10; int n, dp1[N][N], dp2[N][N], k, par[N][N]; string s; void printpath(int i, int j) { if (j == 0) return; printpath(i - par[i][j], j - 1); if (j > 1) cout << + ; if (par[i][j] == 1) cout << s[i - 1]; else { for (int l = i - par[i][j]; l <= i - (((par[i][j] + 1) / 2) + 1); l++) cout << s[l]; if (par[i][j] % 2 == 1) cout << s[i - (((par[i][j] + 1) / 2) + 1) + 1]; for (int l = i - (((par[i][j] + 1) / 2) + 1); l >= i - par[i][j]; l--) cout << s[l]; } } int main() { cin >> s >> k; n = s.size(); for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) for (int l = i; l <= ((j - i) / 2) + i; l++) if (s[l] != s[j - l + i]) dp1[i][j]++; for (int i = 0; i < N; i++) fill(dp2[i], dp2[i] + N, INT_MAX); dp2[0][0] = 0; for (int i = 0; i < n; i++) for (int j = 0; j < k; j++) for (int len = 1; len <= n; len++) if (dp2[i][j] != INT_MAX) if (dp2[i + len][j + 1] >= dp2[i][j] + dp1[i][i + len - 1]) dp2[i + len][j + 1] = dp2[i][j] + dp1[i][i + len - 1], par[i + len][j + 1] = len; int ans = INT_MAX, r; for (int i = 1; i <= k; i++) if (dp2[n][i] < ans) ans = dp2[n][i], r = i; cout << ans << endl; printpath(n, r); return 0; } |
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define low_pos(x,y) `high_pos(x,y) - 63
`define high_pos(x,y) 1599 - 64*(5*y+x)
`define add_1(x) (x == 4 ? 0 : x + 1)
`define add_2(x) (x == 3 ? 0 : x == 4 ? 1 : x + 2)
`define sub_1(x) (x == 0 ? 4 : x - 1)
`define rot_up(in, n) {in[63-n:0], in[63:63-n+1]}
`define rot_up_1(in) {in[62:0], in[63]}
module round(in, round_const, out);
input [1599:0] in;
input [63:0] round_const;
output [1599:0] out;
wire [63:0] a[4:0][4:0];
wire [63:0] b[4:0];
wire [63:0] c[4:0][4:0], d[4:0][4:0], e[4:0][4:0], f[4:0][4:0], g[4:0][4:0];
genvar x, y;
/* assign "a[x][y][z] == in[w(5y+x)+z]" */
generate
for(y=0; y<5; y=y+1)
begin : L0
for(x=0; x<5; x=x+1)
begin : L1
assign a[x][y] = in[`high_pos(x,y) : `low_pos(x,y)];
end
end
endgenerate
/* calc "b[x] == a[x][0] ^ a[x][1] ^ ... ^ a[x][4]" */
generate
for(x=0; x<5; x=x+1)
begin : L2
assign b[x] = a[x][0] ^ a[x][1] ^ a[x][2] ^ a[x][3] ^ a[x][4];
end
endgenerate
/* calc "c == theta(a)" */
generate
for(y=0; y<5; y=y+1)
begin : L3
for(x=0; x<5; x=x+1)
begin : L4
assign c[x][y] = a[x][y] ^ b[`sub_1(x)] ^ `rot_up_1(b[`add_1(x)]);
end
end
endgenerate
/* calc "d == rho(c)" */
assign d[0][0] = c[0][0];
assign d[1][0] = `rot_up_1(c[1][0]);
assign d[2][0] = `rot_up(c[2][0], 62);
assign d[3][0] = `rot_up(c[3][0], 28);
assign d[4][0] = `rot_up(c[4][0], 27);
assign d[0][1] = `rot_up(c[0][1], 36);
assign d[1][1] = `rot_up(c[1][1], 44);
assign d[2][1] = `rot_up(c[2][1], 6);
assign d[3][1] = `rot_up(c[3][1], 55);
assign d[4][1] = `rot_up(c[4][1], 20);
assign d[0][2] = `rot_up(c[0][2], 3);
assign d[1][2] = `rot_up(c[1][2], 10);
assign d[2][2] = `rot_up(c[2][2], 43);
assign d[3][2] = `rot_up(c[3][2], 25);
assign d[4][2] = `rot_up(c[4][2], 39);
assign d[0][3] = `rot_up(c[0][3], 41);
assign d[1][3] = `rot_up(c[1][3], 45);
assign d[2][3] = `rot_up(c[2][3], 15);
assign d[3][3] = `rot_up(c[3][3], 21);
assign d[4][3] = `rot_up(c[4][3], 8);
assign d[0][4] = `rot_up(c[0][4], 18);
assign d[1][4] = `rot_up(c[1][4], 2);
assign d[2][4] = `rot_up(c[2][4], 61);
assign d[3][4] = `rot_up(c[3][4], 56);
assign d[4][4] = `rot_up(c[4][4], 14);
/* calc "e == pi(d)" */
assign e[0][0] = d[0][0];
assign e[0][2] = d[1][0];
assign e[0][4] = d[2][0];
assign e[0][1] = d[3][0];
assign e[0][3] = d[4][0];
assign e[1][3] = d[0][1];
assign e[1][0] = d[1][1];
assign e[1][2] = d[2][1];
assign e[1][4] = d[3][1];
assign e[1][1] = d[4][1];
assign e[2][1] = d[0][2];
assign e[2][3] = d[1][2];
assign e[2][0] = d[2][2];
assign e[2][2] = d[3][2];
assign e[2][4] = d[4][2];
assign e[3][4] = d[0][3];
assign e[3][1] = d[1][3];
assign e[3][3] = d[2][3];
assign e[3][0] = d[3][3];
assign e[3][2] = d[4][3];
assign e[4][2] = d[0][4];
assign e[4][4] = d[1][4];
assign e[4][1] = d[2][4];
assign e[4][3] = d[3][4];
assign e[4][0] = d[4][4];
/* calc "f = chi(e)" */
generate
for(y=0; y<5; y=y+1)
begin : L5
for(x=0; x<5; x=x+1)
begin : L6
assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]);
end
end
endgenerate
/* calc "g = iota(f)" */
generate
for(x=0; x<64; x=x+1)
begin : L60
if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63)
assign g[0][0][x] = f[0][0][x] ^ round_const[x];
else
assign g[0][0][x] = f[0][0][x];
end
endgenerate
generate
for(y=0; y<5; y=y+1)
begin : L7
for(x=0; x<5; x=x+1)
begin : L8
if(x!=0 || y!=0)
assign g[x][y] = f[x][y];
end
end
endgenerate
/* assign "out[w(5y+x)+z] == out_var[x][y][z]" */
generate
for(y=0; y<5; y=y+1)
begin : L99
for(x=0; x<5; x=x+1)
begin : L100
assign out[`high_pos(x,y) : `low_pos(x,y)] = g[x][y];
end
end
endgenerate
endmodule
`undef low_pos
`undef high_pos
`undef add_1
`undef add_2
`undef sub_1
`undef rot_up
`undef rot_up_1
|
#include <bits/stdc++.h> using namespace std; void FastIO() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); } vector<long long int> fib; void calc(int n) { fib.assign(n + 1, 0); fib[0] = 1; fib[1] = 1; for (int i = (int)2; i <= (int)n; i++) { fib[i] = fib[i - 1] + fib[i - 2]; } } int main() { long long int n, k; cin >> n >> k; calc(n); vector<long long int> ans; for (int i = 0; i < (int)n; i++) { if (k <= fib[n - 1 - i]) ans.push_back(i + 1); else { ans.push_back(i + 2); ans.push_back(i + 1); k -= fib[n - 1 - i]; i++; } } for (int i = 0; i < (int)n; i++) { cout << ans[i] << ; } cout << n ; return 0; } |
#include<bits/stdc++.h> using namespace std; template<typename AA>inline void CMax(AA &u,AA v){if(v>u)u=v;} template<typename AA>inline void CMin(AA &u,AA v){if(v<u)u=v;} #define Put(a) cout<<(a)<<endl #define For(a,b,c) for(int a=(b);a<=(c);++a) #define Fov(a,b,c) for(int a=(b);a>=(c);--a) #define Foe(a,b,c) for(int a=(b);a<(c);++a) #define Clear(a,b) memset(a,b,sizeof(a)) const double eps=1E-8;const int Inf=0x3f3f3f3f,oo=0x7fffffff,Mod=998244353; typedef long long lon;const lon Lnf=0x3f3f3f3f3f3f3f3f; template<typename AA>void read(AA &x) {int s=0;char c;while(c=getchar(),(c< 0 ||c> 9 )&&c!= - );c== - ?(s=1,x=0):(x=c- 0 ); while(c=getchar(),c>= 0 &&c<= 9 ) x=x*10+c- 0 ;if(s) x=-x;} template<typename AA, typename...Args>void read(AA &t,Args &...args) {read(t);read(args...);}template<typename AA>void print(AA k){int num=0; static char stk[23];if(k<0){putchar( - );k=-k;}while(k>0)stk[++num]=k%10+48,k/=10; if(!num)putchar( 0 );else while(num)putchar(stk[num--]);putchar( n );} inline int Log2(int x) {if(!x)return 0;else return 31-__builtin_clz(x);} char getc(){char ch;do{ch=getchar();}while(ch== ||ch== n );return ch;} lon Pow(lon d,lon m){lon f=1;while(m){if(m&1)f=f*d%Mod;d=d*d%Mod;m>>=1;}return f;} //#include<ext/rope> using namespace __gnu_cxx; //#include<bits/extc++.h>#include<ext/pb_ds/assoc_container.hpp> //using namespace __gnu_pbds; //#pragma GCC optimize(3) int N,M,S,Q,K,T=1; int u,v; char s[300030]; int n; int nd[300030]; int ansp;char ansc; void init() { int cnt[26]={}; For(a,1,n) { if(cnt[s[a]- a ]==0) nd[a]=nd[a-1]+K-1; else nd[a]=nd[a-1]-1; cnt[s[a]- a ]=(cnt[s[a]- a ]+1)%K; if(a<n&&s[a+1]< z ) { Fov(b,25,0) { if( a +b==s[a+1]) break; if(cnt[b]==0) { nd[a+1]=nd[a]+K-1; } else { nd[a+1]=nd[a]-1; } if(n-a-1>=nd[a+1]&&(n-a-1-nd[a+1])%K==0) ansp=a+1,ansc= a +b; } } } } signed main() { //freopen( 1.in , r ,stdin); read(T); while(T--) { read(N,K); scanf( %s ,s+1); n=strlen(s+1); ansp=1;ansc=s[1]+1; if(N%K) {puts( -1 );continue;} init(); //printf( %d %c n ,ansp,ansc); if(nd[n]==0) {printf( %s n ,s+1);continue;} if(ansp==1&&ansc> z ) {puts( -1 );continue;} int cnt[26]={}; s[ansp]=ansc; For(a,1,ansp) { cnt[s[a]- a ]=(cnt[s[a]- a ]+1)%K; } For(a,0,25) if(cnt[a]!=0) cnt[a]=K-cnt[a]; int now=n; Fov(a,25,0) { while(cnt[a]--) s[now--]= a +a; } while(now>ansp) s[now--]= a ; printf( %s n ,s+1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_TB_V
`define SKY130_FD_SC_HD__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_TB_V
|
#include <bits/stdc++.h> int n, k, a, b, p, na; std::vector<int> avg; long long f(int l, int r) { auto it1 = std::upper_bound(avg.begin(), avg.end(), r); auto it2 = std::lower_bound(avg.begin(), avg.end(), l); if (it2 != avg.end()) na = it1 - it2; else na = 0; long long ans; if (na) ans = 1LL * b * na * (r - l + 1); else ans = a; if (na && r != l) ans = std::min(ans, f(l, (l + r) / 2) + f((l + r) / 2 + 1, r)); return ans; } int main() { scanf( %d%d%d%d , &n, &k, &a, &b); for (int i = 0; i < k; i++) { scanf( %d , &p); avg.push_back(p - 1); } std::sort(avg.begin(), avg.end()); printf( %lld n , f(0, (1 << n) - 1)); return 0; } |
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bigasfuckram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module bigasfuckram (
address,
clock,
data,
wren,
q);
input [4:0] address;
input clock;
input [26:0] data;
input wren;
output [26:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "27"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 27 0 INPUT NODEFVAL "data[26..0]"
// Retrieval info: USED_PORT: q 0 0 27 0 OUTPUT NODEFVAL "q[26..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 27 0 data 0 0 27 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 27 0 @q_a 0 0 27 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, m, A, B, inf = 1e9, f[110][110], x, y, K, g[110][110], Cnt[110], d[110][110]; bool vis[110][110], V[110][110], Must[110][110]; vector<int> E1[110], E2[110], E[110][110]; queue<pair<int, int> > h; void read(int &x) { char ch = getchar(); int mark = 1; for (; ch != - && (ch < 0 || ch > 9 ); ch = getchar()) ; if (ch == - ) mark = -1, ch = getchar(); for (x = 0; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 48; x *= mark; } int main() { read(n); read(m); read(A); read(B); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) f[i][j] = f[j][i] = inf; for (int i = 1; i <= m; i++) { read(x); read(y); f[x][y] = 1; E1[x].push_back(y); E2[y].push_back(x); } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) f[i][j] = min(f[i][j], f[i][k] + f[k][j]); read(K); for (int i = 1; i <= K; i++) { read(x); read(y); int dis = f[x][y]; if (dis == inf) continue; memset(Cnt, 0, sizeof(Cnt)); for (int j = 1; j <= n; j++) if (f[x][j] + f[j][y] == dis) { V[i][j] = 1; Cnt[f[x][j]]++; for (int k = 0; k < E1[j].size(); k++) { int v = E1[j][k]; if (f[x][j] + 1 + f[v][y] == dis) E[i][v].push_back(j), d[i][j]++; } } for (int j = 1; j <= n; j++) if (V[i][j] && Cnt[f[x][j]] == 1) Must[i][j] = 1; } for (int i = 1; i <= K; i++) if (V[i][B]) { vis[B][i] = 1, g[B][i] = 1; h.push(make_pair(B, i)); } for (int _ = 1; _ <= K; _++) { while (h.size()) { pair<int, int> now = h.front(); h.pop(); int u = now.first, x = now.second; for (int i = 0; i < E[x][u].size(); i++) { int v = E[x][u][i]; d[x][v]--; if (d[x][v] == 0 && !vis[v][x]) { vis[v][x] = 1; g[v][x] = g[u][x]; h.push(make_pair(v, x)); } } } for (int i = 1; i <= K; i++) if (vis[A][i] && Must[i][A]) { printf( %d n , _); return 0; } for (int i = 1; i <= n; i++) for (int j = 1; j <= K; j++) if (vis[i][j] && Must[j][i] && g[i][j] == _) { for (int k = 1; k <= K; k++) if (!vis[i][k] && V[k][i]) { g[i][k] = g[i][j] + 1; vis[i][k] = 1; h.push(make_pair(i, k)); } } } printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> t[100000]; int n; int h[100000]; int arr[100000]; double fac[100001]; bool cmp(int a, int b) { return h[a] < h[b]; } void dfs(int cur, int he, int par = -1) { h[cur] = he; for (int i = 0; i < t[cur].size(); i++) { if (t[cur][i] == par) continue; dfs(t[cur][i], he + 1, cur); } } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; t[a - 1].push_back(b - 1); t[b - 1].push_back(a - 1); } dfs(0, 1); for (int i = 0; i < n; i++) arr[i] = i; sort(arr, arr + n, cmp); double ans = 1; fac[0] = 1; fac[1] = 1; for (int i = 2; i <= n; i++) fac[i] = 1.0 / i; for (int i = 1; i < n; i++) { ans = (ans + 1) * fac[h[i]] + ans * (1 - fac[h[i]]); } printf( %.9lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void clear(T &x) { T t; x.swap(t); } template <class T> void miz(T &a, T b) { if (b < a) a = b; } template <class T> void maz(T &a, T b) { if (b > a) a = b; } template <class T> T gcd(T a, T b) { while (b) { a %= b; swap(a, b); } return a; } struct Shoe { int p, i; Shoe() {} Shoe(int p, int i) : p(p), i(i) {} }; struct Customer { int m, f, i; bool operator<(const Customer &q) const { return f < q.f; } }; const int CMAX = 100000; map<int, Shoe> bst; int C; Customer cus[CMAX]; Shoe sa[CMAX], sb[CMAX]; long long dp[CMAX][2][2]; int pd[CMAX][2][2]; void MAZ(int i, int j, int k, long long v1, int v2) { if (v1 > dp[i][j][k]) { dp[i][j][k] = v1; pd[i][j][k] = v2; } } void solve() { int i, j, k; long long x; for (i = C - 1; i >= 0; i--) { for (j = 0; j < 2; j++) { for (k = 0; k < 2; k++) { if (i != C - 1) { if (cus[i + 1].f == cus[i].f) { dp[i][j][k] = dp[i + 1][j][k]; } else if (cus[i + 1].f == cus[i].f + 1) { dp[i][j][k] = dp[i + 1][k][0]; } else { dp[i][j][k] = dp[i + 1][0][0]; } } if (!j && cus[i].m >= sa[i].p) { if (i == C - 1) { x = 0; } else if (cus[i + 1].f == cus[i].f) { x = dp[i + 1][1][k]; } else if (cus[i + 1].f == cus[i].f + 1) { x = dp[i + 1][k][0]; } else { x = dp[i + 1][0][0]; } MAZ(i, j, k, sa[i].p + x, 1); } if (!k && cus[i].m >= sb[i].p) { if (i == C - 1) { x = 0; } else if (cus[i + 1].f == cus[i].f) { x = dp[i + 1][j][1]; } else if (cus[i + 1].f == cus[i].f + 1) { x = dp[i + 1][1][0]; } else { x = dp[i + 1][0][0]; } MAZ(i, j, k, sb[i].p + x, 2); } } } } printf( %I64d n , dp[0][0][0]); vector<pair<int, int> > ans; i = 0; j = 0; k = 0; while (1) { if (pd[i][j][k] == 0) { if (i == C - 1) { break; } else if (cus[i + 1].f == cus[i].f) { i++; } else if (cus[i + 1].f == cus[i].f + 1) { i++; j = k; k = 0; } else { i++; j = 0; k = 0; } } else if (pd[i][j][k] == 1) { ans.push_back(make_pair(cus[i].i, sa[i].i)); if (i == C - 1) { break; } else if (cus[i + 1].f == cus[i].f) { i++; j = 1; } else if (cus[i + 1].f == cus[i].f + 1) { i++; j = k; k = 0; } else { i++; j = 0; k = 0; } } else if (pd[i][j][k] == 2) { ans.push_back(make_pair(cus[i].i, sb[i].i)); if (i == C - 1) { break; } else if (cus[i + 1].f == cus[i].f) { i++; k = 1; } else if (cus[i + 1].f == cus[i].f + 1) { i++; j = 1; k = 0; } else { i++; j = 0; k = 0; } } } printf( %d n , ans.size()); for (i = 0; i < ans.size(); i++) printf( %d %d n , ans[i].first, ans[i].second); } void GetShoe(int s, Shoe &shoe) { map<int, Shoe>::iterator it; it = bst.find(s); shoe = (it != bst.end() ? it->second : Shoe(INT_MAX, -1)); } void input() { int S, i; scanf( %d , &S); for (i = 1; i <= S; i++) { int p, s; scanf( %d%d , &p, &s); bst.insert(make_pair(s, Shoe(p, i))); } scanf( %d , &C); for (i = 0; i < C; i++) { scanf( %d%d , &cus[i].m, &cus[i].f); cus[i].i = i + 1; } sort(cus, cus + C); for (i = 0; i < C; i++) { GetShoe(cus[i].f, sa[i]); GetShoe(cus[i].f + 1, sb[i]); } } int main() { input(); solve(); return 0; } |
#include <bits/stdc++.h> using ll = long long; using namespace std; int main() { cin.tie(0); ios_base::sync_with_stdio(false); int n, m; char c; cin >> n >> m >> c; vector<string> vec(n); for (int i = 0; i < n; ++i) { cin >> vec[i]; } unordered_set<char> s; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (vec[i][j] == c) { if (i - 1 >= 0 && vec[i - 1][j] != . && vec[i - 1][j] != c) { s.insert(vec[i - 1][j]); } if (j - 1 >= 0 && vec[i][j - 1] != . && vec[i][j - 1] != c) { s.insert(vec[i][j - 1]); } if (i + 1 < n && vec[i + 1][j] != . && vec[i + 1][j] != c) { s.insert(vec[i + 1][j]); } if (j + 1 < m && vec[i][j + 1] != . && vec[i][j + 1] != c) { s.insert(vec[i][j + 1]); } } } } cout << s.size() << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; set<int> E[100005]; vector<int> L[100005]; int True = 0; int vst[100005]; int main() { int n, m, h, t, i, u, v, _h, _t, j, k; cin >> n >> m >> h >> t; for (i = 0; i < (m); i++) { scanf( %d%d , &u, &v); L[u].push_back(v); L[v].push_back(u); E[u].insert(v); E[v].insert(u); } for (i = (1); i <= (n); i++) { u = i; if (((int)(E[u]).size()) < h + 1) continue; for (j = 0; j < (((int)(L[i]).size())); j++) { v = L[i][j]; if (((int)(E[u]).size()) + ((int)(E[v]).size()) < h + t + 2) continue; if (((int)(E[v]).size()) < t + 1) continue; bool sp = 0; if (((int)(E[u]).size()) > ((int)(E[v]).size())) { swap(u, v); sp = 1; } set<int>::iterator it = E[u].begin(); _h = 0; vector<int> cmn; True++; for (k = 0; k < (((int)(L[u]).size())); k++) vst[L[u][k]] = True; for (k = 0; k < (((int)(L[v]).size())); k++) { if (vst[L[v][k]] == True) { _h++; cmn.push_back(L[v][k]); } } if (sp) swap(u, v); if (((int)(E[u]).size()) + ((int)(E[v]).size()) - _h < h + t + 2) continue; printf( YES n ); printf( %d %d n , u, v); it = E[u].begin(); while (it != E[u].end()) { if (E[v].find(*it) == E[v].end()) { if (*it == v) { it++; continue; } h--; printf( %d , *it); } if (!h) break; it++; } while (h--) { printf( %d , cmn[((int)(cmn).size()) - 1]); cmn.pop_back(); } printf( n ); it = E[v].begin(); while (it != E[v].end()) { if ((E[u].find(*it) == E[u].end())) { if (*it == u) { it++; continue; } t--; printf( %d , *it); } if (!t) break; it++; } while (t--) { printf( %d , cmn[((int)(cmn).size()) - 1]); cmn.pop_back(); } printf( n ); return 0; } } printf( NO n ); return 0; } |
module top
(
input gnd
);
wire CAPTURE;
wire UPDATE;
wire DRCK1;
wire TDI;
wire TDO1;
wire CSB;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
wire MISO;
wire MOSI = TDI;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst
(
.CAPTURE(CAPTURE),
.DRCK1(DRCK1),
.DRCK2(),
.RESET(RESET),
.SEL1(SEL1),
.SEL2(),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO1(TDO1),
.TDO2(1'b0)
);
SPI_ACCESS
#(.SIM_DEVICE("3S50AN")
)
SPI_ACCESS_inst
(
.MISO(MISO),
.CLK(DRCK1),
.CSB(CSB),
.MOSI(MOSI)
);
`include "bscan_common.v"
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3, MOD = (1e9) + 7; int n, m, k, A[N + 9][N + 9], row[N + 9], col[N + 9], x, y; char c; void init() { for (int i = 0; i < N + 5; ++i) row[i] = col[i] = i; } int main() { scanf( %d%d%d , &n, &m, &k); init(); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) scanf( %d , &A[i][j]); } for (int i = 0; i < k; ++i) { cin.ignore(); scanf( %c %d %d , &c, &x, &y); switch (c) { case c : swap(col[x], col[y]); break; case r : swap(row[x], row[y]); break; case g : printf( %d n , A[row[x]][col[y]]); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_SYMBOL_V
`define SKY130_FD_SC_MS__BUF_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<pair<int, int> > v(n); multiset<int> l, r; for (int i = 0; i < n; i++) { scanf( %d%d , &v[i].first, &v[i].second); l.insert(v[i].first); r.insert(v[i].second); } int ans = 0; for (int i = 0; i < n; i++) { l.erase(l.find(v[i].first)); r.erase(r.find(v[i].second)); ans = max(ans, *r.begin() - *--l.end()); l.insert(v[i].first); r.insert(v[i].second); } printf( %d n , ans); return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 32041 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8,
w9,
w32768,
w32777,
w288,
w33065,
w1024,
w32041;
assign w1 = i_data0;
assign w1024 = w1 << 10;
assign w288 = w9 << 5;
assign w32041 = w33065 - w1024;
assign w32768 = w1 << 15;
assign w32777 = w9 + w32768;
assign w33065 = w32777 + w288;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign o_data0 = w32041;
//multiplier_block area estimate = 6622.86247982941;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2 * 300000 + 1000; int block[maxN], start[maxN], fin[maxN]; int main() { ios::sync_with_stdio(0); ; int n, m; cin >> n >> m; string s; cin >> s; set<int> st; st.insert(-1); st.insert(n); for (int i = 0; i < n; i++) { if (s[i] != . ) st.insert(i); } int f = 0; int cur = 0; for (int i = 0; i < n; i++) { if (s[i] == . ) cur++; else { if (cur) f += cur - 1; cur = 0; } } if (cur) f += cur - 1; while (m--) { int pos; char c; cin >> pos >> c; pos--; if (c == . ) { auto left = st.lower_bound(pos); if (*left != pos) { cout << f << n ; continue; } left--; int l = *left; int r = *st.upper_bound(pos); int sub = r - pos - 2; if (sub > 0) f -= sub; sub = pos - l - 2; if (sub > 0) f -= sub; st.erase(pos); sub = r - l - 2; if (sub > 0) f += sub; } else { auto left = st.lower_bound(pos); if (*left == pos) { cout << f << n ; continue; } left--; int l = *left; int r = *st.lower_bound(pos); int sub = r - l - 2; f -= sub; sub = pos - l - 2; if (sub > 0) f += sub; sub = r - pos - 2; if (sub > 0) f += sub; st.insert(pos); } cout << f << n ; } } |
module step_ex_ts(clk, rst_, ena_, rdy_,
mode, r0_dout,
fl_din, fl_dout, fl_we_);
input clk;
input rst_;
input ena_;
output rdy_;
input[1:0] mode;
input[7:0] r0_dout;
output[7:0] fl_din;
input[7:0] fl_dout;
output fl_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
wire result = mode[1] ? mode[0] ? r0_dout[7] : r0_dout != 8'b0 : r0_dout[0];
reg fl_din_en;
assign fl_din = fl_din_en ? {fl_dout[7:1], result} : 8'bZ;
reg fl_we_en;
assign fl_we_ = fl_we_en ? 1'b0 : 1'bZ;
reg state;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
state <= 0;
end else if(!ena_) begin
rdy_en <= 0;
fl_din_en <= 1;
fl_we_en <= 0;
state <= 1;
end else if(state) begin
rdy_en <= 1;
fl_din_en <= 1;
fl_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_4_V
`define SKY130_FD_SC_MS__O2111AI_4_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111ai_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_4_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_to_stream (
// Inputs
clk,
reset,
stream_ready,
master_readdata,
master_readdatavalid,
master_waitrequest,
reading_first_pixel_in_frame,
reading_last_pixel_in_frame,
// Bidirectional
// Outputs
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_arbiterlock,
master_read,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input stream_ready;
input [MDW:0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input reading_first_pixel_in_frame;
input reading_last_pixel_in_frame;
// Bidirectional
// Outputs
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
output master_arbiterlock;
output master_read;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam STATE_0_IDLE = 2'h0,
STATE_1_WAIT_FOR_LAST_PIXEL = 2'h1,
STATE_2_READ_BUFFER = 2'h2,
STATE_3_MAX_PENDING_READS_STALL = 2'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW+2):0] fifo_data_in;
wire fifo_read;
wire fifo_write;
wire [(DW+2):0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_almost_empty;
wire fifo_almost_full;
// Internal Registers
reg [ 3: 0] pending_reads;
reg startofpacket;
// State Machine Registers
reg [ 1: 0] s_dma_to_stream;
reg [ 1: 0] ns_dma_to_stream;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
s_dma_to_stream <= STATE_0_IDLE;
else
s_dma_to_stream <= ns_dma_to_stream;
end
always @(*)
begin
case (s_dma_to_stream)
STATE_0_IDLE:
begin
if (reset)
ns_dma_to_stream = STATE_0_IDLE;
else if (fifo_almost_empty)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else
ns_dma_to_stream = STATE_0_IDLE;
end
STATE_1_WAIT_FOR_LAST_PIXEL:
begin
if (pending_reads == 4'h0)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
end
STATE_2_READ_BUFFER:
begin
if (~master_waitrequest)
begin
if (reading_last_pixel_in_frame)
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else if (pending_reads >= 4'hC)
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
STATE_3_MAX_PENDING_READS_STALL:
begin
if (pending_reads <= 4'h7)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
end
default:
begin
ns_dma_to_stream = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
pending_reads <= 4'h0;
else if (master_read & ~master_waitrequest)
begin
if (~master_readdatavalid)
pending_reads <= pending_reads + 1'h1;
end
else if (master_readdatavalid & (pending_reads != 4'h0))
pending_reads <= pending_reads - 1'h1;
end
always @(posedge clk)
begin
if (reset)
startofpacket <= 1'b0;
else if ((s_dma_to_stream == STATE_0_IDLE) & (reading_first_pixel_in_frame))
startofpacket <= 1'b1;
else if (master_readdatavalid)
startofpacket <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_data = fifo_data_out[DW:0];
assign stream_startofpacket = fifo_data_out[DW+1];
assign stream_endofpacket = fifo_data_out[DW+2];
assign stream_empty = 'h0;
assign stream_valid = ~fifo_empty;
assign master_arbiterlock = !((s_dma_to_stream == STATE_2_READ_BUFFER) |
(s_dma_to_stream == STATE_3_MAX_PENDING_READS_STALL));
assign master_read = (s_dma_to_stream == STATE_2_READ_BUFFER);
assign inc_address = master_read & ~master_waitrequest;
assign reset_address = inc_address & reading_last_pixel_in_frame;
// Internal Assignments
assign fifo_data_in[DW:0] = master_readdata[DW:0];
assign fifo_data_in[DW+1] = startofpacket;
assign fifo_data_in[DW+2] = (s_dma_to_stream == STATE_1_WAIT_FOR_LAST_PIXEL) &
(pending_reads == 4'h1);
assign fifo_write = master_readdatavalid & ~fifo_full;
assign fifo_read = stream_ready & stream_valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Image_Buffer (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_empty (fifo_almost_empty),
.almost_full (fifo_almost_full),
// synopsys translate_off
.aclr (),
.usedw ()
// synopsys translate_on
);
defparam
Image_Buffer.add_ram_output_register = "OFF",
Image_Buffer.almost_empty_value = 32,
Image_Buffer.almost_full_value = 96,
Image_Buffer.intended_device_family = "Cyclone II",
Image_Buffer.lpm_numwords = 128,
Image_Buffer.lpm_showahead = "ON",
Image_Buffer.lpm_type = "scfifo",
Image_Buffer.lpm_width = DW + 3,
Image_Buffer.lpm_widthu = 7,
Image_Buffer.overflow_checking = "OFF",
Image_Buffer.underflow_checking = "OFF",
Image_Buffer.use_eab = "ON";
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module halfband_tb( ) ;
// Parameters for instantiation
parameter clocks = 2 ; // Number of clocks per input
parameter decim = 0 ; // Sets the filter to decimate
parameter rate = 2 ; // Sets the decimation rate
reg clock ;
reg reset ;
reg enable ;
reg strobe_in ;
reg signed [17:0] data_in ;
wire strobe_out ;
wire signed [17:0] data_out ;
// Setup the clock
initial clock = 1'b0 ;
always #5 clock <= ~clock ;
// Come out of reset after a while
initial reset = 1'b1 ;
initial #100 reset = 1'b0 ;
// Enable the entire system
initial enable = 1'b1 ;
// Instantiate UUT
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
integer i, ri, ro, infile, outfile ;
// Setup file IO
initial begin
infile = $fopen("input.dat","r") ;
outfile = $fopen("output.dat","r") ;
$timeformat(-9, 2, " ns", 10) ;
end
reg endofsim ;
reg signed [17:0] compare ;
integer noe ;
initial noe = 0 ;
initial begin
// Initialize inputs
strobe_in <= 1'd0 ;
data_in <= 18'd0 ;
// Wait for reset to go away
@(negedge reset) #0 ;
// While we're still simulating ...
while( !endofsim ) begin
// Write the input from the file or 0 if EOF...
@( posedge clock ) begin
#1 ;
strobe_in <= 1'b1 ;
if( !$feof(infile) )
ri = $fscanf( infile, "%d", data_in ) ;
else
data_in <= 18'd0 ;
end
// Clocked in - set the strobe to 0 if the number of
// clocks per sample is greater than 1
if( clocks > 1 ) begin
@(posedge clock) begin
strobe_in <= 1'b0 ;
end
// Wait for the specified number of cycles
for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
@(posedge clock) #1 ;
end
end
end
// Print out the number of errors that occured
if( noe )
$display( "FAILED: %d errors during simulation", noe ) ;
else
$display( "PASSED: Simulation successful" ) ;
$stop ;
end
// Output comparison of simulated values versus known good values
always @ (posedge clock) begin
if( reset )
endofsim <= 1'b0 ;
else begin
if( !$feof(outfile) ) begin
if( strobe_out ) begin
ro = $fscanf( outfile, "%d\n", compare ) ;
if( compare != data_out ) begin
$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1 ;
end
end
end else begin
// Signal end of simulation when no more outputs
endofsim <= 1'b1 ;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j, k, dances = 0, a[250][2]; cin >> n >> m; dances = m + n - 1; for (i = 0; i < m; i++) { a[i][0] = 1; a[i][1] = i + 1; } k = 2; for (j = i; j < dances; j++) { a[j][0] = k; a[j][1] = 1; k++; } cout << dances << n ; for (i = 0; i < dances; i++) { cout << a[i][0] << << a[i][1] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a = 97, z = 97 + 25, t = n; string s = ; for (int i = 0; i < n; i++) { if (t >= k) { for (int j = 0; j < k; j++) { s += a + j; } i += k; i--; t -= k; } else { s += a; a++; } } cout << s << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`begin_keywords "VAMS-2.3"
module t (/*autoarg*/
// Inputs
clk, in
);
input clk;
input [15:0] in;
wreal aout;
integer cyc = 0;
real vin;
wreal vpass;
through through (.vin, .vpass);
real gnd;
wire out;
within_range within_range (/*AUTOINST*/
// Interfaces
.vpass (vpass),
.gnd (gnd),
// Outputs
.out (out));
// wreal bus declaration
wreal vin_upper_bus[1:0];
// wreal nets declaration
wreal vout_split_0;
wreal vout_split_1;
wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]),
.vout_split_0(vout_split_0),
.vout_split_1(vout_split_1));
// implicit declaration of wreal
`ifdef VERILATOR
wreal wreal_implicit_net; // implicit declaration of wreal not supported yet
`endif
// verilator lint_off IMPLICIT
first_level first_level(.in(cyc[0]), .out(wreal_implicit_net));
// verilator lint_on IMPLICIT
parameter real lsb = 1;
// verilator lint_off WIDTH
assign aout = $itor(in) * lsb;
// verilator lint_on WIDTH
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n", $time, cyc, out, vin, gnd, within_range.in_int);
`endif
if (cyc==0) begin
// Setup
gnd = 0.0;
vin = 0.2;
end
else if (cyc==2) begin
if (out != 0) $stop;
end
else if (cyc==3) begin
gnd = 0.0;
vin = 0.6;
end
else if (cyc==4) begin
if (out != 1) $stop;
end
else if (cyc==5) begin
gnd = 0.6;
vin = 0.8;
end
else if (cyc==6) begin
if (out != 0) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module through
(input wreal vin,
output wreal vpass);
assign vpass = vin;
endmodule
module within_range
(input wreal vpass,
input wreal gnd,
output out);
parameter real V_MIN = 0.5;
parameter real V_MAX = 10;
wreal in_int = vpass - gnd;
assign out = (V_MIN <= in_int && in_int <= V_MAX);
endmodule
module wreal_bus
(input wreal vin_bus [1:0],
output wreal vout_split_0,
output wreal vout_split_1);
assign vout_split_0 = vin_bus[0];
assign vout_split_1 = vin_bus[1];
endmodule
module first_level
(input in,
`ifdef VERILATOR
output wreal out
`else
output out // Implicity becomes real
`endif
);
second_level second_level(.in(in), .out(out));
endmodule
module second_level(in, out);
input in;
output out;
wreal out;
assign out = in ? 1.23456: 7.8910;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INVKAPWR_BEHAVIORAL_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__invkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_axi_basic_tx.v
// Version : 3.2
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
PCIeGen2x8If128_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
PCIeGen2x8If128_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; using ii = pair<int, int>; using ll = long long; const int N = 1e5 + 5; const int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int a, b; cin >> a >> b; vector<int> ans1, ans2; ll limit = 0; for (; limit * (limit + 1) / 2 <= a + b; limit++) ; cerr << limit << n ; for (int i = --limit; i >= 1; i--) { if (a >= b) ans1.push_back(i), a -= i; else ans2.push_back(i), b -= i; } cout << ans1.size() << n ; for (auto x : ans1) cout << x << ; cout << n ; cout << ans2.size() << n ; for (auto x : ans2) cout << x << ; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (b < a) { a = b; return 1; } return 0; } signed main() { cin.tie(0); ios::sync_with_stdio(false); long long N, K; cin >> N >> K; vector<long long> A(N), sum(N + 1, 0); long long ans = 0; for (long long i = 0; i < N; i++) { cin >> A[i]; ans += A[i]; sum[i + 1] += sum[i] + A[i]; } vector<long long> tmp; for (long long i = (1); i <= (N - 1); ++i) { tmp.push_back(sum[N] - sum[i]); } sort((tmp).rbegin(), (tmp).rend()); for (long long i = 0; i < K - 1; i++) ans += tmp[i]; cout << ans << endl; return 0; } |
#pragma GCC optimize(4) #include<bits/stdc++.h> #define FOR(i,a,b) for(int i=a;i<=b;++i) #define REP(u) for(int i=p[u];i!=-1;i=e[i].nxt) #define ll long long #define rd (rand()<<16^rand()) #define PII pair<int,int> #define pb push_back #define sz(x) (int)(x.size()) #define gc (_p1==_p2&&(_p2=(_p1=_buf)+fread(_buf,1,100000,stdin),_p1==_p2)?EOF:*_p1++) using namespace std; char _buf[100000],*_p1=_buf,*_p2=_buf; inline int gi() { int x=0,f=1;char ch=gc; while(ch> 9 ||ch< 0 ){if(ch== - )f=-1;ch=gc;} while(ch>= 0 &&ch<= 9 ){x=(x<<3)+(x<<1)+(ch^48);ch=gc;} return (f==1)?x:-x; } inline int max(int a,int b){return a>b?a:b;} inline int min(int a,int b){return a<b?a:b;} const int maxn=105; int T,n,m,a[maxn][maxn],sum[maxn*2]; inline void init() { memset(sum,0,sizeof(sum)); } inline void input() { n=gi(),m=gi(); } inline void solve() { FOR(i,1,n)FOR(j,1,m)a[i][j]=gi(); FOR(i,1,n)FOR(j,1,m)sum[i+j]^=a[i][j]; FOR(i,2,n+m)if(sum[i]){printf( Ashish n );return ;} printf( Jeel n ); } int main() { T=gi(); while(T--) { init(); input(); solve(); } return 0; } /// |
#include <bits/stdc++.h> using namespace std; template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(long long &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const long long &x) { printf( %lld , x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.first); putchar( ); _W(x.second); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } int MOD = 1e9 + 7; void ADD(long long &x, long long v) { x = (x + v) % MOD; if (x < 0) x += MOD; } const int SIZE = 210; int AA[SIZE][SIZE], BB[SIZE][SIZE]; int n, m; int col[SIZE], row[SIZE]; void check(int x) { for (int i = 0; i < (m); ++i) { col[i] = (i >= x) ^ AA[0][i]; BB[0][i] = col[i] ^ AA[0][i]; } for (int i = (1); i < (n); ++i) { bool suc = 0; for (int j = 0; j < (2); ++j) { row[i] = AA[i][0] ^ j ^ col[0]; for (int k = 0; k < (m); ++k) { BB[i][k] = AA[i][k] ^ row[i] ^ col[k]; } if (BB[i][0] < BB[i - 1][m - 1]) continue; bool fail = 0; for (int k = (1); k < (m); ++k) { if (BB[i][k] < BB[i][k - 1]) { fail = 1; } } if (fail) continue; suc = 1; break; } if (!suc) return; } W( YES ); for (int i = 0; i < (n); ++i) _W(row[i]); W( ); for (int i = 0; i < (m); ++i) _W(col[i]); W( ); exit(0); } int main() { R(n, m); for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) { R(AA[i][j]); } for (int i = (1); i <= (m); ++i) { check(i); } W( NO ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: David Ariando
//
// Create Date: 22:22:00 01/31/2018
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: TF_CLS_PWM_Interval_Timer.v
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.1
// Description: CLS Scan Rate Timer Timer Testbench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_CLS_Scan_Rate_Timer();
wire SRT_TICK;
reg CLOCK_50;
reg [1:0] RATE_SELECT;
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
initial
begin
RATE_SELECT = 2'h0;
end
CLS_Scan_Rate_Timer
#(
.CLK_RATE_HZ (CLK_RATE_HZ) // Hz
)
uut
(
// Input Signals
.RATE_SELECT (RATE_SELECT),
// Output Signals
.SRT_TICK (SRT_TICK),
// System Signals
.CLK (CLOCK_50)
);
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { char spots[9][9]; for (int i = 0; i < 9; i++) { for (int j = 0; j < 3; j++) { string input; cin >> input; for (int k = 0; k < input.size(); k++) { spots[i][j * 3 + k] = input[k]; } } } int first, second; cin >> first >> second; first--; second--; int targetedFirst = first % 3; int targetedSecond = second % 3; bool changed = false; for (int i = targetedFirst * 3; i < targetedFirst * 3 + 3; i++) { for (int j = targetedSecond * 3; j < targetedSecond * 3 + 3; j++) { if (spots[i][j] == . ) { changed = true; spots[i][j] = ! ; } } } if (changed == false) { for (int i = 0; i < 9; i++) { for (int j = 0; j < 9; j++) { if (spots[i][j] == . ) { spots[i][j] = ! ; } } } } for (int i = 0; i < 9; i++) { for (int j = 0; j < 9; j++) { cout << spots[i][j]; if (j % 3 == 2) { cout << ; } } if (i % 3 == 2 && i != 8) { cout << endl; } cout << endl; } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_gt_rx_valid_filter_7x.v
// Version : 3.2
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:47:11 07/31/2013
// Design Name:
// Module Name: dataRegConvert
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dataRegConvert(
input clk,
input [1:0] sr_bypass,
input signed [12:0] din,
input signed [12:0] offset,
//input [5:0] sr_tap,
input [4:0] sr_tap,
(* keep = "yes" *) output reg signed [13:0] dout = 14'sd0
//output signed [12:0] dout
);
//parameter ADDPIPEREG = 1;
parameter width = 13;
parameter BITFLIP = (13'd0 ^ -13'sd4096); //Generic conversion for correct polarity LVDS signals in offset binary
//`define ADDPIPEREGS
//(* IOB = "true" *) reg signed [width-1:0] data_reg = 13'sd0;
(* IOB = "true" *) reg signed [width-1:0] data_reg = BITFLIP;
//(* shreg_extract = "no" *) reg [5:0] sr_tap_a = 5'd0, sr_tap_b = 5'd0;//, sr_tap_c = 5'd0;
//(* shreg_extract = "no", equivalent_register_removal = "no" *) reg [5:0] sr_tap_b = 6'd0;
//(* shreg_extract = "no" *) reg [5:0] sr_tap_a = 6'd0, sr_tap_b = 6'd0;
//(* shreg_extract = "no" *) reg [4:0] sr_tap_a = 5'd0, sr_tap_b = 5'b0;//, sr_tap_b = 5'd0, sr_tap_c = 5'd0;
`ifdef ADDPIPEREGS reg signed [width-1:0] pipereg = BITFLIP;
`else reg signed [width-1:0] dreg_b = 13'd0;
`endif
//reg signed [width-1:0] dreg_b;
//reg signed [width-1:0] dout;
wire signed [width-1:width-13] data_out;
//(* async_reg = "TRUE" *) reg signed [12:0] offset_a = 13'd0, offset_b = 13'd0;
always @(posedge clk) begin
//sr_tap_a <= sr_tap;
//sr_tap_b <= sr_tap_a;
//sr_tap_c <= sr_tap_b;
//offset_b <= offset_a;
//offset_a <= offset;
data_reg <= din;
`ifdef ADDPIPEREGS begin
pipereg <= data_reg;
//dout <= {~pipereg[width-1], pipereg[width-2:0]};
//dout <= (sr_tap_b[5]) ? (data_out ^ BITFLIP) : (pipereg ^ BITFLIP);
dout <= (sr_bypass[0]) ? (pipereg ^ BITFLIP) : (data_out ^ BITFLIP) + offset;
end
`else
//dout <= {~data_reg[width-1], data_reg[width-2:0]};
//dout <= data_reg ^ BITFLIP;
//dout <= (sr_tap_b[5]) ? (data_out ^ BITFLIP) : (data_reg ^ BITFLIP);
dreg_b <= (sr_bypass[0]) ? (data_reg ^ BITFLIP) : (data_out ^ BITFLIP);// +offset;
dout <= dreg_b + offset;
`endif
//dout <= dreg_b + offset;
end
`ifdef ADDPIPEREGS ShiftReg #(32, BITFLIP) DataInreg(clk, sr_bypass[1], pipereg, sr_tap, data_out);
`else ShiftReg #(32, BITFLIP) DataInreg(clk, sr_bypass[1], data_reg, sr_tap, data_out);
`endif
//assign dout = data_out ^ BITFLIP;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_4_V
`define SKY130_FD_SC_HD__CLKINVLP_4_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinvlp_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinvlp_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 7; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]==0) struct_bg <= '0;
else if (cnt[30:2]==1) struct_bg <= '0;
else if (cnt[30:2]==2) struct_bg <= '0;
else if (cnt[30:2]==3) struct_bg <= '0;
else if (cnt[30:2]==4) struct_bg <= '0;
else if (cnt[30:2]==5) struct_bg <= '0;
else if (cnt[30:2]==6) struct_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_bg <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_bg <= '{e3:6, e2:4, e1:2, e0:0};
// verilator lint_off WIDTH
else if (cnt[30:2]==4) struct_bg <= '{default:13};
else if (cnt[30:2]==5) struct_bg <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_bg <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
// verilator lint_on WIDTH
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_bg !== 15'b0_00_0000_00000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b0_01_0010_00000011) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b1_10_0011_00000100) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b0_10_0100_00000110) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b1_01_1101_00001101) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b1_01_1010_00000001) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_bg !== 15'b1_10_1011_00011100) begin $display("%b", struct_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]==0) struct_lt <= '0;
else if (cnt[30:2]==1) struct_lt <= '0;
else if (cnt[30:2]==2) struct_lt <= '0;
else if (cnt[30:2]==3) struct_lt <= '0;
else if (cnt[30:2]==4) struct_lt <= '0;
else if (cnt[30:2]==5) struct_lt <= '0;
else if (cnt[30:2]==6) struct_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '{0 ,1 , 2, 3};
else if (cnt[30:2]==2) struct_lt <= '{e0:1, e1:2, e2:3, e3:4};
else if (cnt[30:2]==3) struct_lt <= '{e3:6, e2:4, e1:2, e0:0};
// verilator lint_off WIDTH
else if (cnt[30:2]==4) struct_lt <= '{default:13};
else if (cnt[30:2]==5) struct_lt <= '{e2:8'haa, default:1};
else if (cnt[30:2]==6) struct_lt <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3};
// verilator lint_on WIDTH
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]==0) begin if (struct_lt !== 15'b0_00_0000_00000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b0_01_0010_00000011) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b1_10_0011_00000100) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b0_10_0100_00000110) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b1_01_1101_00001101) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b1_01_1010_00000001) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (struct_lt !== 15'b1_10_1011_00011100) begin $display("%b", struct_lt); $stop(); end end
end
endmodule
|
//AYUSH VERMA //********************************************* ********************************* //***************/A ************************** ****** *********///************* //**************//Y ************************ ******** *******///************** //*************///U ********************** ********** **A**///*************** //************///*S* ******************** ************ *M*///**************** //***********/////H ****************** ************** R///***************** //**********///******* **************** **************** E//****************** //*********///********* ************** ****************** V/******************* //************************************* ***************************************** #include<bits//stdc++.h> #define till(condition) while(condition) #define ull unsigned long long int #define ll long long int #define space printf( ) #define nl printf( n ) #define MOD 1000000007 using namespace std; int main() { int t; cin>>t; till(t--) { int n; cin>>n; ll a[100001],want[100001]; ll max=0; ll maxtest=0; for(int i=0;i<n;i++) { cin>>a[i]; if(a[i]>maxtest) { maxtest=a[i]; } } sort(a,a+n,greater<int>()); ll wantsum=0; for(int i=0;i<n;i++) { want[i]=(maxtest-a[i]); wantsum+=(want[i]); } for(int i=0;i<n;i++) { ll temp=a[i],fill; ll tempwantsum=wantsum-want[i]; if(i!=0) { fill=a[0]; } else { fill=a[1]; } ll subs=(n-1)*(temp-fill); if(subs>0) { tempwantsum-=(subs); } // cout<< * <<temp; // nl; if(tempwantsum<=temp) { temp-=(tempwantsum); if(temp%(n-1)!=0) { ll ans=(n-1)-(temp%(n-1)); if(ans>max) { max=ans; } } } else { if((tempwantsum-temp)>max) { max=(tempwantsum-temp); } } // cout<< ** <<max; // nl; } cout<<max; nl; } } |
#include <bits/stdc++.h> using namespace std; int n, m, A[405][405], B[405][405], a[405][405]; char s[405][405]; void Solve() { cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> (s[i] + 1); for (int j = 1; j <= m; ++j) { a[i][j] = s[i][j] - 0 ; } } for (int j = 1; j <= m; ++j) { for (int i = 1; i <= n; ++i) { B[i][j] = B[i - 1][j] + a[i][j]; A[i][j] = A[i - 1][j] + !a[i][j]; } } int ans = n * m; for (int i = 2; i < n; ++i) { for (int j = i + 2; j < n; ++j) { static int s[405], pre[405]; pre[0] = n * m; for (int k = 1; k <= m; ++k) { int w = B[j][k] - B[i - 1][k] + !a[j + 1][k] + !a[i - 1][k]; s[k] = s[k - 1] + w; pre[k] = min(pre[k - 1], A[j][k] - A[i - 1][k] - s[k]); } for (int k = 4; k <= m; ++k) { ans = min(ans, pre[k - 3] + s[k - 1] + A[j][k] - A[i - 1][k]); } } } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; while (T--) Solve(); return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Generic single-channel AXI FIFO
// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.
// Transfers received on the AXI slave port are pushed onto the FIFO.
// FIFO output, when available, is presented on the AXI master port and
// popped when the master port responds (M_READY).
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_fifo
// fifo_gen
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int maxm = 1e5 + 5; const int INF = 0x3f3f3f3f; int main() { int l, p, q; scanf( %d%d%d , &l, &p, &q); printf( %.10lf n , l * 1.0 / (p + q) * 1.0 * p); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_2_V
`define SKY130_FD_SC_HS__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_2 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_2_V
|
/*
IOBUF
Not a primitive?
Looks like it has an OBUFT
Output buffer family:
OBUF
OBUFDS
OBUFT
OBUFTDS
*/
`ifndef ROI
ERROR: must set ROI
`endif
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
`ROI
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi_io_a(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
IOBUF_INTERMDISABLE #(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW"),
.USE_IBUFDISABLE("TRUE")
) IOBUF_INTERMDISABLE_inst (
.O(1'b0),
.IO(1'bz),
.I(dout[8]),
.IBUFDISABLE(1'b0),
.INTERMDISABLE(1'b0),
.T(1'b1));
endmodule
module roi_io_b(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
wire onet;
IOBUF_INTERMDISABLE #(
.DRIVE(12),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW"),
.USE_IBUFDISABLE("FALSE")
) IOBUF_INTERMDISABLE_inst (
.O(onet),
.IO(1'bz),
.I(dout[8]),
.IBUFDISABLE(1'b0),
.INTERMDISABLE(1'b0),
.T(1'b1));
PULLUP PULLUP_inst (
.O(onet)
);
IOBUF_INTERMDISABLE #(
.DRIVE(12),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW"),
.USE_IBUFDISABLE("FALSE")
) i2 (
.O(),
.IO(1'bz),
.I(dout[8]),
.IBUFDISABLE(1'b0),
.INTERMDISABLE(1'b0),
.T(1'b1));
endmodule
/*
For some reason this doesn't diff
Was this optimized out?
ERROR: [Place 30-69] Instance roi/dut/OBUFT (OBUFT) is unplaced after IO placer
ERROR: [Place 30-68] Instance roi/dut/OBUFT (OBUFT) is not placed
*/
/*
module roi_prop_a(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
//(* LOC="D19", KEEP, DONT_TOUCH *)
(* KEEP, DONT_TOUCH *)
IOBUF #(
.DRIVE(8),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
.O(dout[1]),
.I(din[0]),
.T(din[1]));
endmodule
module roi_prop_b(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
//(* LOC="D19", KEEP, DONT_TOUCH *)
(* KEEP, DONT_TOUCH *)
IOBUF #(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
.O(dout[1]),
.I(din[0]),
.T(din[1]));
endmodule
*/
/*
ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1
ERROR: [Place 30-69] Instance roi/dut (OBUFT) is unplaced after IO placer
hmm
Abandoning verilog approach
tcl seems to work well, just use it directly
*/
module roi_prop_a(input clk, input [255:0] din, output [255:0] dout);
(* LOC="D19", KEEP, DONT_TOUCH *)
//(* KEEP, DONT_TOUCH *)
OBUFT #(
.DRIVE(8),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
//.O(dout[1]),
.O(),
.I(din[0]),
.T(din[1]));
endmodule
module roi_prop_b(input clk, input [255:0] din, output [255:0] dout);
(* LOC="D19", KEEP, DONT_TOUCH *)
//(* KEEP, DONT_TOUCH *)
(* KEEP, DONT_TOUCH *)
OBUFT #(
.DRIVE(12),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
//.O(dout[1]),
.O(),
.I(din[0]),
.T(din[1]));
endmodule
|
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