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/*
* main - main loop for grey_counter
*
* This section includes the grey counter and
* adds all necessary support for clocks and resets.
*
* This code was derived from the Demo program provided
* for the Lattice MachX) 2280 Breakout Board which
* blinks the LED's.
* [www.latticesemi.com/breakoutboards]
*
* Due to the hardware configuration the LEDs are
* inverted from what is expected. For example an
* LED that is on actually indicates a 0 instead of a 1.
* This is why the grey code, starting at all zeros,
* has all the LED's on.
*
*/
`include "grey_counter.v"
// 4 bit oscillating LED pattern
module main(rstn, osc_clk, led, clk );
input rstn ;
output osc_clk ;
output wire [7:0] led ;
output clk ;
reg [22:0]c_delay ;
// Reset occurs when argument is active low.
GSR GSR_INST (.GSR(rstn));
OSCC OSCC_1 (.OSC(osc_clk)) ;
grey_counter gc1(clk, led);
// The c_delay counter is used to slow down the internal oscillator (OSC) output
// to a rate of approximately 0.5 Hz
always @(posedge osc_clk or negedge rstn)
begin
if (~rstn)
c_delay <= 32'h0000 ;
else
c_delay <= c_delay + 1 ;
end
assign clk = c_delay[22] ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int mas[15] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47}; int m, n; bool ans = false; cin >> n >> m; for (int i = 0; i < 15; i++) { if (mas[i] == n) { if (mas[i + 1] == m) { ans = true; break; } } } if (ans) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x[100], n, a, b, i, dem = 0; scanf( %d , &n); for (i = 0; i < n - 1; i++) scanf( %d , &x[i]); scanf( %d , &a); scanf( %d , &b); for (i = a - 1; i != b - 1; i++) dem = dem + x[i]; printf( %d , dem); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:47:43 05/19/2015
// Design Name: erosion3x3
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/tb_erosion3x3.v
// Project Name: vision
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: erosion3x3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_erosion3x3(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
// proccessing
reg [7:0] erosion_r;
reg [7:0] erosion_g;
reg [7:0] erosion_b;
wire erosion;
wire erosion_de;
wire erosion_vsync;
wire erosion_hsync;
erosion3x3 #
(
.H_SIZE(10'd83)
)
erode3
(
.clk(rx_pclk),
.ce(1'b1),
.rst(1'b0),
.mask((rx_red == 8'hFF) ? 1'b1 : 1'b0),
.in_de(rx_de),
.in_vsync(rx_vsync),
.in_hsync(rx_hsync),
.eroded(erosion),
.out_de(erosion_de),
.out_vsync(erosion_vsync),
.out_hsync(erosion_hsync)
);
always @(posedge rx_pclk) begin
erosion_r = (erosion) ? 8'hFF : 8'h00;
erosion_g = (erosion) ? 8'hFF : 8'h00;
erosion_b = (erosion) ? 8'hFF : 8'h00;
end
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = erosion_de;
assign tx_hsync = erosion_hsync;
assign tx_vsync = erosion_vsync;
assign tx_red = erosion_r;
assign tx_green = erosion_g;
assign tx_blue = erosion_b;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, c; c = 0; string s; cin >> n >> s; for (int i = 0; i < n; i++) { if (s[i] == 8 ) { c += 1; } } cout << min(n / 11, c); } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int MAXN = 1e6; int solve(int a, int b, int c) { if (b < a) swap(a, b); int dis = b - a; int statr = 1; int all = dis * 2; int res = 0; if (a - dis >= 1 || c > 2 * dis) return -1; if (c > dis) res = c - dis; if (c <= dis) res = c + dis; return res; } int main() { int t; cin >> t; while (t--) { int a, b, c; cin >> a >> b >> c; cout << solve(a, b, c) << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O32AI_BLACKBOX_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_BLACKBOX_V
|
// test_mis.v - Testbench for mis.bvrl
// 01-22-01 E. Brombaugh
/*
* Copyright (c) 2001 Eric Brombaugh <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The mis'' module was generated by the synopsis module compiler
* and is typical of the modules it generates. The testbench was hand
* coded. This file was merged into a single file using the Verilog
* preprocessor.
*/
`timescale 1ns / 10 ps
module mis( y, a, b );
input [3:0] a;
input [3:0] b;
output [12:0] y;
wire dpa_zero, dpa_one;
wire [5:0] const__1_24_;
wire [7:0] C0;
wire [6:0] const__2_33_;
wire [7:0] C1;
wire [12:0] y_1_;
assign dpa_zero= 1024'h0;
assign dpa_one= 1024'h1;
assign const__1_24_=- 1024'h18;
assign const__2_33_=- 1024'h21;
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:5 input signed [3:0] a, b; */
/* mis.mcl:10 C0 = -24; */
assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5)));
/* mis.mcl:11 C1 = -33; */
assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6)));
/* mis.mcl:13 y = C0*a + C1*b; */
assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+
(C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3)));
/* mis.mcl:6 output signed [12:0] y; */
assign y = y_1_[12:0];
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:13 y = C0*a + C1*b; */
/*User Defined Aliases */
endmodule
module test_mis;
reg [10:0] count;
reg clk;
reg [3:0] a, b;
wire [12:0] y;
mis u1(y, a, b);
initial
begin
count = 0;
clk = 0;
a = 0;
b = 0;
end
always
#10 clk = ~clk;
always @(posedge clk)
begin
a = count[3:0];
b = count[7:4];
#10
$display("%h %h %h", a, b, y);
count = count + 1;
if(count == 0)
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; int main() { int T; scanf( %d , &T); while (T--) { ll n, m, ans = 0; scanf( %lld%lld , &n, &m); for (ll k = 1; k <= n / k; k++) { ans += max(0ll, min(n / k - 1, m) - k); } printf( %lld n , ans); } return 0; } /* 1 50 3 */ |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MAXN = 1e6 + 7; const double EPS = 1e-8; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; vector<long long> cnt(m, 0); long long d = n % m; for (long long i = 0; i < m; i++) { cnt[i * i % m] += n / m; if (i && i <= d) { cnt[i * i % m]++; } } long long res = 0; for (long long i = 0; i < m; i++) { res += cnt[i] * cnt[(m - i) % m]; } cout << res; } |
#include <bits/stdc++.h> template <typename T> bool Chkmin(T &x, T y) { return y < x ? x = y, true : false; } template <typename T> bool Chkmax(T &x, T y) { return y > x ? x = y, true : false; } const int MAXN = 1e6 + 1e3, MAXM = MAXN, oo = 0x3f3f3f3f; int n, m, tote, S, T; int head[MAXN], next[MAXM], to[MAXM], dp[MAXN], out[MAXN], pos[MAXN], cur[MAXN]; void AddEdge(int u, int v) { to[++tote] = v; next[tote] = head[u]; head[u] = tote; } void Init() { int u, v; scanf( %d%d , &n, &m); for (int i = 1, _ = m; i <= _; i++) { scanf( %d%d , &u, &v); AddEdge(v, u); out[u]++; } scanf( %d%d , &S, &T); } void Solve() { int u, v, num; std::deque<int> q, p; q.push_front(T); p.push_front(++cur[T]); memset(dp, 0x3f, sizeof(dp)); dp[T] = 0; while (!q.empty()) { u = q.front(); q.pop_front(); num = p.front(); p.pop_front(); if (num != cur[u]) continue; for (int i = head[u]; i; i = next[i]) { v = to[i]; out[v]--; if (out[v] == 0) { if (Chkmin(dp[v], dp[u])) { q.push_front(v); p.push_front(++cur[v]); } } else { if (Chkmin(dp[v], dp[u] + 1)) { q.push_back(v); p.push_front(++cur[v]); } } } } } int main() { Init(); Solve(); if (dp[S] == oo) dp[S] = -1; printf( %d n , dp[S]); } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module tb_norflash16();
reg sys_clk;
reg sys_rst;
reg [31:0] wb_adr_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
wire wb_ack_o;
reg [3:0] wb_sel_i;
wire [21:0] flash_adr;
inout [15:0] flash_d;
reg [15:0] flash_do;
always @(flash_adr) #110 flash_do <= flash_adr[15:0] + 16'b1;
norflash16 dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_sel_i(wb_sel_i),
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n)
);
assign flash_d = flash_oe_n ? 16'bz : flash_do;
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
initial begin
$dumpfile("norflash16.vcd");
$dumpvars(-1, dut);
sys_rst = 1'b1;
sys_clk = 1'b0;
wb_adr_i = 32'h00000000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_sel_i = 4'b1111;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
sys_rst = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_sel_i = 4'b1111;
wbread(32'h0000fff0);
wb_sel_i = 4'b0001;
wbread(32'h0000fff0);
wb_sel_i = 4'b0010;
wbread(32'h0000fff1);
wb_sel_i = 4'b0100;
wbread(32'h0000fff2);
wb_sel_i = 4'b1000;
wbread(32'h0000fff3);
wb_sel_i = 4'b0100;
wbread(32'h0000fff0);
wb_sel_i = 4'b1111;
wbread(32'h00000010);
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wbread(32'h00000040);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; for (int i = 0; i < s.size(); i++) { if (s[i] == t[s.size() - i - 1]) { continue; } else { cout << NO ; return 0; } } cout << YES ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__FA_BEHAVIORAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int nvertices, nedges; vector<vector<pair<int, int>>> adjList(110); vector<bool> visited; void dfs(int u, int c) { visited[u] = true; for (auto e : adjList[u]) { if (!visited[e.first] && (e.second == c)) { dfs(e.first, c); } } } int main() { cin >> nvertices >> nedges; for (int i = 0; i < nedges; i++) { int u, v, c; cin >> u >> v >> c; adjList[u].push_back({v, c}); adjList[v].push_back({u, c}); } int m; cin >> m; while (m--) { int u, v; cin >> u >> v; set<int> ans; for (auto e : adjList[u]) { visited.assign(110, false); visited[u] = true; dfs(e.first, e.second); if (visited[v] == true) ans.insert(e.second); } cout << ans.size() << endl; } return 0; } |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_mulRecFN#(parameter expWidth = 3, parameter sigWidth = 3);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(formatWidth - 1):0] a, b, expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recA, recB, recExpectOut;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_a(a, recA);
fNToRecFN#(expWidth, sigWidth) fNToRecFN_b(b, recB);
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(expectOut, recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
mulRecFN#(expWidth, sigWidth)
mulRecFN(control, recA, recB, roundingMode, recOut, exceptionFlags);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth) sameRecFN(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'mulRecF%0d'", formatWidth);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000,
"%h %h %h %h",
a,
b,
expectOut,
expectExceptionFlags
) == 4
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut || (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'mulRecF%0d', control %H, rounding mode %0d:",
formatWidth,
control,
roundingMode
);
end
$write("%H %H", recA, recB);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$write("=> %H %H", recOut, exceptionFlags);
if (formatWidth > 32) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", recExpectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'mulRecF%0d', control %H, rounding mode %0d.",
count,
formatWidth,
control,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_mulRecF16;
test_mulRecFN#(5, 11) test_mulRecF16();
endmodule
module test_mulRecF32;
test_mulRecFN#(8, 24) test_mulRecF32();
endmodule
module test_mulRecF64;
test_mulRecFN#(11, 53) test_mulRecF64();
endmodule
module test_mulRecF128;
test_mulRecFN#(15, 113) test_mulRecF128();
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long dp[2010][2010]; int a[2010]; int p[2010]; bool used[2010]; bool ok[2010]; int main() { int n; cin >> n; dp[0][0] = 1; int rem = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] != -1) { used[a[i] - 1] = true; rem++; } else p[i] = i - rem + 1; } int cnt = 0; for (int i = 0; i < n; i++) if (used[i]) ok[p[i]] = true; for (int i = 1; i <= n; i++) { dp[i][0] = dp[i - 1][1] + dp[i - 1][0] * (i - 1); if (ok[i]) dp[i][0] += dp[i - 1][0]; dp[i][0] %= 1000000007; for (int j = 1; j <= i; j++) { dp[i][j] = dp[i - 1][j + 1] * (j + 1) + dp[i - 1][j] * (i - 1 - j); if (ok[i]) dp[i][j] += dp[i - 1][j]; else dp[i][j] += dp[i - 1][j - 1]; dp[i][j] %= 1000000007; } } long long ans = 0; for (int j = 0; j <= cnt; j++) ans = (dp[n - rem][j] + ans) % 1000000007; cout << ans << endl; } |
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : ethernet_controller_top.v
// Version : 0.2
// Author : Shreejith S, Vipin K
//
// Description: Ethernet Controller Module Top File
//
//--------------------------------------------------------------------------------
module v7_ethernet_controller_top #(parameter tx_dst_addr = 48'h001F293A10FD,tx_src_addr = 48'hAABBCCDDEEFF,tx_max_data_size = 16'd1024,rx_dst_addr=48'hAABBCCDDEEFF)
(
// asynchronous reset
input glbl_rst,
// 200MHz clock input from board
input clkin200,
output phy_resetn,
//added SGMII serial data and reference clock ports
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// MDIO Interface
//---------------
input mdio_i,
output mdio_o,
output mdio_t,
output mdc,
input enet_loopback,
input enet_wr_clk,
input enet_wr_data_valid, // axi_tvalid
input [63:0] enet_wr_data, // axi_tdata
output enet_wr_rdy, // axi_tready
input enet_rd_clk,
input enet_rd_rdy, // axi_tready
output [63:0] enet_rd_data, // axi_tdata
output reg enet_rd_data_valid, // axi_tvalid
input if_enable,
output o_tx_mac_count
);
wire w_core_ip_clk;
wire w_core_ip_rst_n;
wire [7:0] w_core_ip_data;
wire w_core_ip_data_valid;
wire w_core_ip_data_last;
wire w_ip_core_data_ready;
wire [7:0] w_ip_core_data;
reg ip_core_data_valid;
wire w_core_ip_data_ready;
wire w_ip_core_data_last;
wire [13:0] eth_tx_fifo_data_cnt;
wire [10:0] eth_tx_fifo_wr_data_cnt;
wire [7:0] eth_rx_fifo_rd_data_cnt;
reg [2:0] rd_state;
reg enet_rd_en;
reg [3:0] dat_cnt;
reg tx_fifo_rd;
tx_fifo eth_tx_fifo
(
.rst(glbl_rst), // input rst
.wr_clk(enet_wr_clk), // input wr_clk
.rd_clk(w_core_ip_clk), // input rd_clk
.din(enet_wr_data), // input [63 : 0] din
.wr_en(enet_wr_data_valid & enet_wr_rdy & if_enable), // input wr_en
.rd_en(tx_fifo_rd || w_core_ip_data_ready), // input rd_en
.dout(w_ip_core_data), /// output [7 : 0] dout
.full(tx_full), // output full
.empty(tx_fifo_empty), // output empty
.rd_data_count(eth_tx_fifo_data_cnt), // output [13 : 0] rd_data_count
.wr_data_count(eth_tx_fifo_wr_data_cnt)
);
assign enet_wr_rdy = ((eth_tx_fifo_wr_data_cnt > 2045) || (tx_full)) ? 1'b0 : 1'b1;
reg tx_fif_rd_state;
always @(posedge w_core_ip_clk)
begin
if (~w_core_ip_rst_n) begin
tx_fifo_rd <= 1'b0;
ip_core_data_valid <= 1'b0;
tx_fif_rd_state <= 'd0;
end
else begin
tx_fifo_rd <= 1'b0;
ip_core_data_valid <= 1'b0;
case (tx_fif_rd_state)
1'b0 : begin
if (|eth_tx_fifo_data_cnt) begin
// if (w_core_ip_data_ready) begin
//tx_fifo_rd <= 1'b1;
tx_fif_rd_state <= 1'b1;
ip_core_data_valid <= 1'b1;
// end
end
end
1'b1 : begin
if (w_core_ip_data_ready && (eth_tx_fifo_data_cnt>14'd2)) begin
//tx_fifo_rd <= 1'b1;
tx_fif_rd_state <= 1'b1;
ip_core_data_valid <= 1'b1;
end
else begin
ip_core_data_valid <= 1'b1;
if (tx_fifo_empty) begin
tx_fifo_rd <= 1'b0;
tx_fif_rd_state <= 1'b0;
end
end
end
endcase
end
end
v7_ethernet_controller
#(.tx_dst_addr(tx_dst_addr),
.tx_src_addr(tx_src_addr),
.tx_max_data_size(tx_max_data_size),
.rx_dst_addr(rx_dst_addr))
ec
(
.glbl_rst(glbl_rst),
.clkin200(clkin200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_i),
.mdio_t(mdio_t),
.mdio_o(mdio_o),
.mdc(mdc),
.o_axi_rx_clk(w_core_ip_clk),
.o_axi_rx_rst_n(w_core_ip_rst_n),
.o_axi_rx_tdata(w_core_ip_data),
.o_axi_rx_data_tvalid(w_core_ip_data_valid),
.o_axi_rx_data_tlast(w_core_ip_data_last),
.loop_back_en(enet_loopback),
.i_axi_rx_data_tready(1'b1),
.o_axi_tx_clk(),
.o_axi_tx_rst_n(),
.i_axi_tx_tdata(w_ip_core_data),
.i_axi_tx_data_tvalid(ip_core_data_valid),
.o_axi_tx_data_tready(w_core_ip_data_ready),
.i_axi_tx_data_tlast(1'b0),
.o_tx_mac_count(o_tx_mac_count)
);
wire rx_fifo_rd_en = (enet_rd_en || ((rd_state == 1'b1) && (enet_rd_en || enet_rd_rdy)));
rx_fifo eth_rx_fifo
(
.rst(glbl_rst), // input rst
.wr_clk(w_core_ip_clk), // input wr_clk
.rd_clk(enet_rd_clk), // input rd_clk
.din(w_core_ip_data), // input [7 : 0] din
.wr_en(w_core_ip_data_valid && if_enable), // input wr_en
.rd_en(rx_fifo_rd_en), // input rd_en
.dout(enet_rd_data), // output [63 : 0] dout
.full(), // output full
.empty(), // output empty
.rd_data_count(eth_rx_fifo_rd_data_cnt) // output [7 : 0] rd_data_count
);
always @ (posedge enet_rd_clk)
begin
if (glbl_rst) begin
enet_rd_data_valid <= 1'b0;
rd_state <= 2'd0;
enet_rd_en <= 1'b0;
dat_cnt <= 'd0;
end
else begin
enet_rd_en <= 1'b0;
case (rd_state)
2'd0 : begin
if (eth_rx_fifo_rd_data_cnt >= 8) begin
enet_rd_en <= 1'b1;
rd_state <= 2'd1;
if (enet_rd_rdy)
dat_cnt <= 4'd0;
else
dat_cnt <= 4'd1;
end
end
2'd1 : begin
enet_rd_data_valid <= 1'b1;
if (enet_rd_rdy) begin
enet_rd_en <= 1'b1;
dat_cnt <= dat_cnt + 1'b1;
end
else
enet_rd_en <= 1'b0;
if (dat_cnt == 8) begin
enet_rd_data_valid <= 1'b0;
enet_rd_en <= 1'b0;
rd_state <= 2'd2;
end
end
2'd2 : begin
rd_state <= 2'd0;
end
endcase
end
end
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/25/2009
Version 1.0
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
generate
if (BURST_ENABLE == 1)
begin
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
/*************************************************************************
* This file is part of Stierlitz: *
* https://github.com/asciilifeform/Stierlitz *
*************************************************************************/
/*************************************************************************
* (c) Copyright 2012 Stanislav Datskovskiy *
* http://www.loper-os.org *
**************************************************************************
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
* *
*************************************************************************/
`include "stierlitz.v"
`include "infer-sram.v"
module stierlitz_demo_top
(sys_clk, /* 100MHz main clock line */
sys_rst_pin, /* Master reset */
/************* Cypress CY7C67300 *************/
sace_usb_a, /* CY HPI Address bus (two bits) */
sace_usb_d, /* CY HPI Data bus */
sace_usb_oen, /* CY HPI nRD */
sace_usb_wen, /* CY HPI nWR */
usb_csn, /* CY HPI nCS */
usb_hpi_reset_n, /* CY HPI nRESET */
usb_hpi_int, /* CY HPI INT */
/*********************************************/
sace_mpce, /* Xilinx ACE nCS */
/*********************************************/
CBUTTON, /* Center Button */
EBUTTON, /* East Button */
/*********************************************/
led_byte /* LED bank, 8 bits wide */
);
/* The basics */
input wire sys_clk;
input wire sys_rst_pin;
input wire CBUTTON; /* These buttons are active-high */
input wire EBUTTON;
output wire [7:0] led_byte;
/* Xilinx ACE - must be disabled for Cypress CY to work */
output wire sace_mpce;
/* CY7C67300 */
output wire sace_usb_oen;
output wire sace_usb_wen;
output wire usb_csn;
input wire usb_hpi_int;
output wire [6:0] sace_usb_a;
inout wire [15:0] sace_usb_d;
output wire usb_hpi_reset_n;
wire [1:0] usb_addr;
assign sace_usb_a[2:1] = usb_addr[1:0];
assign sace_usb_a[0] = 1'bz;
assign sace_usb_a[6:3] = 4'bz;
/* CY manual reset */
wire usbreset = CBUTTON | ~sys_rst_pin; /* tie rst to main rst */
// assign usb_hpi_reset_n = ~usbreset;
/* Ideally, 16 MHz (x2) clock for HPI interface */
wire hpi_clock;
/* A bit OC's, ok. */
reg [1:0] clkdiv;
always @(posedge sys_clk, posedge usbreset)
if (usbreset)
begin
clkdiv <= 0;
end
else
begin
clkdiv <= clkdiv + 1;
end
assign hpi_clock = clkdiv[1];
// DCM_BASE hpi_clock_dcm (.CLKIN(sys_clk),
// .CLKFX(hpi_clock),
// .RST(sys_rst_pin)
// );
// defparam hpi_clock_dcm.CLK_FEEDBACK = "NONE";
// defparam hpi_clock_dcm.CLKFX_MULTIPLY = 4;
// defparam hpi_clock_dcm.CLKFX_DIVIDE = 25;
assign sace_mpce = 1; /* Switch off ACE to free the bus it shares with CY */
wire hpi_manual_test = EBUTTON; /* temporary manual toggle to run tester */
wire usb_irq = usb_hpi_int; /* HPI IRQ is active-high */
wire sbus_ready;
wire sbus_rw;
wire sbus_start_op;
wire [40:0] sbus_address;
wire [7:0] sbus_data;
assign sbus_ready = 1;
assign led_byte = sbus_address[16:9];
stierlitz s(.clk(hpi_clock),
.reset(usbreset),
.enable(1'b1),
/* Control wiring */
.bus_ready(sbus_ready),
.bus_address(sbus_address),
.bus_data(sbus_data),
.bus_rw(sbus_rw),
.bus_start_op(sbus_start_op),
/* CY7C67300 connections */
.cy_hpi_address(usb_addr),
.cy_hpi_data(sace_usb_d),
.cy_hpi_oen(sace_usb_oen),
.cy_hpi_wen(sace_usb_wen),
.cy_hpi_csn(usb_csn),
.cy_hpi_irq(usb_hpi_int),
.cy_hpi_resetn(usb_hpi_reset_n)
);
// reg [7:0] test;
// wire [7:0] test;
// assign sbus_data = sbus_rw ? test : 8'bz;
// always @(posedge sys_clk)
// begin
// case (sbus_address[1:0])
// 2'b00:
// test <= sbus_address[16:9];
// 2'b01:
// test <= sbus_address[24:17];
// 2'b10:
// test <= sbus_address[32:25];
// 2'b11:
// test <= sbus_address[40:33];
// endcase // case (sbus_address[1:0])
// end
wire ram_we;
wire ram_oe;
assign ram_we = (~sbus_rw) & sbus_start_op;
assign ram_oe = sbus_rw & sbus_start_op;
infer_sram #(17, 8, 131072)
ram(.clk(sys_clk),
.we(ram_we),
.oe(ram_oe),
.address(sbus_address[16:0]),
.data(sbus_data)
);
endmodule
|
/*
* File: top_pss.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* top module for pippo sub-system, includes
* pippo core, imc, dmc, icbu, dcbu
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module top_pss(
clk, rst,
txd, rxd,
dsu_rst,
dsu_burn_enable,
dsu_sram_we,
iimx_adr_o,
iimx_rqt_o,
iimx_rty_i,
iimx_ack_i,
iimx_err_i,
iimx_dat_i,
iimx_adr_i,
dimx_adr_o,
dimx_rqt_o,
dimx_we_o,
dimx_sel_o,
dimx_dat_o,
dimx_dat_i,
dimx_ack_i,
dimx_err_i
);
//
// I/O
//
input clk;
input rst;
input dsu_rst;
input dsu_burn_enable;
output dsu_sram_we;
output txd;
input rxd;
output [31:0] iimx_adr_o;
output iimx_rqt_o;
output [31:0] iimx_dat_i;
output iimx_ack_i;
output iimx_rty_i;
output iimx_err_i;
output [31:0] iimx_adr_i;
output [31:0] dimx_adr_o;
output dimx_rqt_o;
output dimx_we_o;
output [3:0] dimx_sel_o;
output [31:0] dimx_dat_o;
output [31:0] dimx_dat_i;
output dimx_ack_i;
output dimx_err_i;
//
// interconnections
//
wire [31:0] iimx_adr_o;
wire iimx_rqt_o;
wire [31:0] iimx_dat_i;
wire iimx_ack_i;
wire iimx_rty_i;
wire iimx_err_i;
wire [31:0] iimx_adr_i;
wire [31:0] dimx_adr_o;
wire dimx_rqt_o;
wire dimx_we_o;
wire [3:0] dimx_sel_o;
wire [31:0] dimx_dat_o;
wire [31:0] dimx_dat_i;
wire dimx_ack_i;
wire dimx_err_i;
wire [31:0] dsu_sram_data;
wire [`IOCM_Word_BW-1:0] dsu_sram_addr;
//
// pippo_core
//
pippo_core pippo_core(
.clk(clk),
.rst(rst),
.iimx_adr_o(iimx_adr_o),
.iimx_rqt_o(iimx_rqt_o),
.iimx_rty_i(iimx_rty_i),
.iimx_ack_i(iimx_ack_i),
.iimx_err_i(iimx_err_i),
.iimx_dat_i(iimx_dat_i),
.iimx_adr_i(iimx_adr_i),
.dimx_adr_o(dimx_adr_o),
.dimx_rqt_o(dimx_rqt_o),
.dimx_we_o(dimx_we_o),
.dimx_sel_o(dimx_sel_o),
.dimx_dat_o(dimx_dat_o),
.dimx_dat_i(dimx_dat_i),
.dimx_ack_i(dimx_ack_i),
.dimx_err_i(dimx_err_i),
.sig_ext_ci(1'b0),
.sig_ext_i(1'b0),
.rqt_core_rst(rqt_core_rst),
.rqt_sys_rst(rqt_sys_rst),
.rqt_chip_rst(rqt_chip_rst),
.txd(txd),
.rxd(rxd),
.dsu_rst(dsu_rst),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_ce(dsu_sram_ce),
.dsu_sram_we(dsu_sram_we),
.dsu_sram_addr(dsu_sram_addr),
.dsu_sram_data(dsu_sram_data)
);
//
// IMX unified memory controller
//
imx_umc imx_umc(
.clk(clk),
.rst(rst),
.iimx_adr_i(iimx_adr_o),
.iimx_rqt_i(iimx_rqt_o),
.iimx_rty_o(iimx_rty_i),
.iimx_ack_o(iimx_ack_i),
.iimx_err_o(iimx_err_i),
.iimx_dat_o(iimx_dat_i),
.iimx_adr_o(iimx_adr_i),
// .lsuimc_adr_i(dimx_adr_o),
// .lsuimc_rqt_i(dimx_rqt_o),
// .lsuimc_we_i(dimx_we_o),
// .lsuimc_dat_i(dimx_dat_o),
// .lsuimc_sel_i(dimx_sel_o),
// .imclsu_dat_o(imclsu_dat_o),
// .imclsu_ack_o(imclsu_ack_o),
// .imclsu_err_o(imclsu_err_o),
.dimx_adr_i(dimx_adr_o),
.dimx_rqt_i(dimx_rqt_o),
.dimx_we_i(dimx_we_o),
.dimx_dat_i(dimx_dat_o),
.dimx_sel_i(dimx_sel_o),
.dimx_dat_o(dimx_dat_i),
.dimx_ack_o(dimx_ack_i),
.dimx_err_o(dimx_err_i),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_ce(dsu_sram_ce),
.dsu_sram_we(dsu_sram_we),
.dsu_sram_addr(dsu_sram_addr),
.dsu_sram_data(dsu_sram_data)
);
//
// i-side cbu
//
//
// d-side cbu
//
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); puts( Even ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; struct pos { long long int x; long long int h; int indx; int sum; } p[100005]; bool cmp(pos a, pos b) { return a.x < b.x; } bool cmp2(pos a, pos b) { return a.indx < b.indx; } int bs(long long int key) { int l = 0; int r = n; int mid; while (l <= r) { mid = (l + r) / 2; if (p[mid].x == key) { return mid; } else if (p[mid].x < key) { l = mid + 1; } else { r = mid - 1; } } } int main() { scanf( %d , &n); long long int ar[n + 5]; for (int i = 0; i < n; i++) { scanf( %lld%lld , &p[i].x, &p[i].h); p[i].indx = i; p[i].sum = 1; } sort(p, p + n, cmp); p[n - 1].sum = 1; for (int i = n - 2; i >= 0; i--) { long long int val = p[i].h + p[i].x; int poscnt = 1; while (val > p[i + poscnt].x && poscnt + i < n) { p[i].sum += p[poscnt + i].sum; poscnt += p[poscnt + i].sum; } } sort(p, p + n, cmp2); for (int i = 0; i < n; i++) { printf( %d , p[i].sum); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100001], n; inline long long sum(int t) { long long s = 0; for (int i = 1; i <= n; ++i) s += min(a[i], t); return s; } int main() { int i, j, l, r, m, t = 1; int nr = 0; long long k, s = 0, smin; scanf( %d %I64d , &n, &k); for (i = 1; i <= n; ++i) { scanf( %d , &a[i]); s += a[i]; } if (s < k) printf( -1 ); else if (s == k) printf( ); else { l = 0; r = 1000000000; while (l + 1 < r) { m = (l + r) >> 1; if (sum(m) <= k) l = m; else r = m; } k -= sum(l); if (s == k) printf( ); else { for (i = 1; i <= n; ++i) { if (k == 0) break; if (a[i] > l) { --k; --a[i]; } } for (j = i; j <= n; ++j) if (a[j] > l) printf( %d , j); for (j = 1; j < i; ++j) if (a[j] > l) printf( %d , j); } } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T f = 0, x = 0; char c = getchar(); while (!isdigit(c)) f = c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 48, c = getchar(); return f ? -x : x; } namespace run { const int mod = 998244353, N = 1 << 16, inv2 = (mod + 1) / 2; inline int add(int x, int y) { return x + y >= mod ? x - mod + y : x + y; } inline int sub(int x, int y) { return x >= y ? x - y : x + mod - y; } inline int qpow(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = 1LL * x * ret % mod; x = 1LL * x * x % mod, y >>= 1; } return ret; } int inv[17], fac[17], ifac[17]; inline void Getln(int *a, int *b, int len) { assert(a[0] == 1), b[0] = 0; for (int i = 0; i < len - 1; i++) { int sum = 1LL * a[i + 1] * (i + 1) % mod; for (int j = 0; j < i; j++) sum = sub(sum, 1LL * a[i - j] * (j + 1) % mod * b[j + 1] % mod); b[i + 1] = 1LL * sum * inv[i + 1] % mod; } } inline void Getexp(int *a, int *b, int len) { assert(a[0] == 0), b[0] = 1; for (int i = 0; i < len - 1; i++) { b[i + 1] = 0; for (int j = 0; j <= i; j++) b[i + 1] = (1LL * (j + 1) * a[j + 1] % mod * b[i - j] + b[i + 1]) % mod; b[i + 1] = 1LL * inv[i + 1] * b[i + 1] % mod; } } inline void fwt_xor(int *a, int inv, int limit) { for (int mid = 1; mid < limit; mid <<= 1) for (int i = 0; i < limit; i += (mid << 1)) for (int j = 0; j < mid; j++) { int x = a[i + j], y = a[i + j + mid]; if (inv == -1) x = 1LL * inv2 * x % mod, y = 1LL * inv2 * y % mod; a[i + j] = add(x, y), a[i + j + mid] = sub(x, y); } } int a[N], n, f[N], K, C, vis[N]; map<vector<int>, int> mp; vector<int> st[209]; int count[N], tot, top, num[209], r[209], A[209]; int main() { n = read<int>(), K = read<int>(), C = read<int>(); inv[0] = inv[1] = fac[0] = ifac[0] = ifac[1] = 1, count[0] = 0; for (int i = 1; i <= K; i++) fac[i] = 1LL * fac[i - 1] * i % mod; for (int i = 2; i <= K; i++) inv[i] = 1LL * (mod - mod / i) * inv[mod % i] % mod, ifac[i] = 1LL * inv[i] * ifac[i - 1] % mod; for (int i = 1; i < 1 << C; i++) count[i] = count[i >> 1] + (i & 1); int xorsum = 0; for (int i = 0; i < n; i++) xorsum ^= (a[i] = read<int>()); for (int i = 0; i < n; i++) { vector<int> b; for (int j = 0; j <= K; j++) b.push_back(a[i] ^ (a[i] - j)); mp[b]++; } for (map<vector<int>, int>::iterator i = mp.begin(); i != mp.end(); i++) st[++top] = i->first, num[top] = i->second; for (int s = 0; s < 1 << C; s++) { tot = 0; for (int i = 1; i <= top; i++) { int tmp = 0; for (int j = 0; j <= K; j++) tmp = (tmp << 1) | (count[st[i][j] & s] & 1); if (!vis[tmp]) A[++tot] = tmp, r[tot] = num[i], vis[tmp] = tot; else r[vis[tmp]] += num[i]; } static int c[17], d[17], ret[17]; memset(ret, 0, sizeof ret); for (int i = 1; i <= tot; i++) { for (int j = 0; j <= K; j++) c[j] = (A[i] >> (K - j) & 1) ? mod - ifac[j] : ifac[j]; Getln(c, d, K + 1); for (int j = 0; j <= K; j++) ret[j] = (1LL * d[j] * r[i] + ret[j]) % mod; vis[A[i]] = 0; } Getexp(ret, c, K + 1), f[s] = 1LL * c[K] * fac[K] % mod; } fwt_xor(f, -1, 1 << C); int p = qpow(qpow(n, K), mod - 2); for (int i = 0; i < 1 << C; i++) printf( %lld , 1LL * f[i ^ xorsum] * p % mod); return 0; } } // namespace run int main() { return run::main(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; int l = 0; int r = 0; vector<int> a(3); vector<int> b(3); for (int i = 0; i < 3; i++) { a[i] = (int)(s[i] - 0 ); b[i] = (int)(s[i + 3] - 0 ); l += a[i]; r += b[i]; } if (l == r) { cout << 0 ; return 0; } int dif = abs(l - r); if (l > r) { sort(a.rbegin(), a.rend()); sort(b.begin(), b.end()); if (a[0] >= dif || (9 - b[0]) >= dif) { cout << 1 ; return 0; } int mx = max({a[0] + (9 - b[0]), a[0] + a[1], 18 - b[0] - b[1]}); if (mx >= dif) { cout << 2 ; return 0; } } else { sort(a.begin(), a.end()); sort(b.rbegin(), b.rend()); if (b[0] >= dif || (9 - a[0]) >= dif) { cout << 1 ; return 0; } int mx = max({b[0] + (9 - a[0]), b[0] + b[1], 18 - a[0] - a[1]}); if (mx >= dif) { cout << 2 ; return 0; } } cout << 3 ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; vector<int> v; cin >> n; int x = 1; for (int i = 1; i <= n; i++) { int d; cin >> d; if (d == x) { v.push_back(i + 2000); x++; } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i] << ; return 0; } |
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_9_b2s_simple_fifo
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 20:18:43 04/19/2015
// Design Name:
// Module Name: rgb2hsv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rgb2hsv(
input clk,
input ce,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input in_hsync, // hsync data
input in_vsync, // vsync data
input in_de,
output [7:0] H,
output [7:0] S,
output [7:0] V,
output out_hsync, // hsync data
output out_vsync, // vsync data
output out_de
);
wire [7:0] q_R;
wire [7:0] q_G;
wire [7:0] q_B;
wire [7:0] f_R;
wire [7:0] f_G;
wire [7:0] f_B;
wire signed [9:0] n_R;
wire signed [9:0] n_G;
wire signed [9:0] n_B;
wire signed [9:0] v_max;
wire signed [9:0] v_min;
wire signed [9:0] v_delta;
wire [1:0] index_min;
wire [1:0] index_max;
// moduly dzielce RGB / 255
div255 divR (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(R), // input [7 : 0] dividend
.divisor(8'hFF), // input [7 : 0] divisor
.quotient(q_R), // output [7 : 0] quotient
.fractional(f_R) // output [7 : 0] fractional
);
div255 divG (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(G), // input [7 : 0] dividend
.divisor(8'hFF), // input [7 : 0] divisor
.quotient(q_G), // output [7 : 0] quotient
.fractional(f_G) // output [7 : 0] fractional
);
div255 divB (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(B), // input [7 : 0] dividend
.divisor(8'hFF), // input [7 : 0] divisor
.quotient(q_B), // output [7 : 0] quotient
.fractional(f_B) // output [7 : 0] fractional
);
assign n_R = {1'b0, q_R[1:0], f_R[6:1]};
assign n_G = {1'b0, q_G[1:0], f_G[6:1]};
assign n_B = {1'b0, q_B[1:0], f_B[6:1]};
//wyznaczanie wartoci max i min z RGB
min minRGB
(
.a(n_R),
.b(n_G),
.c(n_B),
.o(v_min),
.index(index_min)
);
max maxRGB
(
.a(n_R),
.b(n_G),
.c(n_B),
.o(v_max),
.index(index_max)
);
//wyznaczanie max - min
sub10 sub_delta (
.a(v_max), // input [9 : 0] a
.b(v_min), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_delta) // output [9 : 0] s
);
//wyznaczanie S
wire [9:0] f_S;
wire [9:0] q_S;
div10 delta_div_max (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(v_delta), // input [9 : 0] dividend
.divisor(v_max), // input [9 : 0] divisor
.quotient(q_S), // output [9 : 0] quotient
.fractional(f_S) // output [9 : 0] fractional
);
wire [9:0] v_S;
assign v_S = (v_delta > 0 ) ? {1'b0, q_S[0], f_S[8:1]} : 10'b0;
//wyznaczanie H
wire [9:0] v_H [3:0];
wire [9:0] v_Subs [2:0];
wire [9:0] f_Subs [2:0];
wire [9:0] q_Subs [2:0];
sub10 G_sub_B (
.a(n_G), // input [9 : 0] a
.b(n_B), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_Subs[0]) // output [9 : 0] s
);
sub10 B_sub_R (
.a(n_B), // input [9 : 0] a
.b(n_R), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_Subs[1]) // output [9 : 0] s
);
sub10 R_sub_G (
.a(n_R), // input [9 : 0] a
.b(n_G), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_Subs[2]) // output [9 : 0] s
);
div10 G_sub_B_div (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_Subs[0]), // input [9 : 0] dividend
.divisor(v_delta), // input [9 : 0] divisor
.quotient(q_Subs[0]), // output [9 : 0] quotient
.fractional(f_Subs[0]) // output [9 : 0] fractional
);
div10 B_sub_R_div (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_Subs[1]), // input [9 : 0] dividend
.divisor(v_delta), // input [9 : 0] divisor
.quotient(q_Subs[1]), // output [9 : 0] quotient
.fractional(f_Subs[1]) // output [9 : 0] fractional
);
div10 R_sub_G_div (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_Subs[2]), // input [9 : 0] dividend
.divisor(v_delta), // input [9 : 0] divisor
.quotient(q_Subs[2]), // output [9 : 0] quotient
.fractional(f_Subs[2]) // output [9 : 0] fractional
);
wire [9:0] v_H2;
assign v_H2 = (v_delta > 0) ? {q_Subs[index_max + 1][9], q_Subs[index_max + 1][0], f_Subs[index_max + 1][8:1]} : 10'b0;
wire [11:0] const_H[3:0];
wire [11:0] v_const_H;
assign const_H[0] = 12'b0;
assign const_H[1] = 12'b0;
assign const_H[2] = 12'h20;
assign v_const_H = (v_delta > 0) ? const_H[index_max] : 12'h0;
//dodawanie staej
wire [11:0] v_H3;
add12 add_H_const (
.a({v_H2[9], 2'b0, v_H2}), // input [11 : 0] a
.b(v_const_H), // input [11 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_H3) // output [11 : 0] s
);
//sprawdzanie, czy H < 0
wire signed [11:0] v_H4;
assign v_H4 = (v_H3 > 0) ? v_H3 : (v_H3 + 12'h600);
wire [11:0] q_H2;
wire [11:0] f_H2;
//dzielenie przez 6 (!!!)
div12 div_H_6 (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_H4), // input [11 : 0] dividend
.divisor({12'h600}), // input [11 : 0] divisor
.quotient(q_H2), // output [11 : 0] quotient
.fractional(f_H2) // output [11 : 0] fractional
);
wire signed [9:0] v_H5;
assign v_H5 = {q_H2[11], q_H2[0], f_H2[10:3]};
wire signed [16:0] H1;
wire signed [16:0] S1;
wire signed [16:0] V1;
mul9 mul_255_H (
.clk(clk), // input clk
.a(v_H5[7:0]), // input [8 : 0] a
.p(H1) // output [16 : 0] p
);
mul9 mul_255_S (
.clk(clk), // input clk
.a(v_S[7:0]), // input [8 : 0] a
.p(S1) // output [16 : 0] p
);
mul9 mul_255_V (
.clk(clk), // input clk
.a(v_max[7:0]), // input [8 : 0] a
.p(V1) // output [16 : 0] p
);
assign H = H1[15:8];
assign S = S1[15:8];
assign V = V1[15:8];
assign out_hsync = in_hsync;
assign out_vsync = in_vsync;
assign out_de = in_de;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[300000]; int main() { int i, j, n, k, m, l = 0, h, b = 0, c; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; for (i = 1; i < n - 1; i++) { if (a[i - 1] == 1 && a[i + 1] == 1 && a[i] == 0) { l++; a[i + 1] = 0; } } cout << l << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)2e5 + 5; int n, t; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); while (cin >> n) { int ans = 0; set<int> s; for (int i = 1; i <= n && cin >> t; ++i) { if (t) { if (s.count(t)) ans++; else s.insert(t); } else ans++; } cout << ans << endl; } } |
`timescale 1ns/1ps
module hpdmc_ofd
#(parameter g_width = 1,
parameter g_delay = 0)
(
input rst_i,
input clk_p_i,
input clk_n_i,
input [g_width-1:0] in_i,
output [g_width-1:0] out_o
);
genvar i;
wire [g_width-1:0] predelay;
generate
for(i=0; i<g_width; i=i+1) begin
ODDR2
#(.DDR_ALIGNMENT ("C0"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr2_inst
(.D0 (in_i[i]),
.D1 (in_i[i]),
.C0 (clk_p_i),
.C1 (clk_n_i),
.CE (1'b1),
.Q (predelay[i]),
.R (1'b0),
.S (1'b0));
IODELAY2
#(.DATA_RATE ("DDR"),
.ODELAY_VALUE ( g_delay ),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"),
.DELAY_SRC ("ODATAIN"),
.SERDES_MODE ("NONE"),
.SIM_TAPDELAY_VALUE (75))
iodelay2_bus
(
// required datapath
.T (1'b0),
.DOUT (out_o[i]),
.ODATAIN (predelay[i]),
// inactive data connections
.IDATAIN (1'b0),
.TOUT (),
.DATAOUT (),
.DATAOUT2 (),
// connect up the clocks
.IOCLK0 (1'b0), // No calibration needed
.IOCLK1 (1'b0), // No calibration needed
// Tie of the variable delay programming
.CLK (1'b0),
.CAL (1'b0),
.INC (1'b0),
.CE (1'b0),
.BUSY (),
.RST (rst_i));
end // for (i=0; i<g_width; i=i+1)
endgenerate
endmodule // hpdmc_odelay
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_TB_V
`define SKY130_FD_SC_MS__A22O_TB_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a22o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__a22o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { if (false) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } int n; cin >> n; vector<int> v(n + 1, -1); int xx = 1048576; long long sum = 0; for (int i = n; i > 0; i--) { if (v[i] >= 0) { continue; } while (xx / 2 > i) { xx /= 2; } int a = i ^ (xx - 1); v[i] = a; v[a] = i; sum += (a + i) * 2; } if (v[0] < 0) { v[0] = 0; } cout << sum << endl; for (int i = 0; i <= n; i++) { if (i > 0) { cout << ; } cout << v[i]; } cout << endl; if (false) { fclose(stdin); fclose(stdout); } return 0; } |
#include <bits/stdc++.h> using namespace std; int intcmp(const void *v1, const void *v2) { return *(int *)v1 - *(int *)v2; } long long n; long long x[1010]; long long y[1010]; int main() { cin >> n; for (int i = 0; i < n / 3; i++) { printf( %d %d n , 0, i * 2 + 1); } for (int i = 0; i < n - n / 3; i++) { printf( %d %d n , 3, i); } return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/29/2015 08:16:45 AM
// Design Name:
// Module Name: bin_to_bcd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bin_to_bcd(
input wire [10:0] bin,
output reg [3:0] ones,
output reg [3:0] tens,
output reg [3:0] hundreds,
output reg [3:0] thousands
);
parameter THOU = 1000;
parameter HUND = 100;
parameter TENS = 10;
parameter ONES = 1;
reg [10:0] buffer;
integer i;
integer sub;
always @ (*)
begin
buffer = bin;
ones = 4'd0;
tens = 4'd0;
hundreds = 4'd0;
thousands = 4'd0;
sub = 0;
if(buffer >= THOU) begin
for(i = 0; i < 10; i = i + 1) begin
if(i*THOU < buffer) begin
sub = sub + 1;
end
end
if(buffer < sub*THOU) begin
sub = sub - 1;
end
buffer = buffer - sub*THOU;
thousands = sub;
end
sub = 0;
if(buffer >= HUND) begin
for(i = 0; i < 10; i = i + 1) begin
if(i*HUND < buffer) begin
sub = sub + 1;
end
end
if(buffer < sub*HUND) begin
sub = sub - 1;
end
buffer = buffer - sub*HUND;
hundreds = sub;
end
sub = 0;
if(buffer >= TENS) begin
for(i = 0; i < 10; i = i + 1) begin
if(i*TENS < buffer) begin
sub = sub + 1;
end
end
if(buffer < sub*TENS) begin
sub = sub - 1;
end
buffer = buffer - sub*TENS;
tens = sub;
end
sub = 0;
if(buffer >= ONES) begin
for(i = 0; i < 10; i = i + 1) begin
if(i*ONES < buffer) begin
sub = sub + 1;
end
end
if(buffer < sub) begin
sub = sub - 1;
end
buffer = buffer - sub;
ones = sub;
end
end
endmodule
|
`timescale 1ns / 1ps
module uart_ctrl(
input CLK,
input RST,
input EN,
input [3:0] BAUD,
input TXEN,
input RXEN,
output TX,
input RX,
input WRITE,
input [7:0] WRDATA,
output ISFULL,
input READ,
output [7:0] RDDATA,
output DATARDY
);
wire uart_clk;
wire uart_tx_read;
wire [7:0] uart_tx_data;
wire uart_tx_datardy;
wire uart_tx_empty;
wire uart_rx_write;
wire [7:0] uart_rx_data;
wire uart_rx_full;
wire uart_rx_empty;
wire tx_en;
wire rx_en;
clk_div clk_div_inst(
.CLKIN(CLK),
.RST(RST),
.BAUD(BAUD),
.CLKOUT(uart_clk)
);
circular_buff buff_tx(
.CLK(CLK),
.RST(RST),
.WRITE(WRITE),
.WRDATA(WRDATA),
.READ(uart_tx_read),
.RDDATA(uart_tx_data),
.ISFULL(ISFULL),
.ISEMPTY(uart_tx_empty)
);
assign uart_tx_datardy = ~uart_tx_empty;
circular_buff buff_rx(
.CLK(CLK),
.RST(RST),
.WRITE(uart_rx_write),
.WRDATA(uart_rx_data),
.READ(READ),
.RDDATA(RDDATA),
.ISFULL(uart_rx_full),
.ISEMPTY(uart_rx_empty)
);
assign DATARDY = ~uart_rx_empty;
uart_tx tx(
.CLK(uart_clk),
.RST(RST),
.EN(tx_en),
.DATA(uart_tx_data),
.DATARDY(uart_tx_datardy),
.READ(uart_tx_read),
.TX(TX)
);
uart_rx rx(
.CLK(uart_clk),
.RST(RST),
.EN(rx_en),
.RX(RX),
.ISFULL(uart_rx_full),
.WRITE(uart_rx_write),
.DATA(uart_rx_data)
);
assign tx_en = EN ? TXEN ? 1'b1 : 1'b0 : 1'b0;
assign rx_en = EN ? RXEN ? 1'b1 : 1'b0 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 5e9; long long w[20], s[20], m; bool solve(int bm) { long long l = 0, r = m; for (int i = 0; i < 14; ++i) { if (bm % 3 == 0) l += w[i]; else if (bm % 3 == 1) r += w[i]; bm /= 3; } return l == r; } void special4() { while (m > 0) { if (m % 4 == 2) { cout << NO n ; exit(0); } if (m % 4 == 3) { m += 4; } m /= 4; } cout << YES n ; } int main() { w[0] = 1; cin >> w[1] >> m; if (w[1] <= 3) { cout << YES n ; return 0; } for (int i = 2; i < 20; ++i) { w[i] = w[i - 1] * w[1]; if (w[i] > inf) w[i] = 0; } if (w[1] == 4) { special4(); return 0; } for (int bm = 0; bm < (int)5e6; ++bm) { if (solve(bm)) { cout << YES n ; return 0; } } cout << NO n ; }; |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR2B_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m; cin >> n >> m; if (n > 26) cout << m; else { n = pow(2, n); cout << m % n; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 4; string s, des[3]; int n, q, next_occur[26][MAX], dp[255][255][255]; void makeNO() { for (int j = 0; j < 26; j++) next_occur[j][n + 1] = next_occur[j][n] = n; for (int i = n - 1; i >= 0; i--) { for (int j = 0; j < 26; j++) { next_occur[j][i] = (s[i] - a == j ? i : next_occur[j][i + 1]); } } } void makeDp(int a, int b, int c) { int& val = dp[a][b][c]; val = n; if (a) val = min(val, next_occur[des[0][a - 1] - a ][dp[a - 1][b][c] + 1]); if (b) val = min(val, next_occur[des[1][b - 1] - a ][dp[a][b - 1][c] + 1]); if (c) val = min(val, next_occur[des[2][c - 1] - a ][dp[a][b][c - 1] + 1]); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); ; cin >> n >> q >> s; makeNO(); dp[0][0][0] = -1; while (q--) { char o, c; int rel_id; cin >> o >> rel_id; rel_id--; if (o == + ) { cin >> c; des[rel_id] += c; int max0 = des[0].size(), max1 = des[1].size(), max2 = des[2].size(); int min0 = rel_id == 0 ? max0 : 0; int min1 = rel_id == 1 ? max1 : 0; int min2 = rel_id == 2 ? max2 : 0; for (int b = min1; b <= max1; b++) for (int a = min0; a <= max0; a++) for (int c = min2; c <= max2; c++) makeDp(a, b, c); } else { des[rel_id].pop_back(); } bool answer = dp[des[0].size()][des[1].size()][des[2].size()] < n; cout << (answer ? YES n : NO n ); } } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; const int inf = 0x7FFFFFFF; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> void show(T a, int n) { for (int i = 0; i < n; ++i) cout << a[i] << ; cout << endl; } template <class T> void show(T a, int r, int l) { for (int i = 0; i < r; ++i) show(a[i], l); cout << endl; } int sgn(double x) { return x < -eps ? -1 : x > eps; } int main() { double y1, y2, yw, xb, yb, r; while (cin >> y1 >> y2 >> yw >> xb >> yb >> r) { if (sgn(y2 - y1 - 2 * r) < 0) { puts( -1 ); continue; } else { double y = (y1 + r), yyw = yw - r; double ax = (yyw - y) / (yyw - y + yyw - yb) * xb; double ds = (y2 - y) * ax / (sqrt(sqr(ax) + sqr(yyw - y))); if (sgn(ds - r) <= 0) { puts( -1 ); continue; } printf( %.12lf n , ax); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_LP_V
`define SKY130_FD_SC_LP__BUF_LP_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_lp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_lp (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_LP_V
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> arr{2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 4, 9, 25, 49}; int i = 0, k = 0; int l = arr.size(); while (i < l) { string s; cout << arr[i] << endl; cin >> s; if (s == yes ) k++; if (k == 2) { cout << composite << endl; break; } i++; } if (k < 2) { cout << prime << endl; } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module clips video streams on the DE boards. If the incoming image is *
* the wrong size, the circuit will discard or add pixels as necessary. *
* *
******************************************************************************/
module altera_up_video_clipper_drop (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Image in width in pixels
parameter IMAGE_HEIGHT = 480; // Image in height in lines
parameter WW = 9; // Image in width address width
parameter HW = 8; // Image in height address width
parameter DROP_PIXELS_AT_START = 0;
parameter DROP_PIXELS_AT_END = 0;
parameter DROP_LINES_AT_START = 0;
parameter DROP_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam STATE_0_WAIT_FOR_START = 2'h0,
STATE_1_RUN_CLIPPER = 2'h1,
STATE_2_ADD_MISSING_PART = 2'h2;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire full_frame_endofpacket;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
reg [ 1: 0] s_video_clipper_drop;
reg [ 1: 0] ns_video_clipper_drop;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_video_clipper_drop <= STATE_0_WAIT_FOR_START;
else
s_video_clipper_drop <= ns_video_clipper_drop;
end
always @(*)
begin
case (s_video_clipper_drop)
STATE_0_WAIT_FOR_START:
begin
if (stream_in_startofpacket & stream_in_valid)
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
else
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
STATE_1_RUN_CLIPPER:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else if (increment_counters & stream_in_endofpacket)
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
else
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
end
STATE_2_ADD_MISSING_PART:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
end
default:
begin
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_data <= ADD_DATA;
else
stream_out_data <= stream_in_data;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= stream_in_empty;
if (s_video_clipper_drop == STATE_1_RUN_CLIPPER)
stream_out_valid <= pass_inner_frame & stream_in_valid;
else if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_valid <= pass_inner_frame;
else
stream_out_valid <= 1'b0;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready =
(s_video_clipper_drop == STATE_0_WAIT_FOR_START) ?
~(stream_in_startofpacket & stream_in_valid) :
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
// Internal Assignments
assign increment_counters =
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
stream_in_valid & stream_in_ready :
(s_video_clipper_drop == STATE_2_ADD_MISSING_PART) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Drop_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bi-Directional
// Outputs
.start_of_outer_frame (),
.end_of_outer_frame (full_frame_endofpacket),
.start_of_inner_frame (new_startofpacket),
.end_of_inner_frame (new_endofpacket),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Drop_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Drop_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Drop_Counters.WW = WW,
Clipper_Drop_Counters.HW = HW,
Clipper_Drop_Counters.LEFT_OFFSET = DROP_PIXELS_AT_START,
Clipper_Drop_Counters.RIGHT_OFFSET = DROP_PIXELS_AT_END,
Clipper_Drop_Counters.TOP_OFFSET = DROP_LINES_AT_START,
Clipper_Drop_Counters.BOTTOM_OFFSET = DROP_LINES_AT_END;
endmodule
|
// Copyright (C) 2017 Harmon Instruments, LLC
// MIT License
`timescale 1ns / 1ps
// Synchronous clock domain crossing from 100 to 125 MHz via 50 MHz
// up to 100% enable on input
module cdc_100_125
(
input c100, c125, c50,
input [NB-1:0] i, // c100
input iv, // c100
output reg [NB-1:0] o,
output reg ov = 0);
parameter integer NB=8;
reg [NB-1:0] iprev;
reg ivprev = 0;
always @ (posedge c100)
begin
iprev <= i;
ivprev <= iv;
end
reg [NB*2-1:0] i_50;
reg [1:0] iv_50 = 0;
reg t_50 = 0;
always @ (posedge c50)
begin
t_50 <= ~t_50;
i_50 <= {iprev, i};
iv_50 <= {ivprev, iv};
end
reg tprev_125 = 0;
wire v_125 = t_50 ^ tprev_125;
reg vprev_125 = 0;
always @ (posedge c125)
begin
tprev_125 <= t_50;
vprev_125 <= v_125;
ov <= (v_125 && iv_50[1]) || (vprev_125 && iv_50[0]);
o <= (v_125) ? i_50[2*NB-1:NB] : i_50[NB-1:0];
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x, y; cin >> n >> m; y = 3 * m; x = 2 * n; for (int i = 6; i <= x && i <= y; i += 6) { if (x <= y) x += 2; else y += 3; } cout << max(x, y); return 0; } |
module top(
//SMIMS SDK signals
input SDK_CLK, //48MHz
input SDK_RSTN,
input [7:0] SDK_FIFO_CH,
output SDK_FIFO_RD,
input [15:0] SDK_FIFO_DI,
input SDK_FIFO_Empty,
input SDK_FIFO_AlmostEmpty,
output SDK_FIFO_WR,
output [15:0] SDK_FIFO_DO,
input SDK_FIFO_Full,
input SDK_FIFO_AlmostFull,
output SDK_Interrupt,
//UART signals, but not be used now
input core0_UART_RXD,
output core0_UART_TXD,
//GPIO signals
output [7:0] GPIO_o, //mapping to gpio pin on the board
output [7:0] LED, //mapping to LED on the board
input [1:0] GPIO_i //mapping to button on the board
);
wire [5:0] state;
assign LED[0] = GPIO_o[0];
assign LED[1] = GPIO_o[1];
assign LED[2] = GPIO_o[2];
assign LED[3] = GPIO_o[3];
assign LED[4] = GPIO_o[4];
assign LED[5] = GPIO_o[5];
assign LED[6] = GPIO_o[6];
assign LED[7] = GPIO_o[7];
//assign LED = {3'b0, state}; //Using LED to debug
//UART signals
wire core0_tf_push_o;
wire [7:0] core0_print_data_o;
//openRISC signas
wire [15:0] core_id;
wire [7:0] openRISC_RSTN;
wire [7:0] openRISC_STALL;
wire [7:0] openRISC_ram_we;
wire [15:0] openRISC_ram_addr;
wire [31:0] openRISC_data_o;
reg [31:0] openRISC_data_i,_openRISC_data_i;
wire [31:0] openRISC_pc_0;
wire [31:0] openRISC_pc_1;
wire [31:0] openRISC_pc_2;
wire [31:0] openRISC_pc_3;
wire [31:0] openRISC_pc_4;
wire [31:0] openRISC_pc_5;
wire [31:0] openRISC_pc_6;
wire [31:0] openRISC_pc_7;
wire [31:0] openRISC_RAM_DATA_O_0, openRISC_RAM_DATA_O_1, openRISC_RAM_DATA_O_2, openRISC_RAM_DATA_O_3;
wire [31:0] openRISC_RAM_DATA_O_4, openRISC_RAM_DATA_O_5, openRISC_RAM_DATA_O_6, openRISC_RAM_DATA_O_7;
always@(posedge SDK_CLK or negedge SDK_RSTN)
begin
if(~SDK_RSTN)
openRISC_data_i <= 32'd0;
else
openRISC_data_i <= _openRISC_data_i;
end
always@* begin
case(core_id[3:0])
4'd0: _openRISC_data_i = openRISC_RAM_DATA_O_0;
4'd1: _openRISC_data_i = openRISC_RAM_DATA_O_1;
4'd2: _openRISC_data_i = openRISC_RAM_DATA_O_2;
4'd3: _openRISC_data_i = openRISC_RAM_DATA_O_3;
4'd4: _openRISC_data_i = openRISC_RAM_DATA_O_4;
4'd5: _openRISC_data_i = openRISC_RAM_DATA_O_5;
4'd6: _openRISC_data_i = openRISC_RAM_DATA_O_6;
4'd7: _openRISC_data_i = openRISC_RAM_DATA_O_7;
default: _openRISC_data_i = openRISC_RAM_DATA_O_0;
endcase
end
OpenRISC_Interface OR_Interface0(
.SDK_CLK(SDK_CLK), //This clk must be the same with core0's clk. (48MHz)
.SDK_RSTN(SDK_RSTN),
//UART data signals
.core0_tf_push_i(core0_tf_push_o),
.core0_print_data_i(core0_print_data_o),
//SMIMS SDK signals
.SDK_FIFO_RD(SDK_FIFO_RD),
.SDK_FIFO_DI(SDK_FIFO_DI),
.SDK_FIFO_Empty(SDK_FIFO_Empty),
.SDK_FIFO_WR(SDK_FIFO_WR),
.SDK_FIFO_DO(SDK_FIFO_DO),
.SDK_FIFO_Full(SDK_FIFO_Full),
.SDK_Interrupt(SDK_Interrupt),
//openRISC signals
.openRISC_RSTN(openRISC_RSTN),
.openRISC_STALL(openRISC_STALL),
.openRISC_ram_we(openRISC_ram_we),
.openRISC_ram_addr(openRISC_ram_addr),
.openRISC_data_o(openRISC_data_o),
.openRISC_data_i(openRISC_data_i),
.core_id(core_id),
//each core's pc
.openRISC_pc_0(openRISC_pc_0),
.openRISC_pc_1(openRISC_pc_1),
.openRISC_pc_2(openRISC_pc_2),
.openRISC_pc_3(openRISC_pc_3),
.openRISC_pc_4(openRISC_pc_4),
.openRISC_pc_5(openRISC_pc_5),
.openRISC_pc_6(openRISC_pc_6),
.openRISC_pc_7(openRISC_pc_7),
//For DEBUG
.state_o(state)
);
/** core 0 **/
or1200_sopc or1200_sopc_inst_0
(
.CLOCK_48(SDK_CLK),
.rst_n(openRISC_RSTN[0]),
.openRISC_STALL(openRISC_STALL[0]),
.openRISC_pc(openRISC_pc_0),
//For ram top module
.RAM_WE(openRISC_ram_we[0]),
.RAM_ADDR(openRISC_ram_addr),
.RAM_DATA_I(openRISC_data_o),
.RAM_DATA_O(openRISC_RAM_DATA_O_0),
.UART_TXD(core0_UART_TXD),
.UART_RXD(core0_UART_RXD),
//UART data signals
.print_data_o(core0_print_data_o),
.tf_push_o(core0_tf_push_o),
//GPIO
.GPIO_o(GPIO_o),
.GPIO_i(GPIO_i)
);
//The following is for multi-core version.
//But haven't implemented.
/** core 1 **/
// or1200_sopc or1200_sopc_inst_1
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[1]),
//
//
// .openRISC_STALL(openRISC_STALL[1]),
// .openRISC_pc(openRISC_pc_1),
// //For ram top module
// .RAM_WE(openRISC_ram_we[1]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_1)
// );
//
/** core 2 **/
//
// or1200_sopc or1200_sopc_inst_2
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[2]),
//
// .openRISC_STALL(openRISC_STALL[2]),
// .openRISC_pc(openRISC_pc_2),
// //For ram top module
// .RAM_WE(openRISC_ram_we[2]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_2)
// );
/** core 3 **/
// or1200_sopc or1200_sopc_inst_3
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[3]),
//
// .openRISC_STALL(openRISC_STALL[3]),
// .openRISC_pc(openRISC_pc_3),
// //For ram top module
// .RAM_WE(openRISC_ram_we[3]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_3)
// );
//
///** core 4 **/
// or1200_sopc or1200_sopc_inst_4
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[4]),
//
// .openRISC_STALL(openRISC_STALL[4]),
// .openRISC_pc(openRISC_pc_4),
// //For ram top module
// .RAM_WE(openRISC_ram_we[4]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_4)
// );
//
///** core 5 **/
// or1200_sopc or1200_sopc_inst_5
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[5]),
//
// .openRISC_STALL(openRISC_STALL[5]),
// .openRISC_pc(openRISC_pc_5),
// //For ram top module
// .RAM_WE(openRISC_ram_we[5]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_5)
// );
//
///** core 6 **/
// or1200_sopc or1200_sopc_inst_6
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[6]),
//
// .openRISC_STALL(openRISC_STALL[6]),
// .openRISC_pc(openRISC_pc_6),
// //For ram top module
// .RAM_WE(openRISC_ram_we[6]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_6)
// );
//
// /** core 7 **/
// or1200_sopc or1200_sopc_inst_7
// (
// .CLOCK_50(SDK_CLK),
// .rst_n(openRISC_RSTN[7]),
//
// .openRISC_STALL(openRISC_STALL[7]),
// .openRISC_pc(openRISC_pc_7),
// //For ram top module
// .RAM_WE(openRISC_ram_we[7]),
// .RAM_ADDR(openRISC_ram_addr),
// .RAM_DATA_I(openRISC_data_o),
// .RAM_DATA_O(openRISC_RAM_DATA_O_7)
// );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFBBP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPVGND_FUNCTIONAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> const int N = 1000001; int gcd(int a, int b) { int c; while (a) { c = a; a = b % a; b = c; } return b; } void cal(int a, int b, int &s1, int &s2) { int c; while (a > 1) { s1 += b / a; s2 += b / a - 1; c = a; a = b % a; b = c; } s1 += b; s2 += b - 2; } int s[N]; void output(int a, int b) { int sign = 0, m = 0, c; while (a > 1) { for (int i = b / a; i >= 1; --i) s[m++] = sign; c = a; a = b % a; b = c; sign ^= 1; } if (sign) for (int i = m - 1; i >= 0; --i) s[i] ^= 1; for (int i = b - 1; i >= 1; --i) s[m++] = 0; s[m++] = 1; for (int i = m - 1; i >= 0; --i) if (s[i]) printf( T ); else printf( B ); printf( n ); } int main() { int n, r, mis, d; int s1, s2; while (scanf( %d%d , &n, &r) != EOF) { mis = n + 1; d = -1; for (int i = 1; i <= r; ++i) { if (gcd(i, r) != 1) continue; s1 = s2 = 0; cal(i, r, s1, s2); if (s2 < 0) s2 = 0; if (s1 == n && s2 < mis) mis = s2, d = i; } if (mis > n) printf( IMPOSSIBLE n ); else { printf( %d n , mis); output(d, r); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> adj[100005], stx, sty; long long mx = 0ll, ans[100005]; int sz[100005], par[100005]; pair<int, int> centroid = {0, 0}; bool cmp(int u, int v) { return sz[u] < sz[v]; } void dfs(int nw, int bf) { par[nw] = bf; sz[nw] = 1; for (int nx : adj[nw]) if (nx != bf) { dfs(nx, nw); sz[nw] += sz[nx]; } sort(adj[nw].begin(), adj[nw].end(), cmp); mx += 2 * min(sz[nw], n - sz[nw]); centroid = max(centroid, {min(sz[nw], n - sz[nw]), nw}); } void get_subtree(int nw, int bf, vector<int> &v) { v.push_back(nw); for (int nx : adj[nw]) if (nx != bf) get_subtree(nx, nw, v); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int u, v, i = 1; i < n; i++) { cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1, 0); int x = centroid.second, y = par[x]; if (sz[x] * 2 > n) swap(x, y); get_subtree(x, y, stx); get_subtree(y, x, sty); for (int i = 0; i < stx.size(); i++) { ans[stx[i]] = sty[i]; ans[sty[sty.size() - stx.size() + i]] = stx[i]; } for (int i = 0; i < sty.size() - stx.size(); i++) ans[sty[i]] = sty[stx.size() + i]; cout << mx << endl; for (int i = 1; i <= n; i++) cout << ans[i] << ; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_0_ar_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_0_ar_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_W\
IDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_ar_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for struct of ent_aa
//
// Generated
// by: wig
// on: Fri Jul 7 06:37:54 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_aa.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: ent_aa.v,v $
// Revision 1.4 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module struct of ent_aa
//
// No user `defines in this module
module ent_aa
//
// Generated Module inst_aa
//
(
p_mix_sc_sig_2_go,
p_mix_sc_sig_4_go
);
// Generated Module Outputs:
output [31:0] p_mix_sc_sig_2_go;
output [31:0] p_mix_sc_sig_4_go;
// Generated Wires:
wire [31:0] p_mix_sc_sig_2_go;
wire [31:0] p_mix_sc_sig_4_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [31:0] sc_sig_2; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sc_sig_4; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sc_sig_2_go = sc_sig_2; // __I_O_BUS_PORT
assign p_mix_sc_sig_4_go = sc_sig_4; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aaa
ent_aaa inst_aaa ( // is i_mic32_top / hier inst_aaa inst_aaa inst_aa
.sc_p_3(sc_sig_2), // reverse orderreverse order
// multiline comments
.sc_p_4(sc_sig_4) // reverse order
// multiline comments
// line 3
// line 4
// line 5
// line 6
// line 7
// line 8
// line 9
// line 10
// ...[cut]...
);
// End of Generated Instance Port Map for inst_aaa
endmodule
//
// End of Generated Module struct of ent_aa
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int INF = 2e6; const long long LINF = 8e18; const int MOD = 1e9 + 7; const long double EPS = 1e-9; int n; vector<long long> a; struct triplet { int ti, i, j; }; vector<struct triplet> s; int cnt[INF]; int main() { scanf( %d , &n); ; if (n == 1) { printf( 0 ); return 0; } for (int i = 0; i < INF; i++) cnt[i] = 0; for (int i = 0; i < n; i++) { long long X; scanf( %lld , &X); a.push_back(X); cnt[X]++; } int mx = -1, mx_i = 0; for (int i = 0; i < n; i++) mx = max(mx, cnt[a[i]]); for (int i = 0; i < n; i++) if (mx == cnt[a[i]]) mx_i = i; for (int i = mx_i + 1; i < n; i++) { if (a[i] < a[mx_i]) s.push_back({1, i, i - 1}); if (a[i] > a[mx_i]) s.push_back({2, i, i - 1}); } for (int i = mx_i - 1; i > -1; i = i - 1) { if (a[i] < a[mx_i]) s.push_back({1, i, i + 1}); if (a[i] > a[mx_i]) s.push_back({2, i, i + 1}); } printf( %ld , s.size()); for (struct triplet it : s) { printf( n ); printf( %d %d %d , it.ti, it.i + 1, it.j + 1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_LS__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const int inf = numeric_limits<int>::max() / 2 - 1; inline int run() { int n, a, b, k; cin >> n >> a >> b >> k; string s; cin >> s; int cur = 0; vector<int> ans; for (int i = 0; i < n; ++i) { if (s[i] == 0 ) cur++; if (s[i] == 1 ) cur = 0; if (cur == b) ans.push_back(i), cur = 0; } for (int i = 0; i < a - 1 && ans.size() > 1; ++i) { ans.pop_back(); } cout << ans.size() << endl; for (auto i : ans) cout << i + 1 << ; return 0; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); run(); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[10010]; int n, cnt; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) if (a[a[i]] == i && a[i] <= i) cnt++; cout << cnt << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_BLACKBOX_V
|
// -*- Mode: Verilog -*-
// Filename : adxl362.v
// Description : Top level for ADXL362 Model
// Author : Philip Tracton
// Created On : Wed Jun 22 21:28:54 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jun 22 21:28:54 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "adxl362_registers.vh"
module adxl362 (/*AUTOARG*/
// Outputs
MISO, INT1, INT2,
// Inputs
SCLK, MOSI, nCS
) ;
input wire SCLK;
input wire MOSI;
input wire nCS;
output wire MISO;
output reg INT1;
output reg INT2;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] act_inact_ctrl; // From registers of adxl362_regs.v
wire [5:0] address; // From spi of adxl362_spi.v
wire clk; // From sys_con of adxl362_system_controller.v
wire clk_odr; // From sys_con of adxl362_system_controller.v
wire clk_sys; // From sys_con of adxl362_system_controller.v
wire data_fifo_write; // From spi of adxl362_spi.v
wire [7:0] data_write; // From spi of adxl362_spi.v
wire [3:0] fifo_ctrl; // From registers of adxl362_regs.v
wire [7:0] fifo_samples; // From registers of adxl362_regs.v
wire fifo_write; // From accelerometer of adxl362_accelerometer.v
wire [15:0] fifo_write_data; // From accelerometer of adxl362_accelerometer.v
wire [7:0] filter_ctrl; // From registers of adxl362_regs.v
wire [7:0] intmap1; // From registers of adxl362_regs.v
wire [7:0] intmap2; // From registers of adxl362_regs.v
wire [7:0] power_ctrl; // From registers of adxl362_regs.v
wire read_data_fifo; // From spi of adxl362_spi.v
wire reset; // From sys_con of adxl362_system_controller.v
wire rising_clk_odr; // From accelerometer of adxl362_accelerometer.v
wire rst; // From sys_con of adxl362_system_controller.v
wire self_test; // From registers of adxl362_regs.v
wire [10:0] threshold_active; // From registers of adxl362_regs.v
wire [10:0] threshold_inactive; // From registers of adxl362_regs.v
wire [7:0] time_active; // From registers of adxl362_regs.v
wire [15:0] time_inactive; // From registers of adxl362_regs.v
wire write; // From spi of adxl362_spi.v
// End of automatics
/*AUTOREG*/
reg soft_reset = 0;
wire [11:0] xdata;
wire [11:0] ydata;
wire [11:0] zdata;
wire [11:0] temperature;
wire [7:0] data_fifo;
wire [2:0] odr;
wire [1:0] fifo_mode;
wire fifo_enable;
wire fifo_temp;
wire fifo_empty;
wire [7:0] status;
reg data_ready = 0;
wire [15:0] data_fifo_read;
wire [7:0] data_read;
wire empty;
assign odr = filter_ctrl[2:0];
assign fifo_mode = fifo_ctrl[1:0];
assign fifo_enable = (fifo_ctrl[1:0] != 2'b00);
assign fifo_temp = fifo_ctrl[2];
assign status = {5'b0, ~empty, data_ready};
always @(posedge clk_sys)
if (rst) begin
INT1 <= 0;
end else begin
if (intmap1[0]) begin
if (intmap1[7]) begin
INT1 <= ~status[0];
end else begin
INT1 <= status[0];
end
end
if (intmap1[1]) begin
if (intmap1[7]) begin
INT1 <= ~status[1];
end else begin
INT1 <= status[1];
end
end
end // else: !if(rst)
always @(posedge clk_sys)
if (rst) begin
INT2 <= 0;
end else begin
if (intmap2[0]) begin
if (intmap2[7]) begin
INT2 <= ~status[0];
end else begin
INT2 <= status[0];
end
end
if (intmap2[1]) begin
if (intmap2[7]) begin
INT2 <= ~status[1];
end else begin
INT2 <= status[1];
end
end
end // else: !if(rst)
always @(posedge clk_sys) begin
//data_ready = fifo_enable & ~fifo_empty;
if (fifo_write || rising_clk_odr) begin
data_ready <= 1;
end
if (!write & ((address == `ADXL362_XDATA_LOW) |
(address == `ADXL362_YDATA_LOW) |
(address == `ADXL362_ZDATA_LOW) )
) begin
data_ready <= 0;
end
end
//
// System Controller
//
// This module generates the 51.2 KHz clock used in the sytem. This
// module is not synthesizable.
//
adxl362_system_controller sys_con (/*AUTOINST*/
// Outputs
.clk (clk),
.clk_sys (clk_sys),
.reset (reset),
.clk_odr (clk_odr),
.rst (rst),
// Inputs
.soft_reset (soft_reset),
.odr (odr[2:0]));
//
// SPI
//
// This module handles SPI communication with host CPU. Register bus interface
// is synched to the clk domain in this module!
//
adxl362_spi spi(/*AUTOINST*/
// Outputs
.MISO (MISO),
.address (address[5:0]),
.data_write (data_write[7:0]),
.data_fifo_write (data_fifo_write),
.write (write),
.read_data_fifo (read_data_fifo),
// Inputs
.SCLK (SCLK),
.MOSI (MOSI),
.nCS (nCS),
.clk_sys (clk_sys),
.data_read (data_read[7:0]),
.data_fifo_read (data_fifo_read[15:0]),
.rst (rst));
//
// Registers
//
// These are the firmware accessible registers
//
adxl362_regs registers(/*AUTOINST*/
// Outputs
.data_read (data_read[7:0]),
.threshold_active (threshold_active[10:0]),
.time_active (time_active[7:0]),
.threshold_inactive (threshold_inactive[10:0]),
.time_inactive (time_inactive[15:0]),
.act_inact_ctrl (act_inact_ctrl[7:0]),
.fifo_ctrl (fifo_ctrl[3:0]),
.fifo_samples (fifo_samples[7:0]),
.intmap1 (intmap1[7:0]),
.intmap2 (intmap2[7:0]),
.filter_ctrl (filter_ctrl[7:0]),
.power_ctrl (power_ctrl[7:0]),
.self_test (self_test),
// Inputs
.clk_sys (clk_sys),
.write (write),
.address (address[5:0]),
.data_write (data_write[7:0]),
.xdata (xdata[11:0]),
.ydata (ydata[11:0]),
.zdata (zdata[11:0]),
.temperature (temperature[11:0]),
.status (status[7:0]));
//
// Data FIFO
//
adxl362_fifo fifo(
// Outputs
.data_read (data_fifo_read[15:0]),
.full (full),
.empty (empty),
// Inputs
.data_write (fifo_write_data),
.clk (clk_sys),
.rst (rst),
.flush (1'b0),
.read (read_data_fifo),
.write (fifo_write));
//
// Accelerometer
//
adxl362_accelerometer accelerometer (/*AUTOINST*/
// Outputs
.rising_clk_odr (rising_clk_odr),
.fifo_write (fifo_write),
.fifo_write_data(fifo_write_data[15:0]),
.xdata (xdata[11:0]),
.ydata (ydata[11:0]),
.zdata (zdata[11:0]),
.temperature (temperature[11:0]),
// Inputs
.clk_sys (clk_sys),
.clk_odr (clk_odr),
.fifo_mode (fifo_mode[1:0]),
.fifo_temp (fifo_temp));
endmodule // adxl362
|
// ghrd_10as066n2_hps_m.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_hps_m (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
ghrd_10as066n2_hps_m_altera_jtag_avalon_master_171_wqhllki #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_m (
.clk_clk (clk_clk), // input, width = 1, clk.clk
.clk_reset_reset (clk_reset_reset), // input, width = 1, clk_reset.reset
.master_address (master_address), // output, width = 32, master.address
.master_readdata (master_readdata), // input, width = 32, .readdata
.master_read (master_read), // output, width = 1, .read
.master_write (master_write), // output, width = 1, .write
.master_writedata (master_writedata), // output, width = 32, .writedata
.master_waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.master_readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.master_byteenable (master_byteenable), // output, width = 4, .byteenable
.master_reset_reset (master_reset_reset) // output, width = 1, master_reset.reset
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module CapBoardDecoderMain(clk,swIn,enableSer,enablePar,tuningCodeSer,tuningCodePar,capBankSer,capBankPar,stateSer,statePar);
//swIn, enable, tuningCode, and ledOut are as defined in CapBoardDecoder.v
//capBankSer and capBankPar are vectors corresponding to the gates on the MOSFET
//switches for the (four) serial and (four) parallel capacitors.
//PINOUT
//swIn[0] Location PIN_40 Yes
//swIn[1] Location PIN_41 Yes
//swIn[2] Location PIN_44 Yes
//swIn[3] Location PIN_46 Yes
//swIn[4] Location PIN_48 Yes
//swIn[5] Location PIN_49 Yes
//enableSer Location PIN_8 Yes AC24 - enable serial cap bank switching
//enablePar Location PIN_6 Yes AC25 - enable parallel cap bank switching
//tuningCodeSer[0] Location PIN_36 Yes AC3 - serial cap bank code
//tuningCodeSer[1] Location PIN_33 Yes AC6 - serial cap bank code
//tuningCodeSer[2] Location PIN_29 Yes AC9 - serial cap bank code
//tuningCodeSer[3] Location PIN_25 Yes AC12 - serial cap bank code
//tuningCodeSer[4] Location PIN_21 Yes AC15 - serial cap bank code
//tuningCodeSer[5] Location PIN_17 Yes AC18 - serial cap bank code
//tuningCodeSer[6] Location PIN_11 Yes AC21 - serial cap bank code
//tuningCodePar[0] Location PIN_35 Yes AC4 - parallel cap bank code
//tuningCodePar[1] Location PIN_31 Yes AC7 - parallel cap bank code
//tuningCodePar[2] Location PIN_28 Yes AC10 - parallel cap bank code
//tuningCodePar[3] Location PIN_24 Yes AC13 - parallel cap bank code
//tuningCodePar[4] Location PIN_20 Yes AC16 - parallel cap bank code
//tuningCodePar[5] Location PIN_16 Yes AC19 - parallel cap bank code
//tuningCodePar[6] Location PIN_10 Yes AC22 - parallel cap bank code
//clk Location PIN_83 Yes CLOCK - 2 MHz
//capBankSer[0] Location PIN_70 Yes U10_2 - Column E (Cap Bank Serial 1)
//capBankSer[1] Location PIN_74 Yes U9_2 - Column F (Cap Bank Serial 2)
//capBankSer[2] Location PIN_76 Yes U8_2 - Column G (Cap Bank Serial 3)
//capBankSer[3] Location PIN_79 Yes U7_2 - Column H (Cap Bank Serial 4)
//capBankSer[4] Location PIN_73 Yes U10_4 - Column E (Cap Bank Serial 1)
//capBankSer[5] Location PIN_75 Yes U9_4 - Column F (Cap Bank Serial 2)
//capBankSer[6] Location PIN_77 Yes U8_4 - Column G (Cap Bank Serial 3)
//capBankSer[7] Location PIN_80 Yes U7_4 - Column H (Cap Bank Serial 4)
//capBankPar[0] Location PIN_60 Yes U14_2 - Column A (Cap Bank Parallel 1)
//capBankPar[1] Location PIN_63 Yes U13_2 - Column B (Cap Bank Parallel 2)
//capBankPar[2] Location PIN_65 Yes U12_2 - Column C (Cap Bank Parallel 3)
//capBankPar[3] Location PIN_68 Yes U11_2 - Column D (Cap Bank Parallel 4)
//capBankPar[4] Location PIN_61 Yes U14_4 - Column A (Cap Bank Parallel 1)
//capBankPar[5] Location PIN_64 Yes U13_4 - Column B (Cap Bank Parallel 2)
//capBankPar[6] Location PIN_67 Yes U12_4 - Column C (Cap Bank Parallel 3)
//capBankPar[7] Location PIN_69 Yes U11_4 - Column D (Cap Bank Parallel 4)
//stateSer[0] Location PIN_54 Yes Diode12 - state of 1st serial cap bank (Col. E)
//stateSer[1] Location PIN_52 Yes Diode11 - state of 2nd serial cap bank (Col. F)
//stateSer[2] Location PIN_51 Yes Diode10 - state of 3rd serial cap bank (Col. G)
//stateSer[3] Location PIN_50 Yes Diode9 - state of 4th serial cap bank (Col. H)
//statePar[0] Location PIN_58 Yes Diode16 - state of 1st parallel cap bank (Col. A)
//statePar[1] Location PIN_57 Yes Diode15 - state of 2nd parallel cap bank (Col. B)
//statePar[2] Location PIN_56 Yes Diode14 - state of 3rd parallel cap bank (Col. C)
//statePar[3] Location PIN_55 Yes Diode13 - state of 4th parallel cap bank (Col. D)
input clk; //Clock - 2 MHz
reg [2:0] clkCnt; //For dividing the clock to lower rates.
input [5:0] swIn;
input enableSer,enablePar;
input [6:0] tuningCodeSer,tuningCodePar;
//Hold square wave signals going to MIC4427 drivers for cap banks.
//Last four bits are inversion of first four bits
//for 180 degree phase shift of square wave to drive transformers push-pull.
output [7:0] capBankSer, capBankPar;
//Variables for storing state of serial and parallel capacitor groups.
//These are tied to LEDs providing visual diagnosis of which cap banks are on.
//One bit per cap bank (serial or parallel).
output [3:0] stateSer, statePar;
//reg [3:0] stateS, stateP;
//Initialize clock count variable.
initial begin
#0; //Act on zeroth simulation cycle.
clkCnt=3'b0; //Zero.
end
//Act on clk positive edges.
always @(posedge clk) begin
//Divide clk to get slower rate wave for driving transformers,
//so increment counter.
clkCnt=clkCnt+3'b1;
end
//Create instances of decoder objects for serial and parallel capacitor banks.
CapBoardDecoder decoderPar(clk,swIn,enablePar,tuningCodePar,statePar);
CapBoardDecoder decoderSer(clk,swIn,enableSer,tuningCodeSer,stateSer);
//TEST: tie state to tuning code inputs.
//assign stateSer={enableSer, tuningCodeSer[6:4]};
//assign statePar={enablePar, tuningCodePar[6:4]};
//assign stateSer=4'b1101;
//assign statePar=4'b1111;
//Create instances of driver objects - these are responsible for sending
//square wave signal to MOSFET drivers.
//CapBoardDriver is designed to take a 500 kHz clock. The point of
//putting the divide-down action in the main file is to make the CapBoardDriver
//and other sub-modules less likely to be in need of change.
CapBoardDriver driverSer(clkCnt[2],stateSer,capBankSer);
CapBoardDriver driverPar(clkCnt[2],statePar,capBankPar);
//assign capBankSer={clk,clk,clk,clk,~clk,~clk,~clk,~clk};
//assign capBankPar={clk,clk,clk,clk,~clk,~clk,~clk,~clk};//Zero output for parallel cap FET drivers.
//assign capBankPar={4{~clk}};
endmodule
|
#include <bits/stdc++.h> using namespace std; deque<char> D; int main() { int n; cin >> n; string s; cin >> s; for (int i = 0; i < n; i++) if (D.size() % 2 == 0 || D.back() != s[i]) D.push_back(s[i]); if (D.size() % 2 == 1) D.pop_back(); cout << n - D.size() << endl; for (int i = 0; i < D.size(); i++) cout << D[i]; cout << endl; return 0; } |
// my simple if else example, indented by verilog-mode
if (x == 1)
begin
test1 <= 1;
test2 <= 2;
end
else
begin
test1 <= 2;
test2 <= 1;
end
// code from IEEE spec, pg. 164
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 3
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
//
endclass // MyBus
// same example, with verilog mode indenting, Cexp indent = 0
class MyBus extends Bus;
rand AddrType atype;
constraint addr_range
{
(atype == low ) -> addr inside { [0 : 15] };
(atype == mid ) -> addr inside { [16 : 127]};
(atype == high) -> addr inside {[128 : 255]};
}
endclass // MyBus
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a {
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b : coverpoint v_b {
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
//
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
// here is the same code with verilog-mode indenting
// covergroup example from IEEE pg. 317
covergroup cg @(posedge clk );
a : coverpoint v_a
{
bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
// foo
b : coverpoint v_b
{
bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross a, b
{
bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
}
endgroup
module fool;
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case (condition[1 :0])
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case (condition[1:0])
end
// But not this :
always @(posedge clk) begin
if(!M_select)
xferCount < = 8'd0;
else
case ({M_seqAddr,OPB_xferAck})
2'b00 : xferCount <= xferCount;
2'b01 : xferCount <= xferCount - 8'd1;
2'b10 : xferCount <= xferCount + 8'd1;
2'b11 : xferCount <= xferCount;
endcase // case ({M_seqAddr,OPB_xferAck})
end // always @ (posedge clk)
endmodule // fool
module foo;
initial begin
k = 10;
std::randomize(delay) with { (delay>=1000 && delay<=3000); };
j = 9;
end
endmodule // foo
// Issue 324 - constraint indentation is not correct
// This checks for indentation around { and } inside constraint contents
class myclass;
constraint c {
foreach(items[i]) {
if(write) {
items[i].op_code == WRITE;
} else if(read) {
items[i].op_code == READ;
}
}
}
endclass // myclass
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { T f = 1; x = 0; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = x * 10 + s - 0 ; s = getchar(); } x *= f; } template <typename T> void prll(T x) { if (x < 0) putchar( - ), x = -x; if (x > 9) prll(x / 10); putchar(x % 10 + 0 ); } struct Change { int x, y, Ans; } q[2005]; char s[2005][2005]; int up[2005][2005], down[2005][2005]; int dp[2005][2005]; int n, m, Q; struct Deque { int s, t, deq[2005]; Deque() { s = 1, t = 0; } bool empty() { return s > t; } void push_back(int x) { deq[++t] = x; } void pop_back() { t--; } void pop_front() { s++; } void clear() { s = 1, t = 0; } int front() { return deq[s]; } int back() { return deq[t]; } } q1, q2; bool check(const int x, const int len) { q1.clear(); q2.clear(); for (int i = 1; i < len; i++) { while (!q1.empty() && up[x][q1.back()] >= up[x][i]) q1.pop_back(); q1.push_back(i); while (!q2.empty() && down[x][q2.back()] >= down[x][i]) q2.pop_back(); q2.push_back(i); } for (int i = len; i <= m; i++) { while (!q1.empty() && q1.front() <= i - len) q1.pop_front(); while (!q2.empty() && q2.front() <= i - len) q2.pop_front(); while (!q1.empty() && up[x][q1.back()] >= up[x][i]) q1.pop_back(); q1.push_back(i); while (!q2.empty() && down[x][q2.back()] >= down[x][i]) q2.pop_back(); q2.push_back(i); if (up[x][q1.front()] + down[x][q2.front()] - 1 >= len) return true; } return false; } int main() { read(n); read(m); read(Q); for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 1; i <= Q; i++) { read(q[i].x); read(q[i].y); s[q[i].x][q[i].y] = X ; q[i].Ans = 0; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (s[i][j] != . ) s[i][j] = 0; if (s[i][j]) up[i][j] = up[i - 1][j] + 1; } } for (int i = n; i >= 1; i--) { for (int j = 1; j <= m; j++) if (s[i][j]) down[i][j] = down[i + 1][j] + 1; } int res = 0; for (int i = 1; i <= n; i++) if (s[i][1]) dp[i][1] = 1, res = max(res, dp[i][1]); for (int i = 1; i <= m; i++) if (s[1][i]) dp[1][i] = 1, res = max(res, dp[i][1]); for (int i = 2; i <= n; i++) { for (int j = 2; j <= m; j++) if (s[i][j]) dp[i][j] = min(dp[i - 1][j], min(dp[i][j - 1], dp[i - 1][j - 1])) + 1, res = max(res, dp[i][j]); } for (int i = Q; i >= 1; i--) { q[i].Ans = res; if (i == 1) break; int x = q[i].x, y = q[i].y; s[x][y] = 1; for (int i = 1; i <= n; i++) if (s[i][y]) up[i][y] = up[i - 1][y] + 1; for (int i = n; i >= 1; i--) if (s[i][y]) down[i][y] = down[i + 1][y] + 1; int l = 0, r = m, mid, ans; while (l <= r) { mid = (l + r) >> 1; if (check(x, mid)) l = mid + 1, ans = mid; else r = mid - 1; } res = max(ans, res); } for (int i = 1; i <= Q; i++) printf( %d n , q[i].Ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(0); int n, a, b; cin >> n >> a >> b; int ans = 0; int c[n]; for (int i = 0; i < n; i++) cin >> c[i]; int st = 0; int en = n - 1; while (st <= en) { if (st == en) { if (c[st] == 2) { if (a < b) { c[st] = 0; ans += a; } else ans += b; } } else if (c[st] == c[en] && c[st] != 2) { st++, en--; continue; } else { if (c[st] == 2) { if (c[en] == 1) ans += b, c[st] = 1; else if (c[en] == 0) ans += a, c[st] = 0; else { if (a < b) { c[en] = 0; c[st] = 0; ans += 2 * a; } else { c[en] = 1; c[st] = 1; ans += 2 * b; } } } else if (c[en] == 2) { if (c[st] == 1) ans += b, c[en] = 1; else if (c[st] == 0) ans += a, c[en] = 0; else { if (a < b) { c[en] = 0; c[st] = 0; ans += 2 * a; } else { c[en] = 1; c[st] = 1; ans += 2 * b; } } } } st++; en--; } st = 0; en = n - 1; while (st <= en) { if (c[st] != c[en]) { cout << -1; return 0; } st++; en--; } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_LP_V
`define SKY130_FD_SC_LP__NOR4B_LP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_lp (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4b_lp (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_LP_V
|
#include <bits/stdc++.h> int mat[500][500]; int N, K; int main() { scanf( %d%d , &N, &K); int Cnt = 1; int sum = 0; for (int i = 0; i < N; i++) { for (int j = 0; j < K - 1; j++) { mat[i][j] = Cnt++; } } for (int i = 0; i < N; i++) { for (int j = K - 1; j < N; j++) { mat[i][j] = Cnt++; } } for (int i = 0; i < N; i++) { sum += mat[i][K - 1]; } printf( %d n , sum); for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { printf( %d , mat[i][j]); } printf( n ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_TB_V
`define SKY130_FD_SC_LS__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR2B_FUNCTIONAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Output Buffer
// /___/ /\ Filename : OBUFT_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim
// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OBUFT_DCIEN (O, DCITERMDISABLE, I, T);
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter SLEW = "SLOW";
output O;
input DCITERMDISABLE;
input I;
input T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (O, I, ts);
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
`default_nettype none
/* verilator lint_off UNOPTFLAT */
module cdp1802 (
input clock,
input resetq,
output reg Q, // external pin Q
input [3:0] EF, // external flags EF1 to EF4
input [7:0] io_din, // IO data in
output [7:0] io_dout, // IO data out
output [2:0] io_n, // IO control lines: N2,N1,N0
output io_inp, // IO input signal
output io_out, // IO output signal
output unsupported,// unsupported instruction signal
output ram_rd, // RAM read enable
output ram_wr, // RAM write enable
output [15:0] ram_a, // RAM address
input [7:0] ram_q, // RAM read data
output [7:0] ram_d // RAM write data
);
// ---------- execution states -------------------------
reg [2:0] state, state_n;
localparam RESET = 3'd0; // hardware reset asserted
localparam FETCH = 3'd1; // fetching opcode from PC
localparam EXECUTE = 3'd2; // main exection state
localparam EXECUTE2 = 3'd3; // second execute, if memory was read
localparam BRANCH2 = 3'd4; // long branch, collect new PC hi-byte
localparam BRANCH3 = 3'd5; // short branch, new PC lo-byte
localparam SKIP = 3'd6; // for untaken branch
// ---------- registers --------------------------------
reg [3:0] P, X;
reg [15:0] R[0:15]; // 16x16 register file
wire [3:0] Ra; // which register to work on this clock
wire [15:0] Rrd = R[Ra]; // read out the selected register
reg [15:0] Rwd; // write-back value for the register
reg [7:0] D; // data register (accumulator)
reg DF; // data flag (ALU carry)
reg [7:0] B; // used for hi-byte of long branch
reg [7:0] ram_q_; // registered copy of ram_q, for multi-cycle ops
wire [3:0] I, N; // the current instruction
// ---------- RAM hookups ------------------------------
assign ram_d = (I == 4'h6) ? io_din : D;
assign ram_a = Rrd; // RAM address always one of the 16-bit regs
// ---------- conditional branch -----------------------
reg sense;
always @*
casez ({I, N})
{4'h3, 4'b?000}, {4'hc, 4'b??00}: sense = 1;
{4'h3, 4'b?001}, {4'hc, 4'b??01}: sense = Q;
{4'h3, 4'b?010}, {4'hc, 4'b??10}: sense = (D == 8'h00);
{4'h3, 4'b?011}, {4'hc, 4'b??11}: sense = DF;
{4'h3, 4'b?1??}: sense = EF[N[1:0]];
default: sense = 1'bx;
endcase
wire take = sense ^ N[3];
// ---------- fetch/execute ----------------------------
always @*
case (state)
FETCH: state_n = EXECUTE;
EXECUTE:
case (I)
4'h3: state_n = take ? BRANCH3 : FETCH;
4'hc: state_n = take ? BRANCH2 : SKIP;
default: state_n = ram_rd ? EXECUTE2 : FETCH;
endcase
BRANCH2: state_n = BRANCH3;
default: state_n = FETCH;
endcase
assign {I, N} = (state == EXECUTE) ? ram_q : ram_q_;
// ---------- decode and execute -----------------------
wire [3:0] P_n = ((I == 4'hD)) ? N : P; // SEP
wire [3:0] X_n = ((I == 4'hE)) ? N : X; // SEX
wire Q_n = (({I, N} == 8'h7a) | ({I, N} == 8'h7b)) ? N[0] : Q; // REQ, SEQ
reg [5:0] action; // reg. address; RAM rd; RAM wr
assign {Ra, ram_rd, ram_wr} = action;
localparam MEM___ = 2'b00; // no memory access
localparam MEM_RD = 2'b10; // memory read strobe
localparam MEM_WR = 2'b01; // memory write strobe
always @(state, I, N)
case (state)
FETCH, BRANCH2, SKIP: {action, Rwd} = {P, MEM_RD, Rrd + 16'd1};
EXECUTE, EXECUTE2:
casez ({I, N})
/* LDN */ 8'h0?: {action, Rwd} = {N, MEM_RD, Rrd};
/* INC */ 8'h1?: {action, Rwd} = {N, MEM___, Rrd + 16'd1};
/* DEC */ 8'h2?: {action, Rwd} = {N, MEM___, Rrd - 16'd1};
/* LDA */ 8'h4?: {action, Rwd} = {N, MEM_RD, Rrd + 16'd1};
/* STR */ 8'h5?: {action, Rwd} = {N, MEM_WR, Rrd};
/* SEP */ 8'hd?,
/* SEX */ 8'he?,
/* GLO */ 8'h8?,
/* GHI */ 8'h9?: {action, Rwd} = {N, MEM___, Rrd};
/* PLO */ 8'ha?: {action, Rwd} = {N, MEM___, Rrd[15:8], D};
/* PHI */ 8'hb?: {action, Rwd} = {N, MEM___, D, Rrd[7:0]};
/* STXD */ 8'h73: {action, Rwd} = {X, MEM_WR, Rrd - 16'd1};
/* LDXA */ 8'h72,
/* OUT */ {4'h6, 4'b0???}: {action, Rwd} = {X, MEM_RD, Rrd + 16'd1};
/* INP */ {4'h6, 4'b1???}: {action, Rwd} = {X, MEM_WR, Rrd};
/* immediate and branch instructions must fetch from R[P] */
8'h7c, 8'h7d, 8'h7f, 8'hf8, 8'hf9, 8'hfa, 8'hfb, 8'hfc, 8'hfd, 8'hff,
8'h3?, 8'hc?: {action, Rwd} = {P, MEM_RD, Rrd + 16'd1};
default: {action, Rwd} = {X, MEM_RD, Rrd};
endcase
BRANCH3: {action, Rwd} = {P, MEM___, (I == 4'hc) ? B : Rrd[15:8], ram_q};
default: {action, Rwd} = {X, MEM___, Rrd};
endcase
wire [8:0] carry = (I[3]) ? 9'd0 : {8'd0, DF}; // 0 or 1 for ADC
wire [8:0] borrow = (I[3]) ? 9'd0 : ~{9{DF}}; // -1 or 0 for SDB and SMB
reg [8:0] DFD_n;
always @*
casez ({I, N})
/* LDXA */ 8'h72,
/* LDX */ 8'hf0,
/* LDI */ 8'hf8,
/* LDA */ 8'h4?,
/* LDN */ 8'h0?: DFD_n = {DF, ram_q};
/* GLO */ 8'h8?: DFD_n = {DF, Rrd[7:0]};
/* GHI */ 8'h9?: DFD_n = {DF, Rrd[15:8]};
/* INP */ 8'b0110_1???: DFD_n = {DF, io_din};
/* OR */ 8'b1111_?001: DFD_n = {DF, D | ram_q};
/* AND */ 8'b1111_?010: DFD_n = {DF, D & ram_q};
/* XOR */ 8'b1111_?011: DFD_n = {DF, D ^ ram_q};
/* ADD */ 8'b?111_?100: DFD_n = {1'b0, D} + {1'b0, ram_q} + carry;
/* SD */ 8'b?111_?101: DFD_n = ({1'b1, ram_q} - {1'b0, D}) + borrow;
/* SM */ 8'b?111_?111: DFD_n = ({1'b1, D} - {1'b0, ram_q}) + borrow;
/* SHR */ 8'b?111_0110: DFD_n = {D[0], carry[0], D[7:1]};
/* SHL */ 8'b?111_1110: DFD_n = {D, carry[0]};
default: DFD_n = {DF, D};
endcase
assign io_n = N[2:0];
assign io_out = (I == 4'h6) & ~N[3] & (state == EXECUTE2) & (N[2:0] != 3'b000);
assign io_inp = (I == 4'h6) & N[3] & (state == EXECUTE) & (N[2:0] != 3'b000);
assign io_dout = ram_q;
assign unsupported = {I, N} == 8'h70;
// ---------- cycle commit -----------------------------
always @(negedge resetq or posedge clock)
if (!resetq) begin
{ram_q_, Q, P, X} <= 0;
{DF, D} <= 9'd0;
R[0] <= 16'd0;
state <= RESET;
end else begin
state <= state_n;
if (state == EXECUTE)
{ram_q_, Q, P, X} <= {ram_q, Q_n, P_n, X_n};
if (state != EXECUTE2)
R[Ra] <= Rwd;
if (((state == EXECUTE) & !ram_rd) || (state == EXECUTE2))
{DF, D} <= DFD_n;
if (state == BRANCH2)
B <= ram_q;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A311O_BEHAVIORAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; int a[maxn]; int n, l, t; int main() { scanf( %d%d%d , &n, &l, &t); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } double ans = 0; int k = 2 * t / l, c = 2 * t % l; for (int i = 0; i < n; i++) { int w = a[i] - c; int cnt = 0; if (w >= 0) { cnt = i - (lower_bound(a, a + n, w) - a); } else { cnt += i; cnt += n - (lower_bound(a, a + n, l + w) - a); } ans += 0.5 * 0.5 * k * (n - 1) + 0.5 * 0.5 * cnt; } cout.setf(ios::fixed); cout << setprecision(9) << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { long long v, p, id; } t[2000001]; bool cmp2(node a, node b) { return a.p < b.p; } struct cmp { bool operator()(node a, node b) { return a.v > b.v; } }; priority_queue<node, vector<node>, cmp> q; priority_queue<long long> q2; long long vis[2000001]; signed main() { long long T; scanf( %I64d , &T); while (T--) { long long n; scanf( %I64d , &n); for (long long i = 1; i <= n; i++) vis[i] = 0; while (!q.empty()) q.pop(); while (!q2.empty()) q2.pop(); for (long long i = 1; i <= n; i++) { scanf( %I64d%I64d , &t[i].p, &t[i].v); t[i].id = i; q.push(t[i]); } sort(t + 1, t + n + 1, cmp2); long long cur = 0, ans = 0; for (long long i = 1; i <= n; i++) { while (cur != n && cur < t[i].p) { while (vis[q.top().id] == 1) q.pop(); if (q2.size()) { ans += q.top().v - q2.top(); q2.pop(); vis[q.top().id] = 1; q.pop(); } else { ans += q.top().v; vis[q.top().id] = 1; q.pop(); } cur++; } if (cur == n) break; if (vis[t[i].id]) q2.push(t[i].v); else ++cur; vis[t[i].id] = 1; } printf( %I64d n , ans); } return 0; } |
// part of NeoGS project (c) 2008-2009 NedoPC
// dma sequencer
/*
input interface of every DMA end-user
clocks: ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
reqN _______/```````````\______________/`````````````````\______________/``````````````````
ackN ________________/``\_____________________________/``\____________________/``\__/``\__/
doneN _________________________/``\_____________________________/``\______________/``\__/``\
rnwN -------/```````````\--------------\_________________/--------------/````````\_____/```
adrwdN -------< read addr >--------------< write addr&data >--------------< rdaddr X wra X rd
rdN -------------------------<dd>-----------------------------------------------<dd>------
sequencing algorithm is round-robin with fixed initial prioritizing when multiple requests appear simultaneously while
everything was idle
*/
module dma_sequencer(
input wire clk,
input wire rst_n,
// dma requests connection
//
input wire req0,
input wire req1,
input wire req2,
input wire req3,
input wire [20:0] addr0,
input wire [20:0] addr1,
input wire [20:0] addr2,
input wire [20:0] addr3,
input wire rnw0,
input wire rnw1,
input wire rnw2,
input wire rnw3,
input wire [7:0] wd0,
input wire [7:0] wd1,
input wire [7:0] wd2,
input wire [7:0] wd3,
output wire ack0,
output wire ack1,
output wire ack2,
output wire ack3,
output wire end0,
output wire end1,
output wire end2,
output wire end3,
output wire [7:0] rd,
// dma controller connection
output wire dma_req,
output wire [20:0] dma_addr,
output wire dma_rnw,
output wire [7:0] dma_wd,
input wire [7:0] dma_rd,
input wire dma_ack,
input wire dma_end
);
localparam DEVNUM = 4;
wire [DEVNUM-1:0] reqs;
wire [20:0] addrs [0:DEVNUM-1];
wire [DEVNUM-1:0] rnws;
wire [7:0] wds [0:DEVNUM-1];
wire [DEVNUM-1:0] acks;
wire [DEVNUM-1:0] ends;
// aggregate signals for brewity
assign reqs[DEVNUM-1:0] = {req3,req2,req1,req0};
assign addrs[0] = addr0;
assign addrs[1] = addr1;
assign addrs[2] = addr2;
assign addrs[3] = addr3;
assign rnws[DEVNUM-1:0] = {rnw3,rnw2,rnw1,rnw0};
assign wds[0] = wd0;
assign wds[1] = wd1;
assign wds[2] = wd2;
assign wds[3] = wd3;
assign {ack3,ack2,ack1,ack0} = acks[DEVNUM-1:0];
assign {end3,end2,end1,end0} = ends[DEVNUM-1:0];
reg [DEVNUM-1:0] cur_input_mux; // which current input is muxed to the DMA (input=req,ack,addr,wd)
reg [DEVNUM-1:0] cur_output_mux; // which current output is muxed to the DMA (output=end)
wire [DEVNUM-1:0] next_input_mux;
reg busy;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
busy = 1'b0;
else // posedge clk
begin
if( !busy )
busy <= |reqs;
else // busy
busy <= dma_req;
end
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
cur_input_mux = {DEVNUM{1'b0}};
end
else // posedge clk
begin
if( (!busy) || dma_ack ) // idle or dma acknoledges data receive
begin
cur_input_mux <= next_input_mux;
end
end
end
rr_arbiter #( .DEVNUM(DEVNUM) ) rr_arbiter(
.reqs(reqs),
.prev( cur_input_mux),
.next(next_input_mux)
);
// output mux should follow input after dma_ack
//
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
cur_output_mux = {DEVNUM{1'b0}};
end
else // posedge clk
begin
if( dma_ack )
cur_output_mux <= cur_input_mux;
end
end
// actual muxing of input data
//
wor int_dma_req; // wor is to do easily decoded AND-OR muxes
wor [20:0] int_dma_addr; //
wand int_dma_rnw; // this is WAND to have it 1 in idle
wor [7:0] int_dma_wd; //
//
genvar i;
generate
for(i=0;i<DEVNUM;i=i+1)
begin : mux_dma_inputs
assign int_dma_req = cur_input_mux[i] & reqs[i]; // wired OR happens!
assign int_dma_addr = {21{cur_input_mux[i]}} & addrs[i]; //
assign int_dma_rnw = (~cur_input_mux[i]) | rnws[i]; // wired AND...
assign int_dma_wd = {8{cur_input_mux[i]}} & wds[i]; //
end
endgenerate
//
// output data to dma controller
//
assign dma_req = int_dma_req;
assign dma_addr = int_dma_addr;
assign dma_rnw = int_dma_rnw;
assign dma_wd = int_dma_wd;
// actual de-muxing of output data from dma controller
//
assign acks = cur_input_mux & {DEVNUM{dma_ack}};
assign ends = cur_output_mux & {DEVNUM{dma_end}};
//
assign rd = dma_rd; // read data does not need (de)muxing
endmodule
// round-robin arbiter
module rr_arbiter(
/*input wire [DEVNUM-1:0]*/ reqs,
/*input wire [DEVNUM-1:0]*/ prev,
/*output wire [DEVNUM-1:0]*/ next
);
parameter DEVNUM=4;
input wire [DEVNUM-1:0] reqs;
input wire [DEVNUM-1:0] prev;
output wire [DEVNUM-1:0] next;
genvar i;
// arbitration if there was previous actives
//
wire [DEVNUM-1:0] loop;
wire [DEVNUM-1:0] next_arb;
generate
for(i=0;i<DEVNUM;i=i+1)
begin : gen_forwarders
if( i==0 )
rr_fwd forwarder( .prev(prev[i]),
.req(reqs[i]),
.next(next_arb[i]),
.loop_in(loop[DEVNUM-1]),
.loop_out(loop[i]) );
else
rr_fwd forwarder( .prev(prev[i]),
.req(reqs[i]),
.next(next_arb[i]),
.loop_in(loop[i-1]),
.loop_out(loop[i]) );
end
endgenerate
// arbitration if there was no actives prior to requests
//
wire [DEVNUM-1:0] next_empty;
generate
for(i=0;i<DEVNUM;i=i+1)
begin : pri_enc
if( i==0 )
begin : pri_zero
assign next_empty[0] = reqs[0];
end
else
begin : pri_nonzero
assign next_empty[i] = reqs[i] & ( ~|reqs[i-1:0] );
end
end
endgenerate
// select between prev-busy and prev-free cases
assign next = ( prev ) ? next_arb : next_empty;
endmodule
// round-robin request forwarder (1 bit)
module rr_fwd(
input wire prev, // who was arbitrated last time (one-hot)
input wire req, // who are requesting
output reg next, // who will be next
input wire loop_in, // for internal arbitration
output reg loop_out //
);
always @*
begin
if( prev )
begin
loop_out = 1'b1;
end
else //!prev
begin
loop_out = req ? 1'b0 : loop_in;
end
end
always @*
begin
next = req ? loop_in : 1'b0;
end
endmodule
|
`include "oled_init.v"
`include "oled_cls.v"
module fpga (
input CLK,
input RST,
output CSN,
output SDIN,
output SCLK,
output DCN,
output RESN,
output VBATN,
output VDDN,
output [1:0] Led
);
reg [7:0] clock_counter='b0;
reg init_fin_latched='b1;
reg cls_fin_latched='b1;
assign Led[0]=init_fin_latched;
oled_init i_oled_init(
.clk(CLK),
.reset(RST),
.init_start(init_start),
.init_fin(init_fin),
.spi_csn(init_csn),
.spi_sdo(init_sdin),
.spi_sclk(init_sclk),
.spi_dcn(init_dcn),
.spi_resn(RESN),
.spi_vbatn(VBATN),
.spi_vddn(VDDN)
);
oled_cls i_oled_cls(
.clk(CLK),
.reset(RST),
.cls_start(cls_start),
.cls_fin(cls_fin),
.spi_csn(cls_csn),
.spi_sdo(cls_sdin),
.spi_sclk(cls_sclk),
.spi_dcn(cls_dcn)
);
assign init_start = (((&clock_counter)==1'b1) && (init_fin_latched==1'b0)) ? 1'b1 : 1'b0;
assign CSN = init_fin_latched ? cls_csn : init_csn;
assign SDIN = init_fin_latched ? cls_sdin : init_sdin;
assign SCLK = init_fin_latched ? cls_sclk : init_sclk;
assign DCN = init_fin_latched ? cls_dcn : init_dcn;
always @(posedge CLK) begin
if (RST) begin
clock_counter <= 'b0;
init_fin_latched <= 'b0;
cls_fin_latched <= 'b0;
end else begin
clock_counter <= clock_counter + 1;
if (init_fin)
init_fin_latched <= 'b1;
if (cls_fin)
cls_fin_latched <= 'b1;
end
end
assign cls_start = init_fin;
assign Led[1] = cls_fin_latched;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { bool discount_flag = true; int num_of_session; cin >> num_of_session; vector<int> num_of_teams(200001); for (int i = 0; i < num_of_session; i++) cin >> num_of_teams[i]; for (int i = 0; i < num_of_session; i++) if (num_of_teams[i] % 2 == 1) if (i != num_of_session - 1 and num_of_teams[i + 1] > 0) { num_of_teams[i + 1] -= 1; num_of_teams[i] = 0; } else if (num_of_teams[i + 1] == 0) discount_flag = false; else if (i == num_of_session) discount_flag = false; if (discount_flag) cout << YES << endl; else cout << NO << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_PP_V |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult_21_coeff_83443.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.3 Build 178 02/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_21_coeff_83443 (
clken,
clock,
dataa,
result);
input clken;
input clock;
input [20:0] dataa;
output [41:0] result;
wire [41:0] sub_wire0;
wire [20:0] sub_wire1 = 21'd83443;
wire [41:0] result = sub_wire0[41:0];
lpm_mult lpm_mult_component (
.clock (clock),
.datab (sub_wire1),
.clken (clken),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=NO,INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=1",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 21,
lpm_mult_component.lpm_widthb = 21,
lpm_mult_component.lpm_widthp = 42;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_SYMBOL_V
`define SKY130_FD_SC_LP__NOR3_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> std::ostream &operator<<(std::ostream &out, vector<T> &v) { for (typename vector<T>::size_type i = 0; i < v.size(); ++i) out << v[i] << ; out << n ; return out; } template <typename T> std::ostream &operator<<(std::ostream &out, vector<vector<T> > &v) { for (size_t i = 0; i < v.size(); ++i) { for (size_t j = 0; j < v[i].size(); ++j) { out << v[i][j] << ; } out << n ; } return out; } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; vector<long long> divisors; for (long long i = 1; i * i <= n; ++i) { if (n % i == 0) { divisors.push_back(i); if (n / i != i) { divisors.push_back(n / i); } } } if (k > divisors.size()) { cout << -1 n ; return 0; } sort(divisors.begin(), divisors.end()); cout << divisors[k - 1] << n ; return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_jtaggpioport(
input clock,
input reset,
output io_jtag_TCK,
output io_jtag_TMS,
output io_jtag_TDI,
input io_jtag_TDO,
output io_jtag_TRST,
input io_jtag_DRV_TDO,
input io_pins_TCK_i_ival,
output io_pins_TCK_o_oval,
output io_pins_TCK_o_oe,
output io_pins_TCK_o_ie,
output io_pins_TCK_o_pue,
output io_pins_TCK_o_ds,
input io_pins_TMS_i_ival,
output io_pins_TMS_o_oval,
output io_pins_TMS_o_oe,
output io_pins_TMS_o_ie,
output io_pins_TMS_o_pue,
output io_pins_TMS_o_ds,
input io_pins_TDI_i_ival,
output io_pins_TDI_o_oval,
output io_pins_TDI_o_oe,
output io_pins_TDI_o_ie,
output io_pins_TDI_o_pue,
output io_pins_TDI_o_ds,
input io_pins_TDO_i_ival,
output io_pins_TDO_o_oval,
output io_pins_TDO_o_oe,
output io_pins_TDO_o_ie,
output io_pins_TDO_o_pue,
output io_pins_TDO_o_ds,
input io_pins_TRST_n_i_ival,
output io_pins_TRST_n_o_oval,
output io_pins_TRST_n_o_oe,
output io_pins_TRST_n_o_ie,
output io_pins_TRST_n_o_pue,
output io_pins_TRST_n_o_ds
);
wire T_101;
wire T_117;
assign io_jtag_TCK = T_101;
assign io_jtag_TMS = io_pins_TMS_i_ival;
assign io_jtag_TDI = io_pins_TDI_i_ival;
assign io_jtag_TRST = T_117;
assign io_pins_TCK_o_oval = 1'h0;
assign io_pins_TCK_o_oe = 1'h0;
assign io_pins_TCK_o_ie = 1'h1;
assign io_pins_TCK_o_pue = 1'h1;
assign io_pins_TCK_o_ds = 1'h0;
assign io_pins_TMS_o_oval = 1'h0;
assign io_pins_TMS_o_oe = 1'h0;
assign io_pins_TMS_o_ie = 1'h1;
assign io_pins_TMS_o_pue = 1'h1;
assign io_pins_TMS_o_ds = 1'h0;
assign io_pins_TDI_o_oval = 1'h0;
assign io_pins_TDI_o_oe = 1'h0;
assign io_pins_TDI_o_ie = 1'h1;
assign io_pins_TDI_o_pue = 1'h1;
assign io_pins_TDI_o_ds = 1'h0;
assign io_pins_TDO_o_oval = io_jtag_TDO;
assign io_pins_TDO_o_oe = io_jtag_DRV_TDO;
assign io_pins_TDO_o_ie = 1'h0;
assign io_pins_TDO_o_pue = 1'h0;
assign io_pins_TDO_o_ds = 1'h0;
assign io_pins_TRST_n_o_oval = 1'h0;
assign io_pins_TRST_n_o_oe = 1'h0;
assign io_pins_TRST_n_o_ie = 1'h1;
assign io_pins_TRST_n_o_pue = 1'h1;
assign io_pins_TRST_n_o_ds = 1'h0;
assign T_101 = $unsigned(io_pins_TCK_i_ival);
assign T_117 = ~ io_pins_TRST_n_i_ival;
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S9_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAMB16_S9_altera (
address,
clock,
data,
rden,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input rden;
input wren;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (address),
.rden_a (rden),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../../../Documents and Settings/Danaoula/Desktop/NF2/projects/ngnp_multicore/src/bb_ram0.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../../../Documents and Settings/Danaoula/Desktop/NF2/projects/ngnp_multicore/src/bb_ram0.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../../../Documents and Settings/Danaoula/Desktop/NF2/projects/ngnp_multicore/src/bb_ram0.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT NODEFVAL rden
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = int(1e5) + 10; const int K = 11; const int MOD = int(1e9) + 7; const int INF = int(2e9) + 5; const long long INF64 = 1e18; int dp[N]; void solve() { string s; cin >> s; stack<int> st; int n = s.length(); for (int i = 0; i < n; i++) { if (s[i] == ( || s[i] == [ || s[i] == { ) { st.push(i); } else { if (st.empty()) continue; int t = st.top(); if (s[i] == ) && s[t] == ( ) { dp[i] = i - t + 1; if (t > 0) dp[i] += dp[t - 1]; st.pop(); } else if (s[i] == ] && s[t] == [ ) { dp[i] = i - t + 1; if (t > 0) dp[i] += dp[t - 1]; st.pop(); } else if (s[i] == } && s[t] == { ) { dp[i] = i - t + 1; if (t > 0) dp[i] += dp[t - 1]; st.pop(); } else { while (!st.empty()) st.pop(); } } } int i = n - 1; int mx = 0, index = -1; while (i >= 0) { if (dp[i] == 0) { i--; continue; } int cnt = 0, t = i; int x = dp[i]; for (int j = 0; j < x; j++) { if (s[i] == [ ) cnt++; i--; } if (cnt > mx) { mx = cnt; index = t; } } if (mx == 0) { cout << 0 << n ; return; } cout << mx << n ; cout << s.substr(index + 1 - dp[index], dp[index]); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1100000; const long long M = 1000000007; long long i, j, k, l, m, n, o, p, K, w, F[N], ni[N]; inline long long fastmi(long long x, long long m) { long long ans = 1; while (m) { if (m & 1) ans = (ans * x) % M; x = (x * x) % M; m >>= 1; } return ans; } inline long long get(long long l, long long r) { long long ans; if ((r < 0) || (l < 0)) return 0; if (l > r) return 1; if (l == 0) return 0; ans = (F[r] * ni[l - 1]) % M; return ans; } inline long long Solve() { long long ans1, ans2, ans, cul, cant; F[0] = 1; ni[0] = 1; for (i = 1; i <= K; i++) { F[i] = (F[i - 1] * i) % M; ni[i] = fastmi(F[i], M - 2); } ans = 0; for (i = 0; i <= K - 1; i++) { cant = i + 1 - w + 1; if (cant < 0) cant = 0; k = K - cant; o = (get(K - i, K - 1) * min(w, i + 1)) % M; l = w - i - 2; if (l < 0) l = 0; j = w - 1 - l; p = (fastmi(k, l) * get(k - j + 1, k)) % M; cul = (o * p) % M; ans += cul; if (ans >= M) ans -= M; } ans1 = ans; ans = 0; for (i = 0; i <= K - 1; i++) { cant = i + 1 - (w - 1) + 1; if (cant < 0) cant = 0; k = K - cant; o = (get(K - i, K - 1) * min(w - 1, i + 1)) % M; l = w - 1 - i - 2; if (l < 0) l = 0; j = w - 1 - l; p = (fastmi(k, l) * get(k - j + 1, k)) % M; cul = (o * p) % M; ans += cul; if (ans >= M) ans -= M; } ans2 = ans1 - ans; if (ans2 < 0) ans2 += M; ans1 = ans1 + ans1; if (ans1 >= M) ans1 -= M; ans1 -= ans2; if (ans1 < 0) ans1 += M; ans = (ans1 * K) % M; return ans; } int main() { cin >> K >> w; cout << Solve() << endl; fclose(stdin); fclose(stdout); return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 3
(* X_CORE_INFO = "xlconstant_v1_1_3_xlconstant,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "fmrv32im_artya7_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{}" *)
(* CORE_GENERATION_INFO = "fmrv32im_artya7_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_xlconstant_0_0 (
dout
);
output wire [0 : 0] dout;
xlconstant_v1_1_3_xlconstant #(
.CONST_WIDTH(1),
.CONST_VAL('H1)
) inst (
.dout(dout)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, m, pnt[N], vis[N]; long long vsum[N], esum[N], vcnt[N]; pair<pair<int, int>, pair<int, int> > edge[N]; vector<int> edge2[N]; int find(int x) { if (x != pnt[x]) pnt[x] = find(pnt[x]); return pnt[x]; } void dfs(int u, int root) { vis[u] = root; vsum[u] = vcnt[u]; for (int i = 0; i < (int)(edge2[u]).size(); ++i) { int v = edge2[u][i]; if (vis[v]) continue; dfs(v, root); vsum[u] += vsum[v]; } } void solve() { int u, v, w; m = n - 1; memset(esum, 0, sizeof(esum)); for (int i = 0; i < n; ++i) { vcnt[i] = 1; pnt[i] = i; } for (int i = 0; i < m; ++i) { scanf( %d%d%d , &u, &v, &w); edge[i] = make_pair(make_pair(w, i), make_pair(u - 1, v - 1)); } sort(edge, edge + m); for (int i = 0; i < m; ++i) { int j = i + 1; for (; j < m; ++j) if (edge[i].first.first != edge[j].first.first) break; set<int> s; for (int k = i; k < j; ++k) { s.insert(find(edge[k].second.first)); s.insert(find(edge[k].second.second)); } vector<int> vt((s).begin(), (s).end()); for (int k = 0; k < (int)(vt).size(); ++k) { vsum[vt[k]] = vis[vt[k]] = 0; edge2[vt[k]] = vector<int>(); } for (int k = i; k < j; ++k) { int p = find(edge[k].second.first); int q = find(edge[k].second.second); edge2[p].push_back(q); edge2[q].push_back(p); } for (int k = 0; k < (int)(vt).size(); ++k) { if (vis[vt[k]]) continue; dfs(vt[k], vt[k] + 1); } for (int k = i; k < j; ++k) { int p = find(edge[k].second.first); int q = find(edge[k].second.second); long long c = min(vsum[p], vsum[q]); esum[edge[k].first.second] = 2 * c * (vsum[vis[p] - 1] - c); } for (int k = i; k < j; ++k) { int p = find(edge[k].second.first); int q = find(edge[k].second.second); pnt[p] = q; vcnt[q] += vcnt[p]; } i = j - 1; } long long ans = 0; int ct = 0; for (int i = 0; i < m; ++i) { if (ans < esum[i]) { ans = esum[i]; ct = 1; } else if (ans == esum[i]) { ct++; } } printf( %I64d %d n , ans, ct); bool first = true; for (int i = 0; i < m; ++i) { if (esum[i] != ans) continue; if (!first) printf( ); else first = false; printf( %d , i + 1); } puts( ); } int main() { while (scanf( %d , &n) != EOF) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline string toString(T a) { ostringstream os( ); os << a; return os.str(); } template <typename T> inline long long toLong(T a) { long long res; istringstream os(a); os >> res; return res; } template <typename T> inline int toInt(T a) { int res; istringstream os(a); os >> res; return res; } template <typename T> inline double toDouble(T a) { double res; istringstream os(a); os >> res; return res; } template <typename T> inline T SQ(T a) { return a * a; } template <typename T> inline T GCD(T a, T b) { if (b == 0) return a; else return GCD(b, a % b); } template <typename T> inline T LCM(T a, T b) { long long res = a * b; res /= GCD(a, b); return res; } template <typename T> inline unsigned long long BIGMOD(T a, T b, T m) { if (b == 0) return 1; else if (b % 2 == 0) return SQ(BIGMOD(a, b / 2, m)) % m; else return (a % m * BIGMOD(a, b - 1, m)) % m; } template <typename T> inline vector<string> PARSE(T str) { vector<string> res; string s; istringstream os(str); while (os >> s) res.push_back(s); return res; } template <typename T> inline unsigned long long DIST(T A, T B) { unsigned long long res = (A.x - B.x) * (A.x - B.x) + (A.y - B.y) * (A.y - B.y); return res; } template <typename T> inline long long CROSS(T A, T B, T C) { return (B.x - A.x) * (C.y - A.y) - (C.x - A.x) * (B.y - A.y); } template <typename T> inline double cosAngle(T a, T b, T c) { double res = a * a + b * b - c * c; res = res / (2 * a * b); res = acos(res); return res; } template <typename T> inline T POWER(T base, int po) { T res = 1; if (base == 0) return 0; for (int i = (0); i < (po); i++) res *= base; return res; } template <typename T> inline bool IS_ON(T mask, T pos) { return mask & (1 << pos); } template <typename T> inline int OFF(T mask, T pos) { return mask ^ (1 << pos); } template <typename T> inline int ON(T mask, T pos) { return mask | (1 << pos); } template <typename T> inline bool INSIDE_GRID(int R, int C, int ro, int clm) { if (R >= 0 && C >= 0 && R < ro && C < clm) return 1; return 0; } template <typename T> inline void PRINT_GRID(T GRID, int ro, int clm) { cout << GRID << : << GRID << endl; for (int i = (0); i < (ro); i++) { for (int j = (0); j < (clm); j++) cout << GRID[i][j] << ; puts( ); } } map<string, int> mp; pair<long long, long long> dp[800005]; vector<int> g[800005]; vector<int> gr[800005]; int stk[800008]; string str, str2; vector<string> inp; pair<long long, long long> Tolower(string &str) { int len = str.size(), r = 0; for (int i = (0); i < (len); i++) { str[i] = tolower(str[i]); if (str[i] == r ) r++; } return make_pair((long long)r, (long long)len); } int vis[800005], top = 0, rng; void trop(int u) { vis[u] = 1; for (int i = (g[u].size() - 1); i >= (0); i--) if (!vis[g[u][i]]) trop(g[u][i]); stk[++top] = u; } void manipul(int u, int papa) { vis[u] = 3; dp[u] = min(dp[u], dp[papa]); for (int i = (gr[u].size() - 1); i >= (0); i--) if (vis[gr[u][i]] != 3) manipul(gr[u][i], papa); } pair<long long, long long> DP(int pos) { if (vis[pos] != 2) { vis[pos] = 2; for (int i = (g[pos].size() - 1); i >= (0); i--) dp[pos] = min(dp[pos], DP(g[pos][i])); } return dp[pos]; } int main() { int n, m; int cnt = 1; int s, d, len, r; for (int i = (0); i < (800000); i++) dp[i] = make_pair(100000000000000LL, 100000000000000LL); scanf( %d , &n); pair<long long, long long> tmp; for (int i = (0); i < (n); i++) { cin >> str; tmp = Tolower(str); inp.push_back(str); if (mp.find(str) == mp.end()) mp[str] = cnt++; s = mp[str]; dp[s] = min(dp[s], tmp); } rng = cnt; scanf( %d , &m); for (int i = (0); i < (m); i++) { cin >> str >> str2; tmp = Tolower(str); tmp = Tolower(str2); if (mp.find(str) == mp.end()) mp[str] = cnt++; if (mp.find(str2) == mp.end()) mp[str2] = cnt++; s = mp[str]; d = mp[str2]; dp[d] = min(dp[d], tmp); dp[s] = min(dp[s], dp[d]); g[s].push_back(d); gr[d].push_back(s); } pair<long long, long long> res; res = make_pair(0, 0); for (int i = (0); i < (n); i++) { s = mp[inp[i]]; if (!vis[s]) trop(s); } for (int i = (top + 1 - 1); i >= (0); i--) { DP(stk[i]); } for (int i = (top + 1 - 1); i >= (0); i--) { if (vis[stk[i]] != 3) manipul(stk[i], stk[i]); } for (int i = (0); i < (n); i++) { s = mp[inp[i]]; res.first += dp[s].first; res.second += dp[s].second; } cout << res.first << << res.second << endl; return 0; } |
`timescale 1ns / 1ps
module satadd(a,b,mode,y);
input [11:0] a,b;
input [1:0] mode;
output [11:0] y;
wire aSign, bSign, rSign, cout, vFlag;
wire [12:0] r;
add13bit u1 (.a({1'b0,a}), .b({1'b0,b}), .s(r));
assign vFlag = (~aSign & ~bSign & rSign | aSign & bSign & ~rSign);
assign cout = r[12];
assign rSign = r[11];
//assign r = a + b;
assign aSign = a[11];
assign bSign = b[11];
//sign saturation
reg[11:0] sSatSum;
always @* begin
sSatSum = 'h000;
case(vFlag)
1'b0:
sSatSum = r[11:0];
1'b1:
begin
if(aSign == 1 & bSign == 1 & rSign == 0)
sSatSum = 'h800;
else
sSatSum = 'h7FF;
end
endcase
end
//unsign saturation
reg[11:0] uSatSum;
always @* begin
uSatSum = 'h000;
case(cout)
1'b0:
uSatSum = r[11:0];
1'b1:
uSatSum = 'hFFF;
endcase
end
//4x1 mux
reg[11:0] result;
always @* begin
result = 'h000;
case(mode)
2'b00:
result = uSatSum;
2'b01:
result = sSatSum;
2'b10:
result = r[11:0];
2'b11:
result = r[11:0];
endcase
end
assign y = result;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { double a, b, c, delta, x1, x2; cin >> a >> b >> c; delta = b * b - 4.0 * a * c; delta = sqrt(delta); x1 = (-b + delta) / (2.0 * a); x2 = (-b - delta) / (2.0 * a); if (x1 < x2) swap(x1, x2); cout << fixed << setprecision(8) << x1 << endl << fixed << setprecision(8) << x2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, t, a, b, da, db; cin >> x >> t >> a >> b >> da >> db; for (int i = 0; i < t; i++) for (int h = 0; h <= 1; h++) for (int j = 0; j < t; j++) for (int s = 0; s <= 1; s++) if (((a - (da * i)) * h) + ((b - (db * j)) * s) == x) { cout << YES << endl; return 0; } cout << NO << endl; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9625 (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
adc_sref,
adc_raddr_in,
adc_raddr_out,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [255:0] rx_data;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [255:0] adc_data;
input adc_dovf;
input adc_dunf;
output [ 15:0] adc_sref;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [ 31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [191:0] adc_data_s;
wire adc_or_s;
wire adc_status_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [ 31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_rack <= up_rack_s[0] | up_rack_s[1] ;
up_wack <= up_wack_s[0] | up_wack_s[1] ;
end
end
// main (device interface)
assign adc_valid = 1'b1;
axi_ad9625_if #(.PCORE_ID(PCORE_ID)) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.adc_sref (adc_sref),
.adc_raddr_in (adc_raddr_in),
.adc_raddr_out (adc_raddr_out));
// channel
axi_ad9625_channel i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_dfmt_data (adc_data),
.adc_enable (adc_enable),
.up_adc_pn_err (up_adc_pn_err_s),
.up_adc_pn_oos (up_adc_pn_oos_s),
.up_adc_or (up_adc_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_adc_pn_err_s),
.up_status_pn_oos (up_adc_pn_oos_s),
.up_status_or (up_adc_or_s),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
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