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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 15; struct tree { int l, r, sum; tree *left, *right; tree(int L, int R, int val) { l = L, r = R, sum = val; left = right = NULL; } }; tree *pq[N], *db[N]; tree *update(tree *cur, int l, int r, int ind, int add) { tree *ret = new tree(l, r, 0); ret->sum += cur->sum + add; if (l == r) { ret->sum = cur->sum; ret->sum += add; return ret; } int mid = (l + r) / 2; if (ind <= mid) { if (!cur->left) { cur->left = new tree(l, mid, 0); } ret->right = cur->right; ret->left = update(cur->left, l, mid, ind, add); } else { if (!cur->right) { cur->right = new tree(mid + 1, r, 0); } ret->right = update(cur->right, mid + 1, r, ind, add); ret->left = cur->left; } return ret; } int getval(tree *cur, int l, int r, int ind) { if (l == r) { return cur->sum; } int mid = (l + r) / 2; if (ind <= mid) { if (!cur->left) return 0; return getval(cur->left, l, mid, ind); } else { if (!cur->right) return 0; return getval(cur->right, mid + 1, r, ind); } } int count(tree *cur, int l, int r, int ind) { if (cur == NULL) return 0; if (ind < l) { return 0; } if (r <= ind) { return cur->sum; } int mid = (l + r) / 2; int ret = 0; if (cur->left) ret = count(cur->left, l, mid, ind); if (cur->right) ret += count(cur->right, mid + 1, r, ind); return ret; } map<string, int> Hash; int main() { int q, i; string s, name; int pos = 1; int x; cin >> q; int n = 1e5; int m = 1e9; int C = 0, v; pq[C] = new tree(1, n, -1); db[C] = new tree(1, m, 0); while (q--) { cin >> s; if (s[0] == u ) { scanf( %d , &x); pq[C + 1] = pq[C - x]; db[C + 1] = db[C - x]; } else { cin >> name; if (!Hash.count(name)) { Hash[name] = pos++; } int id = Hash[name]; if (s[0] == s ) { scanf( %d , &x); v = getval(pq[C], 1, n, id); if (v != 0) { pq[C + 1] = update(pq[C], 1, n, id, -v + x); db[C + 1] = update(db[C], 1, m, v, -1); db[C + 1] = update(db[C + 1], 1, m, x, 1); } else { pq[C + 1] = pq[C], db[C + 1] = db[C]; pq[C + 1] = update(pq[C + 1], 1, n, id, x); db[C + 1] = update(db[C + 1], 1, m, x, 1); } } else if (s[0] == q ) { pq[C + 1] = pq[C]; db[C + 1] = db[C]; v = getval(pq[C + 1], 1, n, id); if (v != 0) { printf( %d n , count(db[C + 1], 1, m, v - 1)); } else printf( -1 n ); } else { pq[C + 1] = pq[C]; db[C + 1] = db[C]; v = getval(pq[C + 1], 1, n, id); if (v != 0) { pq[C + 1] = update(pq[C + 1], 1, n, id, -v); db[C + 1] = update(db[C + 1], 1, m, v, -1); } } } ++C; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; int x1, y1, x2, y2; cin >> n; long long ans = 0; for (int i = 1; i <= n; i++) { cin >> x1 >> y1 >> x2 >> y2; ans += (long long)(x2 - x1 + 1) * (y2 - y1 + 1); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int t, n; long long a[100005]; int get_bit(long long x) { int ans = 0; while (x) { ans++; x >>= 1; } return ans; } int main() { int i, j; scanf( %d , &t); while (t--) { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %lld , &a[i]); int ans = 0, last = a[1]; for (i = 2; i <= n; i++) { if (a[i] >= last) { last = a[i]; continue; } ans = max(ans, get_bit(last - a[i])); } printf( %d n , ans); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4BB_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "unsmul.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_arrmul();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
arrmul am (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=(`w8+2'b01);
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=(`w16+2'b01);
a_op=`aluwmulou;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INFL = 1LL << 60; const long long INF = 1 << 30; long long MOD = 1000000007; vector<long long> dy = {0, 1, 0, -1, 1, 1, -1, -1, 0}; vector<long long> dx = {1, 0, -1, 0, 1, -1, 1, -1, 0}; void pres(double A, long long x = 10) { cout << fixed << setprecision(x) << A << endl; } void BinarySay(long long x, long long y = 60) { for (long long i = 0; i < (y); i++) cout << (x >> (y - 1 - i) & 1); cout << endl; } long long cnt_bit(long long x) { return __builtin_popcountll(x); } long long pow_long(long long x, long long k) { long long res = 1; while (k > 0) { if (k % 2) res *= x; x *= x; k /= 2; } return res; } long long pow_mod(long long x, long long k) { long long res = 1; while (k > 0) { if (k % 2) { res *= x; res %= MOD; } x *= x; x %= MOD; k /= 2; } return res; } long long inverse(long long x) { return pow_mod(x, MOD - 2); }; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long x, long long y) { return x / gcd(x, y) * y; }; vector<long long> Row[100010]; vector<long long> Col[100010]; void solve() { long long N, M, K; cin >> N >> M >> K; for (long long i = 0; i < (K); i++) { long long a, b; cin >> a >> b; Row[a].push_back(b); Col[b].push_back(a); } for (long long i = 0; i <= M + 1; i++) { Row[0].push_back(i); Col[i].push_back(0); Row[N + 1].push_back(i); Col[i].push_back(N + 1); } for (long long i = 0; i <= N + 1; i++) { Col[0].push_back(i); Row[i].push_back(0); Col[M + 1].push_back(i); Row[i].push_back(M + 1); } for (long long i = 0; i < (N + 1); i++) { sort(Row[i].begin(), Row[i].end()); Row[i].erase(unique(Row[i].begin(), Row[i].end()), Row[i].end()); } for (long long i = 0; i < (M + 1); i++) { sort(Col[i].begin(), Col[i].end()); Col[i].erase(unique(Col[i].begin(), Col[i].end()), Col[i].end()); } long long Cnt = 0; for (long long i = 1; i <= N; i++) { long long x = *lower_bound(Row[i].begin(), Row[i].end(), 1); if (x == 1) break; Cnt++; } if (Cnt == N * M - K) { cout << Yes << endl; return; } long long y = 1, x = 1; long long dir = 1; long long cnt = 1; long long L = 0, R = M + 1, U = 1, D = N + 1; while (true) { long long dif = -cnt; if (dir == 1) { long long nx = *lower_bound(Row[y].begin(), Row[y].end(), x); nx = min(nx - 1, R - 1); cnt += nx - x; x = nx; R = x; } if (dir == 2) { long long ny = *lower_bound(Col[x].begin(), Col[x].end(), y); ny = min(ny - 1, D - 1); cnt += ny - y; y = ny; D = y; } if (dir == 3) { auto itr = lower_bound(Row[y].begin(), Row[y].end(), x); itr--; long long nx = *itr; nx = max(nx + 1, L + 1); cnt += x - nx; x = nx; L = x; } if (dir == 4) { auto itr = lower_bound(Col[x].begin(), Col[x].end(), y); itr--; long long ny = *itr; ny = max(ny + 1, U + 1); cnt += y - ny; y = ny; U = y; } dif += cnt; if (dif == 0) break; dir++; if (dir == 5) dir = 1; } if (cnt == N * M - K) { cout << Yes << endl; } else { cout << No << endl; } } int main() { cin.tie(0); ios::sync_with_stdio(false); solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int x1, y1, x2, y2; int sum = 0; for (int i = 0; i < n; ++i) { cin >> x1 >> y1 >> x2 >> y2; sum += (abs(x2 - x1) + 1) * (abs(y2 - y1) + 1); } cout << sum; return 0; } |
#include <bits/stdc++.h> void initialize(int *arr, int length) { for (int i = 0; i < length; i++) arr[i] = 0; } int teams(int *arr, int length) { for (int i = 1; i < length; i++) { if (arr[i - 1] == 1 && arr[i] == 1) return 2; } return 1; } int main() { int queries, len, curr, sieve[100]; scanf( %d n , &queries); for (int i = 0; i < queries; i++) { initialize(sieve, 100); scanf( %d n , &len); for (int j = 0; j < len; j++) { scanf( %d , &curr); sieve[curr - 1] = 1; } scanf( n ); printf( %d n , teams(sieve, 100)); } return 0; } |
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_decoder #(parameter CHAR_COUNT=16, DELIMITER=0)
(
clk,
rst, //active high
config_valid,
config_chars, // an eight bit character for each checker
config_ranges, // two eight bit characters for each range checker (>=LOW, <LARGE)
config_conds, // one bit to indicate whether the checker should only match if the previous one in line matched
input_valid,
input_last,
input_char,
index_rewind,
output_valid,
output_data, // bitmask for each char and range matcher
output_index, // the sequence number of the character in the string
output_last // high for the last character (delimiter)
);
input clk;
input rst;
input config_valid;
input [CHAR_COUNT*8-1:0] config_chars;
input [(CHAR_COUNT/2)-1:0] config_ranges;
input [CHAR_COUNT-1:0] config_conds;
input input_valid;
input input_last;
input [7:0] input_char;
input index_rewind;
output reg output_valid;
output reg [CHAR_COUNT-1:0] output_data;
output reg [15:0] output_index;
output reg output_last;
reg [15:0] index;
reg in_reg_valid;
reg [7:0] in_reg_char;
reg in_reg_last;
wire [CHAR_COUNT:0] match_bits;
wire [CHAR_COUNT-1:0] intermediary;
assign match_bits[0] = 0;
genvar X;
generate
for (X=0; X < CHAR_COUNT; X=X+2)
begin: gen_charmatch
rem_halfrange #(.HIGH_HALF(0)) match_low (
.clk(clk),
.rst(rst),
.config_valid(config_valid),
.config_char(config_chars[X*8+7:X*8]),
.config_chained(config_conds[X]),
.config_range_en(1'b0),
.input_valid(input_valid),
.input_char(input_char),
.prev_matched(match_bits[X]),
.this_matched(match_bits[X+1]),
.low_smaller(),
.this_smaller(intermediary[X])
);
rem_halfrange #(.HIGH_HALF(1)) match_high (
.clk(clk),
.rst(rst),
.config_valid(config_valid),
.config_char(config_chars[(X+1)*8+7:(X+1)*8]),
.config_chained(config_conds[(X+1)]),
.config_range_en(config_ranges[(X+1)/2]),
.input_valid(input_valid),
.input_char(input_char),
.prev_matched(match_bits[(X+1)]),
.this_matched(match_bits[(X+1)+1]),
.low_smaller(intermediary[X]),
.this_smaller()
);
end
endgenerate
always @(posedge clk)
begin
if (rst) begin
output_valid <= 0;
in_reg_valid <= 0;
in_reg_last <= 0;
index <= 0;
end
else begin
in_reg_valid <= input_valid;
in_reg_char <= input_char;
in_reg_last <= input_last;
if (in_reg_valid) begin
index <= index+1;
//if (in_reg_char==DELIMITER) index <= 0;
if (in_reg_last==1) index <= 0;
end
output_valid <= in_reg_valid;
output_data <= match_bits[CHAR_COUNT:1];
output_last <= in_reg_last;//(in_reg_char==DELIMITER) ? 1 : 0;
output_index <= index;
if (index_rewind==1) begin
index <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n; cin >> n; if (n % 2 == 0) cout << NO << endl; else { cout << YES << endl; long long int b[(2 * n) + 1]; b[1] = 1; b[2 * n] = 2 * n; long long int i = n + 1; long long int j = 2; long long int k = 2; long long int flag = 1; while (k < 2 * n) { if (flag == 1) { b[i] = k; b[i + 1] = k + 1; k = k + 2; i = i + 2; flag = 0; } else { b[j] = k; b[j + 1] = k + 1; k = k + 2; j = j + 2; flag = 1; } } for (long long int i = 1; i <= 2 * n; i++) cout << b[i] << ; } } |
#include <bits/stdc++.h> using namespace std; const int Mod = (int)1e9 + 7; const int MX = 1073741822; const long long MXLL = 4e18; const int Sz = 1110111; inline void Read_rap() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); } inline void randomizer3000() { unsigned int seed; asm( rdtsc : =A (seed)); srand(seed); } void files(string problem) { if (fopen((problem + .in ).c_str(), r )) { freopen((problem + .in ).c_str(), r , stdin); freopen((problem + .out ).c_str(), w , stdout); } } int n; long long d[Sz], m[Sz], r[Sz], p[Sz]; bool used[Sz]; struct fenwick { int n; vector<vector<pair<int, int> > > t; fenwick(int n) : n(n), t(n + 1) {} void add(int x, int y, int id) { for (int i = x; i <= n; i |= (i + 1)) t[i].push_back(make_pair(y, id)); } void preSort() { for (int i = 0; i <= n; i++) sort(t[i].begin(), t[i].end(), [](pair<int, int> a, pair<int, int> b) { return a > b; }); } void expand(int x, int y, queue<int> &q) { for (int i = x; i >= 0; i = (i & (i + 1)) - 1) { while ((int)(t[i].size()) && t[i].back().first <= y) { int id = t[i].back().second; if (!used[id]) { used[id] = 1; q.push(id); } t[i].pop_back(); } } } }; int Bfs(int st) { fenwick T(2 * (n + 1)); for (int i = 1; i <= n; i++) T.add(m[i], d[i], i); T.preSort(); queue<int> q; q.push(st); int cnt = 0; while (!q.empty()) { int i = q.front(); q.pop(); int p = ::p[i]; int r = ::r[i]; T.expand(p, r, q); cnt++; } return cnt - 1; } void compress(long long a[], long long b[]) { static vector<long long> c; c.clear(); for (int i = 0; i <= n; i++) { c.push_back(a[i]); c.push_back(b[i]); } sort(c.begin(), c.end()); for (int i = 0; i <= n; i++) a[i] = lower_bound(c.begin(), c.end(), a[i]) - c.begin(); for (int i = 0; i <= n; i++) b[i] = lower_bound(c.begin(), c.end(), b[i]) - c.begin(); } long long dist(int x, int y) { return x * 1ll * x + y * 1ll * y; } int main() { int sx, sy; scanf( %d %d %d %d %d , &sx, &sy, p + 0, r + 0, &n); for (int i = 1; i <= n; i++) { int x, y; scanf( %d %d %d %d %d , &x, &y, m + i, p + i, r + i); d[i] = dist(x - sx, y - sy); } for (int i = 0; i <= n; i++) r[i] *= r[i]; compress(r, d); compress(p, m); cout << Bfs(0); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const int INF = 0x3f3f3f3f; int m, n, c[N], cnt[N]; vector<int> g[N]; int bit[N]; void add(int x, int t) { for (; x <= n; x += x & -x) bit[x] += t; } int ask(int x) { int ret = 0; for (; x > 0; x -= x & -x) ret += bit[x]; return ret; } struct Que { int p, c, ret; } q[N]; vector<int> geet[N]; int st[N], ed[N], clk, sz[N], son[N], mat[N]; void predfs(int u, int f) { st[u] = ++clk, mat[clk] = u, son[u] = -1, sz[u] = 1; for (int i = 0; i < (int)g[u].size(); ++i) { int v = g[u][i]; if (v == f) continue; predfs(v, u); sz[u] += sz[v]; if (son[u] == -1 || sz[v] > sz[son[u]]) son[u] = v; } ed[u] = clk; } void dfs(int u, int f, bool keep) { for (int i = 0; i < (int)g[u].size(); ++i) { int v = g[u][i]; if (v == f || v == son[u]) continue; dfs(v, u, 0); } if (son[u] != -1) dfs(son[u], u, 1); ++cnt[c[u]]; if (cnt[c[u]] - 1 > 0) add(cnt[c[u]] - 1, -1); add(cnt[c[u]], 1); for (int i = 0; i < (int)g[u].size(); ++i) { int v = g[u][i]; if (v == f || v == son[u]) continue; for (int j = st[v]; j <= ed[v]; ++j) { ++cnt[c[mat[j]]]; if (cnt[c[mat[j]]] - 1 > 0) add(cnt[c[mat[j]]] - 1, -1); add(cnt[c[mat[j]]], 1); } } for (int i = 0; i < (int)geet[u].size(); ++i) { int id = geet[u][i]; q[id].ret = ask(n) - ask(min(n, q[id].p - 1)); } if (!keep) { for (int i = st[u]; i <= ed[u]; ++i) { add(cnt[c[mat[i]]], -1); --cnt[c[mat[i]]]; if (cnt[c[mat[i]]]) add(cnt[c[mat[i]]], 1); } } } int main() { while (~scanf( %d%d , &n, &m)) { for (int i = 1; i <= n; ++i) { scanf( %d , &c[i]); } for (int i = 0; i < N; ++i) g[i].clear(), geet[i].clear(); memset(bit, 0, sizeof(bit)); memset(cnt, 0, sizeof(cnt)); clk = 0; for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } predfs(1, 0); for (int i = 1; i <= m; ++i) { int u; scanf( %d%d , &u, &q[i].p); geet[u].push_back(i); } dfs(1, 0, 1); for (int i = 1; i <= m; ++i) { printf( %d n , q[i].ret); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; int a[1003][1003], p[maxn], num[maxn], n, m, vis[1003][1003]; long long k; int dx[4] = {1, -1, 0, 0}; int dy[4] = {0, 0, 1, -1}; int fi(int x) { return p[x] == x ? x : p[x] = fi(p[x]); } void uni(int x, int y) { int p1 = fi(x), p2 = fi(y); if (p1 == p2) return; p[p1] = p2; num[p2] += num[p1]; num[p1] = 0; } struct node { int x, y, z; node(int x1, int y1, int z1) { x = x1, y = y1, z = z1; } }; bool cmp(node a, node b) { return a.x > b.x; } vector<node> Q; void solve(int x, int y, int z, int v) { queue<node> Q; Q.push(node(x, y, 0)); vis[x][y] = 1; z--; while (!Q.empty()) { node now = Q.front(); Q.pop(); for (int i = 0; i < 4; i++) { int xx = now.x + dx[i]; int yy = now.y + dy[i]; if (z == 0) continue; if (xx <= 0 || xx > n) continue; if (yy <= 0 || yy > m) continue; if (vis[xx][yy]) continue; if (a[xx][yy] < v) continue; vis[xx][yy] = 1, z--; Q.push(node(xx, yy, 0)); } } for (int i = 1; i <= n; i++, cout << endl) for (int j = 1; j <= m; j++) if (vis[i][j]) printf( %d , v); else printf( 0 ); } int main() { scanf( %d%d%lld , &n, &m, &k); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &a[i][j]), Q.push_back(node(a[i][j], i, j)); for (int i = 0; i < maxn; i++) p[i] = i, num[i] = 1; sort(Q.begin(), Q.end(), cmp); for (int i = 0; i < Q.size(); i++) { int v = Q[i].x; if (v == 0) break; int x = Q[i].y; int y = Q[i].z; for (int j = 0; j < 4; j++) { int xx = x + dx[j]; int yy = y + dy[j]; if (a[xx][yy] >= v) uni((xx - 1) * m + yy, (x - 1) * m + y); } long long Num = k / v; if (k % v) continue; int fa = fi((x - 1) * m + y); if (Num <= num[fa]) { printf( YES n ); solve(x, y, Num, v); return 0; } } printf( NO n ); } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file memoria.v when simulating
// the core, memoria. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module memoria(
clka,
addra,
douta
);
input clka;
input [13 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("memoria.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(11264),
.C_READ_DEPTH_B(11264),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(11264),
.C_WRITE_DEPTH_B(11264),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Sep 20 15:46:23 2016
// Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/jacobwei/Public/project_1/project_1.srcs/sources_1/ip/ila_0/ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2015.2" *)
module ila_0(clk, trig_out, trig_out_ack, trig_in, trig_in_ack, probe0)
/* synthesis syn_black_box black_box_pad_pin="clk,trig_out,trig_out_ack,trig_in,trig_in_ack,probe0[0:0]" */;
input clk;
output trig_out;
input trig_out_ack;
input trig_in;
output trig_in_ack;
input [0:0]probe0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:35:06 04/15/2014
// Design Name:
// Module Name: diff_d2e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module diff_e2m(
clk,clrn,
ewreg,em2reg,ewmem,erd,eresult,eqb,esdepend,
mwreg,mm2reg,mwmem,mrd,mresult,mqb,msdepend
);
input clk,clrn;
input ewreg,em2reg,ewmem;
input[4:0] erd;
input[31:0] eresult,eqb;
input[1:0] esdepend;
output mwreg,mm2reg,mwmem;
output[4:0] mrd;
output[31:0] mresult,mqb;
output[1:0] msdepend;
dff1 push_wreg(ewreg,clk,clrn,mwreg);
dff1 push_m2reg(em2reg,clk,clrn,mm2reg);
dff1 push_wmem(ewmem,clk,clrn,mwmem);
dff5 push_rd(erd,clk,clrn,mrd);
dff32 push_result(eresult,clk,clrn,mresult);
dff32 push_qb(eqb,clk,clrn,mqb);
dff2 push_sdepend (esdepend,clk,clrn,msdepend);
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Merges two Wishbone busses onto a single bus. One side can from the --
// -- instruction cache while the other from data cache. This module can --
// -- be used to connect any 2 generic Wishbone devices. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_wb_merger (
// Clock and reset
input wire i_clk,
input wire i_reset,
// Wishbone bus 1
input wire i_c_wb_stb,
input wire i_c_wb_cyc,
input wire i_c_wb_wen,
input wire [3:0] i_c_wb_sel,
input wire [31:0] i_c_wb_dat,
input wire [31:0] i_c_wb_adr,
input wire [2:0] i_c_wb_cti,
output reg o_c_wb_ack,
// Wishbone bus 2
input wire i_d_wb_stb,
input wire i_d_wb_cyc,
input wire i_d_wb_wen,
input wire [3:0] i_d_wb_sel,
input wire [31:0] i_d_wb_dat,
input wire [31:0] i_d_wb_adr,
input wire [2:0] i_d_wb_cti,
output reg o_d_wb_ack,
// Common bus
output reg o_wb_cyc,
output reg o_wb_stb,
output reg o_wb_wen,
output reg [3:0] o_wb_sel,
output reg [31:0] o_wb_dat,
output reg [31:0] o_wb_adr,
output reg [2:0] o_wb_cti,
input wire i_wb_ack
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
localparam CODE = 1'd0;
localparam DATA = 1'd1;
reg sel_ff, sel_nxt;
always @ (posedge i_clk)
begin
if ( i_reset )
sel_ff <= CODE;
else
sel_ff <= sel_nxt;
end
always @*
begin
if ( sel_ff == CODE )
begin
o_c_wb_ack = i_wb_ack;
o_d_wb_ack = 1'd0;
end
else
begin
o_d_wb_ack = i_wb_ack;
o_c_wb_ack = 1'd0;
end
end
always @*
begin
sel_nxt = sel_ff;
case(sel_ff)
CODE:
begin
if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_d_wb_stb )
sel_nxt = DATA;
else if ( !i_c_wb_stb && i_d_wb_stb )
sel_nxt = DATA;
else
sel_nxt = sel_ff;
end
DATA:
begin
if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_c_wb_stb )
sel_nxt = CODE;
else if ( i_c_wb_stb && !i_d_wb_stb )
sel_nxt = CODE;
else
sel_nxt = sel_ff;
end
endcase
end
always @ (posedge i_clk)
begin
if ( i_reset )
begin
o_wb_cyc <= 0;
o_wb_stb <= 0;
o_wb_wen <= 0;
o_wb_sel <= 0;
o_wb_dat <= 0;
o_wb_adr <= 0;
o_wb_cti <= 0;
end
else if ( sel_nxt == CODE )
begin
o_wb_cyc <= i_c_wb_cyc;
o_wb_stb <= i_c_wb_stb;
o_wb_wen <= i_c_wb_wen;
o_wb_sel <= i_c_wb_sel;
o_wb_dat <= i_c_wb_dat;
o_wb_adr <= i_c_wb_adr;
o_wb_cti <= i_c_wb_cti;
end
else
begin
o_wb_cyc <= i_d_wb_cyc;
o_wb_stb <= i_d_wb_stb;
o_wb_wen <= i_d_wb_wen;
o_wb_sel <= i_d_wb_sel;
o_wb_dat <= i_d_wb_dat;
o_wb_adr <= i_d_wb_adr;
o_wb_cti <= i_d_wb_cti;
end
end
endmodule
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct node { int l, r, id; bool operator<(const node& nd) const { return l == nd.l ? r > nd.r : l < nd.l; } } a[300010]; int main() { int n; scanf( %d , &n); for (int i = (0); i < (n); ++i) { scanf( %d%d , &a[i].l, &a[i].r); a[i].id = i; } sort(a, a + n); int idx = 0; for (int i = (1); i < (n); ++i) { if (a[i].r <= a[idx].r) { printf( %d %d n , a[i].id + 1, a[idx].id + 1); return 0; } else { idx = i; } } puts( -1 -1 ); return 0; } |
module pcie_axi_bridge (
// PCI Express Fabric Interface
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
// Transaction (TRN) Interface
output user_lnk_up,
// Tx
output s_axis_tx_tready,
input [31:0] s_axis_tx_tdata,
input [3:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
output [5:0] tx_buf_av,
output tx_err_drop,
input tx_cfg_gnt,
output tx_cfg_req,
// Rx
output [31:0] m_axis_rx_tdata,
output [3:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
// Flow Control
input [2:0] fc_sel,
output [7:0] fc_nph,
output [11:0] fc_npd,
output [7:0] fc_ph,
output [11:0] fc_pd,
output [7:0] fc_cplh,
output [11:0] fc_cpld,
// Host (CFG) Interface
output [31:0] cfg_do,
output cfg_rd_wr_done,
input [9:0] cfg_dwaddr,
input cfg_rd_en,
// Configuration: Error
input cfg_err_ur,
input cfg_err_cor,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
// Conifguration: Interrupt
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
output [7:0] cfg_interrupt_do,
input [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
// Configuration: Power Management
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_pm_wake,
// Configuration: System/Status
output [2:0] cfg_pcie_link_state,
input cfg_trn_pending,
input [63:0] cfg_dsn,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// System Interface
input sys_clk_p,
input sys_clk_n,
input sys_reset,
output user_clk_out,
output user_reset_out,
output received_hot_reset
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; char ara[100][100]; int fr[100], fc[100]; vector<int> r, c; int pr; void row(int j); void col(int j) { fc[j] = 1; c.push_back(j); for (int i = 0; i < n; i++) if (ara[i][j] == # ) if (fr[i] == 0) row(i); } void row(int i) { fr[i] = 1; r.push_back(i); for (int j = 0; j < m; j++) if (ara[i][j] == # ) if (fc[j] == 0) col(j); } int check() { for (int i = 0; i < r.size(); i++) { for (int j = 0; j < c.size(); j++) { if (ara[r[i]][c[j]] == . ) return 1; } } return 0; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> ara[i][j]; } } for (int j = 0; j < m; j++) { if (fc[j] == 0) { pr++; c.clear(); r.clear(); col(j); if (check()) { cout << No n ; return 0; } } } cout << Yes n ; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); $stop; end while(0)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc= 64'h5aef0c8d_d70a4497;
reg [63:0] prev_crc;
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
prev_crc <= crc;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
wire cond2 = &crc[1:0];
wire cond3 = &crc[2:0];
reg shuf_q [63:0];
always @(posedge clk) begin
reg bits [63:0];
reg shuf_a [63:0];
reg shuf_b [63:0];
reg shuf_c [63:0];
reg shuf_d [63:0];
reg shuf_e [63:0];
// Unpack these to test core algorithm
for (int i = 0; i < 64; i = i + 1) begin
bits[i] = crc[i];
end
for (int i = 0; i < 64; i = i + 1) begin
shuf_a[i] = cyc[0] ? bits[i] : bits[63-i];
end
if (cyc[1]) begin
for (int i = 0; i < 64; i = i + 1) begin
shuf_b[i] = cyc[0] ? bits[i] : bits[63-i];
end
end else begin
for (int i = 0; i < 64; i = i + 1) begin
shuf_b[i] = cyc[0] ? bits[63-i] : bits[i];
end
end
// Also test merge under clean/bit extract
for (int i = 0; i < 64; i = i + 1) begin
shuf_c[i] = cyc[0] ? crc[i] : crc[63-i];
end
// Merge with 'cond & value', 'value & cond', or 'cond'
shuf_d[0] = cond2 ? bits[0] : bits[63];
for (int i = 1; i < 32; i = i + 2) begin
shuf_d[i] = cond2 & bits[i];
end
for (int i = 2; i < 32; i = i + 2) begin
shuf_d[i] = bits[i] & cond2;
end
for (int i = 32; i < 64; i = i + 1) begin
shuf_d[i] = cond2;
end
// Merge with an '&' also used for masking of LSB.
shuf_e[0] = cond3 ? bits[0] : bits[63];
for (int i = 1; i < 64; i = i + 1) begin
shuf_e[i] = cond3 & crc[0];
end
// Also delayed..
for (int i = 0; i < 64; i = i + 1) begin
shuf_q[i] <= cyc[0] ? crc[i] : crc[63-i];
end
// Check results
if (cyc[0]) begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[i]);
end else begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[63-i]);
end
if (cyc[0] ~^ cyc[1]) begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[i]);
end else begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[63-i]);
end
if (cyc[0]) begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[i]);
end else begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[63-i]);
end
if (cond2) begin
`check(shuf_d[0], crc[0]);
for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], crc[i]);
for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd1);
end else begin
`check(shuf_d[0], crc[63]);
for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], 1'b0);
for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd0);
end
if (cond3) begin
`check(shuf_e[0], crc[0]);
for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], crc[0]);
end else begin
`check(shuf_e[0], crc[63]);
for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], 1'b0);
end
if (cyc > 0) begin
if (~cyc[0]) begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[i]);
end else begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[63-i]);
end
if (((cyc - 1) >> 1) % 2 == 1) begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[i]);
end else begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[63-i]);
end
end
if (cyc[2]) begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[i]);
end else begin
for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[63-i]);
end
end
// Generated always
reg shuf_g [63:0];
generate for (genvar i = 0 ; i < 64; i = i + 1)
always @(posedge clk) begin
shuf_g[i] <= cyc[1] ? crc[i] : crc[63-i];
end
endgenerate
// Generated assign
wire shuf_w [63:0];
generate for (genvar i = 0 ; i < 64; i = i + 1)
assign shuf_w[i] = cyc[2] ? crc[i] : crc[63-i];
endgenerate
// Things not to merge
always @(posedge clk) begin
reg bits [63:0];
reg x;
reg y;
reg z;
reg w;
// Unpack these to test core algorithm
for (int i = 0; i < 64; i = i + 1) begin
bits[i] = crc[i];
end
// Do not merge if condition appears in an LVALUE
x = bits[0];
y = x ? bits[2] : bits[1];
x = x ? bits[3] : bits[4];
x = x ? bits[5] : bits[6];
`check(x, (bits[0] ? bits[3] : bits[4]) ? bits[5] : bits[6]);
`check(y, bits[0] ? bits[2] : bits[1]);
// However do merge when starting a new list in the same block with the
// previous condition variable, but without the condition being an LVALUE
x = cond2 ? bits[0] : bits[1];
y = cond2 & bits[2];
z = cond2 & bits[3];
w = cond2 & bits[4];
`check(x, cond2 ? bits[0] : bits[1]);
`check(y, cond2 & bits[2]);
`check(z, cond2 & bits[3]);
`check(w, cond2 & bits[4]);
// Do not merge if condition is not a pure expression
$c("int _cnt = 0;");
x = $c("_cnt++") ? bits[0] : bits[1];
y = $c("_cnt++") ? bits[2] : bits[3];
z = $c("_cnt++") ? bits[4] : bits[5];
w = $c("_cnt++") ? bits[6] : bits[7];
$c("if (_cnt != 4) abort();");
`check(x, bits[1]);
`check(y, bits[2]);
`check(z, bits[4]);
`check(w, bits[6]);
// Do not merge with assignment under other statement
x = cond2 ? bits[0] : bits[1];
if (bits[1]) begin
y = cond2 ? bits[2] : bits[3];
end
`check(x, cond2 ? bits[0] : bits[1]);
if (bits[1]) begin
`check(y, cond2 ? bits[2] : bits[3]);
end
// Do not merge with assignment under other statement
x = cond2 ? bits[0] : bits[1];
if (bits[1]) begin
y = cond2 & bits[2];
end
`check(x, cond2 ? bits[0] : bits[1]);
if (bits[1]) begin
`check(y, cond2 & bits[2]);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_4_V
`define SKY130_FD_SC_HD__SDFRTP_4_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_4_V
|
/*
* File: pippo_alu.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Assigner:
* Description:
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* Task:
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*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_alu(
clk, rst,
alu_uops, bus_a, bus_b,
sh_mb_me,
result
);
parameter width = `OPERAND_WIDTH;
//
input clk;
input rst;
input [`ALUUOPS_WIDTH-1:0] alu_uops;
input [width-1:0] bus_a;
input [width-1:0] bus_b;
input reg_zero;
input [14:0] sh_mb_me;
output [width-1:0] result;
// global wires in module
wire [width-1:0] bus_a;
wire [width-1:0] bus_b;
//
// Logic
//
wire [`ALUOP_WIDTH-1:0] alu_op;
assign alu_op = alu_uops[`ALUOP_WIDTH-1:0];
//
// barrel shifter
//
wire [5:0] shrot_cnt;
wire shift_arith;
wire shift_left;
wire shift_mode_32b
// shrot operands
assign shrot_cnt = alu_op[`ALUOP_SHTEN_BIT] ? bus_b[5:0] : 6'b0;
// control signals
assign shift_mode_32b = alu_op[`ALUOP_M32B_BIT];
assign shift_left = alu_op[`ALUOP_LFT_BIT];
assign shift_arith = alu_op[`ALUOP_AGM_BIT];
// shifted result
wire [width-1:0] shrot_result;
pippo_barrel pippo_barrel (
.shift_in(bus_a),
.shift_cnt(shrot_cnt),
.shift_left(shift_left),
.shift_arith(shift_arith),
.shift_mode_32b(shift_mode_32b),
.shrot_out(shrot_result)
);
//
// multiplier for 32x32
//
//wire [63:0] mul_out, mul_out_a;
//reg [31:0] mul_result;
//wire [31:0] bus_a_u;
//wire [31:0] bus_b_u;
//wire [31:0] opa;
//wire [31:0] opb;
//assign tag_unsigned = (alu_op == `ALUOP_MULHWU);
//assign mul_sign = bus_a[31] ^ bus_b[31];
//assign bus_a_u = bus_a[31] ? (~bus_a + 32'd1) : bus_a;
//assign bus_b_u = bus_b[31] ? (~bus_b + 32'd1) : bus_b;
//assign opa = tag_unsigned ? bus_a : {1'b0, bus_a_u[30:0]};
//assign opb = tag_unsigned ? bus_b : {1'b0, bus_b_u[30:0]};
// unsigned multiplier
//pippo_mul32x32 pippo_mul32x32 (
// .clk(clk),
// .rst(rst),
// .opa(opa),
// .opb(opb),
// .result(mul_out_a)
//);
// adjust the sign bit of result
// 1, if unsigned instruction, nothing to do
// 2, if positive mulitply negative, transfer the absolute result to negative value
// Notes: it doesn't matter for the last case: actually it's a 31*31 multiplication
//assign mul_out = tag_unsigned ? mul_out_a[63:0] : (mul_sign ? (~mul_out_a + 1'd1): {1'b0, mul_out_a[62:0]});
//assign mul_out = tag_unsigned ? mul_out_a[63:0] : (mul_sign ? (~mul_out_a + 1'd1): mul_out_a[63:0]);
//always @(alu_op or mul_out or mul_sign) begin
// mul_result=32'd0;
// casex (alu_op) // synopsys parallel_case
// `ALUOP_MULHWU: begin
// mul_result = mul_out[63:32];
// end
// `ALUOP_MULHW: begin
// mul_result = mul_out[31:0];
// end
// `ALUOP_MULLI: begin
// mul_result = mul_out[31:0];
// end
// `ALUOP_MULLW: begin
// mul_result = mul_out[31:0];
// end
// default: begin
// mul_result = mul_out[31:0];
// end
// endcase
//end
//
// hardware divider
//
//`ifdef pippo_DIV_IMPLEMENTED
//module pippo_div64x32 (
// clk(),
// ena(),
// z(),
// d(),
// q(),
// s(),
// ovf(),
// div0()
//);
//`endif
//
// ALU
//
reg [width-1:0] result;
wire [width-1:0] cmp_a, cmp_b;
assign cmp_a = {bus_a[width-1] ^ alu_uops[`ALUOP_SCMP_BIT], bus_a[width-2:0]};
assign cmp_b = {bus_b[width-1] ^ alu_uops[`ALUOP_SCMP_BIT], bus_b[width-2:0]};
always @(alu_op or bus_a or bus_b or cmp_a or cmp_b or shrot_result ) begin
result = 64'd0;
casex (alu_op) // synopsys parallel_case
// arithmetic
`ALUOP_ADD : begin
result = bus_a + bus_b;
end
`ALUOP_SUB : begin
result = bus_b - bus_a;
end
// logic
`ALUOP_AND : begin
result = bus_a & bus_b;
end
`ALUOP_OR : begin
result = bus_a | bus_b;
end
`ALUOP_XOR : begin
result = bus_a ^ bus_b;
end
`ALUOP_SLT, `ALUOP_SLTU: begin
result = (cmp_a < cmp_b);
end
// barrel shifter
`ALUOP_SLL, `ALUOP_SRL, `ALUOP_SRA,
`ALUOP_SLLW, `ALUOP_SRLW, `ALUOP_SRAW: begin
result = shrot_result;
end
// multiplier
// `ifdef pippo_MULT_IMPLEMENTED
// `ALUOP_MULHWU, `ALUOP_MULHW, `ALUOP_MULLI, `ALUOP_MULLW: begin
// result = mul_result;
// end
// `endif
endcase
end
//
// Simulation check for bad ALU behavior
//
`ifdef pippo_WARNINGS
// synopsys translate_off
always @(result) begin
if (result === 32'bx)
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1061109567; const long long LINF = 4557430888798830399ll; void TestCase() { long long d; scanf( %lld , &d); d %= 360; if (d < 0) d += 360; int ans = INF, cnt = 0; for (int i = 0; i < 4; ++i) { int nd = abs(d - 90 * i); if (min(nd, 360 - nd) < ans) { ans = min(nd, 360 - nd); cnt = i; } } printf( %d n , cnt); } int main() { int t = 1; for (int i = 1; i <= t; ++i) { TestCase(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010, maxs = 200010; const int inf = 2000000000; int n, m, ecnt; pair<int, int> edges[maxs]; bool dat[maxn]; int c[maxn]; int pos[maxn], last[maxn], nowt; vector<pair<int, int> > ga[maxn]; vector<int> weight[maxn]; void insertunit(int* c, int pos, int x) { for (; pos <= n; pos += pos & (-pos)) c[pos] += x; } int querysum(int* c, int pos) { int ans = 0; for (; pos; pos -= pos & (-pos)) ans += c[pos]; return ans; } int lcaf[maxn][20], depth[maxn]; void dfs(int start = 1) { pos[start] = ++nowt; for (int i = 1; i < 20; i++) lcaf[start][i] = lcaf[lcaf[start][i - 1]][i - 1]; for (vector<pair<int, int> >::iterator it = ga[start].begin(); it != ga[start].end(); it++) { if (it->first != lcaf[start][0]) { lcaf[it->first][0] = start; depth[it->first] = depth[start] + 1; dfs(it->first); } } last[start] = nowt; } int lca(int x, int y) { if (depth[x] > depth[y]) swap(x, y); for (int i = 19; i >= 0; i--) if (lcaf[y][i] && depth[lcaf[y][i]] >= depth[x]) y = lcaf[y][i]; if (x == y) return x; for (int i = 19; i >= 0; i--) if (lcaf[x][i] != lcaf[y][i]) x = lcaf[x][i], y = lcaf[y][i]; return lcaf[x][0]; } void insertpath(int x, int y) { int u = lca(x, y); insertunit(c, pos[x], 1); insertunit(c, pos[y], 1); insertunit(c, pos[u], -1); if (depth[u]) insertunit(c, pos[lcaf[u][0]], -1); } int querynode(int x) { return querysum(c, last[x]) - querysum(c, pos[x] - 1); } pair<int, int> f[maxs]; bool vis[maxs]; pair<int, int> getf(int en) { if (ga[edges[en].first].size() == 1) if (dat[edges[en].first]) return make_pair(0, edges[en].first); else return make_pair(-inf, -1); if (vis[en]) return f[en]; vis[en] = true; int st = edges[en].first; int ed = edges[en].second; int nowmin = -inf, cnt = 0, nowlca = -1; if (dat[st]) { nowmin = 0; cnt = 1; nowlca = st; } int p = 0; for (vector<pair<int, int> >::iterator it = ga[st].begin(); it != ga[st].end(); it++, p++) if (it->first != ed) { pair<int, int> t = getf(it->second); if (t.second == -1) continue; t.first += weight[st][p]; if (t.first > nowmin) { nowmin = t.first; nowlca = t.second; cnt = 1; } else if (t.first == nowmin) cnt++; } if (cnt > 1) f[en] = make_pair(nowmin, st); else if (cnt == 1) f[en] = make_pair(nowmin, nowlca); else f[en] = make_pair(-inf, -1); return f[en]; } void processpath() { for (int i = 1; i <= n; i++) { if (dat[i]) { int nowmin = -inf, cnt = 0, nowlca = -1, p = 0; for (vector<pair<int, int> >::iterator it = ga[i].begin(); it != ga[i].end(); it++, p++) { pair<int, int> t = getf(it->second); if (t.second == -1) continue; t.first += weight[i][p]; if (t.first > nowmin) { nowmin = t.first; nowlca = t.second; cnt = 1; } else if (t.first == nowmin) { cnt++; } } if (cnt == 1) insertpath(i, nowlca); } } } pair<int, int> getans() { int nowmax = 0, cnt = 0; for (int i = 1; i <= n; i++) { if (dat[i]) continue; int t = querynode(i); if (t > nowmax) { nowmax = t; cnt = 1; } else if (t == nowmax) cnt++; } return make_pair(nowmax, cnt); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int x; scanf( %d , &x); dat[x] = true; } for (int i = 1; i < n; i++) { int x, y, w; scanf( %d%d%d , &x, &y, &w); edges[ecnt++] = make_pair(x, y); edges[ecnt++] = make_pair(y, x); ga[x].push_back(make_pair(y, ecnt - 1)); ga[y].push_back(make_pair(x, ecnt - 2)); weight[x].push_back(w); weight[y].push_back(w); } dfs(); processpath(); pair<int, int> t = getans(); printf( %d %d n , t.first, t.second); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_TB_V
`define SKY130_FD_SC_LS__A311OI_TB_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a311oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cclk_inv_48x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_cclk_inv_48x.behV
// --------------------------------------------------
//
module bw_clk_cclk_inv_48x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int num, a1, a2, b1, b2, c1, c2, d, a, b, c; cin >> num >> a1 >> a2 >> b1 >> b2 >> c1 >> c2; a = a2; b = b2; c = c2; if (a + b + c == num) cout << a << << b << << c; else { d = a + b + c - num; if (c - d >= c1) { c = c - d; d = 0; } else { d = d - c + c1; c = c1; } if (d > 0) if (b - d >= b1) { b = b - d; d = 0; } else { d = d - b + b1; b = b1; } if (d > 0) if (a - d >= a1) { a = a - d; d = 0; } else { d = d - a + a1; a = a1; } cout << a << << b << << c; } } |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_cobs_encode
*/
module test_axis_cobs_encode_zero_frame;
// Parameters
parameter APPEND_ZERO = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_cobs_encode_zero_frame.lxt");
$dumpvars(0, test_axis_cobs_encode_zero_frame);
end
axis_cobs_encode #(
.APPEND_ZERO(APPEND_ZERO)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v(100003); long long solve() { long long n; vector<long long> u; string s; cin >> n; while (n > 0) { auto itr = lower_bound((v).begin(), (v).end(), n); long long a = itr - v.begin(); if (v[a] > n) a--; u.push_back(a + 2); n = n - v[a]; } s.push_back( 1 ); long long j = 1; for (long long i = 0; i < u[0]; i++) { while (j < u.size() && i + u[j] == u[0]) { s.push_back( 1 ); j++; } s.push_back( 3 ); } s.push_back( 7 ); cout << s; return 0; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t = 1; cin >> t; v[0] = 1; for (long long i = 1; i < 100003; i++) v[i] = v[i - 1] + i + 1; while (t--) { solve(); cout << n ; } } |
/*
* Read rotary/quadrature encoder using the clock
*
*/
module quadrature_decoder(
CLOCK,
RESET,
A,
B,
COUNT_ENABLE,
DIRECTION,
SPEED
);
input CLOCK, RESET, A, B;
output COUNT_ENABLE;
output DIRECTION;
output [3:0] SPEED;
reg [2:0] A_delayed;
reg [2:0] B_delayed;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
A_delayed <= 0;
end else begin
A_delayed <= {A_delayed[1:0], A};
end
end
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
B_delayed <= 0;
end else begin
B_delayed <= {B_delayed[1:0], B};
end
end
assign COUNT_ENABLE = A_delayed[1] ^ A_delayed[2] ^ B_delayed[1] ^ B_delayed[2];
assign DIRECTION = A_delayed[1] ^ B_delayed[2];
assign SPEED = 4'd0;
/*
wire count_enable = A_delayed[1] ^ A_delayed[2] ^ B_delayed[1] ^ B_delayed[2];
wire count_direction = A_delayed[1] ^ B_delayed[2];
reg [31:0] total;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
total <= 0;
end
else if (count_enable) begin
// only want a final count between 0 & 27 (x4 for the clicks)
if (count_direction && total < 109) begin
total <= total+1;
end
else if (total > 0) begin
total <= total-1;
end
end
end
wire [31:0] clicks;
assign clicks = total >> 2; // divide by 4 as the encoder has 4 edges per "click"
assign COUNT = clicks[7:0];
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_SYMBOL_V
|
#include <bits/stdc++.h> int dx[] = {0, -1, 0, 1, -1, 1, -1, 1}; int dy[] = {-1, 0, 1, 0, 1, -1, -1, 1}; const int MOD = 1e9 + 7, N = 2e5 + 5, oo = 2e9; const double pi = acos(-1); using namespace std; long long day[N], h[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; long long ans = -1; for (int i = 0; i < m; i++) { cin >> day[i] >> h[i]; ans = max(ans, h[i]); if (i and day[i] - day[i - 1] < abs(h[i] - h[i - 1])) return cout << IMPOSSIBLE , 0; } ans = max(ans, h[0] + day[0] - 1); ans = max(ans, h[m - 1] + (n - day[m - 1])); for (int i = 1; i < m; i++) { long long dif = day[i] - day[i - 1], cur = h[i - 1]; if (h[i] > h[i - 1]) ans = max(ans, h[i] + (day[i] - day[i - 1] - abs(h[i] - h[i - 1])) / 2); else ans = max(ans, h[i - 1] + (day[i] - day[i - 1] - abs(h[i] - h[i - 1])) / 2); } cout << ans; return 0; } |
/*****************************************************************************/
//
// Module : bbox_wrap.v
// Revision : $$
// Last Modified On: $$
// Last Modified By: $$
//
//-----------------------------------------------------------------------------
//
// Original Author : Bryan Hornung
// Created On : Mon Feb 13 13:06:02 2012
//
//-----------------------------------------------------------------------------
//
// Description : top level interface of black box
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2012 : created by Convey Computer Corp. This model is the
// confidential and proprietary property of Convey Computer Corp.
//
/*****************************************************************************/
/* $Id: $ */
`timescale 1 ns / 1 ps
module bbox_wrap (
//outputs
vm, vt,
//inputs
intfClk1x, intfClk2x, reset,
scalar, arc0,
va, vb
);
input intfClk1x;
input intfClk2x;
input reset;
input [11:0] arc0;
input [63:0] scalar;
input [63:0] va;
input [63:0] vb;
output [63:0] vt; // result data
output vm; // match (unused in both verilog and cpp)
bbox_box_top bbox (
.o_result(vt), //
.o_vm(vm), //
.o_hit(),
.o_done(),
.o_error(),
.clk2x(intfClk1x), // bbox timed at 300 but we're running at 150
.clk1x(1'b0), // rset of clocks unused
.clkhx(1'b0),
.bb_clk1x(1'b0),
.bb_clk2x(1'b0),
.i_reset(reset),
.i_start(1'b1), // start a instruction each clock
.i_elemCnt(9'b00000001), // one element for each start
.i_scalar(scalar),
.i_vrA(va),
.i_vrB(vb),
.i_arc0(arc0[10:0]), // control
.i_arc1(1'b0), // unused
.i_arc2(1'b0), // unused
.i_arc3(1'b0) // unused
);
endmodule
|
<?
generics[0] := "CLKFX_DIVIDE";
generics[1] := "CLKFX_MULTIPLY";
generics[2] := "CLKIN_PERIOD";
-?>
module DIG_DCM_SP #(
parameter integer CLKFX_DIVIDE = 1,
parameter integer CLKFX_MULTIPLY = 2,
parameter real CLKIN_PERIOD = 10.0
)
(
input cin,
output cout
);
// DCM_SP: Digital Clock Manager
// Spartan-6
// Xilinx HDL Libraries Guide, version 14.1
DCM_SP #(
.CLKDV_DIVIDE(2.0), // CLKDV divide value
// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
.CLKFX_DIVIDE(CLKFX_DIVIDE), // Divide value on CLKFX outputs - D - (1-32)
.CLKFX_MULTIPLY(CLKFX_MULTIPLY), // Multiply value on CLKFX outputs - M - (2-32)
.CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
.CLKIN_PERIOD(CLKIN_PERIOD), // Input clock period specified in nS
.CLKOUT_PHASE_SHIFT("NONE"), //Output phase shift (NONE, FIXED, VARIABLE)
.CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X)
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
.DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
.DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
.DSS_MODE("NONE"), // Unsupported - Do not change value
.DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value
.FACTORY_JF(16'hc080), // Unsupported - Do not change value
.PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255)
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
DCM_SP_inst (
.CLK0(), // 1-bit output: 0 degree clock output
.CLK180(), // 1-bit output: 180 degree clock output
.CLK270(), // 1-bit output: 270 degree clock output
.CLK2X(), // 1-bit output: 2X clock frequency clock output
.CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output
.CLK90(), // 1-bit output: 90 degree clock output
.CLKDV(), // 1-bit output: Divided clock output
.CLKFX(cout), // 1-bit output: Digital Frequency Synthesizer output (DFS)
.CLKFX180(), // 1-bit output: 180 degree CLKFX output
.LOCKED(), // 1-bit output: DCM_SP Lock Output
.PSDONE(), // 1-bit output: Phase shift done output
.STATUS(), // 8-bit output: DCM_SP status output
.CLKFB(), // 1-bit input: Clock feedback input
.CLKIN(cin), // 1-bit input: Clock input
.DSSEN(1'b0), // 1-bit input: Unsupported, specify to GND.
.PSCLK(1'b0), // 1-bit input: Phase shift clock input
.PSEN(1'b0), // 1-bit input: Phase shift enable
.PSINCDEC(), // 1-bit input: Phase shift increment/decrement input
.RST(1'b0) // 1-bit input: Active high reset input
);
endmodule |
#include <bits/stdc++.h> using namespace std; char s[2004], temp[2004], e[2004], c, cnt; int n; int q[27]; void f(int x) { cnt++; if (cnt != n * 3) printf( %d , x); else printf( %d n , x); int i; for (i = n - x + 1; i <= n; i++) temp[n - i + 1] = s[i]; for (i = 1; i < n - x + 1; i++) temp[i + x] = s[i]; for (i = 1; i <= n; i++) s[i] = temp[i]; } int main() { int t, i, j, k, x, l1, l2, flag, o; scanf( %d , &t); scanf( %s , s + 1); scanf( %s , e + 1); l1 = strlen(s + 1); l2 = strlen(e + 1); if (l1 != l2) { printf( -1 n ); return 0; } memset(q, 0, sizeof(q)); for (i = 1; i <= l1; i++) { q[s[i] - a ]++; q[e[i] - a ]--; } flag = 1; for (i = 0; i < 26; i++) { if (q[i]) flag = 0; } if (flag == 0) { printf( -1 n ); return 0; } n = l1; printf( %d n , n * 3); cnt = 0; for (o = 0; o < n; o++) { f(n); c = e[n - o]; for (i = n - o; i >= 0; i--) { if (s[i] == c) break; } f(n - i); f(1); } return 0; } |
/*
* Palette register file for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_palette_regs (
input clk,
// VGA read interface
input [3:0] attr,
output reg [7:0] index,
// CPU interface
input [3:0] address,
input write,
output reg [7:0] read_data,
input [7:0] write_data
);
// Registers
reg [7:0] palette [0:15];
// Behaviour
// VGA read interface
always @(posedge clk) index <= palette[attr];
// CPU read interface
always @(posedge clk) read_data <= palette[address];
// CPU write interface
always @(posedge clk)
if (write) palette[address] <= write_data;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5, maxf = 1 << 18; const int mod = 998244353; namespace usual { int fac[maxf + 5], ifac[maxf + 5]; int add(int ta, int tb) { return ta + tb >= mod ? ta + tb - mod : ta + tb; } int sub(int ta, int tb) { return ta < tb ? ta - tb + mod : ta - tb; } int ksm(long long ta, int tp) { int s = 1; for (; tp; ta = ta * ta % mod, tp >>= 1) if (tp & 1) s = ta * s % mod; return s; } void make_fac(int len) { fac[0] = 1; for (int i = 1; i <= len; i++) fac[i] = 1ll * fac[i - 1] * i % mod; ifac[len] = ksm(fac[len], mod - 2); for (int i = len; i; i--) ifac[i - 1] = 1ll * ifac[i] * i % mod; } int inv(int i) { return 1ll * ifac[i] * fac[i - 1] % mod; } } // namespace usual using namespace usual; namespace poly { int pa[maxf + 5], pb[maxf + 5]; int rev[maxf + 5], g[maxf + 5], invg[maxf + 5]; void Cpy(int *A, int *B, int len) { for (int i = 0; i < len; i++) A[i] = B[i]; } void Rev(int *A, int len) { for (int i = 0; i < len - i; i++) swap(A[i], A[len - i]); } void Cl(int *A, int len) { memset(A, 0, len * 4); } void make_tt(int *T, int len, int da) { int tmp = ksm(da, (mod - 1) / len); for (int i = len >> 1; i; i >>= 1, tmp = 1ll * tmp * tmp % mod) { T[i] = 1; for (int j = 1; j < i; j++) T[i + j] = 1ll * T[i + j - 1] * tmp % mod; } } void pre_poly(int len) { make_tt(g, len, 3); make_tt(invg, len, 332748118); } void make_rev(int len) { for (int i = 1; i < len; i++) rev[i] = (rev[i >> 1] >> 1) | (i & 1 ? len >> 1 : 0); } void NTT(int *T, int len, bool ok) { int *tt, ny; for (int i = 1; i < len; i++) if (i < rev[i]) swap(T[i], T[rev[i]]); for (int i = 1; i < len; i <<= 1) { tt = ok ? g + i : invg + i; for (int j = 0; j < len; j += i << 1) for (int l = 0; l < i; l++) { ny = 1ll * T[i + j + l] * tt[l] % mod; T[i + j + l] = sub(T[j + l], ny); T[j + l] = add(T[j + l], ny); } } } void Mult(int *A, int *B, int *C, int len) { Cpy(pa, A, len); Cpy(pb, B, len); make_rev(len); NTT(pa, len, 1); NTT(pb, len, 1); for (int i = 0; i < len; i++) pa[i] = 1ll * pa[i] * pb[i] % mod; NTT(pa, len, 0); int invn = ksm(len, mod - 2); for (int i = 0; i < len; i++) C[i] = 1ll * pa[i] * invn % mod; } void Inv(int *T, int *Ans, int len) { static int tf[maxf + 5], tg[maxf + 5]; int invn; Cl(tf, len << 1); Cl(tg, len << 1); Cl(Ans, len << 1); Ans[0] = ksm(T[0], mod - 2); for (int i = 2; i <= len; i <<= 1) { Cpy(tf, Ans, i); Cpy(tg, T, i); make_rev(i << 1); NTT(tf, i << 1, 1); NTT(tg, i << 1, 1); for (int j = 0; j < i << 1; j++) tf[j] = 1ll * tf[j] * sub(2, 1ll * tf[j] * tg[j] % mod) % mod; NTT(tf, i << 1, 0); invn = ksm(i << 1, mod - 2); for (int j = 0; j < i; j++) Ans[j] = 1ll * tf[j] * invn % mod; } } void diff(int *T, int len) { for (int i = 1; i < len; i++) T[i - 1] = 1ll * T[i] * i % mod; T[len - 1] = 0; } void inte(int *T, int len) { for (int i = len - 1; i; i--) T[i] = 1ll * T[i - 1] * inv(i) % mod; T[0] = 0; } void Ln(int *T, int *Ans, int len) { static int invT[maxf + 5]; Cl(invT, len << 1); Cl(Ans, len << 1); Inv(T, invT, len); Cpy(Ans, T, len); diff(Ans, len); Mult(Ans, invT, Ans, len << 1); Cl(Ans + len, len); inte(Ans, len); } void Exp(int *T, int *Ans, int len) { static int lnT[maxf + 5]; Cl(Ans, len << 1); Ans[0] = 1; for (int i = 2; i <= len; i <<= 1) { Ln(Ans, lnT, i); for (int j = 0; j < i; j++) lnT[j] = sub(T[j], lnT[j]); lnT[0] = add(lnT[0], 1); Mult(Ans, lnT, Ans, i << 1); Cl(Ans + i, i); } } void Ksm(int *T, int *Ans, int len, int tp) { static int ts[maxf + 5]; Ln(T, ts, len); for (int i = 0; i < len; i++) ts[i] = 1ll * ts[i] * tp % mod; Exp(ts, Ans, len); } } // namespace poly using namespace poly; int n, len = 1; int F[maxf + 5]; int T[maxf + 5], H[maxf + 5]; int powH[maxf + 5], invH[maxf + 5]; int S1[maxf + 5], S2[maxf + 5]; void make_F() { for (int i = 0; i <= n; i++) T[i] = sub(0, ifac[i + 2]); Inv(T, F, len); for (int i = 0; i <= n; i++) F[i] = F[i + 1]; Cl(F + n - 1, len - n + 1); } void make_H() { Cl(T, len); T[0] = 1; T[1] = 1; Ln(T, H, len); for (int i = 0; i <= n; i++) T[i] = H[i + 1]; Inv(T, H, len); Cl(H + n + 1, len - n - 1); Ksm(H, powH, len, n - 1); Cl(powH + n + 1, len - n - 1); for (int i = 0; i <= n; i++) T[i] = sub(0, H[i + 1]); T[n] = 0; Inv(T, invH, len); Cl(invH + n + 1, len - n - 1); Cpy(S1, H, n + 1); diff(S1, n + 1); Mult(powH, invH, S2, len << 1); Cl(S2 + n + 1, (len << 1) - n - 1); Mult(S1, S2, S1, len << 1); Cl(S1 + n + 1, (len << 1) - n - 1); Mult(S1, invH, S1, len << 1); Cl(S1 + n + 1, (len << 1) - n - 1); n -= 2; for (int i = 1; i <= n; i++) F[i] = sub(F[i], 1ll * add(S1[i + 1], 1ll * (n - i + 1) * S2[i + 1] % mod) * inv(n + 1) % mod); F[0] = n; } int main() { scanf( %d , &n); if (n == 1) { printf( 1 n ); return 0; } n += 2; while (len <= n + 1) len <<= 1; make_fac(len << 1); pre_poly(len << 1); make_F(); make_H(); for (int i = 0; i <= n; i++) if (i & 1) T[i] = sub(0, ifac[i]); else T[i] = ifac[i]; for (int i = 0; i <= n; i++) F[i] = 1ll * F[i] * fac[i] % mod; Rev(F, n + 1); Cl(T + n + 1, (len << 1) - n - 1); Mult(F, T, F, len << 1); for (int i = 0; i < n; i++) printf( %lld , 1ll * fac[n] * ifac[i] % mod * F[n - i + 1] % mod); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int n, k, link; cin >> n >> k; vector<int> ans(n + 1); for (int i = 1; i <= n; i++) { cin >> link; ans[i] = min(n, i + k) - max(1, i - k) + 1; if (link != 0) { ans[i] += ans[link] - max(0, (min(n, link + k) - max(1, i - k) + 1)); } cout << ans[i] << ; } cout << endl; return 0; } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* I2S RX
*/
module i2s_rx #
(
parameter WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* I2S interface
*/
input wire sck,
input wire ws,
input wire sd,
/*
* AXI stream output
*/
output wire [WIDTH-1:0] output_l_tdata,
output wire [WIDTH-1:0] output_r_tdata,
output wire output_tvalid,
input wire output_tready
);
reg [WIDTH-1:0] l_data_reg = 0;
reg [WIDTH-1:0] r_data_reg = 0;
reg l_data_valid_reg = 0;
reg r_data_valid_reg = 0;
reg [WIDTH-1:0] sreg = 0;
reg [$clog2(WIDTH)-1:0] bit_cnt = 0;
reg last_sck = 0;
reg last_ws = 0;
reg last_ws2 = 0;
assign output_l_tdata = l_data_reg;
assign output_r_tdata = r_data_reg;
assign output_tvalid = l_data_valid_reg & r_data_valid_reg;
always @(posedge clk) begin
if (rst) begin
l_data_reg <= 0;
r_data_reg <= 0;
l_data_valid_reg <= 0;
r_data_valid_reg <= 0;
sreg <= 0;
bit_cnt <= 0;
last_sck <= 0;
last_ws <= 0;
last_ws2 <= 0;
end else begin
if (output_tready & output_tvalid) begin
l_data_valid_reg <= 0;
r_data_valid_reg <= 0;
end
last_sck <= sck;
if (~last_sck & sck) begin
// rising edge sck
last_ws <= ws;
last_ws2 <= last_ws;
if (last_ws2 != last_ws) begin
bit_cnt <= WIDTH-1;
sreg <= {{WIDTH-1{1'b0}}, sd};
end else begin
if (bit_cnt > 0) begin
bit_cnt <= bit_cnt - 1;
if (bit_cnt > 1) begin
sreg <= {sreg[WIDTH-2:0], sd};
end else if (last_ws2) begin
r_data_reg <= {sreg[WIDTH-2:0], sd};
r_data_valid_reg <= l_data_valid_reg;
end else begin
l_data_reg <= {sreg[WIDTH-2:0], sd};
l_data_valid_reg <= 1;
end
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; struct EDGE { int to, w; EDGE *las; } e[100005]; int ne; EDGE *last[100005]; void link(int u, int v, int w) { e[ne] = {v, w, last[u]}; last[u] = e + ne++; } long long dis[100005], f[100005]; void adjust() { for (int i = 1; i <= n; ++i) for (EDGE *ei = last[i]; ei; ei = ei->las) ei->w += dis[i] - dis[ei->to]; for (int i = 1; i <= n; ++i) f[i] += dis[i]; } void SP0() { static priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > q; memset(dis, 127, sizeof(long long) * (n + 1)); dis[1] = 0; q.push(make_pair(0, 1)); while (!q.empty()) { int x = q.top().second; long long s = q.top().first; q.pop(); if (s != dis[x]) continue; for (EDGE *ei = last[x]; ei; ei = ei->las) if (s + ei->w < dis[ei->to]) { dis[ei->to] = s + ei->w; q.push(make_pair(dis[ei->to], ei->to)); } } adjust(); } void SP1() { static vector<int> b[100005]; memset(dis, 127, sizeof(long long) * (n + 1)); dis[1] = 0; b[0].push_back(1); for (int i = 0; i < n; ++i) { for (int j = 0; j < b[i].size(); ++j) { int x = b[i][j]; if (dis[x] < i) continue; for (EDGE *ei = last[x]; ei; ei = ei->las) if (i + ei->w < n && i + ei->w < dis[ei->to]) { dis[ei->to] = i + ei->w; b[dis[ei->to]].push_back(ei->to); } } b[i].clear(); } adjust(); } int main() { int Q; scanf( %d%d%d , &n, &m, &Q); for (int i = 0; i < m; ++i) { int u, v, w; scanf( %d%d%d , &u, &v, &w); link(u, v, w); } SP0(); while (Q--) { int op; scanf( %d , &op); if (op == 1) { int v; scanf( %d , &v); printf( %lld n , dis[v] > 100000000000000 ? -1 : f[v]); } else { int c; scanf( %d , &c); for (int i = 0; i < c; ++i) { int id; scanf( %d , &id), --id; e[id].w++; } SP1(); } } return 0; } |
/**
# SmallLpf - Single-pole IIR Low-Pass Filter #
Small Single-Pole IIR low-pass filter, made using just adders and bit shifts.
Set the filter frequency using the FILT_BITS parameter. It can be slowed down by
strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is always stable and is immune
to limit cycling.
The transfer function is:
1 / 2^N
H(z) = -------------------------------
1 - z^-1 * (1-2^(-N))
where N = FILT_BITS. The -3 dB cutoff frequency, in radians, is:
w = ln ( (2^N - 1) / (2^N - 2) )
The cutoff frequency in the continuous-time domain is approximately f_clk
/ (2*pi*2^N), where f_clk is the filter's running rate. The design equation to
select an appropriate FILT_BITS value is thus:
FILT_BITS = log2( f_clk / (2*pi*f_cutoff))
*/
module SmallLpf #(
parameter WIDTH = 8, ///< Width of data path
parameter FILT_BITS = 8 ///< Number of additional bits used by filter
)
(
input clk, ///< System clock
input rst, ///< Reset, active high and synchronous
input en, ///< Filter enable
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter output
);
reg signed [WIDTH+FILT_BITS-1:0] filter;
assign dataOut = filter[WIDTH+FILT_BITS-1:FILT_BITS];
always @(posedge clk) begin
if (rst) begin
filter <= 'd0;
end
else if (en) begin
filter <= filter + dataIn - dataOut;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_BLACKBOX_V
`define SKY130_FD_SC_MS__DFBBN_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; long long int a[1004][1004]; long long int b[1005]; long long int c[1005]; long long int ci, cj; int main() { long long int i, j; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) for (j = 0; j < m; j++) scanf( %I64d , &a[i][j]); for (i = 0; i < n; i++) for (j = 0; j < m; j++) b[i] += a[i][j]; for (i = 0; i < n; i++) for (j = 0; j < m; j++) c[j] += a[i][j]; long long int mm = -1, tt; long long int res = 0; long long int mi; for (i = 0; i <= n; i++) { tt = 0; for (j = 0; j < n; j++) { tt += b[j] * (4 * i - 4 * j - 2) * (4 * i - 4 * j - 2); } if (mm < 0 || mm > tt) { mm = tt; mi = i; } } ci = mi; res += mm; mm = -1; for (i = 0; i <= m; i++) { tt = 0; for (j = 0; j < m; j++) { tt += c[j] * (4 * i - 4 * j - 2) * (4 * i - 4 * j - 2); } if (mm < 0 || mm > tt) { mm = tt; mi = i; } } cj = mi; res += mm; printf( %I64d n , res); printf( %I64d %I64d n , ci, cj); } |
#include <bits/stdc++.h> using namespace std; int a, b, c, d; int main() { cin >> a >> b >> c >> d; if (c - d < -1 || c - d > 1 || a < max(c, d) || b < max(c, d)) { cout << -1; return 0; } if (c - d == -1) { for (int i = 0; i < d; i++) { if (i == d - 1) for (int j = b; j > d; j--) cout << 7; cout << 74; if (!i) for (int j = a; j > d; j--) cout << 4; } } if (c - d == 1) { for (int i = a; i > c; i--) cout << 4; for (int i = 0; i < c; i++) cout << 47; for (int i = b; i > c; i--) cout << 7; } if (c == d) { if (a == c && b == d) { cout << -1; return 0; } if (a > c) { for (int i = a; i > c + 1; i--) cout << 4; for (int i = 0; i < c; i++) { cout << 47; } for (int i = b; i > d; i--) cout << 7; cout << 4; } else { cout << 7; for (int i = 0; i < c; i++) cout << 47; for (int i = b; i > d + 1; i--) cout << 7; } } } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_Acceleration_To_Velocity.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Rotor_Acceleration_To_Velocity
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Rotor_Acceleration_To_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
Vel_Target,
RV
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] Vel_Target; // sfix18_En8
output signed [31:0] RV; // sfix32_En22
wire signed [31:0] Reset_Delay_out1; // sfix32_En22
wire signed [17:0] Set_Acceleration_out1; // sfix18_En10
wire signed [35:0] Gain_out1; // sfix36_En41
wire signed [31:0] Convert_out1; // sfix32_En22
wire signed [32:0] Sum_add_cast; // sfix33_En22
wire signed [32:0] Sum_add_cast_1; // sfix33_En22
wire signed [32:0] Sum_add_temp; // sfix33_En22
wire signed [31:0] Sum_out1; // sfix32_En22
// Rotor Acceleration To Velocity
// <S22>/Set_Acceleration
controllerHdl_Set_Acceleration u_Set_Acceleration (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.v_target(Vel_Target), // sfix18_En8
.v_current(Reset_Delay_out1), // sfix32_En22
.a(Set_Acceleration_out1) // sfix18_En10
);
// <S22>/Gain
assign Gain_out1 = 85899 * Set_Acceleration_out1;
// <S22>/Convert
assign Convert_out1 = {{15{Gain_out1[35]}}, Gain_out1[35:19]};
// <S22>/Sum
assign Sum_add_cast = Convert_out1;
assign Sum_add_cast_1 = Reset_Delay_out1;
assign Sum_add_temp = Sum_add_cast + Sum_add_cast_1;
assign Sum_out1 = ((Sum_add_temp[32] == 1'b0) && (Sum_add_temp[31] != 1'b0) ? 32'sb01111111111111111111111111111111 :
((Sum_add_temp[32] == 1'b1) && (Sum_add_temp[31] != 1'b1) ? 32'sb10000000000000000000000000000000 :
$signed(Sum_add_temp[31:0])));
// <S22>/Reset_Delay
controllerHdl_Reset_Delay_block u_Reset_Delay (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.In(Sum_out1), // sfix32_En22
.Out(Reset_Delay_out1) // sfix32_En22
);
assign RV = Reset_Delay_out1;
endmodule // controllerHdl_Rotor_Acceleration_To_Velocity
|
// this is the 32 colour colour table
// because this module also supports EHB (extra half brite) mode,
// it actually has a 6bit colour select input
// the 6th bit selects EHB colour while the lower 5 bit select the actual colour register
module denise_colortable
(
input wire clk, // 28MHz clock
input wire clk7_en, // 7MHz clock enable
input wire [ 9-1:1] reg_address_in, // register adress inputs
input wire [ 12-1:0] data_in, // bus data in
input wire [ 8-1:0] select, // colour select input
input wire [ 8-1:0] bplxor, // clut address xor value
input wire [ 3-1:0] bank, // color bank select
input wire loct, // 12-bit pallete select
input wire ehb_en, // EHB enable
output reg [ 24-1:0] rgb // RGB output
);
// register names and adresses
parameter COLORBASE = 9'h180; // colour table base address
// select xor
wire [ 8-1:0] select_xored = select;// ^ bplxor;
// color ram
wire [ 8-1:0] wr_adr = {bank[2:0], reg_address_in[5:1]};
wire wr_en = (reg_address_in[8:6] == COLORBASE[8:6]) && clk7_en;
wire [32-1:0] wr_dat = {4'b0, data_in[11:0], 4'b0, data_in[11:0]};
wire [ 4-1:0] wr_bs = loct ? 4'b0011 : 4'b1111;
wire [ 8-1:0] rd_adr = ehb_en ? {3'b000, select_xored[4:0]} : select_xored;
wire [32-1:0] rd_dat;
reg ehb_sel;
// color lut
denise_colortable_ram_mf clut
(
.clock (clk ),
.enable (1'b1 ),
.wraddress (wr_adr ),
.wren (wr_en ),
.byteena_a (wr_bs ),
.data (wr_dat ),
.rdaddress (rd_adr ),
.q (rd_dat )
);
// register half-brite bit
always @ (posedge clk) begin
ehb_sel <= #1 select_xored[5];
end
// pack color values
wire [12-1:0] color_hi = rd_dat[12-1+16:0+16];
wire [12-1:0] color_lo = rd_dat[12-1+ 0:0+ 0];
wire [24-1:0] color = {color_hi[11:8], color_lo[11:8], color_hi[7:4], color_lo[7:4], color_hi[3:0], color_lo[3:0]};
// extra half brite mode shifter
always @ (*) begin
if (ehb_sel && ehb_en) // half bright, shift every component 1 position to the right
rgb = {1'b0,color[23:17],1'b0,color[15:9],1'b0,color[7:1]};
else // normal colour select
rgb = color;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Edge { int u, v; int c; int w; int id; bool use; }; bool operator<(const Edge& l, const Edge& r) { return l.w < r.w; } class Node { int depth; pair<int, int> w; Node* parent; public: Node() : depth(0), w(0, -1), parent(nullptr) {} static pair<int, int> merge(Node* a, Node* b, int W, int id) { pair<int, int> mx = {-1, -1}; while ((a->parent || b->parent) && a != b) { if (!b->parent || a->parent && a->depth <= b->depth) { mx = max(mx, a->w); a = a->parent; } else { mx = max(mx, b->w); b = b->parent; } } if (a == b) return {W - mx.first, mx.second}; if (a->depth < b->depth) swap(a, b); b->parent = a; b->w.first = W; b->w.second = id; a->depth = max(a->depth, b->depth + 1); return {0, -id}; } }; int main(int argc, const char* argv[]) { int N, M; std::vector<int> W, C; int S; scanf( %d%d , &N, &M); W.resize(M); C.resize(M); for (auto&& x : W) scanf( %d , &x); for (auto&& x : C) scanf( %d , &x); vector<Edge> edges(M); for (int i = 0; i < M; i++) { Edge& e = edges[i]; scanf( %d %d , &e.u, &e.v); e.u--; e.v--; e.c = C[i]; e.w = W[i]; e.id = i + 1; } scanf( %d , &S); sort((edges).begin(), (edges).end()); vector<Node> nodes(N); int best = 1 << 30; int exc = -1; const Edge* useE = nullptr; long long sumw = 0; for (auto&& e : edges) { pair<int, int> r = Node::merge(&nodes[e.u], &nodes[e.v], e.w, e.id); if (r.second < 0) { e.use = true; sumw += e.w; r.second = -r.second; } else { e.use = false; } int bonus = r.first - S / e.c; if (bonus < best) { best = bonus; exc = r.second; useE = &e; } } printf( %I64d n , sumw + best); for (auto&& e : edges) if (e.use && e.id != exc) printf( %d %d n , e.id, e.w); printf( %d %d n , useE->id, useE->w - S / useE->c); return 0; } |
/**
* bsg_cache_to_test_dram_tx.v
*
*/
`include "bsg_defines.v"
module bsg_cache_to_test_dram_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p)
, parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
)
(
input core_clk_i
, input core_reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, input [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
, input dram_clk_i
, input dram_reset_i
, output logic dram_data_v_o
, output logic [dram_data_width_p-1:0] dram_data_o
, input dram_data_yumi_i
);
// tag fifo
//
logic tag_v_lo;
logic [lg_num_cache_lp-1:0] tag_lo;
logic tag_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p*num_req_lp)
) tag_fifo (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(v_i)
,.ready_o(ready_o)
,.data_i(tag_i)
,.v_o(tag_v_lo)
,.data_o(tag_lo)
,.yumi_i(tag_yumi_li)
);
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_lo)
,.v_i(tag_v_lo)
,.o(cache_sel)
);
// de-serialization
//
logic [num_cache_p-1:0] sipo_v_li;
logic [num_cache_p-1:0] sipo_ready_lo;
logic [num_cache_p-1:0][dma_data_width_p-1:0] sipo_data_li;
logic [num_cache_p-1:0] sipo_v_lo;
logic [num_cache_p-1:0][dram_data_width_p-1:0] sipo_data_lo;
logic [num_cache_p-1:0] sipo_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_serial_in_parallel_out_full #(
.width_p(dma_data_width_p)
,.els_p(dram_data_width_p/dma_data_width_p)
) sipo (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(sipo_v_li[i])
,.data_i(sipo_data_li[i])
,.ready_o(sipo_ready_lo[i])
,.v_o(sipo_v_lo[i])
,.data_o(sipo_data_lo[i])
,.yumi_i(sipo_yumi_li[i])
);
end
if (num_req_lp == 1) begin
assign sipo_v_li = dma_data_v_i;
assign sipo_data_li = dma_data_i;
assign dma_data_yumi_o = dma_data_v_i & sipo_ready_lo;
end
else begin
logic [num_cache_p-1:0] fifo_ready_lo;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_fifo_1r1w_small #(
.width_p(dma_data_width_p)
,.els_p(block_size_in_words_p*data_width_p/dma_data_width_p)
) fifo0 (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(dma_data_v_i[i])
,.ready_o(fifo_ready_lo[i])
,.data_i(dma_data_i[i])
,.v_o(sipo_v_li[i])
,.data_o(sipo_data_li[i])
,.yumi_i(sipo_v_li[i] & sipo_ready_lo[i])
);
assign dma_data_yumi_o[i] = fifo_ready_lo[i] & dma_data_v_i[i];
end
end
// async fifo
//
logic afifo_full;
logic [dram_data_width_p-1:0] afifo_data_li;
logic afifo_enq;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_cache_p*num_req_lp,4)))
,.width_p(dram_data_width_p)
) data_afifo (
.w_clk_i(core_clk_i)
,.w_reset_i(core_reset_i)
,.w_enq_i(afifo_enq)
,.w_data_i(afifo_data_li)
,.w_full_o(afifo_full)
,.r_clk_i(dram_clk_i)
,.r_reset_i(dram_reset_i)
,.r_deq_i(dram_data_yumi_i)
,.r_data_o(dram_data_o)
,.r_valid_o(dram_data_v_o)
);
wire send_data = tag_v_lo & ~afifo_full & sipo_v_lo[tag_lo];
assign afifo_enq = send_data;
assign tag_yumi_li = send_data;
assign afifo_data_li = sipo_data_lo[tag_lo];
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux0 (
.i(tag_lo)
,.v_i(send_data)
,.o(sipo_yumi_li)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_tx)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_SYMBOL_V
`define SKY130_FD_SC_HS__NAND2B_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n; long long a, sum, ans; priority_queue<long long, vector<long long>, greater<long long> > Q; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %lld , &a); Q.push(a); } if (n % 2 == 0) Q.push(0); ans = 0; while (Q.size() > 2) { sum = Q.top(); Q.pop(); sum += Q.top(); Q.pop(); sum += Q.top(); Q.pop(); ans += sum; Q.push(sum); } printf( %lld n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:50:34 03/11/2015
// Design Name:
// Module Name: delay_line
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delayLine #(
parameter DELAY = 0,
parameter WIDTH = 8
)(
input ce,
input rst,
input clk,
input [WIDTH - 1:0] in,
output [WIDTH - 1:0] out
);
wire [WIDTH - 1:0] chain [DELAY:0];
assign chain[0] = in;
assign out = chain[DELAY];
genvar i;
generate
for(i = 0; i < DELAY; i = i + 1)
begin : chain_connector
wlatch #(
.WIDTH(WIDTH)
)
lat (
.ce(ce),
.rst(rst),
.clk(clk),
.in(chain[i]),
.out(chain[i + 1])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; class opr { public: int q; int w; opr *pNext; opr *pLost; }; opr *pHead = 0; opr *pTail = 0; opr *pN = 0; void addvalue(int e, int r) { opr *p = new opr; if (pHead == 0) { p->q = e; p->w = r; p->pNext = 0; p->pLost = 0; pHead = p; pTail = p; pN = p; } else { p->q = e; p->w = r; p->pLost = pN; p->pNext = 0; pN->pNext = p; pN = p; pTail = p; } } void resilt() { pN = pHead; while (pN != 0) { cout << pN->q << << pN->w << endl; pN = pN->pNext; } } int main() { int n; cin >> n; int *old = new int[n]; int *nw = new int[n]; for (int i = 0; i < n; i++) cin >> old[i]; for (int i = 0; i < n; i++) cin >> nw[i]; int sum = 0; for (int i = 0; i < n; i++) { if (old[i] != nw[i]) { int k = i + 1; while (old[i] != nw[k]) k++; addvalue(k - 1 + 1, k + 1); int temp = nw[k]; nw[k] = nw[k - 1]; nw[k - 1] = temp; sum++; if ((k - 1) != i) i--; } } cout << sum << endl; resilt(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long i, sum, a, b, c; int main() { for (i = 0; i < 4; i++) { cin >> a; if (i == 0) { b = a; c = a; } if (a < b) { b = a; } if (a > c) { c = a; } sum += a; } if (sum % 2 == 1) { cout << NO ; } else if (c + b == sum / 2 || c == sum / 2) { cout << YES ; } else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int N, M; long long ans, add[400009], sum[400009]; set<pair<int, pair<int, int> > > segm; int mod(int x) { if (x < 0) return -x; return x; } void split(int nod, int l1, int l2) { if (add[nod] == 0) return; int f1 = nod << 1, f2 = (nod << 1) + 1; sum[f1] += 1LL * add[nod] * l1, sum[f2] += 1LL * add[nod] * l2; add[f1] += add[nod], add[f2] += add[nod]; add[nod] = 0; } void U(int nod, int st, int dr, int x, int y, int val) { if (x <= st && dr <= y) { add[nod] += val; sum[nod] += 1LL * val * (dr - st + 1); return; } int mij = (st + dr) >> 1; split(nod, mij - st + 1, dr - mij); if (x <= mij) U(nod << 1, st, mij, x, y, val); if (y > mij) U((nod << 1) + 1, mij + 1, dr, x, y, val); sum[nod] = sum[nod << 1] + sum[(nod << 1) + 1]; } void Q(int nod, int st, int dr, int x, int y) { if (x <= st && dr <= y) { ans += sum[nod]; return; } int mij = (st + dr) >> 1; split(nod, mij - st + 1, dr - mij); if (x <= mij) Q(nod << 1, st, mij, x, y); if (y > mij) Q((nod << 1) + 1, mij + 1, dr, x, y); } void Update(int L, int R, int val) { set<pair<int, pair<int, int> > >::iterator it = segm.lower_bound( make_pair(L, make_pair(0, 0))), it2; if (it->second.first < L) { int A = it->second.first, B = it->first, C = it->second.second; if (B > R) { U(1, 1, N, L, R, mod(val - C)); segm.erase(it); segm.insert(make_pair(L - 1, make_pair(A, C))); segm.insert(make_pair(B, make_pair(R + 1, C))); segm.insert(make_pair(R, make_pair(L, val))); return; } U(1, 1, N, L, B, mod(val - C)); segm.erase(it); segm.insert(make_pair(L - 1, make_pair(A, C))); it = segm.lower_bound(make_pair(L, make_pair(0, 0))); } while (1) { if (it == segm.end()) break; if (it->second.first > R) break; if (it->first > R) { int A = it->second.first, B = it->first, C = it->second.second; U(1, 1, N, A, R, mod(val - C)); segm.erase(it); segm.insert(make_pair(B, make_pair(R + 1, C))); break; } it2 = it, it2++; U(1, 1, N, it->second.first, it->first, mod(val - it->second.second)); segm.erase(it); it = it2; } segm.insert(make_pair(R, make_pair(L, val))); } int main() { scanf( %d %d , &N, &M); for (int i = 1; i <= N; i++) segm.insert(make_pair(i, make_pair(i, i))); while (M--) { int tip, a, b, c; scanf( %d , &tip); if (tip == 1) { scanf( %d %d %d , &a, &b, &c); Update(a, b, c); } else { scanf( %d %d , &a, &b), ans = 0LL; Q(1, 1, N, a, b); printf( %I64d n , ans); } } return 0; } |
// MBT 8-28-14
//
// sequence through all of the tests.
//
// for each test, assert a prepare line for prepare_time_p cycles
// then wait for either 1) all channels to pass that test
// or 2) one channel passes and things have stabilized
// for timeout_time_p cycles
//
//
`include "bsg_defines.v"
module bsg_source_sync_channel_control_master_master
#(parameter `BSG_INV_PARAM( link_channels_p )
, parameter `BSG_INV_PARAM(tests_p )
, parameter `BSG_INV_PARAM(prepare_cycles_p )
, parameter `BSG_INV_PARAM(timeout_cycles_p ))
(input clk_i
, input reset_i
, input start_i
, input [tests_p+1-1:0][link_channels_p-1:0] test_scoreboard_i
, output [$clog2(tests_p+1)-1:0] test_index_r_o
, output prepare_o
, output done_o
);
logic [$clog2(tests_p+1)-1:0] test_index_n, test_index_r;
logic [tests_p+1-1:0][link_channels_p-1:0] test_scoreboard_r;
wire prep_done, timeout_wait_done;
logic prep_actiwait;
assign test_index_r_o = test_index_r;
assign prepare_o = ~prep_done;
logic done_r, done_n;
assign done_o = done_r;
wire final_test = (test_index_r == tests_p);
bsg_wait_cycles #(.cycles_p(prepare_cycles_p)) bwc
(.clk_i (clk_i)
,.reset_i (reset_i)
,.activate_i (prep_actiwait)
,.ready_r_o (prep_done)
);
// reactivate the timeout if the channels that pass change
// this timeout is not really for handling intermittant operation
// but more to deal with slight amounts of skew between channel
// wakeup times.
//
// note: this means that we could potentially loop indefinitely
// if things are intermittant; i.e. a channel oscillates between
// going active and being inactive.
//
// fixme: this is okay for FPGA (we can fix the code after the fact)
// but not for ASIC.
//
bsg_wait_cycles #(.cycles_p(timeout_cycles_p)) bwc2
(.clk_i (clk_i)
,.reset_i (reset_i)
,.activate_i(test_scoreboard_i[test_index_r] != test_scoreboard_r[test_index_r])
,.ready_r_o( timeout_wait_done)
);
always_ff @(posedge clk_i)
begin
if (reset_i)
test_index_r <= { ($clog2(tests_p+1)) { 1'b0 } };
else
test_index_r <= test_index_n;
if (reset_i)
test_scoreboard_r <= { link_channels_p*(tests_p+1) { 1'b0 } };
else
test_scoreboard_r <= test_scoreboard_i;
if (reset_i)
done_r <= 1'b0;
else
done_r <= done_n;
end
always_comb
begin
done_n = done_r;
test_index_n = test_index_r;
prep_actiwait = 0;
if (start_i)
begin
done_n = 1'b0;
test_index_n = 0;
prep_actiwait = 1'b1;
end
else
if (prep_done & ~done_r) // if we're done preparing for the tests,
begin // or haven't finished them all...
if ( (& test_scoreboard_r[test_index_r]) // all chanls passed the test
| ( (| test_scoreboard_r[test_index_r]) // or if at least one has
& timeout_wait_done // and we have timed out
)
)
begin
if (final_test)
done_n = 1'b1;
else
begin
// if we've already passed all tests
// then go directly to the last test.
// "temporary fix" for accelerating simulation 5/1/17 mbt
if (&test_scoreboard_r[tests_p-1:0])
test_index_n = tests_p;
else
test_index_n = test_index_r + 1'b1;
prep_actiwait = 1'b1;
end
end
end
end // always_comb
endmodule
`BSG_ABSTRACT_MODULE(bsg_source_sync_channel_control_master_master)
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "utils/cdc_pulse_sync.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "utils/ramb_8_to_n.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "utils/RAMB16_S1_S9_sim.v"
`include "utils/CG_MOD_pos.v"
`include "gpac_adc_rx/gpac_adc_rx_core.v"
`include "gpac_adc_rx/gpac_adc_rx.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_syncfifo.v"
`include "utils/pulse_gen_rising.v"
`include "utils/clock_divider.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/cdc_reset_sync.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam SEQ_GEN_BASEADDR = 32'h1000; //0x1000
localparam SEQ_GEN_HIGHADDR = 32'h3000-1; //0x300f
localparam ADC_RX_BASEADDR = 32'h3000;
localparam ADC_RX_HIGHADDR = 32'h5000 - 1;
localparam SPI_ADC_BASEADDR = 32'h5000;
localparam SPI_ADC_HIGHADDR = 32'h6000-1;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire DIV_CLK;
clock_divider #(
.DIVISOR(8)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(DIV_CLK)
);
wire EX_START_PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(DIV_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire [15:0] SEQ_OUT;
seq_gen #(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16*1024),
.OUT_BITS(16)
) i_seq_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(DIV_CLK),
.SEQ_OUT(SEQ_OUT)
);
wire SDI;
spi #(
.BASEADDR(SPI_ADC_BASEADDR),
.HIGHADDR(SPI_ADC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(2)
) i_spi (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(DIV_CLK),
.SCLK(),
.SDI(SDI),
.SDO(SDI),
.SEN(),
.SLD()
);
wire FIFO_READ_ADC;
wire FIFO_EMPTY_ADC;
wire [31:0] FIFO_DATA_ADC;
gpac_adc_rx #(
.BASEADDR(ADC_RX_BASEADDR),
.HIGHADDR(ADC_RX_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.ADC_ID(0),
.HEADER_ID(0)
) i_gpac_adc_rx (
.ADC_ENC(DIV_CLK),
.ADC_IN(SEQ_OUT[13:0]),
.ADC_SYNC(EX_START_PULSE),
.ADC_TRIGGER(1'b0),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ(FIFO_READ_ADC),
.FIFO_EMPTY(FIFO_EMPTY_ADC),
.FIFO_DATA(FIFO_DATA_ADC),
.LOST_ERROR()
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_ADC;
assign FIFO_EMPTY = FIFO_EMPTY_ADC;
assign FIFO_READ_ADC = FIFO_READ;
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("adcrx.vcd");
$dumpvars(0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
logic [3:0] array_oned;
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
// IEEE says '{} allowed only on assignments, not !=, ==.
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if (array_simp !== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if (array_simp !== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
end
//====================
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size
localparam NO = 11; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_bg <= '0;
else if (cnt[30:2]== 1) array_bg <= '0;
else if (cnt[30:2]== 2) array_bg <= '0;
else if (cnt[30:2]== 3) array_bg <= '0;
else if (cnt[30:2]== 4) array_bg <= '0;
else if (cnt[30:2]== 5) array_bg <= '0;
else if (cnt[30:2]== 6) array_bg <= '0;
else if (cnt[30:2]== 7) array_bg <= '0;
else if (cnt[30:2]== 8) array_bg <= '0;
else if (cnt[30:2]== 9) array_bg <= '0;
else if (cnt[30:2]==10) array_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_bg <= '{default:13};
else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13};
else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_lt <= '0;
else if (cnt[30:2]== 1) array_lt <= '0;
else if (cnt[30:2]== 2) array_lt <= '0;
else if (cnt[30:2]== 3) array_lt <= '0;
else if (cnt[30:2]== 4) array_lt <= '0;
else if (cnt[30:2]== 5) array_lt <= '0;
else if (cnt[30:2]== 6) array_lt <= '0;
else if (cnt[30:2]== 7) array_lt <= '0;
else if (cnt[30:2]== 8) array_lt <= '0;
else if (cnt[30:2]== 9) array_lt <= '0;
else if (cnt[30:2]==10) array_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_lt <= '{default:13};
else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end
end
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for array querying functions for unpacked arrays
// (IEEE Std 1800-2012 7.11)
module array_unpacked_sysfunct();
bit [7:0] bit_darray [];
//bit bit_darray []; // not available yet
bit [7:0] array [2:4];
bit [7:0] reverse_array[5:3];
bit [2:8] packed_array;
bit [4:1] reverse_packed_array;
initial begin
string test_msg = "13 characters";
bit_darray = new[5];
if($left(bit_darray) != 0 || $right(bit_darray) != 4) begin
$display("FAILED 1");
$finish();
end
if($left(array) != 2 || $right(array) != 4) begin
$display("FAILED 2");
$finish();
end
if($left(reverse_array) != 5 || $right(reverse_array) != 3) begin
$display("FAILED 3");
$finish();
end
if($left(test_msg) != 0 || $right(test_msg) != 12) begin
$display("FAILED 4");
$finish();
end
if($left(packed_array) != 2 || $right(packed_array) != 8) begin
$display("FAILED 5");
$finish();
end
if($left(reverse_packed_array) != 4 || $right(reverse_packed_array) != 1) begin
$display("FAILED 6");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int DIM = 2 * 100001; struct nr { int val, ind; } mins[DIM]; int n, m, d; int used[DIM], afis[DIM]; bool cmp(nr x, nr y) { return x.val < y.val; } int main() { cin >> n >> m >> d; for (int i = 1; i <= n; ++i) { cin >> mins[i].val; mins[i].ind = i; } sort(mins + 1, mins + n + 1, cmp); int point = 1, last = 1; afis[mins[point].ind] = 1; for (int i = 2; i <= n; ++i) { if (mins[point].val + d < mins[i].val) { afis[mins[i].ind] = afis[mins[point].ind]; point++; } else { afis[mins[i].ind] = ++last; } } cout << last << n ; for (int i = 1; i <= n; ++i) cout << afis[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; char stra[110]; char strb[110]; int mark[110]; int g[11000]; int main() { int b, d; scanf( %d%d , &b, &d); scanf( %s , stra); scanf( %s , strb); int lena = strlen(stra); int lenb = strlen(strb); memset(mark, -1, sizeof(mark)); mark[0] = 0; int pos = 0; int key = 0; int cnt = 0; int num = 0; for (int ii = 1; ii <= 1000; ii++) { int sum = 0; for (int i = 0; i < lena; i++) { if (stra[i] == strb[pos]) { pos++; if (pos == lenb) { sum++; pos = 0; } } } g[ii] = sum; if (mark[pos] == -1) mark[pos] = ii; else { key = mark[pos]; cnt = ii - key; for (int ti = key + 1; ti <= ii; ti++) num += g[ti]; break; } } int ans = 0; if (b <= key) { for (int i = 1; i <= b; i++) ans += g[i]; } else { int tb = (b - key) / cnt; int tt = (b - key) - tb * cnt; for (int i = 1; i <= key; i++) ans += g[i]; ans += tb * num; for (int i = key + 1; i <= key + tt; i++) ans += g[i]; } printf( %d n , ans / d); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
// surefire lint_off STMINI
// surefire lint_off CSEBEQ
input clk;
reg [7:0] a_to_clk_levm3;
reg [7:0] b_to_clk_levm1;
reg [7:0] c_com_levs10;
reg [7:0] d_to_clk_levm2;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v
wire [7:0] n_from_clk_lev2; // From a of t_order_a.v
wire [7:0] o_from_com_levs11; // From a of t_order_a.v
wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v
wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v
// End of automatics
reg [7:0] cyc; initial cyc=0;
t_order_a a (
.one (8'h1),
/*AUTOINST*/
// Outputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]),
.n_from_clk_lev2 (n_from_clk_lev2[7:0]),
.o_from_com_levs11 (o_from_com_levs11[7:0]),
.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]),
// Inputs
.clk (clk),
.a_to_clk_levm3 (a_to_clk_levm3[7:0]),
.b_to_clk_levm1 (b_to_clk_levm1[7:0]),
.c_com_levs10 (c_com_levs10[7:0]),
.d_to_clk_levm2 (d_to_clk_levm2[7:0]));
t_order_b b (
/*AUTOINST*/
// Outputs
.o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]),
// Inputs
.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]));
reg [7:0] o_from_com_levs12;
reg [7:0] o_from_com_levs13;
always @ (/*AS*/o_from_com_levs11) begin
o_from_com_levs12 = o_from_com_levs11 + 8'h1;
o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize
o_from_com_levs13 = o_from_com_levs12;
end
reg sepassign_in;
// verilator lint_off UNOPTFLAT
wire [3:0] sepassign;
// verilator lint_on UNOPTFLAT
// verilator lint_off UNOPT
assign #0.1 sepassign[0] = 0,
sepassign[1] = sepassign[2],
sepassign[2] = sepassign[3],
sepassign[3] = sepassign_in;
wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2;
// verilator lint_on UNOPT
always @ (posedge clk) begin
cyc <= cyc+8'd1;
sepassign_in <= 0;
if (cyc == 8'd1) begin
a_to_clk_levm3 <= 0;
d_to_clk_levm2 <= 1;
b_to_clk_levm1 <= 1;
c_com_levs10 <= 2;
sepassign_in <= 1;
end
if (cyc == 8'd2) begin
if (sepassign !== 4'b1110) $stop;
end
if (cyc == 8'd3) begin
$display("%d %d %d %d",m_from_clk_lev1_r,
n_from_clk_lev2,
o_from_com_levs11,
o_from_comandclk_levs12);
if (m_from_clk_lev1_r !== 8'h2) $stop;
if (o_subfrom_clk_lev3 !== 8'h2) $stop;
if (n_from_clk_lev2 !== 8'h2) $stop;
if (o_from_com_levs11 !== 8'h3) $stop;
if (o_from_com_levs13 !== 8'h5) $stop;
if (o_from_comandclk_levs12 !== 8'h5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct edge { long long a, b, index; long long u, v; }; bool compare(edge i, edge j) { if (i.a == j.a) return i.b > j.b; return i.a < j.a; } bool compare2(edge i, edge j) { return i.index < j.index; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, m; cin >> n >> m; edge a[m]; for (long long i = 0; i < m; i++) { cin >> a[i].a >> a[i].b; a[i].index = i; } long long suc = 0, unsuc = 0; sort(a, a + m, compare); long long u1 = 2, v1 = 3; for (long long i = 0; i < m; i++) { if (a[i].b == 1) { a[i].u = 1; a[i].v = suc + 2; suc++; } else { unsuc++; long long edges = ((suc + 1) * (suc)) / 2 - (suc); if (edges < unsuc) { cout << -1 << n ; return 0; } a[i].u = u1; a[i].v = v1; if (u1 + 1 == v1) { u1 = 2; v1++; } else { u1++; } } } sort(a, a + m, compare2); for (long long i = 0; i < m; i++) cout << a[i].u << << a[i].v << n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:43:48 05/12/2015
// Design Name:
// Module Name: processor_16
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module processor_16(
input clock,
input IRQ,
input [15:0] processor_input,
input processor_uart_rx,
output [15:0] processor_output,
output processor_uart_tx
);
wire [15:0] IR;
wire [11:0] PC;
wire N, Z, C, V;
wire [2:0] reg_write_adr_d, reg_write_adr_e, reg_write_adr_m, reg_write_adr_w;
wire reg_write_d, reg_write_e, reg_write_m, reg_write_w;
wire mem_to_reg_d, mem_to_reg_e, mem_to_reg_w;
wire mem_write_d, mem_write_m;
wire [2:0] reg_read_adr1_d, reg_read_adr1_e;
wire [2:0] reg_read_adr2_d, reg_read_adr2_e;
wire [7:0] ALU_con_d, ALU_con_e;
wire ALU_source2_d, ALU_source2_e;
wire [15:0] offset_register_d, offset_register_e;
wire flush_d, flush_e;
wire stall_d, stall_f;
wire PC_source;
wire [1:0] forward1_e, forward2_e;
wire branch_d;
wire [3:0] branch_condition_d;
wire [11:0] ISR_adr;
wire branch_ISR;
wire subroutine_call_d;
wire subroutine_return_d;
wire [11:0] RTS_adr;
wire IEN_d, IOF_d, RTI_d;
organisation organisation_unit (
.clock(clock),
.reg_read_adr1(reg_read_adr1_d),
.reg_read_adr2(reg_read_adr2_d),
.reg_write_adr(reg_write_adr_w),
.reg_write(reg_write_w),
.flush_e(flush_e),
.forward1(forward1_e),
.forward2(forward2_e),
.ALU_con(ALU_con_e),
.ALU_source2(ALU_source2_e),
.offset(offset_register_e),
.mem_write(mem_write_m),
.mem_to_reg(mem_to_reg_w),
.processor_input(processor_input),
.processor_uart_rx(processor_uart_rx),
// Outputs
.N(N),
.Z(Z),
.C(C),
.V(V),
.processor_output(processor_output),
.processor_uart_tx(processor_uart_tx),
.internal_IRQ(internal_IRQ)
);
IR_fetch fetch_unit (
.clock(clock),
.PC_source(PC_source),
.PC_offset(offset_register_d[11:0]),
.ISR_adr(ISR_adr),
.branch_ISR(branch_ISR),
.stall_d(stall_d),
.stall_f(stall_f),
.flush_d(flush_d),
// Outputs
.IR(IR),
.PC(PC)
);
decode_unit decode_unit (
.IR(IR),
.PC(PC),
.RTS_adr(RTS_adr), /////////////////
// Outputs
.reg_read_adr1_d(reg_read_adr1_d),
.reg_read_adr2_d(reg_read_adr2_d),
.reg_write_adr_d(reg_write_adr_d),
.reg_write_d(reg_write_d),
.ALU_source2_d(ALU_source2_d),
.ALU_con_d(ALU_con_d),
.offset_register_d(offset_register_d),
.mem_write_d(mem_write_d),
.mem_to_reg_d(mem_to_reg_d),
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.subroutine_call_d(subroutine_call_d), /////////////////////////////
.subroutine_return_d(subroutine_return_d), ///////////////
.IEN_d(IEN_d),
.IOF_d(IOF_d),
.RTI_d(RTI_d)
);
branch branch_control_unit (
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.Z(Z),
.N(N),
.V(V),
.C(C),
// Outputs
.PC_source(PC_source)
);
subroutine_stack sub_stack (
.clock(clock),
.subroutine_call(subroutine_call_d),
.subroutine_return(subroutine_return_d),
.PC(PC),
// Outputs
.RTS_adr(RTS_adr)
);
hazard hazard_detection_unit (
.reg_read_adr1_d(reg_read_adr1_d),
.reg_read_adr2_d(reg_read_adr2_d),
.reg_read_adr1_e(reg_read_adr1_e),
.reg_read_adr2_e(reg_read_adr2_e),
.reg_write_adr_e(reg_write_adr_e),
.mem_to_reg_e(mem_to_reg_e),
.reg_write_m(reg_write_m),
.reg_write_adr_m(reg_write_adr_m),
.reg_write_w(reg_write_w),
.reg_write_adr_w(reg_write_adr_w),
.PC_source(PC_source),
// Outputs
.stall_f(stall_f),
.stall_d(stall_d),
.flush_d(flush_d),
.flush_e(flush_e),
.forward1_e(forward1_e),
.forward2_e(forward2_e)
);
interrupt interrupt_control_unit (
.clock(clock),
.IEN_d(IEN_d),
.IOF_d(IOF_d),
.RTI_d(RTI_d),
.branch_d(branch_d),
.IRQ(IRQ),
.PC(PC),
// Outputs
.branch_ISR(branch_ISR),
.ISR_adr(ISR_adr)
);
pipeline_control_registers pipeline_registers (
.clock(clock),
.flush_e(flush_e),
.reg_write_d(reg_write_d),
.reg_write_adr_d(reg_write_adr_d),
.mem_to_reg_d(mem_to_reg_d),
.mem_write_d(mem_write_d),
.ALU_con_d(ALU_con_d),
.ALU_source2_d(ALU_source2_d),
.offset_register_d(offset_register_d),
.reg_read_adr1_d(reg_read_adr1_d),
.reg_read_adr2_d(reg_read_adr2_d),
// Outputs
.reg_write_e(reg_write_e),
.reg_write_adr_e(reg_write_adr_e),
.mem_to_reg_e(mem_to_reg_e),
.mem_write_e(), /////////////////////////////////
.ALU_con_e(ALU_con_e),
.ALU_source2_e(ALU_source2_e),
.offset_register_e(offset_register_e),
.reg_read_adr1_e(reg_read_adr1_e),
.reg_read_adr2_e(reg_read_adr2_e),
.reg_write_m(reg_write_m),
.reg_write_adr_m(reg_write_adr_m),
.mem_to_reg_m(mem_to_reg_m),
.mem_write_m(mem_write_m),
.reg_write_w(reg_write_w),
.reg_write_adr_w(reg_write_adr_w),
.mem_to_reg_w(mem_to_reg_w)
);
endmodule
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module fifo36_to_gpmc16
#(
parameter FIFO_SIZE = 9,
//not ready until minimum xfers of occupancy available
parameter MIN_OCC16 = 2
)
(
//input fifo interface
input fifo_clk, input fifo_rst,
input [35:0] in_data,
input in_src_rdy,
output in_dst_rdy,
//output interface
input gpif_clk, input gpif_rst,
output [15:0] out_data,
output valid,
input enable,
output eof,
output reg has_data
);
wire [15:0] fifo_occ;
always @(posedge gpif_clk)
has_data <= (fifo_occ >= MIN_OCC16);
wire [35:0] data_int;
wire src_rdy_int, dst_rdy_int;
fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) fifo_2clk
(.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(),
.rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
.arst(fifo_rst | gpif_rst));
wire [18:0] data19_int;
wire data19_src_rdy_int, data19_dst_rdy_int;
fifo36_to_fifo19 #(.LE(1)) f36_to_f19
(.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
.f19_dataout(data19_int), .f19_src_rdy_o(data19_src_rdy_int), .f19_dst_rdy_i(data19_dst_rdy_int) );
wire [17:0] data18_int;
fifo_cascade #(.WIDTH(18), .SIZE(FIFO_SIZE+1)) occ_ctrl_fifo
(.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.datain(data19_int[17:0]), .src_rdy_i(data19_src_rdy_int), .dst_rdy_o(data19_dst_rdy_int), .space(),
.dataout(data18_int), .src_rdy_o(valid), .dst_rdy_i(enable), .occupied(fifo_occ));
assign out_data = data18_int[15:0];
assign eof = data18_int[17];
endmodule //fifo_to_gpmc16
|
module processor_test (input wire clk,
input wire pc_reset,
input wire pc_enable
);
// Step 1
wire [31:0] pc_in;
wire [31:0] pc_out;
// Step 2
wire [31:0] pc_plus_four;
wire [31:0] add0_in1;
assign add0_in1 = 32'd4;
// Step 3
wire [31:0] alu_data_output;
wire [31:0] readData2;
wire [31:0] mem_data_out;
wire [31:0] instr;
// Step 4
wire reg_dst, jump, branch, mem_to_reg, ctrl_mem_read_wire, ctrl_mem_write_wire, alu_src, reg_write;
wire [1:0] alu_op;
//************************ STEP 1 - PC ************************************
pc pc0(
.in (pc_in), //32 bits
.clk,
.rst (pc_reset),
.en (pc_enable),
.out (pc_out) //32 bits
);
//******************** STEP 2 - PC + 4 ADDER ********************************
Adder_32b pc_adder(
.clk,
.input0 (pc_out),
.input1 (add0_in1),
.out (pc_plus_four)
);
//******************* STEP 3 - INSTRUCTION MEM *******************************
Memory mem0(
.inst_addr (pc_out), //32 bits
.instr, //32 bits
.data_addr (alu_data_output), //32 bits
.data_in (readData2), //32 bits
.mem_read (ctrl_mem_read_wire),
.mem_write (ctrl_mem_write_wire),
.data_out (mem_data_out) //32 bits
);
//******************* STEP 4 - CONTROL *******************************
/*
Control ctrl0(
.clk,
.opcode (instr[31:26]), //6 bits
.reg_dst,
.jump,
.branch,
.ctrl_mem_read(ctrl_mem_read_wire),
.mem_to_reg,
.ctrl_mem_write(ctrl_mem_write_wire),
.alu_src,
.reg_write,
.alu_op //2 bits
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(){ int t,n; scanf( %d ,&t); while(t--){ scanf( %d ,&n); double ans=0; vector<double>miners; vector<double>diamonds; for(int i=0;i<2*n;i++){ double a,b; scanf( %lf%lf ,&a,&b); if (a==0){miners.push_back(abs(b));} if (b==0){diamonds.push_back(abs(a));} } sort(miners.begin(),miners.end()); sort(diamonds.begin(),diamonds.end()); for (int i=0;i<n;i++){ ans+=sqrt(miners[i]*miners[i]+diamonds[i]*diamonds[i]); } printf( %.15lf n ,ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; const int W = 1005; const long long inf = 1e18; struct dsu { vector<int> pr; vector<int> weights; vector<long long> beauties; set<int> roots; dsu(int _n) { pr.resize(_n + 5); weights.resize(_n + 5); beauties.resize(_n + 5); iota((pr).begin(), (pr).end(), 0); for (int u = (1); u <= ((_n)); u += (+1)) { roots.insert(u); } } int find(int u) { return pr[u] == u ? u : pr[u] = find(pr[u]); } bool unite(int u, int v) { u = find(u); v = find(v); if (u != v) { pr[u] = v; beauties[v] += beauties[u]; weights[v] += weights[u]; roots.erase(u); return true; } return false; } }; set<int> who[W]; long long dp[W]; int weights[N]; long long beauties[N]; bool done[W]; int n, m, max_w; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0), cout.precision(15); cin >> n >> m >> max_w; dsu dg(n); for (int u = (1); u <= ((n)); u += (+1)) { int w; cin >> w; dg.weights[u] = weights[u] = w; } for (int u = (1); u <= ((n)); u += (+1)) { long long b; cin >> b; dg.beauties[u] = beauties[u] = b; } for (int i = (0); i <= ((m)-1); i += (+1)) { int u, v; cin >> u >> v; dg.unite(u, v); } done[0] = true; for (int u : dg.roots) { for (int w = (max_w); w >= (0); w += (-1)) { if (w - dg.weights[u] < 0) { break; } int ru = dg.find(u); if (dp[w - dg.weights[u]] + dg.beauties[u] > dp[w] && !who[w - dg.weights[ru]].count(ru) && done[w - dg.weights[u]]) { done[w] = true; dp[w] = dp[w - dg.weights[u]] + dg.beauties[u]; who[w] = who[w - dg.weights[u]]; who[w].insert(ru); } } } for (int u = (1); u <= ((n)); u += (+1)) { for (int w = (max_w); w >= (0); w += (-1)) { if (w - weights[u] < 0) { break; } int ru = dg.find(u); if (dp[w - weights[u]] + beauties[u] > dp[w] && !who[w - weights[u]].count(ru) && done[w - weights[u]]) { done[w] = true; dp[w] = dp[w - weights[u]] + beauties[u]; who[w] = who[w - weights[u]]; who[w].insert(ru); } } } cout << *max_element(dp, dp + max_w + 1) << n ; return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM.v when simulating
// the core, RAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [3 : 0] wea;
input [7 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; bitset<50000000> arr; int primes[100100], pr = 0; int n; unsigned int A, B, C, D; int main() { cin >> n >> A >> B >> C >> D; for (int i = 2; i <= 18000; i++) { arr[i] = 1; } for (int i = 2; i <= 18000; i++) { if (arr[i] == 0) continue; primes[pr++] = i; for (int j = i * i; j <= 18000; j += i) { arr[j] = 0; } } int st = 2; unsigned int sol = 0; while (st <= n) { int en = min(st + 40000000, n); int ln = en - st + 1; for (int i = 0; i < ln; i++) { arr[i] = 1; } for (int i = 0; i < pr; i++) { int beg = max(primes[i] * primes[i], ((st + primes[i] - 1) / primes[i]) * primes[i]); for (int j = beg - st; j < ln; j += primes[i]) { arr[j] = 0; } } for (int i = 0; i < ln; i++) { if (arr[i] == 1) { unsigned int rep = 0; int cur_pr = st + i; while (cur_pr <= n) { rep += (unsigned int)(n / cur_pr); if (cur_pr > n / (st + i)) { break; } else { cur_pr *= (st + i); } } sol += rep * (A * (st + i) * (st + i) * (st + i) + B * (st + i) * (st + i) + C * (st + i) + D); } } st = en + 1; } cout << sol << endl; } |
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { char c = getchar(); x = 0; while (!isdigit(c) && !isalpha(c)) c = getchar(); if (isalpha(c)) return void(x = c - a ); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); } const int N = 5e5 + 5, SZ = 22; int n, vv, ww; int e, head[N], to[N << 1], val[N << 1], nxt[N << 1]; inline void add(int u, int v, int w) { to[++e] = v; val[e] = w; nxt[e] = head[u]; head[u] = e; } inline void add_edge(int u, int v, int w) { add(u, v, w); add(v, u, w); } int sz[N], son[N], f[1 << 22 | 5], dep[N], Son, Max, ans[N], cur[N], s[N]; inline void dfs1(int u, int fa) { sz[u] = 1; for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa) { int v = to[i], w = val[i]; s[v] = s[u] ^ (1 << w); dep[v] = dep[u] + 1; dfs1(v, u); sz[u] += sz[v]; if (sz[v] > sz[son[u]]) son[u] = v; } } inline void calc(int u, int fa) { if (f[s[u]]) Max = max(Max, f[s[u]] + dep[u]); for (int i = 1; i <= (1 << 21); i <<= 1) if (f[i ^ s[u]]) Max = max(Max, f[i ^ s[u]] + dep[u]); for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa) calc(to[i], u); } inline void update(int u, int fa) { f[s[u]] = max(f[s[u]], dep[u]); for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa) update(to[i], u); } inline void get_Max(int u, int fa) { for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa && to[i] != Son) { calc(to[i], u); update(to[i], u); } } inline void clear(int u, int fa) { f[s[u]] = 0; for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa) clear(to[i], u); } inline void dfs2(int u, int fa, bool keep) { for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa && to[i] != son[u]) dfs2(to[i], u, false); if (son[u]) dfs2(son[u], u, true); Son = son[u]; f[s[u]] = max(f[s[u]], dep[u]); get_Max(u, fa); ans[u] = max(f[s[u]] - dep[u], Max - 2 * dep[u]); for (int i = 1; i <= (1 << 21); i <<= 1) ans[u] = max(ans[u], f[i ^ s[u]] - dep[u]); for (int i = head[u]; i; i = nxt[i]) if (to[i] != fa) ans[u] = max(ans[u], ans[to[i]]); Son = Max = 0; if (!keep) clear(u, fa); } int main() { read(n); for (int uu = 2; uu <= n; uu++) { read(vv); read(ww); add_edge(uu, vv, ww); } dfs1(1, 0); dfs2(1, 0, 0); for (int i = 1; i <= n; i++) printf( %d , ans[i]); return 0; } |
/*
* This demonstrates a basic dynamic array
*/
module main;
int foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i += 2) { cout << a[i + 1] << << -1 * a[i] << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long long ll; const int maxn=1e6+7; const int inf=2e9; const ll inff=1e18; const ll mod=1e9+7; #define pii pair<int,int> #define mkp make_pair #define F first #define S second #define pb push_back #define sz(v) ((int)(v).size()) #define all(v) (v).begin(),(v).end() //#define int ll int32_t main(){ ios::sync_with_stdio(0); cin.tie(0); int t; cin>>t; while (t--) { int n; cin>>n; vector<int> v(n); for (int &i:v) cin>>i; sort(all(v)); ll ans=0; for (int i=1;i<n;i++) ans+=(v[i]-v[i-1]); for (int i=1;i<n;i++) { ans-=i*1LL*(n-i)*(v[i]-v[i-1]); } cout<<ans<< n ; } } |
`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
always @ ( iAddress )
begin
case (iAddress)
/* 0: oInstruction = { `NOP ,24'd400 };
1: oInstruction = { `STO , `R7,16'b0001 };
2: oInstruction = { `STO ,`R3,16'h1 };
3: oInstruction = { `STO, `R4,16'd100 };
4: oInstruction = { `STO, `R5,16'd0 }; //j
//LOOP2:
5: oInstruction = { `LED ,8'b0,`R7,8'b0 };
6: oInstruction = { `STO ,`R1,16'h0 };
7: oInstruction = { `STO ,`R2,16'd65000 };
//LOOP1:
8: oInstruction = { `ADD ,`R1,`R1,`R3 };
9: oInstruction = { `BLE ,`LOOP1,`R1,`R2 };
10: oInstruction = { `ADD ,`R5,`R5,`R3 };
11: oInstruction = { `BLE ,`LOOP2,`R5,`R4 };
12: oInstruction = { `NOP ,24'd4000 };
13: oInstruction = { `ADD ,`R7,`R7,`R3 };
14: oInstruction = { `JMP , 8'd2,16'b0 }; */
0: oInstruction = { `NOP ,24'd400 };
1: oInstruction = { `STO ,`R1,16'd3};
2: oInstruction = { `STO ,`R2,16'd7};
3: oInstruction = { `SMUL ,`R4, `R1, `R3};
4: oInstruction = { `LED ,8'b0, `R4,8'b0 };
5: oInstruction = { `JMP , 8'd1,16'b0 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
// vim: ts=4 sw=4 noexpandtab
/*
* Block RAM
*
* Copyright (c) 2019 Michael Buesch <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`ifndef BLOCK_RAM_MOD_V_
`define BLOCK_RAM_MOD_V_
module block_ram #(
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 8,
parameter MEM_BYTES = 1024,
) (
input clk,
/* Port 0 */
input [ADDR_WIDTH - 1 : 0] addr0,
output reg [DATA_WIDTH - 1 : 0] rd_data0,
input [DATA_WIDTH - 1 : 0] wr_data0,
input wr0,
/* Port 1 */
input [ADDR_WIDTH - 1 : 0] addr1,
output reg [DATA_WIDTH - 1 : 0] rd_data1,
);
reg [DATA_WIDTH - 1 : 0] mem [MEM_BYTES - 1 : 0];
integer i;
initial begin
for (i = 0; i < MEM_BYTES; i++) begin
mem[i] <= 0;
end
end
always @(posedge clk) begin
if (wr0) begin
mem[addr0] <= wr_data0;
end
rd_data0 <= mem[addr0];
rd_data1 <= mem[addr1];
end
endmodule
`endif /* BLOCK_RAM_MOD_V_ */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_2_V
`define SKY130_FD_SC_LP__DFSTP_2_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_2 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfstp_2 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__TAPVGND_FUNCTIONAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_BEHAVIORAL_V |
#include<bits/stdc++.h> using namespace std; #define pi acos(-1) #define printfl printf( %f n ,f) #define printd printf( %lf n ,d) #define printi printf( %d n ,p) #define printl printf( %ld n ,l) #define printll printf( %lld n ,ll) #define case cout<< Case <<TEST<< : #define forcase for(int TEST=1;TEST<=test;TEST++) #define max3(a,b,c) max((a,b),c) #define min3(a,b,c) min((a,b),c) #define newl printf( n ) #define printd1d2 printf( %lf %lf n ,d1, d2) #define ll long long int void solve() { ll n,q;cin>>n>>q; string s;cin>>s; map <ll,ll> mp; ll indx=1; for (ll i = 1; i <=26; i++) { mp[i-1]=i; } ll sum[n+1]; sum[0]=0; ll l=1; for (ll i = 0; i < s.size(); i++) { sum[l]=sum[l-1]+mp[s[i]- a ]; l++; } for (ll i = 0; i < q; i++) { ll c,d;cin>>c>>d; cout<<sum[d]-sum[c-1]<<endl; } // cout<<sum[13]<<endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int test; // cin>>test; //forcase solve(); return 0; } |
/*
* This test tries to assure that all synchronous UDP outputs are
* scheduled before any non-blocking assignment event. The reason
* is that primitive outputs are scheduled in the active event
* queue, which is supposed to empty before any non-blocking
* assignments take effect.
*
* This is based on an example by Steve Sharp
*/
primitive u_dff(q,d,c);
output q;
reg q;
input d,c;
table
//d c : q : q+
0 p : ? : 0 ;
1 p : ? : 1 ;
? n : ? : - ;
* ? : ? : - ;
endtable
endprimitive
module top;
reg rclk, dclk;
wire clk = rclk;
wire q0,q1,q2,q3,q4;
u_dff ff0(q0, 1'b1, clk),
ff1(q1, 1'b1, q0),
ff2(q2, 1'b1, q1),
ff3(q3, 1'b1, q2),
ff4(q4, 1'b1, q3);
initial
begin
#1
// Blocking assign makes an active event that
// starts the u_dff devices rippling
rclk = 1;
// Non-blocking assign and the following @(dclk) pause
// the thread until the non-blocking event queue is
// processed.
dclk <= 1;
@(dclk)
if (q4 !== 1'b1) begin
$display("FAILED -- q4 did not propagate in time (q4=%b)", q4);
$finish;
end
$display("q4=%b", q4);
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; long long mod = 1000000007LL; long long mod2 = 998244353LL; int t, n; int a[200005]; int dp[200005][2]; int main() { cin >> t; for (int cas = 1; cas <= t; ++cas) { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } for (int i = 0; i <= n; ++i) { for (int j = 0; j < 2; ++j) { dp[i][j] = inf; } } dp[0][0] = 0; for (int i = 0; i < n; ++i) { if (dp[i][0] < inf) { if (a[i + 1]) { dp[i + 1][1] = min(dp[i + 1][1], dp[i][0] + 1); } else { dp[i + 1][1] = min(dp[i + 1][1], dp[i][0]); } if (i + 2 <= n) { int cnt = a[i + 1] + a[i + 2]; dp[i + 2][1] = min(dp[i + 2][1], dp[i][0] + cnt); } } if (dp[i][1] < inf) { dp[i + 1][0] = min(dp[i + 1][0], dp[i][1]); if (i + 2 <= n) { dp[i + 2][0] = min(dp[i + 2][0], dp[i][1]); } } } int res = min(dp[n][0], dp[n][1]); printf( %d n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n; long long a[100005]; long long preA[100005]; int main() { cin >> n; for (long long i = 0; i < n; ++i) { cin >> a[i]; } preA[0] = 0; for (long long i = 1; i < n; ++i) { preA[i] = preA[i - 1] + a[i]; } set<long long> nos; map<long long, long long> freq; for (long long i = 0; i < n; ++i) { if (nos.find(preA[i]) != nos.end()) { freq[preA[i]]++; } else { nos.insert(preA[i]); freq[preA[i]] = 1; } } long long maxFreq = -1; for (set<long long>::iterator it = nos.begin(); it != nos.end(); ++it) { if (maxFreq < freq[*it]) { maxFreq = freq[*it]; } } cout << n - maxFreq; } |
#include <bits/stdc++.h> using namespace std; long long l, r, ans = 0; int main() { cin >> l >> r; for (long long i = 1; i <= r; i *= 2) { for (long long j = 1; j <= r; j *= 3) { if (i * j >= l && i * j <= r) ans++; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; long long int M = 1e9 + 7; long long int MOD = 998244353; const double PI = 3.141592653589793238460; long long int power(long long int a, long long int b) { long long int res = 1; if (a == 0) return 0; if (a == 1) return 1; for (; b > 0; b >>= 1) { if (b & 1) { res = (res * a); if (res > M) res %= M; } a = (a * a); if (a > M) a = a % M; } return res; } int main() { long long int maxi = -1e18; long long int n; cin >> n; long long int a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) { long long int x = a[i]; long long int y = b[i]; for (int j = i; j < n; j++) { x |= (a[j]); y |= (b[j]); maxi = max(maxi, x + y); } } cout << maxi; } |
#include <bits/stdc++.h> using namespace std; int main() { string com; map<string, bool> mp; int ans = 0; while (getline(cin, com)) { if (com[0] == + ) { com.erase(com.begin(), com.begin() + 1); mp[com] = 1; } else if (com[0] == - ) { com.erase(com.begin(), com.begin() + 1); mp[com] = 0; } else { int len = com.size() - com.find( : ) - 1, cnt = 0; for (map<string, bool>::iterator it = mp.begin(); it != mp.end(); it++) { if (it->second) cnt++; } ans += cnt * len; } } cout << ans << endl; return 0; } |
/*
* 16-bit 8-way multiplexor
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_mux8_16(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [15:0] out;
reg [15:0] out;
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
iNFromException#(parameter width = 1) (
input signedOut,
input isNaN,
input sign,
output [(width - 1):0] out
);
wire maxInt = isNaN || !sign;
assign out = {signedOut ^ maxInt, {(width - 1){maxInt}}};
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[300], a[300], num[300]; int find(int x) { if (p[x] == 0) return x; else { p[x] = find(p[x]); return p[x]; } } void merge(int x, int y) { x = find(x); y = find(y); if (x != y) p[x] = y; } int main() { int n, m, ans, i, x, j, k; scanf( %d%d , &n, &m); ans = 0; for (i = 1; i <= n; ++i) { scanf( %d , &x); for (j = 1; j <= x; ++j) { scanf( %d , &a[j]); ++num[a[j]]; } if (x == 0) { ++ans; continue; } for (k = 2; k <= x; ++k) merge(a[1], a[k]); } bool flag = false; for (i = 1; i <= m; ++i) { if (p[i] == 0 && num[i] > 0) { ++ans; flag = true; } } if (flag) --ans; printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, n; cin >> n; k = n / 2; for (i = 1; i <= n; i++) { cout << (i - 1) * k + 1; for (j = (i - 1) * k + 2; j <= i * k; j++) cout << << j; for (j = n * n - (i - 1) * k; j > n * n - i * k; j--) cout << << j; cout << endl; } return 0; } |
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
// Major Functions:
// This code is using for generating a pulse while FPGA is configured
// ============================================================================
// Design Description:
//
//
//
// ===========================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 12/02/20 :| Initial Version
// ============================================================================
`define REG_SIZE 20
module initial_config(
iCLK, // system clock 50mhz
iRST_n, // system reset
oINITIAL_START,
iINITIAL_ENABLE,
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
//===========================================================================
// PORT declarations
//===========================================================================
input iCLK;
input iRST_n;
output oINITIAL_START;
input iINITIAL_ENABLE;
//=============================================================================
// REG/WIRE declarations
//=============================================================================
wire oINITIAL_START;
reg [`REG_SIZE-1:0] cnt;
//=============================================================================
// Structural coding
//=============================================================================
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
cnt <= 0;
end
else if (cnt == 20'hfffff)
begin
cnt <=20'hfffff;
end
else
begin
cnt <= cnt + 1;
end
end
assign oINITIAL_START = ((cnt == 20'hffffe)&iINITIAL_ENABLE) ? 1'b1: 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_2_V
`define SKY130_FD_SC_HS__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_2_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 900; struct edge { int v, w, b; double c; }; vector<edge> adj[maxn]; int n, k; int s, t; double dis[maxn]; int bk[maxn], bki[maxn]; bool inq[maxn]; long long x[maxn], y[maxn]; inline void ae(int u, int v, int w, double c) { edge nu, nv; nu.v = v; nu.w = w; nu.c = c; nu.b = adj[v].size(); nv.v = u; nv.w = 0; nv.c = -c; nv.b = adj[u].size(); adj[u].push_back(nu); adj[v].push_back(nv); } inline pair<int, double> spfa() { for (int i = 0; i < maxn; i++) dis[i] = 1e30; memset(inq, 0, sizeof(inq)); dis[s] = 0; queue<int> q; q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); inq[u] = 0; for (int i = adj[u].size() - 1; i >= 0; i--) { int v = adj[u][i].v; int w = adj[u][i].w; double c = adj[u][i].c; if (dis[u] + c < dis[v] && w != 0) { dis[v] = dis[u] + c; bk[v] = u; bki[v] = i; if (!inq[v]) { q.push(v); inq[v] = 1; } } } } if (dis[t] > 1e20) return make_pair(-1, 0.0); int cur = t; int flw = 0x3f3f3f3f; while (cur != s) { flw = min(flw, adj[bk[cur]][bki[cur]].w); cur = bk[cur]; } cur = t; double cst = 0; while (cur != s) { adj[bk[cur]][bki[cur]].w -= flw; adj[cur][adj[bk[cur]][bki[cur]].b].w += flw; cst += flw * adj[bk[cur]][bki[cur]].c; cur = bk[cur]; } return make_pair(flw, cst); } inline pair<int, double> ek() { pair<int, double> ans = make_pair(0ll, 0.0); while (1) { pair<int, double> cr = spfa(); if (cr.first <= 0) return ans; ans.first += cr.first; ans.second += cr.second; } } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> x[i] >> y[i]; } s = n + n + 1; t = n + n + 3; for (int i = 1; i <= n; i++) { ae(s, i, 2, 0.0); ae(i + n, t, 1, 0.0); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j) continue; if (y[i] > y[j]) ae(i, j + n, 1, sqrt((x[i] - x[j]) * (x[i] - x[j]) + (y[i] - y[j]) * (y[i] - y[j]))); } } pair<int, double> ans = ek(); if (ans.first != n - 1) cout << -1; else printf( %.15lf , ans.second); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_SYMBOL_V
/**
* top_ground_hvc_wpad: Ground pad.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_ground_hvc_wpad (
//# {{data|Data Signals}}
inout G_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout G_CORE ,
inout VSWITCH ,
inout DRN_HVC ,
inout OGC_HVC ,
inout SRC_BDY_HVC,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GROUND_HVC_WPAD_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:44:38 02/19/2017
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input wire clk, reset,
input wire sensorA,
input wire sensorB,
output wire sensorAdb,
output wire sensorBdb,
output wire [3:0] enable, // enable 1-out-of-4 asserted low
output wire [7:0] sseg // led segments
);
wire [3:0] counter;
// Debounce sensorA
debouncer dbA (
.clk (clk),
.reset (reset),
.sw (sensorA),
.db (sensorAdb)
);
// Debounce sensorA
debouncer dbB (
.clk (clk),
.reset (reset),
.sw (sensorB),
.db (sensorBdb)
);
//instantiation of car_detector
car_detector count1(
.clk (clk),
.res (reset),
.sensorA (sensorAdb),
.sensorB (sensorBdb),
.car_count (counter)
);
//instantiation of sevenSegValue controller
sevenSegValue brd1(
.d_in (counter),
.an (enable),
.sseg (sseg)
);
endmodule
|
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