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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_P_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_P_SYMBOL_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_P_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFXBP_FUNCTIONAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_pg/sky130_fd_sc_hs__u_df_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxbp (
VPWR,
VGND,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , mux_out, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_FUNCTIONAL_PP_V |
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
module block_ram
(
input clock,
input [DBITS-1:0] w_data,
input w_valid,
input [ABITS-1:0] w_addr,
output reg [DBITS-1:0] r_data,
input [ABITS-1:0] r_addr
);
parameter ABITS = 9;
parameter DBITS = 64;
reg [DBITS-1:0] bram[0:2**ABITS-1];
reg [DBITS-1:0] bram_oreg;
always @ (posedge clock)
begin
if(w_valid)
bram[w_addr] <= w_data;
bram_oreg <= bram[r_addr];
r_data <= bram_oreg;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return (a ? gcd(b % a, a) : b); } long long power(long long a, long long n) { long long p = 1; while (n > 0) { if (n & 1) { p = p * a; } n >>= 1; a *= a; } return p; } long long power(long long a, long long n, long long mod) { long long p = 1; while (n > 0) { if (n & 1) { p = p * a; p %= mod; } n >>= 1; a *= a; a %= mod; } return p % mod; } const int N = 300005; long long x[N]; long long d[N], a[N]; long long find(int i, int j) { if (i == 0) return x[j]; return (x[j] - x[i - 1] + 1000000007) % 1000000007; } int main() { int i, j; int n; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); x[0] = 1; for (i = 1; i < n; i++) { d[i] = a[i] - a[i - 1]; x[i] = (power(2ll, i, 1000000007) + x[i - 1]) % 1000000007; } long long ans = 0; for (i = 1; i < n; i++) { ans += (d[i] * find(i - 1, n - 2)) % 1000000007; } long long z = ans; for (i = 2; i < n; i++) { z = (z - (d[i - 1] * x[n - i]) % 1000000007 + 1000000007) % 1000000007; z = (z * power(2, 1000000007 - 2, 1000000007)) % 1000000007; ans = (ans + z) % 1000000007; } printf( %lld n , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O221AI_BEHAVIORAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, m; string s; vector<int> q; int mo[] = {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int h, w; int data(int x, int y) { int tmp = 0; for (int i = 0; i < x - 1; i++) tmp += mo[i]; return tmp + y; } int cal(int x, int y, int z) { return x * 60 * 60 + y * 60 + z; } int getpos(string s) { int p = data((s[5] - 0 ) * 10 + s[6] - 0 , (s[8] - 0 ) * 10 + s[9] - 0 ); int res = (p - 1) * 24 * 60 * 60; res += cal((s[11] - 0 ) * 10 + s[12] - 0 , (s[14] - 0 ) * 10 + s[15] - 0 , (s[17] - 0 ) * 10 + s[18] - 0 ); return res; } int main() { cin >> n >> m; h = 0; getline(cin, s); while (getline(cin, s)) { int t = getpos(s); q.push_back(t); while (h < q.size() && t - q[h] >= n) h++; if (q.size() - h >= m) { for (int i = 0; i <= 18; i++) cout << s[i]; cout << endl; return 0; } } cout << -1 << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:46:57 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/RAT_RegisterFile_0_0_stub.v
// Design : RAT_RegisterFile_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "RegisterFile,Vivado 2016.4" *)
module RAT_RegisterFile_0_0(D_IN, DX_OUT, DY_OUT, ADRX, ADRY, WE, CLK)
/* synthesis syn_black_box black_box_pad_pin="D_IN[7:0],DX_OUT[7:0],DY_OUT[7:0],ADRX[4:0],ADRY[4:0],WE,CLK" */;
input [7:0]D_IN;
output [7:0]DX_OUT;
output [7:0]DY_OUT;
input [4:0]ADRX;
input [4:0]ADRY;
input WE;
input CLK;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_2TO1_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; t = 1; while (t--) { int c = 0; std::vector<int> v; string s[3]; getline(cin, s[0]); getline(cin, s[1]); getline(cin, s[2]); for (int i = 0; i <= 2; i++) { for (int j = 0; j <= s[i].length() - 1; j++) { if (s[i][j] == a || s[i][j] == e || s[i][j] == i || s[i][j] == o || s[i][j] == u ) c++; } v.push_back(c); c = 0; } if (v[0] == 5 && v[1] == 7 && v[2] == 5) { cout << YES ; } else { cout << NO ; } } cerr << Time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; } |
//#############################################################################
//# Function: Clock mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockmux #(parameter N = 1) // number of clock inputs
(
input [N-1:0] en, // one hot enable vector (needs to be stable!)
input [N-1:0] clkin,// one hot clock inputs (only one is active!)
output clkout
);
`ifdef CFG_ASIC
generate
if((N==2))
begin : asic
asic_clockmux2 imux (.clkin(clkin[N-1:0]),
.en(en[N-1:0]),
.clkout(clkout));
end
else if((N==4))
begin : asic
asic_clockmux4 imux (.clkin(clkin[N-1:0]),
.en(en[N-1:0]),
.clkout(clkout));
end
endgenerate
`else // !`ifdef CFG_ASIC
assign clkout = |(clkin[N-1:0] & en[N-1:0]);
`endif
endmodule // oh_clockmux
|
module SwapUnit(rs,rt,rd,EXMEMregWrite,EXMEMregisterRd,MEMWBregisterRd,MEMWBregWrite,forwardA,forwardB,rst);
input[4:0] rs,rt,rd,EXMEMregisterRd,MEMWBregisterRd;
input EXMEMregWrite,MEMWBregWrite;
output[1:0] forwardB,forwardA;
reg[1:0] forwardA,forwardB;
input rst;
always @(rs or rt or rd or EXMEMregWrite or EXMEMregisterRd or MEMWBregisterRd or MEMWBregWrite or forwardA or forwardB or rst) begin
if (rst) begin
// reset
forwardA<=0;
forwardB<=0;
end
else begin
if(MEMWBregWrite && (MEMWBregisterRd!=0) && !((EXMEMregWrite && (EXMEMregisterRd!=0)) && (EXMEMregisterRd==rs)) && (MEMWBregisterRd==rs))forwardA<=2'b01;
else if(EXMEMregWrite && (EXMEMregisterRd!=0) && (EXMEMregisterRd==rs)) forwardA<=2'b10;
else forwardA<=0;
if(MEMWBregWrite && (MEMWBregisterRd!=0) && !((EXMEMregWrite && (EXMEMregisterRd!=0)) && (EXMEMregisterRd==rt)) && (MEMWBregisterRd==rt))forwardB<=2'b01;
else if(EXMEMregWrite && (EXMEMregisterRd!=0) && (EXMEMregisterRd==rt)) forwardB<=2'b10;
else forwardB<=0;
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLXTN_FUNCTIONAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_FUNCTIONAL_PP_V |
// TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using std::map; long long n; long long p2[100005 * 2] = {1}; long long fa[100005 * 2], size[100005 * 2], p[100005 * 2]; long long vis[100005 * 2]; map<long long, long long> mx, my; long long cnt; long long ans = 1; long long getfa(long long x) { return fa[x] == x ? x : fa[x] = getfa(fa[x]); } int main() { scanf( %I64d , &n); for (long long i = 1; i <= n * 2; i++) { fa[i] = i; size[i] = 1; p2[i] = (p2[i - 1] * 2) % ((int)1e9 + 7); } long long x, y, px, py, fx, fy; for (long long i = 1; i <= n; i++) { scanf( %I64d %I64d , &x, &y); if (mx.find(x) == mx.end()) { mx[x] = ++cnt; } if (my.find(y) == my.end()) { my[y] = ++cnt; } px = mx[x]; py = my[y]; fx = getfa(px); fy = getfa(py); if (fx == fy) { p[fx] = 1; } else { fa[fx] = fy; size[fy] += size[fx]; p[fy] |= p[fx]; } getfa(px); } for (long long i = 1; i <= cnt; i++) { long long fi = getfa(i); if (vis[fi]) continue; vis[fi] = 1; if (p[fi]) { ans *= p2[size[fi]]; } else { ans *= (p2[size[fi]] - 1); } ans %= ((int)1e9 + 7); } printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 410; int cl[maxn * maxn]; int po[maxn * maxn]; int pre[maxn * maxn * 2]; int cnt[maxn * maxn * 2]; short cc[maxn * maxn * 2]; short F[maxn][maxn]; short g[maxn][maxn]; int a[maxn][maxn]; int b[maxn][maxn]; int pos[maxn][maxn]; int n, m; int find(int x) { return cnt[x] ? x : pre[x] = find(pre[x]); } inline void init(int x, short f[][maxn], int a[][maxn]) { int tot = maxn * maxn; for (int i = x; i <= n; i++) { for (int j = 1; j <= m; j++) { cl[a[i][j]] = 0, po[a[i][j]] = a[i][j] + 1; cc[a[i][j] + 1] = 0; cnt[a[i][j] + 1] = 1; } } for (int i = 0; i <= m; i++) f[x - 1][i] = 0; for (int j = 1; j <= m; j++) { for (int i = x; i <= n; i++) { if (cl[a[i][j]] != j) { pos[i][j] = tot; cnt[tot] = 1; cc[tot] = j; pre[tot] = po[a[i][j]]; po[a[i][j]] = tot; tot++; } else { pos[i][j] = po[a[i][j]]; cnt[pos[i][j]]++; } cl[a[i][j]] = j; } } for (int i = n; i >= x; i--) { for (int j = m; j > 0; j--) { int p = pos[i][j]; cnt[p]--; f[i][j] = cc[find(p)]; } } for (int i = x; i <= n; i++) { for (int j = 1; j <= m; j++) { f[i][j] = max(f[i][j], max(f[i - 1][j], f[i][j - 1])); } } } int main() { int w = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); b[i][m - j + 1] = a[i][j]; } } int ans = 0; for (int i = 1; i <= n; i++) { init(i, F, a); init(i, g, b); for (int j = i; j <= n; j++) { int r = 1; for (int k = 1; k <= m; k++) { for (int len = m - g[j][m - k + 1]; r <= len; r++) { if (F[j][r] >= k) break; } ans = max(ans, (j - i + 1) * (r - k)); } } } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int n, m; string s[20][20]; string ran = 23456789TJQKA ; string sui = CDHS ; set<string> st; int j1x = -1, j1y = -1, j2x = -1, j2y = -1; inline bool ok(int x, int y) { set<char> ra, su; for (int i = x; i < x + 3; i++) { for (int j = y; j < y + 3; j++) { ra.insert(s[i][j][0]); su.insert(s[i][j][1]); } } return ra.size() == 9 || su.size() == 1; } int main() { cin >> n >> m; for (int i = 0; i < 13; i++) { for (int j = 0; j < 4; j++) { string ss = ; ss[0] = ran[i]; ss[1] = sui[j]; st.insert(ss); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> s[i][j]; if (s[i][j] != J1 && s[i][j] != J2 ) st.erase(s[i][j]); else if (s[i][j] == J1 ) j1x = i, j1y = j; else j2x = i, j2y = j; } } for (set<string>::iterator it1 = st.begin(); it1 != st.end(); it1++) { if (j1x != -1) s[j1x][j1y] = (*it1); for (set<string>::iterator it2 = st.begin(); it2 != st.end(); it2++) { if (it1 == it2) continue; if (j2x != -1) s[j2x][j2y] = (*it2); vector<pair<int, int> > v; for (int i = 0; i <= n - 3; i++) { for (int j = 0; j <= m - 3; j++) if (ok(i, j)) v.push_back(make_pair(i + 1, j + 1)); } for (int i = 0; i < v.size(); i++) { for (int j = 0; j < i; j++) { if (abs(v[i].first - v[j].first) > 2 || abs(v[i].second - v[j].second) > 2) { cout << Solution exists. n ; if (j1x == -1 && j2x == -1) cout << There are no jokers. n ; if (j1x == -1 && j2x != -1) cout << Replace J2 with << (*it2) << . n ; if (j1x != -1 && j2x == -1) cout << Replace J1 with << (*it1) << . n ; if (j1x != -1 && j2x != -1) cout << Replace J1 with << (*it1) << and J2 with << (*it2) << . n ; cout << Put the first square to ( << v[i].first << , << v[i].second << ). n ; cout << Put the second square to ( << v[j].first << , << v[j].second << ). n ; exit(0); } } } } } cout << No solution. ; return 0; } |
#include <bits/stdc++.h> using namespace std; int ar[200010]; vector<int> ans; void solve() { int n, a, b, k, cnt = 0; cin >> n >> a >> b >> k; string s; cin >> s; int nxt = n + 1; for (int i = n; i > 0; i--) { if (s[i - 1] == 1 ) { cnt += (nxt - i - 1) / b; nxt = i; } ar[i] = nxt; } cnt += (nxt - 1) / b; int last = 0; if (cnt < a) { printf( 0 n ); return; } for (int i = 1; i <= n; i++) { if (s[i - 1] == 1 ) { last = i; continue; } if (i - last == b) { cnt--; ans.push_back(i); last = i; if (cnt < a) break; } } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) { printf( %d , ans[i]); } printf( n ); } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_M_V
`define SKY130_FD_SC_LP__MUX2I_M_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_m (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_m (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_M_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 9: 0] in_port;
input reset_n;
wire clk_en;
wire [ 9: 0] data_in;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_4_V
`define SKY130_FD_SC_LP__A2111O_4_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_4_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %Version
// \ \ Application: MIG
// / / Filename: circ_buffer.v
// /___/ /\ Date Last Modified: $Date: 2010/10/05 16:43:09 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Circular Buffer for synchronizing signals between clock domains. Assumes
// write and read clocks are the same frequency (but can be varying phase).
// Parameter List;
// DATA_WIDTH: # bits in data bus
// BUF_DEPTH: # of entries in circular buffer.
// Port list:
// rdata: read data
// wdata: write data
// rclk: read clock
// wclk: write clock
// rst: reset - shared between read and write sides
//Reference:
//Revision History:
// Rev 1.1 - Initial Checkin - jlogue 03/06/09
//*****************************************************************************
/******************************************************************************
**$Id: circ_buffer.v,v 1.1 2010/10/05 16:43:09 mishra Exp $
**$Date: 2010/10/05 16:43:09 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_7/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/circ_buffer.v,v $
******************************************************************************/
`timescale 1ps/1ps
module circ_buffer #
(
parameter TCQ = 100,
parameter BUF_DEPTH = 5, // valid values are 5, 6, 7, and 8
parameter DATA_WIDTH = 1
)
(
output[DATA_WIDTH-1:0] rdata,
input [DATA_WIDTH-1:0] wdata,
input rclk,
input wclk,
input rst
);
//***************************************************************************
// Local parameters
//***************************************************************************
localparam SHFTR_MSB = (BUF_DEPTH-1)/2;
//***************************************************************************
// Internal signals
//***************************************************************************
reg SyncResetRd;
reg [SHFTR_MSB:0] RdCEshftr;
reg [2:0] RdAdrsCntr;
reg SyncResetWt;
reg WtAdrsCntr_ce;
reg [2:0] WtAdrsCntr;
//***************************************************************************
// read domain registers
//***************************************************************************
always @(posedge rclk or posedge rst)
if (rst) SyncResetRd <= #TCQ 1'b1;
else SyncResetRd <= #TCQ 1'b0;
always @(posedge rclk or posedge SyncResetRd)
begin
if (SyncResetRd)
begin
RdCEshftr <= #TCQ 'b0;
RdAdrsCntr <= #TCQ 'b0;
end
else
begin
RdCEshftr <= #TCQ {RdCEshftr[SHFTR_MSB-1:0], WtAdrsCntr_ce};
if(RdCEshftr[SHFTR_MSB])
begin
if(RdAdrsCntr == (BUF_DEPTH-1)) RdAdrsCntr <= #TCQ 'b0;
else RdAdrsCntr <= #TCQ RdAdrsCntr + 1;
end
end
end
//***************************************************************************
// write domain registers
//***************************************************************************
always @(posedge wclk or posedge SyncResetRd)
if (SyncResetRd) SyncResetWt <= #TCQ 1'b1;
else SyncResetWt <= #TCQ 1'b0;
always @(posedge wclk or posedge SyncResetWt)
begin
if (SyncResetWt)
begin
WtAdrsCntr_ce <= #TCQ 1'b0;
WtAdrsCntr <= #TCQ 'b0;
end
else
begin
WtAdrsCntr_ce <= #TCQ 1'b1;
if(WtAdrsCntr_ce)
begin
if(WtAdrsCntr == (BUF_DEPTH-1)) WtAdrsCntr <= #TCQ 'b0;
else WtAdrsCntr <= #TCQ WtAdrsCntr + 1;
end
end
end
//***************************************************************************
// instantiate one RAM64X1D for each data bit
//***************************************************************************
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i = i+1) begin: gen_ram
RAM64X1D #
(
.INIT (64'h0000000000000000)
)
u_RAM64X1D
(.DPO (rdata[i]),
.SPO (),
.A0 (WtAdrsCntr[0]),
.A1 (WtAdrsCntr[1]),
.A2 (WtAdrsCntr[2]),
.A3 (1'b0),
.A4 (1'b0),
.A5 (1'b0),
.D (wdata[i]),
.DPRA0 (RdAdrsCntr[0]),
.DPRA1 (RdAdrsCntr[1]),
.DPRA2 (RdAdrsCntr[2]),
.DPRA3 (1'b0),
.DPRA4 (1'b0),
.DPRA5 (1'b0),
.WCLK (wclk),
.WE (1'b1)
);
end
endgenerate
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_22ns_30_3_MAC3S_0(clk, ce, a, b, p);
input clk;
input ce;
input[8 - 1 : 0] a; // synthesis attribute keep a "true"
input[22 - 1 : 0] b; // synthesis attribute keep b "true"
output[30 - 1 : 0] p;
reg [8 - 1 : 0] a_reg0;
reg [22 - 1 : 0] b_reg0;
wire [30 - 1 : 0] tmp_product;
reg [30 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_22ns_30_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
image_filter_mul_8ns_22ns_30_3_MAC3S_0 image_filter_mul_8ns_22ns_30_3_MAC3S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module videout(
input CLK_6MB,
input nBNKB,
input SHADOW,
input [15:0] PC,
output reg [6:0] VIDEO_R,
output reg [6:0] VIDEO_G,
output reg [6:0] VIDEO_B
);
// Color data latch/blanking
always @(posedge CLK_6MB)
begin
VIDEO_R <= nBNKB ? {SHADOW, PC[11:8], PC[14], PC[15]} : 7'b0000000;
VIDEO_G <= nBNKB ? {SHADOW, PC[7:4], PC[13], PC[15]} : 7'b0000000;
VIDEO_B <= nBNKB ? {SHADOW, PC[3:0], PC[12], PC[15]} : 7'b0000000;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> tt[1005], kk[1005]; int n1, n2, top; vector<int> vv[1005]; int main() { int k, i, j, n, a, tmp; long long ans = 0, sum = 0; scanf( %d %d , &n, &k); for (i = 0; i < n; i++) { scanf( %d %d , &a, &tmp); if (tmp == 1) tt[n1++] = make_pair(a, i + 1); else kk[n2++] = make_pair(a, i + 1); sum += (long long)a; } sort(tt, tt + n1); sort(kk, kk + n2); if (n1 < k) { for (i = n1 - 1; i >= 0; i--) { vv[top++].push_back(tt[i].second); ans += (long long)tt[i].first; } for (i = 0; top < k; i++) vv[top++].push_back(kk[i].second); for (; i < n2; i++) vv[top - 1].push_back(kk[i].second); } else { for (i = n1 - 1; top < k - 1; i--) { vv[top++].push_back(tt[i].second); ans += (long long)tt[i].first; } if (n1 > 0 && n2 > 0) ans += (long long)min(tt[0].first, kk[0].first); else if (n1 > 0) ans += (long long)tt[0].first; else ans += (long long)kk[0].first; for (; i >= 0; i--) vv[top].push_back(tt[i].second); for (i = 0; i < n2; i++) vv[top].push_back(kk[i].second); } printf( %I64d. , sum - (ans + 1) / 2); if (ans & 1) printf( 5 ); else printf( 0 ); putchar( n ); for (i = 0; i < k; i++) { printf( %d , (int)vv[i].size()); for (j = 0; j < (int)vv[i].size(); j++) printf( %d , vv[i][j]); putchar( n ); } } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_system_nios2_qsys_0_jtag_debug_module_tck the_nios_system_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_system_nios2_qsys_0_jtag_debug_module_sysclk the_nios_system_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_system_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long FastPower(long long x, long long y) { long long res = 1; x = x % MOD; while (y > 0) { if (y & 1) res = (res * x) % MOD; y = y >> 1; x = (x * x) % MOD; } return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; string s; cin >> s; n = s.size(); long long x = 0, y = 0; y = FastPower(2, n - 1); for (int i = 0, j = n - 1; i < n; i++, j--) { if (s[j] == 1 ) { x += FastPower(2, i); x %= MOD; } } cout << (x * y) % MOD; return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History: 3/14/2012 Adding support for "nCK_PER_CLK == 2" abd MEM_BURST_LEN == 2 "
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter nCK_PER_CLK = 4,
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6")
begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ||
// (FAMILY == "VIRTEX6") )
else
begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
// remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop
// sending more read commands but still accepting it if there is one coming.
assign wr_en = cmd_valid_i & !full & wait_done;
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
if (FAMILY == "SPARTAN6")
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
else
// if (nCK_PER_CLK == 2 )
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
// else
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) ))
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
if (rd_data_received_counts[6] == rd_data_counts_asked[6])
buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 );
else
buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] );
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
end
assign gen_valid_o = !empty;
mig_7series_v1_9_afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
/* verilator lint_off UNUSED */
/* verilator lint_off CASEX */
module synthetic_op ( clk , sel, opa32, opb32 , res64 );
input clk;
input [2:0] sel;
input [31:0] opa32,opb32;
output [63:0] res64;
wire signed [31:0] sopa32,sopb32;
wire [31:0] uopa32,uopb32;
wire [31:0] aopa32,aopb32;
wire [63:0] out_abs;
reg [47:0] unsign_st1a, unsign_st1b;
reg [ 2:0] pipe1,pipe2;
reg [31:0] pipea,pipeb;
// cast
assign sopa32 = (sel[1:0] == 2'b10) ? opa32 :
(sel[1:0] == 2'b01) ? {{16{opa32[15]}},opa32[15:0]}:
{{24{opa32[7]}},opa32[ 7:0]};
assign sopb32 = (sel[1:0] == 2'b10) ? opb32 :
(sel[1:0] == 2'b01) ? {{16{opb32[15]}},opb32[15:0]}:
{{24{opb32[7]}},opb32[ 7:0]};
assign uopa32 = (sel[1:0] == 2'b10) ? opa32 :
(sel[1:0] == 2'b01) ? {16'b0,opa32[15:0]}:
{24'b0,opa32[ 7:0]};
assign uopb32 = (sel[1:0] == 2'b10) ? opb32 :
(sel[1:0] == 2'b01) ? {16'b0,opb32[15:0]}:
{24'b0,opb32[ 7:0]};
// absolute value if needed
assign aopa32 = ({sel[2],sopa32[31]} == 2'b11 ) ? ( ~sopa32 + 1 ) : uopa32;
assign aopb32 = ({sel[2],sopb32[31]} == 2'b11 ) ? ( ~sopb32 + 1 ) : uopb32;
// stage 1
always @(posedge clk)
begin
pipea <= aopa32;
pipeb <= aopb32;
pipe1 <= {sel[2],sopa32[31],sopb32[31]};
end
// stage 2
always @(posedge clk)
begin
unsign_st1a <= pipea * pipeb[15:0];
unsign_st1b <= pipea * pipeb[31:16];
pipe2 <= pipe1;
end
// output
assign out_abs = {16'b0,unsign_st1a} + {unsign_st1b,16'b0};
assign res64 = (( pipe2 == 3'b110 ) || ( pipe2 == 3'b101 )) ? ~out_abs + 1 : out_abs;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; const long long inf = 1LL << 60; const int N = 200010; struct Edge { int to, next; } e1[N], e2[N]; int list1[N], list2[N], d1, d2; priority_queue<pair<int, int> > Q; queue<int> S; bool vis[N]; vector<int> v[N]; void add(int x, int y, int *list, int &d, Edge *e) { e[d].to = y, e[d].next = list[x], list[x] = d++; } int n, m, k; int ans[N], Min[N], din[N], dout[N], d[N]; int read() { int w(0), f(0); char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) f = 1, c = getchar(); while (c >= 0 && c <= 9 ) w = w * 10 + c - 0 , c = getchar(); return f ? -w : w; } void Imps() { puts( -1 ); exit(0); } void Delete(int x) { int y; for (int i = list2[x]; i >= 0; i = e2[i].next) { y = e2[i].to; d[y]--; if (!d[y] && !ans[y]) Q.push(make_pair(Min[y], y)); } } int main() { n = read(), m = read(), k = read(); memset(list1, -1, 4 * (n + 1)), memset(list2, -1, 4 * (n + 1)); for (int i = 1; i <= n; ++i) ans[i] = read(), vis[ans[i]] = 1, v[ans[i]].push_back(i); int x, y; pair<int, int> tmp; for (int i = 1; i <= m; ++i) { x = read(), y = read(); add(y, x, list1, d1, e1); add(x, y, list2, d2, e2); din[x]++, dout[y]++; } for (int i = 1; i <= n; ++i) { d[i] = din[i]; if (!d[i]) S.push(i); } while (!S.empty()) { x = S.front(), S.pop(); if (ans[x]) { if (ans[x] < Min[x]) Imps(); else Min[x] = ans[x]; } else if (!Min[x]) Min[x] = 1; for (int i = list1[x]; i >= 0; i = e1[i].next) { y = e1[i].to; Min[y] = max(Min[y], Min[x] + 1); d[y]--; if (!d[y]) S.push(y); } } for (int i = 1; i <= n; ++i) { d[i] = dout[i]; if (!d[i] && !ans[i]) Q.push(make_pair(Min[i], i)); } for (int i = k; i >= 1; --i) { for (int j = 0; j < v[i].size(); ++j) { x = v[i][j]; Delete(x); } while (!Q.empty()) { tmp = Q.top(); if (tmp.first > i) Imps(); else if (tmp.first == i) ans[tmp.second] = i, vis[i] = 1, Q.pop(), Delete(tmp.second); else break; } if (!vis[i]) { if (!Q.empty()) { tmp = Q.top(); ans[tmp.second] = i, vis[i] = 1, Q.pop(), Delete(tmp.second); } else Imps(); } } for (x = 1; x <= n; ++x) for (int i = list1[x]; i >= 0; i = e1[i].next) if (ans[x] >= ans[e1[i].to]) Imps(); for (int i = 1; i <= n; ++i) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, numero; cin >> n; if (n < 10) cout << n; else { n -= 9; if (n < 181) { if (n % 2 == 0) { n /= 2; n -= 1; n %= 10; cout << n; } else { n = (n + 1) / 2; cout << ((n - 1) / 10) + 1; } } else { n -= 180; numero = ((n - 1) / 3) + 1; numero += 99; n = n % 3; switch (n) { case 0: cout << numero % 10; break; case 1: cout << numero / 100; break; default: cout << (numero % 100) / 10; break; } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_TB_V
`define SKY130_FD_SC_LP__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; const int MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; int N, M; int a[110]; int b[110]; int sum[110]; int num[110][30]; char ans[110]; void solve(int n) { string temp; memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); memset(sum, 0, sizeof(sum)); cout << ? 1 << n << endl; cout.flush(); for (int i = n * (n + 1) / 2; i > 0; i--) { cin >> temp; for (int j = 0; j < temp.size(); j++) { a[temp.size()] += temp[j] - a ; } } cout << ? 1 << n - 1 << endl; cout.flush(); for (int i = n * (n - 1) / 2; i > 0; i--) { cin >> temp; for (int j = 0; j < temp.size(); j++) { b[temp.size()] += temp[j] - a ; } } for (int i = 1; i <= n; i++) { sum[i] = a[i] - b[i]; ans[n - i] = sum[i] - sum[i - 1] + a ; } } int main() { string temp; int limit; int now; while (~scanf( %d , &N)) { if (N <= 3) { char c; for (int i = 1; i <= N; i++) { cout << ? << i << << i << endl; cout.flush(); cin >> c; ans[i - 1] = c; } } else { memset(num, 0, sizeof(num)); limit = (N + 1) >> 1; solve(limit); cout << ? << 1 << << N << endl; cout.flush(); for (int i = N * (N + 1) / 2; i > 0; i--) { cin >> temp; for (int j = 0; j < temp.size(); j++) { num[temp.size()][temp[j] - a ]++; } } for (int i = N; i >= limit; i--) { for (int j = 1; j <= min(N - i + 1, limit); j++) { now = j; num[i][ans[j - 1] - a ] -= now; } for (int j = now + 1; j <= limit; j++) { num[i][ans[j - 1] - a ] -= now; } } for (int i = N; i > limit; i--) { for (int j = 0; j < 30; j++) { if (num[i][j] / (N - i + 1) * (N - i + 2) != num[i - 1][j]) { ans[i - 1] = j + a ; for (int k = i - 1; k >= limit; k--) { num[k][j] -= N - i + 1; } break; } } } } ans[N] = 0 ; printf( ! %s n , ans); cout.flush(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const long long linf = (long long)1e18; const double eps = (double)1e-8; const int mod = (int)1e9 + 7; const int maxn = (int)1e5 + 5; const int MX = (int)1e5; const int PRIME = 31; string s, t; int n, m, first; long long hs[maxn], ht[maxn], st[maxn]; int d[maxn][33]; int subs(int l, int r) { return 1ll * (hs[r] - hs[l - 1] + mod) % mod * st[max(n, m) - r] % mod; } int subt(int l, int r) { return 1ll * (ht[r] - ht[l - 1] + mod) % mod * st[max(n, m) - r] % mod; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; cin >> s; s = _ + s; cin >> m; cin >> t; t = _ + t; cin >> first; st[0] = 1; for (int i = (1); i <= (int)(MX); ++i) { st[i] = 1ll * st[i - 1] * PRIME % mod; } hs[0] = 0; for (int i = (1); i <= (int)(n); ++i) { hs[i] = (hs[i - 1] + st[i - 1] * (s[i] - a + 1)) % mod; } ht[0] = 0; for (int i = (1); i <= (int)(m); ++i) { ht[i] = (ht[i - 1] + st[i - 1] * (t[i] - a + 1)) % mod; } memset((d), 0, sizeof(d)); for (int i = (0); i <= (int)(n - 1); ++i) { for (int j = (0); j <= (int)(first); ++j) { d[i + 1][j] = max(d[i + 1][j], d[i][j]); if (j == first) continue; int l = 0; int r = min(n - i, m - d[i][j]); while (l < r) { int mid = (l + r + 1) / 2; if (subs(i + 1, i + mid) == subt(d[i][j] + 1, d[i][j] + mid)) l = mid; else r = mid - 1; } d[i + l][j + 1] = max(d[i + l][j + 1], d[i][j] + l); } } for (int i = (1); i <= (int)(first); ++i) { if (d[n][i] == m) { cout << YES << n ; return 0; } } cout << NO << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_4_V
`define SKY130_FD_SC_LP__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:12:01 05/13/2015
// Design Name:
// Module Name: Memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Memory(
input clk,
input[14:0] adrA,
input[14:0] adrB,
input we,
input[31:0] data,
input lh, //when lh==0, big-endian. when lh==1, sign extension.
input sh,
output[31:0] outA,
output[15:0] outB
);
wire weA,weB;
wire[13:0] addrAA,addrAB,addrBA,addrBB;
wire[15:0] doutAA,doutAB,doutBA,doutBB;
wire[15:0] dinA,dinB;
assign weA = we & ( ~sh | ~adrA[0] );
assign weB = we & ( ~sh | adrA[0] );
assign addrAA = adrA[0] ? (adrA[14:1]+1) : adrA[14:1];
assign addrBA = adrA[14:1];
assign dinA = sh ? data[15:0] : (adrA[0]? data[15:0] : data[31:16]);
assign dinB = sh ? data[15:0] : (adrA[0]? data[31:16] : data[15:0]);
assign outA = lh ? (adrA[0]? { {16{doutBA[15]}} ,doutBA} : { {16{doutAA[15]}}, doutAA}) :
(adrA[0]? {doutBA,doutAA} : {doutAA,doutBA});
assign addrAB = adrB[14:1];
assign addrBB = adrB[14:1];
assign outB = adrB[0]? doutBB : doutAB;
BankA banka (
.clka(clk),
.wea(weA), // Bus [0 : 0]
.addra(addrAA), // Bus [13 : 0]
.dina(dinA), // Bus [15 : 0]
.douta(doutAA), // Bus [15 : 0]
.clkb(clk),
.web(1'b0), // Bus [0 : 0]
.addrb(addrAB), // Bus [13 : 0]
.dinb(16'b0), // Bus [15 : 0]
.doutb(doutAB)); // Bus [15 : 0]
BankB bankb (
.clka(clk),
.wea(weB), // Bus [0 : 0]
.addra(addrBA), // Bus [13 : 0]
.dina(dinB), // Bus [15 : 0]
.douta(doutBA), // Bus [15 : 0]
.clkb(clk),
.web(1'b0), // Bus [0 : 0]
.addrb(addrBB), // Bus [13 : 0]
.dinb(16'b0), // Bus [15 : 0]
.doutb(doutBB)); // Bus [15 : 0]
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n, s1 = 0, s2 = 0; scanf( %d , &n); int a[100] = {0}; for (int i = 0; i < n; i++) { scanf( %d , a + i); if (a[i] % 2) s1++; else s2++; } if (s1 && s2) printf( NO n ); else printf( YES n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; if (n & 1) { cout << 0; } else { int res = n / 4; if (n % 4 == 0) { res--; } cout << res; } return 0; } |
module rd_port_9_to_1 (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
port8_rd_en,
port8_rd_addr,
rd_addr
);
parameter WIDTH = 1;
input port0_rd_en;
input [WIDTH - 1:0] port0_rd_addr;
input port1_rd_en;
input [WIDTH - 1:0] port1_rd_addr;
input port2_rd_en;
input [WIDTH - 1:0] port2_rd_addr;
input port3_rd_en;
input [WIDTH - 1:0] port3_rd_addr;
input port4_rd_en;
input [WIDTH - 1:0] port4_rd_addr;
input port5_rd_en;
input [WIDTH - 1:0] port5_rd_addr;
input port6_rd_en;
input [WIDTH - 1:0] port6_rd_addr;
input port7_rd_en;
input [WIDTH - 1:0] port7_rd_addr;
input port8_rd_en;
input [WIDTH - 1:0] port8_rd_addr;
output [WIDTH - 1:0] rd_addr;
reg [WIDTH - 1:0] rd_addr;
always @ (
port0_rd_en or port1_rd_en or port2_rd_en or port3_rd_en or port4_rd_en or
port5_rd_en or port6_rd_en or port7_rd_en or port8_rd_en or
port0_rd_addr or port1_rd_addr or port2_rd_addr or port3_rd_addr or
port4_rd_addr or port5_rd_addr or port6_rd_addr or port7_rd_addr or port8_rd_addr)
begin
casex({port8_rd_en, port7_rd_en, port6_rd_en, port5_rd_en, port4_rd_en,
port3_rd_en, port2_rd_en, port1_rd_en, port0_rd_en})
9'b000000001: rd_addr <= port0_rd_addr;
9'b000000010: rd_addr <= port1_rd_addr;
9'b000000100: rd_addr <= port2_rd_addr;
9'b000001000: rd_addr <= port3_rd_addr;
9'b000010000: rd_addr <= port4_rd_addr;
9'b000100000: rd_addr <= port5_rd_addr;
9'b001000000: rd_addr <= port6_rd_addr;
9'b010000000: rd_addr <= port7_rd_addr;
9'b100000000: rd_addr <= port8_rd_addr;
default: rd_addr <= 6'bxxxxxx;
endcase
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g_gmii_fifo
*/
module test_eth_mac_1g_gmii_fifo;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg gtx_clk = 0;
reg gtx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg gmii_rx_clk = 0;
reg [7:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg mii_tx_clk = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire gmii_tx_clk;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
wire [1:0] speed;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
gtx_clk,
gtx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
gmii_rx_clk,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
mii_tx_clk,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_tx_clk,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame,
speed
);
// dump file
$dumpfile("test_eth_mac_1g_gmii_fifo.lxt");
$dumpvars(0, test_eth_mac_1g_gmii_fifo);
end
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.gtx_clk(gtx_clk),
.gtx_rst(gtx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(gmii_rx_clk),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_tx_clk(gmii_tx_clk),
.mii_tx_clk(mii_tx_clk),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.speed(speed),
.ifg_delay(ifg_delay)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long k = 2; struct node { vector<node*> to; node() { to.resize(k, 0); } long long cnt = 0; }; node* root = new node(); inline bool getbit(long long a, long long pos) { return a & (1 << pos); } void addstring(long long b) { vector<long long> a; for (long long i = 0; i < 30; ++i) { a.push_back(getbit(b, i)); } reverse(a.begin(), a.end()); node* cur = root; for (long long i = 0; i < a.size(); ++i) { long long c = a[i]; if (cur->to[c] == 0) { cur->to[c] = new node(); } cur = cur->to[c]; cur->cnt++; } } long long get(long long b) { vector<long long> a; long long ans = 0; for (long long i = 0; i < 30; ++i) { a.push_back(getbit(b, i)); } reverse(a.begin(), a.end()); node* cur = root; for (long long i = 0; i < a.size(); ++i) { long long bet = a[i]; if (cur->to[bet] && cur->to[bet]->cnt > 0) { cur = cur->to[bet]; ans += bet * (1 << (29 - i)); cur->cnt--; } else { cur = cur->to[1 - bet]; ans += (1 - bet) * (1 << (29 - i)); cur->cnt--; } } return ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> a(n); vector<long long> b(n); for (long long i = 0; i < n; ++i) { cin >> a[i]; } for (long long i = 0; i < n; ++i) { cin >> b[i]; addstring(b[i]); } for (long long i = 0; i < n; ++i) { cout << (get(a[i]) ^ a[i]) << ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INVLP_BEHAVIORAL_V
/**
* invlp: Low Power Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__invlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_BEHAVIORAL_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Internal DMA Control and status register file for PCIE-DDR2 DMA
// design. This register file should only be used for dma transfers
// up to 4KB in size.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module internal_dma_ctrl
(
input clk,
input rst,
//interface from dma_ctrl_status_reg file;
//these inputs could also be directly driven from the host system if desired
//in which case the dma_ctrl_status_reg_file block should be removed from the
//design
input [31:0] reg_data_in,
input [6:0] reg_wr_addr,
input [6:0] reg_rd_addr,
input reg_wren,
output reg [31:0] reg_data_out, //reg_data_out is never used
//DMA parameter control outputs to TX and RX engines
output [63:0] dmaras, //Read address source (from host memory)
output reg [31:0] dmarad, //Read address destination (to backend memory)
output reg [31:0] dmarxs, //Read transfer size in bytes
output rd_dma_start, //read dma start control signal
input rd_dma_done, //read dma done signal from RX engine
//Performance counts from performance counter module
//Not used in this module because the copies in dma_ctrl_status_reg_file
//are used instead
input [31:0] dma_wr_count,
input [31:0] dma_rd_count
);
reg [31:0] dmaras_l, dmaras_u;
reg [31:0] dmacst;
//concatanate to form the 64 bit outputs
assign dmaras[63:0] = {dmaras_u,dmaras_l};
////assign wr_dma_start = dmacst[0];
assign rd_dma_start = dmacst[2];
//block for writing into the regfile
//--when reg_wren is asserted, reg_data_in will be written to one of the
//registers as chosen by reg_wr_addr selection signal
always@(posedge clk or posedge rst) begin
if(rst) begin
dmaras_l <= 0;
dmaras_u <= 0;
dmarad <= 0;
dmarxs <= 0;
end else begin
if(reg_wren) begin
case(reg_wr_addr)
7'b000_1100: dmaras_l <= reg_data_in; //0x0C
7'b001_0000: dmaras_u <= reg_data_in; //0x10
7'b001_0100: dmarad <= reg_data_in; //0x14
7'b001_1100: dmarxs <= reg_data_in; //0x1C
default: begin
dmaras_l <= dmaras_l;
dmaras_u <= dmaras_u;
dmarad <= dmarad;
dmarxs <= dmarxs;
end
endcase
end
end
end
//use a separate always block for dmacst[3:2] for clarity
//dmacst[2] == rd_dma_start; host sets this bit to start a dma transfer
// it is automatically cleared when the
// dma transfer completes
//dmacst[3] == rd_dma_done; asserted when the dma transfer is finished
// this bit can be polled by the host or it could
// be used to drive hardware block to generate
// an interrupt
// this bit must be cleared by the host by
// writing a "1" to it.
always@(posedge clk) begin
if(rst) begin
dmacst[3:2] <= 2'b00;
end else begin
if(rd_dma_done) begin //rd_dma_done from RX Engine
dmacst[2] <= 1'b0;
dmacst[3] <= 1'b1;
end else if(reg_wren) begin
case(reg_wr_addr)
7'b010_1000: begin //0x28
/// Jiansong:
//take care of the unused bits in this always
//block
dmacst[31:4] <= reg_data_in[31:4];
dmacst[1:0] <= reg_data_in[1:0];
//set the start bit if the host writes a 1
//the host cannot clear this bit
if(reg_data_in[2])
dmacst[2] <= 1'b1;
else
dmacst[2] <= dmacst[2];
//clear the done bit if the host writes a 1
//the host cannot set this bit
if(reg_data_in[3])
dmacst[3] <= 1'b0;
else
dmacst[3] <= dmacst[3];
end
default: begin
dmacst[3:2] <= dmacst[3:2];
end
endcase
end
end
end
// output register for cpu
// this is a read of the reg_file
// the case stmt is a mux which selects which reg location
// makes it to the output data bus
// Not used in this design
always@(posedge clk or posedge rst )
begin
if(rst)
begin
reg_data_out <= 0;
end
else
begin
case(reg_rd_addr[6:0])
7'b000_1100: reg_data_out <= dmaras_l;
7'b001_0000: reg_data_out <= dmaras_u;
7'b001_0100: reg_data_out <= dmarad;
7'b001_1100: reg_data_out <= dmarxs;
7'b010_1000: reg_data_out <= dmacst;
7'b011_0000: reg_data_out <= dma_wr_count;
7'b011_0100: reg_data_out <= dma_rd_count;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 102; int ar[maxn], ans; int main() { int n; cin >> n; n = 2 * n; for (int i = 1; i <= n; i++) cin >> ar[i]; for (int i = 1; i <= n; i++) if (ar[i - 1] != ar[i] && ar[i + 1] != ar[i]) { int j = i + 1; while (ar[j] != ar[i] && j <= n) j++; for (int o = j; o > i + 1; o--) swap(ar[o], ar[o - 1]), ans++; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 101010; int n, ans; int pa[N << 1], ns[N], nt[N], ma[N], pos[N]; vector<pair<int, int> > res; char s[N], sr[N]; void Manacher(char *s, int n, int *pa) { pa[0] = 1; for (int i = 1, j = 0; i < (n << 1) - 1; ++i) { int p = i >> 1, q = i - p, r = ((j + 1) >> 1) + pa[j] - 1; pa[i] = r < q ? 0 : min(r - q + 1, pa[(j << 1) - i]); while (0 <= p - pa[i] && q + pa[i] < n && s[p - pa[i]] == s[q + pa[i]]) pa[i]++; if (q + pa[i] - 1 > r) j = i; } for (int i = (0); i < (n); ++i) pa[i] = pa[i << 1]; } void kmp(char *s, int *ns, char *t, int *nt) { int lens = strlen(s); int lent = strlen(t); nt[0] = -1; for (int i = 0, j = -1; i < lens; ++i) { while (j >= 0 && s[i] != t[j + 1]) j = nt[j]; if (s[i] == t[j + 1]) ++j; ns[i] = j; if (j + 1 == lent) j = nt[j]; } } int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); cin >> s; n = strlen(s); Manacher(s, n, pa); for (int i = (0); i < (n); ++i) sr[i] = s[n - 1 - i]; sr[n] = 0 ; kmp(sr + 1, nt + 1, sr, nt); kmp(s, ns, sr, nt); for (int i = (0); i < (n); ++i) if (~ns[i]) ++ns[i]; ma[0] = ns[0]; pos[0] = 0; for (int i = (1); i < (n); ++i) { ma[i] = ma[i - 1]; pos[i] = pos[i - 1]; if (ma[i] < ns[i]) { ma[i] = ns[i]; pos[i] = i; } } for (int i = (0); i < (n); ++i) { int k = i - pa[i]; int t = max(0, min(k < 0 ? 0 : ma[k], n - i - pa[i])); int c = pa[i] * 2 - 1 + t * 2; if (ans < c) { ans = c; res.clear(); res.push_back(make_pair(i - pa[i] + 1, pa[i] * 2 - 1)); if (t) { res.push_back(make_pair(n - t, t)); int o = pos[k] - 2 * ns[pos[k]] + t + 1; res.push_back(make_pair(o, t)); } } } sort(res.begin(), res.end()); cout << (int)res.size() << n ; for (auto u : res) cout << u.first + 1 << << u.second << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; pair<int, int> s[300100]; pair<int, int> r[300100]; int res[300300]; int s1[300300]; int r1[300300]; map<pair<int, int>, int> rep; int dp[94040]; void add(int a, int b, int x, int l = 1, int h = 1e4 + 2, int p = 1) { if (a == l && b == h) { dp[p] += x; return; } int m = (l + h) / 2; if (b <= m) { add(a, b, x, l, m, 2 * p); } else if (a > m) { add(a, b, x, m + 1, h, 2 * p + 1); } else { add(m + 1, b, x, m + 1, h, 2 * p + 1); add(a, m, x, l, m, 2 * p); } dp[p] = dp[2 * p] + dp[2 * p + 1]; } int cal(int a, int b, int x = 0, int l = 1, int h = 1e4 + 2, int p = 1) { if (a == l && b == h) { return dp[p]; } int m = (l + h) / 2; if (b <= m) { return cal(a, b, x, l, m, 2 * p); } else if (a > m) { return cal(a, b, x, m + 1, h, 2 * p + 1); } else { return cal(m + 1, b, x, m + 1, h, 2 * p + 1) + cal(a, m, x, l, m, 2 * p); } } map<pair<int, int>, int> ch; int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &s[i].first); scanf( %d , &r[i].first); r[i].second = i; s[i].second = i; rep[make_pair(s[i].first, r[i].first)]++; s1[i] = s[i].first; r1[i] = r[i].first; } sort(s + 1, s + n + 1); for (int i = 1; i <= n;) { int j; for (j = i; j <= n; j++) { if (s[i].first != s[j].first) break; int in = s[j].second; res[in] += i - 1; if (r[in].first - 1 >= 1) res[in] -= cal(1, r[in].first - 1); } for (int k = i; k < j; k++) { int in = s[k].second; add(r[in].first, r[in].first, 1); } i = j; } sort(r + 1, r + n + 1); for (int i = 1; i <= n;) { int j; for (j = i; j <= n; j++) { if (r[i].first != r[j].first) break; int in = r[j].second; res[in] += i - 1; } i = j; } vector<pair<long long, long long> > v; for (int i = 1; i <= n; i++) { if (res[i] == n - rep[make_pair(s1[i], r1[i])] && !ch.count(make_pair(s1[i], r1[i]))) { ch[make_pair(s1[i], r1[i])] = 1; v.push_back(make_pair(s1[i], r1[i])); } } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); ch[v[0]]++; if (v.size() > 1) ch[v.back()]++; int m; double t; for (int i = 1; i < v.size() - 1; i++) { double bef = -1e18; int l = i + 1, r = v.size() - 1; while (l <= r) { m = (l + r) / 2; t = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); if (l == r) { bef = max(bef, t); break; } m++; double t1 = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); if (t >= t1) { r = m - 2; bef = max(bef, t); } else { l = m + 1; bef = max(bef, t1); } } m = i + 1; t = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); bef = max(bef, t); m = v.size() - 1; t = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); bef = max(bef, t); double aft = 1e18; l = 0, r = i - 1; while (l <= r) { int m = (l + r) / 2; t = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); if (l == r) { aft = min(aft, t); break; } m++; double t1 = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); if (t <= t1) { r = m - 2; aft = min(aft, t); } else { l = m + 1; aft = min(aft, t1); } } m = 0; t = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); aft = min(aft, t); m = i - 1; t = 1.0 * (1.0 * v[m].second - v[i].second) / (v[m].second * v[i].second) / (1.0 * v[i].first - v[m].first) * (1.0 * v[i].first * v[m].first); aft = min(aft, t); if (aft >= bef) { ch[v[i]]++; } } for (int i = 1; i <= n; i++) { if (ch[make_pair(s1[i], r1[i])] == 2) printf( %d , i); } cout << endl; return 0; } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module scales video streams on the DE boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_scaler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Frame's Channel Width
parameter DW = 7; // Frame's Data Width
parameter EW = 0; // Frame's Empty Width
parameter WIW = 9; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 640;
parameter WIDTH_DROP_MASK = 4'b0000;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 9; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 640; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [CW: 0] stream_out_channel;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [CW: 0] internal_channel;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_multiply_height Multiply_Height (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// Bi-Directional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_channel (stream_out_channel),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Multiply_Height.DW = DW,
Multiply_Height.WW = MH_WW,
Multiply_Height.WIDTH = MH_WIDTH_IN,
Multiply_Height.MCW = MH_CW;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int c[10000007]; vector<pair<int, int> > x; int temp; vector<int> vt; int main() { scanf( %d %d %d , &m, &k, &n); for (int i = 0; i < m; i++) { scanf( %d , &temp); c[temp]++; if (c[temp] > n) { printf( -1 n ); return 0; } } for (int i = 0; i < k; i++) { scanf( %d , &temp); x.push_back(make_pair(temp, i)); } sort(x.begin(), x.end()); int cur = 0; int remain = 0; for (int i = 0; i < k; i++) { while (cur <= x[i].first) { remain += n - c[cur]; cur++; } if (remain) { remain--; vt.push_back(x[i].second); } } printf( %d n , vt.size()); for (int i = 0; i < vt.size(); i++) printf( %d , vt[i] + 1); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_cfg.v
// Version : 1.11
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_cfg (
cfg_do,
cfg_di,
cfg_byte_en_n,
cfg_dwaddr,
cfg_wr_en_n,
cfg_rd_en_n,
cfg_rd_wr_done_n,
cfg_err_cor_n,
cfg_err_ur_n,
cfg_err_ecrc_n,
cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n,
cfg_err_posted_n,
cfg_err_tlp_cpl_header,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_turnoff_ok_n,
cfg_to_turnoff_n,
cfg_bus_number,
cfg_device_number,
cfg_function_number,
cfg_status,
cfg_command,
cfg_dstatus,
cfg_dcommand,
cfg_lstatus,
cfg_lcommand,
cfg_pcie_link_state_n,
cfg_trn_pending_n,
cfg_pm_wake_n,
trn_clk,
trn_reset_n
);
input [(32 - 1):0] cfg_do;
output [(32 - 1):0] cfg_di;
output [(32/8 - 1):0] cfg_byte_en_n;
output [(10 - 1):0] cfg_dwaddr;
output cfg_wr_en_n;
output cfg_rd_en_n;
input cfg_rd_wr_done_n;
output cfg_err_cor_n;
output cfg_err_ur_n;
output cfg_err_ecrc_n;
output cfg_err_cpl_timeout_n;
output cfg_err_cpl_abort_n;
output cfg_err_cpl_unexpect_n;
output cfg_err_posted_n;
output [(48 - 1):0] cfg_err_tlp_cpl_header;
output cfg_interrupt_n;
input cfg_interrupt_rdy_n;
output cfg_turnoff_ok_n;
input cfg_to_turnoff_n;
output cfg_pm_wake_n;
input [(8 - 1):0] cfg_bus_number;
input [(5 - 1):0] cfg_device_number;
input [(3 - 1):0] cfg_function_number;
input [(16 - 1):0] cfg_status;
input [(16- 1):0] cfg_command;
input [(16- 1):0] cfg_dstatus;
input [(16 - 1):0] cfg_dcommand;
input [(16 - 1):0] cfg_lstatus;
input [(16 - 1):0] cfg_lcommand;
input [(3 - 1):0] cfg_pcie_link_state_n;
output cfg_trn_pending_n;
input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
reg [(32 - 1):0] cfg_di;
reg [(32/8 - 1):0] cfg_byte_en_n;
reg [(10 - 1):0] cfg_dwaddr;
reg cfg_wr_en_n;
reg cfg_rd_en_n;
reg cfg_err_cor_n;
reg cfg_err_ecrc_n;
reg cfg_err_ur_n;
reg cfg_err_cpl_timeout_n;
reg cfg_err_cpl_abort_n;
reg cfg_err_cpl_unexpect_n;
reg cfg_err_posted_n;
reg [(48 - 1):0] cfg_err_tlp_cpl_header;
reg cfg_interrupt_n;
reg cfg_turnoff_ok_n;
reg cfg_pm_wake_n;
reg cfg_trn_pending_n;
initial begin
cfg_err_cor_n <= 1'b1;
cfg_err_ur_n <= 1'b1;
cfg_err_ecrc_n <= 1'b1;
cfg_err_cpl_timeout_n <= 1'b1;
cfg_err_cpl_abort_n <= 1'b1;
cfg_err_cpl_unexpect_n <= 1'b1;
cfg_err_posted_n <= 1'b0;
cfg_interrupt_n <= 1'b1;
cfg_turnoff_ok_n <= 1'b1;
cfg_dwaddr <= 0;
cfg_err_tlp_cpl_header <= 0;
cfg_di <= 0;
cfg_byte_en_n <= 4'hf;
cfg_wr_en_n <= 1;
cfg_rd_en_n <= 1;
cfg_pm_wake_n <= 1;
cfg_trn_pending_n <= 1'b0;
end
/************************************************************
Task : TSK_READ_CFG_DW
Description : Read Configuration Space DW
*************************************************************/
task TSK_READ_CFG_DW;
input [31:0] addr_;
begin
if (!trn_reset_n) begin
$display("[%t] : trn_reset_n is asserted", $realtime);
$finish(1);
end
wait ( cfg_rd_wr_done_n == 1'b1)
@(posedge trn_clk);
cfg_dwaddr <= #(Tcq) addr_;
cfg_wr_en_n <= #(Tcq) 1'b1;
cfg_rd_en_n <= #(Tcq) 1'b0;
$display("[%t] : Reading Cfg Addr [0x%h]", $realtime, addr_);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\n[%t] : Local Configuration Read Access :",
$realtime);
@(posedge trn_clk);
#(Tcq);
wait ( cfg_rd_wr_done_n == 1'b0)
#(Tcq);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\t\t\tCfg Addr [0x%h] -> Data [0x%h]\n",
{addr_,2'b00}, cfg_do);
cfg_rd_en_n <= #(Tcq) 1'b1;
end
endtask // TSK_READ_CFG_DW;
/************************************************************
Task : TSK_WRITE_CFG_DW
Description : Write Configuration Space DW
*************************************************************/
task TSK_WRITE_CFG_DW;
input [31:0] addr_;
input [31:0] data_;
input [3:0] ben_;
begin
if (!trn_reset_n) begin
$display("[%t] : trn_reset_n is asserted", $realtime);
$finish(1);
end
wait ( cfg_rd_wr_done_n == 1'b1)
@(posedge trn_clk);
cfg_dwaddr <= #(Tcq) addr_;
cfg_di <= #(Tcq) data_;
cfg_byte_en_n <= #(Tcq) ben_;
cfg_wr_en_n <= #(Tcq) 1'b0;
cfg_rd_en_n <= #(Tcq) 1'b1;
$display("[%t] : Writing Cfg Addr [0x%h]", $realtime, addr_);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\n[%t] : Local Configuration Write Access :",
$realtime);
@(posedge trn_clk);
#(Tcq);
wait ( cfg_rd_wr_done_n == 1'b0)
#(Tcq);
cfg_wr_en_n <= #(Tcq) 1'b1;
end
endtask // TSK_WRITE_CFG_DW;
endmodule // pci_exp_usrapp_cfg
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// MMCM_OR_BUFR_N with DRP and device specific
`timescale 1ns/100ps
module ad_mmcm_drp #(
parameter MMCM_DEVICE_TYPE = 0,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_CLKIN2_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK0_PHASE = 0.000,
parameter MMCM_CLK1_DIV = 6,
parameter MMCM_CLK1_PHASE = 0.000,
parameter MMCM_CLK2_DIV = 2.000,
parameter MMCM_CLK2_PHASE = 0.000) (
// clocks
input clk,
input clk2,
input clk_sel,
input mmcm_rst,
output mmcm_clk_0,
output mmcm_clk_1,
output mmcm_clk_2,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [15:0] up_drp_wdata,
output reg [15:0] up_drp_rdata,
output reg up_drp_ready,
output reg up_drp_locked);
localparam MMCM_DEVICE_7SERIES = 0;
localparam MMCM_DEVICE_ULTRASCALE = 2;
// internal registers
reg up_drp_locked_m1 = 'd0;
// internal signals
wire bufg_fb_clk_s;
wire mmcm_fb_clk_s;
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
wire mmcm_clk_2_s;
wire mmcm_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
// instantiations
generate
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
end else if (MMCM_DEVICE_TYPE == MMCM_DEVICE_ULTRASCALE) begin
MMCME3_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("AUTO"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcme3 (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.CDDCREQ (1'b0),
.CDDCDONE (),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; bool func(pair<int, int> &a, pair<int, int> &b) { return a.first < b.first; } int main() { int n, q; vector<pair<int, int>> arr; int input1, input2; int i, j; int level[5001] = { 0, }; priority_queue<int, vector<int>, greater<int>> exit; int curlev = 1; int cur, prev = 0; int acc1[5001], acc2[5001]; pair<int, int> interv1, interv2, temp; int over1, over2; int last = 0, sum; int cand; int lmax = 0; scanf( %d %d , &n, &q); for (i = 0; i < q; i++) { scanf( %d %d , &input1, &input2); arr.push_back(pair<int, int>(input1, input2)); for (j = input1; j <= input2; j++) { level[j]++; } } sort(arr.begin(), arr.end(), func); sum = n; for (i = 0; i < q; i++) { if (arr[i].first > prev + 1) { sum -= arr[i].first - (prev + 1); } if (arr[i].second > prev) { prev = arr[i].second; } } sum -= n - prev; acc1[0] = acc2[0] = 0; for (i = 1; i <= n; i++) { acc1[i] = acc1[i - 1] + (level[i] == 1); acc2[i] = acc2[i - 1] + (level[i] == 2); } for (i = 0; i < q - 1; i++) { for (j = i + 1; j < q; j++) { interv1 = arr[i]; interv2 = arr[j]; over1 = 1; over2 = 0; if (interv2.first <= interv1.second) { over1 = interv2.first; if (interv2.second < interv1.second) { over2 = interv2.second; } else { over2 = interv1.second; } } cand = sum - ((acc1[interv1.second] - acc1[interv1.first - 1]) + (acc1[interv2.second] - acc1[interv2.first - 1])) - (acc2[over2] - acc2[over1 - 1]); if (cand > lmax) { lmax = cand; } } } printf( %d n , lmax); return 0; } |
// soft_tbm.v
`timescale 1 ns / 1 ps
module soft_tbm
(
input clk,
input sync,
input reset,
input [4:0]trg_in_tbm,
input [4:0]trg_in_ctr,
input [3:0]trg_pos,
output tin,
input tout,
output deser_ena,
output ctr,
output daq_write,
output reg [15:0]daq_data,
input [15:0]token_timeout,
input enable_tout_delay
);
wire ro_enable; // a readout can be started
wire trg_pass; // trigger sent to ROC/TBM
wire queue_read;
wire queue_clear;
wire queue_clear_token;
wire queue_empty;
wire queue_full;
wire [3:0]queue_size;
wire queue_tok;
wire [7:0]queue_trigger_counter;
wire [3:0]queue_trg_pos;
wire [5:0]queue_flags;
wire tout_int;
wire tout_missing;
wire syn; // sync event
wire trg; // trigger event
wire rsr; // ROC reset event
wire rst; // TBM reset event
reg set_rsr;
wire rsr_int = rsr || set_rsr;
assign queue_clear = rst;
assign queue_clear_token = rsr_int;
assign trg_pass = trg && !queue_full;
// === tout delay for ADC ===========================================
reg [15:0]tout_delay;
always @(posedge clk or posedge reset)
begin
if (reset) tout_delay <= 0;
else if (sync) tout_delay <= {tout_delay[14:0], tout};
end
assign tout_int = enable_tout_delay ? tout_delay[15] : tout;
// === receive and decode events ====================================
assign syn = trg_in_tbm[0];
assign trg = trg_in_tbm[1];
assign rsr = trg_in_tbm[2];
assign rst = trg_in_tbm[3];
assign cal = trg_in_tbm[4];
wire trg_dir = trg_in_ctr[1];
wire rsr_dir = trg_in_ctr[2];
wire rst_dir = trg_in_ctr[3];
wire cal_dir = trg_in_ctr[4];
/* commands
* cal
send cal to ROC
set(flag_cal)
* syn
clear(trigger_counter)
set(flag_sync)
* rsr
queue_clear_token
reset ROC
set flag_resr
if (read_in_progress)
{
stop running readout
add trailer
}
* rst
queue_clear
reset ROC
set flag_resr
set flag_rest
if (read_in_progress)
{
stop running readout
}
* trg
queue_write
if (!queue_full)
{
send ROC trigger
}
else set flag_stkf
*/
// === Send Event to ROC/MODULE (CTR Generator) =====================
ctr_encoder ctr_enc
(
.clk(clk),
.sync(sync),
.reset(reset),
.cal(cal || cal_dir),
.trg(trg_pass || trg_dir),
.res_roc(rsr_int || rst || rsr_dir),
.res_tbm(rst || rst_dir),
.res_req(1'b0),
.nmr_req(1'b0),
.trg_veto(1'b0),
.res_veto(1'b0),
.running(),
.ctr_out(ctr),
.trg_out(),
.res_out()
);
// === Flags ========================================================
reg flag_rest; // TBM reset occured
reg flag_resr; // ROC reset occured
reg flag_cal; // calibrate received
reg flag_sync; // sync signal received
reg flag_stkf; // stack full
reg flag_ares; // auto reset sent
reg flag_pkam; // PKAM reset (not queued)
wire [5:0]flags = {flag_ares, flag_stkf, flag_sync, flag_cal, flag_resr, flag_rest};
always @(posedge clk or posedge reset)
begin
if (reset)
begin
flag_cal <= 0;
flag_sync <= 0;
flag_resr <= 0;
flag_rest <= 0;
flag_stkf <= 0;
flag_ares <= 0;
// flag_pkam <= 0;
end
else if (sync)
begin
if (trg_pass)
begin
flag_cal <= 0;
flag_sync <= 0;
flag_resr <= 0;
flag_rest <= 0;
flag_stkf <= 0;
flag_ares <= 0;
// flag_pkam <= 0;
end
else
if (cal) flag_cal <= 1;
if (syn) flag_sync <= 1;
if (rsr_int || rst) flag_resr <= 1;
if (rst) flag_rest <= 1;
if (trg && queue_full) flag_stkf <= 1;
end
end
// === Trigger Counter ==============================================
reg [7:0]trigger_counter;
always @(posedge clk or posedge reset) begin
if (reset) trigger_counter <= 0;
else if (sync) begin
if (syn) trigger_counter <= 0;
else if (trg_pass) trigger_counter <= trigger_counter + 1;
end
end
// === enables start of a new readout id data in trigger stack
// first readout after buffer empty must be delayed
reg [4:0]ro_delay;
assign ro_enable = ro_delay[4];
always @(posedge clk or posedge reset) begin
if (reset) begin
ro_delay <= 5'd0;
end
else if (sync) begin
if (queue_empty) ro_delay = 5'd12;
else if (!ro_enable) ro_delay = ro_delay - 5'd1;
end
end
// === header/trailer generator =====================================
/*
** header format **
A | 0 | ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0
8 | 0 | 0 0 0 0 pos3 pos2 pos1 pos0
** trailer format **
E | 0 | ntok rest resr 0 sync clt cal stkf
C | 0 | ares pkam 0 0 stk3 stk2 stk1 stk0
*/
reg [16:0]token_timeout_counter;
assign tout_missing = token_timeout_counter[16];
reg [5:0]sm_readout;
localparam SM_IDLE = 6'b00_0000;
localparam SM_HDR1 = 6'b00_0010;
localparam SM_HDR2 = 6'b01_0010;
localparam SM_TOUT = 6'b00_1100;
localparam SM_WAIT = 6'b00_1000;
localparam SM_PCAM1 = 6'b01_1000;
localparam SM_PCAM2 = 6'b01_0000;
localparam SM_TRL0 = 6'b11_1000;
localparam SM_TRL1 = 6'b10_0010;
localparam SM_TRL2 = 6'b00_0011;
localparam SM_TRL3 = 6'b10_0000;
assign queue_read = sm_readout[0];
assign daq_write = sm_readout[1] && sync;
assign tin = sm_readout[2];
assign deser_ena = sm_readout[3];
// trailer delay counter
reg [2:0]trldel;
wire trl_start = trldel[2];
always @(posedge clk or posedge reset)
begin
if (reset) trldel <= 0;
else if (sync)
begin
if (~&sm_readout[5:4]) trldel <= 0;
else if (!trl_start) trldel <= trldel + 3'd1;
end
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
sm_readout <= SM_IDLE;
token_timeout_counter <= 0;
set_rsr <= 0;
flag_pkam <= 0;
end
else if (sync)
begin
case (sm_readout)
SM_IDLE:
if (ro_enable) sm_readout <= SM_HDR1;
SM_HDR1:
sm_readout <= SM_HDR2;
SM_HDR2:
sm_readout <= queue_tok ? SM_TOUT : SM_TRL1;
SM_TOUT:
begin
token_timeout_counter <= {1'b0, token_timeout};
sm_readout <= SM_WAIT;
end
SM_WAIT:
begin
token_timeout_counter <= token_timeout_counter - 17'd1;
if (tout_missing) sm_readout <= SM_PCAM1;
else if (tout_int || flag_resr) sm_readout <= SM_TRL0;
end
SM_PCAM1:
begin
flag_pkam <= 1;
set_rsr <= 1;
sm_readout <= SM_PCAM2;
end
SM_PCAM2:
begin
set_rsr <= 0;
sm_readout <= SM_TRL0;
end
SM_TRL0:
if (trl_start) sm_readout <= SM_TRL1;
SM_TRL1:
sm_readout <= SM_TRL2;
SM_TRL2:
sm_readout <= SM_TRL3;
SM_TRL3:
begin
flag_pkam <= 0;
sm_readout <= SM_IDLE;
end
default: sm_readout <= SM_IDLE;
endcase
end
end
always @(*)
begin
if (sm_readout == SM_HDR1)
daq_data <= {8'ha0, queue_trigger_counter};
else if (sm_readout == SM_HDR2)
daq_data <= {8'h80, 4'b0000, queue_trg_pos};
else if (sm_readout == SM_TRL1)
daq_data <= {8'he0, ~queue_tok, queue_flags[0],
queue_flags[1], 1'b0, queue_flags[3], queue_flags[3], queue_flags[2], queue_flags[4]};
else if (sm_readout == SM_TRL2)
daq_data <= {8'hc0, queue_flags[5], flag_pkam, 2'b00, queue_size};
else daq_data <= 16'd0;
end
soft_tbm_queue #(18) stack
(
.clk(clk),
.sync(sync),
.reset(reset),
.write(trg_pass),
.read(queue_read),
.clear(queue_clear),
.clear_token(queue_clear_token),
.empty(queue_empty),
.full(queue_full),
.size(queue_size),
.din({flags, trg_pos, trigger_counter, 1'b1}),
.dout({queue_flags, queue_trg_pos, queue_trigger_counter, queue_tok})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> ans, adj[200007]; bool vis[200007]; int inputorder[200007], relorder[200007]; bool cmp(int a, int b) { return relorder[a] < relorder[b]; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, x, a, b, i, j; cin >> n; for (i = 0; i < n - 1; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } for (i = 0; i < n; i++) { cin >> inputorder[i]; relorder[inputorder[i]] = i; } for (i = 1; i <= n; i++) sort(adj[i].begin(), adj[i].end(), cmp); queue<int> q; q.push(1); memset(vis, false, sizeof(vis)); while (!(q.empty())) { queue<int> temp; while (!(q.empty())) { int x = q.front(); q.pop(); ans.push_back(x); vis[x] = true; for (j = 0; j < adj[x].size(); j++) if (vis[adj[x][j]] == false) temp.push(adj[x][j]); } q = temp; } for (i = 0; i < n; i++) if (inputorder[i] != ans[i]) { cout << No ; return 0; } cout << Yes ; return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_ADC_Peripheral_To_Phase_Current.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_ADC_Peripheral_To_Phase_Current
// Source Path: controllerHdl/ADC_Peripheral_To_Phase_Current
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_ADC_Peripheral_To_Phase_Current
(
adc_0,
adc_1,
phase_currents_0,
phase_currents_1
);
input signed [17:0] adc_0; // sfix18_En17
input signed [17:0] adc_1; // sfix18_En17
output signed [17:0] phase_currents_0; // sfix18_En15
output signed [17:0] phase_currents_1; // sfix18_En15
wire signed [17:0] adc [0:1]; // sfix18_En17 [2]
wire signed [17:0] ADC_Zero_Offset_out1; // sfix18_En16
wire signed [19:0] Add_v; // sfix20_En17
wire signed [19:0] Add_sub_cast; // sfix20_En17
wire signed [19:0] Add_sub_cast_1; // sfix20_En17
wire signed [19:0] Add_out1 [0:1]; // sfix20_En17 [2]
wire signed [17:0] ADC_Amps_Per_Driver_Unit_out1; // sfix18_En15
wire signed [37:0] Product_mul_temp; // sfix38_En32
wire signed [37:0] Product_mul_temp_1; // sfix38_En32
wire signed [17:0] phase_currents [0:1]; // sfix18_En15 [2]
assign adc[0] = adc_0;
assign adc[1] = adc_1;
// <S1>/ADC_Zero_Offset
assign ADC_Zero_Offset_out1 = 18'sb000000000000000000;
// <S1>/Add
assign Add_v = {ADC_Zero_Offset_out1[17], {ADC_Zero_Offset_out1, 1'b0}};
assign Add_sub_cast = adc[0];
assign Add_out1[0] = Add_sub_cast - Add_v;
assign Add_sub_cast_1 = adc[1];
assign Add_out1[1] = Add_sub_cast_1 - Add_v;
// <S1>/ADC_Amps_Per_Driver_Unit
assign ADC_Amps_Per_Driver_Unit_out1 = 18'sb010100000000000000;
// <S1>/Product
assign Product_mul_temp = Add_out1[0] * ADC_Amps_Per_Driver_Unit_out1;
assign phase_currents[0] = ((Product_mul_temp[37] == 1'b0) && (Product_mul_temp[36:34] != 3'b000) ? 18'sb011111111111111111 :
((Product_mul_temp[37] == 1'b1) && (Product_mul_temp[36:34] != 3'b111) ? 18'sb100000000000000000 :
$signed(Product_mul_temp[34:17])));
assign Product_mul_temp_1 = Add_out1[1] * ADC_Amps_Per_Driver_Unit_out1;
assign phase_currents[1] = ((Product_mul_temp_1[37] == 1'b0) && (Product_mul_temp_1[36:34] != 3'b000) ? 18'sb011111111111111111 :
((Product_mul_temp_1[37] == 1'b1) && (Product_mul_temp_1[36:34] != 3'b111) ? 18'sb100000000000000000 :
$signed(Product_mul_temp_1[34:17])));
assign phase_currents_0 = phase_currents[0];
assign phase_currents_1 = phase_currents[1];
endmodule // controllerHdl_ADC_Peripheral_To_Phase_Current
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; long long int arr[n]; map<long long int, bool> mp; deque<long long int> dq; for (long long int i = 0; i < n; i++) { cin >> arr[i]; mp[arr[i]] = false; } for (long long int i = 0; i < n; i++) { if (!mp[arr[i]]) { mp[arr[i]] = true; if (dq.size() == k) { mp[dq.back()] = false; dq.pop_back(); } dq.push_front(arr[i]); } } cout << dq.size() << endl; for (auto x : dq) { cout << x << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 402; int a[maxn], f[maxn][2]; int n, m, s, ans; int main() { int i, j, k; scanf( %d%d , &n, &m); while (m--) { scanf( %d , &k); while (k--) { scanf( %d , &i); a[i] = ++s; } } for (k = 1; k <= n; k++) if (!a[k]) break; for (i = 1; i <= s; i++) { if (a[i] != i) { for (j = i + 1; j <= n; j++) if (a[j] == i) break; if (i != k) { f[++ans][0] = i; f[ans][1] = k; } f[++ans][0] = j; f[ans][1] = i; a[k] = a[i]; a[i] = i; k = j; } } printf( %d n , ans); for (i = 1; i <= ans; i++) printf( %d %d n , f[i][0], f[i][1]); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> p[300100]; int per[300300]; long long sz[300300]; long long mx[300300]; int res[300300]; long long dfs(int x) { sz[x]++; for (int i = 0; i < p[x].size(); i++) { long long t = dfs(p[x][i]); sz[x] += t; mx[x] = max(mx[x], t); } return sz[x]; } bool ch(int x, int y) { if (mx[y] * 2 > sz[x]) return 0; if ((sz[x] - sz[y]) * 2 > sz[x]) return 0; return 1; } void f(int x) { int st = x, maxx = 0; if (ch(x, x)) res[x] = x; for (int i = 0; i < p[x].size(); i++) { f(p[x][i]); if (maxx < sz[p[x][i]]) { maxx = sz[p[x][i]]; st = res[p[x][i]]; } } while (1) { if (ch(x, st)) { res[x] = st; break; } st = per[st]; } } int main() { int n, q, z; cin >> n >> q; for (int i = 2; i <= n; i++) { scanf( %d , &z); per[i] = z; p[z].push_back(i); } dfs(1); f(1); for (int i = 0; i < q; i++) { scanf( %d , &z); printf( %d n , res[z]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const int N = 1e3 + 5; long long fac[N], ifac[N]; long long be(long long b, long long e, long long m) { long long r = 1; while (e) if (e & 1) r = (r * b) % m, e ^= 1; else b = (b * b) % m, e >>= 1; return r; } long long cmb(int n, int k) { long long r = (fac[n] * ifac[k]) % MOD; return (r * ifac[n - k]) % MOD; } int n, A[N]; long long dp[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); fac[0] = ifac[0] = 1; for (long long x = 1; x < N; x++) fac[x] = (fac[x - 1] * (1LL * x)) % MOD, ifac[x] = be(fac[x], MOD - 2, MOD); cin >> n; for (int x = 0, qwerty = n; x < qwerty; x++) cin >> A[x]; dp[n] = 1; for (int x = n - 1; x >= 0; x--) { if (A[x] <= 0 || x + A[x] >= n) continue; for (int y = x + A[x] + 1; y <= n; y++) dp[x] = (dp[x] + cmb(y - (x + 1), A[x]) * dp[y]) % MOD; } long long ans = 0; for (int x = 0; x < n; x++) { ans += dp[x]; if (ans >= MOD) ans -= MOD; } cout << ans << n ; } |
`timescale 1ns / 10ps
/////////////////////////////////////////////////////////////////////
//// ////
//// SPI Slave Model ////
//// ////
//// Authors: Richard Herveille () www.asics.ws ////
//// ////
//// http://www.opencores.org/projects/simple_spi/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: spi_slave_model.v,v 1.2 2006/11/20 17:22:05 tame Exp $
//
// $Date: 2006/11/20 17:22:05 $
// $Revision: 1.2 $
// $Author: tame $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: spi_slave_model.v,v $
// Revision 1.2 2006/11/20 17:22:05 tame
// Added seperate read address so that valid data from previousl write address is sent
// automatically.
//
// Revision 1.1 2006/11/14 16:34:07 tame
// Added testbench. Simulation running.
//
// Revision 1.1 2006/11/10 14:47:52 chu
// initial definition
//
// Revision 1.1 2004/02/28 16:01:47 rherveille
// Initial testbench release added
//
//
//
//
// Requires: Verilog2001
// `include "timescale.v"
module spi_slave_model (
input wire csn,
input wire sck,
input wire di,
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg [7:0] sri, sro; // 8bit shift register
reg [2:0] bit_cnt;
reg ld;
wire clk;
// slave shall automatically send what has been
// written previously
wire [2:0] mem_adr_read;
assign mem_adr_read = mem_adr - 1;
integer ID=99;
// module body
//
assign clk = cpol ^ cpha ^ sck;
// generate shift registers
always @(posedge clk)
sri <= #1 {sri[6:0],di};
always @(posedge clk)
if (&bit_cnt)
sro <= #1 mem[mem_adr_read];
else
sro <= #1 {sro[6:0],1'bx};
assign do = csn==0 ? sro[7] : 1'bz;
//generate bit-counter
always @(posedge clk, posedge csn)
if(csn)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
always @(posedge clk)
ld <= #1 ~(|bit_cnt);
always @(negedge clk)
if (ld) begin
mem[mem_adr] <= #1 sri;
mem_adr <= #1 mem_adr + 1'b1;
if (debug==1)
$display("slave: received %8b", sri);
end
initial
begin
bit_cnt=3'b111;
mem_adr = 0;
sro = mem[mem_adr_read];
end
always @(negedge csn)
if (csn==1'b0) $display("slave: my ID is %2d", ID);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09.10.2016 16:17:23
// Design Name:
// Module Name: FIFO
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo #
(
parameter FIFO_SIZE = 8,
parameter DATA_WIDTH = 32
)
(
input wire enable,
input wire clear,
output wire fifo_ready,
input wire push_clock,
input wire pop_clock,
input wire [DATA_WIDTH - 1 : 0] in_data,
output wire [DATA_WIDTH - 1 : 0] out_data,
output wire popped_last,
output wire pushed_last
);
reg [DATA_WIDTH - 1 : 0] fifo_data [FIFO_SIZE - 1 : 0];
reg [DATA_WIDTH - 1 : 0] buffer;
reg pushed_last_value;
reg popped_last_value;
reg [15: 0] data_count;
reg [15: 0] position;
reg [15: 0] counter;
initial position = 0;
initial buffer = 0;
initial pushed_last_value = 0;
initial popped_last_value = 0;
initial data_count = 0;
assign fifo_ready = enable && ~clear;
assign out_data = buffer;
assign pushed_last = pushed_last_value;
assign popped_last = popped_last_value;
always@ (posedge push_clock, posedge pop_clock, posedge clear)
begin
if(clear)
begin
for(counter = 0; counter < FIFO_SIZE; counter = counter + 1)
fifo_data[counter] <= 0;
position <= 0;
data_count <= 0;
popped_last_value <= 0;
pushed_last_value <= 0;
buffer <= 0;
end
else
begin
if(enable)
begin
//todo: umv: think about smart event separation for push and pop
if(push_clock && ~pop_clock)
begin
if(data_count < FIFO_SIZE)
begin
popped_last_value <= 0;
fifo_data[position] <= in_data;
position <= position + 1;
data_count <= data_count + 1;
if(position == FIFO_SIZE - 1)
begin
position <= 0;
pushed_last_value <= 1;
end
else pushed_last_value <= 0;
end
end
else if(pop_clock && ~push_clock)
begin
if (data_count >= 1)
begin
buffer <= fifo_data[0];
data_count <= data_count - 1;
pushed_last_value <= 0;
for(counter = 0; counter < FIFO_SIZE - 1; counter = counter + 1)
fifo_data[counter] <= fifo_data[counter + 1];
fifo_data[FIFO_SIZE - 1] <= 0;
position <= position - 1;
popped_last_value <= position == 1;
if(data_count == 1)
popped_last_value <= 1;
end
else buffer <= 0;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
`include "../src/axis_generator.v"
module test_axis_generator(
);
localparam integer C_WIN_NUM = 8;
localparam integer C_PIXEL_WIDTH = 8;
localparam integer C_IMG_WBITS = 12;
localparam integer C_IMG_HBITS = 12;
localparam integer C_MAX_WIN_NUM = 8;
localparam integer C_EXT_FSYNC = 1;
reg clk;
reg resetn;
reg fsync;
reg [C_IMG_WBITS-1:0] s_width ;
reg [C_IMG_HBITS-1:0] s_height;
reg [C_IMG_WBITS-1 : 0] win_left [C_MAX_WIN_NUM-1 : 0];
reg [C_IMG_HBITS-1 : 0] win_top [C_MAX_WIN_NUM-1 : 0];
reg [C_IMG_WBITS-1 : 0] win_width [C_MAX_WIN_NUM-1 : 0];
reg [C_IMG_HBITS-1 : 0] win_height [C_MAX_WIN_NUM-1 : 0];
reg [C_MAX_WIN_NUM-1:0] s_dst_bmp [C_MAX_WIN_NUM-1 : 0];
reg m_random ;
reg [C_MAX_WIN_NUM-1:0] m_enprint;
wire m_valid ;
wire [C_PIXEL_WIDTH-1:0] m_data ;
wire m_user ;
wire m_last ;
reg m_ready ;
wire [C_WIN_NUM-1:0] win_pixel_need;
axis_generator # (
.C_WIN_NUM (C_WIN_NUM ),
.C_EXT_FSYNC (C_EXT_FSYNC ),
.C_PIXEL_WIDTH (C_PIXEL_WIDTH ),
.C_IMG_WBITS (C_IMG_WBITS ),
.C_IMG_HBITS (C_IMG_HBITS )
) uut (
.clk(clk),
.resetn(resetn),
.fsync(fsync),
.width(s_width),
.height(s_height),
.s0_left (win_left [0]),
.s0_top (win_top [0]),
.s0_width (win_width [0]),
.s0_height (win_height [0]),
.s0_dst_bmp (s_dst_bmp [0]),
.s1_left (win_left [1]),
.s1_top (win_top [1]),
.s1_width (win_width [1]),
.s1_height (win_height [1]),
.s1_dst_bmp (s_dst_bmp [1]),
.s2_left (win_left [2]),
.s2_top (win_top [2]),
.s2_width (win_width [2]),
.s2_height (win_height [2]),
.s2_dst_bmp (s_dst_bmp [2]),
.s3_left (win_left [3]),
.s3_top (win_top [3]),
.s3_width (win_width [3]),
.s3_height (win_height [3]),
.s3_dst_bmp (s_dst_bmp [3]),
.s4_left (win_left [4]),
.s4_top (win_top [4]),
.s4_width (win_width [4]),
.s4_height (win_height [4]),
.s4_dst_bmp (s_dst_bmp [4]),
.s5_left (win_left [5]),
.s5_top (win_top [5]),
.s5_width (win_width [5]),
.s5_height (win_height [5]),
.s5_dst_bmp (s_dst_bmp [5]),
.s6_left (win_left [6]),
.s6_top (win_top [6]),
.s6_width (win_width [6]),
.s6_height (win_height [6]),
.s6_dst_bmp (s_dst_bmp [6]),
.s7_left (win_left [7]),
.s7_top (win_top [7]),
.s7_width (win_width [7]),
.s7_height (win_height [7]),
.s7_dst_bmp (s_dst_bmp [7]),
.m_axis_tvalid(m_valid ),
.m_axis_tdata (m_data ),
.m_axis_tuser ({win_pixel_need, m_user} ),
.m_axis_tlast (m_last ),
.m_axis_tready(m_ready )
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
`define SET_WIN(_idx, _l, _t, _w, _h) \
win_left [_idx] <= _l; \
win_top [_idx] <= _t; \
win_width [_idx] <= _w; \
win_height[_idx] <= _h
initial begin
fsync <= 0;
m_random <= 1;
m_enprint <= (1 << 0);
s_width <= 20;
s_height <= 15;
s_dst_bmp[0] <= 8'b00000001;
s_dst_bmp[1] <= 8'b00000010;
s_dst_bmp[2] <= 8'b00000000;
s_dst_bmp[3] <= 8'b00000000;
s_dst_bmp[4] <= 8'b00000000;
s_dst_bmp[5] <= 8'b00000000;
s_dst_bmp[6] <= 8'b00000000;
s_dst_bmp[7] <= 8'b00000000;
`SET_WIN(0, 0, 0, 0, 0);
`SET_WIN(1, 0, 0, 0, 0);
`SET_WIN(2, 0, 0, 0, 0);
`SET_WIN(3, 0, 0, 0, 0);
`SET_WIN(4, 0, 0, 0, 0);
`SET_WIN(5, 0, 0, 0, 0);
`SET_WIN(6, 0, 0, 0, 0);
`SET_WIN(7, 0, 0, 0, 0);
end
reg [31:0] fsync_cnt;
reg [31:0] win_seq = 32'b11000;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
fsync <= 0;
fsync_cnt <= 0;
end
else if (fsync_cnt == 0) begin
fsync_cnt <= 1000;
fsync <= 1;
win_seq <= (win_seq >> 1);
if (win_seq[0]) begin
`SET_WIN(0, 0, 1, 10, 5);
end
else begin
`SET_WIN(0, 0, 0, 10, 5);
end
`SET_WIN(1, 3, 10, 5, 3);
`SET_WIN(2, 3, 10, 5, 3);
`SET_WIN(3, 3, 10, 5, 3);
`SET_WIN(4, 3, 10, 5, 3);
`SET_WIN(5, 3, 10, 5, 3);
`SET_WIN(6, 3, 10, 5, 3);
`SET_WIN(7, 3, 10, 5, 3);
end
else begin
fsync <= 0;
fsync_cnt <= fsync_cnt - 1;
end
end
generate
reg [C_IMG_HBITS-1:0] m_ridx;
reg [C_IMG_WBITS-1:0] m_cidx;
reg en_output;
always @ (posedge clk) begin
if (resetn == 1'b0) en_output <= 1'b0;
else en_output <= (m_random ? {$random}%2 : 1) & (fsync < 500);
end
always @(posedge clk) begin
if (resetn == 1'b0)
m_ready <= 1'b0;
else if (~m_ready)
m_ready <= en_output;
else begin
if (m_valid)
m_ready <= en_output;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_ready && m_valid) begin
if (m_user) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_last) begin
m_cidx = 0;
m_ridx = m_ridx + 1;
end
else begin
m_cidx = m_cidx + 1;
m_ridx = m_ridx;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
end
else if (m_ready && m_valid) begin
if (m_user)
$write("out start new frame: \n");
if ((win_pixel_need & m_enprint) != 0)
$write("1 ");
else
$write("0 ");
if (m_last)
$write("\n");
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; vector<vector<long long>> a(n, vector<long long>(3)); vector<long long> b(k); vector<int> make_pair(n + 1); for (int i = 0; i < n; ++i) { cin >> a[i][0]; make_pair[a[i][0]] = i; a[i][1] = i - 1; a[i][2] = i < n - 1 ? i + 1 : -1; } vector<int> st(n + 1, false); for (auto &i : b) { cin >> i; st[i] = true; } long long ans = 1; for (long long i = 0; i < k; ++i) { int pos = make_pair[b[i]]; int cnt = 0; if (a[pos][1] != -1) { int nbr = a[pos][1]; if (!st[a[nbr][0]]) cnt++; } if (a[pos][2] != -1) { int nbr = a[pos][2]; if (!st[a[nbr][0]]) cnt++; } st[b[i]] = false; int l = a[pos][1]; int r = a[pos][2]; if (l != -1) a[l][2] = r; if (r != -1) a[r][1] = l; if (!cnt) { ans = 0; break; } ans = (ans * cnt) % ((long long)(998244353)); } cout << ans << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, s; cin >> a >> b >> s; if (s < abs(a) + abs(b)) cout << NO << endl; else if (s == abs(a) + abs(b)) cout << YES << endl; else { s -= abs(a); s -= abs(b); if (s % 2 == 0) cout << YES << endl; else cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { node *l, *r, *p; long long v, s, z, w, t, k, i; node(long long v, long long i) : l(0), r(0), p(0), v(v), s(1), z(0), w(0), t(v), k(1), i(i) {} }; inline bool is_root(node *n) { return n->p == NULL || n->p->l != n && n->p->r != n; } inline bool left(node *n) { return n == n->p->l; } inline long long size(node *n) { return n ? n->s + n->z : 0; } inline long long tot(node *n) { return n ? n->t : 0; } inline void push(node *n) { n->s += n->z; n->w += n->z; n->k += 2 * n->z * (n->s - n->w); if (n->l) n->l->z += n->z; if (n->r) n->r->z += n->z; n->z = 0; } inline void update(node *n) { push(n); n->t = tot(n->l) + tot(n->r) + n->v * (n->s - n->w); } inline void connect(node *n, node *p, bool l) { (l ? p->l : p->r) = n; if (n) n->p = p; } inline void rotate(node *n) { node *p = n->p, *g = p->p; bool l = left(n); connect(l ? n->r : n->l, p, l); if (!is_root(p)) connect(n, g, left(p)); else n->p = g; connect(p, n, !l); update(p), update(n); } inline void splay(node *n) { while (!is_root(n)) { node *p = n->p, *g = p->p; if (!is_root(p)) push(g); push(p), push(n); if (!is_root(p)) rotate(left(n) ^ left(p) ? n : p); rotate(n); } push(n); } inline node *find_root(node *n) { if (n == NULL) return NULL; while (n->l) { push(n); n = n->l; } return n; } inline node *expose(node *n) { node *last = NULL; for (node *m = n; m; m = m->p) { splay(m); m->w = size(find_root(last)); m->r = last; last = m; update(m); } splay(n); return last; } void link(node *m, node *n) { expose(m), expose(n); m->p = n; n->z += size(m); } void cut(node *n) { expose(n); n->l->z -= size(n); n->l->p = NULL; n->l = NULL; } node *lca(node *m, node *n) { expose(m); return expose(n); } const int MAXN = 50005; long long N, M, P[MAXN], A, B, ans; char C; node *V[MAXN]; int main() { cin >> N; cout << fixed << setprecision(9); for (int i = 1; i < N; i++) { cin >> P[i]; P[i]--; } for (int i = 0; i < N; i++) { int v; cin >> v; V[i] = new node(v, i); ans += v; } for (int i = 1; i < N; i++) { link(V[i], V[P[i]]); ans += 2 * tot(V[P[i]]) * size(V[i]); } cout << 1.0 * ans / N / N << n ; cin >> M; while (M--) { cin >> C >> A >> B; if (C == P ) { node *v = V[A - 1], *u = V[B - 1]; if (lca(u, v) == v) swap(u, v); expose(v); ans -= 2 * tot(v->l) * size(v); cut(v); link(v, u); ans += 2 * tot(u) * size(v); } else { node *v = V[A - 1]; expose(v); update(v); ans += (B - v->v) * v->k; v->v = B; } cout << 1.0 * ans / N / N << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); int n, m; cin >> n >> m; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } cout << 0 ; vector<int> cnt(110, 0); cnt[a[0]]++; for (int w = 1; w < n; ++w) { int s = a[w]; int k = 0; for (int i = 1; i <= 100; ++i) { if (s + i * cnt[i] <= m) { s += i * cnt[i]; k += cnt[i]; } else { int l = -1, r = cnt[i] + 1; while (r - l > 1) { int mid = (l + r) / 2; if (s + i * mid <= m) { l = mid; } else { r = mid; } } k += l; break; } } cout << w - k << ; cnt[a[w]]++; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_1_V
`define SKY130_FD_SC_LP__O211AI_1_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_1_V
|
#include <bits/stdc++.h> using namespace std; const int OO = 1e9; const double EPS = 1e-9; template <class T> void _db(const char* dbStr, T e) { cout << dbStr << = << e << endl; } template <class T, class... L> void _db(const char* dbStr, T e, L... r) { while (*dbStr != , ) cout << *dbStr++; cout << = << e << , ; _db(dbStr + 1, r...); } template <class S, class T> ostream& operator<<(ostream& o, const map<S, T>& v) { o << [ ; int i = 0; for (const pair<S, T>& pr : v) o << (!i++ ? : , ) << { << pr.first << : << pr.second << } ; return o << ] ; } template <template <class, class...> class S, class T, class... L> ostream& operator<<(ostream& o, const S<T, L...>& v) { o << [ ; int i = 0; for (const auto& e : v) o << (!i++ ? : , ) << e; return o << ] ; } template <class S, class T> ostream& operator<<(ostream& o, const pair<S, T>& pr) { return o << ( << pr.first << , << pr.second << ) ; } ostream& operator<<(ostream& o, const string& s) { for (const char& c : s) o << c; return o; } template <class T> using V = vector<T>; template <class T> using VV = V<V<T>>; template <class T> using VVV = VV<V<T>>; using ll = long long; using pii = pair<int, int>; using vi = V<int>; using vii = V<pii>; using vvi = VV<int>; using mii = map<int, int>; using umii = unordered_map<int, int>; using si = set<int>; using usi = unordered_set<int>; vii monoStFunc(vi a) { int n = int(a.size()); vii b(n); stack<pii> st; st.push(make_pair(INT_MAX, -1)); for (int i = 0; i < n; ++i) { while (st.top().first < a[i]) st.pop(); b[i].first = st.top().second; st.push(make_pair(a[i], i)); } while (!st.empty()) st.pop(); st.push(make_pair(INT_MAX, n)); for (int i = n - 1; i >= 0; --i) { while (st.top().first <= a[i]) st.pop(); b[i].second = st.top().second; st.push(make_pair(a[i], i)); } return b; } int n, q; vi a, d; int main() { ios::sync_with_stdio(false); cout.precision(10); cin.tie(0); cin >> n >> q; a.assign(n, 0); for (int i = 0; i < n; ++i) cin >> a[i]; d.assign(n - 1, 0); for (int i = 0; i < n - 1; ++i) d[i] = abs(a[i + 1] - a[i]); true; for (int qq = 0; qq < q; ++qq) { int l, r; cin >> l >> r; --l, --r; vi v; for (int i = l; i < r; ++i) v.push_back(d[i]); vii LR = monoStFunc(v); ll ans = 0; for (int i = 0; i < int(v.size()); ++i) ans += v[i] * 1LL * ((i - LR[i].first) * 1LL * (LR[i].second - i)); cout << ans << n ; } return 0; } |
#include<bits/stdc++.h> #define ll long long #define pii pair<ll,ll> #define debug(a) cout<<a<< n #define maxn 200009 /// I wanna be withma youlu #define MOD 1000000007 #define F first #define S second #define rep(i, a, b) for(ll i = a; i < (b); ++i) #define per(i, b, a) for(ll i = b-1; i>=a ; i--) #define trav(a, x) for(auto& a : x) #define allin(a , x) for(auto a : x) #define all(x) begin(x), end(x) #define sz(x) (ll)(x).size() using namespace std; const ll INF = 1e9 + 9; int main(){ ios::sync_with_stdio(false); cin.tie(0); ll t; cin>>t; while(t--){ ll n; cin>>n; string s,s2; cin>>s>>s2; ll conta = 0,contb = 0; rep(i,0,n){ if(s[i] - 0 > s2[i] - 0 )conta++; else if(s[i] - 0 < s2[i] - 0 )contb++; } // cout<<conta<< <<contb<<endl; if(conta > contb) cout<< RED n ; else if(conta == contb) cout<< EQUAL n ; else cout<< BLUE n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1100], b[1100]; int main() { int i, j, n, k, x; cin >> n >> k >> x; int arr[n]; for (i = 0; i < n; i++) { cin >> arr[i]; a[arr[i]]++; } for (j = 0; j < k; j++) { int sum = 0; for (i = 0; i < 1100; i++) { if (a[i] > 0) { if (a[i] % 2 == 0) { int l = (i ^ x); b[l] += a[i] / 2; b[i] += a[i] / 2; } else { if (sum % 2 == 0) { int l = (i ^ x); b[l] += a[i] / 2 + 1; b[i] += a[i] / 2; } else { int l = (i ^ x); b[l] += a[i] / 2; b[i] += a[i] / 2 + 1; } } sum += a[i]; } } for (i = 0; i < 1100; i++) { a[i] = b[i]; b[i] = 0; } } int Min = INT_MAX; int Max = INT_MIN; for (i = 0; i < 1100; i++) { if (a[i] > 0) { Min = min(i, Min); Max = max(Max, i); } } cout << Max << << Min << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; static const int maxn = 100010; static const int INF = 0x3f3f3f3f; static const int mod = (int)1e9 + 7; static const double eps = 1e-6; static const double pi = acos(-1); void redirect() {} char s[maxn]; int cnt[26]; int main() { redirect(); int T; scanf( %d , &T); while (T--) { memset(cnt, 0, sizeof(cnt)); scanf( %s , s); for (int i = 0; s[i]; i++) cnt[s[i] - a ]++; bool flag = true; for (int i = 0; i < 26; i++) if (cnt[i] > 1) flag = false; int i = 0; while (i < 26 && cnt[i] == 0) i++; while (i < 26 && cnt[i] == 1) i++; for (; i < 26; i++) if (cnt[i]) flag = false; if (flag) puts( Yes ); else puts( No ); } return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_serialize #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
input pipe_stb_i,
output reg pipe_ack_o,
input [fml_depth-5-1:0] tadra,
input [fml_depth-5-1:0] tadrb,
input [fml_depth-5-1:0] tadrc,
input [fml_depth-5-1:0] tadrd,
input miss_a,
input miss_b,
input miss_c,
input miss_d,
output reg pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-5-1:0] adr
);
/* Input registers */
reg load_en;
reg [fml_depth-5-1:0] r_tadra;
reg [fml_depth-5-1:0] r_tadrb;
reg [fml_depth-5-1:0] r_tadrc;
reg [fml_depth-5-1:0] r_tadrd;
reg r_miss_a;
reg r_miss_b;
reg r_miss_c;
reg r_miss_d;
always @(posedge sys_clk) begin
if(load_en) begin
r_tadra <= tadra;
r_tadrb <= tadrb;
r_tadrc <= tadrc;
r_tadrd <= tadrd;
r_miss_a <= miss_a;
r_miss_b <= miss_b;
r_miss_c <= miss_c;
r_miss_d <= miss_d;
end
end
/* Output multiplexer */
reg [1:0] adr_sel;
always @(*) begin
case(adr_sel)
2'd0: adr = r_tadra;
2'd1: adr = r_tadrb;
2'd2: adr = r_tadrc;
default: adr = r_tadrd;
endcase
end
/* Miss mask */
reg [3:0] missmask;
reg missmask_init;
reg missmask_we;
always @(posedge sys_clk) begin
if(missmask_init)
missmask <= 4'b1111;
if(missmask_we) begin
case(adr_sel)
2'd0: missmask <= missmask & 4'b1110;
2'd1: missmask <= missmask & 4'b1101;
2'd2: missmask <= missmask & 4'b1011;
default: missmask <= missmask & 4'b0111;
endcase
end
end
/* Control logic */
reg state;
reg next_state;
parameter LOAD = 1'b0;
parameter SERIALIZE = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= LOAD;
else
state <= next_state;
end
always @(*) begin
next_state = state;
busy = 1'b0;
pipe_ack_o = 1'b0;
pipe_stb_o = 1'b0;
load_en = 1'b0;
adr_sel = 2'd0;
missmask_init = 1'b0;
missmask_we = 1'b0;
case(state)
LOAD: begin
pipe_ack_o = 1'b1;
load_en = 1'b1;
missmask_init = 1'b1;
if(pipe_stb_i)
next_state = SERIALIZE;
end
SERIALIZE: begin
pipe_stb_o = 1'b1;
missmask_we = 1'b1;
if(r_miss_a & missmask[0])
adr_sel = 2'd0;
else if(r_miss_b & missmask[1])
adr_sel = 2'd1;
else if(r_miss_c & missmask[2])
adr_sel = 2'd2;
else if(r_miss_d & missmask[3])
adr_sel = 2'd3;
else begin
pipe_stb_o = 1'b0;
next_state = LOAD;
end
if(~pipe_ack_i)
missmask_we = 1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int N = 2e5 + 5; void solve() { long long int n; cin >> n; long long int k = sqrt(n); long long int sum = 0; if (n == k * k) { cout << 4 * k << n ; return; } sum = sum + k * 4; n = n - (k * k); if (n > (k)) { sum = sum + (n / (k)) * 2; if (n % k != 0) sum = sum + 2; } else { sum = sum + 2; } cout << sum << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); string x; cin >> x; string y = x; for (int i = 0; i < x.length(); i++) { if (x[i] == a ) continue; for (int j = i; j < x.length(); j++) { if (x[j] == a ) break; x[j] = char(int(x[j]) - 1); } break; } if (y == x) { x[x.length() - 1] = z ; } cout << x << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long rev_6 = 166666668ll; const long long rev_2 = 500000004ll; const long long MOD = 1000000007ll; long long pow(long long A, long long n) { long long r = 1ll; while (n) { if (n & 1ll) r = r * A % MOD; A = A * A % MOD; n >>= 1; } return r; } int main() { bool odd = true, one = true; int k; long long ans = 2, temp; cin >> k; while (k--) { cin >> temp; if (temp > 1ll) one = false; if (temp % 2ll == 0ll) odd = false; ans = pow(ans, temp); } if (one) cout << 0/1 n ; else { long long q = ans * rev_2 % MOD; if (odd) ans -= 2; else ans += 2; if (ans < 0) ans += MOD; ans = ans * rev_6 % MOD; cout << ans << / << q << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFBBN_PP_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::system_clock::now().time_since_epoch().count()); mt19937_64 rngll(rng()); const int mn = 1e6 + 10; const long long mod = 1e9 + 7; long long fact[mn]; long long po(long long a, long long b = mod - 2) { if (b < 0) b += mod - 1; long long ans = 1; for (; b; b >>= 1, a *= a, a %= mod) if (b & 1) ans *= a, ans %= mod; return ans; } long long ch(long long n, long long k) { if (k < 0 || k > n) return 0; return fact[n] * po(fact[k] * fact[n - k] % mod) % mod; } int main() { int n, m, a, b; scanf( %d%d%d%d , &n, &m, &a, &b); fact[0] = 1; for (int i = 1; i < mn; i++) fact[i] = fact[i - 1] * i % mod; long long ans = 0; for (int i = 1; i <= n - 1; i++) { long long num = ch(m - 1, i - 1); num *= ch(n - 2, i - 1) * fact[i - 1] % mod, num %= mod; num *= po(m, n - i - 1), num %= mod; num *= (i + 1) * po(n, n - 1 - i - 1) % mod, num %= mod; ans += num, ans %= mod; } printf( %lld , ans); } |
module alu (a_input, b_input, funct, res, z);
// input
input [31:0] a_input;
input [31:0] b_input;
input [4:0] funct;
// output
output [31:0] res;
output z;
// reg
reg [31:0] res = 0;
reg z = 0;
reg [31:0] hi = 0;
reg [31:0] lo = 0;
// combinational logic but easier to understand format
always @(a_input or b_input or funct)
begin
if (funct == 'b00000)
begin
// sll
res = a_input << b_input;
z = 0;
$display("%d = %d << %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00001)
begin
// srl
res = a_input >> b_input;
z = 0;
$display("%d = %d >> %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00010)
begin
// sra
res = $signed(a_input) >>> $signed(b_input);
z = 0;
$display("%d = %d >>> %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00011)
begin
// mfhi
res = hi;
z = 0;
$display("HI = %d", res);
end
else if (funct == 'b00100)
begin
// mflo
res = lo;
z = 0;
$display("LO = %d", res);
end
else if (funct == 'b00101)
begin
// mul
res = ($signed(a_input) * $signed(b_input));
z = 0;
$display("%d = %d * %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00110)
begin
// div
lo = ($signed(a_input) / $signed(b_input));
hi = ($signed(a_input) % $signed(b_input));
$display("%d = %d / %d", $signed(lo), $signed(a_input), $signed(b_input));
z = 0;
end
else if (funct == 'b00111)
begin
// divu
hi = ($unsigned(a_input) / $unsigned(b_input));
lo = ($unsigned(a_input) % $unsigned(b_input));
z = 0;
end
else if (funct == 'b01000)
begin
// add rd, rs, rt
res = $signed(a_input) + $signed(b_input);
z = 0;
$display("%d = %d + %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01001)
begin
// addu rd, rs, rt
res = a_input + b_input;
z = 0;
$display("%d = u%d + u%d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01010)
begin
// sub rd, rs, rt
res = $signed(a_input) - $signed(b_input);
z = 0;
$display("%d = %d - %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01011)
begin
// subu rd, rs, rt
res = a_input - b_input;
z = 0;
$display("%d = u%d - u%d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01100)
begin
// and rd, rs, rt
res = a_input & b_input;
z = 0;
$display("%d = %d & %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01101)
begin
// or rd, rs, rt
res = a_input | b_input;
z = 0;
$display("%d = %d | %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01110)
begin
// xor rd, rs, rt
res = a_input ^ b_input;
z = 0;
$display("%d = %d ^ %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01111)
begin
// nor rd, rs, rt
res = ~(a_input | b_input);
z = 0;
$display("%d = ~(%d | %d)", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b10000)
begin
// slt rd, rs, rt
res = $signed(a_input) < $signed(b_input) ? 1 : 0;
z = 0;
$display("%d = (%d < %d)", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b10001)
begin
// sltu rd, rs, rt
res = a_input < b_input ? 1 : 0;
z = 0;
$display("%d = u%d < u%d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b10010)
begin
// lui
res = b_input << 16;
z = 0;
$display("%d = %d << 16", $signed(res), $signed(b_input));
end
else if (funct == 'b10011)
begin
// beq rd, rs, rt
z = a_input == b_input ? 1 : 0;
res = 0;
$display("%d = %d == %d", z, $signed(a_input), $signed(b_input));
end
else if (funct == 'b10100)
begin
// blt rd, rs, rt
z = $signed(a_input) < $signed(b_input) ? 1 : 0;
res = 0;
$display("%d = %d < %d", z, $signed(a_input), $signed(b_input));
end
else if (funct == 'b10101)
begin
// bne rd, rs, rt
z = a_input != b_input ? 1 : 0;
res = 0;
$display("%d = %d != %d", z, $signed(a_input), $signed(b_input));
end
else if (funct == 'b10110)
begin
// bleq rd, rs, rt
z = $signed(a_input) <= $signed(b_input) ? 1 : 0;
res = 0;
$display("%d = %d <= %d", z, $signed(a_input), $signed(b_input));
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; char s[10], a1[] = { vaporeon }, a2[] = { jolteon }, a3[] = { flareon }, a4[] = { espeon }, a5[] = { umbreon }, a6[] = { leafeon }, a7[] = { glaceon }, a8[] = { sylveon }; int n, i; int main() { cin >> n; cin >> s; if (n == 6) { cout << a4; return 0; } if (n == 8) { cout << a1; return 0; } for (i = 0; i < n; i++) { if (s[i] != . ) if (s[i] != a2[i]) break; } if (i == n) { cout << a2; return 0; } for (i = 0; i < n; i++) { if (s[i] != . ) if (s[i] != a3[i]) break; } if (i == n) { cout << a3; return 0; } for (i = 0; i < n; i++) { if (s[i] != . ) if (s[i] != a5[i]) break; } if (i == n) { cout << a5; return 0; } for (i = 0; i < n; i++) { if (s[i] != . ) if (s[i] != a6[i]) break; } if (i == n) { cout << a6; return 0; } for (i = 0; i < n; i++) { if (s[i] != . ) if (s[i] != a7[i]) break; } if (i == n) { cout << a7; return 0; } for (i = 0; i < n; i++) { if (s[i] != . ) if (s[i] != a8[i]) break; } if (i == n) { cout << a8; return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; char str[5009]; int main() { int a = 0, b = 0, c = 0, i; scanf( %s , str); int n = strlen(str); for (i = 0; str[i] == a ; i++) a++; for (; str[i] == b ; i++) b++; for (; str[i] == c ; i++) c++; if (a && b && n == a + b + c && (a == c || c == b)) { printf( YES n ); } else { printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct rec { int w, h; }; vector<rec> v; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { int w, h; scanf( %d %d , &w, &h); v.push_back({w, h}); } int last = -0x3f3f3f3f; for (int i = n; i > 0; i--) { int prev = max(v[i - 1].w, v[i - 1].h); int mini = min(v[i].h, v[i].w); int maxi = max(v[i].h, v[i].w); if (mini >= last && mini <= prev) { last = mini; } else if (maxi >= last && maxi <= prev) { last = maxi; } else { printf( NO n ); return 0; } } printf( YES n ); return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../tracking_camera_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "tracking_camera_system_onchip_memory2_0.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; bool poss = true; int n, rt = 0; vector<int> v, res; vector<vector<int>> adj; vector<pair<int, int>> dfs(int second, int p) { vector<pair<int, int>> cur; for (auto i : adj[second]) { if (i != p) { vector<pair<int, int>> ch = dfs(i, second); for (auto i : ch) { cur.push_back(i); } } } sort(cur.begin(), cur.end()); for (int i = 0; i < cur.size(); ++i) { if (i < v[second]) cur[i].first = i; else cur[i].first = i + 1; } if (v[second] > cur.size()) poss = false; cur.push_back({v[second], second}); return cur; } int main() { cin >> n; adj.assign(n, vector<int>()); v.assign(n, 0); res.assign(n, 0); for (int i = 0; i < n; ++i) { int x; cin >> x >> v[i]; x--; if (x != -1) { adj[x].push_back(i); adj[i].push_back(x); } else rt = i; } vector<pair<int, int>> cur = dfs(rt, rt); for (auto i : cur) { res[i.second] = i.first + 1; } if (!poss) { cout << NO ; return 0; } cout << YES n ; for (auto i : res) { cout << i << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; long long cnt = 0.5 * n / (k + 1); cout << cnt << << cnt * k << << n - cnt - cnt * k << endl; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The SRAM module to implement all SRAMs
//
// ====================================================================
`include "e203_defines.v"
module e203_srams(
`ifdef E203_HAS_ITCM //{
input itcm_ram_sd,
input itcm_ram_ds,
input itcm_ram_ls,
input itcm_ram_cs,
input itcm_ram_we,
input [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr,
input [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem,
input [`E203_ITCM_RAM_DW-1:0] itcm_ram_din,
output [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout,
input clk_itcm_ram,
input rst_itcm,
`endif//}
`ifdef E203_HAS_DTCM //{
input dtcm_ram_sd,
input dtcm_ram_ds,
input dtcm_ram_ls,
input dtcm_ram_cs,
input dtcm_ram_we,
input [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
input [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
input clk_dtcm_ram,
input rst_dtcm,
`endif//}
input test_mode
);
`ifdef E203_HAS_ITCM //{
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout_pre;
e203_itcm_ram u_e203_itcm_ram (
.sd (itcm_ram_sd),
.ds (itcm_ram_ds),
.ls (itcm_ram_ls),
.cs (itcm_ram_cs ),
.we (itcm_ram_we ),
.addr (itcm_ram_addr ),
.wem (itcm_ram_wem ),
.din (itcm_ram_din ),
.dout (itcm_ram_dout_pre ),
.rst_n(rst_itcm ),
.clk (clk_itcm_ram )
);
// Bob: we dont need this bypass here, actually the DFT tools will handle this SRAM black box
//assign itcm_ram_dout = test_mode ? itcm_ram_din : itcm_ram_dout_pre;
assign itcm_ram_dout = itcm_ram_dout_pre;
`endif//}
`ifdef E203_HAS_DTCM //{
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout_pre;
e203_dtcm_ram u_e203_dtcm_ram (
.sd (dtcm_ram_sd),
.ds (dtcm_ram_ds),
.ls (dtcm_ram_ls),
.cs (dtcm_ram_cs ),
.we (dtcm_ram_we ),
.addr (dtcm_ram_addr ),
.wem (dtcm_ram_wem ),
.din (dtcm_ram_din ),
.dout (dtcm_ram_dout_pre ),
.rst_n(rst_dtcm ),
.clk (clk_dtcm_ram )
);
// Bob: we dont need this bypass here, actually the DFT tools will handle this SRAM black box
//assign dtcm_ram_dout = test_mode ? dtcm_ram_din : dtcm_ram_dout_pre;
assign dtcm_ram_dout = dtcm_ram_dout_pre;
`endif//}
endmodule
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire req0, req1, req2;
wire ack0, ack1, ack2;
reg req0_reg;
reg start;
wire [7:0] data0;
reg [7:0] data0_reg;
wire [7:0] data1;
wire [7:0] data2;
wire [7:0] data3;
// assign data0 = data0_reg;
// two_phase_event_gen U_PORT1_EVENT_GEN (
// .run(rst_async_n),
// .req(req0),
// .ack(a)
// );
mousetrap_elt U_MOUSETRAP_STAGE0(
.ackNm1(), // out
.reqN(req0), // In
.ackN(a), // In
.doneN(done0), // Out
.datain(data0),
.dataout(data1),
.rstn(rst_async_n)
);
buff #(.DELAY(20)) U_DELAY0(.i(done0), .z(done0_d));
assign #10 data0 = data1 + 4;
inv U_INV(.i(done0_d), .zn(req0_tmp));
assign req0 = req0_tmp;
assign a =done0_d ;
// two_phase_slave U_SLAVE(.req(req3), .ack(ack2));
// assign #30 ack2_tmp = req3;
// assign ack2 = (ack2_tmp === 1'b1);
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n <= 1'b0;
start <= 1'b0;
// Wait long enough for the X's in the delay elements to disappears
#50;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#5;
start <= 1'b1;
#5;
#200000;
start <= 1'b0;
$display("-I- Done !");
$finish;
end
endmodule // tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_0_V
`define SKY130_FD_SC_LP__O32A_0_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_0 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_0_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:56:24 02/25/2016
// Design Name:
// Module Name: Ctr
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ctr(
input [5:0] opCode,
output reg regDst,
output reg aluSrc,
output reg memToReg,
output reg regWrite,
output reg memRead,
output reg memWrite,
output reg branch,
output reg [1:0] aluOp,
output reg jump
);
always @(opCode)
begin
case (opCode)
6'b000010:
//jump
begin
regDst = 0;
aluSrc = 0;
memToReg = 0;
regWrite = 0;
memRead = 0;
memWrite = 0;
branch =0;
aluOp = 2'b00;
jump = 1;
end
6'b000000:
//R-format
begin
regDst = 1;
aluSrc = 0;
memToReg = 0;
regWrite = 1;
memRead = 0;
memWrite = 0;
branch = 0;
aluOp = 2'b10;
//which one is the MSB?
jump = 0;
end
6'b100011:
//lw
begin
regDst = 0;
aluSrc = 1;
memToReg = 1;
regWrite = 1;
memRead = 1;
memWrite = 0;
branch = 0;
aluOp = 2'b00;
jump = 0;
end
6'b101011:
//sw
begin
regDst = 1; //don't care term
aluSrc = 1;
memToReg = 1; //don't care term
regWrite = 0;
memRead = 0;
memWrite = 1;
branch = 0;
aluOp = 2'b00;
jump = 0;
end
6'b000100:
//beq
begin
regDst = 0; //don't care term
aluSrc = 0;
memToReg = 0; //don't care term
regWrite = 0;
memRead = 0;
memWrite = 0;
branch = 1;
aluOp = 2'b01;
jump = 0;
end
default:
begin
regDst = 0;
aluSrc = 0;
memToReg = 0;
regWrite = 0;
memRead = 0;
memWrite = 0;
branch = 0;
aluOp = 2'b00;
jump = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<string> V; for (int i = 0; i < 4; ++i) { string s; cin >> s; V.push_back(s); } bool pos = false; for (int r = 0; r < 3; ++r) { for (int c = 0; c < 3; ++c) { int dots = 0, nums = 0; dots += (V[r][c] == . ); nums += (V[r][c] != . ); dots += (V[r][c + 1] == . ); nums += (V[r][c + 1] != . ); dots += (V[r + 1][c] == . ); nums += (V[r + 1][c] != . ); dots += (V[r + 1][c + 1] == . ); nums += (V[r + 1][c + 1] != . ); if (dots >= 3 || nums >= 3) pos = true; } } cout << (pos ? YES : NO ); return 0; } |
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module memory_system (
input clk,
input reset,
output stall,
input vm_enable,
input [31:0] ptbr,
input flush_tlb,
input [31:0] fetch_addr,
input fetch_request,
output fetch_data_valid,
input [31:0] dmem_addr,
input [31:0] dmem_write_data,
input [3:0] dmem_write_mask,
input dmem_request,
input dmem_request_type,
output dmem_data_valid,
output [31:0] request_data
);
localparam S_IDLE = 2'd0;
localparam S_TRANSLATE = 2'd1;
localparam S_MEM_ACCESS = 2'd2;
localparam MM_SELECT_TRANSLATER = 1'd1;
localparam MM_SELECT_ARBITER = 1'd0;
reg [1:0] state;
reg [1:0] next_state;
always @ (posedge clk) begin
if (reset)
state <= S_IDLE;
else
state <= next_state;
end
wire arbiter_stall;
wire arbiter_mem_enable;
wire arbiter_cmd;
wire [31:0] arbiter_addr;
wire [31:0] arbiter_write_data = dmem_write_data;
wire [3:0] arbiter_write_mask = dmem_write_mask;
wire [31:0] arbiter_read_data;
wire arbiter_data_valid;
arbiter arbit(.clk(clk), .reset(reset),
.request_data(request_data), .stall(arbiter_stall),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(dmem_addr), .dmem_write_data(dmem_write_data), .dmem_write_mask(dmem_write_mask),
.dmem_request(dmem_request), .dmem_request_type(dmem_request_type), .dmem_data_valid(dmem_data_valid),
.mem_addr(arbiter_addr), .mem_mask(arbiter_write_mask), .mem_enable(arbiter_mem_enable), .mem_cmd(arbiter_cmd),
.mem_data(arbiter_read_data), .mem_wdata(arbiter_write_data), .mem_valid(arbiter_data_valid));
wire translater_mem_enable;
wire translater_cmd = `MEM_CMD_READ;
wire [31:0] translater_addr;
wire [31:0] translater_write_data = dmem_write_data;
wire [3:0] translater_write_mask = dmem_write_mask;
wire [31:0] translater_read_data;
wire translater_data_valid;
wire [31:0] translated_addr;
wire translate_enable = vm_enable;
wire translation_complete;
wire launch_translation;
translater t(.clk(clk), .reset(reset),
.vm_enable(translate_enable), .launch_translation(launch_translation),
.physical_address(translated_addr), .virtual_address(arbiter_addr),
.translation_complete(translation_complete), .ptbr(ptbr), .flush_tlb(flush_tlb),
.translate_mem_enable(translater_mem_enable),
.translate_addr(translater_addr), .request_data(translater_read_data), .translate_data_valid(translater_data_valid));
wire mem_enable;
wire mem_cmd;
wire [31:0] mem_addr;
wire [31:0] mem_write_data;
wire [3:0] mem_write_mask;
wire [31:0] mem_data;
wire mem_valid;
wire mm_select;
memory_mux m(.select(mm_select),
.enable_0(arbiter_mem_enable), .command_0(arbiter_cmd), .address_0(arbiter_addr),
.write_data_0(arbiter_write_data), .write_mask_0(arbiter_write_mask),
.read_data_0(arbiter_read_data), /* .valid_0(), */
.enable_1(translater_mem_enable), .command_1(translater_cmd), .address_1(translater_addr),
.write_data_1(translater_write_data), .write_mask_1(translater_write_mask),
.read_data_1(translater_read_data), .valid_1(translater_data_valid),
.enable(mem_enable), .command(mem_cmd), .address(mem_addr),
.write_data(mem_write_data), .write_mask(mem_write_mask),
.read_data(mem_data), .valid(mem_valid));
assign request_data = mm_select ? translater_read_data : arbiter_read_data;
always @ (*) begin
case (state)
S_IDLE:
if (vm_enable && arbiter_mem_enable)
next_state = S_TRANSLATE;
else
next_state = S_IDLE;
S_TRANSLATE:
if (translation_complete)
next_state = S_MEM_ACCESS;
else
next_state = S_TRANSLATE;
S_MEM_ACCESS:
if (mem_valid)
next_state = S_IDLE;
else
next_state = S_MEM_ACCESS;
default:
next_state = S_IDLE;
endcase
end
wire translation_stall = (state != S_IDLE);
assign launch_translation = (next_state == S_TRANSLATE);
assign mm_select = state == S_TRANSLATE ? MM_SELECT_TRANSLATER : MM_SELECT_ARBITER;
assign arbiter_data_valid = vm_enable ? mem_valid : translation_complete && mem_valid;
wire [31:0] physical_address = (vm_enable && translation_complete) ? translated_addr : mem_addr;
assign stall = arbiter_stall || translation_stall;
/* actual memory device */
mem simmem(.clk(clk), .reset(reset),
.addr(physical_address), .mask(mem_write_mask), .enable(mem_enable),
.cmd(mem_cmd), .load_data(mem_data), .write_data(mem_write_data), .valid(mem_valid));
endmodule
|
// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = int(1e6) + 10; const int MAX_M = 21; int n, r, c; int a[MAX_N], b[MAX_N]; int f[MAX_N][MAX_M]; char buffer[MAX_N * 6]; int main() { scanf( %d%d%d n , &n, &r, &c); c++; gets(buffer); int m = strlen(buffer); buffer[m++] = ; for (int i = 0, j = 0; i < n; i++, j++) { b[i] = j; for (a[i] = 0; j < m && buffer[j] != ; j++, a[i]++) ; } b[n] = m; for (int i = 0, j = 0, sum = 0; i < n; i++) { for (; j < n && sum + a[j] + 1 <= c; sum += a[j++] + 1) ; f[i][0] = j - i; if (i < j) { sum -= a[i] + 1; } else { j++; } } for (int j = 1; 1 << j <= r; j++) { for (int i = 0; i < n; i++) { f[i][j] = f[i][j - 1] + f[i + f[i][j - 1]][j - 1]; } } int result = 0, start = 0, l = 0; for (; 1 << l <= r; l++) ; for (int i = 0; i < n; i++) { int sum = 0, tmp = r; for (int k = l; k >= 0; k--) { if (tmp - (1 << k) >= 0) { sum += f[i + sum][k]; tmp -= 1 << k; } } if (sum > result) { result = sum; start = i; } } for (int i = 0, p = start; i < r; i++) { int sum = 0; for (; p < n && (sum + a[p] + 1) <= c; sum += a[p++] + 1) { if (sum > 0) { putchar( ); } for (int j = b[p]; j < b[p + 1] - 1; j++) { putchar(buffer[j]); } } if (sum > 0) { puts( ); } } } |
#include <bits/stdc++.h> int main() { using namespace std; ios_base::sync_with_stdio(false); cin.tie(0); int n, m, k, t; cin >> n >> m >> k >> t; vector<pair<int, int>> w; for (int i = 0, r, c; i < k; i++, w.push_back(make_pair(r, c))) cin >> r >> c; sort(w.begin(), w.end()); const char* s[] = { Carrots , Kiwis , Grapes }; for (int r, c; t--;) { cin >> r >> c; auto v = make_pair(r, c); auto vi = upper_bound(w.begin(), w.end(), v) - w.begin(); int i = (r - 1) * m + c - 1; if (vi && w[vi - 1] == v) cout << Waste << n ; else cout << s[(i - vi) % 3] << n ; } } |
module sdram_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET);
input REFERENCECLK;
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE sdram_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=100.5, Fout=100.5;
defparam sdram_pll_inst.DIVR = 4'b0000;
defparam sdram_pll_inst.DIVF = 7'b0000000;
defparam sdram_pll_inst.DIVQ = 3'b011;
defparam sdram_pll_inst.FILTER_RANGE = 3'b110;
defparam sdram_pll_inst.FEEDBACK_PATH = "DELAY";
defparam sdram_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam sdram_pll_inst.FDA_FEEDBACK = 4'd0;
defparam sdram_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam sdram_pll_inst.FDA_RELATIVE = 4'd7;
defparam sdram_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam sdram_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam sdram_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule
|
/*
* Copyright (c) Atomic Rules LLC, Auburn NH., 2009-2010
*
* Atomic Rules LLC
* 287 Chester Road
* Auburn, NH 03032
* United States of America
* Telephone
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
// arSRLFIFO.v
//
// 2009-05-10 ssiegel Creation in VHDL
// 2009-11-01 ssiegel Converted to Verilog from VHDL
// 2010-07-23 ssiegel Logic change for empty and full
module arSRLFIFO (CLK,RST_N,ENQ,DEQ,FULL_N,EMPTY_N,D_IN,D_OUT,CLR);
parameter width = 128;
parameter l2depth = 5;
parameter depth = 2**l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input[width-1:0] D_IN;
output[width-1:0] D_OUT;
reg[l2depth-1:0] pos; // head position
reg[width-1:0] dat[depth-1:0]; // SRL and output DFFs wed together
reg empty, full;
integer i;
always@(posedge CLK) begin
if(!RST_N || CLR) begin
pos <= 1'b0;
empty <= 1'b1;
full <= 1'b0;
end else begin
if (!ENQ && DEQ) pos <= pos - 1;
if ( ENQ && !DEQ) pos <= pos + 1;
if (ENQ) begin
for(i=depth-1;i>0;i=i-1) dat[i] <= dat[i-1];
dat[0] <= D_IN;
end
//was... (1-cycle "late" in updating empty after ENQ or full after DEQ)
//empty <= (pos==0 || (pos==1 && (DEQ&&!ENQ)));
//full <= (pos==(depth-1) || (pos==(depth-2) && (ENQ&&!DEQ)));
//is...
empty <= ((pos==0 && !ENQ) || (pos==1 && (DEQ&&!ENQ)));
full <= ((pos==(depth-1) && !DEQ) || (pos==(depth-2) && (ENQ&&!DEQ)));
end
end
assign FULL_N = !full;
assign EMPTY_N = !empty;
assign D_OUT = dat[pos-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long nax = 1e5 + 10; vector<long long> g[nax]; signed main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; long long n; cin >> n; long long f = 0; vector<pair<pair<long long, long long>, long long> > a(n - 2); for (long long i = 0; i < n - 2; i++) { long long x, y, z; cin >> x >> y >> z; a[i].first.first = x; a[i].first.second = y; a[i].second = z; g[x].push_back(i); g[y].push_back(i); g[z].push_back(i); } for (long long i = 1; i <= n; i++) { if (g[i].size() == 1) { f = i; break; } } vector<long long> ans; long long id = g[f][0]; long long cur1 = -1, cur2 = -1; if (a[id].first.first != f) { cur1 = a[id].first.first; if (a[id].second != f) cur2 = a[id].second; else cur2 = a[id].first.second; } else { cur1 = a[id].first.second, cur2 = a[id].second; } ans.push_back(f); ans.push_back(cur1); ans.push_back(cur2); long long cd = cur1; long long dc = cur2; set<long long> yy; yy.insert(id); while (ans.size() < n) { for (auto &i : g[cur1]) if (yy.find(i) == yy.end()) id = i; yy.insert(id); if (a[id].first.first != cur1 && a[id].first.first != cur2) ans.push_back(a[id].first.first); else if (a[id].first.second != cur1 && a[id].first.second != cur2) ans.push_back(a[id].first.second); else ans.push_back(a[id].second); cur1 = ans[ans.size() - 2]; cur2 = ans.back(); } vector<long long> ans1; id = g[f][0]; cur1 = dc; cur2 = cd; ans1.push_back(f); ans1.push_back(cur1); ans1.push_back(cur2); set<long long> xx; xx.insert(id); while (ans1.size() < n) { for (auto &i : g[cur1]) if (xx.find(i) == xx.end()) id = i; xx.insert(id); if (a[id].first.first != cur1 && a[id].first.first != cur2) ans1.push_back(a[id].first.first); else if (a[id].first.second != cur1 && a[id].first.second != cur2) ans1.push_back(a[id].first.second); else ans1.push_back(a[id].second); cur1 = ans1[ans1.size() - 2]; cur2 = ans1.back(); } set<long long> s1, s2; for (auto &i : ans) s1.insert(i); for (auto &i : ans1) s2.insert(i); if (s1.size() == n) for (auto &i : ans) cout << i << ; else for (long long i = 0; i < n; i++) cout << ans1[i] << ; } |
#include <bits/stdc++.h> using namespace std; int main() { long int n, arr[200001], ctr[200001]; set<long int> s; vector<long int> s2; list<long int> s1; memset(ctr, 0, sizeof(ctr)); cin >> n; for (long int i = 0; i < n; i++) { cin >> arr[i]; s.insert(arr[i]); ctr[arr[i]]++; } if (s.size() == n) { cout << 0 << n ; for (long int i = 0; i < n; i++) cout << arr[i] << ; return 0; } for (long int i = 1; i <= n; i++) { if (!ctr[i]) s2.push_back(i); } sort(s2.begin(), s2.end()); for (auto it : s2) { s1.push_back(it); } vector<bool> visited(n + 1, false); cout << s2.size() << n ; for (long int i = 0; i < n; i++) { if (s1.size() == 0) break; if (ctr[arr[i]] > 1) { if (s1.front() < arr[i]) { ctr[arr[i]] = ctr[arr[i]] - 1; arr[i] = s1.front(); s1.pop_front(); } else if (s1.front() > arr[i] && visited[arr[i]] == false) visited[arr[i]] = true; else if (s1.front() > arr[i] && visited[arr[i]] == true) { ctr[arr[i]] = ctr[arr[i]] - 1; arr[i] = s1.front(); s1.pop_front(); } } } for (long int i = 0; i < n; i++) cout << arr[i] << ; } |
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { for (auto v : V) os << v << ; return cout << ; } template <class T> ostream& operator<<(ostream& os, set<T> S) { for (auto s : S) os << s << ; return cout << ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << P.first << << P.second; } vector<long long> vis; vector<vector<long long>> adj; int main() { long long i, j, n, f1, f2, t, k, a, b, x1, x2, m, w, z; t = 1; while (t--) { cin >> n >> z; vector<pair<long long, long long>> v(n + 1); vis.assign(n + 1, 0); adj.assign(n + 1, {}); for (i = 1; i <= n - 1; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } long long s; queue<long long> q; vector<long long> used(n + 1); vector<long long> x(n + 1), y(n + 1); vector<long long> p(n + 1); s = z; q.push(s); used[s] = 1; p[s] = -1; while (!q.empty()) { long long v = q.front(); q.pop(); for (long long u : adj[v]) { if (!used[u]) { used[u] = 1; q.push(u); x[u] = x[v] + 1; p[u] = v; } } } used.assign(n + 1, 0); s = 1; q.push(s); used[s] = 1; p[s] = -1; while (!q.empty()) { long long v = q.front(); q.pop(); for (long long u : adj[v]) { if (!used[u]) { used[u] = 1; q.push(u); y[u] = y[v] + 1; p[u] = v; } } } long long ans = 0; for (i = 1; i <= n; i++) { if (y[i] > x[i]) { ans = max(ans, 2 * y[i]); } } cout << ans; } } |
module Arria10_tb;
reg clk; // in
reg reset; // in
// For S_AVALON
reg [6:0] addr; // in
wire [31:0] readdata; // out
reg [31:0] writedata; // in
wire io_rdata;
reg chipselect; // in
reg write; // in
reg read; // in
// For M_AXI
// AW
wire [5:0] awid; // out
wire [31:0] awuser; // out
wire [31:0] awaddr; // out
wire [7:0] awlen; // out
wire [2:0] awsize; // out
wire [1:0] awburst; // out
wire awlock; // out
wire [3:0] awcache; // out
wire [2:0] awprot; // out
wire [3:0] awqos; // out
wire awvalid; // out
reg awready; // in
// AR
wire [5:0] arid; // out
wire [31:0] aruser; // out
wire [31:0] araddr; // out
wire [7:0] arlen; // out
wire [2:0] arsize; // out
wire [1:0] arburst; // out
wire arlock; // out
wire [3:0] arcache; // out
wire [2:0] arprot; // out
wire [3:0] arqos; // out
wire arvalid; // out
reg arready; // in
// W
wire [511:0] wdata; // out
wire [63:0] wtrb; // out
wire wlast; // out
wire wvalid; // out
reg wready; // in
// R
reg [5:0] rid; // in
reg [31:0] ruser; // in
reg [511:0] rdata; // in
reg [1:0] rresp; // in
reg rlast; // in
reg rvalid; // in
wire rready; // out
// B
reg [5:0] bid; // in
reg [31:0] buser; // in
reg [1:0] bresp; // in
reg bvalid; // in
wire bready; // out
Top_DUT top0 (.clock (clk),
.reset (reset),
.io_raddr (clk),
.io_wen (write),
.io_waddr (clk),
.io_rdata (io_rdata),
.io_S_AVALON_readdata (readdata),
.io_S_AVALON_address (addr),
.io_S_AVALON_chipselect (chipselect),
.io_S_AVALON_write (write),
.io_S_AVALON_read (read),
.io_S_AVALON_writedata (writedata),
.io_M_AXI_0_AWID (awid),
.io_M_AXI_0_AWUSER (awuser),
.io_M_AXI_0_AWADDR (awaddr),
.io_M_AXI_0_AWLEN (awlen),
.io_M_AXI_0_AWSIZE (awsize),
.io_M_AXI_0_AWBURST (awburst),
.io_M_AXI_0_AWLOCK (awlock),
.io_M_AXI_0_AWCACHE (awcache),
.io_M_AXI_0_AWPROT (awprot),
.io_M_AXI_0_AWQOS (awqos),
.io_M_AXI_0_AWVALID (awvalid),
.io_M_AXI_0_AWREADY (awready),
.io_M_AXI_0_ARID (arid),
.io_M_AXI_0_ARUSER (aruser),
.io_M_AXI_0_ARADDR (araddr),
.io_M_AXI_0_ARLEN (arlen),
.io_M_AXI_0_ARSIZE (arsize),
.io_M_AXI_0_ARBURST (arburst),
.io_M_AXI_0_ARLOCK (arlock),
.io_M_AXI_0_ARCACHE (arcache),
.io_M_AXI_0_ARPROT (arprot),
.io_M_AXI_0_ARQOS (arqos),
.io_M_AXI_0_ARVALID (arvalid),
.io_M_AXI_0_ARREADY (arready),
.io_M_AXI_0_WDATA (wdata),
.io_M_AXI_0_WSTRB (wtrb),
.io_M_AXI_0_WLAST (wlast),
.io_M_AXI_0_WVALID (wvalid),
.io_M_AXI_0_WREADY (wready),
.io_M_AXI_0_RID (rid),
.io_M_AXI_0_RUSER (ruser),
.io_M_AXI_0_RDATA (rdata),
.io_M_AXI_0_RRESP (rresp),
.io_M_AXI_0_RLAST (rlast),
.io_M_AXI_0_RVALID (rvalid),
.io_M_AXI_0_RREADY (rready),
.io_M_AXI_0_BID (bid),
.io_M_AXI_0_BUSER (buser),
.io_M_AXI_0_BRESP (bresp),
.io_M_AXI_0_BVALID (bvalid),
.io_M_AXI_0_BREADY (bready));
initial
begin
$dumpfile("arria10_argInOuts.vcd");
$dumpvars(0, top0);
clk = 0;
chipselect = 1;
reset = 0;
write = 0;
addr = 0;
writedata = 0;
chipselect = 0;
write = 0;
read = 0;
awready = 0;
arready = 0;
wready = 0;
rid = 6'b0;
ruser = 32'b0;
rdata = 512'b0;
rresp = 2'b0;
rlast = 0;
rvalid = 0;
bid = 0;
buser = 32'b1;
bresp = 2'b0;
bvalid = 0;
// reset the machine
#10
reset = 1;
#10
reset = 0;
// start the flow
// set up write eanbles
awready = 1;
#10
wready = 1;
// start fringe
#20
addr = 10'h0;
writedata = 32'h1;
write = 1;
#10
write = 0;
#500
bvalid = 1;
bid = 6'b100000;
#5000
// check status
// argouts
read = 1;
#30
addr = 10'h1;
$finish;
end
always
#5 clk = !clk;
endmodule
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