text stringlengths 59 71.4k |
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`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_B_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test B (6 AM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 21 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int cnt[maxn], a[maxn], n, q; signed main() { scanf( %d , &q); while (q--) { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); cnt[i] = 0; } vector<int> res; for (int i = 1; cnt[i] < 3; i -= a[i]) if ((++cnt[i]) == 2) res.push_back(i); else if (cnt[i] == 3) break; printf( %d n , (int)res.size()); for (int u : res) printf( %d , u); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int Comb[2015][2015], Fact[2015], used[2015], a[2015]; int main() { cin.sync_with_stdio(false); int n, m = 0, k = 0; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; if (a[i] != -1) used[a[i]] = 1; } Fact[0] = 1; for (int i = 1; i <= n; ++i) { if (used[i] == 0) { ++m; if (a[i] == -1) ++k; } Fact[i] = 1LL * Fact[i - 1] * i % MOD; } for (int i = 0; i <= n; ++i) { Comb[i][0] = 1; for (int j = 1; j <= i; ++j) Comb[i][j] = (Comb[i - 1][j] + Comb[i - 1][j - 1]) % MOD; } int sol = 0; for (int i = 1; i <= k; ++i) { int x = (1LL * Comb[k][i] * Fact[m - i]) % MOD; if (i & 1) sol = (sol + x) % MOD; else sol = (0LL + sol + MOD - x) % MOD; } cout << (0LL + Fact[m] + MOD - sol) % MOD; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 10; int inf = (int)3e15; int mod = (int)1e9 + 7; int sz = 500, timer = 0; vector<int> gr[MAX]; int n, q, odd[MAX], even[MAX], h[MAX], tin[MAX], tout[MAX], mus[MAX], o[MAX]; vector<pair<int, int>> tmp; void calc(int v, int p) { tin[v] = ++timer; h[v] = h[p] + 1; for (auto u : gr[v]) { if (u != p) calc(u, v); } tout[v] = ++timer; } void dfs_rebuild(int v, int p) { odd[v] += even[p]; even[v] += odd[p]; for (auto u : gr[v]) { if (u != p) dfs_rebuild(u, v); } } void rebuild() { for (int i = 1; i <= n; i++) { even[i] = 0; odd[i] = 0; } for (int i = 0; i < tmp.size(); i++) mus[tmp[i].first] += tmp[i].second; for (int i = 1; i <= n; i++) even[i] = mus[i]; tmp.clear(); dfs_rebuild(1, 0); } void out_val(int v) { int ans = even[v] - odd[v] + o[v]; for (int i = 0; i < tmp.size(); i++) { int u = tmp[i].first; int val = tmp[i].second; if (tin[u] <= tin[v] && tout[u] >= tout[v]) { if ((h[v] - h[u]) % 2 == 1) ans -= val; else ans += val; } } cout << ans << n ; } void solve() { cin >> n >> q; for (int i = 1; i <= n; i++) { cin >> o[i]; } for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; gr[a].push_back(b); gr[b].push_back(a); } calc(1, 0); for (int i = 0; i < q; i++) { int a; cin >> a; if (a == 1) { int b, c; cin >> b >> c; tmp.push_back({b, c}); if (tmp.size() == 2000) rebuild(); } else { int c; cin >> c; out_val(c); } } } int main() { ios::sync_with_stdio(0); int q; q = 1; while (q--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long front[1000001], back[1000001], vt[1000001]; int main() { long long k, sz, ko = 0, j = 0, kq = 0; string s; cin >> k >> s; sz = s.size(); s = + s; for (long long i = 1; i <= sz + 1; i++) { front[i] = ko; if (s[i] == 0 ) ko++; else ko = 0; } ko = 0; for (long long i = sz; i >= 1; i--) { back[i] = ko; if (s[i] == 0 ) ko++; else ko = 0; } for (long long i = 1; i <= sz; i++) if (s[i] == 1 ) j++, vt[j] = i; if (k == 0) { vt[j + 1] = sz + 1; front[sz + 1] = ((s[sz] == 1 ) ? 0 : front[sz] + 1); j++; for (long long i = 1; i <= j; i++) kq += front[vt[i]] * (front[vt[i]] + 1) / 2; cout << kq; return 0; } for (long long i = 1; i <= j - k + 1; i++) kq += (front[vt[i]] + 1) * (back[vt[i + k - 1]] + 1); cout << kq; } |
#include <bits/stdc++.h> using namespace std; int l; char s[205]; int exe(int a, int b) { int u = 0, r = 0; for (int i = a; i < b; i++) { switch (s[i]) { case U : u++; break; case D : u--; break; case R : r++; break; case L : r--; break; } } return u == 0 and r == 0; } int main() { scanf( %d n , &l); gets(s); int r = 0; for (int i = 0; i < l; i++) for (int j = i + 1; j <= l; j++) r += exe(i, j); printf( %d , r); } |
#include <bits/stdc++.h> using namespace std; bool debug = false; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; long long ln, lk, lm; int gg(int x, int y) { int z = y; while (x % y != 0) { z = x % y; x = y; y = z; } return z; } map<int, vector<int>> X[2]; map<pair<pair<int, int>, pair<int, int>>, vector<int>> mp[2]; int cx[20005], cy[20005], cr[20005], ans; int dis(int i, int j) { return (cx[i] - cx[j]) * (cx[i] - cx[j]) + (cy[i] - cy[j]) * (cy[i] - cy[j]); } pair<int, int> gett(int x, int y) { if (y == 0) return {0, 1}; int tmp = gg(abs(x), abs(y)); pair<int, int> tt = {abs(y / tmp), abs(x / tmp)}; if ((y < 0 && x > 0) || (y > 0 && x < 0)) tt.second *= -1; return tt; } void cal(int i, int j) { if (cy[i] == cy[j]) { int x = cx[i] + cx[j]; if (x % 2 != 0) return; x /= 2; auto p = X[0][x]; int sz = p.size(); if (sz == 0) return; int tar = cy[i]; int c = p.end() - upper_bound(p.begin(), p.end(), tar); p = X[1][x]; c += sz - (p.end() - lower_bound(p.begin(), p.end(), tar)); ans += sz - c; return; } int x = cx[i] - cx[j], y = cy[i] - cy[j]; int zx = (cx[i] + cx[j]), zy = (cy[i] + cy[j]); pair<int, int> kk = gett(y * -1, x); pair<int, int> bb = gett(kk.second * 2, kk.second * zy - kk.first * zx); if (mp[0].find({kk, bb}) == mp[0].end()) return; auto p = mp[0][{kk, bb}]; int sz = p.size(); int tar = zx / 2; int c = p.end() - upper_bound(p.begin(), p.end(), tar); p = mp[1][{kk, bb}]; c += sz - (p.end() - lower_bound(p.begin(), p.end(), tar)); ans += sz - c; } int main() { scanf( %d%d , &n, &m); int a, b, c, d; for (int(i) = 0; (i) < (int)(n); (i)++) { scanf( %d%d%d%d , &a, &b, &c, &d); if (a == c) { X[0][a].push_back({min(b, d)}); X[1][a].push_back({max(b, d)}); } else { int x = a - c, y = b - d; pair<int, int> tt = gett(x, y); y = d * a - c * b; pair<int, int> bb = gett(x, y); mp[0][{tt, bb}].push_back(min(a, c)); mp[1][{tt, bb}].push_back(max(a, c)); } } for (int(i) = 0; (i) < (int)(2); (i)++) { for (auto &p : X[i]) sort(p.second.begin(), p.second.end()); for (auto &p : mp[i]) sort(p.second.begin(), p.second.end()); } for (int(i) = 0; (i) < (int)(m); (i)++) scanf( %d%d%d , cx + i, cy + i, cr + i); for (int(i) = 0; (i) < (int)(m); (i)++) for (int j = i + 1; j < m; j++) if (cr[i] == cr[j]) { int D = cr[i] + cr[j]; D *= D; if (dis(i, j) > D) { cal(i, j); } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int mod = 998244353; long long int hmaxii = 0; vector<long long int> values[2 * 100000 + 1]; long long int MAXN = 2 * 100000 + 1; long long int spf[2 * 100000 + 1]; long long int diff, x, y, z; long long int flag = 1; long long int price[1001][1001]; long long int dp[2000][2000]; long long int ans = 0; long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } long long int power(long long int a, long long int b) { if (b == 0) { return 1; } long long int temp = power(a, b / 2); temp = temp * temp; } void solution() { int n; cin >> n; int arr[n + 1]; int brr[n + 1]; for (int i = 1; i <= n; i++) { int x; cin >> x; arr[x] = i; } for (int i = 1; i <= n; i++) { int x; cin >> x; brr[x] = i; } int answer = 0; map<int, int> values; for (int i = 1; i <= n; i++) { values[(brr[i] - arr[i] + n) % n]++; answer = max(answer, values[(brr[i] - arr[i] + n) % n]); } cout << answer << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; t = 1; while (t--) { solution(); } return 0; } |
#include <bits/stdc++.h> int w, n, m, c[1 << 12], id[1 << 12], f[531441]; int dfs(char* g, int s, int t) { if (!*g) return c[s] * f[t]; s <<= 1; t *= 3; switch (*g++) { case A : return dfs(g, s, t + 2) + dfs(g, s | 1, t); case O : return dfs(g, s, t); case X : return dfs(g, s, t) + dfs(g, s | 1, t + 1); case a : return dfs(g, s | 1, t + 1); case o : return dfs(g, s, t + 1) + dfs(g, s | 1, t + 2); case x : return dfs(g, s, t + 1) + dfs(g, s | 1, t); } } int main() { scanf( %d%d%d , &w, &n, &m); for (int i = 1; i < 1 << w; i++) id[i] = id[i / 2] * 3 + i % 2; while (n--) { int a; scanf( %d , &a); c[a]++; f[id[a]]++; } for (int i = 0, lim = 1; i < w; i++, lim *= 3) for (int s = 0; s < 1 << w; s += 1 << i + 1) for (int t = 0, j = id[s]; t < lim; t++, j++) f[j + lim * 2] += f[j] + f[j + lim]; while (m--) { char g[15]; scanf( %s , g); printf( %d n , dfs(g, 0, 0)); } } |
// TVM mmap maps virtual DRAM into interface of SRAM.
// This allows create testcases that directly access DRAM.
// Read only memory map, one cycle read.
// Usage: create and pass instance to additional arguments of $tvm_session.
module tvm_vpi_read_mmap
#(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 8,
parameter BASE_ADDR_WIDTH = 32
)
(
input clk,
input rst,
// Read Ports
input [ADDR_WIDTH-1:0] addr, // Local offset in terms of number of units
output [DATA_WIDTH-1:0] data_out, // The data port for read
// Configure port
input [BASE_ADDR_WIDTH-1:0] mmap_addr // The base address of memory map.
);
reg [DATA_WIDTH-1:0] reg_data;
assign data_out = reg_data;
endmodule
// Write only memory map, one cycle write.
// Usage: create and pass instance to additional arguments of $tvm_session.
module tvm_vpi_write_mmap
#(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 8,
parameter BASE_ADDR_WIDTH = 32
)
(
input clk,
input rst,
// Write Ports
input [ADDR_WIDTH-1:0] addr, // Local offset in terms of number of units
input [DATA_WIDTH-1:0] data_in, // The data port for write
input en, // The enable port for write
// Configure port
input [BASE_ADDR_WIDTH-1:0] mmap_addr // The base address of memap
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<vector<int>> a(n, vector<int>(m, 0)); vector<vector<int>> b(n, vector<int>(m, 0)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } vector<pair<int, int>> ans; for (int i = 0; i < n - 1; i++) { for (int j = 0; j < m - 1; j++) { if (a[i][j] == 1 && a[i][j + 1] == 1 && a[i + 1][j + 1] == 1 && a[i + 1][j] == 1) { ans.push_back(make_pair(i, j)); b[i][j] = 1; b[i][j + 1] = 1; b[i + 1][j + 1] = 1; b[i + 1][j] = 1; } } } bool flag = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] != b[i][j]) { flag = false; i = n; break; } } } if (flag) { cout << ans.size() << endl; for (auto it = ans.begin(); it != ans.end(); it++) { cout << (*it).first + 1 << << (*it).second + 1 << endl; } } else cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const long long MAX = 1e9 + 7; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int a[n]; set<int> s; for (int i = 0; i < n; i++) s.insert(i + 1); for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i]) s.erase(a[i]); } int prev = -1; for (int i = 0; i < n; i++) { if (a[i] == 0) { auto it = s.begin(); while (it != s.end() && *it == (i + 1)) it++; if (it == s.end()) { it = s.begin(); a[i] = a[prev]; a[prev] = *it; } else { a[i] = *it; s.erase(it); prev = i; } } } for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[500 + 5]; long long ans = 1LL << 60; void cal(int x) { if (!x) return; long long sum = 0; for (int i = 1; i <= n; ++i) { if (a[i] % x == 0 || (a[i] / x >= x - 1 - a[i] % x)) sum += a[i] / x + bool(a[i] % x); else return; } ans = min(ans, sum); } int main() { int i; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); for (i = 1; i * i <= a[1]; ++i) cal(i), cal(a[1] / i), cal(a[1] / i - 1), cal(a[1] / i + 1); printf( %I64d , ans); } |
#include <bits/stdc++.h> using namespace std; int n, k, t, s; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> k; if (n < 3 * k) return cout << -1, 0; for (int i = 0; i < n; i++) if (i / k % 2 == 1) cout << (1 + i) % k + 1 << ; else cout << i % k + 1 << ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, count = 0; string s; cin >> n >> s; for (int i = 0; i < n; i++) { if (s[i] == 8 ) count++; } if (n < 11) cout << 0 << endl; else { cout << min(count, n / 11) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char **argv) { int n; unsigned long long ans; string str; cin >> n >> str; map<int, vector<int> > myMap; myMap[0].push_back(0); int cur = 0; ans = 0; for (int i = 0; i < str.size(); i++) { if (str[i] == 0 ) { } else { cur++; } if (cur >= n && myMap.count(cur - n) != 0) { ans += myMap[cur - n].size(); } myMap[cur].push_back(i); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; char s[N], t[N]; int n, m; int ch[N][26]; int lps[N]; void calcLps() { memset(lps, 0, sizeof(lps)); int i = 1; int len = 0; lps[0] = 0; while (i < m) { if (t[i + 1] == t[len + 1]) { len++; lps[i] = len; i++; } else { if (len == 0) { lps[i] = 0; i++; } else { len = lps[len - 1]; } } } } int main() { scanf( %s , s + 1); scanf( %s , t + 1); n = strlen(s + 1), m = strlen(t + 1); for (int i = 1; i <= m; i++) ch[i - 1][t[i] - a ] = i; calcLps(); for (int i = 1; i <= m; i++) { for (int j = 0; j < 26; j++) { if (!ch[i][j]) { ch[i][j] = ch[lps[i - 1]][j]; } } } vector<vector<int> > dp(n + 1, vector<int>(m + 1, -1)); dp[0][0] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j <= m; j++) { if (dp[i][j] == -1) continue; if (s[i + 1] == ? ) { for (int c = 0; c < 26; c++) { dp[i + 1][ch[j][c]] = max(dp[i + 1][ch[j][c]], dp[i][j] + (ch[j][c] == m)); } } else { int c = s[i + 1] - a ; dp[i + 1][ch[j][c]] = max(dp[i + 1][ch[j][c]], dp[i][j] + (ch[j][c] == m)); } } } int ans = 0; for (int i = 0; i <= m; i++) { ans = max(ans, dp[n][i]); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> using v2d = vector<vector<T> >; template <class T> bool uin(T &a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T &a, T b) { return a < b ? (a = b, true) : false; } mt19937 rng(chrono::system_clock::now().time_since_epoch().count()); const int maxN = 2e5 + 10; const int maxM = 5e5 + 10; int n, m, a, b; vector<int> adj[maxN]; int fa[maxN], fb[maxN]; long long ca = 0, cb = 0; void DFSa(int u) { if (u == b) { return; } fa[u] = 1; for (auto &v : adj[u]) { if (!fa[v]) { DFSa(v); } } } void DFSb(int u) { if (u == a) { return; } fb[u] = 1; for (auto &v : adj[u]) { if (!fb[v]) { DFSb(v); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int T; cin >> T; while (T--) { cin >> n >> m >> a >> b; for (int i = 1; i <= (int)(n); ++i) { adj[i].clear(); fa[i] = fb[i] = 0; } while (m--) { int u, v; cin >> u >> v; adj[u].emplace_back(v); adj[v].emplace_back(u); } DFSa(a); DFSb(b); ca = cb = 0; for (int i = 1; i <= (int)(n); ++i) { if (fa[i]) { ca += !fb[i]; } if (fb[i]) { cb += !fa[i]; } } cout << (ca - 1) * (cb - 1) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int WYMIAR = 17; int mod = MOD; struct M { int t[WYMIAR][WYMIAR]; M() { for (int i = 0; i < (WYMIAR); ++i) for (int j = 0; j < (WYMIAR); ++j) t[i][j] = 0; for (int i = 0; i < (WYMIAR); ++i) t[i][i] = 1; } }; M operator*(const M &a, const M &b) { M res; for (int i = 0; i < (WYMIAR); ++i) for (int j = 0; j < (WYMIAR); ++j) { long long acc = 0; for (int k = 0; k < (WYMIAR); ++k) acc += (long long)a.t[i][k] * b.t[k][j] % mod; res.t[i][j] = acc % mod; } return res; } M potega(M x, long long n) { M res, acc = x; for (int i = 0; i < (WYMIAR); ++i) res.t[i][i] = 1; while (n) { if (n & 1) res = res * acc; acc = acc * acc; n /= 2; } return res; } pair<int, int> rozloz(int x) { return make_pair(x / 4, x % 4); } int zabron(int a, int b) { if (a > b) return zabron(b, a); if (a == b) return 1; if (a == 0 && b == 3) return 1; if (a == 1 && b == 2) return 1; return 0; } int dobra_para(int aa, int bb) { pair<int, int> a = rozloz(aa); pair<int, int> b = rozloz(bb); if (a.second != b.first) return 0; if (zabron(b.first, b.second)) return 0; if (a.first == 1 && b.first == 0 && b.second == 2) return 0; if (a.first == 2 && b.first == 0 && b.second == 1) return 0; return 1; } int licz(int n) { if (n == 0) return 0; if (n == 1) return 4; M m; for (int i = 0; i < (16); ++i) for (int j = 0; j < (16); ++j) m.t[i][j] = dobra_para(i, j); for (int i = 0; i < (17); ++i) m.t[i][16] = 1; int stan[17]; stan[16] = 4; for (int i = 0; i < (16); ++i) { pair<int, int> p = rozloz(i); stan[i] = !zabron(p.first, p.second); } M tmp = potega(m, n - 1); int acc = 0; for (int i = 0; i < (17); ++i) acc = (acc + (long long)stan[i] * tmp.t[i][16]) % MOD; return acc % MOD; } int licz2(int n) { if (n == 0) return 0; if (n == 1) return 4; int res = licz(n); int palindromy = licz((n + 1) / 2); int niepal = ((MOD + res - palindromy) % MOD) * (long long)500000004 % MOD; return (palindromy + niepal) % MOD; } int main() { int l, r; scanf( %d %d , &l, &r); printf( %d n , (licz2(r) + MOD - licz2(l - 1)) % MOD); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_2_V
`define SKY130_FD_SC_HS__SEDFXTP_2_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_2 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_2 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_2_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 13: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 7: 0] mem_dm;
inout [ 63: 0] mem_dq;
inout [ 7: 0] mem_dqs;
inout [ 7: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 31: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 13: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 7: 0] mem_dm;
wire [ 63: 0] mem_dq;
wire [ 7: 0] mem_dqs;
wire [ 7: 0] mem_dqsn;
wire [ 24: 0] mem_local_addr;
wire [ 31: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [255: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 6: 0] mem_local_size;
wire [255: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 31: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[13 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[7 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[7 : 0]),
.mem_dqsn (mem_dqsn[7 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[24 : 22]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[21 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[31 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
#include <bits/stdc++.h> using namespace std; struct _ { int a, b, c, d, id; bool operator<(const _ &ob) const { return b < ob.b; } } a[200010]; struct __ { int val, id; bool operator<(const __ &ob) const { return val < ob.val; } }; struct event { int x, y, depth, id; }; queue<event> q; set<int> ss; multiset<__> s[200010]; _ min_[800010]; int val[200010], tx, ty, n, anss[200010], ans; int fa[200010]; void pushup(int rt) { min_[rt] = min(min_[rt << 1], min_[rt << 1 | 1]); } void update(_ tar, int l, int r, int rt) { if (l == r) { min_[rt] = tar; return; } int m = l + r >> 1; if (tar.a <= m) update(tar, l, m, rt << 1); else update(tar, m + 1, r, rt << 1 | 1); pushup(rt); } _ query(int L, int R, int l, int r, int rt) { if (L <= l && r <= R) return min_[rt]; int m = l + r >> 1; _ ans; ans.b = 1234567890; if (m >= L) ans = min(ans, query(L, R, l, m, rt << 1)); if (m < R) ans = min(ans, query(L, R, m + 1, r, rt << 1 | 1)); return ans; } void bfs(int x, int y, int depth, int id) { if (id == n) { ans = depth; anss[depth] = id; return; } _ t = query(1, x, 1, n << 1, 1); while (t.b <= y) { s[t.a].erase(s[t.a].begin()); if (s[t.a].empty()) update((_){t.a, 1234567890, 0, 0, 0}, 1, n << 1, 1); else update(a[s[t.a].begin()->id - 1], 1, n << 1, 1); q.push((event){t.c, t.d, depth + 1, t.id}); fa[t.id] = id; t = query(1, x, 1, n << 1, 1); } } void bbfs(int x, int y, int depth, int id) { q.push((event){x, y, depth, id}); event t; while (!q.empty()) { t = q.front(); q.pop(); bfs(t.x, t.y, t.depth, t.id); if (ans) return; } } int main() { memset(min_, 63, sizeof(min_)); memset(val, 63, sizeof(val)); scanf( %d , &n); int i; for (i = 0; i < n; i++) { scanf( %d%d%d%d , &a[i].a, &a[i].b, &a[i].c, &a[i].d); ss.insert(a[i].a); ss.insert(a[i].c); } set<int>::iterator it; for (it = ss.begin(), i = 1; it != ss.end(); it++, i++) { val[i] = *it; } for (i = 0; i < n; i++) { a[i].a = lower_bound(val + 1, val + 1 + (n << 1), a[i].a) - val; a[i].c = lower_bound(val + 1, val + 1 + (n << 1), a[i].c) - val; a[i].id = i + 1; } tx = a[n - 1].c; ty = a[n - 1].d; if (*ss.begin()) { printf( -1 n ); return 0; } int t; for (i = 0; i < n; i++) { t = query(a[i].a, a[i].a, 1, n << 1, 1).b; if (a[i].b < t) update(a[i], 1, n << 1, 1); s[a[i].a].insert((__){a[i].b, i + 1}); } bbfs(1, 0, 0, -1); if (!ans) printf( -1 n ); else { for (i = ans; i; i--) { anss[i - 1] = fa[anss[i]]; } printf( %d n , ans); for (i = 1; i <= ans; i++) { printf( %d , anss[i]); } printf( n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__MAJ3_FUNCTIONAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_FUNCTIONAL_PP_V |
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
module t (clk);
input clk;
reg [31:0] state; initial state=0;
wire A = state[0];
wire OE = state[1];
wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9;
wire [3:0] Z10;
wire Z11;
Test1 test1(/*AUTOINST*/
// Inouts
.Z1 (Z1),
// Inputs
.OE (OE),
.A (A));
Test2 test2(/*AUTOINST*/
// Inouts
.Z2 (Z2),
// Inputs
.OE (OE),
.A (A));
Test3 test3(/*AUTOINST*/
// Inouts
.Z3 (Z3),
// Inputs
.OE (OE),
.A (A));
Test4 test4(/*AUTOINST*/
// Outputs
.Z4 (Z4),
// Inouts
.Z5 (Z5));
Test5 test5(/*AUTOINST*/
// Inouts
.Z6 (Z6),
.Z7 (Z7),
.Z8 (Z8),
.Z9 (Z9),
// Inputs
.OE (OE));
Test6 test6(/*AUTOINST*/
// Inouts
.Z10 (Z10[3:0]),
// Inputs
.OE (OE));
Test7 test7(/*AUTOINST*/
// Outputs
.Z11 (Z11),
// Inputs
.state (state[2:0]));
always @(posedge clk) begin
state <= state + 1;
`ifdef TEST_VERBOSE
$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n",
$time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11);
`endif
if(state == 0) begin
if(Z1 !== 1'b1) $stop; // tests pullups
if(Z2 !== 1'b1) $stop;
if(Z3 !== 1'b1) $stop;
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b1) $stop;
if(Z7 !== 1'b0) $stop;
if(Z8 !== 1'b0) $stop;
if(Z9 !== 1'b1) $stop;
if(Z10 !== 4'b0001) $stop;
if(Z11 !== 1'b0) $stop;
end
else if(state == 1) begin
if(Z1 !== 1'b1) $stop; // tests pullup
if(Z2 !== 1'b1) $stop;
if(Z3 !== 1'b1) $stop;
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b1) $stop;
if(Z7 !== 1'b0) $stop;
if(Z8 !== 1'b0) $stop;
if(Z9 !== 1'b1) $stop;
if(Z10 !== 4'b0001) $stop;
if(Z11 !== 1'b1) $stop;
end
else if(state == 2) begin
if(Z1 !== 1'b0) $stop; // tests output driver low
if(Z2 !== 1'b0) $stop;
if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b0) $stop;
if(Z7 !== 1'b1) $stop;
if(Z8 !== 1'b1) $stop;
if(Z9 !== 1'b0) $stop;
if(Z10 !== 4'b0010) $stop;
//if(Z11 !== 1'bx) $stop; // Doesn't matter
end
else if(state == 3) begin
if(Z1 !== 1'b1) $stop; // tests output driver high
if(Z2 !== 1'b1) $stop;
if(Z3 !== 1'b1) $stop;
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b0) $stop;
if(Z7 !== 1'b1) $stop;
if(Z8 !== 1'b1) $stop;
if(Z9 !== 1'b0) $stop;
if(Z10 !== 4'b0010) $stop;
if(Z11 !== 1'b1) $stop;
end
else if(state == 4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
pullup(Z1);
pullup(Z2);
pullup(Z3);
pullup(Z4);
pullup(Z5);
pullup(Z6);
pulldown(Z7);
pullup(Z8);
pulldown(Z9);
pulldown pd10[3:0] (Z10);
endmodule
module Test1(input OE, input A, inout Z1);
assign Z1 = (OE) ? A : 1'bz;
endmodule
module Test2(input OE, input A, inout Z2);
assign Z2 = (OE) ? A : 1'bz;
endmodule
// mixed low-Z and tristate
module Test3(input OE, input A, inout Z3);
assign Z3 = (OE) ? A : 1'bz;
assign Z3 = 1'b1;
endmodule
// floating output and inout
`ifndef VERILATOR
// Note verilator doesn't know to make Z4 a tristate unless marked an inout
`endif
module Test4(output Z4, inout Z5);
endmodule
// AND gate tristates
module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9);
assign Z6 = (OE) ? 1'b0 : 1'bz;
assign Z7 = (OE) ? 1'b1 : 1'bz;
assign Z8 = (OE) ? 1'bz : 1'b0;
assign Z9 = (OE) ? 1'bz : 1'b1;
endmodule
// AND gate tristates
module Test6(input OE, inout [3:0] Z10);
wire [1:0] i;
Test6a a (.OE(OE), .Z({Z10[0],Z10[1]}));
Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]}));
endmodule
module Test6a(input OE, inout [1:0] Z);
assign Z = (OE) ? 2'b01 : 2'bzz;
endmodule
module Test7(input [2:0] state, output reg Z11);
always @(*) begin
casez (state)
3'b000: Z11 = 1'b0;
3'b0?1: Z11 = 1'b1;
default: Z11 = 1'bx;
endcase
end
endmodule
// This is not implemented yet
//module Test3(input OE, input A, inout Z3);
// always @(*) begin
// if(OE) begin
// Z3 = A;
// end else begin
// Z3 = 1'bz;
// end
// end
//endmodule
|
module draw_screen(
input clk,
output [X_ADDR_WIDTH - 1 : 0] x,
output [Y_ADDR_WIDTH - 1 : 0] y,
output vs,
output vs_valid,
output hs,
output hs_valid
);
localparam X_MAX = 64;
localparam Y_MAX = 32;
localparam X_ADDR_WIDTH = $clog2(X_MAX);
localparam Y_ADDR_WIDTH = $clog2(Y_MAX);
localparam X_PIX = 640;
localparam Y_PIX = 480;
localparam X_DIV = X_PIX / X_MAX;
localparam Y_DIV = Y_PIX / Y_MAX;
localparam X_DIV_WIDTH = $clog2(X_DIV);
localparam Y_DIV_WIDTH = $clog2(Y_DIV);
reg [X_DIV_WIDTH - 1 : 0] x_div_ctr = 0;
reg [Y_DIV_WIDTH - 1 : 0] y_div_ctr = 0;
reg [X_ADDR_WIDTH - 1 : 0] _x = 0;
reg [Y_ADDR_WIDTH - 1 : 0] _y = 0;
wire _hs_valid, _vs_valid;
assign vs_valid = _vs_valid;
assign hs_valid = _hs_valid;
assign x = _x;
assign y = _y;
always @ (posedge clk)
begin
if (_hs_valid)
begin
if (x_div_ctr == X_DIV - 1)
begin
x_div_ctr <= 0;
end
else
begin
x_div_ctr <= x_div_ctr + 1;
end
end
else
begin
x_div_ctr <= 0;
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
if (_vs_valid)
begin
if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= 0;
end
else if( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= y_div_ctr + 1;
end
end
else
begin
y_div_ctr <= 0;
end
end
always @ (posedge clk)
begin
if ( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
_x <= 0;
end
else if (x_div_ctr == X_DIV - 1)
begin
_x <= x + 1;
end
end
always @ (posedge clk)
begin
if ( (_y == Y_MAX - 1) & (y_div_ctr == Y_DIV - 1))
begin
_y <= 0;
end
else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))
begin
_y <= _y + 1;
end
end
vga vga(
.clk(clk),
.vs_o(vs),
.vs_valid(_vs_valid),
.hs_o(hs),
.hs_valid(_hs_valid)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_SYMBOL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1000; bool fg[55][55]; long long n, m, dy[4] = {1, 0, -1, 0}, dx[4] = {0, 1, 0, -1}; bool flag; char s[55][55]; void dfs(long long x, long long y, long long st, long long ed) { fg[x][y] = true; for (long long i = 0; i < 4; i++) { long long a = x + dx[i], b = y + dy[i]; if (a >= 1 && a <= n && b >= 1 && b <= m && s[a][b] == s[x][y] && (st != a || ed != b)) { if (fg[a][b]) { flag = true; break; } dfs(a, b, x, y); } } } signed main() { memset(fg, false, sizeof fg); cin >> n >> m; flag = false; for (long long i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { if (!fg[i][j]) { fg[i][j] = true; dfs(i, j, i, j); if (flag) break; } } if (flag) break; } if (flag) cout << Yes ; else cout << No ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_PP_BLACKBOX_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4B_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, i, X[200005], poz, nr0; long long A[200005], B[200005], val, t; int main() { ios::sync_with_stdio(false); cin >> n >> t; for (i = 1; i <= n; i++) cin >> A[i]; for (i = 1; i <= n; i++) { cin >> X[i]; if (X[i] < X[i - 1]) { cout << No n ; return 0; } if (X[i] < i) { cout << No n ; return 0; } if (X[i - 1] != X[i] && X[i - 1] != (i - 1)) { cout << No n ; return 0; } } A[n + 1] = A[n] + 1000000001; for (i = 1; i <= n; i++) B[X[i]] = A[X[i] + 1] + t - 1; val = B[n] - 1; for (i = n - 1; i >= 1; i--) { if (B[i] != 0) val = B[i]; else { if (val < A[i + 1] + t) { cout << No n ; return 0; } } B[i] = val; val--; } cout << Yes n ; for (i = 1; i <= n; i++) cout << B[i] << ; cout << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_LS__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_4_V
`define SKY130_FD_SC_LP__XOR2_4_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_4_V
|
#include <bits/stdc++.h> using namespace std; struct r { int p, t; } a; vector<r> v; bool sss(const r& i, const r& j) { if (i.p > j.p) return true; else if (i.p == j.p) return i.t < j.t; else return false; } int main() { int n, k; cin >> n >> k; map<pair<int, int>, int> mp; for (int cs = 1; cs <= n; cs++) { cin >> a.p >> a.t; mp[make_pair(a.p, a.t)]++; v.push_back(a); } sort(v.begin(), v.end(), sss); cout << mp[{v[k - 1].p, v[k - 1].t}] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_1_V
`define SKY130_FD_SC_HDLL__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_1_V
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was inspired by PR#539. We check that the calculated bit
* select of a net in a continuous assignment gets bits in the right
* order and position. The trick here is that the bits are numbered
* from MSB to LSB.
*/
module main;
reg [63:0] target0 = 64'h0040_2000_0000_0000;
reg [64:1] target1 = 64'h0040_2000_0000_0000;
reg [6:0] idx;
wire mux0 = target0[idx];
wire mux1 = target1[idx+1];
initial begin
$display( "Using constant indices:" );
$display( " %b=v[45]", target0[45] );
if (target0[45] !== 1'b1) begin
$display("FAILED -- target0[45] != 1");
$finish;
end
$display( " %b=v[54]", target0[54] );
if (target0[54] !== 1'b1) begin
$display("FAILED -- target0[54] != 1");
$finish;
end
$display( " %b=v[18]", target0[18] );
if (target0[18] !== 1'b0) begin
$display("FAILED -- target0[18] != 0");
$finish;
end
$display( " %b=v[ 9]", target0[9] );
if (target0[9] !== 1'b0) begin
$display("FAILED -- target0[ 9] != 0");
$finish;
end
$display( "Using calcuated indices:" );
for (idx = 0 ; idx < 64 ; idx = idx + 1) begin
#1 $display("target0[%2d]=%b, mux0=%b", idx, target0[idx], mux0);
$display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1);
if (target0[idx] !== mux0) begin
$display("FAILED -- target0[idx] != mux0");
$finish;
end
if (target1[idx+1] !== mux1) begin
$display("FAILED -- target1[idx+1] != mux1");
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int N = 2000000 + 10; int a[N], b[N]; int n, m; int main() { int x, y; scanf( %d%d , &n, &m); { for (int i = 0; i < m; i++) { scanf( %d%d , &x, &y); x--; y--; a[x]++; a[y]++; } for (int i = 0; i < n; i++) b[i] = n - 1 - a[i]; long long total = 0; for (int i = 0; i < n; i++) total += (long long)a[i] * b[i]; total /= 2; cout << (long long)n * (n - 1) / 2 * (n - 2) / 3 - total << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[] = {-1, 1, 0, 0, 0, 0, 0, 0}; int dy[] = {0, 0, 1, -1, 0, 0, 0, 0}; const int inf = 1000000000; const double eps = 0.000000009; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; string a[n]; for (int i = 0; i < n; i++) cin >> a[i]; long long ans = 7; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { int diff = 0; for (int k = 0; k < 6; k++) { if (a[i][k] != a[j][k]) diff++; } ans = min(ans, (long long)ceil(diff / 2.0)); } } cout << ans - 1 << endl; return 0; } |
#include <bits/stdc++.h> const int mod = 1000000007; const int inf = 1000000009; const long long INF = 1000000000000000009; const long long big = 1000000000000000; const long double eps = 1e-9; using namespace std; struct odcinek { int l, x, r, nr; }; int suma = 1; odcinek T[100005]; int D[1100005], M[1100005], S[1100005]; bool cmp(odcinek a, odcinek b) { return a.x < b.x; } void lazy(int u) { if (2 * u + 1 <= suma) { D[2 * u] += D[u]; D[2 * u + 1] += D[u]; } M[u] += D[u]; D[u] = 0; } void dodaj(int a, int b, int lo, int hi, int u, int c) { if (b <= a) return; lazy(u); if (a == lo && b == hi) { D[u] += c; return; } int mid = (lo + hi) / 2; dodaj(a, min(b, mid), lo, mid, 2 * u, c); dodaj(max(a, mid), b, mid, hi, 2 * u + 1, c); if (M[2 * u] + D[2 * u] >= M[2 * u + 1] + D[2 * u + 1]) { M[u] = M[2 * u] + D[2 * u]; S[u] = S[2 * u]; } else { M[u] = M[2 * u + 1] + D[2 * u + 1]; S[u] = S[2 * u + 1]; } } int main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(); int n; cin >> n; while (suma < 300000) suma *= 2; suma *= 2; suma--; for (int i = suma / 2 + 1; i <= suma; i++) S[i] = i - suma / 2; for (int i = suma / 2; i >= 1; i--) S[i] = S[2 * i]; for (int i = 1; i <= n; i++) { int a, b, c; cin >> a >> b >> c; T[i] = {a, b, c, i}; } sort(T + 1, T + n + 1, cmp); priority_queue<pair<int, int> > Q; int wynik = 0; pair<int, int> skad; for (int i = 1; i <= n; i++) { while (!Q.empty() && -Q.top().first < T[i].x) { pair<int, int> x = Q.top(); dodaj(T[x.second].l, T[x.second].x + 1, 1, suma / 2 + 2, 1, -1); Q.pop(); } dodaj(T[i].l, T[i].x + 1, 1, suma / 2 + 2, 1, 1); lazy(1); if (M[1] > wynik) { wynik = M[1]; skad = make_pair(S[1], T[i].x); } Q.push(make_pair(-T[i].r, i)); } cout << wynik << n ; for (int i = 1; i <= n; i++) { if (T[i].l <= skad.first && T[i].r >= skad.second && T[i].x >= skad.first && T[i].x <= skad.second) cout << T[i].nr << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int nxt[N]; map<int, vector<int>> w; int extendA[N], extendB[N], l[N], r[N]; char s[N], t[N]; int n, m, k; void pre_EKMP(char x[], int m, int nxt[]) { nxt[0] = m; int j = 0; while (j + 1 < m && x[j] == x[j + 1]) j++; nxt[1] = j; int k = 1; for (int i = 2; i < m; i++) { int p = nxt[k] + k - 1; int L = nxt[i - k]; if (i + L < p + 1) nxt[i] = L; else { j = max(0, p - i + 1); while (i + j < m && x[i + j] == x[j]) j++; nxt[i] = j; k = i; } } } void EKMP(char x[], int m, char y[], int n, int nxt[], int extend[]) { pre_EKMP(x, m, nxt); int j = 0; while (j < n && j < m && x[j] == y[j]) j++; extend[0] = j; int k = 0; for (int i = 1; i < n; i++) { int p = extend[k] + k - 1; int L = nxt[i - k]; if (i + L < p + 1) extend[i] = L; else { j = max(0, p - i + 1); while (i + j < n && j < m && y[i + j] == x[j]) j++; extend[i] = j; k = i; } } } struct node { int son[26]; int len, fail; int id; } tri[N]; int lst, L; void add(int last, int c) { static int v, u, up, up1; v = ++L; u = last; tri[v].len = tri[u].len + 1; for (; u && !tri[u].son[c]; u = tri[u].fail) tri[u].son[c] = v; if (!u) tri[v].fail = 1; else { up = tri[u].son[c]; if (tri[up].len == tri[u].len + 1) tri[v].fail = up; else { up1 = ++L; tri[up1] = tri[up]; tri[up1].len = tri[u].len + 1; tri[up].fail = tri[v].fail = up1; for (; u && tri[u].son[c] == up; u = tri[u].fail) tri[u].son[c] = up1; } } lst = v; } int rt[N]; int main() { scanf( %d %d %d , &n, &m, &k); scanf( %s , s); scanf( %s , t); lst = 1, L = 1; rt[0] = 1; for (int i = 0; i < m; i++) { add(lst, t[i] - a ); rt[i + 1] = lst; } EKMP(t, m, s, n, nxt, extendA); reverse(s, s + n); reverse(t, t + m); EKMP(t, m, s, n, nxt, extendB); reverse(extendB, extendB + n); for (int i = 0; i < n; i++) { extendB[i] = min(extendB[i], k), extendA[i] = min(extendA[i], k); if (extendA[i] == m) { int l = max(i + extendA[i] - k, 0); if (l + k + k - 1 < n) { puts( Yes ); printf( %d %d n , l + 1, l + k + 1); return 0; } l = min(n - 1, i + k - 1); if (l - k - k + 1 >= 0) { puts( Yes ); printf( %d %d n , l - k - k + 2, l - k + 2); return 0; } } } int last = 1e9; for (int i = n - 1; i >= 0; i--) { l[i] = (extendA[i] == k) * k; for (auto u : w[i + k - 1]) last = min(last, u); l[i] = max(l[i], i + k - last); if (extendA[i]) { int x = i + extendA[i] - 1; if (x >= (i + k - 1)) last = i; else w[x].push_back(i); } } w.clear(); last = -1e9; for (int i = 0; i < n; i++) { r[i] = (extendB[i] == k) * k; for (auto u : w[i - k + 1]) last = max(last, u); r[i] = max(r[i], last - (i - k)); if (extendB[i]) { int x = i - extendB[i] + 1; if (x <= i - k + 1) last = i; else w[x].push_back(i); } } for (int i = 2 * k - 1; i < n; i++) { int x = rt[l[i - 2 * k + 1]]; while (!tri[x].id) { tri[x].id = i - 2 * k + 2; x = tri[x].fail; } if (tri[rt[m - r[i]]].id) { puts( Yes ); printf( %d %d n , tri[rt[m - r[i]]].id, i - k + 2); return 0; } } printf( No ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:29 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_1_0_stub.v
// Design : ip_design_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[4:0],gpio2_io_i[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [4:0]gpio_io_i;
input [7:0]gpio2_io_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct tree { int lf; int rt; int we; } a[2000010]; int v[2000010]; int main() { int n; scanf( %d , &n); for (int j = 0; j < n - 1; j++) { scanf( %d%d , &a[j].lf, &a[j].rt); a[j].we = -1; v[a[j].lf]++; v[a[j].rt]++; } int maxi = 0, ans = -1, p = 0; for (int j = 0; j < 2000010; j++) { if (maxi < v[j]) { maxi = v[j]; ans = j; } } for (int j = 0; j < n - 1; j++) if ((a[j].lf == ans || a[j].rt == ans) && a[j].we == -1) a[j].we = p++; for (int j = 0; j < n - 1; j++) if (a[j].we == -1) a[j].we = p++; for (int j = 0; j < n - 1; j++) printf( %d n , a[j].we); return 0; } |
#include <bits/stdc++.h> bool IsCircular(const std::string &s, const int n) { bool isCircular = true; for (int i = 0; i < n; i++) { int j = (i + 1) % n; isCircular &= ((s[i] == > || s[i] == - ) && (s[j] == > || s[j] == - )); } if (isCircular) return true; isCircular = true; for (int i = 0; i < n; i++) { int j = (i + 1) % n; isCircular &= ((s[i] == < || s[i] == - ) && (s[j] == < || s[j] == - )); } return isCircular; } int main() { int t; std::cin >> t; while (t--) { int n; std::string s; std::cin >> n >> s; if (IsCircular(s, n)) std::cout << n << std::endl; else { int ans = 0; for (int i = 0; i < n; i++) { int j = (i - 1 + n) % n; if (s[i] == - || s[j] == - ) ans++; } std::cout << ans << std::endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, T, cnt, top; char s[5100][5100]; struct poi { int x, y; poi() {} poi(int x, int y) : x(x), y(y) {} void trs() { swap(x, y); x--; y = n - y; } friend bool operator<(const poi &r1, const poi &r2) { if (r1.x == r2.x) return r1.y < r2.y; return r1.x < r2.x; } friend int operator^(const poi &r1, const poi &r2) { return r1.x * r2.y - r2.x * r1.y; }; friend poi operator-(const poi &r1, const poi &r2) { return poi(r1.x - r2.x, r1.y - r2.y); }; } a[5100 << 5], st[5100 << 5]; int onleft(poi p1, poi p2, poi p3) { return ((p1 - p2) ^ (p3 - p2)) >= 0; } int main() { while (scanf( %d , &n) != EOF && n) { top = 0; cnt = 0; for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (s[i][j] > 0 && s[i][j + 1] > 0 && s[i + 1][j] > 0 && s[i + 1][j + 1] > 0 && (s[i][j] == 1 || s[i][j + 1] == 1 || s[i + 1][j] == 1 || s[i + 1][j + 1] == 1 )) a[++cnt] = poi(i, j + 1); for (int i = 1; i <= cnt; i++) a[i].trs(); sort(a + 1, a + 1 + cnt); for (int i = 1; i <= cnt; i++) { while (top >= 2 && onleft(st[top], st[top - 1], a[i])) top--; st[++top] = a[i]; } int t = top; for (int i = cnt - 1; i >= 1; i--) { while (top > t && onleft(st[top], st[top - 1], a[i])) top--; st[++top] = a[i]; } printf( %d n , top - 1); for (int i = 1; i < top; i++) printf( %d %d n , st[i].x, st[i].y); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MaxN = 111; int op[123456], val[123456], b[123456]; vector<int> x; vector<int>::iterator it; long long sum[333][5]; int k[333], sumk; map<int, int> ma; char s[5]; int main(void) { int i, j, n; int no, ni; long long res; scanf( %d , &n); x.clear(); for (i = 0; i < n; i++) { scanf( %s , s); if (s[0] == a ) op[i] = 1; else if (s[0] == d ) op[i] = 2; else op[i] = 3; if (op[i] < 3) { scanf( %d , &val[i]); x.push_back(val[i]); } } sort(x.begin(), x.end()); it = unique(x.begin(), x.end()); x.resize(it - x.begin()); for (i = 0; i < x.size(); i++) ma[x[i]] = i; memset(sum, 0, sizeof(sum)); memset(k, 0, sizeof(k)); memset(b, 0, sizeof(b)); for (i = 0; i < n; i++) { if (op[i] == 1) { b[ma[val[i]]]++; no = ma[val[i]] / 320; k[no]++; for (j = 0; j < 5; j++) sum[no][j] = 0; j = 0; for (ni = 0; ni < 320; ni++) { if (b[no * 320 + ni]) { sum[no][j] = sum[no][j] + x[no * 320 + ni]; j++; if (j == 5) j = 0; } } } else if (op[i] == 2) { b[ma[val[i]]]--; no = ma[val[i]] / 320; k[no]--; for (j = 0; j < 5; j++) sum[no][j] = 0; j = 0; for (ni = 0; ni < 320; ni++) { if (b[no * 320 + ni]) { sum[no][j] = sum[no][j] + x[no * 320 + ni]; j++; if (j == 5) j = 0; } } } else if (op[i] == 3) { res = 0; sumk = 2; for (no = 0; no < 320; no++) { res += sum[no][4 - sumk % 5]; sumk += k[no]; } printf( %I64d n , res); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<pair<int, bool> > list(n); for (int i = 0; i < n; i++) cin >> list[i].first; int tmp; for (int i = 0; i < m; i++) { cin >> tmp; list[tmp - 1].second = 1; } vector<int> v1(n - m), v2(m); int c1 = 0, c2 = 0; for (int i = 0; i < n; i++) { if (list[i].second == 1) v2[c1++] = list[i].first; else v1[c2++] = list[i].first; } sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); c1 = c2 = 0; long long cnt = 0; for (int i = 0; i < v1.size(); i++) cnt += v1[i]; if (cnt < v2.back()) { cnt += v2.back(); v2.back() = -1; } for (int i = 0; i < v2.size(); i++) { if (v2[i] != -1) cnt *= 2; } cout << cnt; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; const long long L = 1e18 + 18; int Z; struct edge { int s; int t; long long W; int ind; edge(int a, int b, long long c, int I) { s = a; t = b; W = c; ind = I; } }; struct cmp { bool operator()(edge a, edge b) { return a.W > b.W; } }; long long odl[N]; vector<edge> G[N]; vector<pair<long long, long long> > D[N]; void dfs(int v, int oj, int k); int main() { Z = 0; int n, m, k; scanf( %d%d%d , &n, &m, &k); for (long long i = 1; i <= n; i++) odl[i] = L; for (long long i = 1; i <= m; i++) { long long a, b, c; scanf( %lld%lld%lld , &a, &b, &c); G[a].push_back(edge(a, b, c, i)); G[b].push_back(edge(b, a, c, i)); } priority_queue<edge, vector<edge>, cmp> kol; odl[1] = 0; for (auto z : G[1]) kol.push(z); while (!kol.empty()) { edge X = kol.top(); kol.pop(); if (odl[X.t] < L) continue; odl[X.t] = X.W; D[X.s].push_back(make_pair(X.t, X.ind)); for (auto z : G[X.t]) { if (odl[z.t] > X.W + z.W) { kol.push(edge(z.s, z.t, z.W + X.W, z.ind)); } } } k = min(k, n - 1); printf( %d n , k); dfs(1, 1, k); if (k > 0) printf( n ); } void dfs(int v, int oj, int k) { for (auto z : D[v]) { if (z.first == oj) continue; if (Z >= k) break; printf( %lld , z.second); Z++; dfs(z.first, v, k); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_TB_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_TB_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dlatch_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_TB_V
|
#include <bits/stdc++.h> #define int long long #define mod 1000000007 #define inv 500000004 using namespace std; int ksm(int a, int b) { int ans = 1, base = a % mod; while (b) { if (b & 1) ans = (ans * base) % mod; base = (base * base) % mod; b /= 2; } return ans % mod; } struct Edge{ int to; int next; }; Edge edge[405]; int head[205], cnt = 0; void add(int u, int v) { cnt++; edge[cnt].to = v; edge[cnt].next = head[u]; head[u] = cnt; } int n, fa[205][25], f[205][205], dep[205]; void dfs(int u, int fath) { for (int i = head[u]; i; i = edge[i].next) { int v = edge[i].to; if (v == fath) continue; dep[v] = dep[u] + 1; fa[v][0] = u; for (int j = 1; j <= 22; j++) { fa[v][j] = fa[fa[v][j - 1]][j - 1]; } dfs(v, u); } } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = 22; i >= 0; i--) { if (dep[fa[x][i]] >= dep[y]) { x = fa[x][i]; } } if (x == y) return x; for (int i = 22; i >= 0; i--) { if (fa[x][i] != fa[y][i]) { x = fa[x][i]; y = fa[y][i]; } } return fa[x][0]; } signed main() { cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; add(u, v); add(v, u); } for (int i = 1; i <= n; i++) f[0][i] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { f[i][j] = ((f[i - 1][j] + f[i][j - 1]) % mod * inv % mod) % mod; } } int ans = 0; for (int rt = 1; rt <= n; rt++) { memset(dep, 0, sizeof dep); memset(fa, 0, sizeof fa); dep[rt] = 1; dfs(rt, 0); for (int i = 1; i <= n; i++) { for (int j = 1; j <= i - 1; j++) { int LCA = lca(i, j); ans = (ans % mod + f[dep[i]-dep[LCA]][dep[j]-dep[LCA]] % mod) % mod; } } } cout << (ans % mod * ksm(n, mod - 2) % mod) % mod; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[505][505], b[505][505], num[250005], c[505]; int read() { int A; bool K; char C; C = A = K = 0; while (C < 0 || C > 9 ) K |= C == - , C = getchar(); while (C > / && C < : ) A = (A << 3) + (A << 1) + (C ^ 48), C = getchar(); return (K ? -A : A); } void write(int X) { if (X < 0) putchar( - ), X = -X; if (X > 9) write(X / 10); putchar(X % 10 | 48); } int main() { int t, i, j, n, m; t = read(); while (t--) { n = read(), m = read(); for (i = 1; i <= (n); i++) for (j = 1; j <= (m); j++) a[i][j] = read(); for (j = 1; j <= (m); j++) for (i = 1; i <= (n); i++) b[j][i] = read(), num[b[j][i]] = j; for (j = 1; j <= (m); j++) c[j] = num[a[1][j]]; for (i = 1; i <= (n); i++) { for (j = 1; j <= (m); j++) write(b[c[j]][i]), putchar( ); putchar( n ); } } return 0; } |
//------------------------------------------------------------------------------
// This is GT common file for ultrascale devices
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_gt_common_wrapper
(
input qpll0_refclk, // connect to refclk1_in from example design
input qpll0_reset, // connect to reset out of TX clocking module
input qpll0_lock_detclk,
output qpll0_lock, // connect to &txpmareset done from multi GT
output qpll0_outclk, // connect to single quad input clock of GT channel
output qpll0_outrefclk, // connect to single quad input reference clock of GT channel
output qpll0_refclklost
);
// List of signals to connect to GT Common block
wire GTYE4_COMMON_GTREFCLK00;
wire GTYE4_COMMON_QPLL0RESET;
wire GTYE4_COMMON_QPLL0LOCK;
wire GTYE4_COMMON_QPLL0OUTCLK;
wire GTYE4_COMMON_QPLL0OUTREFCLK;
wire [2:0] GTYE4_COMMON_QPLL0REFCLKSEL; // select 3'b001, GTREFCLK1 is the choice as input
wire GTYE4_COMMON_QPLL0REFCLKLOST;
wire GTYE4_COMMON_QPLL0LOCKDETCLK;
// Connect only required internal signals to GT Common block
assign GTYE4_COMMON_QPLL0RESET = qpll0_reset;
assign GTYE4_COMMON_GTREFCLK00 = qpll0_refclk;
assign GTYE4_COMMON_QPLL0REFCLKSEL = 3'b001;
assign GTYE4_COMMON_QPLL0LOCKDETCLK = qpll0_lock_detclk;
assign qpll0_lock = GTYE4_COMMON_QPLL0LOCK;
assign qpll0_outclk = GTYE4_COMMON_QPLL0OUTCLK;
assign qpll0_outrefclk = GTYE4_COMMON_QPLL0OUTREFCLK;
assign qpll0_refclklost = GTYE4_COMMON_QPLL0REFCLKLOST;
// dynamic call of GT common instance is here
aurora_64b66b_25p4G_gt_gtye4_common_wrapper aurora_64b66b_25p4G_gt_gtye4_common_wrapper_i
(
.GTYE4_COMMON_BGBYPASSB(1'b1),
.GTYE4_COMMON_BGMONITORENB(1'b1),
.GTYE4_COMMON_BGPDB(1'b1),
.GTYE4_COMMON_BGRCALOVRD(5'b10000),
.GTYE4_COMMON_BGRCALOVRDENB(1'b1),
.GTYE4_COMMON_DRPADDR(16'b0000000000000000),
.GTYE4_COMMON_DRPCLK(1'b0),
.GTYE4_COMMON_DRPDI(16'b0000000000000000),
.GTYE4_COMMON_DRPDO(),
.GTYE4_COMMON_DRPEN(1'b0),
.GTYE4_COMMON_DRPRDY(),
.GTYE4_COMMON_DRPWE(1'b0),
.GTYE4_COMMON_GTGREFCLK0(1'b0),
.GTYE4_COMMON_GTGREFCLK1(1'b0),
.GTYE4_COMMON_GTNORTHREFCLK00(1'b0),
.GTYE4_COMMON_GTNORTHREFCLK01(1'b0),
.GTYE4_COMMON_GTNORTHREFCLK10(1'b0),
.GTYE4_COMMON_GTNORTHREFCLK11(1'b0),
.GTYE4_COMMON_GTREFCLK00(GTYE4_COMMON_GTREFCLK00),
.GTYE4_COMMON_GTREFCLK01(1'b0),
.GTYE4_COMMON_GTREFCLK10(1'b0),
.GTYE4_COMMON_GTREFCLK11(1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK00(1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK01(1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK10(1'b0),
.GTYE4_COMMON_GTSOUTHREFCLK11(1'b0),
.GTYE4_COMMON_PCIERATEQPLL0(3'b000),
.GTYE4_COMMON_PCIERATEQPLL1(3'b000),
.GTYE4_COMMON_PMARSVD0(8'b00000000),
.GTYE4_COMMON_PMARSVD1(8'b00000000),
.GTYE4_COMMON_PMARSVDOUT0(),
.GTYE4_COMMON_PMARSVDOUT1(),
.GTYE4_COMMON_QPLL0CLKRSVD0(1'b0),
.GTYE4_COMMON_QPLL0CLKRSVD1(1'b0),
.GTYE4_COMMON_QPLL0FBCLKLOST(),
.GTYE4_COMMON_QPLL0FBDIV(8'b00000000),
.GTYE4_COMMON_QPLL0LOCK(GTYE4_COMMON_QPLL0LOCK),
.GTYE4_COMMON_QPLL0LOCKDETCLK(GTYE4_COMMON_QPLL0LOCKDETCLK),
.GTYE4_COMMON_QPLL0LOCKEN(1'b1),
.GTYE4_COMMON_QPLL0OUTCLK(GTYE4_COMMON_QPLL0OUTCLK),
.GTYE4_COMMON_QPLL0OUTREFCLK(GTYE4_COMMON_QPLL0OUTREFCLK),
.GTYE4_COMMON_QPLL0PD(1'b0),
.GTYE4_COMMON_QPLL0REFCLKLOST(GTYE4_COMMON_QPLL0REFCLKLOST),
.GTYE4_COMMON_QPLL0REFCLKSEL(GTYE4_COMMON_QPLL0REFCLKSEL),
.GTYE4_COMMON_QPLL0RESET(GTYE4_COMMON_QPLL0RESET),
.GTYE4_COMMON_QPLL1CLKRSVD0(1'b0),
.GTYE4_COMMON_QPLL1CLKRSVD1(1'b0),
.GTYE4_COMMON_QPLL1FBCLKLOST(),
.GTYE4_COMMON_QPLL1FBDIV(8'b00000000),
.GTYE4_COMMON_QPLL1LOCK(),
.GTYE4_COMMON_QPLL1LOCKDETCLK(1'b0),
.GTYE4_COMMON_QPLL1LOCKEN(1'b0),
.GTYE4_COMMON_QPLL1OUTCLK(),
.GTYE4_COMMON_QPLL1OUTREFCLK(),
.GTYE4_COMMON_QPLL1PD(1'b1),
.GTYE4_COMMON_QPLL1REFCLKLOST(),
.GTYE4_COMMON_QPLL1REFCLKSEL(3'b001),
.GTYE4_COMMON_QPLL1RESET(1'b1),
.GTYE4_COMMON_QPLLDMONITOR0(),
.GTYE4_COMMON_QPLLDMONITOR1(),
.GTYE4_COMMON_QPLLRSVD1(8'b00000000),
.GTYE4_COMMON_QPLLRSVD2(5'b00000),
.GTYE4_COMMON_QPLLRSVD3(5'b00000),
.GTYE4_COMMON_QPLLRSVD4(8'b00000000),
.GTYE4_COMMON_RCALENB(1'b1),
.GTYE4_COMMON_REFCLKOUTMONITOR0(),
.GTYE4_COMMON_REFCLKOUTMONITOR1(),
.GTYE4_COMMON_RXRECCLK0SEL(),
.GTYE4_COMMON_RXRECCLK1SEL(),
.GTYE4_COMMON_SDM0DATA(25'b0000000000000000000000000),
.GTYE4_COMMON_SDM0FINALOUT(),
.GTYE4_COMMON_SDM0RESET(1'b0),
.GTYE4_COMMON_SDM0TESTDATA(),
.GTYE4_COMMON_SDM0TOGGLE(1'b0),
.GTYE4_COMMON_SDM0WIDTH(2'b00),
.GTYE4_COMMON_SDM1DATA(25'b0000000000000000000000000),
.GTYE4_COMMON_SDM1FINALOUT(),
.GTYE4_COMMON_SDM1RESET(1'b0),
.GTYE4_COMMON_SDM1TESTDATA(),
.GTYE4_COMMON_SDM1TOGGLE(1'b0),
.GTYE4_COMMON_SDM1WIDTH(2'b00),
.GTYE4_COMMON_UBCFGSTREAMEN(1'b0),
.GTYE4_COMMON_UBDADDR(),
.GTYE4_COMMON_UBDEN(),
.GTYE4_COMMON_UBDI(),
.GTYE4_COMMON_UBDO(16'b0000000000000000),
.GTYE4_COMMON_UBDRDY(1'b0),
.GTYE4_COMMON_UBDWE(),
.GTYE4_COMMON_UBENABLE(1'b0),
.GTYE4_COMMON_UBGPI(2'b00),
.GTYE4_COMMON_UBINTR(2'b00),
.GTYE4_COMMON_UBIOLMBRST(1'b0),
.GTYE4_COMMON_UBMBRST(1'b0),
.GTYE4_COMMON_UBMDMCAPTURE(1'b0),
.GTYE4_COMMON_UBMDMDBGRST(1'b0),
.GTYE4_COMMON_UBMDMDBGUPDATE(1'b0),
.GTYE4_COMMON_UBMDMREGEN(4'b0000),
.GTYE4_COMMON_UBMDMSHIFT(1'b0),
.GTYE4_COMMON_UBMDMSYSRST(1'b0),
.GTYE4_COMMON_UBMDMTCK(1'b0),
.GTYE4_COMMON_UBMDMTDI(1'b0),
.GTYE4_COMMON_UBMDMTDO(),
.GTYE4_COMMON_UBRSVDOUT(),
.GTYE4_COMMON_UBTXUART()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i; printf( 9 ? ?>> ? ?0 n ); for (i = 8; i >= 0; i--) printf( %d ? ?<>%d n , i, i + 1); printf( ? ?<>1 n ); for (i = 9; i >= 0; i--) printf( ?%d>>%d? n , i, i); printf( >>? n ); } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module doHist_CTRL_BUS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 4,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// 0x0 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x4 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x8 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0xc : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 4'h0,
ADDR_GIE = 4'h4,
ADDR_IER = 4'h8,
ADDR_ISR = 4'hc,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 4;
//------------------------Local signal-------------------
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done;
reg int_ap_start;
reg int_auto_restart;
reg int_gie;
reg [1:0] int_ier;
reg [1:0] int_isr;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
//------------------------Memory logic-------------------
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:11:26 05/24/2015
// Design Name: add3
// Module Name: D:/Digilent/Data/Xilinx/Projects/ISE_12_4/Binary_to_BCD_Eight_Bit/add3_tb.v
// Project Name: Binary_to_BCD_Eight_Bit
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: add3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module add3_tb;
// Inputs
reg [3:0] in;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
add3 uut (
.in(in),
.out(out)
);
initial begin
// Initialize Inputs
#10 in = 4'b0000;
#10 in = 4'b0001;
#10 in = 4'b0010;
#10 in = 4'b0011;
#10 in = 4'b0100;
#10 in = 4'b0101;
#10 in = 4'b0110;
#10 in = 4'b0111;
#10 in = 4'b1000;
#10 in = 4'b1001;
#10 in = 4'b1010;
#10 in = 4'b1011;
#10 in = 4'b1100;
#10 in = 4'b1101;
#10 in = 4'b1110;
#10 in = 4'b1111;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; set<string> st; string s; cin >> t; getchar(); while (t--) { getline(cin, s); st.insert(s); } cout << st.size() << endl; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; double h, d, c, n, mx; int hh, mm; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> hh >> mm; hh = hh * 60 + mm; cin >> h >> d >> c >> n; double nec = ceil(h / n) * c; if (hh >= 1200 && hh < 1440) return cout << setprecision(5) << fixed << nec * 0.8, 0; mm = 20 * 60; int diff = mm - hh; double nec2 = ceil((diff * d + h) / n) * c; cout << setprecision(5) << fixed << min(nec2 * 0.8, nec); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000000000 ) using namespace std; const long long int INF = 2e9; void init(vector<int> &dsu) { for (int i = 0; i < ((int)(dsu).size()); i++) { dsu[i] = i; } } int find_p(vector<int> &dsu, int id) { if (dsu[id] == id) return id; return dsu[id] = find_p(dsu, dsu[id]); } bool unite(vector<int> &dsu, int f, int s) { f = find_p(dsu, f); s = find_p(dsu, s); if (f == s) return true; dsu[f] = s; return false; } inline bool in(long double f, long double s, long double d) { return s >= f && s <= d; } bool intr(pair<long double, long double> f, pair<long double, long double> s, long double time) { if (time == INF) return true; long double a1 = -1, b1 = -1, c1 = -(a1 * f.first + b1 * f.second); long double a2 = 1, b2 = -1, c2 = -(a2 * s.first + b2 * s.second); long double x = (b1 * c2 - b2 * c1) / (a1 * b2 - b1 * a2), y = (c1 * a2 - a1 * c2) / (a1 * b2 - b1 * a2); return in(f.first - time, x, f.first + time) && in(f.second - time, y, f.second + time) && in(s.first - time, x, s.first + time) && in(s.second - time, y, s.second + time); } bool ini(long double f, long double s, long double time) { return (f - s) <= time * 2; } bool intr2(pair<long double, long double> f, pair<long double, long double> s, int q, long double time) { if (!q && !(f.first + f.second == s.first + s.second)) return false; if (q && !(f.first - f.second == s.first - s.second)) return false; if (time == INF) return true; long double x = min(f.first, s.first), x2 = max(f.first, s.first); long double y = min(f.second, s.second), y2 = max(f.second, s.second); return ini(x, x2, time) && ini(y, y2, time); } bool can(vector<pair<long double, long double> > p1, vector<pair<long double, long double> > p2, long long int time) { int n = (int)(p1).size(), m = (int)(p2).size(); for (int q = 0; q < (2); q++) { vector<int> with(n, -1); vector<int> dsu(m); init(dsu); for (int i = 0; i < (n); i++) { for (int j = 0; j < (m); j++) { if (intr(!q ? p1[i] : p2[j], !q ? p2[j] : p1[i], time)) { if (with[i] == -1) with[i] = j; else { if (unite(dsu, j, with[i])) { return true; } } } } for (int j = 0; j < (i); j++) { if (i == j) continue; if (with[j] == -1 || with[i] == -1) continue; if (intr2(p1[i], p1[j], q, time)) { if (unite(dsu, with[i], with[j])) { return true; } } } } swap(n, m); swap(p1, p2); } return false; } int main() { int n, m; cin >> n >> m; vector<pair<long double, long double> > p1(n), p2(m); bool yes = false; for (int i = 0; i < (n); i++) { int a, b; scanf( %d%d , &a, &b); p1[i] = make_pair(a, b); if (i && a + b != p1[i - 1].first + p1[i - 1].second) yes = true; } bool yes2 = false; for (int i = 0; i < (m); i++) { int a, b; scanf( %d%d , &a, &b); p2[i] = make_pair(a, b); if (i && a - b != p2[i - 1].first - p2[i - 1].second) yes2 = true; } if ((!yes || !yes2) || !can(p1, p2, INF)) { cout << Poor Sereja! ; return 0; } long long int l = 0, r = INF; while (l != r) { long long int m = (l + r) / 2; if (can(p1, p2, m)) { r = m; } else l = m + 1; } cout << l; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:27:13 02/22/2015
// Design Name:
// Module Name: MultiplyState_Y
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MultiplyState_Y(
input [32:0] aout_Special,
input [32:0] bout_Special,
input [35:0] cout_Special,
input [35:0] zout_Special,
input [31:0] sout_Special,
input [1:0] modeout_Special,
input operationout_Special,
input NatLogFlagout_Special,
input [7:0] InsTag_Special,
input clock,
input [1:0] idle_Special,
output reg [1:0] idle_Multiply,
output reg [35:0] cout_Multiply,
output reg [35:0] zout_Multiply,
output reg [31:0] sout_Multiply,
output reg [1:0] modeout_Multiply,
output reg operationout_Multiply,
output reg NatLogFlagout_Multiply,
output reg [49:0] productout_Multiply,
output reg [7:0] InsTag_Multiply
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire a_sign;
wire [7:0] a_exponent;
wire [23:0] a_mantissa;
wire b_sign;
wire [7:0] b_exponent;
wire [23:0] b_mantissa;
assign a_sign = aout_Special[32];
assign a_exponent = aout_Special[31:24] - 127;
assign a_mantissa = {aout_Special[23:0]};
assign b_sign = bout_Special[32];
assign b_exponent = bout_Special[31:24] - 127;
assign b_mantissa = {bout_Special[23:0]};
always @ (posedge clock)
begin
InsTag_Multiply <= InsTag_Special;
sout_Multiply <= sout_Special;
cout_Multiply <= cout_Special;
modeout_Multiply <= modeout_Special;
operationout_Multiply <= operationout_Special;
idle_Multiply <= idle_Special;
NatLogFlagout_Multiply <= NatLogFlagout_Special;
if (idle_Special == no_idle) begin
zout_Multiply[35] <= ~(a_sign ^ b_sign);
zout_Multiply[34:27] <= a_exponent + b_exponent + 1;
zout_Multiply[26:0] <= 0;
productout_Multiply <= a_mantissa * b_mantissa * 4;
end
else begin
zout_Multiply <= zout_Special;
end
end
endmodule
|
//MIT License
//
//Copyright (c) 2017 tvelliott
//
//Permission is hereby granted, free of charge, to any person obtaining a copy
//of this software and associated documentation files (the "Software"), to deal
//in the Software without restriction, including without limitation the rights
//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//copies of the Software, and to permit persons to whom the Software is
//furnished to do so, subject to the following conditions:
//
//The above copyright notice and this permission notice shall be included in all
//copies or substantial portions of the Software.
//
//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//SOFTWARE.
module spi_master (
input clk,
input rst,
input miso,
output mosi,
output sck,
input start,
input[7:0] data_in,
output[7:0] data_out,
output busy,
output new_data
);
localparam CLK_DIV=3;
localparam IDLE = 3'd0,
TRANSFER = 3'd1;
reg [2:0] state;
reg [7:0] data;
reg [CLK_DIV-1:0] sck_q;
assign sck = (sck_q[CLK_DIV-1] && state!=IDLE);
reg mosi;
reg [2:0] ctr;
reg [7:0] data_out;
reg new_data;
reg busy;
always @(posedge clk) begin
if (!rst) begin
ctr <= 3'b0;
sck_q <= 3'h0;
mosi <= 1'b0;
state <= IDLE;
data_out <= 8'b0;
new_data <= 1'b0;
end else begin
case (state)
IDLE: begin
sck_q <= 3'h0;
ctr <= 3'b0;
if (start == 1'b1) begin
busy<=1'b1;
new_data <= 1'b0;
data <= data_in;
state <= TRANSFER;
end
end
TRANSFER: begin
sck_q <= sck_q + 1'b1;
case(sck_q)
3'b000: begin
end
3'b001: begin
end
3'b010: begin
mosi <= data[7];
end
3'b011: begin
end
3'b100: begin
end
3'b101: begin
end
3'b110: begin
data <= {data[6:0], miso};
end
3'b111: begin
ctr <= ctr + 1'b1;
if (ctr == 3'b111) begin
data_out <= data;
busy<=1'b0;
new_data <= 1'b1;
state <= IDLE;
end
end
endcase
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
//
// Delay a signal by one clock...
//
module dly_signal #(
parameter WIDTH = 1
)(
input wire clk,
input wire [WIDTH-1:0] indata,
output reg [WIDTH-1:0] outdata
);
always @(posedge clk) outdata <= indata;
endmodule
//
// Delay & Synchronizer pipelines...
//
module pipeline_stall #(
parameter WIDTH = 1,
parameter DELAY = 1
)(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
);
reg [(WIDTH*DELAY)-1:0] dly_datain = 0;
assign dataout = dly_datain[(WIDTH*DELAY)-1 : WIDTH*(DELAY-1)];
always @ (posedge clk, posedge reset)
if (reset) dly_datain <= 0;
else dly_datain <= {dly_datain, datain};
endmodule
//
// Two back to back flop's. A full synchronizer (which XISE
// will convert into a nice shift register using a single LUT)
// to sample asynchronous signals safely.
//
module full_synchronizer #(
parameter WIDTH = 1
)(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
);
pipeline_stall #(WIDTH,2) sync (clk, reset, datain, dataout);
endmodule
//
// Create a stretched synchronized reset pulse...
//
module reset_sync (
input wire clk,
input wire hardreset,
output wire reset
);
reg [3:0] reset_reg = 4'hF;
assign reset = reset_reg[3];
always @ (posedge clk, posedge hardreset)
if (hardreset) reset_reg <= 4'hF;
else reset_reg <= {reset_reg,1'b0};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_LP_V
`define SKY130_FD_SC_LP__SDFSTP_LP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_lp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O2111AI_PP_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int sgn(double x) { return (x > 1e-8) - (x < -1e-8); } int count_bit(int x) { return x == 0 ? 0 : count_bit(x >> 1) + (x & 1); } template <class T> inline void ckmin(T& a, const T b) { if (b < a) a = b; } template <class T> inline void ckmax(T& a, const T b) { if (b > a) a = b; } const int MAXN = 100000 + 10; struct binary_indexed_tree { int a[MAXN], val[MAXN]; void clear() { memset(a, 0, sizeof(a)); memset(val, 0, sizeof(val)); } void update(int x, int y) { val[x] += y; for (; x < MAXN; x += ((x) & (-(x)))) { a[x] += y; } } int getsum(int x) { int ret = 0; for (; x; x -= ((x) & (-(x)))) { ret += a[x]; } return ret; } int getsum(int l, int r) { int ret = 0; while (l <= r) { if (r - ((r) & (-(r))) + 1 >= l) { ret += a[r]; r -= ((r) & (-(r))); } else { ret += val[r--]; } } return ret; } } bit; void filp_left(int& l, int& r, int len) { for (int i = (1); i <= (len); ++i) { bit.update(l + len + len - i, bit.val[l + i - 1]); } l += len; } void filp_right(int& l, int& r, int len) { for (int i = (1); i <= (len); ++i) { bit.update(r - len - len + i, bit.val[r - i + 1]); } r -= len; } int main() { int n, q; while (scanf( %d%d , &n, &q) != EOF) { bit.clear(); for (int i = 0; i < (n); ++i) { bit.update(i + 1, 1); } int off = 0; int l = 1, r = n; bool rev = false; for (int i = 0; i < (q); ++i) { int optype, flen, cl, cr; scanf( %d , &optype); if (optype == 1) { scanf( %d , &flen); int clen = r - l + 1; if (2 * flen > clen) { if (!rev) { filp_right(l, r, clen - flen); } else { filp_left(l, r, clen - flen); } rev = !rev; } else { if (!rev) { filp_left(l, r, flen); } else { filp_right(l, r, flen); } } } else { scanf( %d%d , &cl, &cr); int ret; if (!rev) { ret = bit.getsum(l + cl, l + cr - 1); } else { ret = bit.getsum(r - cr + 1, r - cl); } printf( %d n , ret); } } } return 0; } |
`include "defines.v"
`timescale 1ns/1ps
module tb(
);
wire injrd;
reg clk, rst;
wire `control_w port0_co, port1_co, port2_co, port3_co, port4_co;
wire `data_w port0_do, port1_do, port2_do, port3_do, port4_do;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(28'h0), .port0_co(port0_co),
.port1_ci(28'h0), .port1_co(port1_co),
.port2_ci(28'h0), .port2_co(port2_co),
.port3_ci(28'h0), .port3_co(port3_co),
.port4_ci(28'h0), .port4_co(port4_co),
.port0_di(128'h0), .port0_do(port0_do),
.port1_di(128'h0), .port1_do(port1_do),
.port2_di(128'h0), .port2_do(port2_do),
.port3_di(128'h0), .port3_do(port3_do),
.port4_di(128'h0), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
$set_toggle_region(tb.r);
$toggle_start();
clk = 0;
rst = 0;
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
$toggle_stop();
$toggle_report("./bless_backward_0.saif", 1.0e-9, "tb.r");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 3, M = 1e6 + 3, O = 2e6 + 3; int c[N], a[N], b[N], id[O], tp; bool f[N]; struct P { int f, sz; } d[M], st[O]; int gf(int x) { return d[x].f == x ? x : gf(d[x].f); } void mg(int x, int y) { int u = gf(x), v = gf(y); if (d[u].sz > d[v].sz) swap(u, v); st[++tp] = d[u], id[tp] = u, st[++tp] = d[v], id[tp] = v; d[v].sz += d[u].sz, d[u].f = v; } map<pair<int, int>, int> mp; vector<int> vc[N]; int main() { int n, m, k, i, j, l, u, v, w, uu, vv, tt, uuu, vvv; long long ans = 0; scanf( %d%d%d , &n, &m, &k); for (i = 1; i <= n; ++i) scanf( %d , c + i); for (i = 1; i <= n * 2; ++i) d[i].f = i, d[i].sz = 1; for (i = 1; i <= m; ++i) scanf( %d%d , a + i, b + i); for (i = 1; i <= m; ++i) if (c[a[i]] == c[b[i]]) { u = gf(a[i]), v = gf(b[i]); if (u == v) f[c[a[i]]] = 1; else mg(a[i], b[i] + n), mg(b[i], a[i] + n); } for (i = 1, j = 0; i <= m; ++i) if (c[a[i]] != c[b[i]] && !f[c[a[i]]] && !f[c[b[i]]]) { u = c[a[i]], v = c[b[i]]; if (u > v) swap(u, v); l = mp[{u, v}]; if (!l) l = mp[{u, v}] = ++j; vc[l].push_back(i); } for (auto o : mp) { u = o.first.first, v = o.first.second, w = o.second, tt = tp; for (int o2 : vc[w]) { uu = a[o2], vv = b[o2], uuu = gf(uu), vvv = gf(vv); if (uuu == vvv) { --ans; break; } mg(uu, vv + n), mg(uu + n, vv); } while (tp != tt) d[id[tp]] = st[tp], --tp; } for (i = 1, j = 0; i <= k; ++i) if (!f[i]) ++j; ans += j * 1ll * (j - 1) / 2; printf( %lld , ans); return 0; } |
//#############################################################################
//# Purpose: A toy accelerator example ("put code here") #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see below) #
//#############################################################################
`include "accelerator_regmap.vh"
module accelerator (/*AUTOARG*/
// Outputs
m_wr_access, m_wr_packet, m_rd_access, m_rd_packet, m_rr_wait,
s_wr_wait, s_rd_wait, s_rr_access, s_rr_packet,
// Inputs
clk, nreset, m_wr_wait, m_rd_wait, m_rr_access, m_rr_packet,
s_wr_access, s_wr_packet, s_rd_access, s_rd_packet, s_rr_wait
);
//##############################################################
//#INTERFACE
//###############################################################
parameter AW = 32; //native address width
parameter PW = 2 * AW + 40; //packet width
parameter ID = 12'h810; //epiphany ID for elink (ie addr[31:20])
parameter RFAW = 6;
//clock and reset
input clk; // single system clock for master/slave FIFOs
input nreset; // reset for axi facing logic (active low)
//############################
// ACCELERATOR GENERATERD
//############################
//Master Write (from RX)
output m_wr_access;
output [PW-1:0] m_wr_packet;
input m_wr_wait;
//Master Read Request
output m_rd_access;
output [PW-1:0] m_rd_packet;
input m_rd_wait;
//Master Read Response
input m_rr_access;
input [PW-1:0] m_rr_packet;
output m_rr_wait;
//############################
// HOST GENERATERD
//############################
//Slave Write
input s_wr_access;
input [PW-1:0] s_wr_packet;
output s_wr_wait;
//Slave Read Request
input s_rd_access;
input [PW-1:0] s_rd_packet;
output s_rd_wait;
//Slave Read Response
output s_rr_access;
output [PW-1:0] s_rr_packet;
input s_rr_wait;
//##############################################################
//#BODY
//###############################################################
wire access_in;
wire [PW-1:0] packet_in;
reg [31:0] data_out;
reg s_rr_access;
wire [31:0] result;
reg [31:0] reg_input0;
reg [31:0] reg_input1;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From s_wr of packet2emesh.v
wire [AW-1:0] data_in; // From s_wr of packet2emesh.v
wire [1:0] datamode_in; // From s_wr of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From s_wr of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From s_wr of packet2emesh.v
wire write_in; // From s_wr of packet2emesh.v
// End of automatics
//############################
// INPUTS
//############################
emesh_mux #(.N(2),.AW(AW))
mux2(// Outputs
.wait_out ({s_rd_wait, s_wr_wait}),
.access_out (access_in),
.packet_out (packet_in[PW-1:0]),
// Inputs
.access_in ({s_rd_access, s_wr_access}),
.packet_in ({s_rd_packet[PW-1:0],s_wr_packet[PW-1:0]}),
.wait_in (s_rr_wait)
);
packet2emesh #(.AW(AW))
s_wr(/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0])); // Templated // Templated)
//#####################
//#CONTROL LOGIC
//#####################
//registers
assign acc_match = access_in &
(dstaddr_in[31:20]==ID) &
(dstaddr_in[19:16]==`EGROUP_MMR);
assign input0_match = acc_match & (dstaddr_in[RFAW+1:2]==`REG_INPUT0);
assign input1_match = acc_match & (dstaddr_in[RFAW+1:2]==`REG_INPUT1);
assign output_match = acc_match & (dstaddr_in[RFAW+1:2]==`REG_OUTPUT);
assign input0_write = input0_match & write_in;
assign input1_write = input1_match & write_in;
assign output_read = output_match & ~write_in;
//input0
always @ (posedge clk)
if(input0_write)
reg_input0[31:0] <= data_in[31:0];
//input1
always @ (posedge clk)
if(input1_write)
reg_input1[31:0] <= data_in[31:0];
//#############################
//#ACCELERATOR
//#############################
//(PUT CODE HERE!)
assign result[31:0] = reg_input0[31:0] + reg_input1[31:0];
//#########################
//#READBACK WITH PIPELINE
//#########################
always @ (posedge clk)
if(~nreset)
s_rr_access <= 'b0;
else
s_rr_access <= output_read;
always @ (posedge clk)
data_out[31:0] <= result[31:0];
emesh2packet #(.AW(32))
p2e (.packet_out (s_rr_packet[PW-1:0]),
.write_out (1'b1),
.datamode_out (2'b10),
.ctrlmode_out (5'b0),
.dstaddr_out (32'b0),
.srcaddr_out (32'b0),
/*AUTOINST*/
// Inputs
.data_out (data_out[AW-1:0]));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl" )
// End:
//////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software")//
// to deal in the Software without restriction, including without limitation//
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT//
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
//////////////////////////////////////////////////////////////////////////////
|
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
`define NS_DBG_SRC_ADDR 3
`define NS_DBG_INIT_CK 14
`define NS_DBG_INIT_DAT 5
`define NS_DBG_INIT_RED 15
`define NS_DBG_MAX_SRC_CASE 4
module pakin_io
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
PSZ=`NS_PACKET_SIZE,
FSZ=`NS_PACKIN_FSZ,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src_clk,
input wire snk_clk,
input wire reset,
// SRC_0
`NS_DECLARE_PAKOUT_CHNL(o0),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk_clk, reset, i0)
localparam TOT_PKS = ((`NS_FULL_MSG_SZ / PSZ) + 1);
localparam FIFO_IDX_WIDTH = ((($clog2(FSZ)-1) >= 0)?($clog2(FSZ)-1):(0));
localparam PACKETS_IDX_WIDTH = ((($clog2(TOT_PKS)-1) >= 0)?($clog2(TOT_PKS)-1):(0));
reg [0:0] rg_rdy = `NS_OFF;
reg [3:0] cnt_0 = `NS_DBG_INIT_DAT;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [ASZ-1:0] ro0_src = `NS_DBG_SRC_ADDR;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [DSZ-1:0] ro0_dat = `NS_DBG_INIT_DAT;
reg [RSZ-1:0] ro0_red = `NS_DBG_INIT_RED;
//reg [0:0] ro0_req = `NS_OFF;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
r1 (ro0_src, ro0_dst, ro0_dat, ro0_redun);
`NS_DECLARE_FIFO(bf0)
reg [0:0] added_hd = `NS_OFF;
`NS_DECLARE_REG_PAKOUT(rgo0)
reg [0:0] rgo0_req = `NS_OFF;
// SNK
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp0)
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_back_dat = 15;
//reg [ASZ-1:0] inp0_back_dst = 0;
reg [0:0] inp0_err = `NS_OFF;
reg [0:0] inp0_err_0 = `NS_OFF;
reg [0:0] inp0_err_1 = `NS_OFF;
reg [0:0] inp0_err_2 = `NS_OFF;
reg [0:0] inp0_err_3 = `NS_OFF;
`NS_DECLARE_REG_DBG(rg_dbg)
//SRC_0
always @(posedge src_clk)
begin
if(reset) begin
rg_rdy <= `NS_OFF;
end
if(! reset && ! rg_rdy) begin
rg_rdy <= `NS_ON;
`NS_PACKOUT_INIT(rgo0)
rgo0_req <= `NS_OFF;
`NS_FIFO_INIT(bf0);
added_hd <= `NS_OFF;
end
if(! reset && rg_rdy) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
`NS_FIFO_TRY_ADD_HEAD(bf0, ro0, added_hd);
end
if(added_hd) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
added_hd <= `NS_OFF;
end
`NS_PACKOUT_TRY_INC(rgo0, bf0, o0_ckd_ack, rgo0_req)
end
end
//SNK_0
always @(posedge snk_clk)
begin
if(i0_ckd_req && (! inp0_ack)) begin
if(! has_inp0) begin
has_inp0 <= `NS_ON;
`NS_MOV_REG_MSG(inp0, i0)
end
else
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err) begin
if(inp0_src != `NS_DBG_SRC_ADDR) begin
inp0_err <= `NS_ON;
inp0_err_0 <= `NS_ON;
end
else
if(inp0_red != inp0_redun) begin
inp0_err <= `NS_ON;
inp0_err_1 <= `NS_ON;
end
//else
if((inp0_back_dat <= 14) && ((inp0_back_dat + 1) != inp0_dat)) begin
inp0_err <= `NS_ON;
inp0_err_2 <= `NS_ON;
//rg_dbg_disp0 <= inp0_back_dat[3:0];
//rg_dbg_disp1 <= inp0_dat[3:0];
end
else
begin
inp0_back_dat <= inp0_dat;
end
end
end
if(inp0_done_cks) begin
rg_dbg_disp0 <= inp0_dat[3:0];
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
inp0_ack <= `NS_ON;
end
end
else
if((! i0_ckd_req) && inp0_ack) begin
inp0_ack <= `NS_OFF;
end
end
//SRC_0
assign o0_pakio = rgo0_pakio;
assign o0_req_out = rgo0_req;
//SNK_0
assign i0_ack_out = inp0_ack;
assign dbg_leds[0:0] = inp0_err_0;
assign dbg_leds[1:1] = inp0_err_1;
assign dbg_leds[2:2] = inp0_err_2;
assign dbg_leds[3:3] = inp0_err;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* RTL Simulation Control Device
*/
`include "common.vh"
`include "ocp_const.vh"
/*
* Simulation control device
* Registers:
* 0x00 - control register;
* Bits:
* [31] - used to indicate error condition on model termination;
* [30:1] - ignored;
* [0] - stop simulation if 1 written.
* 0x04 - response delay register;
* Bits:
* [31:8] - ignored;
* [7:0] - cycles to delay.
* 0x08 - bus error register (access generates bus error response).
*/
module sim_control(
clk,
nrst,
/* OCP interface */
i_MAddr,
i_MCmd,
i_MData,
i_MByteEn,
o_SCmdAccept,
o_SData,
o_SResp
);
/* Register offsets */
localparam [`ADDR_WIDTH-1:0] CTRLREG = 32'h000; /* Control register */
localparam [`ADDR_WIDTH-1:0] DELYREG = 32'h004; /* Delay register */
localparam [`ADDR_WIDTH-1:0] BUSEREG = 32'h008; /* Bus error register */
/* Inputs and outputs */
input wire clk;
input wire nrst;
input wire [`ADDR_WIDTH-1:0] i_MAddr;
input wire [2:0] i_MCmd;
input wire [`DATA_WIDTH-1:0] i_MData;
input wire [`BEN_WIDTH-1:0] i_MByteEn;
output wire o_SCmdAccept;
output reg [`DATA_WIDTH-1:0] o_SData;
output reg [1:0] o_SResp;
reg [`DATA_WIDTH-1:0] last_value; /* Last written value */
reg [7:0] delay; /* Amount of cycles to delay */
reg [7:0] counter; /* Current delay counter */
assign o_SCmdAccept = (i_MCmd == `OCP_CMD_IDLE || counter == 8'h00) ? 1'b1 : 1'b0;
/* Ctl device logic */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_SData <= { (`DATA_WIDTH){1'b0} };
o_SResp <= `OCP_RESP_NULL;
delay <= 8'h00;
counter <= 8'h00;
last_value <= 32'h00;
end
else if(counter == 8'h00)
begin
case(i_MCmd)
`OCP_CMD_WRITE: begin
if(i_MAddr == CTRLREG)
begin
last_value <= i_MData;
if(i_MData[0])
begin
if(i_MData[31])
$display("SIMULATION TERMINATED WITH ERRORS!");
else
$display("SIMULATION SUCCESSFULLY TERMINATED!");
$finish;
end
end
else if(i_MAddr == DELYREG)
begin
delay <= i_MData[7:0];
end
/* Respond if no delay needed or bus error response needed */
if(i_MAddr == BUSEREG)
o_SResp <= `OCP_RESP_ERR;
else if(delay == 8'h00)
o_SResp <= `OCP_RESP_DVA;
else
counter <= delay;
end
`OCP_CMD_READ: begin
if(i_MAddr == CTRLREG)
begin
o_SData <= last_value;
end
else if(i_MAddr == DELYREG)
begin
o_SData <= { 24'h0, delay };
end
else
o_SData <= 32'hDEADDEAD;
/* Respond if no delay needed or bus error response needed */
if(i_MAddr == BUSEREG)
o_SResp <= `OCP_RESP_ERR;
else if(delay == 8'h00)
o_SResp <= `OCP_RESP_DVA;
else
counter <= delay;
end
default: begin
o_SData <= { (`DATA_WIDTH){1'b0} };
o_SResp <= `OCP_RESP_NULL;
end
endcase
end
else if(counter == 8'h01)
begin
o_SResp <= `OCP_RESP_DVA;
counter <= 8'h00;
end
else
counter <= counter - 1;
end
endmodule /* sim_control */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_2_V
`define SKY130_FD_SC_HS__A2BB2OI_2_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_BLACKBOX_V
`define SKY130_FD_SC_MS__SEDFXTP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_V |
// simple ram
// 2014,
module tg68_ram #(
parameter MS = 512
)(
input wire clk,
input wire tg68_as,
input wire [ 32-1:0] tg68_adr,
input wire tg68_rw,
input wire tg68_lds,
input wire tg68_uds,
input wire [ 16-1:0] tg68_dat_out,
output wire [ 16-1:0] tg68_dat_in,
output wire tg68_dtack
);
// memory
reg [8-1:0] mem0 [0:MS-1];
reg [8-1:0] mem1 [0:MS-1];
// internal signals
reg [16-1:0] mem_do = 0;
reg trn = 1;
reg ack = 1;
// clear on start
integer i;
initial begin
for (i=0; i<MS; i=i+1) begin
mem1[i] = 0;
mem0[i] = 0;
end
end
// read
always @ (posedge clk) begin
if (!tg68_as && tg68_rw) mem_do <= #1 {mem1[tg68_adr[31:1]], mem0[tg68_adr[31:1]]};
end
//write
always @ (posedge clk) begin
if (!tg68_as && !tg68_rw) begin
if (!tg68_uds) mem1[tg68_adr[31:1]] <= #1 tg68_dat_out[15:8];
if (!tg68_lds) mem0[tg68_adr[31:1]] <= #1 tg68_dat_out[7:0];
end
end
// acknowledge
always @ (posedge clk) begin
trn <= #1 tg68_as;
ack <= #1 trn;
end
// outputs
assign tg68_dat_in = mem_do;
assign tg68_dtack = ack || tg68_as; // TODO
// load task
task load;
input [1024*8-1:0] file;
reg [16-1:0] memory[0:MS-1];
reg [16-1:0] dat;
integer i;
begin
$readmemh(file, memory);
for (i=0; i<MS; i=i+1) begin
dat = memory[i];
mem1[i] = dat[15:8];
mem0[i] = dat[7:0];
end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned long long const Mod = 1000000007; unsigned long long sq_sum(unsigned long long n) { unsigned long long ret = n; ret = (n * (n + 1)); ret /= 2; if (ret % 3 == 0) { return ((ret / 3) % Mod * (2 * n + 1)) % Mod; } else { return ((ret % Mod) * ((2 * n + 1) / 3)) % Mod; } } unsigned long long check(unsigned long long a, unsigned long long b) { unsigned long long ret = 0; for (unsigned long long x = b; x < 100000; ++x) { if (x % b != 0) { unsigned long long t1 = x / b; unsigned long long t2 = x % b; if (t1 % t2 == 0 && t1 / t2 <= a) ret += x; } } return ret; } int main() { unsigned long long a, b; while (cin >> a >> b) { cout << (((a * (a + 1) / 2) % Mod * b + a) % Mod * ((b * (b - 1) / 2) % Mod)) % Mod << endl; } } |
#include <bits/stdc++.h> using namespace std; struct E { int ad, id, ne; } e[100010 * 4]; int n, m, q, u[100010], v[100010], w[100010], h1[100010], h2[100010], de[100010], fa[100010], f[100010], p0[100010], p1[100010]; bool o[100010]; void add(int* he, int x, int y, int d) { static int t = 0; ++t, e[t].ne = he[x], he[x] = t, e[t].ad = y, e[t].id = d; } int ff(int* f, int x) { if (f[x] == x) return x; else return f[x] = ff(f, f[x]); } void ff1(int x) { p0[x] = p1[x] = x; for (int p = h1[x]; p; p = e[p].ne) { int y = e[p].ad; if (!de[y]) { fa[y] = x, de[y] = de[x] + 1, ff1(y), p1[y] = x; if (ff(p0, x) == ff(p0, y)) o[x] |= o[y]; } else if (de[y] + 1 < de[x]) { int z = ff(p0, x); while (de[z] > de[y] + 1) p0[z] = fa[z], z = ff(p0, z); if ((de[x] - de[y]) % 2 == 0) o[x] = 1; } } for (int p = h2[x]; p; p = e[p].ne) if (de[e[p].ad]) w[e[p].id] = ff(p1, e[p].ad); } void ff2(int x) { if (o[ff(p0, x)]) f[x]++; for (int i = h1[x]; i; i = e[i].ne) { int y = e[i].ad; if (de[y] == de[x] + 1) { if (ff(p0, x) == ff(p0, y)) o[y] |= o[x]; f[y] = f[x], ff2(y); } } } bool chk(int u, int v, int w) { if (ff(p1, u) != ff(p1, v)) return 0; if ((de[u] - de[v]) % 2) return 1; return f[u] + f[v] - f[w] * 2 > 0; } int main() { scanf( %d%d , &n, &m); for (int i = 1, x, y; i <= m; i++) scanf( %d%d , &x, &y), add(h1, x, y, i), add(h1, y, x, i); scanf( %d , &q); for (int i = 1; i <= q; i++) scanf( %d%d , u + i, v + i), add(h2, u[i], v[i], i), add(h2, v[i], u[i], i); for (int i = 1; i <= n; i++) if (!de[i]) de[i] = 1, ff1(i), ff2(i); for (int i = 1; i <= q; i++) puts(chk(u[i], v[i], w[i]) ? Yes : No ); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 100; int ans; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; int a[1111] = {}, cnt[1111] = {}; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { if (cnt[i] == 0) { ans++; for (int j = i + 1; j <= n; j++) { if (a[j] % a[i] == 0) { cnt[j] = 1; } } } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, n; scanf( %d , &n); for (i = 1; i <= 4; ++i) { int m1, m2, a, b; scanf( %d%d , &a, &b); m1 = min(a, b); scanf( %d%d , &a, &b); m2 = min(a, b); if (m1 + m2 <= n) { printf( %d %d %d n , i, m1, n - m1); return 0; } } puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; string char_to_str(char c) { string tem(1, c); return tem; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <class T> T rand() { return uniform_int_distribution<T>()(rng); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long n, k; cin >> n >> k; vector<long long> v; vector<long long> v2; for (long long i = 1; i * i <= n; ++i) { if (n % i == 0) { v.push_back(i); v2.push_back(n / i); } } reverse(v2.begin(), v2.end()); for (auto r : v2) v.push_back(r); long long f = 0; for (long long i = v.size() - 1; i >= 0; --i) { long long t = n / v[i]; if (k > 100000000 || (k * (k + 1)) / 2 > t) { continue; } for (long long j = 1; j < k; ++j) { t -= j; cout << j * v[i] << ; } cout << t * v[i]; return 0; } cout << -1 ; } |
#include <bits/stdc++.h> using namespace std; ifstream fin( input.txt ); ofstream fout( output.txt ); const long long mod = 1000000000 + 7; const int maxn = 500 + 10; const int inf = 1000000000; int n, m, par[maxn][maxn][2], dist[maxn][maxn][2]; vector<int> v[maxn], e[2]; queue<pair<pair<int, int>, int> > q; bool mark[maxn][maxn][2]; void pr(int x, int y, int o) { if (par[x][y][o] == -1) return; if (o == 0) { pr(x, par[x][y][o], 1 - o); e[o].push_back(y); } else { pr(par[x][y][o], y, 1 - o); e[o].push_back(x); } } int main() { for (int i = 0; i < maxn; i++) for (int j = 0; j < maxn; j++) dist[i][j][0] = dist[i][j][1] = inf; cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } q.push(make_pair(make_pair(1, n), 0)); par[1][n][0] = -1; mark[1][n][0] = 1; dist[1][n][0] = 0; while (!q.empty()) { int x = q.front().first.first; int y = q.front().first.second; int o = q.front().second; q.pop(); if (o == 0) { for (int i = 0; i < v[x].size(); i++) if (!mark[v[x][i]][y][1]) { q.push(make_pair(make_pair(v[x][i], y), 1)); dist[v[x][i]][y][1] = dist[x][y][0] + 1; mark[v[x][i]][y][1] = 1; par[v[x][i]][y][1] = x; } } else { for (int i = 0; i < v[y].size(); i++) if (v[y][i] != x && !mark[x][v[y][i]][0]) { q.push(make_pair(make_pair(x, v[y][i]), 0)); dist[x][v[y][i]][0] = dist[x][y][1] + 1; mark[x][v[y][i]][0] = 1; par[x][v[y][i]][0] = y; } } } if (dist[n][1][0] != inf) { cout << dist[n][1][0] / 2 << endl; pr(n, 1, 0); cout << 1 << ; for (int i = 0; i < e[1].size(); i++) cout << e[1][i] << ; cout << endl << n << ; for (int i = 0; i < e[0].size(); i++) cout << e[0][i] << ; cout << endl; } else cout << -1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_0_V
`define SKY130_FD_SC_LP__A2111OI_0_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_0 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S6S_FUNCTIONAL_PP_V |
//---------------------------------------------------------------------//
// Name: vex.v
// Author: Chris Wynnyk
// Date: 2/21/2008
// Purpose: This module creates and retrieves the exercise price, Vex.
//---------------------------------------------------------------------//
module vex(
clk_slow,
clk_fast,
nrst,
start_s1,
start_s2,
log_lambda_up,
log_lambda_down,
K_over_S,
chan0,
chan1,
chan2,
chan3,
done_s1,
vexaddr
);
input clk_slow;
input clk_fast;
input nrst;
input start_s1;
input start_s2;
input [12:0] vexaddr;
input [63:0] log_lambda_up;
input [63:0] log_lambda_down;
input [63:0] K_over_S;
output [63:0] chan0;
output [63:0] chan1;
output [63:0] chan2;
output [63:0] chan3;
output done_s1;
//---------------------------------------------------------------------//
// Wires
//---------------------------------------------------------------------//
wire [63:0] v_ex;
wire [9:0] wraddr;
wire [7:0] wren;
wire [63:0] m0_out;
wire [63:0] m1_out;
wire [63:0] m2_out;
wire [63:0] m3_out;
wire [63:0] m4_out;
wire [63:0] m5_out;
wire [63:0] m6_out;
wire [63:0] m7_out;
wire [63:0] bank0_out;
wire [63:0] bank1_out;
wire [63:0] bank2_out;
wire [63:0] bank3_out;
wire [63:0] chan0;
wire [63:0] chan1;
wire [63:0] chan2;
wire [63:0] chan3;
wire [9:0] bank0_addr;
wire [9:0] bank1_addr;
wire [9:0] bank2_addr;
wire [9:0] bank3_addr;
wire odd;
wire [1:0]sel;
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
addrdecode addrdecode_inst(
.clk(clk_fast),
.addr_in(vexaddr),
.bank0_addr(bank0_addr),
.bank1_addr(bank1_addr),
.bank2_addr(bank2_addr),
.bank3_addr(bank3_addr),
.sel(sel),
.odd(odd)
);
compute_vex compute_vex_inst(
.clk(clk_slow),
.nrst(nrst),
.start(start_s1),
.log_lambda_up(log_lambda_up),
.log_lambda_down(log_lambda_down),
.K_over_S(K_over_S),
.v_ex(v_ex),
.wraddr(wraddr),
.wren(wren),
.done(done_s1)
);
mem_1k m0 (
.data(v_ex),
.rdaddress(bank0_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[0]),
.q(m0_out)
);
mem_1k m1 (
.data(v_ex),
.rdaddress(bank0_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[1]),
.q(m1_out)
);
mem_1k m2 (
.data(v_ex),
.rdaddress(bank1_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[2]),
.q(m2_out)
);
mem_1k m3 (
.data(v_ex),
.rdaddress(bank1_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[3]),
.q(m3_out)
);
mem_1k m4 (
.data(v_ex),
.rdaddress(bank2_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[4]),
.q(m4_out)
);
mem_1k m5 (
.data(v_ex),
.rdaddress(bank2_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[5]),
.q(m5_out)
);
mem_1k m6 (
.data(v_ex),
.rdaddress(bank3_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[6]),
.q(m6_out)
);
mem_1k m7 (
.data(v_ex),
.rdaddress(bank3_addr),
.rdclock(clk_fast),
.wraddress(wraddr),
.wrclock(clk_slow),
.wren(wren[7]),
.q(m7_out)
);
//---------------------------------------------------------------------//
// Control Logic
//---------------------------------------------------------------------//
// Mux for even vs. odd memory bank.
assign bank0_out = odd ? m1_out : m0_out;
assign bank1_out = odd ? m3_out : m2_out;
assign bank2_out = odd ? m5_out : m4_out;
assign bank3_out = odd ? m7_out : m6_out;
// Mux for bank shifting based on select state.
assign chan0 = sel[1]?(sel[0]?bank3_out:bank2_out):(sel[0]?bank1_out:bank0_out);
assign chan1 = sel[1]?(sel[0]?bank0_out:bank3_out):(sel[0]?bank2_out:bank1_out);
assign chan2 = sel[1]?(sel[0]?bank1_out:bank0_out):(sel[0]?bank3_out:bank2_out);
assign chan3 = sel[1]?(sel[0]?bank2_out:bank1_out):(sel[0]?bank0_out:bank3_out);
endmodule |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate case/endcase w/ label list - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
case (val1 & val2 )
3'b000,3'b001: result = 0;
3'b101: result = 1 ;
3'b110,3'b111,3'b100: result = 2;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
#1 if(result !==0)
begin
$display("FAILED case 3.8B - case (expr) lab1: ");
error = 1;
end
val1 = 3'b101;
val2 = 3'b111;
#1 if(result !==1)
begin
$display("FAILED case 3.8B - case (expr) lab2: ");
error = 1;
end
val1 = 3'b110;
#1 if(result !==2)
begin
$display("FAILED case 3.8B - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t;
// verilator lint_off PINMISSING
`ifdef T_GEN_MISSING_BAD
foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module
`elsif T_GEN_MISSING
foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0
`else
`error "Bad Test"
`endif
endmodule
module foobar
#( parameter
FOO_START = 0,
FOO_NUM = 2,
FOO_TYPE = 1
)
(
input wire[FOO_NUM-1:0] foo,
output wire[FOO_NUM-1:0] bar);
generate
begin: g
genvar j;
for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1)
begin: foo_inst;
if (FOO_TYPE == 0)
begin: foo_0
// instatiate foo0
foo0 i_foo(.x(foo[j]), .y(bar[j]));
end
if (FOO_TYPE == 1)
begin: foo_1
// instatiate foo1
foo_not_needed i_foo(.x(foo[j]), .y(bar[j]));
end
end
end
endgenerate
endmodule
module foo0(input wire x, output wire y);
assign y = ~x;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT_IBUFDISABLE.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 04/04/11 - CR 604808 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT_IBUFDISABLE (O, OB, I, IB, IBUFDISABLE);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
input I;
input IB;
input IBUFDISABLE;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
wire out_val;
wire out_b_val;
initial begin
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE")) begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE.", SIM_DEVICE);
$finish;
end
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT_IBUFDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB or DQS_BIAS_BINARY) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (I === 1'bx || IB === 1'bx)
o_out <= 1'bx;
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? o_out : (IBUFDISABLE == 1)? out_val : 1'bx;
assign OB = (IBUFDISABLE == 0)? ~o_out : (IBUFDISABLE == 1)? out_b_val : 1'bx;
end
"FALSE" : begin
assign O = o_out;
assign OB = ~o_out;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_1_V
`define SKY130_FD_SC_HDLL__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:16:07 11/07/2013
// Design Name:
// Module Name: ram_memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ram_memory # (parameter N=4, M=4) /*Parameter permite la parametrización del modulo, donde se asigna el nombre y su respectivo valor, que en nuestro caso es N =4.*/
(input clk,
input we, /*especificaamos el nombre de las entradas y salidas respectivamente con las cuales se van a trabajar.*/
input [N-1:0] adr,
input [M-1:0] din,
output [N-1:0]dout);
reg [M-1:0] mem [N-1:0]; /*reg se usa para modelar las memorias, donde se accede mediante un determinado bit, con esta variable se declara el tamaño de cada memoria*/
always @ (posedge clk) /* Always se ejecuta continuamente a modo de bucle, y está continuamente ejecutándose. Que se activa cuando detecta un flanco de subida (posedge)*/
if (we) mem [adr] <= din;
assign dout = mem[adr];
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 1; char a[N], b[N]; vector<int> g[26]; bool vis[26][26]; vector<pair<char, char> > sol; char go[26]; int main() { scanf( %s%s , a, b); int n = strlen(a); for (int i = 0; i < n; ++i) { if (a[i] == b[i]) continue; int x = a[i] - a ; int y = b[i] - a ; g[x].push_back(y); g[y].push_back(x); } bool can = true; for (int i = 0; i < 26 && can; ++i) { sort(g[i].begin(), g[i].end()); g[i].resize(unique(g[i].begin(), g[i].end()) - g[i].begin()); can &= g[i].size() <= 1; } if (!can) { puts( -1 ); return 0; } for (int i = 0; i < 26; ++i) if (!g[i].empty()) { int x = min(i, g[i][0]), y = max(i, g[i][0]); if (vis[x][y]) continue; go[x] = y + a ; go[y] = x + a ; vis[x][y] = true; sol.push_back(make_pair(x + a , y + a )); } else go[i] = i + a ; for (int i = 0; i < 26 && can; ++i) { can &= go[a[i] - a ] == b[i]; can &= go[b[i] - a ] == a[i]; } if (!can) { puts( -1 ); return 0; } printf( %d n , (int)sol.size()); for (int i = 0; i < (int)sol.size(); ++i) printf( %c %c n , sol[i].first, sol[i].second); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); int64_t a, b; cin >> a; a = a * (a + 1) / 2; while (cin >> b) a -= b; cout << a; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
`ifndef verilator // Hacky array subscripting
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
assign bitout = (^ onebit) ^ (^ allbits);
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_atan2_s5 (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_atan2_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.b(datab),
.q(sub_wire0));
endmodule
|
#include <bits/stdc++.h> using namespace std; int Array[100005], Left[100005]; int Right[100005]; int main() { int N, i; scanf( %d , &N); for (i = 1; i <= N; ++i) { scanf( %d , Array + i); Left[i] = min(Left[i - 1] + 1, Array[i]); } for (i = N; i >= 1; --i) Right[i] = min(Right[i + 1] + 1, Array[i]); int Ans = 0; for (i = 1; i <= N; ++i) Ans = max(Ans, min(Left[i], Right[i])); printf( %d n , Ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s50 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s50.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_2_V
|
#include <bits/stdc++.h> using namespace std; bool myfunction(int i, int j) { return (i < j); } void solve() { long long n; cin >> n; set<long long> st; long long a; for (long long int i = 0; i < n; i++) { cin >> a; st.insert(a); } if (st.size() > 3) { cout << -1; return; } else if (st.size() == 1) { cout << 0; return; } else if (st.size() == 2) { auto it = st.begin(); int a = *it; it++; int b = *it; if ((a + b) % 2 == 0) { cout << (b - a) / 2; } else cout << (b - a); return; } else { auto it = st.begin(); int a = *it; it++; int b = *it; it++; int c = *it; if (c - b != b - a) { cout << -1 ; return; } else cout << b - a; return; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int test = 1; while (test--) solve(); return 0; } |
/*---------------------------------------------------------------------------------------------------------------------
-- Author: Peter Hasza,
--
-- Create Date: 04/02/2017
-- Module Name: CLK_gen_simple
-- Project Name: AXI_SPI_IF
-- Description:
-- Simple Clock generator module. The purpose of a less resourceful implementation of the SPI interface
-- SCLK generation in case of modulo 2 clock ratio.
-- The use case clock ratios:
-- - clk_div 2,4,8
-- But the module can handle any modulo 2 clock ratios.
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2017.apr.2 | hp3265 || Initial version
--
-----------------------------------------------------------------------------------------------------------------------*/
module CLK_gen_simple(
input clk_i,
output clk_o
);
parameter g_clk_div;
localparam c_counter_width = clog2(g_clk_div);
reg [c_counter_width:0] clk_cnt_y = 0;
always @(posedge clk_i)
clk_cnt_y <= clk_cnt_y + 1;
assign clk_o = clk_cnt_y[c_counter_width];
end module; |
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Vectors.Vector.
Local Open Scope vector_scope.
Import VectorNotations.
Require Import ExtLib.Structures.Monads.
Import MonadNotation.
Local Open Scope monad_scope.
Require Import Cava.Core.Core.
Require Import Cava.Lib.Combinators.
(**** IMPORTANT: if you make changes to the API of these definitions, or add new
ones, make sure you update the reference at docs/reference.md! ****)
Section WithCava.
Context `{semantics:Cava}.
(* Constant signals. *)
(* This component always returns the value 0. *)
Definition zero : signal Bit := constant false.
(* This component always returns the value 1. *)
Definition one : signal Bit := constant true.
Definition all {n} (v : signal (Vec Bit n)) : cava (signal Bit) :=
match n with
| 0 => ret one
| _ => tree and2 v
end.
Definition any {n} (v : signal (Vec Bit n)) : cava (signal Bit) :=
match n with
| 0 => ret zero
| _ => tree or2 v
end.
Fixpoint eqb {t : SignalType} : signal t * signal t -> cava (signal Bit) :=
match t as t0 return signal t0 * signal t0 -> cava (signal Bit) with
| Void => fun _ => ret one
| Bit => xnor2
| ExternalType s => fun _ => ret one
| Vec a n => fun '(x,y) =>
eq_results <- Vec.map2 eqb (x, y) ;;
all eq_results
end.
End WithCava.
|
#include <bits/stdc++.h> using namespace std; int main(void) { cin.tie(0); ios_base::sync_with_stdio(false); int a, ta, b, tb; string t; cin >> a >> ta >> b >> tb >> t; int p = 600 * (t[0] - 0 ) + 60 * (t[1] - 0 ) + 10 * (t[3] - 0 ) + t[4] - 0 ; int q = p + ta; int ans = 0, i; for (i = 300; i < 1440; i += b) { if (p * (ta + tb) < ta * tb + p * tb + i * ta && ta * tb + p * tb + i * ta < q * (ta + tb)) ans++; } cout << ans << endl; return 0; } |
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`include "globalDefines.vh"
/*function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction*/
module logicBlock(
stateA, maskA, stateB, maskB, constant, opBMux,
prevConfigInvalid,
resultMux, out,
configInvalid
);
input [31:0] stateA;
input [31:0] stateB;
input [31:0] maskA; // Configuration
input [31:0] maskB; // Configuration
input [31:0] constant; // Configuration
input opBMux; // Configuration, 1 = stateB, 0 = constant
input [2:0] resultMux; // Configuration, 0 = ==, 1 = !=, 2 = >,
// 3 = >=, 4 = <, 5 = <=
input prevConfigInvalid;
output out;
output configInvalid;
reg out;
wire configInvalid;
// Create both operands
wire [31:0] maskedA = stateA & maskA;
wire [31:0] operandA = maskedA;
wire [31:0] maskedB = stateB & maskB;
wire [31:0] operandB = opBMux ? maskedB : constant;
// Perform the operations in parallel
wire eq = operandA == operandB;
wire neq = operandA != operandB;
wire gt = operandA > operandB;
wire gteq = operandA >= operandB;
wire lt = operandA < operandB;
wire lteq = operandA `LTEQ operandB;
// Check for valid configurations
assign configInvalid = prevConfigInvalid | (resultMux > 3'd5);
// Send the correct result to the output
always @(resultMux or eq or neq or gt or gteq or lt or lteq) begin
case(resultMux)
0: out = eq;
1: out = neq;
2: out = gt;
3: out = gteq;
4: out = lt;
5: out = lteq;
default : out = 0;
endcase
end
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
//Date : Tue Sep 19 00:27:34 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target zynq_design_1_wrapper.bd
//Design : zynq_design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module zynq_design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
leds_8bits_tri_o);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [7:0]leds_8bits_tri_o;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [7:0]leds_8bits_tri_o;
zynq_design_1 zynq_design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.leds_8bits_tri_o(leds_8bits_tri_o));
endmodule
|
module psdos ( input Rx,
input CLKOUT,
//output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
//reg [1:0] k;
reg init;
//reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
//Rx_error=0;
DONE=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
//DONE=0;
//Rx_error=0;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
//=======
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
//if((!(j%2)&&(regis[8]))||((j%2)&&(!regis[8])))
//begin
//Rx_error=0;
regis0={regis[7:0]};
DONE=1;
//end
//else
//begin
// Rx_error=1;
// regis0=0;
// DONE=0;
//end
j=0;
i<=0;
init<=0;
end
end
assign DATA=regis0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_V |
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