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// Top-Level Verilog Module
// Only include pins the design is actually using. Make sure that the pin is
// given the correct direction: input vs. output vs. inout
`include "cscv2.v"
`include "txuart.v"
`ifdef VERILATOR
module ULX3S(i_clk, o_setup, o_uart_tx);
input wire i_clk;
output wire [31:0] o_setup; // Tell UART co-sim about clocks per baud
output wire o_uart_tx; // UART transmit signal line
`else
module ULX3S (input clk_25mhz, output ftdi_rxd, output [7:0] led);
wire i_clk;
assign i_clk= clk_25mhz;
assign ftdi_rxd= o_uart_tx; // Wire it up to real ULX3S line
assign led= PCval;
`endif
// The 25MHz clock is used to increment a counter.
// We tap one of the bits to provide a lower frequency
// clock, csc_clk. Internally the csc_clk is used for the
// RAM component and the CPU itself runs at half this clock.
reg [15:0] counter=0;
always @(posedge i_clk) counter <= counter + 1;
wire csc_clk;
assign csc_clk= counter[12];
/* verilator lint_off UNUSED */
// CPU wires: not all used
wire TX;
wire [3:0] Aval;
wire [3:0] Bval;
wire [7:0] PCval;
wire RAMwrite;
wire [7:0] address;
wire [3:0] Flagsval;
wire [2:0] ALUop;
wire [3:0] ALUresult;
wire [3:0] RAMresult;
wire [3:0] databus;
wire Aload;
wire Bload;
wire Asel;
/* verilator lint_on UNUSED */
// CPU
cscv2 CPU(csc_clk, TX, Aval, Bval, PCval, RAMwrite,
address, Flagsval, ALUop, ALUresult, RAMresult,
databus, Aload, Bload, Asel);
// UART input and output
wire [7:0] tx_data;
assign tx_data[7:4]= Aval;
assign tx_data[3:0]= Bval;
wire o_uart_tx;
/* verilator lint_off UNUSED */
wire tx_busy; // Unused
/* verilator lint_on UNUSED */
// The TX line goes low, but it stays low for many 25MHz clock
// cycles as the CPU is running at a lower clock rate. We need
// tx_stb to go high for one clock cycle only.
reg oldTX= 1;
reg tx_stb= 0;
always @(posedge i_clk) begin
// Strobe tx_stb only when TX drops, on one 25MHz cycle only
if ((TX==0) && (oldTX==1))
tx_stb <= 1;
else
tx_stb <= 0;
// Save TX for the next cycle
oldTX <= TX;
end
// UART
parameter CLOCK_RATE_HZ = 25_000_000; // 25MHz clock
parameter BAUD_RATE = 9_600; // 9600 baud
parameter CLOCKS_PER_BAUD = CLOCK_RATE_HZ/BAUD_RATE;
`ifdef VERILATOR
assign o_setup = CLOCKS_PER_BAUD;
`endif
txuart #(CLOCKS_PER_BAUD[23:0])
transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
endmodule
|
module contadorprueba (
input [7:0] cantidad,
input entrada,
input ENABLE,
input clk,
input reset,
output [3:0] an,
output [6:0] seg,
output pulse
);
wire [7:0] count;
wire [3:0] centenas;
wire [3:0] decenas;
wire [3:0] unidades;
wire [1:0] mostrar;
wire [3:0] digito;
cantidadecho cantidadecho0 (
.cantidad ( cantidad ),
.entrada ( entrada ),
.CLKOUT ( CLKOUT ),
.reset ( reset ),
.ECHO ( ECHO )
);
contador contador0 (
.count ( count ),
.pulse ( pulse ),
.calculate ( calculate ),
.ECHO ( ECHO ),
.ENABLE ( ENABLE ),
.CLKOUT ( CLKOUT ),
.reset ( reset )
);
divisorfrec divisorfrec0 (
.clk ( clk ),
.CLKOUT ( CLKOUT )
);
anteconmutador anteconmutador0 (
.clk ( clk ),
.count ( count ),
.calculate ( calculate ),
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.De ( De ),
.U ( U )
);
conmutacion conmutacion0 (
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.De ( De ),
.U ( U ),
.CLKOUTseg ( CLKOUTseg ),
.mostrar ( mostrar ),
.digito ( digito )
);
display display0 (
.mostrar ( mostrar ),
.digito ( digito ),
.an ( an ),
.seg ( seg )
);
divisorfrecdisp divisorfrecdisp0 (
.clk ( clk ),
.CLKOUTseg ( CLKOUTseg )
);
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef pair<int,int> pi; const int maxn=1e5+7; double dp[maxn][10]; int pre[maxn][10]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n,d; cin>>n>>d; vector<int> a(n+1); for(int i=0;i<maxn;i++) for(int j=0;j<10;j++) dp[i][j]=-1e9; dp[0][1]=0; for(int i=1;i<=n;i++) { cin>>a[i]; double val=log(a[i]); for(int j=0;j<10;j++) { int nxt=j*a[i]%10; if(dp[i-1][j]>dp[i][j]) { dp[i][j]=dp[i-1][j]; pre[i][j]=j; } if(dp[i-1][j]+val>dp[i][nxt]) { dp[i][nxt]=dp[i-1][j]+val; pre[i][nxt]=j; } } } if(dp[n][d]<0) { cout<<-1<< n ; return 0; } vector<int> ans; int cur=d; for(int i=n;i>=1;i--) { int cc=a[i]%10; if((pre[i][cur]*cc)%10==cur) { cur=pre[i][cur]; ans.push_back(a[i]); } } if(ans.size()==0) { cout<<-1<< n ; return 0; } cout<<ans.size()<< n ; for(int i=0;i<ans.size();i++) cout<<ans[i]<< n [i+1==ans.size()]; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_join_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 8'd0;
reg input_0_axis_tvalid = 1'b0;
reg input_0_axis_tlast = 1'b0;
reg input_0_axis_tuser = 1'b0;
reg [7:0] input_1_axis_tdata = 8'd0;
reg input_1_axis_tvalid = 1'b0;
reg input_1_axis_tlast = 1'b0;
reg input_1_axis_tuser = 1'b0;
reg [7:0] input_2_axis_tdata = 8'd0;
reg input_2_axis_tvalid = 1'b0;
reg input_2_axis_tlast = 1'b0;
reg input_2_axis_tuser = 1'b0;
reg [7:0] input_3_axis_tdata = 8'd0;
reg input_3_axis_tvalid = 1'b0;
reg input_3_axis_tlast = 1'b0;
reg input_3_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
tag);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_frame_join_4.lxt");
$dumpvars(0, test_axis_frame_join_4);
end
axis_frame_join_4 #(
.TAG_ENABLE(1)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// config
.tag(tag),
// status
.busy(busy)
);
endmodule
|
`include "defines.v"
`include "HRnode.v"
`timescale 1ns/1ps
/*module HRnode
#(parameter addr = 4'b0010)
(
input `control_w port0_i,
input `control_w port1_i,
input `control_w port0_local_i,
input `control_w port1_local_i,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_o,
output `control_w port1_o,
output `control_w port0_local_o,
output `control_w port1_local_o
);*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
HRnode r(
.clk(clk),
.rst(rst),
.port0_i(flit0c), .port0_o(port0_co),
.port1_i(flit1c), .port1_o(port1_co),
.port0_local_i(flitl0), .port0_local_o(portl0_co),
.port1_local_i(flitl1), .port1_local_o(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef0123456789abcdef1851;
flit1c = 144'h0;
flitl1 = 144'h0;
flitl0 = 144'h0;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Input buffer map
module \$__inpad (input I, output O);
twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end*/ else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
#include <bits/stdc++.h> int main() { long n, m; scanf( %ld %ld , &n, &m); std::vector<long> a(n + 2, 0); a[n + 1] = m; for (long p = 1; p <= n; p++) { scanf( %ld , &a[p]); } long orig(0), off(0), mx(0); for (long p = n; p >= 0; p--) { if (p % 2) { off += a[p + 1] - a[p]; } else { orig += a[p + 1] - a[p]; } mx = (mx > off - orig) ? mx : (off - orig); } printf( %ld n , orig + (mx > 0) * (mx - 1)); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [31:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [`SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
assign p_out = data;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
begin
if (rst)
data <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
data[95:88] <= #Tp p_in[31:24];
if (byte_sel[2])
data[87:80] <= #Tp p_in[23:16];
if (byte_sel[1])
data[79:72] <= #Tp p_in[15:8];
if (byte_sel[0])
data[71:64] <= #Tp p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
data[127:120] <= #Tp p_in[31:24];
if (byte_sel[2])
data[119:112] <= #Tp p_in[23:16];
if (byte_sel[1])
data[111:104] <= #Tp p_in[15:8];
if (byte_sel[0])
data[103:96] <= #Tp p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[3])
data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long C[1200][1200]; int main() { for (int i = 0; i < 1200; i++) C[i][i] = C[i][0] = 1LL; for (int i = 2; i < 1200; i++) for (int j = 1; j < i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % 1000000007; long long k, n, m; scanf( %I64d%I64d%I64d , &n, &m, &k); if (n - 1 < 2 * k || m - 1 < 2 * k) printf( 0 n ); else printf( %I64d n , C[n - 1][2 * k] * C[m - 1][2 * k] % 1000000007); return 0; } |
#include <bits/stdc++.h> using namespace std; void read() { return; } void wrt() { cout << (string) n ; } void wrt(long long t) { cout << t; } void wrt(int t) { cout << t; } void wrt(char t) { cout << t; } void wrt(string t) { cout << t; } void wrt(double t) { cout << t; } template <class T> void wrt(set<T> v); template <class T> void wrt(vector<T> v); template <class T> void wrt(multiset<T> v); template <class T, class V> void wrt(map<T, V> v); template <class T, class V> void wrt(pair<T, V> p); template <size_t T> void wrt(const char (&a)[T]) { string s = a; wrt(s); wrt(); } template <class T> void wrt(set<T> v) { for (T i : v) { wrt(i); wrt( ); } wrt(); } template <class T> void wrt(vector<T> v) { for (T i : v) { wrt(i); wrt( ); } wrt(); } template <class T> void wrt(multiset<T> v) { for (T i : v) { wrt(i); wrt( ); } wrt(); } template <class T, class V> void wrt(map<T, V> v) { for (auto i : v) { wrt(i); wrt( ); } wrt(); } template <class T, class V> void wrt(pair<T, V> p) { wrt(p.first); wrt( ); wrt(p.second); wrt(); } template <class T, class... V> void wrt(T x, V... args) { (wrt(x), wrt( ), wrt(args...)); } template <class T, class... V> void read(T &x, V &...args) { ((cin >> x), read(args...)); } template <class T> void readArr(T &arr, int x, int y) { for (int i = (int)x; i < (int)y; ++i) cin >> arr[i]; } const int N = 1e6; const int INF = INT_MAX; const int MOD = 1e9 + 7; int countBits(long long number) { return (int)log2(number) + 1; } long long getSum(vector<int> a) { return accumulate(a.begin(), a.end(), 0ll); } long long gcd(long long a, long long b) { return (b == 0) ? (a) : (gcd(b, a %= b)); } long long lcd(long long a, long long b) { return (a * b) / gcd(a, b); } long long add(long long x, long long y) { return (x + y) % MOD; } long long sub(long long x, long long y) { return (x - y + MOD) % MOD; } long long mul(long long x, long long y) { return (x * 1ll * y) % MOD; } long long inv(long long p, long long q) { long long expo = MOD - 2; while (expo) { if (expo & 1) p = mul(p, q); q = mul(q, q), expo >>= 1; } return p; } long long power(long long x, long long y) { if (y == 0) return 1; else if (y % 2 == 0) { long long tmp = power(x, y / 2); return mul(tmp, tmp); } else return mul(x, power(x, y - 1)); } void solveTestCase() { int n, m; read(n, m); vector<int> f(n * m + 1, -1); vector<vector<int> > r(n, vector<int>(m)), c(m, vector<int>(n)); for (int i = (int)0; i < (int)n; ++i) readArr(r[i], 0, m); for (int i = (int)0; i < (int)m; ++i) readArr(c[i], 0, n); for (int i = (int)0; i < (int)n; ++i) { f[c[0][i]] = i; } vector<vector<int> > ans(n, vector<int>(m)); for (int i = (int)0; i < (int)n; ++i) { int done = -1; for (int j = (int)0; j < (int)m; ++j) { if (f[r[i][j]] != -1) { done = f[r[i][j]]; break; } } for (int j = (int)0; j < (int)m; ++j) { ans[done][j] = r[i][j]; } } wrt(ans); } int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); ; int t = 1; cin >> t; while (t--) solveTestCase(); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_GTE2.v
// \ \ / \ Timestamp : Tue Jun 1 14:31:01 PDT 2010
// \___\/\___\
//
// Revision:
// 06/01/10 - Initial version.
// 09/29/11 - 627247 -- Changed CLKSWING_CFG from blooean to bits
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module IBUFDS_GTE2 (
O,
ODIV2,
CEB,
I,
IB
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter [1:0] CLKSWING_CFG = 2'b11;
output O;
output ODIV2;
input CEB;
input I;
input IB;
// Output signals
reg O_out=0, ODIV2_out=0;
// Counters and Flags
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
// Attribute settings
// Other signals
reg clkcm_cfg_int = 0;
reg clkrcv_trst_int = 0;
reg clkswing_cfg_int = 0;
reg [1:0] CLKSWING_CFG_BINARY;
reg notifier;
initial begin
allEqual = 0;
//-------------------------------------------------
//----- CLKCM_CFG check
//-------------------------------------------------
case (CLKCM_CFG)
"FALSE" : clkcm_cfg_int <= 1'b0;
"TRUE" : clkcm_cfg_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKCM_CFG on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKCM_CFG);
$finish;
end
endcase // case(CLKCM_CFG)
//-------------------------------------------------
//----- CLKRCV_TRST check
//-------------------------------------------------
case (CLKRCV_TRST)
"FALSE" : clkrcv_trst_int <= 1'b0;
"TRUE" : clkrcv_trst_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKRCV_TRST on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKRCV_TRST);
$finish;
end
endcase // case(CLKRCV_TRST)
//-------------------------------------------------
//----- CLKSWING_CFG check
//-------------------------------------------------
if ((CLKSWING_CFG >= 2'b00) && (CLKSWING_CFG <= 2'b11))
CLKSWING_CFG_BINARY = CLKSWING_CFG;
else begin
$display("Attribute Syntax Error : The Attribute CLKSWING_CFG on IBUFDS_GTE2 instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", CLKSWING_CFG);
$finish;
end
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(posedge I)
ODIV2_out <= allEqual;
// =====================
// Generate O
// =====================
always @(I)
O_out <= I & ~CEB;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$period (posedge IB, 0:0:0, notifier);
( I => O) = (100:100:100, 100:100:100);
( I => ODIV2) = (100:100:100, 100:100:100);
( IB => O) = (100:100:100, 100:100:100);
( IB => ODIV2) = (100:100:100, 100:100:100);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int N = 3005; const int mod = 1e9 + 7; int dp1[N][N], dp2[N][N], a[N]; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } memset(dp1, 0, sizeof(dp1)); memset(dp2, 0, sizeof(dp2)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dp1[i][j] = dp1[i - 1][j]; } dp1[i][a[i]]++; } for (int i = n; i >= 1; i--) { for (int j = 1; j <= n; j++) { dp2[i][j] = dp2[i + 1][j]; } dp2[i][a[i]]++; } long long ans = 0; for (int i = 2; i <= n; i++) { for (int j = i + 1; j < n; j++) { ans += dp1[i - 1][a[j]] * dp2[j + 1][a[i]]; } } printf( %lld n , ans); } return 0; } |
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module aes_256 (clk, state, key, out);
input clk;
input [127:0] state;
input [255:0] key;
output [127:0] out;
reg [127:0] s0;
reg [255:0] k0, k0a, k1;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8,
s9, s10, s11, s12, s13;
wire [255:0] k2, k3, k4, k5, k6, k7, k8,
k9, k10, k11, k12, k13;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b,
k9b, k10b, k11b, k12b, k13b;
always @ (posedge clk)
begin
s0 <= state ^ key[255:128];
k0 <= key;
k0a <= k0;
k1 <= k0a;
end
assign k0b = k0a[127:0];
expand_key_type_A_256
a1 (clk, k1, 8'h1, k2, k1b),
a3 (clk, k3, 8'h2, k4, k3b),
a5 (clk, k5, 8'h4, k6, k5b),
a7 (clk, k7, 8'h8, k8, k7b),
a9 (clk, k9, 8'h10, k10, k9b),
a11 (clk, k11, 8'h20, k12, k11b),
a13 (clk, k13, 8'h40, , k13b);
expand_key_type_B_256
a2 (clk, k2, k3, k2b),
a4 (clk, k4, k5, k4b),
a6 (clk, k6, k7, k6b),
a8 (clk, k8, k9, k8b),
a10 (clk, k10, k11, k10b),
a12 (clk, k12, k13, k12b);
one_round
r1 (clk, s0, k0b, s1),
r2 (clk, s1, k1b, s2),
r3 (clk, s2, k2b, s3),
r4 (clk, s3, k3b, s4),
r5 (clk, s4, k4b, s5),
r6 (clk, s5, k5b, s6),
r7 (clk, s6, k6b, s7),
r8 (clk, s7, k7b, s8),
r9 (clk, s8, k8b, s9),
r10 (clk, s9, k9b, s10),
r11 (clk, s10, k10b, s11),
r12 (clk, s11, k11b, s12),
r13 (clk, s12, k12b, s13);
final_round
rf (clk, s13, k13b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_256 (clk, in, rcon, out_1, out_2);
input clk;
input [255:0] in;
input [7:0] rcon;
output reg [255:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, k6, k7,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8a;
assign {k0, k1, k2, k3, k4, k5, k6, k7} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a} <= {v0, v1, v2, v3, k4, k5, k6, k7};
S4
S4_0 (clk, {k7[23:0], k7[31:24]}, k8a);
assign k0b = k0a ^ k8a;
assign k1b = k1a ^ k8a;
assign k2b = k2a ^ k8a;
assign k3b = k3a ^ k8a;
assign {k4b, k5b, k6b, k7b} = {k4a, k5a, k6a, k7a};
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
/* expand k4,k5,k6,k7 for every two clock cycles */
module expand_key_type_B_256 (clk, in, out_1, out_2);
input clk;
input [255:0] in;
output reg [255:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, k6, k7,
v5, v6, v7;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8a;
assign {k0, k1, k2, k3, k4, k5, k6, k7} = in;
assign v5 = k4 ^ k5;
assign v6 = v5 ^ k6;
assign v7 = v6 ^ k7;
always @ (posedge clk)
{k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a} <= {k0, k1, k2, k3, k4, v5, v6, v7};
S4
S4_0 (clk, k3, k8a);
assign {k0b, k1b, k2b, k3b} = {k0a, k1a, k2a, k3a};
assign k4b = k4a ^ k8a;
assign k5b = k5a ^ k8a;
assign k6b = k6a ^ k8a;
assign k7b = k7a ^ k8a;
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b};
assign out_2 = {k4b, k5b, k6b, k7b};
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[310][310]; int main() { int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } int t = min(m, n); for (int d = 1; d < t; d++) { for (int i = d; i < n - d; i++) { for (int j = d; j < m - d; j++) { if (a[i][j] == * && a[i][j - d] == * && a[i][j + d] == * && a[i - d][j] == * && a[i + d][j] == * ) k--; if (k == 0) { cout << i + 1 << << j + 1 << endl; cout << i + 1 - d << << j + 1 << endl; cout << i + 1 + d << << j + 1 << endl; cout << i + 1 << << j - d + 1 << endl; cout << i + 1 << << j + d + 1 << endl; return 0; } } } } cout << -1 << endl; return 0; } |
// file: testclk_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module testclk_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Connect the feedback on chip
wire CLKFB_OUT;
wire CLKFB_IN;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Connect the feedback on chip- duplicate the delay for CLK_OUT1
assign CLKFB_IN = CLKFB_OUT;
// Instantiation of the clocking network
//--------------------------------------
testclk clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
.CLKFB_IN (CLKFB_IN),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
.CLK_OUT4 (clk_int[4]),
.CLKFB_OUT (CLKFB_OUT));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
ODDR clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
BUFG clkout1_buf
(.O (clk[1]),
.I (clk_int[1]));
BUFG clkout2_buf
(.O (clk[2]),
.I (clk_int[2]));
BUFG clkout3_buf
(.O (clk[3]),
.I (clk_int[3]));
BUFG clkout4_buf
(.O (clk[4]),
.I (clk_int[4]));
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
module frequency_divider(
input clk,
input rst_n,
output clk_out
);
parameter N= 6;
reg clk_out1;
reg [9:0] cnt1;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt1 <= 10'd0;
clk_out1 <= 1'd0;
end
else
begin
if(N==2)
clk_out1 <= ~clk_out1;
else
if(cnt1 <= ((N-1'd1)/2)- 1'd1)
begin
cnt1 <= cnt1 +1'd1;
clk_out1 <= 1'd1;
end
else
if(cnt1 <= (N-2'd2))
begin
cnt1 <= cnt1 +1'd1;
clk_out1 <= 1'd0;
end
else
begin
cnt1 <= 10'd0;
clk_out1 <= 1'd0;
end
end
end
reg clk_out2;
reg [9:0] cnt2;
always @(negedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt2 <= 10'd0;
clk_out2 <= 1'd0;
end
else
begin
if(N==2)
clk_out2 <= ~clk_out2;
else
if(cnt2 <= ((N-1'd1)/2)- 1'd1)
begin
cnt2 <= cnt2 +1'd1;
clk_out2 <= 1'd1;
end
else
if(cnt2 <= (N-2'd2))
begin
cnt2 <= cnt2 +1'd1;
clk_out2 <= 1'd0;
end
else
begin
cnt2 <= 10'd0;
clk_out2 <= 1'd0;
end
end
end
assign clk_out = clk_out1 | clk_out2;
endmodule |
#include <bits/stdc++.h> const int64_t mod = 998244353; int gcd(int64_t a, int64_t b) { while (a != 0 && b != 0) { if (a >= b) a = a % b; else b = b % a; } return a + b; } struct Fraction { int64_t numerator; int64_t devider; Fraction(int64_t n = 0, int64_t d = 1) : numerator(n), devider(d){}; const Fraction& operator+(const Fraction& rv) { if (rv.devider == devider) { numerator += rv.numerator; numerator %= mod; return *this; } else { numerator *= rv.devider; numerator %= mod; numerator += rv.numerator * devider; numerator %= mod; devider *= rv.devider; devider %= mod; return *this; } } const Fraction& operator*(const Fraction& rv) { numerator *= rv.numerator; devider *= rv.devider; numerator %= mod; devider %= mod; return *this; } }; struct Item { Item(Fraction f, int64_t s, int64_t v) : possibility(f), sum(s), val(v){}; Fraction possibility; int64_t sum; int64_t val; }; void extended_euclid(int64_t a, int64_t b, int64_t& x, int64_t& y, int64_t& d) { int64_t q, r, x1, x2, y1, y2; if (b == 0) { d = a, x = 1, y = 0; return; } x2 = 1, x1 = 0, y2 = 0, y1 = 1; while (b > 0) { q = a / b, r = a - q * b; x = x2 - q * x1, y = y2 - q * y1; a = b, b = r; x2 = x1, x1 = x, y2 = y1, y1 = y; } d = a, x = x2, y = y2; } int main() { int64_t n, m; std::cin >> n >> m; std::vector<std::pair<int64_t, bool>> data; int64_t posWeight = 0, negWeight = 0; for (int64_t i = 0; i < n; ++i) { int64_t a; std::cin >> a; if (a == 0) data.push_back(std::make_pair(-1, false)); else data.push_back(std::make_pair(-1, true)); } for (auto& i : data) { int64_t w; std::cin >> w; i.first = w; if (i.second) posWeight += w; else negWeight += w; } std::vector<Item> posVec{ Item(Fraction(1, 1), posWeight + negWeight, posWeight)}, negVec{Item(Fraction(1, 1), posWeight + negWeight, negWeight)}; for (int64_t i = 0; i < m; ++i) { std::vector<Item> newPos, newNeg; for (auto j : posVec) { if (!newPos.size()) { Fraction f(j.val, j.sum); f = f * j.possibility; newPos.push_back(Item(f, j.sum + 1, j.val + 1)); } else { Fraction f(j.val, j.sum); f = f * j.possibility; newPos.rbegin()->possibility = newPos.rbegin()->possibility + f; } if (j.sum > j.val) { Fraction f(j.sum - j.val, j.sum); f = f * j.possibility; newPos.push_back(Item(f, j.sum - 1, j.val)); } } for (auto j : negVec) { if (!newNeg.size() && j.val > 1) { Fraction f(j.val, j.sum); f = f * j.possibility; newNeg.push_back(Item(f, j.sum - 1, j.val - 1)); } else if (j.val > 1) { Fraction f(j.val, j.sum); f = f * j.possibility; newNeg.rbegin()->possibility = newNeg.rbegin()->possibility + f; } Fraction f(j.sum - j.val, j.sum); f = f * j.possibility; newNeg.push_back(Item(f, j.sum + 1, j.val)); } posVec = newPos; negVec = newNeg; } Fraction pos, neg; for (auto i : posVec) pos = pos + Fraction(i.val, 1) * i.possibility; for (auto i : negVec) neg = neg + Fraction(i.val, 1) * i.possibility; for (auto i : data) { Fraction res; if (i.second) res = Fraction(i.first, posWeight) * pos; else res = Fraction(i.first, negWeight) * neg; int64_t g = gcd(res.numerator, res.devider); res.numerator /= g; res.devider /= g; int64_t d, x, y; extended_euclid(res.devider, mod, x, y, d); std::cout << (((x % mod + mod) % mod) * res.numerator) % mod << std::endl; } return 0; } |
// Library - static, Cell - th34, View - schematic
// LAST TIME SAVED: May 23 16:59:44 2014
// NETLIST TIME: May 23 17:00:06 2014
`timescale 1ns / 1ns
module th34 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th34";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P15 ( .b(cds_globals.vdd_), .g(b), .s(net59), .d(net28));
pfet_b P14 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net59));
pfet_b P16 ( .b(cds_globals.vdd_), .g(c), .s(net28), .d(net60));
pfet_b P17 ( .b(cds_globals.vdd_), .g(d), .s(net60), .d(net26));
pfet_b P20 ( .b(cds_globals.vdd_), .g(c), .s(net39), .d(net44));
pfet_b P18 ( .b(cds_globals.vdd_), .g(y), .s(net28), .d(net26));
pfet_b P19 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net39));
pfet_b P21 ( .b(cds_globals.vdd_), .g(y), .s(net44), .d(net26));
pfet_b P23 ( .b(cds_globals.vdd_), .g(d), .s(net39), .d(net44));
pfet_b P22 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net39));
pfet_b P24 ( .b(cds_globals.vdd_), .g(c), .s(cds_globals.vdd_),
.d(net58));
pfet_b P25 ( .b(cds_globals.vdd_), .g(d), .s(net58), .d(net44));
nfet_b N0 ( .d(net34), .g(a), .s(net57), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net26), .g(c), .s(net34), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net57), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net34), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N4 ( .d(net26), .g(d), .s(net34), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net26), .g(a), .s(net40), .b(cds_globals.gnd_));
nfet_b N7 ( .d(net56), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N8 ( .d(net40), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N9 ( .d(net26), .g(b), .s(net40), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net40), .g(c), .s(net56), .b(cds_globals.gnd_));
inv I2 ( y, net26);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O22A_FUNCTIONAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o22a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_SYMBOL_V
`define SKY130_FD_SC_HS__AND4BB_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A21BO_FUNCTIONAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_FUNCTIONAL_V |
//
// fixed for 9.1 jan 21 2010 cruben
//
`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 23:27:29 04/27/2016
// Design Name: Search_8Comparators
// Module Name: D:/Documents/College/CalPolyPomona/SeniorProject/hardware-accelerated-dna-matching-and-variation-detection/Hardware/Verilog/Search_8Comparators_tf.v
// Project Name: Verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Search_8Comparators
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Search_8Comparators_tf;
// Inputs
reg clock;
reg reset;
reg [1023:0] data;
reg [63:0] key;
// Outputs
wire match;
// Instantiate the Unit Under Test (UUT)
Search_8Comparators uut (
.clock(clock),
.reset(reset),
.data(data),
.key(key),
.match(match)
);
// Alternate the clock every unit of time.
initial begin
clock = 0;
repeat (1_000_000)
#1 clock =~ clock;
end
initial begin
// Initialization
reset = 1;
data = 1024'b0100111010111010001100110010000010010111001110111010001010111000010111111100010011101110000010000010010100001010001111011010010010001101000100100001111100010111001110011110010001000111110010000001101100000000100100011000011100011110000110111011011000111011010000011010011011010000011111101100101100000101011101010011000010001110001110100111011000000100101000000100001010011010000011000100100000100011001101110000100011001111110001010011001100101011100100000000110000110000001010011010001000101101111000111100111100110000111100010000001000010000100110000000000011110011101000101100110011000011111000000001001001100100000000000000000001000010000010011001111000110001000010111111110101100000111110011001111000100000001100000011111111010110000010111100110111111110101110111110010001100001110010111001000110101011011110111000000100001101110000110000110010101000111001110001011100110101111100000001001100011000111011101000100000101011100000000110111010111101101001000100011110011010101110101111110111100100011100001111111110001011;
key = 64'b0100111010111010001100110010000010010111001110111010001010111000;
@(negedge clock);
// Turn off the reset and let the module be tested as is.
reset = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_2_V
`define SKY130_FD_SC_MS__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_2_V
|
#include <bits/stdc++.h> using namespace std; const int M = 1e6 + 7; inline long long stoll(char* s, const long long& p, bool f = 0) { long long a = 0; bool fl = 0; for (; *s; ++s) a = a * 10 + *s - 48, fl |= (f && a >= p), a %= p; return a + fl * p; } long long b, n, p, phi; char B[M], N[M]; inline long long fp(long long x, long long k, const long long& p) { long long r = 1; for (; k; k >>= 1, x = x * x % p) if (k & 1) r = r * x % p; return r; } inline long long getphi(long long n) { long long r = n, nn = n; for (long long i = 2; i * i <= nn; ++i) if (!(n % i)) for (r = r / i * (i - 1); !(n % i); n /= i) ; if (n > 1) r = r / n * (n - 1); return r; } inline long long mod(long long x, long long p) { return x < p ? x : x % p + p; }; inline char* N_1() { register int s = strlen(N) - 1; for (; s >= 0 && !N[s]; --s) ; --N[s]; return N; } int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> B >> N >> p; phi = getphi(p); b = stoll(B, p), n = stoll(N_1(), phi, 1); long long ans = ((b - 1) * fp(b, n, p) + p) % p; if (!(ans)) ans = p; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n; cin >> n; bitset<6> a(n); string s = a.to_string(); swap(s[1], s[5]); swap(s[2], s[3]); bitset<6> b(s); cout << static_cast<int>(b.to_ulong()) << n ; } |
module main(CLOCK_50, KEY, LEDR, SW, UART_RXD, UART_TXD);
input CLOCK_50;
input KEY[3:0];
output [17:0] LEDR;
input [17:0] SW;
input UART_RXD;
output UART_TXD;
integer i;
// Regs
reg [7:0] current_value, value_into_genetico;
reg [10:0] current_circuit_les[8:0];
reg [3:0] current_circuit_outs[1:0];
// Wires
wire [31:0] data_to_send, rs232_received_data;
wire [7:0] mem_out, genetico_out;
wire rx_done, tx_done, tx_send, start_sampling, start_sending, mem_write,
finished_sampling, finished_sending, mem_addr, fetch_value, serial_reset,
insert_value, done_receiving, set_current_circuit;
wire [15:0] sampler_mem_addr, sender_mem_addr;
wire [7:0] received_data[199:0];
assign LEDR[7:0] = current_value;
assign LEDR[17:10] = genetico_out;
assign data_to_send = {24'b0, mem_out};
always @(posedge CLOCK_50) begin
if (fetch_value)
current_value <= received_data[1];
if (insert_value)
value_into_genetico <= current_value;
if (set_current_circuit) begin
for (i = 0; i < 9; i = i + 1) begin
current_circuit_les[i][10:8] <= received_data[(i * 3) + 1][2:0];
current_circuit_les[i][7:4] <= received_data[(i * 3) + 2][3:0];
current_circuit_les[i][3:0] <= received_data[(i * 3) + 3][3:0];
end
for (i = 0; i < 2; i = i + 1) begin
current_circuit_outs[i] <= received_data[i + 27 + 1][3:0];
end
end
end
sampler sampler(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iStartSignal(start_sampling),
.oAddress(sampler_mem_addr),
.oFinished(finished_sampling)
);
sender sender(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iTxDone(tx_done),
.iStartSignal(start_sending),
.oAddress(sender_mem_addr),
.oFinished(finished_sending),
.oTxSend(tx_send)
);
main_fsm fsm(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iDoneReceiving(done_receiving),
.iReceivedData(received_data),
.iSamplingDone(finished_sampling),
.iSendingDone(finished_sending),
.oMemWrite(mem_write),
.oMemAddr(mem_addr),
.oStartSampling(start_sampling),
.oStartSending(start_sending),
.oFetchValue(fetch_value),
.oSetCurrentCircuit(set_current_circuit),
.oInsertValue(insert_value),
.oResetSerial(serial_reset)
);
memoria memoria(
.address(mem_addr ? sender_mem_addr : sampler_mem_addr),
.clock(CLOCK_50),
.data(genetico_out),
.wren(mem_write),
.q(mem_out)
);
data_receiver data_receiver(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iRxDone(rx_done),
.iReceivedData(rs232_received_data),
.oResultData(received_data),
.oDoneReceiving(done_receiving)
);
uart rs232(
.sys_clk(CLOCK_50),
.sys_rst(~KEY[1] | serial_reset),
.csr_a(14'b0),
.csr_we(tx_send),
.csr_di(data_to_send),
.csr_do(rs232_received_data),
.rx_irq(rx_done),
.tx_irq(tx_done),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD)
);
genetico genetico(
.conf_les(current_circuit_les),
.conf_outs(current_circuit_outs),
.in(value_into_genetico),
.out(genetico_out)
);
endmodule |
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_phy_10g_rx
*/
module test_eth_phy_10g_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 1250/6.4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
reg rx_prbs31_enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] xgmii_rxd;
wire [CTRL_WIDTH-1:0] xgmii_rxc;
wire serdes_rx_bitslip;
wire [6:0] rx_error_count;
wire rx_bad_block;
wire rx_block_lock;
wire rx_high_ber;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
serdes_rx_data,
serdes_rx_hdr,
rx_prbs31_enable
);
$to_myhdl(
xgmii_rxd,
xgmii_rxc,
serdes_rx_bitslip,
rx_error_count,
rx_bad_block,
rx_block_lock,
rx_high_ber
);
// dump file
$dumpfile("test_eth_phy_10g_rx_64.lxt");
$dumpvars(0, test_eth_phy_10g_rx_64);
end
eth_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
UUT (
.clk(clk),
.rst(rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; void solve(){ cin >> n >> k; int cnt = 1; int query = 0; for(int i = 0; i < n; i++){ if(i) query = i ^ (i - 1); cout << query << endl; int r; cin >> r; if(r == 1) return; } } int main(){ // freopen( inp.txt , r , stdin); // freopen( out.txt , w , stdout); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while(t--) solve(); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long SG[1110000] = {0, 1, 2, 1, 4, 3, 2, 1, 5, 6, 2, 1, 8, 7, 5, 9, 8, 7, 3, 4, 7, 4, 2, 1, 10, 9, 3, 6, 11, 12, 14, 13}; long long n, Ans, vis[1110000]; set<long long> Hehe; int main() { scanf( %I64d , &n); long long Orz = (long long)(floor)(sqrt(1.0 * n)); for (long long i = 2; i * i <= n; ++i) { long long c = 0; if (vis[i]) continue; for (long long j = i; j <= n; j *= i, c++) { if (j > Orz) Hehe.insert(j); else vis[j] = 1; } Ans ^= SG[c]; } long long tmp = n - Orz - Hehe.size(); if (!(tmp & 1)) Ans ^= 1; if (Ans) printf( Vasya ); else printf( Petya ); return 0; } |
module firewall_top(
input Clk,
input Rst_n,
input Enet0_Rx_Data,
input Enet0_Rx_Dv,
input Enet0_Rx_Er,
output reg [7:0] Enet0_Tx_Data,
output reg Enet0_Tx_Dv,
output reg Enet0_Tx_Er,
input [7:0] Enet1_Rx_Data,
input Enet1_Rx_Dv,
input Enet1_Rx_Er,
output reg [7:0] Enet1_Tx_Data,
output reg Enet1_Tx_Dv,
output reg Enet1_Tx_Er
);
wire avalonST_1_valid_wire;
wire [7:0] avalonST_1_data_wire;
wire avalonST_1_channel_wire;
wire avalonST_1_error_wire;
wire avalonST_1_ready_wire;
wire avalonST_2_valid_wire;
wire [7:0] avalonST_2_data_wire;
wire avalonST_2_channel_wire;
wire avalonST_2_error_wire;
wire avalonST_2_ready_wire;
wire avalonST_3_valid_wire;
wire [7:0] avalonST_3_data_wire;
wire avalonST_3_channel_wire;
wire avalonST_3_error_wire;
wire avalonST_3_ready_wire;
wire avalonST_4_valid_wire;
wire [7:0] avalonST_4_data_wire;
wire avalonST_4_channel_wire;
wire avalonST_4_error_wire;
wire avalonST_4_ready_wire;
eth_mac_l2 eth_mac_inst(
.Clk(Clk), // 125 MHz clock for GMII signals
.Rst_n(Rst_n), // active-high sync reset
.M_ETH0_avalonST_valid(avalonST_1_valid_wire),
.M_ETH0_avalonST_data(avalonST_1_data_wire),
.M_ETH0_avalonST_channel(avalonST_1_channel_wire),
.M_ETH0_avalonST_error(avalonST_1_error_wire),
.M_ETH0_avalonST_ready(avalonST_1_ready_wire),
.S_ETH0_avalonST_valid(avalonST_2_valid_wire),
.S_ETH0_avalonST_data(avalonST_2_data_wire),
.S_ETH0_avalonST_channel(avalonST_2_channel_wire),
.S_ETH0_avalonST_error(avalonST_2_error_wire),
.S_ETH0_avalonST_ready(avalonST_2_ready_wire),
.M_ETH1_avalonST_valid(avalonST_3_valid_wire),
.M_ETH1_avalonST_data(avalonST_3_data_wire),
.M_ETH1_avalonST_channel(avalonST_3_channel_wire),
.M_ETH1_avalonST_error(avalonST_3_error_wire),
.M_ETH1_avalonST_ready(avalonST_3_ready_wire),
.S_ETH1_avalonST_valid(avalonST_4_valid_wire),
.S_ETH1_avalonST_data(avalonST_4_data_wire),
.S_ETH1_avalonST_channel(avalonST_4_channel_wire),
.S_ETH1_avalonST_error(avalonST_4_error_wire),
.S_ETH1_avalonST_ready(avalonST_4_ready_wire),
.ENET0_RX_DATA(ENET0_RX_DATA),
.ENET0_RX_DV(ENET0_RX_DV),
.ENET0_RX_ER(ENET0_RX_ER),
.ENET0_TX_DATA(ENET0_TX_DATA),
.ENET0_TX_DV(ENET0_TX_DV),
.ENET0_TX_ER(ENET0_TX_ER),
.ENET1_RX_DATA(ENET1_RX_DATA),
.ENET1_RX_DV(ENET1_RX_DV),
.ENET1_RX_ER(ENET1_RX_ER),
.ENET1_TX_DATA(ENET1_TX_DATA),
.ENET1_TX_DV(ENET1_TX_DV),
.ENET1_TX_ER(ENET1_TX_ER)
);
endmodule |
/*
Copyright (c) 2015-2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* PTP clock module
*/
module ptp_clock #
(
parameter PERIOD_NS_WIDTH = 4,
parameter OFFSET_NS_WIDTH = 4,
parameter DRIFT_NS_WIDTH = 4,
parameter FNS_WIDTH = 16,
parameter PERIOD_NS = 4'h6,
parameter PERIOD_FNS = 16'h6666,
parameter DRIFT_ENABLE = 1,
parameter DRIFT_NS = 4'h0,
parameter DRIFT_FNS = 16'h0002,
parameter DRIFT_RATE = 16'h0005
)
(
input wire clk,
input wire rst,
/*
* Timestamp inputs for synchronization
*/
input wire [95:0] input_ts_96,
input wire input_ts_96_valid,
input wire [63:0] input_ts_64,
input wire input_ts_64_valid,
/*
* Period adjustment
*/
input wire [PERIOD_NS_WIDTH-1:0] input_period_ns,
input wire [FNS_WIDTH-1:0] input_period_fns,
input wire input_period_valid,
/*
* Offset adjustment
*/
input wire [OFFSET_NS_WIDTH-1:0] input_adj_ns,
input wire [FNS_WIDTH-1:0] input_adj_fns,
input wire [15:0] input_adj_count,
input wire input_adj_valid,
output wire input_adj_active,
/*
* Drift adjustment
*/
input wire [DRIFT_NS_WIDTH-1:0] input_drift_ns,
input wire [FNS_WIDTH-1:0] input_drift_fns,
input wire [15:0] input_drift_rate,
input wire input_drift_valid,
/*
* Timestamp outputs
*/
output wire [95:0] output_ts_96,
output wire [63:0] output_ts_64,
output wire output_ts_step,
/*
* PPS output
*/
output wire output_pps
);
parameter INC_NS_WIDTH = $clog2(2**PERIOD_NS_WIDTH + 2**OFFSET_NS_WIDTH + 2**DRIFT_NS_WIDTH);
reg [PERIOD_NS_WIDTH-1:0] period_ns_reg = PERIOD_NS;
reg [FNS_WIDTH-1:0] period_fns_reg = PERIOD_FNS;
reg [OFFSET_NS_WIDTH-1:0] adj_ns_reg = 0;
reg [FNS_WIDTH-1:0] adj_fns_reg = 0;
reg [15:0] adj_count_reg = 0;
reg adj_active_reg = 0;
reg [DRIFT_NS_WIDTH-1:0] drift_ns_reg = DRIFT_NS;
reg [FNS_WIDTH-1:0] drift_fns_reg = DRIFT_FNS;
reg [15:0] drift_rate_reg = DRIFT_RATE;
reg [INC_NS_WIDTH-1:0] ts_inc_ns_reg = 0;
reg [FNS_WIDTH-1:0] ts_inc_fns_reg = 0;
reg [47:0] ts_96_s_reg = 0;
reg [29:0] ts_96_ns_reg = 0;
reg [FNS_WIDTH-1:0] ts_96_fns_reg = 0;
reg [29:0] ts_96_ns_inc_reg = 0;
reg [FNS_WIDTH-1:0] ts_96_fns_inc_reg = 0;
reg [30:0] ts_96_ns_ovf_reg = 31'h7fffffff;
reg [FNS_WIDTH-1:0] ts_96_fns_ovf_reg = 16'hffff;
reg [47:0] ts_64_ns_reg = 0;
reg [FNS_WIDTH-1:0] ts_64_fns_reg = 0;
reg ts_step_reg = 1'b0;
reg [15:0] drift_cnt = 0;
reg [47:0] temp;
reg pps_reg = 0;
assign input_adj_active = adj_active_reg;
assign output_ts_96[95:48] = ts_96_s_reg;
assign output_ts_96[47:46] = 2'b00;
assign output_ts_96[45:16] = ts_96_ns_reg;
assign output_ts_96[15:0] = FNS_WIDTH > 16 ? ts_96_fns_reg >> (FNS_WIDTH-16) : ts_96_fns_reg << (16-FNS_WIDTH);
assign output_ts_64[63:16] = ts_64_ns_reg;
assign output_ts_64[15:0] = FNS_WIDTH > 16 ? ts_64_fns_reg >> (FNS_WIDTH-16) : ts_64_fns_reg << (16-FNS_WIDTH);
assign output_ts_step = ts_step_reg;
assign output_pps = pps_reg;
always @(posedge clk) begin
ts_step_reg <= 0;
// latch parameters
if (input_period_valid) begin
period_ns_reg <= input_period_ns;
period_fns_reg <= input_period_fns;
end
if (input_adj_valid) begin
adj_ns_reg <= input_adj_ns;
adj_fns_reg <= input_adj_fns;
adj_count_reg <= input_adj_count;
end
if (DRIFT_ENABLE && input_drift_valid) begin
drift_ns_reg <= input_drift_ns;
drift_fns_reg <= input_drift_fns;
drift_rate_reg <= input_drift_rate;
end
// timestamp increment calculation
{ts_inc_ns_reg, ts_inc_fns_reg} <= $signed({1'b0, period_ns_reg, period_fns_reg}) +
(adj_active_reg ? $signed({adj_ns_reg, adj_fns_reg}) : 0) +
((DRIFT_ENABLE && drift_cnt == 0) ? $signed({drift_ns_reg, drift_fns_reg}) : 0);
// offset adjust counter
if (adj_count_reg > 0) begin
adj_count_reg <= adj_count_reg - 1;
adj_active_reg <= 1;
ts_step_reg <= 1;
end else begin
adj_active_reg <= 0;
end
// drift counter
if (drift_cnt == 0) begin
drift_cnt <= drift_rate_reg-1;
end else begin
drift_cnt <= drift_cnt - 1;
end
// 96 bit timestamp
if (input_ts_96_valid) begin
// load timestamp
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= (FNS_WIDTH > 16 ? input_ts_96[45:0] << (FNS_WIDTH-16) : input_ts_96[45:0] >> (16-FNS_WIDTH)) + {ts_inc_ns_reg, ts_inc_fns_reg};
{ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= (FNS_WIDTH > 16 ? input_ts_96[45:0] << (FNS_WIDTH-16) : input_ts_96[45:0] >> (16-FNS_WIDTH)) + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
ts_96_s_reg <= input_ts_96[95:48];
ts_96_ns_reg <= input_ts_96[45:16];
ts_96_fns_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
ts_step_reg <= 1;
end else if (!ts_96_ns_ovf_reg[30]) begin
// if the overflow lookahead did not borrow, one second has elapsed
// increment seconds field, pre-compute both normal increment and overflow values
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
{ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
{ts_96_ns_reg, ts_96_fns_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg};
ts_96_s_reg <= ts_96_s_reg + 1;
end else begin
// no increment seconds field, pre-compute both normal increment and overflow values
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= {ts_96_ns_inc_reg, ts_96_fns_inc_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
{ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= {ts_96_ns_inc_reg, ts_96_fns_inc_reg} + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
{ts_96_ns_reg, ts_96_fns_reg} <= {ts_96_ns_inc_reg, ts_96_fns_inc_reg};
ts_96_s_reg <= ts_96_s_reg;
end
// 64 bit timestamp
if (input_ts_64_valid) begin
// load timestamp
{ts_64_ns_reg, ts_64_fns_reg} <= input_ts_64;
ts_step_reg <= 1;
end else begin
{ts_64_ns_reg, ts_64_fns_reg} <= {ts_64_ns_reg, ts_64_fns_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
end
pps_reg <= !ts_96_ns_ovf_reg[30];
if (rst) begin
period_ns_reg <= PERIOD_NS;
period_fns_reg <= PERIOD_FNS;
adj_ns_reg <= 0;
adj_fns_reg <= 0;
adj_count_reg <= 0;
adj_active_reg <= 0;
drift_ns_reg <= DRIFT_NS;
drift_fns_reg <= DRIFT_FNS;
drift_rate_reg <= DRIFT_RATE;
ts_inc_ns_reg <= 0;
ts_inc_fns_reg <= 0;
ts_96_s_reg <= 0;
ts_96_ns_reg <= 0;
ts_96_fns_reg <= 0;
ts_96_ns_inc_reg <= 0;
ts_96_fns_inc_reg <= 0;
ts_96_ns_ovf_reg <= 31'h7fffffff;
ts_96_fns_ovf_reg <= {FNS_WIDTH{1'b1}};
ts_64_ns_reg <= 0;
ts_64_fns_reg <= 0;
ts_step_reg <= 0;
drift_cnt <= 0;
pps_reg <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long sum[4]; int main(void) { long long n, a, b, c, d, min_value = 1e14, max_value = 0, flag = 0; scanf( %lld %lld %lld %lld %lld , &n, &a, &b, &c, &d); sum[0] = a + b; sum[1] = b + d; sum[2] = c + d; sum[3] = a + c; for (int i = 0; i < 4; i++) { min_value = min(min_value, sum[i]); max_value = max(max_value, sum[i]); } if (max_value - min_value > n) flag = 1; if (flag == 1) printf( 0 ); else printf( %lld , n * (n - (max_value - min_value))); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_power_hvc_wpad ( P_PAD, AMUXBUS_A, AMUXBUS_B
, P_CORE, DRN_HVC, OGC_HVC, SRC_BDY_HVC,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VSSIO, VSSD, VSSIO_Q
);
inout P_PAD;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout OGC_HVC;
inout DRN_HVC;
inout SRC_BDY_HVC;
inout P_CORE;
inout VDDIO;
inout VDDIO_Q;
inout VDDA;
inout VCCD;
inout VSWITCH;
inout VCCHIB;
inout VSSA;
inout VSSD;
inout VSSIO_Q;
inout VSSIO;
assign P_CORE = P_PAD;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:30 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/ip_design_rst_ps7_0_100M_0_stub.v
// Design : ip_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
module ip_design_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef unsigned long long int ull; typedef long long int ll; typedef long double ld; #define fr(i,a,b) for(ll i=a; i<b; i++) #define rf(i,a,b) for(ll i=a; i>=b; i--) #define pb push_back #define mp make_pair #define show(a) for(auto el:a)cout<<el<< #define ff first #define ss second #define pairv vector<pair<ll,ll>> #define vec vector <ll> #define all(a) a.begin(),a.end() #define fam(v,i) for(auto i=v.begin();i!=v.end();i++) #define fai(v,i) for(auto i : v) #define mo 1000000007 #define nn cout<< n ; #define Y cout<< YES n ; #define N cout<< NO n ; #define cout_dec cout << fixed << setprecision(9) #define casepr(ti) cout<< case # <<ti+1<< : #define fill(a,b) memset(a, b, sizeof(a)) ll pow1(ll n,ll p) { if(p==0) return 1; ll x=pow1(n, p/2); x=(x*x)%mo; if(p%2==0) return x; else return (x*n)%mo; } bool sortbysec(const pair<ll,ll> &a, const pair<ll,ll> &b) { return (a.second < b.second); } bool compare(const pair<ll, ll>&p1, const pair<ll,ll>&p2) { if(p1.ff < p2.ff) return true; if(p1.ff == p2.ff) return p1.ff < p2.ss; return false; } ll const maxn=200007; ll nxt[maxn]; void seive() { for (ll i = 2; i < maxn; ++i) { if (nxt[i] == 0) { nxt[i] = i; for (ll j = i * i; j < maxn; j += i) { if(j>=maxn) { break; } if (nxt[j] == 0) nxt[j] = i; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int test=1; cin>>test; for(int ti=0;ti<test;ti++) { ll i,j,k,e,f,n,c=0,x=0; cin>>n; ll m=n+2; ll b[n+2]; fr(i,0,n+2) cin>>b[i]; sort(b,b+m); fr(i,0,n) { c=c+b[i]; } if(c== b[n] || c==b[n+1]) { fr(i,0,n) { cout<<b[i]<< ; } nn continue; } x=-1; fr(i,0,n) { if(c-b[i]+b[n]==b[n+1]) { x=i; break; } } if(x==-1) { cout<<-1; } else { fr(i,0,n+1) { if(i==x) { continue; } cout<<b[i]<< ; } } nn } return 0; } |
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S9_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAMB16_S9_altera (
address,
clock,
data,
rden,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input rden;
input wren;
output [7:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../../../Documents and Settings/Danaoula/Desktop/NF2/projects/ngnp_multicore/src/bb_ram0.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../../../Documents and Settings/Danaoula/Desktop/NF2/projects/ngnp_multicore/src/bb_ram0.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT NODEFVAL rden
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t, a, b, diff, n; cin >> t; while (t--) { cin >> a >> b; diff = abs(a - b); n = ceil((-1 + sqrt(1 + 8 * diff)) / 2); if (((n + 1) / 2) % 2 != diff % 2) { if (n % 2) n += 2; else n++; } if (n == -0) n = 0; cout << n << n ; } } |
#include <bits/stdc++.h> using namespace std; int l[100000 + 9], r[100000 + 9]; int n, p; int main() { cin >> n >> p; for (int i = 0; i < n; i++) { cin >> l[i] >> r[i]; } double ans = 0; for (int i = 0; i < n; i++) { int j = (i + 1) % n; int div1 = r[i] / p - (l[i] - 1) / p; int nondiv1 = r[i] - l[i] + 1 - div1; int div2 = r[j] / p - (l[j] - 1) / p; int nondiv2 = r[j] - l[j] + 1 - div2; double nondivs = 1.0 - ((double)nondiv1 / double(r[i] - l[i] + 1)) * ((double)nondiv2 / double(r[j] - l[j] + 1)); ans += nondivs * 2000.0; } cout << fixed << setprecision(15) << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; struct st { int x, p; }; bool myfun(st a, st b) { return a.x < b.x; } int main() { int i, sum = 0, c = 0, n, k; st a[110]; cin >> n >> k; for (i = 0; i < n; ++i) { a[i].p = i + 1; cin >> a[i].x; } sort(a, a + n, myfun); for (i = 0; i < n; ++i) { sum += a[i].x; if (sum > k) break; c++; } cout << c << n ; for (i = 0; i < c; ++i) cout << a[i].p << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_V
`define SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ls__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int main() { fast(); long long n; cin >> n; char a[n + 10]; for (int i = 1; i <= n; ++i) cin >> a[i]; long long func[15]; for (int i = 1; i <= 9; ++i) { cin >> func[i]; } for (int i = 1; i <= n; ++i) { if (func[a[i] - 0 ] > a[i] - 0 ) { for (int j = i; j <= n; ++j) { if (a[j] - 0 <= func[a[j] - 0 ]) a[j] = func[a[j] - 0 ] + 0 ; else break; } for (int j = 1; j <= n; ++j) cout << a[j]; return 0; } } for (int i = 1; i <= n; ++i) cout << a[i]; return 0; } |
`include "riscv_functions.vh"
module riscv_wb (
input clk,
input rstn,
//Downstream
input mem_wb_rdy,
output mem_wb_ack,
//Mem bus input
input [31:0] data_bif_rdata,
input data_bif_rvalid,
//MEM input
input [`LD_FUNCT_W-1:0] mem_wb_funct,
input [31:0] mem_wb_data,
input [4:0] mem_wb_rsd,
//RF output
output [31:0] wb_rf_data,
output [4:0] wb_rf_rsd,
output wb_rf_write
);
//Outputs
reg [31:0] wb_rf_data;
reg [4:0] wb_rf_rsd;
reg wb_rf_write;
wire [31:0] rdata_lsht;
wire [23:0] sign_ext_byte;
wire [15:0] sign_ext_half;
wire [23:0] zero_ext_byte;
wire [15:0] zero_ext_half;
wire load_pending;
wire [1:0] baddr;
reg [31:0] wb_data;
//wb_data = address
assign baddr = mem_wb_data[1:0];
assign load_pending = (mem_wb_funct == `LD_NOP || data_bif_rvalid) ? 1'b0 : 1'b1;
assign rdata_lsht = data_bif_rdata >> (8*baddr);
assign sign_ext_byte = {24{rdata_lsht[7]}};
assign sign_ext_half = {16{rdata_lsht[15]}};
assign zero_ext_byte = {24{1'b0}};
assign zero_ext_half = {15{1'b0}};
assign mem_wb_ack = ~load_pending;
always @ (*) begin
case (mem_wb_funct)
`LD_NOP : wb_data = mem_wb_data;
`LD_LB : wb_data = {sign_ext_byte, rdata_lsht[7:0]};
`LD_LH : wb_data = {sign_ext_half, rdata_lsht[15:0]};
`LD_LW : wb_data = rdata_lsht;
`LD_LBU : wb_data = {zero_ext_byte, rdata_lsht[7:0]};
`LD_LHU : wb_data = {zero_ext_half, rdata_lsht[15:0]};
default: begin
$display("ERROR mem_wb: unknown function: %x", mem_wb_funct);
$finish;
end
endcase
end
/*
* Pulse wb_rf_write?
*/
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
wb_rf_data <= 'h0;
wb_rf_rsd <= 'h0;
wb_rf_write <= 'h0;
end
else begin
if (mem_wb_rdy && mem_wb_ack) begin
wb_rf_data <= wb_data;
wb_rf_rsd <= mem_wb_rsd;
wb_rf_write <= 1'b1;
end
else begin
wb_rf_data <= 'h0;
wb_rf_rsd <= 'h0;
wb_rf_write <= 'h0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_TB_V
`define SKY130_FD_SC_MS__AND2_TB_V
/**
* and2: 2-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:16:04 05/14/2015
// Design Name:
// Module Name: NumIn
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NumIn(
input clk,
input[7:0] addFlag,
output reg[31:0] number
);
wire[7:0] btn_out;
pbdebounce p0(clk,addFlag[0],btn_out[0]);
pbdebounce p1(clk,addFlag[1],btn_out[1]);
pbdebounce p2(clk,addFlag[2],btn_out[2]);
pbdebounce p3(clk,addFlag[3],btn_out[3]);
pbdebounce p4(clk,addFlag[4],btn_out[4]);
pbdebounce p5(clk,addFlag[5],btn_out[5]);
pbdebounce p6(clk,addFlag[6],btn_out[6]);
pbdebounce p7(clk,addFlag[7],btn_out[7]);
always @(posedge btn_out[0]) number[ 3: 0] <= number[ 3: 0] + 4'd1;
always @(posedge btn_out[1]) number[ 7: 4] <= number[ 7: 4] + 4'd1;
always @(posedge btn_out[2]) number[11: 8] <= number[11: 8] + 4'd1;
always @(posedge btn_out[3]) number[15:12] <= number[15:12] + 4'd1;
always @(posedge btn_out[4]) number[19:16] <= number[19:16] + 4'd1;
always @(posedge btn_out[5]) number[23:20] <= number[23:20] + 4'd1;
always @(posedge btn_out[6]) number[27:24] <= number[27:24] + 4'd1;
always @(posedge btn_out[7]) number[31:28] <= number[31:28] + 4'd1;
endmodule
module pbdebounce
(input wire clk,
input wire button,
output reg pbreg);
reg [7:0] pbshift;
wire clk_1ms;
timer_1ms m0(clk, clk_1ms);
always@(posedge clk_1ms) begin
pbshift <=pbshift<<1;
pbshift[0] <=button;
if (pbshift==0)
pbreg <=0;
if (pbshift==8'hFF)
pbreg <=1;
end
endmodule
module timer_1ms
(input wire clk,
output reg clk_1ms);
reg [15:0] cnt;
initial begin
cnt [15:0] <=0;
clk_1ms <= 0;
end
always@(posedge clk)
if(cnt>=25000) begin
cnt<=0;
clk_1ms <= ~clk_1ms;
end
else begin
cnt<=cnt+1;
end
endmodule
|
// $Id: c_clkgate.v 1649 2009-11-01 07:17:55Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// a generic clock gating module
module c_clkgate
(clk, enable, clk_gated);
input clk;
input enable;
output clk_gated;
wire clk_gated;
reg enable_q;
always @(clk, enable)
begin
if(clk == 0)
enable_q <= enable;
end
assign clk_gated = clk & enable_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1 << 28; const long long LINF = 1ll << 61; const long long mod = 1e9 + 7; unsigned long long base = 1000000007; char a[2][2011], s[2011]; int n, m; unsigned long long hsl[2][2011], hsr[2][2011], hss[2011], pw[2011]; unsigned long long gethsl(int i, int x, int y) { return hsl[i][y] - hsl[i][x - 1] * pw[y - x + 1]; } unsigned long long gethsr(int i, int x, int y) { return hsr[i][y] - hsr[i][x + 1] * pw[x - y + 1]; } unsigned long long gethss(int x, int y) { return hss[y] - hss[x - 1] * pw[y - x + 1]; } long long dp[2][2011][2], pre[2][2011][2]; long long solve() { for (int i = 0; i < 2; i++) { hsl[i][0] = 0; for (int j = 1; j <= n; j++) hsl[i][j] = hsl[i][j - 1] * base + a[i][j]; hsr[i][n + 1] = 0; for (int j = n; j >= 1; j--) hsr[i][j] = hsr[i][j + 1] * base + a[i][j]; } long long ans = 0; memset(dp, 0, sizeof(dp)); for (int p = 1; p <= m; p++) { for (int i = 0; i < 2; i++) for (int j = 1; j <= n; j++) for (int t = 0; t < 2; t++) pre[i][j][t] = dp[i][j][t]; memset(dp, 0, sizeof(dp)); if (p % 2 == 0 && p > 2 && p < m) { int len = p >> 1; for (int i = 0; i < 2; i++) { for (int j = len + 1; j <= n + 1; j++) { if (gethsr(i, j - 1, j - len) * pw[len] + gethsl(!i, j - len, j - 1) != gethss(1, p)) continue; dp[!i][j - 1][1] = 1; } } } else if (p == 1) { for (int i = 0; i < 2; i++) for (int j = 1; j <= n; j++) dp[i][j][0] = (s[1] == a[i][j]); } for (int i = 0; i < 2; i++) { for (int j = 1; j <= n; j++) { if (a[i][j] != s[p]) continue; dp[i][j][0] = (dp[i][j][0] + pre[i][j - 1][0] + pre[i][j - 1][1]) % mod; dp[i][j][1] = (dp[i][j][1] + pre[!i][j][0]) % mod; } } if ((m - p) % 2 == 0 && m - p > 2) { int len = (m - p) >> 1; for (int i = 0; i < 2; i++) { for (int j = 1; j <= n - len; j++) { if (gethsl(i, j + 1, j + len) * pw[len] + gethsr(!i, j + len, j + 1) != gethss(p + 1, m)) continue; for (int t = 0; t < 2; t++) ans = (ans + dp[i][j][t]) % mod; } } } else if (p == m) { for (int i = 0; i < 2; i++) for (int j = 1; j <= n; j++) for (int t = 0; t < 2; t++) ans = (ans + dp[i][j][t]) % mod; } } return ans; } int main() { pw[0] = 1; for (int i = 1; i <= 2005; i++) pw[i] = pw[i - 1] * base; scanf( %s , a[0] + 1); scanf( %s , a[1] + 1); n = strlen(a[0] + 1); scanf( %s , s + 1); m = strlen(s + 1); if (m == 1) { int cnt = 0; for (int i = 0; i < 2; i++) for (int j = 1; j <= n; j++) cnt += (a[i][j] == s[1]); cout << cnt << endl; return 0; } else if (m == 2) { int cnt = 0; for (int i = 0; i < 2; i++) for (int j = 1; j <= n; j++) cnt += (a[i][j] == s[1] && a[!i][j] == s[2]); for (int i = 0; i < 2; i++) for (int j = 1; j <= n; j++) cnt += (a[i][j] == s[1] && a[i][j + 1] == s[2]) + (a[i][j] == s[1] && a[i][j - 1] == s[2]); cout << cnt << endl; return 0; } for (int i = 1; i <= m; i++) hss[i] = hss[i - 1] * base + s[i]; long long ans = solve(); reverse(a[0] + 1, a[0] + n + 1); reverse(a[1] + 1, a[1] + n + 1); ans = (ans + solve()) % mod; if (m % 2 == 0) { int len = m >> 1; for (int i = 0; i < 2; i++) { for (int j = 0; j <= n - len; j++) { ans += (gethsl(i, j + 1, j + len) * pw[len] + gethsr(!i, j + len, j + 1) == gethss(1, m)); } } for (int i = 0; i < 2; i++) { for (int j = len + 1; j <= n + 1; j++) { ans += (gethsr(i, j - 1, j - len) * pw[len] + gethsl(!i, j - len, j - 1) == gethss(1, m)); } } } cout << ans % mod << endl; return 0; } |
//****************************************************************************************************
//*----------------Copyright (c) 2016 C-L-G.FPGA1988.Roger Wang. All rights reserved------------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : gt0000_digital_top.v
//Project Name : gt0000
//Description : the top module of gt0000
//Github Address : https://github.com/C-L-G/gt0000/trunk/ic/digital/rtl/gt0000_digital_top.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : Roger Wang
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : Roger Wang
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//dd.mm.yyyy - Author - Your log of change
//****************************************************************************************************
//02.09.2016 - Roger Wang - Add the clock switch test logic,rename the clk gen module to clk gen top.
//29.08.2016 - Roger Wang - Add the system auxiliary module,add the test logic.
//29.08.2016 - Roger Wang - The initial version.
//*---------------------------------------------------------------------------------------------------
`timescale 1ns/1ps
module gt0000_digital_top(
clk ,//01 In
rst_n ,//01 In
en ,//01 In
clk_sel ,//01 In
led_sel ,//01 In
led ,//08 Out
test_o //08 Out
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
`define CLK_TEST_EN
//************************************************************************************************
// 2.input and output declaration
//************************************************************************************************
input clk ;//the system clk = 20MHz
input rst_n ;//the system reset,low active
input en ;//enable signal
input clk_sel ;//clock select signal
input led_sel ;//led function select
output [07:00] led ;//8 bits led
output [07:00] test_o ;//8 bits test output
//************************************************************************************************
// 3.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the clk wire signal
//------------------------------------------------------------------------------------------------
wire div_2_clk ;//the divide 2 clock
wire div_4_clk ;//the divide 4 clock
wire clk_en ;//the clock enable signal
wire gated_clk ;//the clock gating signal
wire sw_clk ;//the selected clock by clk_sel
//------------------------------------------------------------------------------------------------
// 3.2 the clk wire signal
//------------------------------------------------------------------------------------------------
reg [07:00] aux_data_i ;//aux data input and output
wire [15:00] aux_data_o ;//aux data input and output
//------------------------------------------------------------------------------------------------
// 3.x the test logic
//------------------------------------------------------------------------------------------------
`ifdef CLK_TEST_EN
reg [03:00] test_cnt_1 ;//
reg [03:00] test_cnt_2 ;//
reg [03:00] test_cnt_3 ;//
`endif
//************************************************************************************************
// 4.Main code
//************************************************************************************************
assign led = led_sel ? aux_data_o[15:08] : aux_data_o[07:00] ;//
assign clk_en = en ;//
// assign aux_data_i = 8'b10101010 ;//
always @(posedge clk or negedge rst_n) begin : AUX_DATA_IN
if(!rst_n)
begin
aux_data_i <= 'd0;
end
else
begin
aux_data_i <= aux_data_i + 1'b1;
end
end
//------------------------------------------------------------------------------------------------
// 4.x the Test Logic
//------------------------------------------------------------------------------------------------
`ifdef CLK_TEST_EN
always @(posedge div_2_clk or negedge rst_n) begin : TEST_LOGIC_1
if(!rst_n)
begin
test_cnt_1 <= 'd0;
end
else
begin
test_cnt_1 <= test_cnt_1 + 1'b1;
end
end
always @(posedge div_4_clk or negedge rst_n) begin : TEST_LOGIC_2
if(!rst_n)
begin
test_cnt_2 <= 'd0;
end
else
begin
test_cnt_2 <= test_cnt_2 + 1'b1;
end
end
always @(posedge gated_clk or negedge rst_n) begin : TEST_LOGIC_3
if(!rst_n)
begin
test_cnt_3 <= 'd0;
end
else
begin
test_cnt_3 <= test_cnt_3 + 1'b1;
end
end
reg ccd_log_test_1;
reg ccd_log_test_2;
reg ccd_log_test_3;
reg ccd_log_test_4;
reg ccd_log_test_5;
always @(posedge clk or negedge rst_n) begin : CCD_LOG_1
if(!rst_n)
begin
ccd_log_test_1 <= 'd0;
end
else
begin
ccd_log_test_1 <= ~test_cnt_3[0];
end
end
always @(posedge div_4_clk or negedge rst_n) begin : CCD_LOG_2
if(!rst_n)
begin
ccd_log_test_2 <= 'd0;
end
else
begin
ccd_log_test_2 <= ~test_cnt_1[1];
end
end
always @(posedge clk or negedge rst_n) begin : CCD_LOG_3
if(!rst_n)
begin
ccd_log_test_3 <= 'd0;
end
else
begin
ccd_log_test_3 <= ~test_cnt_2[1];
end
end
always @(posedge clk or negedge rst_n) begin : CCD_LOG_4
if(!rst_n)
begin
ccd_log_test_4 <= 'd0;
end
else if(ccd_log_test_3)
begin
ccd_log_test_4 <= ((test_cnt_1 == 'd3) | (test_cnt_1 == 'd2) | (test_cnt_1 == 'd1)) | (test_cnt_1 & 'b101 == 'b010);
end
else
begin
ccd_log_test_4 <= ccd_log_test_4;
end
end
always @(posedge sw_clk or negedge rst_n) begin : CCD_LOG_5
if(!rst_n)
begin
ccd_log_test_5 <= 'd0;
end
else
begin
ccd_log_test_5 <= ccd_log_test_4;
end
end
assign test_o[0] = test_cnt_1[03] ;
assign test_o[1] = test_cnt_2[03] ;
assign test_o[2] = test_cnt_3[03] ;
// assign test_o[7:3] = {5{test_cnt_2[00]}} ;
assign test_o[3] = ccd_log_test_1 ;
assign test_o[4] = ccd_log_test_2 ;
assign test_o[5] = ccd_log_test_3 ;
assign test_o[6] = ccd_log_test_4 ;
assign test_o[7] = ccd_log_test_5 ;
`else
assign test_o = 8'b00000000 ;
`endif
//************************************************************************************************
// 5.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 5.1 the clk generate module
//------------------------------------------------------------------------------------------------
clk_gen_top clk_gen_inst(
.clk (clk ),//01 In
.rst_n (rst_n ),//01 In
.div_2_clk (div_2_clk ),//01 Out
.div_4_clk (div_4_clk ),//01 Out
.clk_en (clk_en ),//01 In
.clk_sel (clk_sel ),//01 In
.sw_clk (sw_clk ),//01 In
.gated_clk (gated_clk ) //01 Out
);
//------------------------------------------------------------------------------------------------
// 5.2 the system auxiliary module
//------------------------------------------------------------------------------------------------
sys_aux_module sys_aux_inst(
.aux_clk (clk ),//01 In
.aux_rst_n (rst_n ),//01 In
.aux_data_i (aux_data_i ),//08 In
.aux_data_o (aux_data_o ) //15 Out
);
//------------------------------------------------------------------------------------------------
// 5.3 the udp/ip stack module
//------------------------------------------------------------------------------------------------
`ifdef UDP
udpip_stack_module udpip_stack_inst(
.udp_clk (sys_clk ),//xx I/O
.clk_200mhz (adc_refclk_s ),//xx I/O
.clk_in_p (clk_in_p ),//xx I/O
.clk_in_p (clk_in_p ),//xx I/O
.udp_reset (udp_reset ),//xx I/O
.mgtclk_p (mgtclk_p ),//xx I/O
.phy_disable ( ) //xx I/O
);
`endif
endmodule
//****************************************************************************************************
//End of Mopdule
//****************************************************************************************************
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { int k; cin >> k; if (k % 2 != (i + j) % 2) k++; cout << k << ; } cout << endl; } } int main() { int n; cin >> n; while (n--) { solve(); } return 0; } |
#include <bits/stdc++.h> const int mod = 1e6 + 3; int add(int a, int b) { return (a += b) >= mod ? a -= mod : a; } int sub(int a, int b) { return add(a, mod - b); } int mul(int a, int b) { return int(1LL * a * b % mod); } int pow(int a, int64_t n) { int res = 1; while (n > 0) { if (n & 1) { res = mul(res, a); } a = mul(a, a); n >>= 1; } return res; } int inv(int a) { return pow(a, mod - 2); } int main() { const int n = 11; std::vector<int> f(n + 1); for (int i = 1; i <= n; ++i) { std::cout << ? << i << std::endl; std::cin >> f[i]; if (f[i] == 0) { std::cout << ! << i << std::endl; return 0; } } std::vector<std::vector<int> > a(1 + n, std::vector<int>(1 + n)); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { a[i][j] = pow(i, j - 1); } } for (int j = 1, i = 1; j <= n; ++j) { bool was = false; for (int k = i; k <= n; ++k) { if (a[k][j] != 0) { was = true; std::swap(a[i], a[k]); std::swap(f[i], f[k]); break; } } if (!was) { continue; } for (int k = i + 1; k <= n; ++k) { int coeff = mul(sub(0, inv(a[k][j])), a[i][j]); for (int t = j; t <= n; ++t) { a[k][t] = add(mul(coeff, a[k][t]), a[i][t]); } assert(a[k][j] == 0); f[k] = add(f[i], mul(coeff, f[k])); } i++; } std::vector<int> x(1 + n); for (int i = n; i >= 1; --i) { assert(a[i][i] != 0); int res = f[i]; for (int j = i + 1; j <= n; ++j) { res = sub(res, mul(a[i][j], x[j])); } x[i] = mul(res, inv(a[i][i])); } for (int i = 0; i < mod; ++i) { int p = 1, s = 0; for (int j = 1; j <= n; ++j) { s = add(s, mul(x[j], p)); p = mul(p, i); } if (s == 0) { std::cout << ? << i << std::endl; int v; std::cin >> v; assert(v == 0); std::cout << ! << i << std::endl; return 0; } } std::cout << ! << -1 << std::endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX_SZ = 105; struct request { int type; int r; int x, y, val; request(int type0, int r0) { type = type0; r = r0; } request(int type0, int x0, int y0, int val0) { type = type0; x = x0; y = y0; val = val0; } }; int main() { ios_base::sync_with_stdio(false); int n, m, q; cin >> n >> m >> q; int a[MX_SZ][MX_SZ]; memset(a, 0, sizeof(a)); vector<request> v; for (int i = 0; i < q; i++) { int type; cin >> type; if (type != 3) { int r; cin >> r; v.push_back(request(type, r)); } else { int x, y, val; cin >> x >> y >> val; v.push_back(request(type, x, y, val)); } } reverse(v.begin(), v.end()); int tmp[MX_SZ]; for (int i = 0; i < q; i++) { if (v[i].type == 1) { for (int j = 1; j <= m; j++) { if (j == m) { tmp[1] = a[v[i].r][j]; } else { tmp[j + 1] = a[v[i].r][j]; } } for (int j = 1; j <= m; j++) { a[v[i].r][j] = tmp[j]; } } if (v[i].type == 2) { for (int j = 1; j <= n; j++) { if (j == n) { tmp[1] = a[j][v[i].r]; } else { tmp[j + 1] = a[j][v[i].r]; } } for (int j = 1; j <= n; j++) { a[j][v[i].r] = tmp[j]; } } if (v[i].type == 3) { a[v[i].x][v[i].y] = v[i].val; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cout << a[i][j] << ; } cout << n ; } } |
/*
* freq_gen.v: Generates the frequency depending on the given period length while allowing manipulation using
* the inputs provided. Starts frequency generation on the first rising
* edge of the input clk after the period_stable input is 1.
* author: Till Mahlburg
* year: 2019-2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
module freq_gen (
/* global multiplier in the PLL, multiplied by 1000 */
input [31:0] M_1000,
/* global divisor in the PLL */
input [31:0] D,
/* output specific divisor in the PLL, multiplied by 1000 */
input [31:0] O_1000,
input RST,
input PWRDWN,
/* informs the module if the given period length (ref_period) can be trusted */
input period_stable,
input [31:0] ref_period_1000,
/* needed to achieve phase lock, by detecting the first rising edge of the clk
* and aligning the output clk to it */
input clk,
output reg out,
/* period length is multiplied by 1000 for higher precision */
output reg [31:0] out_period_length_1000);
/* tracks when to start the frequency generation */
reg start;
/* generate the wanted frequency */
always begin
if (PWRDWN) begin
out <= 1'bx;
start <= 1'bx;
#1;
end else if (RST) begin
out <= 1'b0;
start <= 1'b0;
#1;
end else if (ref_period_1000 > 0 && start) begin
/* The formula used is based on Equation 3-2 on page 72 of Xilinx UG472,
* but adjusted to calculate the period length not the frequency.
* Multiplying by 1.0 forces verilog to calculate with floating
* point number. Multiplying the out_period_length_1000 by 1000 is an
* easy solution to returning floating point numbers.
*/
out_period_length_1000 <= ((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0)) * 1000);
out <= ~out;
#(((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0))) / 2.0);
end else begin
out <= 1'b0;
#1;
end
end
/* detect the first rising edge of the input clk, after period_stable is achieved */
always @(posedge clk) begin
if (period_stable && !start) begin
#((ref_period_1000 / 1000.0) - 1);
start <= 1'b1;
end else if (!period_stable) begin
start <= 1'b0;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:51:47 08/30/2017
// Design Name: messbauer_generator
// Module Name: ./messbaue_test_environment/tests/messbauer_generator_testbench_channelsync.v
// Project Name: messbaue_test_environment
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: messbauer_generator
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module messbauer_generator_testbench_channelsync;
// Inputs
reg aclk;
reg areset_n;
// Outputs
wire start;
wire channel;
// Instantiate the Unit Under Test (UUT)
messbauer_generator # (.CHANNEL_TYPE(1)) // Start and channel are synchronous
uut
(
.aclk(aclk),
.areset_n(areset_n),
.start(start),
.channel(channel)
);
initial begin
// Initialize Inputs
aclk = 0;
areset_n = 0;
// Wait 100 ns for global reset to finish
#100;
areset_n = 1;
// Add stimulus here
end
always
begin
#20 aclk = ~aclk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k, p; cin >> n >> k >> p; bool odd = false, even = false; string ans = ; if (n % 2 == 0) even = true; else { odd = true; k--; } for (int i = 0; i < p; i++) { long long tmp; cin >> tmp; if (even) { if (tmp % 2 == 0 && n - 2 * k < tmp) ans += X ; else if (tmp % 2 == 1 && n - 2 * (k - n / 2) < tmp) ans += X ; else ans += . ; } else { if (tmp == n && k >= 0) { ans += X ; continue; } if (tmp % 2 == 0 && n - 2 * k <= tmp) ans += X ; else if (tmp % 2 == 1 && n - 2 * (k - n / 2) <= tmp) ans += X ; else ans += . ; } } cout << ans; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; template <typename T> bool mycomp(T x, T y) { return (x == y); } bool paircomp(const pair<long long int, long long int> &x, const pair<long long int, long long int> &y) { return x.second < y.second; } long long int f[6][6]; void solve() { long long int m; cin >> m; for (long long int i = 0; i < m; i++) { long long int x, y; cin >> x >> y; f[x][y] = 1; f[y][x] = 1; } for (long long int i = 1; i <= 5; i++) { for (long long int j = i + 1; j <= 5; j++) { for (long long int k = j + 1; k <= 5; k++) { if (f[i][j] && f[i][k] && f[j][k]) { cout << WIN ; return; } if (!f[i][j] && !f[i][k] && !f[j][k]) { cout << WIN n ; return; } } } } cout << FAIL ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t = 1; while (t--) { solve(); cout << endl; } } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: net2pci_dma_512x32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module net2pci_dma_512x32 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [31:0] q;
output [8:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "4"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "480"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "4"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "480"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 9 0 OUTPUT NODEFVAL "usedw[8..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 9 0 @usedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; vector<int> x[200]; int y[200], n, i, j, k, a, b, c, s, A, B; int main() { scanf( %d , &n); n *= 2; for (i = 1; i <= n; i++) scanf( %d , &k), x[k].push_back(i); for (i = 10; i <= 99; i++) if (x[i].size() == 1) { if (a > b) y[x[i][0]] = 2, b++; else y[x[i][0]] = 1, a++; } s = a * b; A = a; B = b; for (i = 10; i <= 99; i++) if (x[i].size() > 1) { s += a + b; c++; for (j = 0; j < x[i].size(); j++) { if (A > B) y[x[i][j]] = 2, B++; else y[x[i][j]] = 1, A++; } } s += c * c; printf( %d n , s); for (i = 1; i <= n; i++) printf( %d , y[i]); } |
#include <bits/stdc++.h> using namespace std; int n, centru; int l[10]; int r[10]; int vars(int i, int tip) { if (!tip) { if (l[i] <= centru && centru <= r[i]) return centru - l[i]; else if (r[i] < centru) return r[i] - l[i] + 1; return 0; } else if (tip == 1) return ((bool)(l[i] <= centru && centru <= r[i])); else { if (l[i] <= centru && centru <= r[i]) return r[i] - centru; else if (centru < l[i]) return r[i] - l[i] + 1; return 0; } } int tip[10]; int _s[3]; double sum; void backtr(int poz) { if (poz == (n + 1)) { if (!_s[1]) return; if (_s[2] >= 2) return; if (_s[2] == 0) { if (_s[1] == 1) return; } double prod = 1; for (int i = 1; i <= n; i++) prod *= vars(i, tip[i]); sum += centru * prod; return; } for (int i = 0; i < 3; i++) { _s[i]++; tip[poz] = i; backtr(poz + 1); _s[i]--; } } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> l[i] >> r[i]; for (int i = 1; i <= 10000; i++) { centru = i; backtr(1); } for (int i = 1; i <= n; i++) { sum /= (r[i] - l[i] + 1); } cout << fixed << setprecision(12) << sum << n ; return 0; } |
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_rld_if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : QDRII+ SRAM / RLDRAM II SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: qdr_rld_if_post_fifo.v,v 1.1 2011/06/02 08:36:28 mishra Exp $
**$Date: 2011/06/02 08:36:28 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/qdriiplus_sram/verilog/rtl/phy/qdr_rld_if_post_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v2_0_qdr_rld_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
reg my_empty;
reg my_full;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty, my_full})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 1'b0;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_empty <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_full <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty, my_full);
rd_ptr <= 2'bxx;
wr_ptr <= 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
wire [WIDTH-1:0] mem_out;
assign d_out = my_empty ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in & my_empty;
always @(posedge clk)
if (rst) begin
my_empty <= 1'b1;
my_full <= 1'b0;
rd_ptr <= 'b0;
wr_ptr <= 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty && !my_full && rd_en_in && !empty_in) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, ~empty_in);
end
wire wr_en;
assign wr_en = (!rd_en_in & !empty_in & !my_full)
| (rd_en_in & !empty_in & !my_empty);
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem [rd_ptr];
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 20351 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16384,
w16383,
w4096,
w20479,
w128,
w20351;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w16383 = w16384 - w1;
assign w16384 = w1 << 14;
assign w20351 = w20479 - w128;
assign w20479 = w16383 + w4096;
assign w4096 = w1 << 12;
assign o_data0 = w20351;
//multiplier_block area estimate = 4567.14715007059;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> odd; int main() { int n, t; cin >> n; long long cnt = 0, res = -1e9; for (int i = 0; i < n; i++) { cin >> t; if (abs(t) % 2 == 1) odd.push_back(t); else if (t > 0) cnt += t; } sort(odd.begin(), odd.end()); bool flag = 0; int sz = odd.size(); for (int i = sz - 1; i >= 0; i--) { cnt += odd[i]; if (abs(cnt) % 2 == 1) res = max(cnt, res); } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n = 0; int max = 0; int cur = 0; cin >> n; string students[n]; for (int i = 0; i < n; ++i) { cin >> students[i]; } for (int i = 0; i < 7; ++i) { cur = 0; for (int j = 0; j < n; ++j) { if (students[j][i] == 1 ) { cur++; } } if (cur > max) { max = cur; } } cout << max; return 0; } |
// file: Clock_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> v; int n, m; void addOne(string &res) { int i = (int)res.size() - 1; while (res[i] == 1 ) { res[i--] = 0 ; } res[i] = 1 ; } string toBinary(long long k) { if (k == 0) { return string(m, 0 ); } string res; while (k) { res.push_back((k % 2) + 0 ); k >>= 1; } while (res.size() != m) { res.push_back( 0 ); } reverse(res.begin(), res.end()); return res; } void findRes(string &res, long long k) { long long x = max(k - 100, 0ll); res = toBinary(x); int a = lower_bound(v.begin(), v.end(), res) - v.begin(); long long rem = min(100ll, k) + a + (a != n && v[a] == res); while (rem) { addOne(res); rem -= !binary_search(v.begin(), v.end(), res); } } int main() { int t; cin >> t; while (t--) { cin >> n >> m; v.resize(n); for (auto &x : v) { cin >> x; } sort(v.begin(), v.end()); string res(m, 0 ); findRes(res, ((1ll << m) - n - 1) / 2); cout << res << endl; } cin.ignore(2); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); clock_t startTime; double getCurrentTime() { return (double)(clock() - startTime) / CLOCKS_PER_SEC; } void solve() { int n; cin >> n; vector<int> a(n); int totalXor = 0; for (int i = 0; i < n; ++i) { cin >> a[i]; totalXor ^= a[i]; } if (totalXor == 1) { cout << NO n ; return; } auto solve = [](int l, int r) { assert((r - l + 1) % 2 == 1); vector<int> res; for (int i = l; i <= r - 2; i += 2) { res.push_back(i); } for (int i = r - 4; i >= l; i -= 2) { res.push_back(i); } return res; }; if (n % 2 == 1) { auto res = solve(0, n - 1); cout << YES n ; cout << res.size() << n ; for (auto x : res) { cout << x + 1 << ; } cout << n ; } else { bool ok = false; int prefXor = 0; for (int i = 0; i < n; ++i) { prefXor ^= a[i]; if (prefXor == 0 && i % 2 == 0) { auto res1 = solve(0, i); auto res2 = solve(i + 1, n - 1); cout << YES n ; cout << res1.size() + res2.size() << n ; for (auto x : res1) { cout << x + 1 << ; } for (auto x : res2) { cout << x + 1 << ; } cout << n ; ok = true; break; } } if (!ok) cout << NO n ; } } int main() { startTime = clock(); ios_base::sync_with_stdio(false); cin.tie(nullptr); int tests; cin >> tests; for (int t = 0; t < tests; ++t) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int n, x; cin >> n >> x; vector<int> a(n), b(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; sort(a.begin(), a.end()); sort(b.rbegin(), b.rend()); int f = 0; for (int i = 0; i < n; i++) { if (a[i] + b[i] > x) { f = 1; break; } } if (f) cout << No << endl; else cout << Yes << endl; } } |
`timescale 1 ps / 1 ps
module Sobel (
input clk,
input rst,
output [31:0] data_fifo_out,
output data_valid_fifo_out,
input wire [8:0] usedw_fifo_out,
output wire[31:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[3:0] ram_r_byteenable,
output wire ram_r_read,
input wire[31:0] ram_r_readdata,
output wire[5:0] ram_r_burstcount,
input start,
output endf,
input [31:0] base_add
);
parameter DATA_WIDTH=32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg [18:0] pixel_counter;
reg [1:0] run;
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (pixel_counter == 0) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
pixel_counter <= 384000;
end else begin
if (data_valid_fifo_out) begin
pixel_counter <= pixel_counter - 1;
end
end
end
wire [12:0] cache_valid_lines;
wire cache_free_line;
wire [7:0] cache_pixel;
Sobel_cache Sobel_cache_instance (
.clk(clk),
.rst(rst),
.start(start),
.base_add(base_add),
.rdaddress(add_pix_around),
.valid_lines(cache_valid_lines),
.free_line(cache_free_line),
.q(cache_pixel),
.ram_r_address(ram_r_address),
.ram_r_waitrequest(ram_r_waitrequest),
.ram_r_readdatavalid(ram_r_readdatavalid),
.ram_r_byteenable(ram_r_byteenable),
.ram_r_read(ram_r_read),
.ram_r_readdata(ram_r_readdata),
.ram_r_burstcount(ram_r_burstcount)
);
//*********************************************************************Sobel Implementation*************************************************************************
reg [3:0] stage;
wire go_sobel;
assign go_sobel = (stage == 0) & (pixel_counter > 0) & (run == 1) & (usedw_fifo_out < FIFO_DEPTH) & (cache_valid_lines > 13'd2399);
assign cache_free_line = (sobel_col == 799) & (stage == 2) & (sobel_line > 0) & (sobel_line < 478);
reg [9:0] sobel_col;
reg [8:0] sobel_line;
reg [13:0] add_main_pix;
always @(posedge clk) begin
if (start == 1) begin
sobel_col <= 0;
sobel_line <= 0;
add_main_pix <= 0;
end else begin
if (stage == 3) begin
if (sobel_col == 799) begin
sobel_line <= sobel_line + 1;
sobel_col <= 0;
end else begin
sobel_col <= sobel_col + 1;
end
if (add_main_pix == 7999) begin
add_main_pix <= 0;
end else begin
add_main_pix <= add_main_pix + 1;
end
end
end
end
reg [13:0] add_pix_around;
always @(posedge clk) begin
if (go_sobel == 1) begin
if (sobel_col == 0) begin
if (add_main_pix < 800) begin
add_pix_around <= 7200 + add_main_pix;
end else begin
add_pix_around <= add_main_pix - 800;
end
end else begin
if (add_main_pix < 800) begin
add_pix_around <= 7201 + add_main_pix;
end else begin
add_pix_around <= add_main_pix - 799;
end
end
end
if (stage == 1) begin
if (pending_reads != 4) begin
if (add_pix_around > 7199) begin
add_pix_around <= add_pix_around - 7200;
end else begin
add_pix_around <= add_pix_around + 800;
end
end
if (pending_reads == 4) begin
if (add_pix_around > 1598) begin
add_pix_around <= add_pix_around - 1599;
end else begin
add_pix_around <= add_pix_around + 6401;
end
end
end
end
reg [3:0] pending_reads;
always @(posedge clk) begin
if (go_sobel == 1) begin
if (sobel_col == 0) begin
pending_reads <= 6;
end else begin
pending_reads <= 3;
end
end else begin
if (stage == 1) begin
pending_reads <= pending_reads - 1;
end
end
end
reg [2:0] g_col;
reg [2:0] g_line;
always @(posedge clk) begin
if (start == 1) begin
g_col <= 1;
g_line <= 0;
end else begin
if (stage == 1) begin
if (g_line == 2) begin
g_col <= g_col + 1;
g_line <= 0;
end else begin
g_line <= g_line + 1;
end
end
if (stage == 3) begin
if (sobel_col == 799) begin
g_col <= 1;
g_line <= 0;
end else begin
g_col <= 2;
g_line <= 0;
end
end
end
end
wire jump_stage2;
assign jump_stage2 = (pending_reads == 0) & (stage == 1);
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
stage <= 0;
end else begin
if ((start == 1) | (stage == 8)) begin
stage <= 0;
end else begin
if (go_sobel == 1) begin
stage <= 1;
end
if (jump_stage2 == 1) begin
stage <= 2;
end else begin
if (stage > 1) begin
stage <= stage + 1;
end
end
end
end
end
wire out_bound;
assign out_bound = ((sobel_col + g_col - 2) == -1) | ((sobel_col + g_col - 2) == 800) | ((sobel_line + g_line - 2) == -1) | ((sobel_line + g_line - 2) == 480);
reg [10:0] gx;
reg [9:0] gx2;
reg [10:0] gy;
reg [9:0] gy2;
reg [20:0] gxgy;
reg [7:0] sobel_r;
wire[10:0] sqrt_r;
reg [7:0] g[0:2][0:2];
always @(posedge clk) begin
if (go_sobel == 1) begin
if (sobel_col != 0) begin
g[0][0] <= g[1][0];
g[0][1] <= g[1][1];
g[0][2] <= g[1][2];
g[1][0] <= g[2][0];
g[1][1] <= g[2][1];
g[1][2] <= g[2][2];
end else begin
g[0][0] <= 0;
g[0][1] <= 0;
g[0][2] <= 0;
end
end
if (stage == 1) begin
if (out_bound == 0) begin
g[g_col][g_line] <= cache_pixel;
end else begin
g[g_col][g_line] <= 0;
end
end
if (stage == 2) begin
gx <= g[0][0] + {g[0][1], 1'b0} + g[0][2];
gx2 <= g[2][0] + {g[2][1], 1'b0} + g[2][2];
gy <= g[0][0] + {g[1][0], 1'b0} + g[2][0];
gy2 <= g[0][2] + {g[1][2], 1'b0} + g[2][2];
end
if (stage == 3) begin
gx <= (gx > gx2)? gx - gx2 : gx2 - gx; // I need the absolute value
gy <= (gy > gy2)? gy - gy2 : gy2 - gy; //
end
if (stage == 4) begin
gxgy <= gx + gy;
end
if (stage == 5) begin
sobel_r <= gxgy > 255? 255 : gxgy;
end
if (stage == 7) begin
sobel_r <= 255 - sobel_r;
end
end
//------------------------------------------------------------------------------------------------------------------------------------------------------------------
assign data_fifo_out = {8'd0, {3{sobel_r}}};
assign data_valid_fifo_out = (run == 1) & (stage == 8);
assign endf = (run == 2);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_SYMBOL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_SYMBOL_V
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Mon Nov 5 13:19:54 EST 2012
//
//
// Ports:
// Name I/O size props
// RDY_ledDrive O 1 const
// led O 5
// CLK I 1 clock
// RST_N I 1 reset
// ledDrive_i I 5 reg
// EN_ledDrive I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkLedN210(CLK,
RST_N,
ledDrive_i,
EN_ledDrive,
RDY_ledDrive,
led);
input CLK;
input RST_N;
// action method ledDrive
input [4 : 0] ledDrive_i;
input EN_ledDrive;
output RDY_ledDrive;
// value method led
output [4 : 0] led;
// signals for module outputs
wire [4 : 0] led;
wire RDY_ledDrive;
// register doInit
reg doInit;
wire doInit$D_IN, doInit$EN;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register ledReg
reg [4 : 0] ledReg;
wire [4 : 0] ledReg$D_IN;
wire ledReg$EN;
// remaining internal signals
reg [4 : 0] CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1;
wire [4 : 0] x__h621, x__h622;
// action method ledDrive
assign RDY_ledDrive = 1'd1 ;
// value method led
assign led =
doInit ?
CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 :
~x__h621 ;
// register doInit
assign doInit$D_IN = 1'd0 ;
assign doInit$EN = freeCnt > 32'h08000000 ;
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register ledReg
assign ledReg$D_IN = ledDrive_i ;
assign ledReg$EN = EN_ledDrive ;
// remaining internal signals
assign x__h621 = x__h622 | ledReg ;
assign x__h622 = freeCnt[23] ? 5'h01 : 5'h0 ;
always@(freeCnt)
begin
case (freeCnt[25:23])
3'd0, 3'd1, 3'd2, 3'd6, 3'd7:
CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 =
freeCnt[21] ? 5'd3 : 5'd31;
3'd3: CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 = 5'd27;
3'd4: CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 = 5'd19;
3'd5: CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 = 5'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
doInit <= `BSV_ASSIGNMENT_DELAY 1'd1;
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ledReg <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (doInit$EN) doInit <= `BSV_ASSIGNMENT_DELAY doInit$D_IN;
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (ledReg$EN) ledReg <= `BSV_ASSIGNMENT_DELAY ledReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
doInit = 1'h0;
freeCnt = 32'hAAAAAAAA;
ledReg = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkLedN210
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file snescmd_buf.v when simulating
// the core, snescmd_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module snescmd_buf(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [8 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 3e18 + 5; int N; long long pt[100005][3]; long long ans[3]; pair<long long, long long> gSeg[4]; void input() { cin >> N; for (int i = 0; i < (N); i++) cin >> pt[i][0] >> pt[i][1] >> pt[i][2]; } inline long long mod2(long long x) { return (x % 2 + 2) % 2; } bool check(long long v) { for (int rem = 0; rem < (2); rem++) { pair<long long, long long> seg[4]; for (int i = 0; i < (4); i++) { seg[i].first = gSeg[i].first - v; seg[i].second = gSeg[i].second + v; if (mod2(seg[i].first) != rem) seg[i].first++; if (mod2(seg[i].second) != rem) seg[i].second--; } int fail = 0; for (int i = 0; i < (4); i++) if (seg[i].first > seg[i].second) { fail = 1; } if (fail) continue; if (seg[0].second < seg[1].first + seg[2].first + seg[3].first) continue; if (seg[0].first > seg[1].second + seg[2].second + seg[3].second) continue; long long sum = seg[1].first + seg[2].first + seg[3].first; for (int i = (1); i <= (3); i++) { if (sum >= seg[0].first) break; if (sum + seg[i].second - seg[i].first < seg[0].first) { sum += seg[i].second - seg[i].first; seg[i].first = seg[i].second; } else { seg[i].first += seg[0].first - sum; if (mod2(seg[i].first) != rem) seg[i].first++; if (seg[i].first > seg[i].second) { seg[i].first--; sum--; } else { break; } } } ans[0] = (seg[2].first + seg[3].first) / 2; ans[1] = (seg[1].first + seg[3].first) / 2; ans[2] = (seg[1].first + seg[2].first) / 2; assert(mod2(seg[2].first + seg[3].first) == 0); assert(mod2(seg[1].first + seg[3].first) == 0); assert(mod2(seg[1].first + seg[2].first) == 0); return true; } return false; } void solve() { for (int i = 0; i < (4); i++) gSeg[i] = pair<long long, long long>(-INF, INF); for (int i = 0; i < (N); i++) { long long x = pt[i][0]; long long y = pt[i][1]; long long z = pt[i][2]; gSeg[0].first = max(gSeg[0].first, x + y + z); gSeg[0].second = min(gSeg[0].second, x + y + z); gSeg[1].first = max(gSeg[1].first, -x + y + z); gSeg[1].second = min(gSeg[1].second, -x + y + z); gSeg[2].first = max(gSeg[2].first, x - y + z); gSeg[2].second = min(gSeg[2].second, x - y + z); gSeg[3].first = max(gSeg[3].first, x + y - z); gSeg[3].second = min(gSeg[3].second, x + y - z); } long long l = 0, r = 4e18 + 5; while (l < r) { long long m = (l + r) / 2; if (check(m)) r = m; else l = m + 1; } assert(check(l)); cout << ans[0] << << ans[1] << << ans[2] << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int ts; cin >> ts; for (int t = 0; t < (ts); t++) { input(); solve(); } return 0; } |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_1_0 (
dout
);
output wire [1-1 : 0] dout;
xlconstant #(
.CONST_VAL(1'd0),
.CONST_WIDTH(1)
) inst (
.dout(dout)
);
endmodule
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-11-01 16:15:50
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA_STAGE_1
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > ans; bool is_prime(int v) { if (v == 1 || v == 0) return 0; for (int i = 2; i * i <= v; i++) { if (v % i == 0) return 0; } return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long cnt = n - 1; ans.push_back(make_pair(n, 1)); for (int i = 2; i <= n; i++) { ans.push_back(make_pair(i, i - 1)); } for (int i = 1; i <= n / 2; i++) { if (is_prime(ans.size())) break; ans.push_back(make_pair(i, i + n / 2)); ++cnt; } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) { cout << ans[i].first << << ans[i].second << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100 * 1000; int n; long long dp[2][N]; int c[N], a[N]; bool read() { if (!(cin >> n)) return false; for (int i = 0; i < int(n); ++i) { cin >> a[i]; c[i] = a[i]; } return true; } void upd(long long &a, long long b) { if (a == -1) a = b; a = min(a, b); } void solve() { int t = 0; sort(c, c + n); memset(dp, -1, sizeof dp); dp[t][0] = 0; for (int i = 0; i < int(n); ++i) { memset(dp[!t], -1, sizeof(dp[!t])); long long mn = -1; for (int j = 0; j < int(n); ++j) { if (dp[t][j] != -1) upd(mn, dp[t][j]); upd(dp[!t][j], mn + abs(a[i] - c[j])); } t = !t; } long long res = -1; for (int i = 0; i < int(n); ++i) if (dp[t][i] != -1) upd(res, dp[t][i]); cout << res << endl; } int main() { while (read()) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; class Debugger { public: Debugger(const std::string& _separator = , ) : first(true), separator(_separator) {} template <typename ObjectType> Debugger& operator,(const ObjectType& v) { if (!first) cerr << separator; cerr << v; first = false; return *this; } ~Debugger() { cerr << n ; } private: bool first; string separator; }; template <typename T1, typename T2> inline ostream& operator<<(std::ostream& os, const std::pair<T1, T2>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline ostream& operator<<(ostream& os, const vector<T>& v) { bool first = true; os << [ ; for (unsigned long long i = 0; i < v.size(); i++) { if (!first) os << , ; os << v[i]; first = false; } return os << ] ; } template <typename T> inline ostream& operator<<(ostream& os, const set<T>& v) { bool first = true; os << [ ; for (typename set<T>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } template <typename T1, typename T2> inline ostream& operator<<(ostream& os, const map<T1, T2>& v) { bool first = true; os << [ ; for (typename map<T1, T2>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } long long n, m; long long x, y; long long xx, yy; set<long long> elementi; map<long long, long long> used; int main() { ios_base::sync_with_stdio(0); ; cin >> n; for (long long i = 1; i <= n; i++) { cin >> x >> y; elementi.insert(x); used[x] = max(used[x], y); } cin >> m; for (long long i = 1; i <= m; i++) { cin >> x >> y; elementi.insert(x); used[x] = max(used[x], y); } long long cnt = 0; for (const auto& i : elementi) { cnt += used[i]; } cout << cnt << n ; return 0; } |
#include <bits/stdc++.h> const int MOD = 1e9 + 7; inline int addmod(int a, int b) { return (a + b) % MOD; } const int MAXN = 105; const int MAXM = 10005; int cnt[MAXN]; int n, a[MAXN]; int f[MAXN][MAXM]; int com[MAXN][MAXN]; int main() { for (int i = 0; i < MAXN; i++) { com[i][0] = 1; for (int j = 1; j <= i; j++) { com[i][j] = addmod(com[i - 1][j], com[i - 1][j - 1]); } } scanf( %d , &n); f[0][0] = 1; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); cnt[a[i]]++; for (int x = 100; x >= 1; x--) { for (int y = a[i]; y <= 10000; y++) f[x][y] = addmod(f[x][y], f[x - 1][y - a[i]]); } } int tot = 0; for (int i = 0; i < MAXN; i++) if (cnt[i] > 0) tot++; int ans = 0; for (int i = 0; i <= 100; i++) { int sum = 0; for (int j = 1; j <= cnt[i]; j++) { sum += i; if (f[j][sum] == com[cnt[i]][j]) { ans = std::max(ans, j); if (j == cnt[i] && tot == 2) ans = n; } } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(T x) { return x * x; } const double PI = acos(-1.0); using namespace std; double dp[1005][1005]; int main(void) { int n, m; scanf( %d %d , &n, &m); if (n == 1) { puts( 1.0000000 ); return 0; } dp[0][0] = 1; for (int i = 1; i <= n - 1; i++) { dp[i][0] = dp[i - 1][0] * (1 - (m - 1.0) / (n * m - i)); for (int j = 1; j <= i && j <= m; j++) { dp[i][j] = dp[i - 1][j - 1] * (m - j + 0.0) / (n * m - i) + dp[i - 1][j] * (1 - (m - j - 1.0) / (n * m - i)); } } double ans = 0; for (int i = 0; i <= n - 1; i++) { ans += dp[n - 1][i] * (i + 1.0) / n; } printf( %.10lf n , ans); return 0; } |
#include <bits/stdc++.h> int n, arr[1005][3], sum, cnt; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d %d %d , &arr[i][0], &arr[i][1], &arr[i][2]); for (int i = 0; i < n; i++) { for (int j = 0; j < 3; j++) sum += arr[i][j]; if (sum >= 2) cnt++; sum = 0; } printf( %d , cnt); return 0; } |
#include <complex> #include <queue> #include <set> #include <unordered_set> #include <list> #include <chrono> #include <random> #include <iostream> #include <algorithm> #include <cmath> #include <string> #include <vector> #include <map> #include <unordered_map> #include <stack> #include <iomanip> #include <fstream> using namespace std; const int N = 200001; int cntA[N], cntB[N], A[N], B[N]; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int lcm(int a, int b) { return a * b / gcd(a, b); } bool isPrime(int n) { int d = 2; while (d * d <= n && n % d) d++; return n - 1 && d * d > n; } void localTest() { int a, b, k; cin >> a >> b >> k; memset(A, 0, N); memset(B, 0, N); memset(cntA, 0, N); memset(cntB, 0, N); for (int i = 0; i < k; i++) { cin >> A[i]; cntA[A[i]]++; } for (int i = 0; i < k; i++) { cin >> B[i]; cntB[B[i]]++; } long long ans = 0; for (int i = 0; i < k; i++) ans += k - cntA[A[i]] - cntB[B[i]] + 1; cout << ans / 2 << n ; //не недооценивай первую задачу, если она для первого и второго дивизионов //внимательно читай условия //всё будет хорошо } int main() { cin.tie(nullptr)->sync_with_stdio(false); int globalTests = 1; cin >> globalTests; while (globalTests--) localTest(); } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g_rx #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Status
*/
output wire [1:0] rx_start_packet,
output wire [6:0] rx_error_count,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH * 32 != DATA_WIDTH) begin
$error("Error: HDR_WIDTH must be equal to DATA_WIDTH/32");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_baser_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
axis_baser_rx_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRBP_PP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_TB_V
`define SKY130_FD_SC_HS__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_TB_V
|
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
module main;
parameter use_wid = 4;
reg [use_wid-1:0] d;
wire [use_wid-1:0] q;
reg clk;
defparam dut.wid = use_wid;
B dut (.Q(q), .D(d), .C(clk));
initial begin
clk = 0;
d = 4'b0000;
#1 clk = 1;
#1 clk = 0;
if (q !== 4'b0000) begin
$display("FAILED -- d=%b, q=%b", d, q);
$finish;
end
d = 4'b1111;
#1 clk = 1;
#1 clk = 0;
if (q !== 4'b1111) begin
$display("FAILED -- d=%b, q=%b", d, q);
$finish;
end
$display("PASSED");
end
endmodule // main
/*
* although the wid paramter is default to 3 in this module, the point
* of this test is to have the instantiating module (main) give a
* different value and have that value properly handlued in all the
* situations of this module.
*/
module B
#(parameter wid = 3)
(output [wid-1:0] Q,
input [wid-1:0] D,
input C);
// the override from main will cause this to be a width of 4.
prim U [wid-1:0] (Q, D, C);
//prim U [wid-1:0] (.Q(Q), .D(D), .C(C));
endmodule // B
module prim(output reg Q, input D, C);
always @(posedge C)
Q <= D;
endmodule // prim
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; char c = getchar(); int fh = 1; while (!isdigit(c)) { if (c == - ) fh = -1; c = getchar(); } while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); x *= fh; } struct Info { int nu, ne; } a[400010 * 2], na[400010 * 2]; struct seg { int l, r, mi; } t[400010 * 4]; int num, b[400010], m, n, x, y, lo[400010], df[400010], su, q, nu, nb[400010], nst, st[400010], va[400010], f[400010], d[400010], si[400010], so[400010], tp[400010], bi[400010]; multiset<int> v[400010]; void jb(int x, int y) { a[++num].nu = y; a[num].ne = b[x]; b[x] = num; } void jnb(int x, int y) { na[++nu].nu = y; na[nu].ne = nb[x]; nb[x] = nu; } void tarjan(int x, int fa) { lo[x] = df[x] = ++num; st[++nst] = x; for (int y = nb[x]; y; y = na[y].ne) { if (na[y].nu != fa) { if (!df[na[y].nu]) { tarjan(na[y].nu, x); lo[x] = min(lo[x], lo[na[y].nu]); if (lo[na[y].nu] >= df[x]) { jb(x, ++su); jb(su, x); while (st[nst] != na[y].nu) { jb(su, st[nst]); jb(st[nst], su); nst--; } jb(su, st[nst]); jb(st[nst], su); nst--; } } else lo[x] = min(lo[x], df[na[y].nu]); } } } void dfs(int x, int fa, int dep) { f[x] = fa; d[x] = dep; si[x] = 1; for (int y = b[x]; y; y = a[y].ne) { if (a[y].nu != fa) { dfs(a[y].nu, x, dep + 1); if (x > n) { v[x].insert(va[a[y].nu]); } si[x] += si[a[y].nu]; if (si[a[y].nu] > si[so[x]]) so[x] = a[y].nu; } } } void dfs1(int x) { bi[x] = ++num; if (so[x] != 0) { tp[so[x]] = tp[x]; dfs1(so[x]); } for (int y = b[x]; y; y = a[y].ne) { if (a[y].nu != f[x] && a[y].nu != so[x]) { tp[a[y].nu] = a[y].nu; dfs1(a[y].nu); } } } int quem(int nu, int l, int r) { if (t[nu].l == l && t[nu].r == r) return t[nu].mi; int mid = (t[nu].l + t[nu].r) / 2; if (l > mid) return quem(nu * 2 + 1, l, r); if (r <= mid) return quem(nu * 2, l, r); return min(quem(nu * 2, l, mid), quem(nu * 2 + 1, mid + 1, r)); } int que(int x, int y) { int no = 1e9; while (tp[x] != tp[y]) { if (d[tp[x]] < d[tp[y]]) swap(x, y); no = min(no, quem(1, bi[tp[x]], bi[x])); x = f[tp[x]]; } if (d[x] > d[y]) swap(x, y); no = min(no, quem(1, bi[x], bi[y])); if (x > n) no = min(no, quem(1, bi[f[x]], bi[f[x]])); return no; } void build(int nu, int l, int r) { t[nu].l = l; t[nu].r = r; t[nu].mi = 0; if (l != r) { build(nu * 2, l, (l + r) / 2); build(nu * 2 + 1, (l + r) / 2 + 1, r); t[nu].mi = min(t[nu * 2].mi, t[nu * 2 + 1].mi); } } int man(int x) { multiset<int>::iterator i = v[x].begin(); return *i; } void chan(int nu, int we, int x) { if (t[nu].l == t[nu].r) { t[nu].mi = x; return; } if (we <= (t[nu].l + t[nu].r) / 2) chan(nu * 2, we, x); else chan(nu * 2 + 1, we, x); t[nu].mi = min(t[nu * 2].mi, t[nu * 2 + 1].mi); } void work(int x, int y, int z) { multiset<int>::iterator i = v[x].find(y); v[x].erase(i); v[x].insert(z); chan(1, bi[x], man(x)); } int main() { read(n); read(m); read(q); su = n; for (int i = 1; i <= n; i++) read(va[i]); for (int i = 1; i <= m; i++) { read(x); read(y); jnb(x, y); jnb(y, x); } for (int i = 1; i <= n; i++) if (!df[i]) tarjan(i, 0); dfs(1, 0, 1); tp[1] = 1; num = 0; dfs1(1); build(1, 1, su); for (int i = 1; i <= su; i++) if (i <= n) chan(1, bi[i], va[i]); else chan(1, bi[i], man(i)); while (q--) { char ch = getchar(); while (ch != A && ch != C ) ch = getchar(); if (ch == A ) { read(x); read(y); printf( %d n , que(x, y)); } else { read(x); read(y); chan(1, bi[x], y); if (f[x]) work(f[x], va[x], y); va[x] = y; } } return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:64000000 ) const int N = 5e3 + 10; int n; int t[N]; int cnt[N]; int res[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i <= n; i++) { cin >> t[i]; } for (int r = 1; r <= n; r++) { memset(cnt, 0, sizeof(cnt)); int mxCnt = 0, val = -1; for (int l = r; l >= 1; l--) { cnt[t[l]]++; if (cnt[t[l]] > mxCnt || (cnt[t[l]] == mxCnt && t[l] < val)) { mxCnt = cnt[t[l]]; val = t[l]; } res[val]++; } } for (int i = 1; i <= n; i++) { cout << res[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) int t, h[2000010], v[2000010 * 2], nxt[2000010 * 2], ec, in[2000010], n, a, b; char s[2000010]; void add(int x, int y) { v[++ec] = y; in[y]++; nxt[ec] = h[x]; h[x] = ec; } void adj(int x, int y) { add(x, y); add(y, x); } int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); ec = 0; memset(h, 0, sizeof(int) * (n + 5)); memset(in, 0, sizeof(int) * (n + 5)); for (int i = 1; i < n; i++) { scanf( %d%d , &a, &b); adj(a, b); } scanf( %s , s + 1); if (n < 3) { printf( Draw n ); continue; } if (n == 3) { int c = 0; for (int i = 1; i <= n; i++) if (s[i] == W ) c++; if (c >= 2) printf( White n ); else printf( Draw n ); continue; } int ct = 0, r = 0, on = n; for (int i = 1; i <= on; i++) if (s[i] == W ) { add(i, ++n); h[n] = 0; add(n, i); in[n] = 3; } for (int i = 1; i <= n; i++) { if (in[i] > 3) r = 1; else if (in[i] == 3) { ct++; int cc = 0; for (int j = h[i]; j; j = nxt[j]) if (in[v[j]] >= 2) cc++; r |= cc >= 2; } } if (ct == 2 && (n & 1)) r = 1; printf(r ? White n : Draw n ); } } |
#include <bits/stdc++.h> using namespace std; int main() { string s1; int tc; cin >> tc; getchar(); while (tc--) { cin >> s1; for (int i = 0; i < s1.length(); i += 2) { cout << s1[i]; } cout << s1[s1.size() - 1] << endl; } } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-8, pi = acos(-1); const int SZ = 100050, INF = 0x7FFFFFFF; vector<int> mp[SZ]; int res, pos; int in[SZ]; void dfs(int u, int par) { int cur = 0; for (int i = 0; i < mp[u].size(); ++i) { int to = mp[u][i]; if (to != par) { ++cur; dfs(to, u); } } if (par == -1 && cur == 2) --cur; if (cur > 1) { pos = u; ++res; } } int main() { std::ios::sync_with_stdio(0); int casenum; { int n; cin >> n; for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; mp[u].push_back(v); mp[v].push_back(u); ++in[u]; ++in[v]; } dfs(1, -1); if (res > 1) cout << No << endl; else if (res == 0) { cout << Yes n1 << endl; vector<int> tmp; for (int i = 1; i <= n; ++i) { if (in[i] == 1) { tmp.push_back(i); } } cout << tmp[0] << << tmp[1] << endl; } else { cout << Yes << endl; int num = count(in + 1, in + 1 + n, 1); cout << num << endl; for (int i = 1; i <= n; ++i) { if (in[i] == 1) cout << i << << pos << endl; } } } return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This is a n-entry n-exit loop limiter module, n=1, 2, ...
module acl_loop_limiter #(
parameter ENTRY_WIDTH = 8,// 1 - n
EXIT_WIDTH = 8, // 0 - n
THRESHOLD = 100,
THRESHOLD_NO_DELAY = 0, // Delay from i_valid/stall to o_valid/stall;
// default is 0, because setting it to 1 will hurt FMAX
// e.g. Assuming at clock cycle n, the internal counter is full (valid_allow=0); i_stall and i_stall_exit both remain 0
// | THRESHOLD_NO_DELAY = 0 | THRESHOLD_NO_DELAY = 1
//time i_valid i_valid_exit | valid_allow o_valid | valid_allow o_valid
//n 2'b11 2'b01 | 0 2'b00 | 0 2'b01
//n+1 2'b11 2'b00 | 1 2'b01 | 0 2'b00
PEXIT_WIDTH = (EXIT_WIDTH == 0)? 1 : EXIT_WIDTH // to avoid negative index(modelsim compile error)
)(
input clock,
input resetn,
input [ENTRY_WIDTH-1:0] i_valid,
input [ENTRY_WIDTH-1:0] i_stall,
input [PEXIT_WIDTH-1:0] i_valid_exit,
input [PEXIT_WIDTH-1:0] i_stall_exit,
output [ENTRY_WIDTH-1:0] o_valid,
output [ENTRY_WIDTH-1:0] o_stall
);
localparam ADD_WIDTH = $clog2(ENTRY_WIDTH + 1);
localparam SUB_WIDTH = $clog2(PEXIT_WIDTH + 1);
localparam THRESHOLD_W = $clog2(THRESHOLD + 1);
integer i;
wire [ENTRY_WIDTH-1:0] inc_bin;
wire [ADD_WIDTH-1:0] inc_wire [ENTRY_WIDTH];
wire [PEXIT_WIDTH-1:0] dec_bin;
wire [SUB_WIDTH-1:0] dec_wire [PEXIT_WIDTH];
wire [ADD_WIDTH-1:0] inc_value [ENTRY_WIDTH];
wire decrease_allow;
wire [THRESHOLD_W:0] valid_allow_wire;
reg [THRESHOLD_W-1:0] counter_next, valid_allow;
wire [ENTRY_WIDTH-1:0] limit_mask;
wire [ENTRY_WIDTH-1:0] accept_inc_bin;
assign decrease_allow = inc_value[ENTRY_WIDTH-1] > dec_wire[PEXIT_WIDTH-1];
assign valid_allow_wire = valid_allow + dec_wire[PEXIT_WIDTH-1] - inc_value[ENTRY_WIDTH-1];
always @(*) begin
if(decrease_allow) counter_next = valid_allow_wire[THRESHOLD_W]? 0 : valid_allow_wire[THRESHOLD_W-1:0];
else counter_next = (valid_allow_wire > THRESHOLD)? THRESHOLD : valid_allow_wire[THRESHOLD_W-1:0];
end
//valid_allow_temp is used only when THRESHOLD_NO_DELAY = 1
wire [THRESHOLD_W:0] valid_allow_temp;
assign valid_allow_temp = valid_allow + dec_wire[PEXIT_WIDTH-1];
genvar z;
generate
for(z=0; z<ENTRY_WIDTH; z=z+1) begin : GEN_COMB_ENTRY
assign inc_bin[z] = ~i_stall[z] & i_valid[z];
assign inc_wire[z] = (z==0)? i_valid[0] : inc_wire[z-1] + i_valid[z];
// set mask bit n to 1 if the sum of (~i_stall[z] & i_valid[z], z=0, 1, ..., n) is smaller or equal to the number of output valid bits allowed.
assign limit_mask[z] = inc_wire[z] <= (THRESHOLD_NO_DELAY? valid_allow_temp : valid_allow);
assign accept_inc_bin[z] = inc_bin[z] & limit_mask[z];
assign inc_value[z] = (z==0)? accept_inc_bin[0] : inc_value[z-1] + accept_inc_bin[z];
assign o_valid[z] = limit_mask[z] & i_valid[z];
assign o_stall[z] = (ENTRY_WIDTH == 1)? (valid_allow == 0 | i_stall[z]) : (!o_valid[z] | i_stall[z]);
end
for(z=0; z<PEXIT_WIDTH; z=z+1) begin : GEN_COMB_EXIT
assign dec_bin[z] = !i_stall_exit[z] & i_valid_exit[z];
assign dec_wire[z] = (z==0)? dec_bin[0] : dec_wire[z-1] + dec_bin[z];
end
endgenerate
// Synchrounous
always @(posedge clock or negedge resetn) begin
if(!resetn) begin
valid_allow <= THRESHOLD;
end
else begin
// update the internal counter
valid_allow <= counter_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_TB_V
`define SKY130_FD_SC_HD__NOR4B_TB_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_TB_V
|
#include <bits/stdc++.h> using namespace std; int getMin(int l, int r, char a[], char ch) { int count = 0; for (int i = l; i <= r; i++) { if (a[i] != ch) { count++; } } return count; } int findans(int l, int r, char a[], char ch) { if (l == r) { if (a[l] == ch) { return 0; } else { return 1; } } int mid = (l + r) / 2; return min(getMin(l, mid, a, ch) + findans(mid + 1, r, a, ch + 1), getMin(mid + 1, r, a, ch) + findans(l, mid, a, ch + 1)); } int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; char a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int ans = findans(0, n - 1, a, a ); cout << ans << endl; } } |
////////////////////////////////////////////////
// Copyright (c) 2012, Andrew "bunnie" Huang
// (bunnie _aht_ bunniestudios "dote" com)
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////
/// according to Xilinx WP272, all flip flops are reset to a "known value"
/// by GSR. You're supposed to trust that. Of course, this "known value"
/// isn't very explicitly stated, searching through the xilinx manuals
/// it seems everything defaults to 0 except for stuff that's presetable.
/// anyways, this module generates a local, synchronized reset based upon
/// a global reset. The idea is to instantiate one of these near every
/// terminal reset sink, so as to avoid loading down a global reset network.
/// this should optimize utilization and speed a bit, and also allow the
/// synthesizer to get more aggressive about using larger primitives
//////////
// the input is the asychronous reset of interest
// and the clock to synchronize it to
// the output is a synchronized reset that is at least four clock cycles wide
module sync_reset (
input wire glbl_reset, // async reset
input wire clk,
output wire reset
);
wire [3:0] reschain;
FDPE fdres0( .Q(reschain[0]), .C(clk), .CE(1'b1), .D(1'b0), .PRE(glbl_reset) );
FDPE fdres1( .Q(reschain[1]), .C(clk), .CE(1'b1), .D(reschain[0]), .PRE(glbl_reset) );
FDPE fdres2( .Q(reschain[2]), .C(clk), .CE(1'b1), .D(reschain[1]), .PRE(glbl_reset) );
FDPE fdres3( .Q(reschain[3]), .C(clk), .CE(1'b1), .D(reschain[2]), .PRE(glbl_reset) );
assign reset = reschain[3];
endmodule // sync_reset
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e7; int n; int m[100], r[100]; bool am[MAX]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> m[i]; for (int i = 1; i <= n; i++) cin >> r[i]; for (int i = 1; i <= n; i++) { bool da = 0; for (int k = 0; k * m[i] + r[i] < MAX; k++) am[k * m[i] + r[i]] = 1; } int cnt = 0; for (int i = 1; i < MAX; i++) cnt += am[i]; cout << 1.00 * cnt / (MAX - 1); return 0; } |
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire no, po;
reg d, c;
nmos n (no, d, c);
pmos p (po, d, c);
initial begin
c = 0;
d = 0;
#1 if (no !== 1'bz) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'b0) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
d = 1;
#1 if (no !== 1'bz) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'b1) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
c = 1;
#1 if (no !== 1'b1) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'bz) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
d = 0;
#1 if (no !== 1'b0) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'bz) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int N = 500010; int k, n, maxb, t, b[N], tot = 1, dp[N << 2], rec[N << 2]; void update(int i, int x) { while (i <= tot) { dp[i] = max(dp[i], x); i += i & -i; } } int sum(int i) { int ret = 0; while (i) { ret = max(ret, dp[i]); i -= i & -i; } return ret; } int main() { scanf( %d%d%d%d , &k, &n, &maxb, &t); t = min(t, maxb); while (tot <= maxb) tot <<= 1; while (k--) { memset(dp, 0, sizeof(dp)); memset(rec, 0, sizeof(rec)); memset(b, 0, sizeof(b)); for (int i = 0; i < n; i++) scanf( %d , &b[i]); for (int i = 1; i <= t; i++) for (int j = 0; j < n; j++) { int tmp = sum(b[j] - 1); if (tmp >= rec[j]) { update(b[j], tmp + 1); rec[j] = tmp + 1; } } printf( %d n , sum(tot)); } return 0; } |
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
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